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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 16. Отображено 12.
10-01-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130010564A1
Автор: SHIBAZAKI Yuzuru
Принадлежит:

According to the embodiments, a semiconductor memory device includes serially-connected cell transistors includes respective gate electrodes coupled to respective word lines, a first driver and a second driver which drive the word lines, and a connection module. The connection module electrically couples the first driver commonly to a first subset of the word lines, and electrically couples the second driver commonly to a second subset of the word lines different from the first subset of the word lines. The first and second subsets of the word lines include the same number of word lines. 1. A semiconductor memory device comprising:cell transistors comprising respective gate electrodes coupled to respective word lines;a first driver and a second driver which drive the word lines; anda connection module which electrically couples the first driver commonly to a first subset of the word lines, and electrically couples the second driver commonly to a second subset of the word lines different from the first subset of the word lines, the first and second subsets of the word lines including the same number of word lines.2. The device of claim 1 , whereinthe first subset of the word lines are apart from a selected word line by one or more of the word lines and include adjacent ones of the word lines,the second subset of the word lines are apart from the selected word line by one or more of the word lines and include adjacent ones of the word lines.3. The device of further comprising third drivers which drive word lines electrically coupled to the third drivers claim 2 , whereinthe connection module electrically couples the third drivers to a third subset of the word lines respectively, and the third subset of the word lines is different from the first and second subsets of the word lines and include the selected word line.4. The device of claim 3 , whereinthe connection module includes connection circuits for respective word lines,each of some of the connection circuits ...

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Номер записи: 1
29-01-2015 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

Номер: US20150029793A1
Автор: SHIBAZAKI Yuzuru, Ueno Koki, Yamamoto Mayumi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A nonvolatile semiconductor memory device including: a memory cell array including NAND strings; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to execute a write operation. The control circuit is configured to, when charging an unselected memory string prior to the write operation, execute both first and second charging operations, the first charging operation applying to the bit line connected to the unselected memory string a first voltage and rendering conductive a first select transistor to charge the unselected memory string, and the second charging operation applying to the source line connected to the unselected memory string a second voltage and rendering conductive a second select transistor to charge the unselected memory string, the first and second charging operations being executed at different timings. 1. A nonvolatile semiconductor memory device , comprising:a memory cell array configured having NAND strings arranged therein, each of the NAND strings including: a memory string configured having a plurality of memory cells connected in series therein; and a first select transistor and a second select transistor respectively connected to two ends of the memory string;a plurality of word lines respectively connected to control gate electrodes of the plurality of memory cells;a plurality of bit lines each connected to a first end of the memory string included in the NAND strings via the first select transistor;a source line connected to a second end of the memory string via the second select transistor; anda control circuit configured to execute a write operation for data write, the write operation applying a selected memory cell in a selected memory string with a certain write voltage from a selected word line,the control circuit being configured capable of,when charging an unselected memory string prior to the write operation, executing both of a first charging operation and a second charging ...

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Номер записи: 2
09-06-2022 дата публикации

Semiconductor memory device

Номер: US20220180945A1
Автор: Yuzuru SHIBAZAKI
Принадлежит: Kioxia Corp

A semiconductor memory device comprises: a first memory cell array comprising a plurality of first memory blocks; a second memory cell array comprising a plurality of second memory blocks; and a voltage supply line electrically connected to the plurality of first memory blocks and the plurality of second memory blocks. Moreover, this semiconductor memory device is capable of executing a write operation. At a first timing of this write operation, the voltage supply line is not electrically continuous with the first and second memory blocks. Moreover, a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first and second memory blocks is larger than a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first memory block.

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Номер записи: 3
27-05-2021 дата публикации

Memory device which generates operation voltages in parallel with reception of an address

Номер: US20210158879A1
Автор: Akio SUGAHARA, BUSHNAQ Sanad, Junichi Sato, Kazuto Uehara, Masashi Yamaoka, Norichika ASAOKA, Noriyasu Kumazaki, Ryosuke Isomura, Takaya HANDA, Yuri Terada, Yuzuru SHIBAZAKI
Принадлежит: Toshiba Memory Corp

A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

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Номер записи: 4
22-09-2022 дата публикации

Semiconductor storage device

Номер: US20220301630A1
Автор: Hideyuki Kataoka, Hiroki Date, Junichi Sato, Takeshi Nakano, Yuzuru SHIBAZAKI
Принадлежит: Kioxia Corp

A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes.

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Номер записи: 5
18-06-2020 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20200194077A1
Автор: Kumazaki Noriyasu, SANAD Bushnaq, SHIBAZAKI Yuzuru
Принадлежит: Toshiba Memory Corporation

According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation. 1. A semiconductor memory device comprising:a memory cell array including a first memory cell;a first word line coupled to a gate of the first memory cell;a first circuit coupled to the first word line;a first driver used for a write operation and a read operation;a second driver used for an erase operation; anda voltage generator respectively coupled to the first and second drivers, a second circuit capable of electrically coupling the first word line and a first interconnect in the write operation, the read operation, and the erase operation in which the first word line is selected;', 'a third circuit capable of electrically coupling the first interconnect and a second interconnect in the write operation, the read operation, and the erase operation;', 'a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write operation and the read operation; and', 'a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation., 'wherein the first circuit includes2. The device according to claim 1 , further comprising:a second word line coupled to the first circuit; anda third driver used for the ...

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Номер записи: 6
25-06-2020 дата публикации

Memory device

Номер: US20200202958A1
Автор: Akio SUGAHARA, BUSHNAQ Sanad, Junichi Sato, Kazuto Uehara, Masashi Yamaoka, Norichika ASAOKA, Noriyasu Kumazaki, Ryosuke Isomura, Takaya HANDA, Yuri Terada, Yuzuru SHIBAZAKI
Принадлежит: Toshiba Memory Corp

According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

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Номер записи: 7
10-09-2015 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DETECTING LEAK CURRENT

Номер: US20150255162A1
Автор: KAMATA Yoshihiko, NAKAMURA Dai, SHIBAZAKI Yuzuru
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a semiconductor memory device includes a leak current detection circuit that includes: a detection input end connected to a word line; a first detection end; a coupling circuit connected between the detection input end and the first detection end; a first switching circuit that supplies a voltage to be a reference to the first detection end according to a control signal; and an output circuit that outputs a detection signal corresponding to a change in a voltage of the first detection end caused by the detection input end and the first detection end being coupled by the coupling circuit. 1. A semiconductor memory device comprising a leak current detection circuit that includes:a detection input end connected to a word line;a first detection end;a coupling circuit connected between the detection input end and the first detection end, the coupling circuit electrically couples the detection input end and the first detection end according to a first control signal;a first switching circuit having an output end connected to the first detection end, the first switching circuit supplies a voltage to be a reference to the first detection end according to a second control signal; andan output circuit that outputs a detection signal corresponding to a change in a voltage of the first detection end caused by the detection input end and the first detection end being coupled by the coupling circuit responding to the first control signal.2. The semiconductor memory device according to claim 1 , wherein the output circuit outputs a detection signal notifying a presence of a leak current in the word line when the change in the voltage of the first detection end caused by the detection input end and the first detection end being electrically coupled by the coupling circuit exceeds a predetermined threshold.3. The semiconductor memory device according to claim 2 , wherein the coupling circuit includes a MOS transistor claim 2 , and a capacitor that is ...

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Номер записи: 8
15-07-2014 дата публикации

Semiconductor memory device

Номер: US8780667B2
Автор: Yuzuru SHIBAZAKI
Принадлежит: Toshiba Corp

According to the embodiments, a semiconductor memory device includes serially-connected cell transistors includes respective gate electrodes coupled to respective word lines, a first driver and a second driver which drive the word lines, and a connection module. The connection module electrically couples the first driver commonly to a first subset of the word lines, and electrically couples the second driver commonly to a second subset of the word lines different from the first subset of the word lines. The first and second subsets of the word lines include the same number of word lines.

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Номер записи: 9
09-01-2024 дата публикации

Semiconductor storage device including a voltage generator for applying first and second intermediate voltages to an adjacent word line in a program operation

Номер: US11869597B2
Автор: Hideyuki Kataoka, Hiroki Date, Junichi Sato, Takeshi Nakano, Yuzuru SHIBAZAKI
Принадлежит: Kioxia Corp

A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes.

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Номер записи: 10
28-04-2022 дата публикации

Memory device which generates operation voltages in parallel with reception of an address

Номер: US20220130469A1
Автор: Akio SUGAHARA, BUSHNAQ Sanad, Junichi Sato, Kazuto Uehara, Masashi Yamaoka, Norichika ASAOKA, Noriyasu Kumazaki, Ryosuke Isomura, Takaya HANDA, Yuri Terada, Yuzuru SHIBAZAKI
Принадлежит: Toshiba Memory Corp

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

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Номер записи: 11
05-10-2023 дата публикации

Memory device which generates operation voltages in parallel with reception of an address

Номер: US20230317177A1
Автор: Akio SUGAHARA, BUSHNAQ Sanad, Junichi Sato, Kazuto Uehara, Masashi Yamaoka, Norichika ASAOKA, Noriyasu Kumazaki, Ryosuke Isomura, Takaya HANDA, Yuri Terada, Yuzuru SHIBAZAKI
Принадлежит: Kioxia Corp

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

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Номер записи: 12