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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 5. Отображено 4.
09-01-2014 дата публикации

Scalable prediction failure analysis for memory used in modern computers

Номер: US20140013170A1
Принадлежит: International Business Machines Corp

One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.

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03-12-2015 дата публикации

SCALABLE PREDICTION FAILURE ANALYSIS FOR MEMORY USED IN MODERN COMPUTERS

Номер: US20150347211A1
Принадлежит:

One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system. 1. A method for scalable predictive failure analysis , the method comprising:a processor gathering values for one or more characteristics of a memory of a computer system;the processor selecting one or more memory-related parameters, each of the one or more memory-related parameters representing a different characteristic of the one or more characteristics of the memory, wherein the one or more memory-related parameters include a memory rank parameter;the processor calculating, a scalable single bit error threshold value using the values for each of the one or more characteristics of the memory represented by the selected one or more memory-related parameters; andthe processor setting the calculated scalable single bit error threshold value for the memory.2. The method of claim 1 , further comprising the processor re-calculating the scalable single bit error threshold value for the memory subsequent to performance of a reparative procedure.3. The method of claim 1 , further comprising causing display of a notice in response to a determination that the calculated scalable single bit error threshold value has been met or exceeded.4. The method of claim 1 , wherein the one or more memory-related parameters include a memory size parameter indicative of a capacity of the memory.5. The method of claim ...

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27-09-1994 дата публикации

Processor-based smart packet memory interface

Номер: CA2110134A1
Принадлежит: International Business Machines Corp

PROCESSOR-BASED SMART PACKET MEMORY INTERFACE ABSTRACT A processor-based packet memory interface for controlling the transfer of data between multiple communications channels and packet memory in a communications adapter is presented, where the communications adapter uses requestor IDs to identify transmit and receive processes. The processor-based packet memory interface is controlled by a microprocessor configured to perform read and write operations with the communications adapter. The microprocessor is further configured to reserve a plurality of blocks of memory in the packet memory so that the number of communications channels that can be supported is not limited to the number of requestor ID's that can be handled by the communications adapter. The processor-based packet memory interface also includes RAM, for use by the microprocessor, to store pointers to reserved blocks of memory in the packet memory and to temporarily store packet data for transfer between the communications channels and the communications adapter.

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24-11-2015 дата публикации

Scalable prediction failure analysis for memory used in modern computers

Номер: US9196383B2
Принадлежит: International Business Machines Corp

One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.

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