Link power savings with state retention

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Enhanced conductivity body biased PMOS driver

According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.

Phase/frequency detector for tracking receivers

A receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase. If certain meta-stable conditions are observed by the voter block, the voter block will vote in one direction in order to push the system out of the meta-stable condition.

Apparatus for interconnecting multiple devices on a circuit board

A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.

Redundant acknowledgment in loopback entry

Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example the acknowledgment is performed by initiating loopback communications from a first agent to a second agent, sending a packet including a redundant acknowledgment sequence from the first agent to the second agent, receiving the packet including the redundant acknowledgement sequence looped back from the second agent at the first agent, sending a test sequence from the first agent to the second agent, and receiving the test sequence looped back from the first agent.

Socket plane

A method and apparatus for a conductive plate for a socket. The conductive plate includes a plurality of openings. The conductive plate is electrically connected to ground and is contained within a socket that may receive an electronic package. The openings allow pins from the electronic package to pass through to contacts in the socket. The diameter of each opening is customizable to produce desired impedance between the electronic package pin inserted in the contact and the conductive plate. Impedance discontinuity seen by signals passing through the socket from the electronic package pins is reduced. The electronic plate may contain one or more pins insertable into contacts in the socket where the contacts provide the electrical connection to ground.

Increasing robustness of source synchronous links by avoiding write pointers based on strobes

A source synchronous scheme in which data from one clock domain is synchronized to a clock of a second clock domain. Using a more reliable clock of the second domain to control and adjust the alignment after the data is latched in allows more robust performance to maintain correctly ordered data. In this manner, a write pointer based on strobe signal(s) from the first clock domain may be avoided.

Decoupling Device Using Stored Charge Reverse Recovery

Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.

Link power saving state

Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Setting multiple chip parameters using one IC terminal

A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.

Low cost and high speed 3-load printed wiring board bus topology

A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units ...

Technique to create link determinism

A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Apparatuses, systems and methods for detecting errors in data streams on point-to-point serial links

Methods, apparatuses and systems for physical link error data capture and analysis. A receiver is coupled to receive a data stream via a point-to-point serial link. A control circuit is coupled with the receiver to cause the receiver to selectively sample the data stream according to an offset parameter and an interval parameter. Comparison circuitry compares the data stream sample to expected data values to determine a bit error rate.

Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection

A method for effecting an in-band reset of the physical layers of two agents interconnected through a link-based interconnection scheme. In accordance with one embodiment of the invention, a first of the two agents ceases its forwarded clock to initiate the in-band reset. Upon realization of the cessation, a second agent ceases its forwarded clock and proceeds to a reset state. The first agent then proceeds to a reset state. Subsequently, after waiting a specified period of time, both agents proceed with a re-initialization of the physical layer. In accordance with one embodiment of the invention, the re-initialization of the physical layer is effected without impacting other layers of the interconnection hierarchy.

Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances

A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

Circuit board-to-circuit board connectors having electro-optic modulators

An electrical connector to be electrically disposed between a first circuit board and a second circuit board to electrically couple the first circuit board with the second circuit board is disclosed. The electrical connector may have an electro-optic modulator to modulate optical signals based on electrical signals exchanged between the first and second circuit boards through the electrical connector. Systems incorporating such electrical connectors, and methods of using the electrical connectors and systems, such as for debug, are also disclosed.

3D System and Wafer Reconstitution with Mid-layer Interposer

A system in package structure and method of fabrication using wafer reconstitution are described. In an embodiment a 3D system includes a mid-layer interposer a first package level underneath the mid-layer interposer and a second package level over the mid-layer interposer. Second package level components can be bonded to the mid-layer interposer with metal-metal bonds and optionally dielectric-dielectric bonds, while the first package level components can be bonded to the mid-layer interposer with dielectric-dielectric and optionally metal-metal bonds. Dies within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

Methods and apparatuses for resetting the physical layers of two agents interconnected through a link-based interconnection

A method for effecting an in-band reset of the physical layers of two agents interconnected through a link-based interconnection scheme. In accordance with one embodiment of the invention, a first of the two agents ceases its forwarded clock to initiate the in-band reset. Upon realization of the cessation, a second agent ceases its forwarded clock and proceeds to a reset state. The first agent then proceeds to a reset state. Subsequently, after waiting a specified period of time, both agents proceed with a re-initialization of the physical layer. In accordance with one embodiment of the invention, the re-initialization of the physical layer is effected without impacting other layers of the interconnection hierarchy.

Method of fabricating a linearized output driver and terminator

A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

SYSTEMS AND METHODS FOR INTERCONNECTING DIES

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

Seal ring designs supporting efficient die to die routing

Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.

Testing microelectronic devices using electro-optic modulator probes

Testing microelectronic devices using electro-optic modulator probes is disclosed. In one aspect, a testing apparatus may include an electrical signaling medium to exchange electrical signals with a microelectronic device. The testing apparatus may include an electro-optic modulator probe to provide optical signals that are modulated by the electrical signals. An optoelectronic transducer may be included to convert the modulated optical signals to modulated electrical signals. The testing apparatus may further include a logic analyzer module to receive and analyze the modulated electrical signals. Other testing apparatus are disclosed, as well as systems incorporating such apparatus, and various methods of testing microelectronic devices.

Providing error correction coding for probed data

In one embodiment, the present invention includes a method for receiving an error correction code for information from a first port of a first agent and receiving the information from a second port of the first agent by probing a first link under test that couples the first agent and a second agent. The code may be used to validate the information, e.g., in a probe receiver during test or debug operations. Other embodiments are described and claimed.

Method and system for improved phase tracking

A method and system for improved phase tracking in communication systems is disclosed. In one embodiment, a method, comprises identifying a slow-time varying phase drift on a link by counting long term beats; calibrating an interpolator with the phase drift; predicting a future phase drift; and updating the interpolator periodically with the future phase drift prediction.

Circuit Board Including Stubless Signal Paths and Method of Making Same

A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Testing for digital signaling

In an electronic system having logic agents that communicate with each other through one or more signal lines, a method for testing high speed digital signaling on the signal lines is disclosed. The method involves sensing a first crosstalk signal induced by a first digital signal. The first digital signal is driven by a first logic agent into a signal line to communicate with a second agent. The second agent is coupled to receive the first digital signal from the signal line. A logic waveform that represents the digital signal is recorded and/or displayed, based upon the crosstalk signal. The technique may also be used for testing simultaneous bidirectional signaling on the same signal line.

High density 3D interconnect configuration

Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

WAFER RECONSTITUTION AND DIE-STITCHING

Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Charge sharing and charge recycling for an on-chip bus

A method for charge sharing among data conductors of a bus. The bus has a first data conductor and a corresponding data conductor. The method includes detecting the logic levels on the first data conductor and the corresponding data conductor, and generating a charge sharing signal for sharing charge between the first data conductor and the corresponding data conductor.

SYSTEMS AND METHODS FOR INTERCONNECTING DIES

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die. 1. A die structure comprising:a semiconductor substrate;a first front-end-of-the-line (FEOL) die area of a first die patterned into the semiconductor substrate;a dicing area adjacent the first FEOL die area; and a plurality of metal layers including lower metal layers and upper metal layers spanning over the first FEOL die area;', 'a metallic seal structure including an inside section and an outside section, the inside section nearer the first FEOL die area than the outside section is, and the outside section nearer the dicing area than the inside section is;', 'a die-to-die routing that navigates from the first FEOL area, through the metallic seal structure, and to the dicing area, wherein the die-to-die routing comprises a vertical interconnect between the inside section and the outside section., 'a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the dicing area, the BEOL build-up structure including2. The die structure of claim 1 , wherein the die-to-die routing includes a lower routing line within a lower metal layer and an upper routing line within an upper metal layer claim 1 , and the vertical interconnect connected to the lower routing line and the upper routing line.3. The die structure of claim 2 , wherein ...

Flexible cable for high-speed interconnect

A system and method are disclosed in which flex cables are affixed to PCBs, for providing high-speed signaling paths between ICs disposed upon the PCBs. The flex cables are fixably attached to the PCBs so as to substantially mimic their structural orientation. Where the configuration includes more than one PCB, the flex cables include multiple portions which are temporarily separable from one another and from the die, using flex-to-flex and flex-to-package connectors, allowing field maintenance of the configuration. By routing the high-speed signals between ICs onto the flex cable, single-layer PCBs can be used for non-critical and power delivery signals, at substantial cost savings. By disposing the flex cables onto the PCB rather than allowing the cables to float freely, the configuration is thermally managed as if the signals were on the PCB and cable routing problems are avoided.

Link power savings with state retention

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Dynamically modulating link width

Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.

Power management system switched capacitor voltage regulator with integrated passive device

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Method and apparatus for interconnecting multiple devices on a circuit board

A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.

Fast bi-directional tristateable line driver

A driver to drive a bus with a pullup and a pulldown transistor according to a data signal during a drive phase and to charge or discharge the bus to intermediate voltage levels during a precondition phase using the pullup and pulldown transistors, the driver comprising a buffer and latch to latch the bus voltage at the end of a drive phase; a precondition circuit responsive to the latch to switch ON a pullup transistor at the beginning of a precondition phase when the bus voltage was LOW in the previous drive phase so as to charge the bus voltage to a first voltage less than a supply voltage, and to switch ON a pulldown transistor at the beginning of the precondition phase when the bus voltage was HIGH in the previous drive phase so as to discharge the bus voltage to a second voltage above ground.

Redundant acknowledgment in loopback entry

Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.

Power management system switched capacitor voltage regulator with integrated passive device

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Serial link apparatus, method, and system

A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.

Seal Ring Designs Supporting Efficient Die to Die Routing

Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure. 1. A chip structure comprising:a semiconductor substrate;a first front-end-of-the-line (FEOL) die area of a first die patterned into the semiconductor substrate; and a plurality of metallization layers including lower metallization layers and upper metallization layers spanning over the first FEOL die area;', 'a split metallic seal structure including an inner metallic seal and an outer metallic seal arranged with one of the inner metallic seal and the outer metallic seal being a lower metallic seal overlapping the lower metallization layers and another of the inner metallic seal and the outer metallic seal being an upper metallic seal overlapping the upper metallization layers;', 'wherein portions of the inner metallic seal and the outer metallic seal are both formed in a same metallization layer of the plurality of metallization layers; and', 'a through seal interconnect extending from the first FEOL die area and into a scribe region laterally outside of the outer metallic seal; and', 'wherein the split metallic seal structure is coupled to a charge source to control potential of at least one of the inner metallic seal and the outer metallic seal., 'a back-end-of-the-line (BEOL) build-up structure including2. The chip of wherein each of the inner metallic seal and the outer metallic seal include a plurality of metal filled trenches and metal wiring layers.3. The chip of claim 1 , wherein the charge source comprises a charge source routing connected with the outer metallic seal.4. The chip of claim 3 , wherein the charge source routing comprises a metal plane spanning across the outer metallic seal.5. The chip of claim 4 , wherein the ...

Setting multiple chip parameters using one IC terminal

A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.

Flexible System Integration to Improve Thermal Properties

In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation. 1. An apparatus comprising:an interposer;a plurality of integrated circuits attached to a surface of the interposer, wherein:a subset of the plurality of integrated circuits are processors;the processors are distributed over the surface of the interposer; andother ones of the plurality of integrated circuits that are not processors are arranged between the processors, distributing a power consumption density of the plurality of integrated circuits over the surface; anda phase change material in contact with the plurality of integrated circuits.2. The apparatus as recited in wherein at least one of the processors has a different leakage current than another one of the processors.3. The apparatus as recited in claim 2 , wherein high performance tasks are executed on the high performance processors having higher leakage currents during use and low performance tasks are executed on the low performance processors that are power efficient for low performance tasks claim 2 , compared to the high ...

High bandwidth routing for die to die interposer and on-chip applications

Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

Thermally Enhanced Chip-on-Wafer or Wafer-on-Wafer Bonding

Semiconductor packages including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.

LINK POWER SAVINGS WITH STATE RETENTION

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed. 1. An apparatus comprising:a first agent coupled to a second agent via a serial link;the first agent to transmit an entry message to the second agent to indicate the first agent is to enter a low power consumption state;the first agent to enter the low power consumption state in response to an acknowledgement message from the second agent, wherein the second agent is to transmit the acknowledgement message in response to receipt of the entry message at the second agent,wherein, during the low power consumption state, the first agent is to retain its link state.2. The apparatus of claim 1 , wherein the first agent is to transmit an inband reset signal to the second agent in response to the acknowledgement message.3. The apparatus of claim 1 , wherein claim 1 , during the low power consumption state claim 1 , an electrical sub-block of the first agent is to be turned off and a logical sub-block of the first agent is to be functionally turned off4. The apparatus of claim 1 , wherein the second agent is to enter the low power consumption state in response to an inband reset signal from the first agent.5. The apparatus of claim 4 , wherein claim 4 , during the low power consumption state claim 4 , the second agent is to retain its link state.6. The apparatus of claim 4 , wherein the first agent or the second agent is to be configured to bypass calibration prior to entering the low power consumption state.7. The apparatus of claim 4 , wherein the second agent is to exit the low power consumption state in response to a signal from the first agent or from the second agent.8. The apparatus of claim 1 , wherein the first agent is to transmit the entry message in response to an indication by a ...

Enhanced conductivity body biased PMOS driver

According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.

I/O link with configurable forwarded and derived clocks

An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.

HIGH DENSITY 3D INTERCONNECT CONFIGURATION

Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible. 1. An electronic package comprising:a redistribution layer (RDL); anda die coupled to the RDL;wherein the RDL includes a 3D interconnect structure for power and signal delivery to the die.2. The electronic package of claim 1 , wherein 3D interconnect structure comprises:a power bar underneath a plurality of contact pads, the power bar configured to supply a positive power supply to the die, wherein the die is bonded to the plurality of contact pads.3. The electronic package of claim 2 , wherein the power bar is directly underneath and in electrical contact with the plurality of contact pads.4. The electronic package of claim 3 , wherein the power bar is part of a power mesh plane.5. The electronic package of claim 3 , further comprising a second power bar underneath a second plurality of contact pads claim 3 , the second power bar to supply a negative power supply to the die claim 3 , wherein the die is bonded to the second plurality of contact pads.6. The electronic package of claim 5 , wherein the second power bar is directly underneath and in electrical contact with the second plurality of contact pads.7. The electronic package of claim 1 , further comprising a chiplet claim 1 , wherein the chiplet is at least partially directly underneath the die.8. The electronic package of claim 7 , wherein the chiplet is on a second side of the RDL opposite the die.9. The electronic package of claim 8 , wherein the die includes a low performance logic and a high performance logic claim 8 , and the chiplet is substantially directly underneath the low performance logic claim 8 , and the 3D interconnect structure includes a substantially vertical ...

Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link

A technique is described by which two link agents with ports coupled together using a point-to-point interconnect in a system exchange their link width support capabilities and negotiate a link width that is mutually agreeable. The interconnect between each pair of agents comprises a pair of uni-directional links having multiple electrical wires, or lanes, where one link is used by a first agent to transmit data to a second agent and another link is used by the second agent to transmit data to the first agent.

Serial link apparatus, method, and system

A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.

Method and apparatus for interactively training links in a lockstep fashion

A method and apparatus for advancing initialization messages in a lock-step manner when initializing an interface is presented. In one embodiment, a lane receiver may transition to a receiver ready attribute when a given number of current training sequence messages is correctly received. When the receiver ready attributes of all the lanes are set, a local acknowledgement attribute may be set. Similarly, a lane receiver may transition to a remote acknowledgement attribute when a given number of current training sequence messages with acknowledgement field set is correctly received. When both the local acknowledgement attribute and the remote acknowledgement attribute are set, the port may advance to the next training sequence messages.

Cache based physical layer self test

A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

Orienting multiple processors on two sides of a printed circuit board

A topology for mounting processors on opposite sides of a printed circuit board (PCB) orients rows of processor connection pins parallel to the bus orientation within the PCB and defines a relative 180 degree orientation between the opposing processors.

Compact System with Memory and PMU Integration

One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits. 1. An integrated circuit implemented in a dynamic random access memory (DRAM) fabrication process , wherein the integrated circuit comprises:a plurality of components, each of the plurality of components implementing one or more features of the integrated circuit;at least one memory implemented as a DRAM, the memory coupled to one or more of the plurality of components; anda plurality of power management units configured to generate power supply voltages for the plurality of components, each of the plurality of power management units including a voltage regulator configured to generate a power supply voltage at a desired voltage magnitude for a corresponding one or more components of the plurality of components, the voltage regulator including one or more capacitors, wherein the capacitors are formed in a same fashion as the capacitors used for the DRAM.2. The integrated circuit as recited in wherein the DRAM is embedded DRAM (eDRAM) claim 1 , and wherein the DRAM fabrication process is an eDRAM fabrication process.3. The integrated circuit as recited in wherein the capacitors are constructed in metal layers above a semiconductor substrate of the integrated circuit.4. The integrated circuit as recited in wherein the memory is a cache.5. The integrated circuit as recited in wherein the voltage regulator is a switched capacitor voltage regulator.6. The integrated circuit as recited in wherein the voltage regulator is a buck voltage regulator claim 1 , and wherein the buck voltage regulator comprises one ...

CIRCUIT BOARD INCLUDING STUBLESS SIGNAL PATHS AND METHOD OF MAKING SAME

A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

EDRAM/DRAM fabricated capacitors for use in on-chip PMUS and as decoupling capacitors in an integrated EDRAM/DRAM and PMU system

One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. The capacitors may be physically placed near the logic components for which the capacitors are providing decoupling capacitance, in an embodiment. The capacitors may be series connections of at least two capacitors, or at least one capacitor and a switch, to provide decoupling capacitance in the face of defects, in an embodiment. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.

Power management system switched capacitor voltage regulator with integrated passive device

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM

Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip. 1. A multi-chip system comprising:a first chip;an interfacing bar coupled with the first chip; anda second chip coupled with the interfacing bar.2. The multi-chip system of claim 1 , the interfacing bar comprises a routing layer extending a substantial portion of a longitudinal length of the interfacing bar.3. The multi-chip system of claim 2 , wherein:the routing layer of the interfacing bar comprises a plurality of metal layers including a lower wiring layer and an upper wiring layer characterized by wider wiring than the lower wiring layer; andthe second chip is electrically coupled with the first chip through a first wire running a substantial distance of the longitudinal length in upper wiring layer, and further comprising a third chip electrically coupled with the first chip through a second wire in the lower wiring layer, wherein the first wire is wider than the second wire and the second chip is located further away from the first chip than the third chip is.4. The multi-chip system of claim 2 , wherein the interfacing bar comprises a discrete head component and one or more discrete active components claim 2 , wherein the discrete head component and the one or more discrete active components are electrically coupled with the routing layer.5. The multi-chip system of claim 4 , wherein the discrete head component and the one or more discrete active components are in an insulating layer.6. The multi-chip system of claim 2 , further comprising a second interfacing bar claim 2 , a plurality of additional chips coupled with the second interfacing bar claim 2 , and a bridge that couples the interfacing bar to the second interfacing bar.7. The multi-chip system of claim 2 , ...

REDUNDANT ACKNOWLEDGMENT IN LOOPBACK ENTRY

Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.

Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment

In one embodiment, the invention is a method of forming a bus. A first conductor having a first impedance is provided, the first conductor is routed through a fifth chip. Coupling of the first conductor to a first chip with a first termination impedance occurs. Coupling of the first conductor to a second chip with a second termination impedance occurs. Coupling of the first conductor to a third chip with a third termination impedance occurs, and coupling of the first conductor to a fourth chip with a fourth termination impedance occurs.

Fabrication of an ion exchange polish pad

Embodiments of the invention include an ion exchange polish pad for polishing a semiconductor substrate, on which various conductive, semiconductive, and/or insulative layers are formed, for example a conductive copper layer. Embodiments also include the method for the manufacture of an ion exchange polish pad. In certain embodiments an ion exchange polish pad includes a base material and a ion exchange layer including, which further includes an ion exchange material. Cations in the ion exchange material may be exchanged with other cations, such as copper, under the proper process conditions for the planarization of a processed semiconductor substrate.

High Density 3D Interconnect Configuration

Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible. 1. (canceled)2. An electronic system comprising:a circuit board;a die bonded to the circuit board with a plurality of solder bumps; a bulk silicon layer;', 'a plurality of trench capacitors in the bulk silicon layer, and a thorough silicon via through the bulk silicon layer;', 'a build-up layer including positive supply (Vdd) routing and negative supply (Vss) routing; and', 'a backside metal layer, wherein the back side metal layer is bonded to the circuit board with a conductive bump., 'a chiplet directly underneath the die and laterally adjacent the plurality of solder bumps, wherein the chiplet includes3. The electronic system of claim 2 , wherein the build-up layer includes a Vdd mesh plane.4. The electronic system of claim 3 , wherein the build-up layer includes a Vss mesh plane.5. The electronic system of claim 2 , further comprising micro bumps bonded to contacts on a top side of the chiplet.6. The electronic system of claim 2 , wherein the die is a system on chip (SoC) die.7. The electronic system of claim 6 , wherein the chiplet includes a voltage regulator.8. The electronic system of claim 7 , wherein the voltage regulator is a switch capacitor voltage regulator or low-dropout (LDO) voltage regulator.9. The electronic system of claim 6 , wherein the die includes a low performance logic and a high performance logic claim 6 , and the chiplet is substantially directly underneath the low performance logic.10. The electronic system of claim 9 , wherein the high performance logic is characterized by a power density that is at least twice a power density of the low performance logic.11. The electronic system of claim 2 , wherein ...

Enhanced conductivity body biased PMOS driver

According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.

POWER MANAGEMENT SYSTEM SWITCHED CAPACITOR VOLTAGE REGULATOR WITH INTEGRATED PASSIVE DEVICE

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip. 1. A power management system comprising: a power supply conductor; and', 'a ground conductor;, 'a circuit board including a voltage input electrically connected to the power supply conductor;', 'a ground connection electrically connected to the ground conductor;', 'a voltage output connected to the circuit load;', 'a high voltage circuit path running between the voltage input and the voltage output; and', 'a low voltage circuit path running between the ground connection and the voltage output;, 'a chip coupled to the circuit board, the chip including a switched capacitor voltage regulator (SCVR) circuit and a circuit load, the SCVR circuit includinga discrete integrated passive device (IPD) connected to the chip, the discrete IPD including a flying capacitor coupled between the high voltage circuit path and the low voltage circuit path.2. The power management system of claim 1 , further comprising a first plurality of switches along the high voltage circuit path and a second plurality of switches along the low voltage circuit path.3. The power management system of claim 2 , wherein the flying capacitor is coupled to the high voltage circuit bath between switches of the first plurality of switches and coupled to the low voltage circuit path between switches of the second plurality of switches.4. The power management system of claim 2 , wherein the flying capacitor is a trench capacitor.5. The power management system of claim 2 , wherein the discrete IPD includes a decoupling capacitor coupled between ...

METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT

A link latency management for a high-speed point-to-point network (pTp) is described The link latency management facilitates calculating latency of a serial interface by tracking a round trip delay of a header that contains latency information. Therefore, the link latency management facilitates testers, logic analyzers, or test devices to accurately measure link latency for a point-to-point architecture utilizing a serial interface. 1. An apparatus to calculate latency of a serial interface by tracking a delay of a header for a point-to-point architecture comprising:a reference clock;a transmitter from a master agent, coupled to a network fabric of the point to point architecture, to enter a mode of operation with a known latency from the reference clock to a header packet; anda receiver from a slave agent, coupled to a network fabric of the point to point architecture, to align a plurality of incoming lanes from the master agent and to calculate a latency based on a clock.2. The apparatus of claim 1 , wherein the clock for the slave agent to calculate the latency is a system reference clock that is the closest to the slave agent.3. An apparatus to calculate latency of a serial interface by tracking a round trip delay of a header for a point-to-point architecture comprising:a reference clock;a transmitter from a master agent, coupled to a network fabric of the point to point architecture, to enter a loop back mode of operation with a known latency from the reference clock to a header packet;a receiver from a slave agent, coupled to a network fabric of the point to point architecture, to align a plurality of incoming lanes from the master agent and to calculate a latency based on a clock and to insert a latency calculation into a loop back start packet data payload; anda master receiver in the master agent to calculate a latency from a reference clock to a header received from the slave.4. The apparatus of claim 1 , wherein the clock for the slave agent to calculate ...

ERROR MONITORING FOR SERIAL LINKS

Methods, apparatuses and systems for physical link error data capture and analysis.

Methods and apparatuses for the physical layer initialization of a link-based system interconnect

Embodiments of the invention provide a state machine for initializing the physical layer of a point-to-point link-based interconnection. Embodiments of the invention use explicit handshakes between the interconnected agent to advance states and provide a variety of optional features for flexibility and efficiency.

Apparatus and methods for multi-lingual user access

An apparatus and method for the multi-lingual creation and retrieval of a work from a database storing multiple texts and/or translations of works in a variety of formats. A user can create and retrieve multiple translations of a work and may choose to have the multiple texts and/or translations presented in different formats. For example, the user may choose to have a document displayed textually in two separate languages, or in text in one language and in audio in a second language.

3D Package with Chip-on-Reconstituted Wafer or Reconstituted Wafer-on-Reconstituted Wafer Bonding

Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets. A heat spreader may be bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding. The chiplets within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

Method and apparatus for interconnecting multiple devices on a circuit board

A method and apparatus interconnecting multiple devices on a circuit board. One disclosed circuit board has a first attach region on a first surface for coupling a first set of pins from a first device to a set of signal lines. A second attach region on a second surface is for coupling a second set of pins from a second device to the set of signal lines. The second attach region is predominantly non-overlapping with respect to the first attach region.

Technique to create link determinism

A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Method and system for improved phase tracking

A method and system for improved phase tracking in communication systems is disclosed. In one embodiment, a method, comprises identifying a slow-time varying phase drift on a link by counting long term beats; calibrating an interpolator with the phase drift; predicting a future phase drift; and updating the interpolator periodically with the future phase drift prediction.

Cache based physical layer self test

A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output ("I/O") unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

Frequency multiplying delay-locked loop

Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the phase shifted signals having increased frequency relative to the incoming signal. The phase-shifted signals being generated by the delay-locked loop in order to position the clock to an optimal detection point of incoming data signals.

Retraining derived clock receivers

Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated by defining control data and payload data for the retraining flit. Error detection data is determined for the retraining flit based on the control and the payload data. The control data, the payload data and the error detection data have sufficient transitions to meet the minimum transition density.

Wafer reconstitution and die-stitching

Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Method, system, and apparatus for loopback entry and exit

A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback test based on detection of a header within a packet. The slave and master agent to support exit out of the loopback test based on whether the loop count is finite.

Local receive clock signal adjustment

According to some embodiments, a local receive clock signal is adjusted.

Scalable Large System Based on Organic Interconnect

Multi-chip modules and methods of fabrication are described. The MCM may include a plurality of dies in which die-to-die routing can be partitioned within multiple metal routing layers for shorter die-to-die routings, while longer die-to-die routing can be routed primarily in a single metal routing layer. The plurality of dies may also be arranged in a spaced apart relationship to accommodate additional wiring area, while preserving direct routing areas for the longer die-to-die routing.

I/O Link with configurable forwarded and derived clocks

An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.

Systems and methods for forming die sets with die-to-die routing and metallic seals

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

Local receive clock signal adjustment

According to some embodiments an apparatus comprising a vote generator, a vote governor, and a local clock controller is provided. The vote generator generates votes based on a local clock signal and transitions in a stream of received data. The vote governor receives the generated votes and discards at least some of the votes. The local clock controller adjusts the local clock signal based on a generated vote that has not been discarded.

Circuit board including stubless signal paths and method of making same

A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Detection of an in-band reset

Methods and apparatuses for detecting an in-band reset using digital circuitry.

Method and apparatus of lowering I/O bus power consumption

The current method and apparatus provides a novel approach to manage the power consumption of a high speed I/O interface by selectively turning off non-essential portions of the interface. Here only part of the interface is powered off as compared to the whole interface being turned off. From the upper layers (protocol/system) perspective, the interface is always “on”. Thus, this mechanism reduces link power by selectively turning off portions of the link, yet allowing for fast wake up in an interface power management architecture.

Programmable passive equalizer

Embodiments of a programmable passive equalizer are described herein.

Methods and apparatuses to effect a variable-width link

Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

Enhanced conductivity body biased PMOS driver

According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.

Decoupling Device Using Stored Charge Reverse Recovery

Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.

Structure and Method for Sealing a Silicon IC

Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

Programmable passive equalizer

Embodiments of a programmable passive equalizer are described herein.

Compliance of master-slave modes for low-level debug of serial links

Methods and apparatuses for testing transmission and/or receiving circuit functionality.

SYSTEMS AND METHODS FOR IMPLEMENTING A SCALABLE SYSTEM

Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip. 1. (canceled)2. A package on package structure:a lower redistribution layer (RDL);a first molding layer on the lower RDL;an interfacing bar is encapsulated in the first molding layer;a second RDL over the first molding layer;a first chip on top of the second RDL; anda package including a plurality of stacked chips on top of the second RDL.3. The package on package structure of claim 2 , further comprising a plurality of through vias extending through the first molding layer connecting the lower RDL and the second RDL.4. The package on package structure of claim 2 , wherein the first chip is a logic chip claim 2 , and the plurality of stacked chips is a plurality of stacked memory chips.5. The package on package structure of claim 4 , further comprising a second molding compound layer on the second RDL.6. The package on package structure of claim 5 , wherein the chip is encapsulated in the second molding compound layer.7. The package on package structure of claim 6 , further comprising a second plurality of through vias extending through the second molding compound layer and connected to the second RDL.8. The package on package structure of claim 7 , wherein the package is bonded to the second plurality of through vias.9. The package on package structure of claim 4 , wherein the interfacing bar comprises a routing layer extending a substantial portion of a longitudinal length of the interfacing bar.10. The package on package structure of claim 9 , wherein:the routing layer of the interfacing bar comprises a plurality of metal layers including a first wiring layer and a second wiring layer characterized by wider wiring than the first wiring layer.11. The package on package ...

Reference voltage distribution for multiload I/O systems

According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.

Flexible system integration to improve thermal properties

In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation.

Very Fine Pitch and Wiring Density Organic Side by Side Chiplet Integration

Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers. 1. A package comprising:a die set encapsulated in a molding compound layer;a package-level redistribution layer (RDL) spanning across the die set and the molding compound layer and on and in electrical connection with the die set;wherein each die in the die set includes a die-level back end of the line (BEOL) build-up structure including a plurality of contact pads; andwherein the package-level RDL includes a plurality of die-to-die interconnects connecting the plurality of contact pads between each die and embedded within one or more photoimageable organic dielectric layers.2. The package of claim 1 , wherein the plurality of die-to-die interconnects comprise damascene interconnects claim 1 , and the BEOL build-up structure for each die in the die set includes damascene metal wiring layers.3. The package of claim 2 , wherein the damascene interconnects comprise copper damascene interconnects.4. The package of claim 2 , wherein the damascene interconnects include multi-layer damascene interconnects including damascene interconnect lines within multiple metal layers in the package-level RDL.5. The package of claim 2 , wherein the damascene interconnects comprise a corresponding plurality of vias formed directly on the plurality of contact pads for each die in the die set.6. The package of claim 5 , wherein the vias formed directly on the plurality of contact pads for each die in the die set are a same height.7. The package of claim 5 , wherein the damascene interconnects include a first die-to-die interconnect that includes a first damascene via directly on a first contact ...

Link power savings with state retention

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Optical debug mechanism

A method for performing analysis of electrical signals in a system is disclosed. The system includes at least two circuit elements between which an electrical signal is transmitted. The method converts the electrical signal to dual optical signals, one of which is converted back to an electrical signal for receipt by the intended circuit element. The second optical signal may be transmitted a great distance, relative to electrical signals, allowing for remote analysis of the signal. The loss in converting the electrical signal to an optical signal, then back to an electrical signal is low compared to other debug methods. The method may be performed with high-speed signals.

Inline and "Y" input-output bus topology

Various bus trace topologies are provided which allow for shorter stub lengths, reduced motherboard costs, more efficient routing between multiple agents, and bus traces with better matched characteristic impedances.

Optimized ESD Clamp Circuitry

ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event. 1. A apparatus comprising:a first sensor circuit;a second sensor circuit, wherein each of the first and second sensor circuits are configured to detect an electro-static discharge (ESD) event; andfirst and second clamp transistors configured to be activated by the first and second ESD sensor circuits, respectively, responsive to detection of the ESD event;wherein a resistive-capacitive (RC) time constant of the first sensor circuit is greater than an RC time constant of the second sensor circuit.2. The apparatus as recited in claim 1 , wherein the first and second sensor circuits are implemented in a global power domain claim 1 , and wherein the first and second clamp transistors are implemented in a gated power domain.3. The apparatus as recited in claim 2 , further comprising first and second power switches coupled between the global power domain and the gated power domain claim 2 , wherein the first and second sensor circuits are configured to cause activation of the first and second power switches claim 2 , respectively claim 2 , responsive to the ESD event.4. The apparatus as recited in claim 1 , wherein the first sensor circuit is a first type of sensor circuit and the second sensor circuit is a second type of sensor circuit claim 1 , wherein the circuit further comprises multiple ...

Dynamically Modulating Link Width

Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability. 1. A method comprising:receiving from a remote port a remote width capability during a link initialization, the remote width capability corresponding to the remote port and including a plurality of supported link widths;comparing the remote width capability to a local width capability of a local port; andselecting a common link map that the remote port and the local port can support; andoperating a link between the local port and the remote port at a plurality of link widths in accordance with the remote width capability.2. The method of claim 1 , further comprising operating the link at the plurality of link widths without an additional link initialization or negotiation between the local port and the remote port.3. The method of claim 1 , further comprising establishing a first link width for the link based on the remote width capability and the local width capability claim 1 , and selecting a second link width to be narrower than the first link width based on the remote width capability and an operating condition of the local port including a power saving condition claim 1 , and modulating the link to the second link width and placing a portion of the local port in a low power state after modulating the link to the second link width.4. The method of claim 3 , further comprising if an increased bandwidth requirement exists claim 3 , selecting the second link width to be wider than the first link width claim 3 , and bringing a portion of the local port out of a low power state and modulating the link to the second link width.5. The method of claim 1 , further including placing an active portion of the local port in an intermediate power state responsive to ...

Physical Layer for Peripheral Interconnect with Reduced Power and Area

An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments.

Link power savings with state retention

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

DYNAMICALLY MODULATING LINK WIDTH

Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability. 1. An apparatus comprising:a hardware local port having control logic to receive from a remote port a remote width capability during a link initialization, the remote width capability of the remote port and including a plurality of supported link widths, compare the remote width capability to a local width capability of the local port, select a common link map that the remote port and the local port can support, and operate a link between the local port and the remote port at a plurality of link widths in accordance with the remote width capability, wherein the control logic is to establish a first link width for the link based on the remote width capability and the local width capability, select a second link width narrower than the first link width based on the remote width capability and a power saving condition of the local port and modulate the link to the second link width, place a portion of the local port in a low power state after the link modulation to the second link width, and transmit data to the remote port at the second link width after the modulation of the link to the second link width if a predetermined amount of time has elapsed after notification of second link width to the remote port.2. The apparatus of claim 1 , wherein the control logic is to bring a portion of the local port out of the low power state before modulation of the link to a third link width wider than the first link width responsive to an increased bandwidth condition.3. The apparatus of claim 1 , wherein each of the plurality of link widths is a different bit width.4. The apparatus of claim 1 , wherein the link comprises a point-to-point link.5. The apparatus of claim 1 ...

Compact System with Memory and PMU Integration

One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits. 1. A system comprising:a first integrated circuit comprising one or more logic circuit components; and a plurality of capacitors, wherein the plurality of capacitors provide decoupling capacitance for the one or more logic components on the first integrated circuit; and', 'a plurality of power management units configured to provide a power supply to respective ones of the one or more logic circuits on the first integrated circuit., 'a second integrated circuit coupled to the first integrated circuit, wherein the second integrated circuit is manufactured using a dynamic random access memory (DRAM) fabrication process, and the second integrated circuit comprises2. The system as recited in wherein the second integrated circuit further comprises a DRAM.3. The system as recited in wherein the DRAM is a cache for a main memory DRAM that is external to the second integrated circuit.4. The system as recited in further comprising a third integrated circuit coupled to the second integrated circuit claim 3 , wherein the third integrated circuit is coupled to the main memory DRAM.5. The system as recited in wherein the third integrated circuit comprises a memory controller for the main memory DRAM.6. The system as recited in wherein the third integrated circuit further comprises a non-volatile memory.7. The system as recited in wherein the DRAM is a main memory for the system.8. The system as recited in further comprising a third integrated circuit including a non-volatile memory that is a backing store for the ...

WAFER RECONSTITUTION AND DIE-STITCHING

Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip including a reconstituted chip-level back endo of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material. 1. A chip comprising:a reconstituted chip-level back end of the line (BEOL) build-up structure including a plurality of interconnects;a die set on the reconstituted chip-level BEOL build-up structure; andan inorganic gap fill material on the reconstituted chip-level BEOL build-up structure and surrounding the die set.2. The chip of claim 1 , wherein the die set include a first die and a second die.3. The chip of claim 2 , wherein the first die includes a first die-level BEOL build-up structure claim 2 , and the second die includes a second die-level BEOL build-up structure.4. The chip of claim 3 , wherein the first and second die-level BEOL build-up structures each include damascene interconnects.5. The chip of claim 4 , wherein the reconstituted chip-level BEOL build-up structure includes damascene interconnects.6. The chip of claim 5 , wherein the reconstituted chip-level BEOL build-up structure includes aluminum damascene interconnects.7. The chip of claim 5 , wherein the inorganic gap fill material is an oxide or oxynitride.8. The chip of claim 5 , wherein the inorganic gap fill material includes a silicon matrix.9. The chip of claim 3 , wherein the reconstituted chip-level BEOL build-up structure includes intra-die interconnections for the first die claim 3 , intra-die interconnections for the second die claim 3 , and die-to-die interconnections between the first die and the second die.10. The chip of claim 9 , wherein the die-to-die interconnections between first die and second die do not include ESD protection circuits.11. The chip of claim 10 , wherein the reconstituted chip-level BEOL build-up structure includes ESD protection ...

High bandwidth routing for die to die interposer and on-chip applications

Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

Power management system switched capacitor voltage regulator with integrated passive device

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Systems and methods for interconnecting dies

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

Link power savings with state retention

Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Physical Layer for Peripheral Interconnect with Reduced Power and Area

An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments.

ESD Protection for Advanced CMOS Processes

Various embodiments of ESD protection circuits and methods for operating the same are disclosed. In one embodiment, one or more driver circuits are protected by a first ESD protection circuit configured to activate and discharge current responsive to an ESD event. The driver circuit may include a pull-up transistor and a pull-down transistor each coupled to drive an output node. A second ESD protection circuit may be associated with and dedicated to the pull-up transistor in the driver circuit. 1. A circuit comprising:a driver comprising a first transistor coupled between a power node and an output node and a second transistor coupled between the output node and a reference node;a first electrostatic discharge (ESD) protection circuit configured to provide protection for the driver responsive to detection of an ESD event; anda second ESD protection circuit configured to provide protection exclusively to the first transistor responsive to detection of the ESD event.2. The circuit as recited in claim 1 , wherein the first transistor is a p-channel metal oxide semiconductor (PMOS) transistor and wherein the second transistor is a first n-channel metal oxide semiconductor (NMOS) transistor.3. The circuit as recited in claim 2 , wherein the second ESD protection circuit comprises one or more series-coupled diodes connected in parallel with the first transistor between the power node and the output node.4. The circuit as recited in claim 3 , wherein the second ESD protection circuit comprises a plurality of series-coupled diodes shared among a plurality of additional drivers and at least one additional diode coupled in series between the output node of the driver and the plurality of series-coupled diodes claim 3 , wherein the at least one additional diode is dedicated to the driver.5. The circuit as recited in claim 2 , wherein the second ESD protection circuit comprises a trigger circuit configured to activate the first transistor responsive to detecting the ESD event.6 ...

Method and apparatus for electrodialytic chemical mechanical polishing and deposition

Embodiments of the invention include methods and apparatus for electrodialytic polishing of various layers formed on semiconductor substrates. In certain embodiments the use of electrodialytic processes in conjunction with chemical mechanical forces to achieve a copper interconnect with a desired level of planarity and process performance. In certain embodiments electrodialytic polishing uses an electrodialytic polish pad, which is an active pad which has copper binding groups provided in its core structure and has an added capability of allowing electrical conductivity. An electrodialytic polish pad allows transfer of cations or anions through a membrane in the presence of an electric field and into a cathodic electrolyte. Under the influence of an electric field the electrodialytic polish pad and/or electrodialytic pads are continuously refreshed to bind cations.

I/O link with configurable forwarded and derived clocks

An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.

Methods and apparatuses for detecting clock failure and establishing an alternate clock lane

Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.

Methods and apparatuses to effect a variable-width link

Diode and transistor design for high speed I/O

An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances

A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

Device and method for retraining a receiver, and a transmitter

Methods and apparatuses to effect a variable-width link

Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

Method, system, and apparatus for loopback entry and exit

A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback test based on detection of a header within a packet. The slave and master agent to support exit out of the loopback test based on whether the loop count is finite.

A method and apparatus for interconnecting multiple devices on a circuit board

Flexible cable for high-speed interconnect

A system and method are disclosed in which flex cables are affixed to PCBs, for providing high-speed signaling paths between ICs disposed upon the PCBs. The flex cables are fixably attached to the PCBs so as to substantially mimic their structural orientation. Where the configuration includes more than one PCB, the flex cables include multiple portions which are temporarily separable from one another and from the die, using flex-to-flex and flex-to-package connectors, allowing field maintenance of the configuration. By routing the high-speed signals between ICs onto the flex cable, single-layer PCBs can be used for non-critical and power delivery signals, at substantial cost savings. By disposing the flex cables onto the PCB rather than allowing the cables to float freely, the configuration is thermally managed as if the signals were on the PCB and cable routing problems are avoided.

Equalizing a transmitter

In one embodiment, the present invention includes a method for associating a first plurality of current sources with a first tap coefficient and associating a second plurality of current sources with a second tap coefficient. A first plurality of output switches coupled to the first plurality of current sources is gated using the first tap coefficient and a second plurality of output switches coupled to the second plurality of current sources is gated using the second tap coefficient. In such manner, the first and second plurality of equalized current sources may be driven onto an interconnect. Other embodiments are described and claimed.

Method and apparatus for generating a reference voltage signal derived from complementary signals

A driver circuit and a receiver circuit. The driver circuit is coupled to drive two complementary signals and the receiver is coupled to receive the two complementary signals. The receiver circuit generates a reference voltage from the two complementary signals.

Low gain phase-locked loop circuit

According to some embodiments, a low gain phase-locked loop circuit is provided.

Programmable passive equalizer

Embodiments of a programmable passive equalizer are described herein.

Methods and apparatuses for detecting clock failure and establishing an alternate clock lane

Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.

Method, system, and apparatus for link latency management

Method and apparatus to emulate external IO interconnection

A method and apparatus are described herein that may be used to provide the cost effective characterization of IO interconnections as simplified RC networks thus allowing for efficient testing of multiple different external interconnection topologies. In one embodiment the electrical characteristics of an IO interconnection are measured and characterized. A resistive-captive network is then designed so that it approximates the IO interconnection within some specified tolerance. The RC network may be fabricated on-chip between the driver and the receiver of an IO port or the RC network may be implemented on a PCB to facilitate production testing. In an alternative embodiment, closer approximation to the actual characteristics of the IO interconnection is achieved through the conjunction of several RC networks. Moreover, this process is repeatable for the emulation of multiple different links.

Error monitoring for serial links

Methods, apparatuses and systems for physical link error data capture and analysis.

Digital signal testing

In an electronic system having logic agents that communicate with each other through one or more signal lines, a method for testing high speed digital signaling on the signal lines is disclosed. The method involves sensing a first crosstalk signal induced by a first digital signal. The first digital signal is driven by a first logic agent into a signal line to communicate with a second agent. The second agent is coupled to receive the first digital signal from the signal line. A logic waveform that represents the digital signal is recorded and/or displayed, based upon the crosstalk signal. The technique may also be used for testing simultaneous bidirectional signaling on the same signal line.

Method and apparatus for detecting strobe errors

A method and apparatus for detecting data strobe errors. A strobe error detection circuit has a strobe input and a counter coupled to the strobe input to count strobe pulses received. The circuit also has a comparator to determine if a strobe error has occurred based on the magnitude of the difference between a first count of strobe pulses and a second count of strobe pulses. In an embodiment, the first count is read from a memory location at a first time and the second count is read at a second time.

Seal Ring Designs Supporting Efficient Die to Die Routing

Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.

Decoupling device using stored charge reverse recovery

Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.

Impedance matched bus traces over de-gassing holes

Various bus trace topologies are provided which allow for shorter stub lengths, reduced motherboard costs, more efficient routing between multiple agents, and bus traces with better matched characteristic impedances.

Reference voltage distribution for multiload i/o systems

According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to reference voltage line based upon whether a driver is driving a data line.

Power management system switched capacitor voltage regulator with integrated passive device

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Structure and Method for Sealing a Silicon IC

Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

Very fine pitch and wiring density organic side by side chiplet integration

Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

Link power savings with state retention

Verbindungsenergieeinsparmodus mit Beibehaltung des Zustands

Es werden Verfahren und Vorrichtungen bezüglich Schnittstellenenergieeinsparungen mit Beibehaltung des Zustands beschrieben. In einer Ausführungsform wird/werden ein oder mehrere Komponenten von zwei über eine serielle Schnittstelle gekoppelten Agenten während Leerlaufperioden abgeschaltet, während der Verbindungszustand in jedem Agenten beibehalten wird. Es werden auch andere Ausführungsformen offenbart.

Verfahren und gerät zum bewirken einer verbindung von variabler breite

Power management system switched capacitor voltage regulator with integrated passive device

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Reference voltage distribution for multiload i/o systems

According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.

Semiconductor Package with Local Interconnect and Chiplet Integration

Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.

Systems and methods for implementing a scalable system

Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

Systems and methods for implementing a scalable system

Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

Selectable monolithic or external scalable die-to-die interconnection system methodology

Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

Structure and method for sealing a silicon IC

Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

Testing for digital signaling

Digital signal testing

In an electronic system having logic agents that communicate with each other through one or more signal lines, a method for testing high speed digital signaling on the signal lines is disclosed. The method involves sensing a first crosstalk signal induced by a first digital signal. The first digital signal is driven by a first logic agent into a signal line to communicate with a second agent. The second agent is coupled to receive the first digital signal from the signal line. A logic waveform that represents the digital signal is recorded and/or displayed, based upon the crosstalk signal. The technique may also be used for testing simultaneous bidirectional signaling on the same signal line.

Flexibles kabel für hochgeschwindigkeitsverbindung

Hochdichte 3d-verbindungs-konfiguration

Es werden elektronische Gehäusestrukturen und Systeme beschrieben, bei denen eine 3D-Verbindungsstruktur in eine Gehäuse-Umverteilungsschicht und/oder ein Chiplet zur Leistungs- und Signalabgabe an einen Chip integriert ist. Solche Strukturen können die Eingangs-Ausgangs-Dichte (E/A) und die Routing-Qualität für Signale erheblich verbessern, während die Leistungsabgabe machbar bleibt.

Input-output bus driver

A bus in which a transmission line is excited by a pMOSFET having a drain connected to the transmission line and having a source at a core voltage VCC, and in which the transmission line is terminated by a device connected to ground.

Verfahren, system und vorrichtung für die verwaltung der verbindungsverzögerung

不良のレーンを特定し、リンクを通じて接続された２つのｃｓｉエージェントの幅の容量を交換するための方法

【課題】 リンクの再初期化なしに、動的なリンク幅の調整に対応することを目的とする。 【解決手段】 システムのポイント・ツー・ポイント相互接続を使用して結合されたポートを備えた２つのリンクのエージェントが、そのリンク幅の対応容量を交換し、相互に合意できるリンク幅をネゴシエーションする技術が説明される。エージェントのそれぞれの対の間の相互接続は、複数の電気配線又はレーンを有する端方向リンクの対を有し、１つのリンクは第２のエージェントにデータを送信するために第１のエージェントにより使用され、他方のリンクは第１のエージェントにデータを送信するために第２のエージェントにより使用される。 【選択図】 図４

Vorrichtung, verfahren und system für serielle verbindungen

Low cost and high speed 3 load printed wiring board bus topology

A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.

3D Package with Chip-on-Reconstituted Wafer or Reconstituted Wafer-on-Reconstituted Wafer Bonding

Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.

3d package with chip-on-reconstituted wafer or reconstituted wafer-on-reconstituted wafer bonding

Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets. A heat spreader may be bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding. The chiplets within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

用於多負載輸入/輸出(i/o)系統的基準電壓分佈

Reference voltage distribution for multiload I/O systems