Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a die including a first surface, a recess extended from an aperture disposed on the first surface and including a sidewall disposed within the die, and a polymeric member configured for filling and sealing the recess and including a first outer surface and a second outer surface, wherein the first outer surface is interfaced with the sidewall of the recess.

3D package with through substrate vias

A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.

3D Package With Through Substrate Vias

A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.

Semiconductor device

A semiconductor device includes a substrate including a pad and an alignment feature disposed over the substrate, a passivation disposed over the substrate and a periphery of the pad, a post passivation interconnect (PPI) including a via portion disposed on the pad and an elongated portion receiving a conductive bump to electrically connect the pad with the conductive bump, a polymer covering the PPI, and a molding material disposed over the polymer and around the conductive bump, wherein the molding material comprises a first portion orthogonally aligned with the alignment feature and adjacent to an edge of the semiconductor device and a second portion distal to the edge of the semiconductor device, a thickness of the first portion is substantially smaller than a thickness of the second portion, thereby the alignment feature is visible through the molding material under a predetermined radiation.

CONDUCTIVE TRACES IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME

A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line. 1. A method for forming a semiconductor device comprising:depositing a passivation layer over a die, the passivation layer physically contacting the device die;depositing a first polymer layer over the passivation layer, the polymer layer physically contacting the passivation layer;forming a first conductive feature and a second conductive feature at the same time, the first conductive feature and a second conductive feature physically contacting the top surface of the first polymer layer, wherein the first conductive feature is part of a conductive signal line and the second conductive feature is part of a conductive power line;after forming the first conductive feature and the second conductive feature, forming a third conductive feature over and physically contacting the second conductive feature; anddepositing a second polymer layer over the first polymer layer, the second polymer layer physically contacting the top surface of the first polymer layer, a sidewall of the first conductive feature, a sidewall of the second conductive feature, and a sidewall of the third conductive feature.2. The method of claim 1 , further comprising forming an external connector over and electrically connected to ...

Method of manufacturing a semiconductor device having scribe lines

The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region. The method further includes disposing a buffer layer at least covering the scribe line, disposing a dielectric layer including an opening over each chip region, and disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region. The method further includes forming a mold over the substrate, covering the buffer layer and cutting the substrate along the scribe line. Furthermore, the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate including a front side, a conductive bump disposed over the front side, and an opaque molding disposed over the front side and around a periphery portion of an outer surface of the conductive bump, wherein the opaque molding includes a recessed portion disposed above a portion of the front side adjacent to a corner of the substrate and extended through the opaque molding to expose the portion of the front side and an alignment feature disposed within the portion of the front side.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.

Conductive Traces in Semiconductor Devices and Methods of Forming Same

An embodiment device package includes a semiconductor device die comprising a passivation layer at a top surface, a first conductive line over the passivation layer and electrically connected to the device die, and a second conductive line over the passivation layer and electrically connected to the device die. The first conductive line is thicker than the second conductive line, and the first conductive line and the second conductive line are formed in a same device package layer. 1. A device package comprises:a semiconductor device die comprising a passivation layer and a polymer layer over the passivation layer;a first conductive line over the polymer layer and electrically connected to the semiconductor device die; anda second conductive line over the polymer layer and electrically connected to the semiconductor device die, wherein the portion of the first conductive line above the polymer layer is thicker than the portion of the second conductive line above the polymer layer, and wherein the first conductive line and the second conductive line are formed in a same device package layer.2. The device package of claim 1 , wherein a top surface of the polymer layer is substantially level with bottom surfaces of the first conductive line and the second conductive line.3. The device package of claim 1 , wherein a top surface of the polymer layer is substantially level with top surfaces of the first conductive line and the second conductive line.4. The device package of claim 1 , wherein the first conductive line has a first thickness claim 1 , wherein the second conductive line has a second thickness claim 1 , and wherein a ratio of the first thickness to the second thickness is about 1.5 to about 2.5.5. The device package of claim 1 , wherein the first conductive line is a power line or a ground line claim 1 , and wherein the second conductive line is an electrical signal line.6. The device package of further comprising a third conductive line formed in the same ...

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Conductive traces in semiconductor devices and methods of forming same

An embodiment device package includes a semiconductor device die comprising a passivation layer at a top surface, a first conductive line over the passivation layer and electrically connected to the device die, and a second conductive line over the passivation layer and electrically connected to the device die. The first conductive line is thicker than the second conductive line, and the first conductive line and the second conductive line are formed in a same device package layer.

Semiconductor structure with oval shaped conductor

A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

REINFORCEMENT STRUCTURE FOR FLIP-CHIP PACKAGING

The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region. 1. A device comprising:a carrier substrate having a chip region and a periphery region, wherein the carrier substrate includes a reinforcement structure embedded within the periphery region; anda chip bonded to the chip region of the carrier substrate.2. The device of wherein the reinforcement structure includes metal.3. The device of wherein the metal is copper.4. The device of wherein the carrier substrate includes a first surface and a second surface opposite the first surface claim 1 , the reinforcement substrate extending within the carrier substrate from the first surface to the second surface.5. The device of wherein the chip includes an active surface and another surface opposite the active surface claim 4 , wherein the active surface of the chip is electrically coupled to one of the first surface and the second surface of the carrier substrate.6. The device of wherein the reinforcement structure encloses the chip.7. The device of wherein the reinforcement structure includes a plurality of posts disposed within the carrier substrate claim 1 , the plurality of posts enclosing the chip.8. The device of wherein the reinforcement structure is disposed in a corner of the carrier substrate.9. The device of wherein the reinforcement structure is L-shaped.10. The device of wherein the carrier substrate is a laminate substrate11. The device of wherein the laminate substrate includes bismaleimide-triazine (BT).12. A package substrate comprising:a laminate substrate including a chip region and a periphery region, the chip region being configured for bonding to a chip; anda ...

3D Semiconductor Package Interposer with Die Cavity

A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die. 1. A method of forming a semiconductor device , the method comprising:attaching one or more first dies to a first side of an interposer using conductive bumps, wherein the conductive bumps are attached to bond pads on a first side of the interposer;attaching one or more second dies to a second side of the interposer using conductive bumps, wherein the conductive bumps are attached to bond pads on a second side of the interposer; andattaching the interposer to a substrate such that at least one of the one or more second dies is positioned within a cavity in the substrate.2. The method of claim 1 , further comprising attaching a carrier substrate to the first side of the interposer and the one or more first dies prior to the attaching one or more second dies and removing the carrier substrate after the attaching one or more second dies.3. The method of claim 1 , further comprising forming a thermal pad layer in the cavity.4. The method of claim 1 , wherein the substrate includes a heat conductive pad layer under the cavity.5. The method of claim 4 , wherein the heat conductive pad layer extends from the cavity to an opposing side of the substrate.6. A method of forming a device comprising:mounting a first die on a first side of an interposer, ...

METHODS AND APPARATUS FOR HEAT SPREADER ON SILICON

Apparatus and methods for forming a heat spreader on a substrate to release heat for a semi-conductor package are disclosed. The apparatus comprises a substrate. A dielectric layer is formed next to the substrate and in contact with a surface of the substrate. A heat spreader is formed next to the substrate and in contact with another surface of the substrate. A passivation layer is formed next to the dielectric layer. A connection pad is placed on top of the passivation layer. The substrate may comprise additional through-silicon-vias. The contact surface between the substrate and the heat spreader may be a scraggy surface. The packaging method further proceeds to connect a chip to the connection pad by way of a connection device such as a solder ball or a bump. 1. A structure for releasing heat for a semi-conductor package , comprising:a substrate;a dielectric layer on a first surface of the substrate;a passivation layer on the dielectric layer;a connection pad on the passivation layer; anda heat spreader layer in contact with a second surface of the substrate opposite to the first surface.2. The structure of claim 1 , further comprising a chip connected to the connection pad by way of a connection device.3. The structure of claim 1 , further comprising a plurality of connection devices in contact with the heat spreader layer and connected to a print circuit board.4. The structure of claim 1 , wherein the passivation layer has an opening where the connection pad is located.5. The structure of claim 1 , the substrate further comprising a plurality of through-silicon-vias (TSV).6. The structure of claim 5 , wherein a TSV of the plurality of TSVs has a height that is equal to a height of the substrate.7. The structure of claim 1 , the heat spreader layer comprising Ni claim 1 , Cu claim 1 , or other thermally conductive material.8. The structure of claim 1 , wherein the substrate has a scraggy surface in contact with the heat spreader layer.9. The structure of claim ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.

PACKAGE STRUCTURE, CHIP STRUCTURE AND METHOD OF FABRICATING THE SAME

A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer. 1. A chip structure , comprising:a first semiconductor chip, comprising a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and a plurality of first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer;a second semiconductor chip embedded within the first semiconductor chip and surrounded by the gap fill layer and the plurality of first conductive vias, wherein the second semiconductor chip comprises a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and a plurality of second conductive vias embedded in the second protection layer and electrically connected with the second ...

MEDICATIONS DIRECTING SYSTEM AND METHOD WITH CLOUD SERVER

A monitoring system includes a cloud server, a first terminal, a second terminal, and a third terminal. The first, second and third terminal are connected to the cloud server. The cloud server includes an updating module and a storing module. The first terminal includes an obtaining module. The second terminal includes an analyzing module. The third terminal includes a downloading module. The obtaining module is used obtain a Body Mass Index to the cloud server, and the analyzing module is used to receive an updated dosage of reagents according to the Body Mass Index to the cloud server. The updating module is used to update an original dosage of reagents in the storing module according the updated dosage of reagents, and the downloading module is used to download the updated dosage of reagents, for allowing the third terminal to dispense pills. The disclosure further provides a monitoring method. 1. A medication directing system comprising:a cloud server comprising an updating module and a storing module;a first terminal connected to the cloud server and comprising an obtaining module;a second terminal connected to the cloud server and comprising an analyzing module; anda third terminal connected to the cloud server and comprising a downloading module;wherein the obtaining module is configured to obtain a Body Mass Index to send to the cloud server; the analyzing module is configured to receive an updated dosage of reagents according to the Body Mass Index to send to the cloud server; the updating module is configured to update an original dosage of reagents in the storing module according the updated dosage of reagents; and the downloading module is configured to download the updated dosage of reagents from the storing module, for allowing the third terminal to dispense pills according to the updated dosage of reagents.2. The medication directing system of claim 1 , wherein the cloud server further comprise a cloud transreceiving module configured for receiving ...

AUTOMATIC PILL GRASPING APPARATUS

An automatic pill grasping apparatus includes an enclosure, a control chip, a pill grasping mechanism, and a pill storage mechanism. The enclosure includes a base. The pill grasping mechanism includes a grasping arm, a nozzle, and a driving mechanism. The nozzle being is engaged with the grasping arm, and the driving mechanism is attached to the base. The pill storage mechanism includes a plurality of pill storage cases for storing pills and an actuating mechanism attached to the base. The control chip is configured to control the actuating mechanism to rotate the plurality of pill storage cases in a first plane substantially parallel to the base and control the driving mechanism to rotate the grasping arm in a second plane perpendicular to the first plane, for rotating the nozzle to stretch into the one of the plurality of pill storage cases to pick a pill. 1. An automatic pill grasping apparatus , comprising:an enclosure comprising a base;a control chip;a pill grasping mechanism comprising a grasping arm, a nozzle, and a driving mechanism, the nozzle being engaged with the grasping arm, and the driving mechanism attached to the base; anda pill storage mechanism comprising a plurality of pill storage cases for storing pills and an actuating mechanism attached to the base;wherein the control chip is configured to control the actuating mechanism to rotate the plurality of pill storage cases in a first plane substantially parallel to the base and control the driving mechanism to rotate the grasping arm in a second plane perpendicular to the first plane, for rotating the nozzle to stretch into the one of the plurality of pill storage cases to pick a pill.2. The automatic pill grasping apparatus of claim 1 , wherein the pill grasping mechanism further comprises a pump attached to the base and a pipe communicating the pump with the nozzle claim 1 , and the pump is configured to generate a negative pressure to the nozzle to draw the pill.3. The automatic pill grasping ...

AUTOMATIC PILL GRASPING APPARATUS AND METHOD

A pill grasping method comprises rotating a grasping arm with a nozzle to a predetermined initial position driven by a driving mechanism, rotating a number of pill storage cases to position one of the pill storage cases with a set number of pills to a predetermined grasping pill position driven by an actuating mechanism, rotating the grasping arm to enter into the corresponding pill storage case, starting a pump to generate a vacuum in the nozzle for sucking a pill, and determining if an actual pressure value in a pipe connecting the nozzle to the pump is less than a predetermined pressure value. The grasping arm is rotated to the predetermined initial position when the actual pressure value is less than the predetermined pressure value. 1. A pill grasping method , the method comprising:rotating a grasping arm with a nozzle to a predetermined initial position driven by a driving mechanism;rotating a plurality of pill storage cases to locate one of the plurality of pill storages with a set pill species to a predetermined grasping pill position driven by an actuating mechanism;rotating the grasping arm to stretch into the one of the plurality of pill storage case;starting a pump to generate vacuum to the nozzle for sucking a pill;determining if an actual pressure value in a pipe connecting the nozzle to the pump being less than a predetermined pressure value; androtating the grasping arm to the predetermined initial position when the actual pressure is less than the predetermined pressure value.2. The pill grasping method of claim 1 , wherein after the block of rotating the grasping arm to the predetermined initial position when the actual pressure is less than the predetermined pressure value claim 1 , the method further comprises:determining if the actual pressure value is less than the predetermined pressure value;rotating a pill output case to the predetermined grasping pill position when the actual pressure value is not less than the predetermined pressure value; ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via. 1. A package structure , comprising:a molding compound;an antenna element molded in the molding compound;at least one die located on the molding compound;a redistribution layer located between the at least one die and the molding compound, wherein the redistribution layer includes a ground plane portion and a location of the antenna element is overlapped with a location of the ground plane portion in a vertical projection on the redistribution layer; andconductive elements connected to a first side of the redistribution layer, wherein the at least one die is connected to the first side of the redistribution layer, and positioning locations of the conductive elements are aside of a positioning location of the at least one die in the vertical projection.2. The package structure of claim 1 , further comprising at least one through interlayer via encapsulated in the molding compound claim 1 , wherein the at least one through interlayer via is connected to the antenna element and the antenna element is electrically connected to the at least one die through the redistribution layer and the at least one through interlayer via.3. The package structure of claim 1 , wherein the location of the antenna element is overlapped with a location of the at least one die in the vertical projection.4. The package structure of claim 1 , wherein the redistribution layer is located between the conductive elements and the antenna element.5. The package structure of claim 1 , further comprising a protective layer located on the molding compound and covering the antenna element.6. A package structure ...

Copper Post Structure for Wafer Level Chip Scale Package

In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure. 1. A device , comprising:a semiconductor substrate;a metal pad on the semiconductor substrate;a first polymer insulating layer overlying the semiconductor substrate and covering a portion of the metal pad;a monolithic copper-containing structure over the metal pad and the first polymer insulating layer, and electrically connected to the metal pad, the monolithic copper-containing structure comprising:a via portion contacting the metal pad embedded in the first polymer insulating layer;a bottom portion having a first thickness and a first width, wherein the bottom portion comprises a post-passivation interconnect (PPI) line; anda top portion adjoining the bottom portion and having a second thickness and a second width, the monolithic copper-containing structure having an undercut structure between the top portion and the bottom portion, wherein the second thickness is greater than the first thickness, and the first width is greater than the second width; anda conductive bump over the top portion of the monolithic copper-containing structure.2. The device of claim 1 , wherein the PPI line is a redistribution ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate. 1. A semiconductor device , comprising:a chip substrate;a mold over the chip substrate; anda buffer layer externally embedded between the chip substrate and the mold, wherein the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold.2. The semiconductor device of claim 1 , wherein the chip substrate comprises an active region and a guard structure region around the active region claim 1 , wherein the buffer layer partially overlies the guard structure region.3. The semiconductor device of claim 2 , wherein the chip substrate comprises a dummy structure in the guard structure region and a seal ring structure between the active region and the dummy structure claim 2 , wherein the buffer layer covers the dummy structure.4. The semiconductor device of claim 1 , further comprising a dielectric layer that extends over the active region of the chip substrate and the guard structure region claim 1 , wherein the buffer layer is separated from the dielectric layer by a gap.5. The semiconductor device of claim 4 , wherein the gap is in a range of from 5 to 20 micrometers.6. The semiconductor device of claim 1 , wherein the buffer layer has a thickness in a range of 5 to 20 micrometers.7. The semiconductor device of claim 1 , ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes: receiving a first substrate with a surface; receiving a second substrate; determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad; forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern and the second type pad in the pad array is clear of any via of the via pattern; laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; and disposing a first conductive bump and a second conductive bump between the first substrate and the second substrate. 1. A method of manufacturing a semiconductor device , comprising:receiving a first substrate with a surface;receiving a second substrate;determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad;forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern and the second type pad in the pad array is clear of any via of the via pattern;laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; anddisposing a first conductive bump and a second conductive bump between the first substrate and the second substrate thereby connecting the first substrate and the second substrate through the first type pad and the second type pad in the pad array.2. The method of claim 1 , further comprising calculating a distance of each pad of the pad array from a neutral point of the pad array.3. The method of claim 1 , ...

Automatic pill dispenser

An automatic pill dispenser includes a chassis, a pill dispensing box located on the chassis, a pill box located on the chassis for a plurality of pills, and a pill fetching assembly. The pill fetching assembly is located on the chassis. The pill fetching assembly includes a driving device and a fetching device. The fetching device includes a boom and an arm assembly. The arm assembly is located on an end of the boom to fetch the plurality of pills from the pill box. The driving device includes a cam adjacent to the boom. The fetching device rotates relative to the chassis in a horizontal plane. The cam urges the fetching device to rotate within a vertical plane.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes first and second semiconductor dies bonded together. The first semiconductor die includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the first semiconductor substrate through the first interconnect structure. The second semiconductor die includes a second semiconductor substrate and a second interconnect structure disposed below and electrically coupled to the second semiconductor substrate, and a through semiconductor via penetrating through the second semiconductor substrate and extending into the second interconnect structure to be electrically coupled to the second interconnect structure. The first bonding conductor extends from the first interconnect structure towards the through semiconductor via to electrically connect the first semiconductor die to the second semiconductor die. The first bonding conductor corresponding to the through semiconductor via is smaller than the through semiconductor via. 1. A semiconductor structure , comprising: a first semiconductor substrate;', 'a first interconnect structure disposed below the first semiconductor substrate; and', 'a first bonding conductor disposed below the first interconnect structure and electrically coupled to the first semiconductor substrate through the first interconnect structure; and, 'a first semiconductor die comprising a second semiconductor substrate and a second interconnect structure disposed below and electrically coupled to the second semiconductor substrate; and', 'a through semiconductor via penetrating through the second semiconductor substrate and extending into the second interconnect structure to be electrically coupled to the second interconnect structure, wherein the first bonding conductor of the first semiconductor die extends from the first interconnect structure of the first ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element. 1. A package structure , comprising:a ground plate;a semiconductor die, located over the ground plate;a molding compound, located over the semiconductor die; andan antenna element, located in the molding compound and overlapping with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound, wherein the antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.2. The package structure of claim 1 , wherein the antenna element has a second side opposing the first side along the stacking direction and a third side connecting the first side and the second side claim 1 , and a portion of the second side and a portion of the third side overlapped with the ground plate are covered by the molding compound.3. The package structure of claim 2 , further comprising:a redistribution circuit structure, located on a second surface of the molding compound and electrically connected to the semiconductor die, the second surface being opposite to the first surface along the stacking direction, wherein the ground plate is a part of redistribution circuit structure, and the redistribution circuit structure is located between the semiconductor die and the molding compound.4. The package structure of claim 3 , further comprising:at least one ...

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a metal derivative in a second region of a post-passivation interconnect (PPI);forming a flux layer in a first region of the PPI, wherein the first region is surrounded by the second region;dropping a solder ball on the flux layer; andforming electrical connection between the solder ball and the PPI.2. The method of manufacturing a semiconductor package in claim 1 , wherein the to patterning the metal derivative in the second region of the PPI further comprising forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer on the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the metal derivative in the second region of the PPI comprises an oxygen plasma ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING PACKAGE STRUCTURE

A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film. 1. A package structure comprising:a radio frequency integrated circuit (RFIC) chip;a redistribution circuit structure disposed at a first side of the RFIC chip and electrically connected to the RFIC chip;a backside redistribution circuit structure disposed at a second side of the RFIC chip and electrically connected to the RFIC chip through the redistribution circuit structure, wherein the first side is opposite to the second side;an isolation film disposed between the backside redistribution circuit structure and the RFIC chip;a die attach film disposed between the RFIC chip and the isolation film; andan insulating encapsulation encapsulating the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure, wherein the isolation film has a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.2. The package structure of claim 1 , wherein the isolation film has a dissipation factor lower than the insulating encapsulation and the die attach film.3. The package structure of ...

PACKAGE STRUCTURE

A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die. 1. A package structure , comprising:a first redistribution circuit structure;a semiconductor die, located on and electrically connected to the first redistribution circuit structure; andfirst antennas and second antennas, located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure,wherein a first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.2. The package structure of claim 1 , wherein a second group of the first antennas are located at a third position claim 1 , a second group of the second antennas are located at a fourth position claim 1 , and the third position is different from the fourth position in the stacking direction claim 1 ,wherein the first position is the same as the third position and the second position is the same as the fourth position in the stacking direction.3. The package structure of claim 2 , wherein the first antennas and the second antennas are aside of the ...

PACKAGE AND MANUFACTURING METHOD OF RECONSTRUCTED WAFER

A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die. 115-. (canceled)16. A manufacturing method of a reconstructed wafer , comprising:providing a first carrier substrate having a first alignment mark formed thereon;attaching a plurality of first dies to the first carrier substrate, wherein the first dies are arranged in an array;fusion bonding the first dies to a second carrier substrate opposite to the first carrier substrate;removing the first carrier substrate from the first dies;forming a first bonding layer onto the first dies;individually placing a plurality of second dies on the corresponding first dies, wherein each second die comprises a semiconductor substrate, a plurality of through semiconductor vias (TSV) embedded in the semiconductor substrate, and a second bonding layer over the semiconductor substrate, and the second bonding layers of the second dies are hybrid bonded to the first bonding layer; andplanarizing the second dies until the TSVs are exposed.17. The method of claim 16 , further comprising:thinning the first dies before the first dies are fusion bonded to the second carrier substrate.18. The method of claim 16 , further comprising:laterally encapsulating the first dies by a first insulating layer before the first dies are fusion bonded to the second carrier substrate;laterally encapsulating the second dies by a second insulating layer; andforming a redistribution structure over the second dies and the second insulating layer, wherein the redistribution structure is electrically connected to the TSVs.19. The method of claim 16 , further comprising:forming a second ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI. 1. A semiconductor structure , comprising:a semiconductive substrate;a post passivation interconnect (PPI) disposed above the semiconductive substrate and including a landing area for receiving a conductor, anda polymer layer on the PPI, wherein the conductor is necking at a turning point so as to include an oval portion being substantially surrounded by the polymer layer,wherein the oval portion of the conductor is disposed on the landing area of the PPI.2. The semiconductor structure of claim 1 , wherein the oval portion includes a projective area at the turning point claim 1 , the projective area has a shape attributed from the landing area.3. The semiconductor structure of claim 2 , wherein the projective area includes an aspect ratio substantially equal to an aspect ratio of the landing area claim 2 , wherein the aspect ratio is a ratio of the longest axis to the shortest axis.4. The semiconductor structure of claim 2 , wherein the projective area and the landing area respectively include a shortest axis claim 2 , and the shortest axis of the landing area is between about 0.7 and about 1.0 times a length of the shortest axis of the projective area.5. The semiconductor structure of claim 2 , wherein the projective area includes an aspect ratio less than about 0.85.6. The semiconductor structure of claim 1 , wherein the conductor includes a portion connecting with the oval portion and exposed outside the polymer layer claim 1 , wherein a curvature of the portion is greater than a curvature ...

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE AND METHOD FOR PACKAGING SEMICONDUCTOR DEVICE

A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area. 1. A semiconductor package , comprising:a first conductive wire layer with a first mounting area and a second mounting area, wherein the first mounting area and the second mounting area do not overlap;an integrated circuit (IC) disposed on a first surface of the first mounting area, wherein the IC is electrically insulated from the first conductive wire layer;a radiation fin structure, disposed on a second surface of the first mounting area; andan antenna, disposed on the second mounting area.2. The semiconductor package of claim 1 , wherein the antenna is disposed on a surface of the second mounting area claim 1 , and the second surface of the first mounting area and the surface of the second mounting area are in the same plane.3. The semiconductor package of claim 1 , wherein the antenna is disposed side-by-side to the heat dissipation structure.4. The semiconductor package of claim 1 , further comprising:a first thermal paste layer, disposed between the IC and the second surface of the first conductive wire layer to form a heat dissipation path from the IC to the radiation fin structure through the first conductive wire layer, wherein the first thermal paste layer is formed by thermally conductive and electrically insulated material.5. The semiconductor package of claim 1 , wherein the antenna comprises at least one first antenna patch claim 1 , and the at least one first antenna patch is formed ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element. 1. A package structure , comprising:a ground plate;a semiconductor die, located on the ground plate;a molding compound, encapsulating the semiconductor die and the ground plate; andan antenna element, located in the molding compound and overlapping with the ground plate, wherein the antenna element has a first side, a second side and a third side connecting the first side and the second side, and a portion of the second side and a portion of the third side overlapped with the ground plate are exposed by a cavity located in the molding compound,wherein the ground plate is located between the semiconductor die and the antenna element along a stacking direction of the ground plate and the semiconductor die.2. The package structure of claim 1 , wherein the molding compound comprises a first portion and a second portion underlying the first portion along the stacking direction claim 1 , wherein:the semiconductor die is in the second portion;the antenna element is in the first portion; andthe ground plate is located between the first portion and the second portion.3. The package structure of claim 2 , wherein the cavity is located in the first portion of the molding compound.4. The package structure of claim 2 , further comprising:a first redistribution circuit structure, located on and electrically connected to the semiconductor die, wherein the ground plate is a part of the first ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die. 1. A structure , comprising:stacked substrates;a first semiconductor die disposed over the stacked substrates;a second semiconductor die stacked over the first semiconductor die; andan insulating encapsulation comprising a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.2. The structure as claimed in claim 1 , wherein an overall thickness of the stacked substrates ranges from about 1500 micrometers to about 1600 micrometers.3. The structure as claimed in claim 1 , wherein the first encapsulation portion being disposed over the stacked substrates claim 1 , and the second encapsulation portion is disposed over the first encapsulation portion and the first semiconductor die.4. The structure as claimed in claim 1 , wherein the first encapsulation portion is spaced apart from the second encapsulation portion by a bonding layer between the first semiconductor die and the second semiconductor die.5. The structure as claimed in claim 1 , further comprising a backside metal layer disposed over the stacked substrates claim 1 , wherein the stacked substrates are between the backside metal layer and the first semiconductor die.6. The structure as claimed in claim 5 , wherein a thickness of the backside metal layer ranges from about 10 micrometers to about 1000 micrometers.7. A structure claim 5 , comprising:a support substrate;a first semiconductor die disposed over a first surface of the support substrate;a second ...

SEMICONDUCTOR PACKAGE STRUCTURE

A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches. 1. A semiconductor package structure comprising:an encapsulation body;a radio frequency integrated circuit (RFIC) chip embedded in the encapsulation body;a first antenna structure disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and comprising a first conductor layer and a plurality of first patches opposite to the first conductor layer; anda second antenna structure stacked on the RFIC chip, electrically connected to the RFIC chip, and comprising a second conductor layer and a plurality of second patches opposite to the second conductor layer, wherein the first patches and the second patches are located at a surface of the encapsulation body and a first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.2. The semiconductor package structure of claim 1 , wherein the encapsulation body comprises a first insulating encapsulation and a second insulating encapsulation disposed on the first insulating encapsulation.3. The ...

PACKAGE STRUCTURE, ELECTRONIC DEVICE AND METHOD OF FABRICATING PACKAGE STRUCTURE

In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna. 1. A package structure , comprising:a radio frequency integrated circuit (RFIC) chip;an insulating encapsulation encapsulating the RFIC chip;a redistribution circuit structure disposed on the insulating encapsulation and electrically connected to the RFIC chip;an antenna disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure; anda microwave director, the antenna being located between the microwave director and the RFIC chip, wherein the microwave director has a microwave directivity enhancement surface located in a propagating path of a microwave received or generated by the antenna,wherein the microwave director comprises a base portion, an extension portion and a lens portion, the extension portion is located between the lens portion and the antenna, the base portion is located between the extension portion and the antenna, the base portion exceeds the extension portion on the antenna, and the lens portion has the microwave directivity enhancement surface.2. (canceled)3. The package structure of claim 1 , wherein a width of the extension portion is substantially constant.4. The package structure of claim 1 , wherein a width of the lens portion is gradually reduced in ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor. 1. A method for manufacturing a semiconductor structure , comprising:receiving a semiconductive substrate with a post passivation interconnect (PPI) including an oval landing area;forming a first conductor on the oval landing area;forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor;polishing the polymer layer and the first conductor in order to form a planarized surface; andforming a second conductor on the polished first conductor.2. The method of claim 1 , wherein polishing the polymer layer and the first conductor further comprises exposing a top surface of the first conductor.3. The method of claim 2 , further comprising planarizing the top surface of the first conductor.4. The method of claim 1 , wherein polishing the polymer layer and the first conductor further comprises applying a diamond disk on the polymer layer and the first conductor.5. The method of claim 1 , wherein receiving the semiconductive substrate comprises chucking the semiconductive substrate on a stage.6. The method of claim 1 , further comprising measuring a thickness of the polymer layer or the first conductor after polishing the polymer layer and the first conductor.7. A method for manufacturing a semiconductor structure claim 1 , comprising:receiving a semiconductive substrate with a metal pad thereon;depositing a layer on the metal pad and above the semiconductive substrate;removing a portion of the layer, thereby forming an oval area; ...

Automatic medicine retrieving device

An automatic medicine retrieving device includes a medicine tray, a medicine box, and a driving mechanism. The medicine tray includes a bearing plate defining an exit port and a medicine separating member rotatably positioned on the bearing plate. The medicine separating member has medicine separating areas and a positioning area. Medications in the form of pills are positioned on the bearing plate and received in the medicine separating areas. The medicine box is opposite to the exit port. The driving mechanism drives the medicine separating member to rotate from being opposite to the exit port, bringing the medicine separating area to a position opposite to the exit port. A pill in the medicine separating area then passes through the exit port to fall into an accepting mechanism.

Package structure

A package structure including an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna is provided. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation.

DIE STACK STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME

A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure. 1. A die stack structure , comprising:a bottom tier semiconductor die comprising a semiconductor substrate and an interconnect structure, the semiconductor substrate comprising a first portion and a second portion disposed on the first portion, the interconnect structure being disposed on a top surface of the second portion, a lateral dimension of the first portion being greater than a lateral dimension of the top surface of the second portion;a top tier semiconductor die bonded to the bottom tier semiconductor die;an insulating encapsulation disposed on the first portion and laterally encapsulating the second portion and the top tier semiconductor die; anda redistribution circuit structure electrically connected with the bottom tier semiconductor die and the top tier semiconductor die, wherein the lateral ...

SEMICONDUCTOR PACKAGES AND MANUFACTURING MEHTODS THEREOF

Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip. 1. A semiconductor package , comprising:a semiconductor chip; anda redistribution layer structure arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein from a top view, the antenna transmitter structure is outside of a chip region of the semiconductor chip, and the antenna receiver structure is within the chip region of the semiconductor chip.2. The semiconductor package of claim 1 , wherein the antenna transmitter structure surrounds the antenna receiver structure.3. The semiconductor package of claim 1 , wherein the transmitter structure has a ring shape claim 1 , a bar shape claim 1 , a spiral shape claim 1 , a wave shape claim 1 , a meandering shape or a combination thereof.4. The semiconductor package of claim 1 , wherein the antenna receiver structure has a plurality of first patterns over the semiconductor chip.5. The semiconductor package of claim 4 , wherein each of the plurality of first patterns has an island shape claim 4 , a snake shape claim 4 , a bar shape claim 4 , a fishbone shape claim 4 , a fence shape claim 4 , a grid shape claim 4 , a ring shape or a combination thereof.6. The semiconductor package of claim 4 , wherein the antenna receiver structure further has a plurality of second patterns over the plurality of first patterns.7. The semiconductor package of claim 6 , wherein the plurality of second patterns are aligned with the plurality of first patterns.8. The semiconductor package of claim 6 , wherein the antenna receiver structure further has a plurality of third patterns ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region. 1. A semiconductor structure , comprising:a circuit region including a first conductive layer;a seal ring region including a second conductive layer; andan assembly isolation region between the circuit region and the seal ring region, wherein the first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region,wherein one end of the electric component is in the seal ring region and the other end of the electric component is in the circuit region.2. (canceled)3. The semiconductor structure of claim 1 , further comprising a dielectric between the extended portion of the first conductive layer and the extended portion of the second conductive layer.4. The semiconductor structure of claim 3 , wherein a thickness uniformity of the dielectric is within about 0.5%.5. The semiconductor structure of claim 1 , wherein the first conductive layer is an interconnect of the circuit region.6. (canceled)7. (canceled)8. The semiconductor structure of claim 1 , wherein the extended portion of the second conductive layer is above the extended portion of the first conductive layer.9. The semiconductor structure of claim 1 , wherein the electric component is an inductor.10. A semiconductor structure claim 1 , comprising:a circuit region;a seal ring region surrounding the circuit region and ...

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A semiconductor package , comprising:a substrate;a passivation layer over the substrate;a post-passivation interconnect (PPI) having a top surface, positioning over the passivation layer; anda conductive structure electrically connected to the PPI, a first region receiving the conductive structure; and', 'a second region surrounding the first region,', 'wherein the second region comprises metal derivative transformed from materials made of the first region., 'wherein the top surface of the PPI comprises2. The semiconductor package in claim 1 , wherein the metal derivative of the second region comprises metal oxides or metal nitrides.3. The semiconductor package in claim 1 , wherein the PPI comprises a power line claim 1 , a redistribution line claim 1 , an inductor claim 1 , a capacitor claim 1 , or passive components.4. The semiconductor package in claim 3 , wherein the PPI comprises conductive materials claim 3 , and wherein the metal derivative of the second region comprises conductive material oxides.5. The semiconductor package in claim 1 , wherein the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric. 1. A semiconductor device , comprising:a first substrate including a surface;a pad array on the surface of the first substrate, wherein the pad array comprises a first type pad and a second type pad at a same level;a conductive bump connecting one of the first type pad of the second type pad to a second substrate;a first via connected to a conductive feature at a different level to the first type pad, the first via being located within a projection area of the first type pad and directly contacting the first type pad, wherein the second type pad is laterally connected with a conductive trace on the same level, and the conductive trace is connected to a second via that is at a same level with the first via; anda dielectric in the first substrate, the dielectric contacting the second type pad, wherein the second type pad is floated on the dielectric.2. The semiconductor device of claim 1 , wherein the second via is connected to the conductive feature.3. The semiconductor device of claim 1 , wherein the second type pad is arranged symmetrically to a geometric center of the pad array.4. The semiconductor device of claim 1 , wherein the first substrate is a printed ...

SEMICONDUCTOR PACKAGE STRUCTURE

A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches. 1. A semiconductor package structure comprising:an insulating encapsulation;an RFIC chip embedded in the insulating encapsulation;an antenna structure disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and comprising a conductor layer and a plurality of patches opposite to the conductor layer; andan isolation layer disposed between the conductor layer and the patches and embedded in the insulating encapsulation, wherein a dissipation factor of the isolation layer is lower than that of the insulating encapsulation.2. The semiconductor package structure of claim 1 , wherein the RFIC chip is stacked on the isolation layer.3. The semiconductor package structure of claim 1 , wherein a thickness of the isolation layer is the same as a thickness of the insulating encapsulation.4. The semiconductor package structure of claim 1 , wherein a thickness of the isolation layer is smaller than a thickness of the insulating encapsulation.5. The semiconductor package structure of claim 1 , further comprising a redistribution circuit structure disposed ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric. 1. A semiconductor device , comprising:a substrate including a surface; anda plurality of pads disposing on the surface of the substrate,wherein the plurality of pads includes a first type pad and a second type pad, the first type pad is contacting a via located underlying the first type pad and within a projection area of the first type pad, and the second type pad is contacting an underlying isolation within a projection area of the second type pad.2. The semiconductor device of claim 1 , wherein the first type pad is arranged in a first region of the surface and the second type pad is arranged in a second region of the surface claim 1 , and the second region is more proximal to a periphery of the substrate.3. The semiconductor device of claim 1 , wherein the via connects with a conductive trace underlying the first type pad.4. The semiconductor device of claim 1 , wherein the substrate includes a plurality of levels of conductive features and the via penetrates through the plurality of levels of conductive features.5. The semiconductor device of claim 1 , wherein the second type pad is arranged proximal to a corner of the substrate.6. The semiconductor device of claim 1 , wherein the second type pad is in a region of a pad array on the surface claim 1 , ...

Wafer on Wafer Bonding Structure

A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other. 1. A method comprising:thinning a first wafer to expose metal vias;forming a bonding layer over the metal vias, the metal vias extending through the bonding layer;positioning a second wafer to the first wafer, wherein bond pads of the second wafer align to the metal vias of the first wafer;bonding the bond pads of the second wafer with the metal vias of the first wafer without using a bonding material between the bond pads and the metal vias; andfusing the bonding layer of the first wafer to a bonding layer of the second wafer.2. The method of claim 1 , wherein forming the bonding layer comprises:recessing a first material surrounding the metal vias;depositing a second material corresponding to the bonding layer; andplanarizing the second material to level an upper surface of the second material with upper surfaces of the metal vias.3. The method of claim 1 , wherein forming the bonding layer comprises:depositing the bonding layer over the metal vias;forming openings in the bonding layer, the openings corresponding to the metal vias;depositing a metal via extension in the openings, the metal via extension being physically coupled to the metal vias; andplanarizing the metal via extension to level an upper surface of the bonding layer with upper surfaces of the metal via extensions.4. The method of claim 1 , wherein the first wafer and second wafer together form a first wafer stack claim 1 , further comprising:positioning the first wafer stack to a third wafer, wherein bond pads of the first wafer align to metal features of the third wafer;bonding the bond pads of the first wafer with the metal features of the third wafer without using a bonding material ...

Semiconductor structure and method of manufacturing the same

The present disclosure provides a semiconductor structure includes a sensing element configured to receive a signal from a sensing target, a molding surrounding the sensing element, a through via in the molding, a front side redistribution layer disposed at a front side of the sensing element and electrically connected thereto, and a back side redistribution layer disposed at a back side of the sensing element, the front side redistribution layer and the back side redistribution layer are electrically connected by the through via. The present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Conductive Traces in Semiconductor Devices and Methods of Forming Same

A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line. 1. A method for forming a semiconductor device comprising:forming a first insulating layer over a substrate;exposing a first portion and a second portion of the first insulating layer;exposing a third portion of the first insulating layer, wherein the third portion does not overlap the first portion and the second portion;removing the first portion, the second portion, and the third portion to form a first recess, a second recess, and a third recess, respectively, wherein the third recess has a different depth than the first recess and the second recess;forming a conductive material in the first recess, the second recess, and the third recess to form a first conductive line in the first recess, a second conductive line in the second recess, and a third conductive line in the third recess; anddepositing a second insulating layer over the first insulating layer.2. The method of claim 1 , wherein the third conductive line comprises a signal line claim 1 , wherein the first conductive line and the second conductive line comprise power/ground lines.3. The method of claim 1 , wherein a depth of the first recess and a depth of the second recess is greater than a depth of the third recess.4. The method of ...

PACKAGE STRUCTURES

A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer. The at least one connecting module connects to the first redistribution layer and is electrically connected to the at least one semiconductor chip through the first redistribution layer, wherein the at least one connecting module comprises a plurality of pins, and the at least one connecting module is mounted onto the first redistribution layer by the protection layer and is accessibly exposed by the protection layer. 1. A package structure , comprising:a first redistribution layer and a second redistribution layer;at least one semiconductor chip, located between and electrically connected to the first redistribution layer and the second redistribution layer;an insulating encapsulation, encapsulating the at least one semiconductor chip;a protection layer, disposed on and partially covering the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer; andat least one connecting module, connecting to the first redistribution layer and electrically connected to the at least one semiconductor chip through the first redistribution layer, wherein the at least one connecting module comprises a plurality of pins, and the at least one connecting module is mounted onto the first redistribution layer by the protection layer and is accessibly exposed by ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via. 1. A package structure , comprising:a molding compound having opposing first and second surfaces;at least one through interlayer via encapsulated in and penetrating through the molding compound;an antenna element at least partially molded in the molding compound and adjacent to the first surface of the molding compound, and electrically connected to the at least one through interlayer via; anda semiconductor die located on the second surface of the molding compound and electrically communicated to the antenna element via the at least one through interlayer via.2. The package structure of claim 1 , further comprising a redistribution layer between the semiconductor die and the molding compound claim 1 , wherein the redistribution layer is connected to the semiconductor die and is electrically coupled to the antenna element through the at least one through interlayer via.3. The package structure of claim 2 , wherein the at least one through interlayer via is connected to the antenna element and is electrically coupled to the semiconductor die through the redistribution layer.4. The package structure of claim 1 , further comprising a plurality of conductive elements electrically coupled to the semiconductor die claim 1 , wherein the plurality of conductive elements and the semiconductor die are located at a side of the molding compound.5. The package structure of claim 4 , wherein the semiconductor die and the plurality of conductive elements are overlapped with each other along a direction different from a stacking direction of the semiconductor die claim 4 , the molding compound ...

PACKAGE STRUCTURE, ELECTRONIC DEVICE AND METHOD OF FABRICATING PACKAGE STRUCTURE

In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna. 1. A structure , comprising:a radio frequency integrated circuit (RFIC) chip;an insulating encapsulation encapsulating the RFIC chip;an antenna disposed on the insulating encapsulation and electrically connected to the RFIC chip; anda microwave director comprising a base portion, an extension portion and a lens portion, wherein the extension portion is located between the lens portion and the antenna, the base portion is located between the extension portion and the antenna, the base portion exceeds the extension portion on the antenna, and the lens portion has a microwave directivity enhancement surface located in a propagating path of a microwave received or generated by the antenna.2. The structure of claim 1 , wherein the antenna comprises a plurality of patches located within an area of an orthogonal projection of the microwave directivity enhancement surface on a plane of the antenna.3. The structure of claim 1 , wherein a width of the extension portion is substantially constant in a direction away from the antenna claim 1 , and a width of the lens portion is gradually reduced in the direction away from the antenna.412212. The structure of claim 1 , wherein an flange portion of the base portion exceeding the extension portion has an ...

Structure and formation method of chip package with antenna element

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies. 1. A method of forming semiconductor structure , the method comprising:attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies;forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies;forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; anddicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.2. The method of claim 1 , further comprising:before the attaching, testing the bottom wafer through disposable probing pads disposed at the front side of the bottom wafer.3. The method of claim 2 , further comprising claim 2 , after the testing and before the attaching:removing the disposable probing pads from the bottom wafer;forming a dielectric layer over the front side of the bottom wafer after removing the disposable probing pads; andforming bonding pads extending through the dielectric layer and electrically coupled to the bottom dies, wherein the first conductive pillars are formed over respective ones of the bonding pads.4. The method of claim 1 , wherein the backsides of the top dies are attached to the front side of the bottom wafer through a fusion bonding process.5. The method of claim 4 , ...

Integrated Devices in Semiconductor Packages and Methods of Forming Same

An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna. 1. A method comprising:forming a ground element and a feed line of an antenna over a first side of a first dielectric layer, the first dielectric layer being on a substrate;placing a dielectric feature and a radio frequency chip over the ground element and the feed line, wherein a portion of the dielectric feature is interposed between the radio frequency chip and the ground element;encapsulating the radio frequency chip and the dielectric feature in an encapsulant, wherein the encapsulant is external to the radio frequency chip;detaching the substrate from the first dielectric layer;forming a second dielectric layer on a second side of the first dielectric layer, the second side being opposite the first side; andattaching a radiating element of the antenna to the second dielectric layer.2. The method of claim 1 , wherein an operating bandwidth of the antenna is 77 GHz to 81 GHz.3. The method of claim 2 , wherein a thickness of the dielectric feature is less than 20 μm claim 2 , a gain of the antenna is in a range of 7.1 dBi to 9.7 dBi claim 2 , and an efficiency of the antenna is in a range of 41% to 70%.4. The method of claim 2 , wherein a thickness of the dielectric feature is in a range of 20 μm to 40 μm claim 2 , a gain of the antenna is in a range of 9.7 dBi to 10.2 dBi claim 2 , and an efficiency of the antenna is in a range of 70% to 82%.5. The method of claim 2 , wherein a thickness of the dielectric feature is in a range of 40 μm to 100 μm claim 2 , a gain of the antenna is in a range of 10.2 dBi to 10.5 dBi claim 2 , and an efficiency of the antenna ...

PILL CASE ASSEMBLY AND PILL DISPENSER WITH PILL CASE ASSEMBLY

A pill case assembly for holding a number of pills includes a case body and a shake member. The case body receives the number of pills. The shake member is located beneath the case body and movable to shake the case body, for dispersing the number of pills. 1. A pill case assembly , comprising:a case body for holding a plurality of pills; anda shake member, wherein the shake member is driveable to engage the case body to shake the case body, for dispersing the plurality of pills.2. The pill case assembly of claim 1 , wherein the case body further comprises a bottom portion claim 1 , and the shake member is rotatable relative to the bottom portion to hit the bottom portion.3. The pill case assembly of claim 2 , wherein the bottom portion is flexible.4. The pill case assembly of claim 2 , wherein the shake member further comprises a cam claim 2 , and the cam is rotatable relative to the bottom portion to deform the bottom portion.5. The pill case assembly of claim 4 , wherein the shake member further comprises a motor connected to the cam claim 4 , and the motor rotates the cam.6. The pill case assembly of claim 1 , wherein the case body further comprises a bottom portion claim 1 , the bottom portion defines a plurality of slits claim 1 , the shake member comprises a plurality of inserting pieces claim 1 , and each of the plurality of inserting pieces are movable to insert into the case body through each of the plurality of slits.7. The pill case assembly of claim 6 , wherein the plurality of inserting pieces are parallel to each other.8. The pill case assembly of claim 6 , wherein a size of each of the plurality of is slightly greater than a size of each of the plurality of inserting pieces.9. The pill case assembly of claim 6 , wherein the plurality of slits are arranged in parallel.10. A pill dispenser claim 6 , comprising:a bottom base; and a case body rotatably secured to the bottom base and comprising a bottom portion supporting the plurality of pills; and', 'a ...

COPPER POST STRUCTURE FOR WAFER LEVEL CHIP SCALE PACKAGE

In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure. 1. A method , comprising:depositing a copper-containing material over the semiconductor substrate, thereby forming a copper-containing layer having a first thickness and a first width over the semiconductor substrate;forming a conductive bump having a second width over the copper-containing layer, wherein the second width is smaller than the first width; andetching an exposed portion of the copper-containing layer using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure comprising a top portion and a bottom portion adjoining the top portion, the top portion having a third thickness which is equal to the first thickness minus the second thickness, the bottom portion having the second thickness.2. The method of claim 1 , wherein the operation of etching the exposed portion of the copper-containing layer forms the second thickness ranging from 4 μm to 10 μm.3. The method of claim 1 , wherein the operation of etching the exposed portion of the copper-containing layer forms the third thickness ranging from 15 μm to 25 ...

THREE-DIMENSIONAL STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF

A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias. 1. A stacking structure , comprising:a first die, having a first metallization structure, wherein the first metallization structure includes first through die vias;a second die, having a second metallization structure, wherein the second die is stacked on the first die, and the second metallization structure includes second through die vias, wherein the first through die vias are bonded with the second through die vias, and critical dimensions of the first through die vias are different from critical dimensions of the second through die vias; anda third die and a fourth die, disposed over the first die and on the second die, wherein the third and fourth dies are disposed side-by-side and are bonded with the second through die vias.2. The structure of claim 1 , wherein the critical dimensions of the first through die vias are smaller than the critical dimensions of the second through die vias.3. The structure of claim 1 , wherein the critical dimensions of the first through die vias are larger than the critical dimensions of the second through die vias.4. The structure of claim 1 , further comprising a bonding film located between the first and second dies claim 1 , and a hybrid bonding interface is located between the bonding film and a semiconductor substrate of the first die.5. The structure of claim 1 , further ...

SEMICONDUCTOR PACKAGES AND MANUFACTURING MEHTODS THEREOF

A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure. 1. A semiconductor package , comprising:a semiconductor chip; anda redistribution layer structure arranged to form an antenna receiver structure over the semiconductor chip, wherein the antenna receiver structure comprises a plurality of sensing electrodes and a plurality of enhancement patterns located at different levels of the redistribution layer structure.2. The semiconductor package of claim 1 , wherein the redistribution layer structure is further arranged to form an antenna transmitter structure aside the antenna receiver structure.3. The semiconductor package of claim 2 , wherein the antenna transmitter structure surrounds the antenna receiver structure.4. The semiconductor package of claim 2 , wherein at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.5. The semiconductor package of claim 2 , wherein the antenna transmitter structure has a ring shape claim 2 , a bar shape claim 2 , a spiral shape claim 2 , a wave shape claim 2 , a meandering shape or a combination thereof.6. The semiconductor package of claim 2 , wherein from a top view claim 2 , the antenna transmitter structure is outside of a chip region of the semiconductor chip claim 2 , and the antenna receiver structure is within the chip region of the semiconductor chip.7. The semiconductor package of claim 1 , wherein the sensing electrodes are located at a higher level of the redistribution layer structure claim 1 ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region. The method further includes disposing a buffer layer at least covering the scribe line, disposing a dielectric layer including an opening over each chip region, and disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region. The method further includes forming a mold over the substrate, covering the buffer layer and cutting the substrate along the scribe line. Furthermore, the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold. 1. A method of manufacturing a semiconductor device , comprising:receiving a substrate, wherein the substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region;disposing a buffer layer at least covering the scribe line;disposing a dielectric layer including an opening over each chip region;disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region;forming a mold over the substrate and covering the buffer layer, wherein the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold; andcutting the substrate along the scribe line.2. The method of claim 1 , wherein each chip region includes a guard structure region and the buffer layer partially overlies the guard structure region.3. The method of claim 1 , wherein the disposing of a buffer layer is simultaneously occurring with the disposing of a dielectric layer.4. The method of claim 1 , wherein the dielectric layer is distant from the buffer layer by a gap of ...

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a first region and a second region on a post-passivation interconnect (PPI), the second region being an oxide or a nitride derivative of the first region; andannealing the first region and the second region on the PPI with a first temperature heat treatment;wherein the first region is surrounded by the second region.2. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the first region and the second region on the PPI further comprises forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer in contact with the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 4 , further comprising forming a flux layer in the first region of the PPI by positioning ...

CHIP PACKAGE WITH ANTENNA ELEMENT

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer. 1. A chip package , comprising:a semiconductor die having a conductive element;an antenna element over the semiconductor die;a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element;a protective layer surrounding the first conductive feature; anda second conductive feature over the first conductive feature, wherein a portion of the second conductive feature is between the first conductive feature and the protective layer.2. The chip package as claimed in claim 1 , wherein compositions of the second conductive feature and the antenna element are the same.3. The chip package as claimed in claim 1 , wherein the protective layer is over the semiconductor die.4. The chip package as claimed in claim 1 , wherein the antenna element is over the protective layer.5. The chip package as claimed in claim 1 , further comprising a second semiconductor die covered by the protective layer.6. The chip package as claimed in claim 1 , further comprising a shielding element between the semiconductor die and the antenna element.7. The chip package as claimed in claim 6 , wherein the shielding element is electrically isolated from the antenna element.8. The chip package as claimed in claim 1 , wherein the antenna element is configured to receive or transmit an electromagnetic signal ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a die including a first surface, a recess extended from an aperture disposed on the first surface and including a sidewall disposed within the die, and a polymeric member configured for filling and sealing the recess and including a first outer surface and a second outer surface, wherein the first outer surface is interfaced with the sidewall of the recess. 1. A semiconductor structure , comprising:a die including a first surface;a recess extended from an aperture disposed on the first surface and including a sidewall disposed within the die; anda polymeric member configured for filling and sealing the recess and including a first outer surface and a second outer surface;wherein the first outer surface is interfaced with the sidewall of the recess.2. The semiconductor structure of claim 1 , wherein the polymeric member includes an epoxy resin claim 1 , a dye claim 1 , a fluorescent dye claim 1 , a colored dye claim 1 , benzoxazol derivatives or sulfonated diaminostilbone derivatives.3. The semiconductor structure of claim 1 , wherein the polymeric member is visible under an ultra violet (UV) light or an electromagnetic radiation with a wavelength of about 10 nm to about 400 nm.4. The semiconductor structure of claim 1 , wherein the second outer surface of the polymeric member or the aperture of the recess has a length of less than about 1 um.5. The semiconductor structure of claim 1 , wherein the recess is laterally extended from the first surface of the die.6. The semiconductor structure of claim 1 , wherein the recess and the polymeric member are in a substantially same dimension and shape.7. A method of manufacturing a semiconductor structure claim 1 , comprising:providing a die including a first surface with a recess extended from an aperture disposed on the first surface;disposing a polymeric material over the first surface;flowing the polymeric material into the recess; andforming a polymeric member including a first outer ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor structure. The semiconductor structure includes a circuit region, a seal ring region and an assembly isolation region. The circuit region includes a first conductive layer. The seal ring region includes a second conductive layer. The assembly isolation region is between the circuit region and the seal ring region. The first conductive layer and the second conductive layer respectively include a portion extending into the assembly isolation region thereby forming an electric component in the assembly isolation region. 1. A semiconductor structure , comprising:a circuit region, comprising a device having a gate layer;a seal ring region, comprising a seal ring structure having a first conductive layer; andan assembly isolation region between the circuit region and the seal ring regionwherein a portion of the gate layer extends into the assembly isolation region and coupling with a portion of the first conductive layer, the portion of the gate layer vertically overlaps with the portion of the first conductive layer in a plan view.2. The semiconductor structure of claim 1 , further comprising a first dielectric between the portion of the first conductive layer and the portion of the first conductive layer.3. The semiconductor structure of claim 2 , wherein the first dielectric claim 2 , the portion of the first conductive layer claim 2 , and the portion of the first conductive layer form a capacitor.4. The semiconductor structure of claim 2 , wherein the gate layer further comprising a second dielectric different from the first dielectric.5. The semiconductor structure of claim 1 , further comprising a second conductive layer in the circuit region and electrically connected to the gate layer.6. The semiconductor structure of claim 1 , wherein the portion of the first conductive layer is above the portion of the gate layer in the assembly isolation region.7. The semiconductor structure of claim 1 , wherein the gate layer ...

Integrated Devices in Semiconductor Packages and Methods of Forming Same

An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna. 18-. (canceled)9. A method of manufacturing a package structure , the method comprising:encapsulating an integrated circuit die in an encapsulant; a ground element;', 'a feed line; and', 'a radiating element electrically coupled to the ground element and the feed line; and, 'forming a conductive via in the encapsulant and electrically connecting the integrated circuit die to a patch antenna, wherein the patch antenna comprisesforming a dielectric feature physically separating the ground element from the integrated circuit die, wherein a thickness of the dielectric feature is selected in accordance with at least one of: an operating bandwidth of the patch antenna, a k-value of the dielectric feature, an area of the patch antenna, and an efficiency of the patch antenna.10. The method of claim 9 , wherein the dielectric feature comprises a first dielectric layer and a second dielectric layer claim 9 , wherein the first dielectric layer comprises a different material than the second dielectric layer.11. The method of claim 10 , wherein the dielectric feature further comprises a third dielectric layer comprising a different material than at least one of the first dielectric layer and the second dielectric layer.12. The method of claim 9 , wherein sidewalls of the dielectric feature are co-terminus with sidewalls of the integrated circuit die.13. The method of claim 9 , wherein the dielectric feature has a different width than the integrated circuit die.14. The method of further comprising forming a radiating antenna extending through the encapsulant and electrically ...

PACKAGE STRUCTURE, CHIP STRUCTURE AND METHOD OF FABRICATING THE SAME

A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer. 1. A structure , comprising:a first chip comprising a first substrate, a gap fill layer disposed on the first substrate, and first conductive vias embedded in the gap fill layer, wherein sidewalls of the gap fill layer is aligned with sidewalls of the first substrate;a second chip embedded in the gap fill layer and surrounded by first conductive vias, wherein the second chip comprises a second substrate and second conductive vias located on the second substrate;an insulating encapsulant laterally surrounding the first chip and physically separated from the second chip by the gap fill layer;through insulator vias embedded in the insulating encapsulant and surrounding the first chip and the second chip; anda redistribution layer disposed on the insulating encapsulant and electrically connected to the first conductive vias, the second conductive vias and the through insulator vias.2. The structure according to claim 1 , further comprising a ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes a die, an encapsulant, and a first redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes a ground plane within the die. The encapsulant encapsulates the die. The first redistribution structure is over the active surface of the die. The first redistribution structure includes an antenna pattern electrically coupled with the ground plane. The antenna pattern is electrically connected to the die. 1. A package structure , comprising:a die having an active surface and a rear surface opposite to the active surface, wherein the die comprises a ground plane within the die;an encapsulant encapsulating the die; anda first redistribution structure over the active surface of the die, wherein the first redistribution structure comprises an antenna pattern electrically coupled with the ground plane, and the antenna pattern is electrically connected to the die.2. The package structure according to claim 1 , further comprising a plurality of conductive structures surrounding the die claim 1 , wherein the plurality of conductive structures penetrates through the encapsulant.3. The package structure according to claim 1 , further comprising:a second redistribution structure over the rear surface of the die; anda plurality of conductive terminals over the second redistribution structure.4. The package structure according to claim 1 , wherein the die comprises:a semiconductor substrate;an interconnection structure on the semiconductor substrate, wherein the interconnection structure comprises the ground plane;a plurality of conductive pads over and electrically connected to portions of the interconnection structure; anda plurality of conductive posts standing on the plurality of conductive pads, wherein the plurality of conductive posts are electrically connected to the first redistribution structure.5. The package structure according to claim 1 , wherein the die comprises:a semiconductor ...

PACKAGE STRUCTURE

A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die. 1. A package structure , comprising:a first semiconductor die, encapsulated in a first insulating encapsulation;a first antenna and a second antenna, electrically coupled to the first semiconductor die, wherein the first antenna and the second antenna are arranged independently next to or atop of the first semiconductor die, and wherein the first antenna generates an electromagnetic wave propagating along a first direction, the second antenna generates an electromagnetic wave propagating along a second direction, and the first direction is different from the second direction; anda first metallic layer, located between the first antenna and the second antenna and over the first semiconductor die, wherein a portion of the first metallic layer is electrically connected to the first semiconductor die and another portion of the first metallic layer is electrically isolated from the first semiconductor die.2. The package structure of claim 1 , further comprising:a second insulating encapsulation, encapsulating the first antenna;a third insulating encapsulation, encapsulating the second antenna, wherein the second insulating encapsulation is located between the first insulating encapsulation and the third insulating encapsulation;a ...

PACKAGE STRUCTURE, ELECTRONIC DEVICE AND METHOD OF FABRICATING PACKAGE STRUCTURE

In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna. 1. A method , comprising:providing a reconstructed wafer comprising a plurality of INFO package units arranged in array, each of the INFO package units comprising an RFIC chip and an antenna electrically connected to the RFIC chip;forming a microwave director array comprising a plurality of microwave directors over the reconstructed wafer, each of the microwave directors being located over one of the INFO package units respectively; andperforming a singulation process to cut the reconstructed wafer and the microwave director array on the reconstructed wafer to obtain a plurality of singulated package structures.2. The method of claim 1 , wherein the microwave directors in the microwave director array are connected to one another before performing the singulation process.3. The method of claim 1 , wherein forming the microwave director array over the reconstructed wafer comprises:forming a photosensitive dielectric material layer over the reconstructed wafer; andpartially removing the photosensitive dielectric material layer by a photolithography process to form the microwave directors over the reconstructed wafer.4. The method of claim 3 , wherein partially removing the photosensitive dielectric material layer by the photolithography process ...

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is provided. Through vias penetrating through the first molding compound are disposed around the die. The reflector pattern is disposed on the die and the through vias. The antenna structure is disposed on the reflector pattern and electrically connected with the reflector pattern and the die. The antenna structure is wrapped by a second molding compound disposed on the reflector pattern. 1. A package structure , comprising:a die;a first molding compound surrounding the die;through vias, disposed beside and around the die and penetrating through the first molding compound;a reflector pattern disposed on the die and the through vias, wherein the reflector pattern is electrically connected to the through vias;an antenna structure, disposed on the reflector pattern and electrically connected with the reflector pattern and the die; anda second molding compound, disposed on the reflector pattern and surrounding the antenna structure.2. The package structure according to claim 1 , wherein the die comprises at least one wireless and radio frequency chip.3. The package structure according to claim 1 , wherein the antenna structure comprises antenna patterns and through interlayer vias connected to the antenna patterns claim 1 , the antenna patterns are metal blocks arranged as an array claim 1 , and pairs of the metal blocks and the through interlayer vias connected to the metal blocks constitute dipole antennas.4. The package structure according to claim 1 , wherein the reflector pattern includes sub-patterns arranged as an array and the antenna structure is electrically connected to the reflector pattern.5. The package structure according to claim 4 , wherein the sub-patterns are shaped as split ring resonators.6. The package structure according to claim 1 , wherein top surfaces of the antenna patterns are exposed from ...

Semiconductor packages and manufacturing mehtods thereof

A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip. 1. A semiconductor device , comprising: a semiconductor chip;', 'an encapsulation enclosing the semiconductor chip; and', 'a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip; and, 'a chip package, comprising an antenna pattern electrically coupled to the chip package; and', 'an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a dielectric casing disposed on the chip package and a ceramic protrusion accommodated in the dielectric casing and corresponding to the semiconductor chip, the ceramic protrusion is in contact with the redistribution structure and thermally dissipates a heat generated from the semiconductor chip, and the ceramic protrusion is surrounded by the antenna pattern and protruded from the dielectric casing., 'an antenna package disposed on the chip package, comprising2. The semiconductor device of claim 1 , wherein the antenna pattern comprises a conductive block claim 1 , and a corner of the conductive block faces a sidewall of the ceramic protrusion in a plan view.3. The semiconductor device of claim 1 , wherein the antenna pattern comprises a plurality of conductive blocks claim 1 , and a ...

CHIP PACKAGE WITH ANTENNA ELEMENT

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die. 1. A chip package , comprising:a semiconductor die having a conductive element;a first protective layer surrounding the semiconductor die;a second protective layer over the semiconductor die and the first protective layer;a conductive feature surrounded by the second protective layer;a conductive material over the conductive feature, wherein a portion of the conductive material is between the conductive feature and the second protective layer; andan antenna element over the second protective layer, wherein the antenna element is electrically connected to the conductive material and the conductive feature.2. The chip package as claimed in claim 1 , wherein the conductive material and the antenna element are made of a same material.3. The chip package as claimed in claim 1 , further comprising a second conductive feature in the first protective layer claim 1 , wherein the antenna element is electrically connected to the conductive element of the semiconductor die through the conductive feature and the second conductive feature.4. The chip package as claimed in claim 3 , wherein a first direct projection of the first conductive feature on a top surface of the second protective layer does not overlap a second direct projection of the second conductive feature on the top surface of the second projective layer.5. The chip package as claimed in claim 1 , wherein the second protective layer has a lower dielectric constant than that of the first protective layer.6. The chip ...

SEMICONDUCTOR DEVICE HAVING TRENCH ADJACENT TO RECEIVING AREA AND METHOD OF FORMING THE SAME

In some embodiments in accordance with the present disclosure, a semiconductor device including a semiconductor substrate is received. An interconnect structure is provided over the semiconductor substrate, and a passivation is provided over the interconnect structure. The passivation includes an opening such that a portion of the interconnect structure is exposed. Moreover, a dielectric is provided over the passivation, and a post-passivation interconnect (PPI) is provided over the dielectric. The PPI is configured to connect with the exposed portion of the interconnect structure through an opening in the dielectric. Furthermore, the PPI includes a receiving area for receiving a conductor, and a trench adjacent to the receiving area. In certain embodiments, the receiving area is defined by the trench. 1. A semiconductor device , comprising:a semiconductor substrate;an interconnect structure over the semiconductor substrate,a passivation over the interconnect structure and comprising an opening to expose a portion of the interconnect structure;a dielectric over the passivation; anda post-passivation interconnect (PPI) over the dielectric, and the PPI configured to connect with the exposed portion of the interconnect structure through an opening in the dielectric, wherein the PPI comprises a receiving area configured to receive a conductor,wherein the PPI includes a trench adjacent to the receiving area.2. The semiconductor device according to claim 1 , wherein the PPI includes more than one trenches adjacent to the receiving area.3. The semiconductor device according to claim 2 , wherein the more than one trenches are configured at opposite sides of the receiving area.4. The semiconductor device according to claim 2 , wherein a distance between the more than one trenches is less than a width of the conductor.5. The semiconductor device according to claim 1 , wherein the PPI includes an upper surface claim 1 , and a portion of the upper surface in proximity with the ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate including a front side, a conductive bump disposed over the front side, and an opaque molding disposed over the front side and around a periphery portion of an outer surface of the conductive bump, wherein the opaque molding includes a recessed portion disposed above a portion of the front side adjacent to a corner of the substrate and extended through the opaque molding to expose the portion of the front side and an alignment feature disposed within the portion of the front side. 1. A semiconductor structure , comprising:a substrate including a front side;a conductive bump disposed over the front side; andan opaque molding disposed over the front side and exposing a portion of an outer surface of the conductive bump,wherein the opaque molding includes a recessed portion disposed above a portion of the front side adjacent to a corner of the substrate and extended through the opaque molding to expose the portion of the front side and an alignment feature disposed within the portion of the front side.2. The semiconductor structure of claim 1 , wherein the recessed portion of the opaque molding exposes the front side.3. The semiconductor structure of claim 1 , wherein the recessed portion of the opaque molding includes a sidewall substantially orthogonal to the front side.4. The semiconductor structure of claim 1 , wherein the alignment feature is disposed at a corner of the front side and exposed from the opaque molding.5. The semiconductor structure of claim 1 , wherein the recessed portion has a length of about 8 mm to 15 mm and a width of about 5 mm to about 10 mm.6. The semiconductor structure of claim 1 , wherein the opaque molding includes an epoxy or is in black color.7. The semiconductor structure of claim 1 , wherein the portion of the front side exposed from the opaque molding is in a triangular claim 1 , a quadrilateral or polygonal shape.8. A semiconductor structure claim 1 , comprising:a substrate including a ...

SENSOR PACKAGES AND MANUFACTURING MEHTODS THEREOF

Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip. 1. A sensor package , comprising:a semiconductor chip having a sensing surface; anda redistribution layer structure arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.2. The sensor package of claim 1 , wherein the antenna transmitter structure surrounds the antenna receiver structure.3. The sensor package of claim 1 , wherein the transmitter structure has a ring shape claim 1 , a bar shape claim 1 , a spiral shape claim 1 , a wave shape claim 1 , a meandering shape or a combination thereof.4. The sensor package of claim 1 , wherein the antenna receiver structure has a plurality of first patterns over the sensing surface of the semiconductor chip.5. The sensor package of claim 4 , wherein each of the plurality of first patterns has an island shape claim 4 , a snake shape claim 4 , a bar shape claim 4 , a fishbone shape claim 4 , a fence shape claim 4 , a grid shape claim 4 , a ring shape or a combination thereof.6. The sensor package of claim 4 , wherein the antenna receiver structure further has a plurality of second patterns over the plurality of first patterns.7. The sensor package of claim 6 , wherein the plurality of second patterns are aligned with the plurality of first patterns.8. The sensor package of claim 4 , wherein the antenna receiver structure further has a plurality of third patterns over the plurality of second patterns claim 4 , the plurality of third patterns are aligned with the plurality of second patterns claim 4 , and the plurality ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.

SEMICONDUCTOR DEVICE HAVING ANTENNA AND MANUFACTURING METHOD THEREOF

A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. 1. A semiconductor device , comprising:a chip package;a dielectric structure disposed on the chip package and comprising a cavity and a vent in communication with the cavity; anda first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.2. The semiconductor device according to claim 1 , further comprising:a second antenna pattern disposed inside the cavity of the dielectric structure, wherein the chip package is electrically coupled to the second antenna pattern.3. The semiconductor device according to claim 1 , wherein the dielectric structure comprises a first layer and a second layer between the chip package and the first layer claim 1 , the second layer comprises the cavity claim 1 , and the first layer covers the cavity.4. The semiconductor device according to claim 3 , wherein the first antenna pattern is disposed on the first layer and located outside the cavity.5. The semiconductor device according to claim 3 , wherein the vent is at the first layer or at the second layer.6. The semiconductor device according to claim 1 , wherein the chip package comprises:a chip;an encapsulant encapsulating the chip; anda redistribution layer disposed on the chip and the encapsulant and electrically connected to the chip.7. The semiconductor device according to claim 6 , wherein the chip package ...

Integrated fan-out package and manufacturing method thereof

A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a substrate and a bump. The substrate includes a first surface and a second surface. A notch is at the second surface and at a sidewall of the substrate. A depth of the notch is smaller than about half the thickness of the substrate. The bump is disposed on the first surface of the substrate. 1. A method of manufacturing a semiconductor device , comprising:receiving a wafer including a substrate, wherein the substrate includes a first surface, and a plurality of die areas are formed above the substrate;cutting the first surface to form a first recess in the substrate, wherein the first recess comprises a first depth and the first recess is located between at least two of the plurality of die areas; andsingulating the wafer to form a plurality of dies by further cutting the substrate from a bottom surface of the first recess with a cut width smaller than a width of the bottom surface of the first recess, thereby forming a second recess with a second depth, wherein the second depth is substantially greater than or equal to the first depth.2. The method of claim 1 , further comprising disposing a plurality of bumps above a second surface of the substrate claim 1 , wherein the plurality of bumps are electrically connected to a post-passivation interconnect (PPI) of the plurality of the dies.3. The method of claim 2 , further comprising disposing a molding on the second surface of the substrate and between the plurality of bumps.4. The method of claim 1 , further comprising flipping over the wafer prior to the cutting of the first surface.5. The method of claim 1 , further comprising changing a first blade into a second blade prior to performing singulation of the plurality of dies.6. The method of claim 5 , wherein the cutting of the first recess is performed by the first blade claim 5 , and the cutting of the second recess is performed by the second blade.7. The method of claim 5 , wherein a width of the second blade is smaller than a ...

Integrated Devices in Semiconductor Packages and Methods of Forming Same

An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna. 1. A package comprising:an integrated circuit die encapsulated in an encapsulant, wherein the encapsulant is external to the integrated circuit die;a device over the integrated circuit die, wherein the device overlaps the integrated circuit die in a top-down view, and wherein the device comprises a ground element and a signal line; anda dielectric feature disposed between the integrated circuit die and the device, wherein a thickness of the dielectric feature is in accordance with an operating bandwidth of the device.2. The package of claim 1 , wherein the thickness of the dielectric feature is further in accordance with a k-value of the dielectric feature claim 1 , an area of the device claim 1 , an efficiency of the device claim 1 , or a combination thereof.3. The package of claim 2 , wherein:the thickness of the dielectric feature is at least 100 μm, the operating bandwidth of the device is 60 GHz and the k-value of the dielectric feature is at least 3;the thickness of the dielectric feature is at least 30 μm, the operating bandwidth of the device is 60 GHz and the k-value of the dielectric feature is less than 3;the thickness of the dielectric feature is at least 50 μm, the operating bandwidth of the device is 77 GHz and the k-value of the dielectric feature is at least 3; orthe thickness of the dielectric feature is at least 15 μm, the operating bandwidth of the device is 77 GHz and the k-value of the dielectric feature is less than 3.4. The package of claim 1 , wherein the device is a patch antenna claim 1 , and wherein the patch antenna comprises a ...

PACKAGE STRUCTURE, PACKAGE-ON-PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts. 1. A package structure , comprising:a first semiconductor die, having a plurality of first conductive posts and a first protection layer laterally surrounding the plurality of first conductive posts;at least one second semiconductor die, embedded in the first protection layer and surrounded by the plurality of first conductive posts of the first semiconductor die, wherein the at least one second semiconductor die comprises a plurality of second conductive posts;an insulating encapsulant encapsulating the first semiconductor die and the at least one second semiconductor die; anda redistribution layer, disposed on the insulating encapsulant and connected with the plurality of first conductive posts and the plurality of second conductive posts, wherein the first semiconductor die is electrically connected with the at least one second semiconductor die through the plurality of first conductive posts, the redistribution layer and the plurality of second conductive posts.2. The package structure according to claim 1 , wherein the at least one second ...

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a pad and an alignment feature disposed over the substrate, a passivation disposed over the substrate and a periphery of the pad, a post passivation interconnect (PPI) including a via portion disposed on the pad and an elongated portion receiving a conductive bump to electrically connect the pad with the conductive bump, a polymer covering the PPI, and a molding material disposed over the polymer and around the conductive bump, wherein the molding material comprises a first portion orthogonally aligned with the alignment feature and adjacent to an edge of the semiconductor device and a second portion distal to the edge of the semiconductor device, a thickness of the first portion is substantially smaller than a thickness of the second portion, thereby the alignment feature is visible through the molding material under a predetermined radiation.

Method of manufacturing integrated fan-out package

A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

Integrated Circuit Package and Method

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar. 1. A device comprising:a bottom integrated circuit die having a first front side and a first back side;a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs);a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; anda through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.2. The device of claim 1 , wherein the second back side is bonded to the first front side by an adhesive.3. The device of claim 1 , wherein the top integrated circuit die comprises a semiconductor substrate claim 1 , and the bottom integrated circuit die comprises a first bonding layer at the first front side claim 1 , the semiconductor substrate being directly bonded to the first bonding layer.4. The device of claim 1 , wherein the bottom ...

SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME

A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device. 1. A semiconductor structure , comprising:a first semiconductor device and a second semiconductor device, wherein the first semiconductor device is bonded on the second semiconductor device;a connection device, bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device comprises a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device; anda redistribution circuit structure, located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device,wherein the redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.2. The semiconductor structure of claim 1 , wherein the connection device and the first semiconductor ...

SEMICONDUCTOR STRUCTURE AND METHOD MANUFACTURING THE SAME

A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die. 1. A semiconductor structure , comprising: a first semiconductor die, comprising a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface; and', 'a second semiconductor die, over the first semiconductor die, comprising a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface, and being bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction,', 'wherein along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die., 'a stacked structure, comprising2. The semiconductor structure of claim 1 , wherein the first semiconductor die further comprises a plurality of first conductive vias penetrating through the first semiconductor substrate claim 1 , and the second semiconductor die further comprises a plurality of second conductive vias penetrating through the second semiconductor substrate claim 1 , ...

SEMICONDUCTOR PACKAGES AND METHOD OF FORMING THE SAME

Semiconductor packages and method of forming the same are disclosed. One of the semiconductor packages includes a first die, a second die, a through via and a dielectric encapsulation. The second die is bonded to the first die. The through via is disposed aside the second die and electrically connected to the first die. The through via includes a step-shaped sidewall. The dielectric encapsulation encapsulates the second die and the through via. 1. A semiconductor package , comprising:a first die;a second die bonded to the first die;a through via, disposed aside the second die and electrically connected to the first die, wherein the through via comprises a step-shaped sidewall; anda dielectric encapsulation, encapsulating the second die and the through via.2. The semiconductor package of claim 1 , wherein the through via comprises a first portion having a first width and a second portion having a second width different from the first width claim 1 , and the second portion is disposed between the first portion and the first die.3. The semiconductor package of claim 2 , wherein the first portion comprises a first seed layer and a first conductive layer claim 2 , the second portion comprises a second seed layer and a second conductive layer claim 2 , the first seed layer is disposed aside an interface between the first conductive layer and the second conductive layer claim 2 , and the second seed layer is disposed between the second conductive layer and the dielectric encapsulation and between the second conductive layer and the first die.4. The semiconductor package of claim 3 , wherein the first seed layer is physically separated from the second seed layer.5. The semiconductor package of claim 3 , wherein the first seed layer is integrally formed with the second seed layer.6. The semiconductor package of claim 1 , further comprises a plurality of first vias and a plurality of second vias aside the through via in the dielectric encapsulation claim 1 , wherein the first ...

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip. 1. A package , comprising: a first chip;', 'a second chip and a third chip disposed side by side on the first chip, wherein the second chip and the third chip are hybrid bonded to the first chip; and', 'a fourth chip fusion bonded to at least one of the second chip and the third chip., 'an integrated circuit, comprising2. The package of claim 1 , wherein the fourth chip is stacked on and fusion bonded to the third chip claim 1 , and a sum of a thickness of the third chip and a thickness of the fourth chip is substantially equal to a thickness of the second chip.3. The package of claim 1 , wherein the fourth chip is stacked on and fusion bonded to both of the second chip and the third chip claim 1 , and a sum of a thickness of the second chip and a thickness of the fourth chip is substantially equal to a sum of a thickness of the third chip and the thickness of the fourth chip.4. The package of claim 1 , wherein the fourth chip is a dummy chip.5. The package of claim 1 , wherein the first chip further comprises a plurality of through semiconductor vias (TSV) embedded therein.6. The package of claim 1 , wherein the integrated circuit further comprises an insulating encapsulant laterally encapsulating the second chip and the third chip.7. The package of claim 6 , wherein the insulating encapsulant further laterally encapsulates the fourth chip.8. The package of claim 6 , wherein the integrated circuit further comprises a plurality of through insulating vias (TIV) penetrating through the insulating encapsulant.9. The package of claim 1 , further comprising:a plurality of conductive structures ...

STACKING STRUCTURE, PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units. 1. A package structure , comprising:a plurality of stacked die units stacked on top of one another, wherein each of the plurality of stacked die units comprises:a first semiconductor die having a plurality of first bonding pads;a first bonding chip stacked on the first semiconductor die and having a plurality of first bonding structures, wherein the plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding; andan insulating encapsulant encapsulating the plurality of stacked die units.2. The package structure according to claim 1 , further comprising a semiconductor substrate claim 1 , wherein the plurality of stacked die units is attached to the semiconductor substrate through an adhesive layer.3. The package structure according to claim 1 , further comprising a redistribution layer wherein the plurality of stacked die units is attached to the redistribution layer through an adhesive layer.4. The package structure according to claim 1 , further comprising a plurality of conductive wires electrically connected to at least one of the first bonding pads in each of the plurality of stacked die units claim 1 , wherein the insulating encapsulant further encapsulates the conductive wires.5. The package structure according to claim 1 , further comprising a second bonding chip stacked on the ...

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a redistribution structure, an integrated circuit, an encapsulant, and conductive structures. The integrated circuit is disposed on the redistribution structure and includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate that extends continuously throughout the first chip. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate that extends continuously throughout the fourth chip. Sidewalls of the first chip are aligned with sidewalls of the fourth chip. The encapsulant laterally encapsulates the integrated circuit. The conductive structures penetrate through the encapsulant. The second package structure is electrically connected to the redistribution structure through the conductive structures. 1. A package , comprising: a redistribution structure;', a first chip comprising a semiconductor substrate that extends continuously throughout the first chip;', 'a second chip and a third chip disposed side by side on the first chip; and', 'a fourth chip disposed over the first chip, wherein the fourth chip comprises a semiconductor substrate that extends continuously throughout the fourth chip, and sidewalls of the first chip are aligned with sidewalls of the fourth chip;, 'an integrated circuit disposed on the redistribution structure, comprising, 'an encapsulant laterally encapsulating the integrated circuit; and', 'a plurality of conductive structures penetrating through the encapsulant; and, 'a first package structure, comprisinga second package structure stacked on the first package structure, wherein the second package structure is electrically connected to the redistribution structure through the conductive structures.2. The package of claim 1 , ...

PACKAGE STRUCTURES

A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.

SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS THEREOF

Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

Circuit board structure and fabrication method of the same

A circuit board structure and a fabrication method of the same are disclosed according to the present invention. The circuit board structure includes: a carrier board with at least one surface formed with a circuit layer having electrically connecting pads; a first solder mask formed on the carrier board and the circuit layer and formed with first openings for exposing the electrically connecting pads; and a second solder mask formed on the first solder mask and formed with second openings for exposing the first openings and the electrically connecting pads. The first solder mask is made of a high-insulation photosensitive material characterized by presence or absence of impurities, such as microparticles, to have enhanced fluidity for being filled in the circuit layer, thereby preventing metal ions migration and subsequent metal hypha electricity discharge which might otherwise affect electrical performance, therefore the present invention is applicable to fine circuit fabrication.

Circuit board structure

A circuit board structure and a fabrication method of the same are disclosed according to the present invention. The circuit board structure includes: a carrier board with at least one surface formed with a circuit layer having electrically connecting pads; a first solder mask formed on the carrier board and the circuit layer and formed with first openings for exposing the electrically connecting pads; and a second solder mask formed on the first solder mask and formed with second openings for exposing the first openings and the electrically connecting pads. The first solder mask is made of a high-insulation photosensitive material characterized by presence or absence of impurities, such as microparticles, to have enhanced fluidity for being filled in the circuit layer, thereby preventing metal ions migration and subsequent metal hypha electricity discharge which might otherwise affect electrical performance, therefore the present invention is applicable to fine circuit fabrication.

Conductive structures for electrically conductive pads of circuit board and fabrication method thereof

Conductive structures for electrically conductive pads of a circuit board and fabrication method thereof are proposed. The fabrication method includes: providing a circuit board with a plurality of first, second and third electrically conductive pads; forming first and second conductive layers on the circuit board; forming first and second resist layers respectively on the first and second conductive layers, the resist layers having a plurality of openings for exposing the conductive layers on the pads; forming a metal layer in the openings of the first and second resist layers; and forming a first connecting layer on the metal layer; forming third and fourth resist layers on the first and second resist layers respectively, the third resist layer having a plurality of openings for exposing the first connecting layer on the metal layer on the second electrically.

Circuit board and fabrication method thereof

Package substrate having double-sided circuits and fabrication method thereof

Package and method of fabricating the same

Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.

Method for fabricating circuit board with conductive structure

Circuit board structure and method for manufacturing the same

A circuit board disclosed in the present invention includes a core board on which a first circuit layer is placed, wherein the first circuit layer has a plurality of conductive pads; and at least one built-up structure covering the surface of the circuit board, which comprises a dielectric layer, a second circuit layer, and a plurality of conductive vias without being surrounded by annular metal rings. The conductive vias are conducted with the conductive pads of the first circuit layer and the second circuit layer. Besides, the surface of the second circuit layer is in the same height as the surface of the dielectric layer. Also, the present invention provides a method for manufacturing the above-mentioned circuit board structure. Therefore, a circuit board having fine circuits can be formed, and the shape of the circuit can be ensured efficiently. Moreover, electric performances of the circuit board can be improved.

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.

Electrically connecting terminal structure of circuit board and manufacturing method thereof

An electrically connecting terminal structure of a circuit board and a manufacturing method thereof are disclosed. The method includes: providing a circuit board defined with first and second predetermined areas; forming the first electrically connecting pad in the first predetermined area and the second electrically connecting pad in a portion of the second predetermined area; forming an insulated protecting layer on the circuit board, forming openings on the insulated protecting layer for exposing the first and second electrically connecting pads and a pad-uncovered portion of the second predetermined area; forming a conductive layer on the insulated protecting layer and forming openings of the insulated protecting layer; forming a resist on the conductive layer, forming openings on the resist above the openings of the insulated protecting layer; and forming first and second metals in the openings above the first and second electrically connecting pads and the pad-uncovered portion of the second predetermined area.

3D package with through substrate vias

A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.

Method for fabricating conductive connection structure of circuit board