Transport safety system

SAFETY SYSTEM CHALLENGE-AND-RESPONSE USING MODIFIED WATCHDOG TIMER

Some embodiments of the present disclosure relate to a watchdog timer having an enhanced functionality that enables the watchdog timer to monitor a process flow of the microprocessor on a task-by-task basis that enables a simple output signal to be used to determine if the watchdog timer is malfunctioning. The watchdog timer has a state machine that increments a state variable from an initial value over a watchdog period. A deterministic service request, received from a microprocessor, controls operation of the watchdog timer. The deterministic service request has an indicator of a monitoring operation to be performed, a password, and an estimated state variable. A comparison element determines if the microprocessor is operating properly based upon a comparison of the received password to an expected password and the received estimated state variable to an actual state variable. 1. A watchdog timer , comprising:a state machine configured to deterministically modify a state variable over a watchdog period;a microprocessor configured provide a deterministic service request to the watchdog timer to control operation of the watchdog timer, wherein the deterministic service request comprises an indicator of a monitoring operation to be performed, a password, and an estimated state variable; anda comparison element configured to determine if the microprocessor is operating properly based upon a comparison of the password to an expected password and the estimated state variable to an actual state variable.2. The watchdog timer of claim 1 , wherein the comparison element is configured to determine that the microprocessor is operating properly if the password is equal to the expected password and if the estimated state variable is within a tolerance value of the actual state variable.3. The watchdog timer of claim 2 ,wherein the indicator comprises a time check command;wherein the watchdog timer is configured to take no action if the initial value if the password is equal to ...

Methods and systems for measuring I/O signals

Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

SAFETY HYPERVISOR FUNCTION

The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module. 1. A system for a safety hypervisor function for accessing a bus in a computer processing system , the system comprising:a module for accessing a system memory; anda memory unit for storing a safety code, wherein the module allocates the safety code to a processing transaction, and wherein the safety code is visible upon access of the bus by the module.2. The system of claim 1 , wherein the module is a Computer Processing Unit (CPU).3. The system of claim 1 , wherein the module is a Direct Memory Access (DMA).4. The system of claim 1 , further comprising a Processor Status Word (PSW) for storing the safety code for the module.5. The system of claim 4 , wherein the safety code is allocated to a task using the PSW.6. The system of claim 3 , further comprising a configuration register for storing the safety code for the DMA.7. The system of claim 6 , wherein the safety code is allocated to a DMA channel transaction.8. A system for a safety hypervisor function claim 6 , the system comprising:a Computer Processing Unit (CPU) Memory Protection Unit (CPU MPU) for protecting access to a CPU and local memories; a Bus Memory Protection Unit (Bus MPU) for protecting access to a processor bus; anda Register Memory Protection Unit (Register MPU) for protecting access to one or more peripherals in the system, wherein a safety privilege level is used by ...

Self-propelled baggage dolly, baggage handling system, baggage handling facility, and related apparatus and method

A self-propelled dolly comprises a cargo portion 104 configured to hold baggage or cargo, a drive system 108 for driving the self-propelled dolly 100, a controller 114 configured to control the drive system in response to control signals and a processor 116 configured to provide control signals to the controller. The dolly may process position, orientation, image speed and direction data and may comprise a sensing system which uses camera, radar, LIDAR, gyroscopes, magnetic field sensors or global positioning satellite systems. The processor may operate in a plurality of autonomy modes, such as SAE level 3,4 or 5 and may respond to a trigger event to provide an output for an operator. The triggers may be geospatial, temporal, visual or electronic. Additionally, the dolly may comprise a weighing system configured to weight the cargo present within the cargo portion and may calculate a weight distribution. The dolly may be used with aircraft in an airport and the like.

Transport safety system

A transport safety system (400) for use in airports comprising a status monitor (300) for an airside dolly (200) used to improve airport safety. The status monitor (300) comprises a sensor (303) configured to sense a safety variable of the airside dolly and an output (301) in communication with the sensor (303). The output (303) is configured to provide a status signal in dependence on the sensed safety variable of the airside dolly (200).

Self-propelled baggage dolly, baggage handling system, baggage handling facility, and related apparatus and methods

Vehicle front end

Self-propelled dolly, baggage handling system, baggage handling facility

The present invention relates to self-propelled airside dollies (100), and particularly but not exclusively to airside baggage dollies and airside cargo dollies, and autonomous airside dollies. The self- propelled airside dolly comprises a cargo portion (104) configured to hold baggage or cargo, a drive system (108) for driving the self- propelled airside dolly (100), a controller (114) configured to control the drive system (108) in response to control signals and a processor (116) configured to provide the control signals to the controller (114).

Transport safety system

A status monitor 300 for an airside dolly 200 used to improve airport safety. The status monitor comprises a sensor 303 configured to sense a safety variable of the airside dolly and an output (301, see fig.7) in communication with the sensor. The output (303) is configured to provide a status signal in dependence on the sensed safety variable of the airside dolly. The status monitor may be configured to trigger a warning and may comprise a clamp sensor to sense whether a container is correctly clamped to the airside dolly or sense the weight or weight distribution of the load. Additionally, the status monitor may comprise a proximity sensor for detecting the presence of a person or object which may be used when the dolly is in an autonomous mode. The invention also relates to a vehicle train comprising the status monitor of the first embodiment. Another embodiment of the invention is a method of monitoring the status of the airside dolly. The invention also relates to a method of retro ...

AUTOMATIC DIVERSE SOFTWARE GENERATION FOR USE IN HIGH INTEGRITY SYSTEMS

Systems, devices and methods of automatic diverse software generation are disclosed. In an embodiment, a method includes providing a base algorithm implementation related to a first hardware profile of a hardware resource, automatically generating a diverse algorithm implementation related to a second hardware profile different from the first hardware profile using the base algorithm implementation and information about the hardware resource, and executing the base algorithm implementation and the diverse algorithm implementation. Embodiments of systems and devices, including microprocessors and compilers, are also disclosed.

REAL-TIME ERROR DETECTION BY INVERSE PROCESSING

Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

Transport Safety System

A transport safety system () for use in airports comprising a status monitor () for an airside dolly () used to improve airport safety. The status monitor () comprises a sensor () configured to sense a safety variable of the airside dolly and an output () in communication with the sensor (). The output () is configured to provide a status signal in dependence on the sensed safety variable of the airside dolly (). 1. A status monitor for an airside dolly , the status monitor comprising:a sensor, the sensor configured to sense a safety variable of the airside dolly; andan output, the output being in communication with the sensor and configured to provide a status signal in dependence on the sensed safety variable of the airside dolly.2. (canceled)3. A status monitor according to wherein the sensor comprises a clamp sensor claim 1 , wherein the clamp sensor is configured to sense whether a ULD or other container is correctly clamped to the airside dolly claim 1 , and wherein the safety variable is whether a ULD or other container is correctly clamped to the airside dolly.4. A status monitor according to wherein the sensor comprises a weight sensor claim 1 , wherein the weight sensor is configured to sense a weight claim 1 , or change in weight claim 1 , of cargo being transported by the airside dolly claim 1 , and wherein the safety variable is whether there is a change in weight of the cargo during transportation.5. A status monitor according to wherein the sensor comprises a coupling sensor claim 1 , wherein the coupling sensor is configured to sense whether a further dolly is coupled to the airside dolly claim 1 , and wherein the safety variable is whether the further dolly has become decoupled from the airside dolly.6. A status monitor according to wherein the sensor comprises a proximity sensor claim 1 , wherein the proximity sensor is configured to sense whether an object claim 1 , person or obstacle is proximal to the airside dolly claim 1 , and wherein the ...

System and method of computation by signature analysis

A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

DMA Integrity Checker

Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets. 1. A Direct Memory Access (DMA) controller , comprising:a set of transaction control registers configured to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller;a bus controller configured to read and write to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets; andan integrity checker configured to determine an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set, and further configured to selectively flag an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.2. The DMA controller of claim 1 , wherein the first transaction control set points to a linked list stored in memory.3. The DMA controller of claim 2 , wherein the linked list comprises:a first link ...

Detection systems and methods

One embodiment of the invention provides a detection system. The detection system includes an analog to digital converter that converts one or more analog vibration signals into one or more digital samples, a filter that analyzes at least a portion of the one or more digital samples and identifies energy values across a range of frequencies, a frequency selector that selects a subset of the frequencies for analysis according to one or more operational characteristics, and an analyzer that analyzes the subset of frequencies along with threshold values to identify one or more results.

Safe memory storage by internal operation verification

The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

DETECTION SYSTEMS AND METHODS

One embodiment of the invention provides a detection system. The detection system includes an analog to digital converter that converts one or more analog vibration signals into one or more digital samples, a filter that analyzes at least a portion of the one or more digital samples and identifies energy values across a range of frequencies, a frequency selector that selects a subset of the frequencies for analysis according to one or more operational characteristics, and an analyzer that analyzes the subset of frequencies along with threshold values to identify one or more results.

Safe Memory Storage By Internal Operation Verification

The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous. 1. A memory block , comprisinga host processing unit configured to provide a memory operation request comprising a requested memory address;a first memory array having a plurality of address lines;a first address decoder configured to receive the requested memory address and to and to selectively activate a respective address line associated with the requested memory address; andan address signature generator configured to receive the memory operation request and further configured to generate an address signature based upon the activated address line and to compare the generated address signature and the requested memory address,wherein an error signal is generated if the address lines of the generated address signature are not the same as the address lines of the requested memory address.2. The memory block of claim 1 , wherein the address signature generator comprises:a second memory array configured to store additional address information; andan address comparator configured to receive the generated address ...

Reliable Data Transmission with Reduced Bit Error Rate

A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal. 1. A system comprising:a recipient configured to receive data frames from at least one transmission line, wherein the recipient is configured to determine a recipient check sum based on a plurality of corresponding data frames that are received from the at least one transmission line;a check sum comparing unit configured to receive and to compare the recipient check sum with a corresponding sender check sum determined by a sender transmitting the data frames received at the recipient and;a switch coupled to an output of the recipient and coupled to be activated upon receipt of a signal; anda safety circuit coupled to the check sum comparing unit, wherein the safety circuit is configured to transmit a deactivation signal configured to prevent the switch from conducting a ON current if the check sums compared are not equal.2. The system of claim 1 , wherein the safety circuit is configured to transmit the deactivation signal at the same time the recipient sends the signal for activating the switch.3. The system of claim 1 , wherein the check sum comparing unit is included in the sender claim 1 , the recipient claim 1 , or in a transmission line monitoring unit arranged separately from the sender and the ...

Safety hypervisor function

The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

METHOD AND SYSTEM FOR DETECTION OF LATENT FAULTS IN MICROCONTROLLERS

Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with inconsistent contents. 1. A system for detecting register corruption of redundant CPUs operating on the same input data comprising:a separate bus in each of the redundant CPUs, each bus configured to read at least one predetermined register of the respective one of the redundant CPUs in a non-invasive way; anda comparator to compare contents of at least one set of according registers of different ones of the redundant CPUs to detect corrupted register contents.2. The system of claim 1 , further comprising a sequencer in each of the redundant CPUs claim 1 , each sequencer configured to determine a frequency in which the at least one predetermined register is read and/or a sequence in which at least two predetermined registers of the respective one of the redundant CPUs are read.3. The system of claim 1 , wherein the redundant CPUs are lockstepped CPUs.4. The system of claim 1 , wherein the separate bus in each of the redundant CPUs is configured to non-invasively access all architectural and at least a subset of the hidden registers of the respective one of the redundant CPUs.5. The system of claim 2 , wherein each sequencer is configured to read at least one critical one of the at least one predetermined register more frequently than other claim 2 , non-critical registers.6. The system of claim 2 , wherein each sequencer is configured to read at least one critical one of the at least one predetermined register in response to a predetermined event.7. A system comprising:at least two microcontrollers operating on the same input data, each of the microcontrollers comprising a plurality of registers controlling the operation of a respective one of the ...

Monitoring circuit with a signature watchdog

A method can be used for monitoring a processing circuit. The processing circuit generates a response to a request and the response is compared with an expected response. A pass pulse is generated when the response matches the expected response. The causing, comparing and generating steps are repeated a number of times A frequency at which pass pulses occur is evaluated.

METHODS AND SYSTEMS FOR MEASURING I/O SIGNALS

Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal. 1. A processing system , comprising:a memory unit to store a plurality of operating instructions;a processing unit coupled to the memory unit, wherein the processing unit is adapted to execute logical operations corresponding to respective operating instructions;an input/output (I/O) interface to receive a first time-varying waveform and to provide an I/O signal that is based on the first time-varying waveform;a comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal;wherein the memory unit, processing unit, and comparison unit are all disposed on a single integrated circuit (IC).2. The processing system of claim 1 , wherein the first time-varying waveform is received on a first external pin of the IC claim 1 , the first external pin being coupled to a first signal generator that is ...

Safety system challenge-and-response using modified watchdog timer

Some embodiments of the present disclosure relate to a watchdog timer having an enhanced functionality that enables the watchdog timer to monitor a process flow of the microprocessor on a task-by-task basis that enables a simple output signal to be used to determine if the watchdog timer is malfunctioning. The watchdog timer has a state machine that increments a state variable from an initial value over a watchdog period. A deterministic service request, received from a microprocessor, controls operation of the watchdog timer. The deterministic service request has an indicator of a monitoring operation to be performed, a password, and an estimated state variable. A comparison element determines if the microprocessor is operating properly based upon a comparison of the received password to an expected password and the received estimated state variable to an actual state variable.

System and Method for Determining Operational Robustness of a System on a Chip

A system and method for determining operational robustness of a system on a chip (SoC) includes modifying one or more internal states of the SoC, during operation of the SoC, to mimic an effect which one or more disturbances have on the SoC, generating one or more signal traces that correspond to at least one internal state of the SoC after modifying the one or more internal states of the SoC, and determining if the operation of the SoC is stable based on the one or more generated signal traces.

Reliable data transmission with reduced bit error rate

A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.

System and Method of Computation by Signature Analysis

A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

System and Method for Signature-Based Redundancy Comparison

A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison. 1. A redundant system , comprising:a master part configured to receive an input signal and generate a binary output signal;a first clock delay configured to receive the input signal and generate a delayed input signal;a first signature generator coupled to the master part and configured to receive the binary output signal and generate a first output signature;a second clock delay coupled to the first signature generator and configured to receive the first output signature and generate a delayed first output signature;a checker part coupled to the first clock delay and configured to receive the delayed input signal and generate a delayed binary output signal;a second signature generator coupled to the checker part and configured to receive the delayed binary output signal and generate a delayed second output signature; anda comparator coupled to the second clock delay and the second signature generator, the comparator configured to receive the delayed first output signature and the delayed second output signature and generate an error signal, a state of the error signal based upon a comparison of the delayed first output signature with the delayed second output signature.2. ...

Self-Propelled Airside Dolly, Baggage Handling System, Baggage Handling Facility, and Related Apparatus and Methods

The present invention relates to self-propelled airside dollies (100), and particularly but not exclusively to airside baggage dollies and airside cargo dollies, and autonomous airside dollies. The self-propelled airside dolly comprises a cargo portion (104) configured to hold baggage or cargo, a drive system (108) for driving the self-propelled airside dolly (100), a controller (114) configured to control the drive system (108) in response to control signals and a processor (116) configured to provide the control signals to the controller (114).

Reliable data transmission with reduced bit error rate

A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.

System and method for determining operational robustness of a system on a chip

A system and method for determining operational robustness of a system on a chip (SoC) includes modifying one or more internal states of the SoC, during operation of the SoC, to mimic an effect which one or more disturbances have on the SoC, generating one or more signal traces that correspond to at least one internal state of the SoC after modifying the one or more internal states of the SoC, and determining if the operation of the SoC is stable based on the one or more generated signal traces.

Monitoring Circuit with a Signature Watchdog

A method can be used for monitoring a processing circuit. The processing circuit generates a response to a request and the response is compared with an expected response. A pass pulse is generated when the response matches the expected response. The causing, comparing and generating steps are repeated a number of times A frequency at which pass pulses occur is evaluated. 1. A method of monitoring a processing circuit , the method comprising:causing the processing circuit to generate a response to a request;comparing the response with an expected response;generating a pass pulse when the response matches the expected response;repeating the causing, comparing and generating steps a plurality of times; andevaluating a frequency at which pass pulses occur.2. The method of claim 1 , further comprising indicating a failure when the frequency does not meet predefined frequency criterion.3. The method of claim 2 , further comprising providing a status signal claim 2 , wherein indicating the failure comprises generating a failure level of the status signal.4. The method of claim 2 , wherein evaluating the frequency comprises:determining a mean frequency in a predefined time period; andcomparing the mean frequency with a frequency threshold.5. The method of claim 4 , further comprising indicating a failure when the mean frequency is below the frequency threshold.6. The method of claim 2 , wherein evaluating the frequency comprises:counting the number of pass pulses in a predefined time frame; andcomparing the number with a threshold.7. The method of claim 6 , further comprising indicating a failure when the number of pass pulses is below the threshold or equal to the threshold.8. The method of claim 7 , wherein the threshold is zero.9. The method of claim 2 , wherein evaluating the frequency comprises:providing a counter and a clock signal;setting the counter to a start value;incrementing the counter using the pass pulses and decrementing the counter using the clock signal or ...

Real-time error detection by inverse processing

Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

System and method to increase lockstep core availability

A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core.

Safety hypervisor function

The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

SAFETY HYPERVISOR FUNCTION

The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module. 1. A system for a safety hypervisor function , the system comprising:a computer processing unit (CPU) memory protection unit (CPU MPU) for protecting access to a CPU and a program memory, wherein the CPU MPU determines access to the CPU and the program memory based on a safety privilege level;a bus memory protection unit (bus MPU) for protecting access to a processor bus, wherein the bus MPU determines access to the processor bus based on the safety privilege level; anda register memory protection unit (register MPU) for protecting access to one or more peripherals in the system, wherein the register MPU determines access to the one or more peripherals based on the safety privilege level.2. The system of claim 1 , wherein the CPU includes a register that includes the safety privilege level.3. The system of claim 1 , wherein the safety privilege level is a safety bit.4. The system of claim 1 , wherein the safety privilege level is a safety code.5. The system of claim 1 , wherein the safety privilege level is pre-determined.6. The system of claim 1 , wherein an operating system running on the CPU dynamically allocates the safety privilege level to one or more CPU hardware structures.7. A system for a safety hypervisor function claim 1 , the system comprising:a CPU having memory protection unit (MPU) properties and configured to perform a task ...

DMA integrity checker

Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

System and method for direct memory access transfers

A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.

Vehicle cab rear wall

System and method for signature-based redundancy comparison

A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

READING TO AND WRITING FROM PERIPHERALS WITH TEMPORALLY SEPARATED REDUNDANT PROCESSOR EXECUTION

Embodiments relate to systems and methods for reading from and writing to interface peripherals or other shared resources during robust computation utilizing temporally separated redundant execution. Embodiments can be utilized in safety-relevant applications related to automotive, banking and finance, aerospace, defense, Internet payment, and others.

Reliable Data Transmission with Reduced Bit Error Rate

A data transmission system includes at least one transmission line. A sender is configured to send data frames to the at least one transmission line and a recipient is configured to receive the data frames from the at least one transmission line. The sender and the recipient are both configured to determine a check sum based on a plurality of corresponding data frames that are sent to and, respectively, received from the at least one transmission line. A check sum comparing unit is configured to receive and to compare the check sum determined by the sender and the corresponding check sum determined by the recipient. The check sum comparing unit is also configured to signal a transmission error or initiate a safety function when the check sums compared are not equal.

Methods and systems for measuring I/O signals

Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Methods and Systems for Measuring I/O Signals

Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal. 1. A processing system , comprising:a memory unit to store a plurality of operating instructions;a processing unit coupled to the memory unit, wherein the processing unit is adapted to execute logical operations corresponding to respective operating instructions;an input/output (I/O) interface to receive a first time-varying waveform and to provide an I/O signal that is based on the first time-varying waveform;a comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.2. The processing system of claim 1 , wherein the memory unit claim 1 , processing unit claim 1 , and comparison unit are all disposed on a single integrated circuit (IC).3. The processing system of claim 2 , wherein the first time-varying waveform is received on a first external pin of the IC claim 2 , the first external ...

System and Method for Direct Memory Access Transfers

A system and method for transferring data between a memory and peripheral units via a plurality of direct memory access (DMA) transactions, wherein a respective timestamp is assigned and/or appended to at least two of the plurality of the DMA transactions.

System and Method to Increase Lockstep Core Availability

A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core.

Method and system for detection of latent faults in microcontrollers

Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with inconsistent contents.

Self-propelled dolly, baggage handling system, baggage handling facility

The present invention relates to self-propelled airside dollies(100), and particularly but not exclusively to airside baggage dollies and airside cargo dollies, and autonomous airside dollies, and baggage handling systems making use of said dollies.Theself-propelled airside dollycomprisesa cargo portion (104)configured to hold baggage or cargo, adrive system(108)for driving the self-propelled airside dolly(100), a controller(114)configured to control the drive system (108)in response to control signalsand a processor(116)configured to provide control signals to the controller(114).

Self-propelled airside dolly, baggage handling system, baggage handling facility, and related apparatus and methods

The present invention relates to an autonomous self-propelled airside dolly 100, and particularly but not exclusively to an airside baggage and/or cargo dolly. The autonomous self-propelled airside dolly 100 comprises a processor 116 which is operable in a plurality of different autonomous modes and is changeable between the different autonomous modes in response to a mode trigger. A mode trigger may be a predetermined trigger, such as a geospatial or weather-responsive trigger, in that the timing and/or position of the trigger is/are predetermined and therefore entirely predictable to the self-propelled airside dolly 100 and/or an operator. The processor 116 may be configured to request intervention, for example from a human operator, in response to an event trigger. An event trigger may relate to unforeseen or unpredictable events or issues that may occur at random or in response to unexpected circumstances. A method of operating an autonomous airside dolly is also disclosed.

System and method for direct memory access transfers

System und Verfahren zum Übertragen von Daten zwischen einem Speicher und einer Peripherie-Einheit über eine Vielzahl von Speicherdirektzugriffs-Transaktionen (DMA-Transaktionen), wobei ein jeweiliger Zeitstempel wenigstens zwei von der Vielzahl der DMA-Transaktionen zugewiesen und/oder an wenigstens zwei von der Vielzahl der DMA-Transaktionen angehängt wird. A system and method for transferring data between a memory and a peripheral device via a plurality of direct memory access (DMA) transactions, wherein a respective time stamp is assigned to at least two of the plurality of DMA transactions and / or to at least two of the Variety of DMA transactions is attached.

Duplex redundant system for use in e.g. microcontroller used with banking system, has comparator receiving two delayed output signatures and generating error signal with state based on comparison of output signatures

The system (100) has a signature generator (106) receiving a binary output signal from a master part (102) to generate an output signature. Another clock delay (114) receives the output signature and generates a delayed output signature. A checker part (104) receives a delayed input signal from a clock delay (112) to generate a delayed binary output signal that is received by another signature generator (108) to generate another delayed output signature. A comparator (110) receives the delayed signatures to generate an error signal with a state based on comparison of the delayed signatures. The comparator is a self-testing comparator (STC). The master part is a CPU. Independent claims are also included for the following: (1) a method for performing signature-based redundancy comparison (2) a system for performing signature-based redundancy comparison.

Method and system for the detection of latent errors in microcontrollers

System mit: wenigstens zwei Mikrocontrollern, die mit den gleichen Eingabedaten betrieben werden, wobei jeder der Mikrocontroller eine Vielzahl von Registern aufweist, die den Betrieb eines jeweiligen Mikrocontrollers steuern; einem Bussystem zum nichtinvasiven Lesen von wenigstens einem Satz von entsprechenden Registern von der Vielzahl von Registern von verschiedenen Mikrocontrollern der Mikrocontroller, wobei jeder der Mikrocontroller einen Ausgangsport aufweist, um Inhalte der Vielzahl von Registern des entsprechenden Mikrocontrollers auszugeben, die von dem Bussystem nichtinvasiv gelesen werden, wobei die Vielzahl von Registern m Bits breit ist, wobei die Breite des Ausgangsports nur m/n Bits breit ist, wodurch eine reduzierte Breite für einen Komparator bereitgestellt wird, der die Inhalte von dem wenigstens einen Satz von entsprechenden Registern von der Vielzahl von Registern von den verschiedenen Mikrocontrollern vergleicht, wobei m eine vorbestimmte natürliche Zahl ist, wobei m = n · i ist, und i eine vorbestimmte natürliche Zahl ist, wobei i ≥ 2 ist. System with: at least two microcontrollers which are operated with the same input data, each of the microcontrollers having a plurality of registers which control the operation of a respective microcontroller; a bus system for non-invasive reading of at least one set of corresponding registers from the plurality of registers of different microcontrollers of the microcontrollers, each of the microcontrollers having an output port for outputting contents of the plurality of registers of the corresponding microcontroller, which are read noninvasively by the bus system, wherein the plurality of registers are m bits wide, the width of the output port is only m / n bits wide, thereby providing a reduced width for a comparator that compares the contents of the at least one set of corresponding registers from the plurality of registers of compares the various microcontrollers, where m is a predetermined natural ...

Controlling or monitoring a remote controlled vehicle

Control or monitoring of a remote controlled vehicle 200 is performed by providing plural remote sensors 120 to determine relative distances, executing a planned manoeuvre of the remote controlled vehicle 200, and using the determined distances to control or monitor a position and movement of the remote controlled vehicle 200 when executing the planned manoeuvre. The manoeuvre is a bodily movement of the remote controlled vehicle and/or a movement of a component of the remote controlled vehicle 200, such as a platform of a scissor lift. The remote sensors 120 may be provided on control vehicles. The planned manoeuvre may be automatically controlled or executed by a human operator. The remote controlled vehicle 200 and the control vehicles 100 may be airside vehicles of an airport, e.g. cargo or baggage handling vehicle. Also provided is a control vehicle and a transportation system.

Detection systems and methods

Erkennungssystem, das umfasst: einen Analog/Digital-Wandler, der ein oder mehrere analoge Signale in eine oder mehrere digitale Abtastwerte umwandelt; ein Filter, das wenigstens einen Teil der einen oder mehreren digitalen Abtastwerte analysiert und Energiewerte in einem Bereich von Frequenzen identifiziert; einen Frequenzumschalter, der eine Teilmenge des Bereichs von Frequenzen für die Analyse gemäß einer oder mehrerer Betriebscharakteristiken wählt; und ein Analysegerät, das die Teilmenge des Bereichs von Frequenzen mit Schwellenwerten analysiert, um ein oder mehrere Ergebnisse zu identifizieren. Detection system comprising: an analog-to-digital converter that converts one or more analog signals into one or more digital samples; a filter that analyzes at least a portion of the one or more digital samples and identifies energy values in a range of frequencies; a frequency selector that selects a subset of the range of frequencies for analysis according to one or more operating characteristics; and an analyzer that analyzes the subset of the range of frequencies with thresholds to identify one or more results.

Knock detection system

Erkennungssystem, das umfasst: einen Analog/Digital-Wandler, der ein oder mehrere analoge Signale in eine oder mehrere digitale Abtastwerte umwandelt; eine Einrichtung, die wenigstens einen Teil der einen oder mehreren digitalen Abtastwerte analysiert und Energiewerte in einem Bereich von Frequenzen identifiziert; einen Frequenzumschalter, der abhängig von einer oder mehreren gemessenen Betriebscharakteristiken eines Motors jeweils mindestens zwei Frequenzvariablen als Teilmenge einer vorausgewählten Menge von Frequenzvariablen so konfiguriert, dass zwei Motorklopf-Frequenzbereiche abgedeckt werden; und ein Analysegerät, das die Teilmenge des Bereichs von Frequenzen mit Schwellenwerten analysiert, um ein Motorklopfen zu identifizieren. A detection system comprising: an analog-to-digital converter that converts one or more analog signals into one or more digital samples; means for analyzing at least a portion of the one or more digital samples and identifying energy values in a range of frequencies; a frequency switch which, depending on one or more measured operating characteristics of an engine, configures at least two frequency variables as a subset of a preselected set of frequency variables such that two engine knock frequency ranges are covered; and an analyzer that analyzes the subset of the range of frequencies with thresholds to identify engine knock.

Knock detection system and method

One embodiment of the invention provides a detection system. The detection system includes an analog to digital converter that converts one or more analog vibration signals into one or more digital samples, a filter that analyzes at least a portion of the one or more, digital samples and identifies energy values across a range of frequencies, a frequency selector that selects a subset of the frequencies for analysis according to one or more operational characteristics, and an analyzer that analyzes the subset of frequencies along with threshold values to identify one or more results.

Self-propelled airside dolly, baggage handling system, baggage handling facility, and related apparatus and methods

Self-propelled airside dolly, baggage handling system, baggage handling facility, and related apparatus and methods

Self-propelled airside dolly, baggage handling system, baggage handling facility, and related apparatus and methods

Self-propelled airside dolly, baggage handling system, baggage handling facility, and related apparatus and methods

Self-propelled airside dolly, baggage handling system, baggage handling facility, and related apparatus and methods

Housing assembly for a sensor assembly, sensor assemblies, vehicles with sensors, and methods of improving sensors

The present invention relates to a housing assembly 1 for a sensor assembly. The housing assembly comprises a housing 11, a motor 17, and a controller 18. The housing 1 comprises an outer wall 111 defining an internal volume 112 for receiving a sensor responsive to electro-magnetic radiation, and an aperture 113 arranged in the outer wall 111 to allow light to pass into the internal volume 112. The motor 17 is configured to rotate the housing 11. The controller 18 is configured to control the motor 17 to control rotation of the housing 11 to align the aperture 113 with a field of view of the sensor. Controlling rotation of the housing 11 allows light from a plurality of directions to pass into the internal volume 112 of the housing 11 via the aperture 113 and inhibits the ingress of material into the internal volume 112 through the aperture 113. The housing assembly 1 may be particularly suitable for use with a rotating lidar sensor. Also disclosed is a sensor assembly, methods of obtaining image data using a sensor assembly, a self-propelled airside dolly comprising a sensor assembly, a method of retrofitting a self-propelled airside dolly, and a method of improving the performance of a sensor responsive to electro-magnetic radiation.

DMA-Integritätsprüfungseinheit

Einige Ausführungsformen betreffen einen DMA-Controller (Direct Memory Access, direkter Speicherzugriff). Der DMA-Controller weist einen Satz von Transaktionssteuerungsregistern auf, die so konfiguriert sind, dass sie eine Folge von Transaktionssteuerungssätzen empfangen, die gemeinsam eine von dem DMA-Controller zu verarbeitende Datenübertragung beschreiben. Ein Bus-Controller liest einen Speicher und schreibt in diesen, während der DMA-Controller einen ersten Transaktionssteuerungssatz ausführt, um einen Teil der in der Folge von Transaktionssteuerungssätzen beschriebenen Datenübertragung zu bewerkstelligen. Eine Integritätsprüfungseinheit bestimmt einen Ist-Fehlererkennungscode auf der Grundlage von Daten oder einer Adresse, die tatsächlich von dem DMA-Controller während der Ausführung des ersten Transaktionssteuerungssatzes verarbeitet wurden bzw. wurde. Die Integritätsprüfungseinheit meldet selektiv einen Fehler, je nachdem, ob der Ist-Fehlererkennungscode derselbe ist wie ein in einem zweiten Transaktionssteuerungssatz der Folge von Transaktionssteuerungssätzen enthaltener Soll-Fehlererkennungscode.

DMA-Integritätsprüfungseinheit

DMA-Controller (Direct Memory Access, direkter Speicherzugriff), der Folgendes aufweist: einen Satz von Transaktionssteuerungsregistern, die so konfiguriert sind, dass sie eine Folge von Transaktionssteuerungssätzen empfangen, die gemeinsam eine von dem DMA-Controller zu verarbeitende Datenübertragung beschreiben; einen Bus-Controller, der so konfiguriert ist, dass er den Speicher liest und in diesen schreibt, während der DMA-Controller einen ersten Transaktionssteuerungssatz ausführt, um einen Teil der in der Folge von Transaktionssteuerungssätzen beschriebenen Datenübertragung zu bewerkstelligen; und eine Integritätsprüfungseinheit, die so konfiguriert ist, dass sie auf der Grundlage von Daten, die tatsächlich von dem DMA-Controller während der Ausführung des ersten Transaktionssteuerungssatzes übertragen wurden, einen Ist-Fehlererkennungscode bestimmt, und die des Weiteren so konfiguriert ist, dass sie selektiv einen Fehler meldet, je nachdem, ob der Ist-Fehlererkennungscode derselbe ist wie ein in einem zweiten Transaktionssteuerungssatz von der Folge von Transaktionssteuerungssätzen enthaltener Soll-Fehlererkennungscode, wobei der Ist-Fehlererkennungscode einen Ist-Daten-Fehlererkennungscode umfaßt, der über die übertragenen Daten berechnet wird.

System und Verfahren zum Bestimmen der operativen Robustheit eines Systems auf einem Chip

Ein System und Verfahren zum Bestimmen der operativen Robustheit eines Systems auf einem Chip (SoC) umfassen das Verändern eines oder mehrerer interner Zustände des SoC während des Betriebs des SoC, um die Auswirkung zu imitieren, die eine oder mehrere Störungen auf das SoC haben, das Generieren eines oder mehrerer Signal-Ablaufprotokolle, die wenigstens einem internen Zustand des SoC entsprechen, und das Bestimmen, auf der Grundlage des einen oder der mehreren generierten Signal-Ablaufprotokolle, ob der Betrieb des SoC stabil ist.

Sichere Speicherung durch interneBetriebssicherstellung

Die offenbarte Erfindung stellt eine Struktur und ein Verfahren zum Ermitteln von Adressleitungs (z. B. Wortleitungs-, Bitleitungs-)Speicherausfällen bereit. Bei einer Ausführungsform weisen das Verfahren und die Struktur das Erzeugen einer Adress-Signatur durch Neucodieren eines intern erzeugten Adress-Signals aus aktivierten Elementen (z. B. Wortleitungen) in einem Speicherarray auf. Die neu erzeugte Adress-Signatur kann mit einer angeforderten Speicheradressstelle verglichen werden. Wenn die neu erzeugte Adress-Signatur und die Speicherstelle gleich sind, liegt in dem Speicherarray kein Fehler vor, wenn jedoch die neu erzeugte Adress-Signatur und die Speicherstelle nicht gleich sind, liegt ein Fehler in dem Speicherarray vor. Demgemäß stellt das Neucodieren einer Adress-Signatur einen geschlossenen Prüfkreislauf bereit, dass eine Wortleitung und/oder Bitleitung, die tatsächlich in einem Speicherarray aktiviert wurde, die korrekte angeforderte Wortleitung und/oder Bitleitung war, dass keine weiteren Wortleitungen oder Bitleitungen ebenfalls angesteuert wurden, und dass die Wortleitung und/oder Bitleitung kontinuierlich ist.

System und verfahren zur erhöhung der lockstep-kern-verfügbarkeit

Lockstep-System (100), das Folgendes aufweist:einen Haupt-CPU-Kern (102), der so konfiguriert ist, dass er eine Aufgabe empfängt, und die Aufgabe eine oder mehrere Anweisungen umfasst, wobei der Haupt-CPU-Kern (102) ferner so konfiguriert ist, dass er die eine oder mehreren Anweisungen ausführt, um eine erste Ausgabe für jede ausgeführte Anweisung zu generieren;einen Prüfer-CPU-Kern (104), der so konfiguriert ist, dass er die Aufgabe empfängt und die eine oder mehreren Anweisungen ausführt, um eine zweite Ausgabe für jede ausgeführte Anweisung zu generieren;einen mit dem Haupt-CPU-Kern (102) und dem Prüfer-CPU-Kern (104) gekoppelten Zustandspuffer (108), wobei der Zustandspuffer (108) so konfiguriert ist, dass er einen Zustand des Haupt-CPU-Kerns (102) speichert; undeinen mit dem Haupt-CPU-Kern (102) und dem Prüfer-CPU-Kern (104) gekoppelten Komparator (106), wobei der Komparator (106) so konfiguriert ist, dass er die erste Ausgabe und die zweite Ausgabe für jede ausgeführte Anweisung empfängt, die erste Ausgabe mit der zweiten Ausgabe vergleicht, und, wenn die erste Ausgabe nicht mit der zweiten Ausgabe übereinstimmt,ein oder mehrere Steuersignale generiert, wobei der Haupt-CPU-Kern (102) und der Prüfer-CPU-Kern (104) ferner so konfiguriert sind, dass sie das eine oder die mehreren Steuersignale empfangen und einen gespeicherten Zustand eines CPU-Kerns aus dem Zustandspuffer (108) laden;wobei der Haupt-CPU-Kern (102) eine Zustandssteuerlogik (112a) für den Haupt-CPU-Kern (102) aufweist, die so konfiguriert ist, dass sie vor dem Ausführen der einen oder mehreren Anweisungen durch den Haupt-CPU-Kern (102) den Zustand des Haupt-CPU-Kerns (102) in den Zustandspuffer (108) schreibt.

Powering and controlling or monitoring of vehicles

The present invention relates to vehicles, particularly but not exclusively airside support vehicles, methods of providing electrical power to a battery powered self-propelled vehicle in an operating environment, energy storage vehicles and logistic systems, such as for use in airside environments, methods of controlling or monitoring remote controlled vehicles, control vehicles for controlling remote controlled vehicles, and transportation and/or logistics systems, particularly but not exclusively airside transportation and/or logistics systems. The invention provides an airside support vehicle (100) comprising a drive system (108), a controller (114) configured to control the drive system (108) in response to control signals, a processor (116) configured to deliver control signals to the controller (114), and a sensing system (120) configured to provide sensing data to the processor (116) to enable operation of the vehicle (100) in an autonomous mode.

Transport safety system