Graphical radar signal processing high-level integrated design platform and method

The invention relates to a graphical radar signal processing high-level integrated design platform and a method. The design method is applied to the design platform, and is mainly used for solving the problems of separation of software and hardware, low efficiency, non-portability and poor universality existing in a radar signal processing design method. The method comprises the following steps of: creating a graphical model in a modeling module; analyzing and detecting the model in a model analyzing module; and transmitting an analysis result to a source code generating module, an engineering file generating module and a time sequence analyzing module, encoding a generated source code, an engineering file and a chained file through a DSP (Digital Signal Processor) compiler to obtain an executable DSP program and an MAP file, loading the two files into a radar signal processor through a hardware debugging module, and communicating to realize on-line debugging, wherein the chained file is ...

Parameterized and modularized multi-channel digital down-conversion design platform and parameterized and modularized multi-channel digital down-conversion design method

The invention provides a parameterized and modularized multi-channel digital down-conversion design platform and a parameterized and modularized multi-channel digital down-conversion design method, belonging to the digital signal processing field. A design platform is a parameterized and modularized multi-channel digital down-conversion design platform, which selects M channels from analog input signals of N channels to perform analog-digital conversion and performs the digital down-conversion treatment to output M paths of baseband digital signals. The invention is also a design method, wherein the design process is as follows: an input analog signal gating performs the analog-digital conversion and then the orthorhombic mixing; order H of a filter and a branch extracting multiple D area analyzed in real time; the signals after performing the orthorhombic mixing are respectively delayed, extracted and buffered; meanwhile, the selected filter coefficients are extracted and rearranged, so ...

Structure for preventing burnt fuse pad from further electrical connection

A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.

Bumping process

A bumping process wherein a substrate is first provided with many electrical connections. Subsequently, the bumps on the bump transfer substrate are pressed onto the electrical connections of the substrate accompanying a heating process and then the bumps are transferred onto the electrical connections of the substrate because the adhesion characteristic between the bumps and the electrical connections is better than that between the bumps and the release layer.

Thermal enhance MCM package and manufacturing method thereof

A thermal enhance multi-chips module (MCM) package mainly comprises a first package, a first carrier, a second package, a second carrier, an intermediate substrate and a cap-like heat spreader. The intermediate substrate has an opening. The first carrier and the second carrier are electrically connected to the first package and the second package respectively. The second package is accommodated in the opening and electrically connected to the first package via the first carrier, the second carrier and the intermediate carrier. The cap-like heat spreader has a supporting portion and an alignment portion wherein the supporting portion is connected to the alignment portion to define a cavity. The cavity not only accommodates the first package, the first carrier, the second package, the second carrier and the intermediate substrate but also provides alignment mechanism by the supporting portion and the alignment portion to prevent the dislocation after all the components of the thermal enhance ...

Under-bump-metallurgy layer for improving adhesion

An under-bump-metallurgy layer is provided. The under-bump-metallurgy layer is formed over the contact pad of a chip and a welding lump is formed over the under-ball-metallurgy layer. The under-bump-metallurgy layer comprises an adhesion layer, a barrier layer and a wettable layer. The adhesion layer is directly formed over the contact pad. The barrier layer made from a material such as nickel-vanadium alloy is formed over the adhesion layer. The wettable layer made from a material such as copper is formed over the barrier layer. The wettable layer has an overall thickness that ranges from about 3 mum to about 8 mum.

Method of dicing a wafer from the back side surface thereof

A method of dicing a wafer from the back side surface thereof comprises the steps of: providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips; forming a through structure corresponding to the scribe lines on the active surface of the wafer; and dicing the wafer from the back side surface of the wafer according to the through structure as positioning reference marks.

Wire structure of substrate for layout detection

The substrate of the present invention mainly includes a plurality of bonding pads, a plurality of ball pads, a plurality of traces, a plurality of holes, a first wire and a second wire. The bonding pads and ball pads are located on a first surface of the substrate and are connected to one another by the traces. The first wire is arranged at the edge of the first surface of the substrate, the second wire is arranged at a slot area of a second surface of the substrate which is adhesively covered by a solder mask and further has two ends connecting to the first wire. The holes connect the first surface to the second surface. The traces are connected the bonding pads and ball pads of the first surface by passing through the corresponding holes and a slot area to the second wire of the second surface to form closed loops. In the slot area, the solder mask adhesively covers the traces. During the slot sawing processes of the slot area, some parts of the traces in the slot area and the second ...

Ball grid array semiconductor package with improved strength and electric performance and method for making the same

Disclosed are metal reinforced layers disposed at the upper and lower surfaces of the thin substrate to reinforce the strength of the thin substrate. With reinforced strength, the thin substrate is not susceptible to deform due to temperature fluctuation during packaging process, and thus the warpage for the semiconductor package is significantly eliminated. According to another aspect of the present invention, the metal reinforced layer at the lower surface of the thin substrate is functioned as a ground plane for the ball grid array (BGA) semiconductor package for better grounding effect. The present invention provides an optimal design for the return current path and impedance matching control. Besides, in high frequency application, the metal reinforced layer also can reduce the noise and cross talk among the signal lines of the ball grid array (BGA) semiconductor package.

Method of making a semiconductor package by dicing a wafer from the backside surface thereof

A method of dicing a wafer from the back side surface thereof comprises the steps of: providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips; forming a through structure corresponding to the scribe lines on the active surface of the wafer; and dicing the wafer from the back side surface of the wafer according to the through structure as positioning reference marks.

WAFER-LEVEL PACKAGE STRUCTURE

A wafer-level package structure, applicable to a flip-chip type arrangement on a carrier having a plurality of contact points is described. This wafer-level package structure comprises a chip having a protective layer and a plurality of bonding pads and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The wafer-level package structure can further include a heat sink to enhance the heat dissipation ability of the package structure.

Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability

A ball grid array semiconductor package includes a substrate, a die mounted on the substrate and electrically connected to the substrate by bonding wires, a heat ring mounted on the substrate to surround the die and the bonding wires, and a heat slug mounted on the heat ring to entirely cover the die and the bonding wires thereby providing improved heat dissipation efficiency and overall electrical performance. Encapsulation material is filled into an inner space surrounded by the heat ring, heat slug and substrate to form an encapsulant for protecting the die and bonding wires. The heat ring and heat slug has at least a portion of surface area sequentially coated with a metal medium layer and an insulation layer to enhance the bonding degree between the encapsulant and the heat ring and heat slug.

Water-level package with bump ring

A wafer-level package includes a first chip, a second chip and a bump ring. The first chip has a semiconductor micro device, a bonding pad ring surrounding the semiconductor micro device, and a plurality of bonding pads disposed outside the bonding pad ring and electrically connected to the semiconductor micro device for electrically connecting to an external circuit. The second chip has a bonding pad ring corresponding to the bonding pad ring of the first chip. The bump ring is disposed between the bonding pad ring of the first chip and the bonding pad ring of the second chip for bonding the first and the second chips so as to form a hermetical cavity.

BMUPING PROCESS

A bumping process wherein a substrate is first provided with many electrical connections. Subsequently, the bumps on the bump transfer substrate are pressed onto the electrical connections of the substrate accompanying a heating process and then the bumps are transferred onto the electrical connections of the substrate because the adhesion characteristic between the bumps and the electrical connections is better than that between the bumps and the release layer.

Die ring used for production of seamless steel pipe with large diameter and thick wall and manufacturing method thereof

The invention relates to a die ring used for production of a seamless steel pipe with a large diameter and a thick wall and a manufacturing method thereof. The die ring is composed of a combination of a die ring sleeve and an inlaid sub-die ring. The manufacturing method of the die ring adopts an inlaid combination manufacturing method of: respectively processing and conducting heat treatment to the die ring sleeve and inlaid sub-die ring manufactured from forged steel, then combining them together by a screw connection way. In the invention, the die ring manufactured by combination of the die ring sleeve made from 45 steel and the inlaid sub-die ring made from 5CrMnMo tool steel with high strength and good red hardness has substantially improved service life compared with traditional 45 steel die rings, and also enhances the pipe blank surface quality of the seamless steel pipe with a large diameter and a thick wall. Also, when reaching the service life, the inlaid sub-die ring can be ...

Multichip module having a stacked chip arrangement

A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Bumping process

A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls are disposed into each opening and melted partially to bond to the metallic layer temporarily by performing a heating process simultaneously. Then, a process of disposing the flux material in the openings to cover the surfaces of the solder balls is performed ...

Base for wire bond checking

A base mainly includes a heating plate and a probe. The probe is attached to the surface of a heating plate which serves to place a substrate having an ball pad on a lower surface facing the probe of the heating plate. The probe contacts the ball pad of the lower surface of the substrate to form a closed loop for wire bond checking while the substrate is placed on the heating plate. When processing the wire bond, the wire connecting the chip and the ball pad of the substrate and the probe connecting to the wire bond checking system form a loop. Then a current is sent to the substrate from the wire bond checking system to check for wire lift bond or missed wire. When the wire bond checking system finds an occurrence of lift bond or missing wire, the wire bonding process stops immediately to avoid unnecessary wire bonding.

Semiconductor package and manufacturing method thereof

A semiconductor package mainly comprises a substrate unit and a chip. The chip is electrically connected to the substrate unit. The substrate unit includes an upper surface, a lower surface and a side surface. A plurality of circuit traces are formed on the upper surface and a plurality of contacts are formed on the side surface, wherein the contacts are electrically connected to the circuit traces. Besides, a plurality of solder balls are formed on the contacts in order to transmit the signals from chip to outside through the substrate unit, the contacts and the solder balls. Furthermore, a semiconductor package module will be formed by electrically connecting the semiconductor packages with each other through solder balls and a module substrate, and mounting the semiconductor packages with each other through an adhesive layer. In addition, a method for manufacturing the semiconductor package is disclosed.

Optical component package and packaging including an optical component horizontally attached to a substrate

An optical component package includes a substrate, an optical component, a plurality of spacers, a plurality of wires, and a transparent molding compound. The optical component is disposed on the substrate, and the surface of the optical component located away from the substrate is used to receive an optical signal. The spacers are disposed between the substrate and optical component. The wires electrically connect the optical component to the substrate. The transparent molding compound encapsulates the optical component. In this case, the diameter of each of the spacers is equal to the thickness of the transparent molding compound minus the thickness of the optical component minus the distance between where the optical signal enters the transparent molding compound and where the optical signal is received by the optical component. Furthermore, this invention also discloses a packaging method for the optical component package.

[STRUCTURE FOR PREVENTING BURNT FUSE PAD FROM FURTHER ELECTRICAL CONNECTION]

A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.

Energy-saving dynamic frequency spectrum planning method in femtocell network

The invention relates to an energy-saving dynamic frequency spectrum planning method in a femtocell network and provides an energy-saving dynamic frequency plan based on soft frequency reuse in a bilayer femtocell network, wherein an energy-consumption model of a downlink of a three-dimensional space femtocell bilayer network is established. According to the method disclosed by the invention, a soft frequency reuse scheme is adopted, interferences to macro cell users in a cell edge area are reduced, and the interruption rate of the edge users is reduced. Frequencies distributed to macro cell users and femtocell users in an internal area are orthogonal mutually, cross-layer interferences between a macro cell network layer and a femtocell network layer are avoided, the user distribution and business traffic distribution of the internal area and an external area of the macro cell are fully considered on the premise of guaranteeing QoS (Quality of Service) requirements of the users, the frequency ...

Perception-based frequency spectrum self-management method in femtocell network

The invention relates to wireless resource management in mobile communication and provides a perception-based frequency sub-band self-management method in a femtocell network. The method comprises the steps: measuring and reporting interferences, produced by adjacent base stations, to a user by the user; and calculating interference weight and generating a weighting interference pattern by a centralized control unit according to a measurement report, and clustering femto base stations according to user service quality requirements and the distribution density of the base stations in the network so as to form a virtual cell. The femto base stations with lower mutual interferences are divided into a same cluster, and nodes in the cluster multiplex frequency sub-band. Because the base stations in the femtocell network are started or closed at any time, the network topology and the base station density are made change at any time, the self-management of frequency spectra is realized by re-executing ...

Thermal enhance package and manufacturing method thereof

A thermal enhance package mainly comprises a chip, a substrate unit, a heat spreader unit and a plurality of pellets. The chip is disposed above the substrate unit and electrically connected to the substrate unit, and an encapsulation unit encapsulates the chip, the substrate unit, the heat spreader unit and the pellets. Therein the pellets are formed on the substrate unit and connect the substrate unit and the heat spreader unit. Thus the heat arisen out of the chip can be transmitted to the heat spreader unit not only through the encapsulation unit but also the pellets. Moreover, the substrate unit has at least one grounding contact connecting to one of the pellets so as to provide the thermal enhance package a good shielding. In addition, a method for manufacturing the thermal enhance package is also provided.

Multi-chip package structure

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Wafer-level package structure

A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

Umbrella head capable of storing residual rain

The invention discloses an umbrella head capable of storing residual rain. The umbrella head capable of storing the residual rain comprises an umbrella head positioning part, a water storage housing connecting rod and a water storage housing. The umbrella head capable of storing the residual rain is characterized in that one end of the umbrella head positioning part is connected with an umbrella main rod, the other end of the umbrella head positioning part is connected with the water storage housing connecting rod, and integral materials of the umbrella head capable of storing the residual rain are preferably made of high-strength engineering plastics. When in use, rain on the umbrella can spontaneously flow into the water storage housing of the umbrella head along the umbrella surface as long as the umbrella is closed up and the umbrella head is downward. By means of the umbrella with the umbrella head capable of storing the residual rain, the fact that residual rain on the umbrella wets ...

Device for preventing rainwater remained on umbrella from reversely leaking

The invention relates to a device for preventing rainwater remained on an umbrella from reversely leaking. The device comprises a positioning head, supporting strips, a circular ring, an arc-shaped groove, internal threads, a water storage cover, a raised ring and a water storage chamber, and is characterized in that the internal threads are arranged in the middle of the positioning head; more than three supporting strips are arranged on the outer side of the positioning head; the circular ring is connected with the positioning head through the supporting strips; the outward arc-shaped groove is formed in the circular ring; the raised ring is arranged at an opening of the water storage chamber; the shape and size of the arc-shaped groove and the raised ring are matched with each other; the water storage cover is made of engineering plastic. The water storage cover of the device can be detached and cleaned; the water storage covers in different colors or sizes can be exchanged; the device ...

Miniaturized holographic antenna used for directed radiation on surface of flight body

The invention provides a miniaturized holographic antenna used for directed radiation on surface of a flight body and aims to solve the problems in the prior art such as too large holographic structure size, too great antenna loss, higher first minor lobe level and too low radiation efficiency and the like. The miniaturized holographic antenna comprises a feed source antenna (1) and a holographic structure (2), wherein the holographic structure comprises a medium base plate (21), a metal group belt (22), horn-shaped metal baffle plates (23) and an earth plate (24); the feed source antenna (1) is arranged at the negative semiaxis focal point of the metal group belt (22); the metal group belt (22) is coated on the surface of the medium base plate (21); the horn-shaped metal baffle plates (23) are vertically welded on the left and right sides of the medium base plate (21); the medium base plate (21) is filled with Duriod 6010 medium; and the horn-shaped metal baffle plates (23) can restrict ...

Bumping process

A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned, so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls with a solidified material on the surface of each solder ball are disposed into each opening. Then, a reflow process is carried out, so that the solder balls bond with the metallic layer. Finally, the photoresist layer is removed.

SOLDER BALL ATTACHING PROCESS

A solder ball attaching process for attaching solder balls to a wafer is provided. First, an under-ball-metallurgy layer is formed on the active surface of the wafer. Patterned masking layers are sequentially formed over the active surface of the wafer. The masking layers together form a step opening structure that exposes the under-ball-metallic layer. A solder ball is placed on the uppermost masking layer and allowed to roll so that the solder ball drops into the step opening structure by gravity. A reflow process is conducted to join the solder ball and the under-ball-metallurgy layer together. Finally, various masking layers are removed to expose the solder ball on the bonding pad of the wafer.

Structure of a solder mask for the circuit module of a BGA substrate

The structure of a solder mask for the circuit module of a BGA substrate mainly comprises a power ring, a ground ring, a plurality of holes, a plurality of first holes and a plurality of second holes. The power ring and the ground ring are arranged between the chip area and the wire bonding area; the first openings are arranged on the power ring and the ground ring for receiving the electronic part. Thus the substrate meets the requirement of keeping the electronic part close to the chip. The second openings are arranged over the associated holes which electrically connect to the power ring and the ground ring by traces; these holes do need not to electrically connect the power layer and the ground layer of the substrate. The openings of the present invention use the power ring, ground ring and the holes of the substrate to electrically connect to the electronic parts, so that the present invention does not need to provide other holes or traces thus simplifying the structure of the substrate. The distance of two openings of the present invention can, moreover, be adjusted according to the length of the electronic part.

Semicondutor wafer device

A semiconductor wafer device is provided in this invention. The semiconductor wafer device includes a plurality of chips, circuits, cutting streets, and a polymer layer. The cutting streets include a plurality of longitudinal cutting streets and transverse cutting streets, which are formed between the neighboring chips, and the polymer layer is formed on the cutting streets. In addition, this invention also provides a semiconductor wafer device with a plurality of bumps formed thereon and the bumps are encompassed with a polymer layer.

Semiconductor chip package and method for manufacturing the same

A semiconductor chip package mainly comprises an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The present invention is characterized in that the peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate. The present invention further provides a method for manufacturing the semiconductor chip package.

Multichip module having a stacked chip arrangement

A multichip module has at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. In some embodiments, the semiconductor chips may have a plurality of bonding pads along only two mutually perpendicular side edges thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

METHOD OF MODIFYING TIN TO LEAD RATIO IN TIN-LEAD BUMP

A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.

Multi-chip package structure

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting ...

Semiconductor chip package and manufacturing method thereof

A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Correlation-based multi-sensor collaborative target detection method

The invention discloses a correlation-based multi-sensor collaborative target detection method. The method is characterized by comprising the following steps that sensor nodes measure signals in a monitoring area independently; when the measured value of a certain sensor node exceeds a preset threshold, triggering to generate a dynamic detection cluster; member nodes in the cluster transmit a detection value sequence in a period of time to a cluster head node to form a detection matrix; and the cluster head node calculates the correlation measure among detection vectors in the detection matrix, and judges the existence of a target according to a calculation result. The target detection method provided by the invention is a measured value-based fusion detection method; a single sensor node does not need to perform local judgment; the influence on the judgment result caused by noises can be inhibited effectively; and the detection result has high accuracy. The method can be used in the aspects ...

Filter with back cavity resonators

The invention provides a filter with back cavity resonators. Under the situation that filter order is small, a transmission zero point can be generated, so that filter out-of-band rejection is improved, and the problem that out-of-band rejection is bad in a duplexer is solved. The filter comprises an input end, a plurality of spiral resonators, a partitioning plate, an output end, the multiple back cavity resonators and a metal frame. The metal frame comprises a plurality of metal cavities. The input end and the output end comprise outer wrapping parts and metal rods in the outer wrapping parts. The metal rods penetrate through the metal walls of the metal cavities of the metal frame and are not in contact with the metal wall. The spiral resonators and the back cavity resonators are placed in the metal frame. The filter is simple in structure and flexible in construction, the filter can be used for cavity filters of any order, the transmission zero point can be generated at any place outside ...

Manufacturing method of targeted magnetic nanometer probe for early diagnosis of atherosclerosis vulnerable plaques

The invention relates to a manufacturing method of a targeted magnetic nanometer probe for early diagnosis of atherosclerosis vulnerable plaques, which is used for carrying out experiment research for the early warning of vulnerable plaques at an early stage and providing experimental data support for development and popularization of an innovation-type diagnostic reagent, so that not only can unstable plaques be effectively found and pre-warned at the early stage, but also the curative effect of the novel anti-atherosclerosis drug can be evaluated. The manufacturing method disclosed by the invention comprises the following steps of: using Fe3O4 nanometer particles PEI (Polyethyleneimine)-Fe3O4-NP (Nonyl Phenol) of PEI as carriers; and connecting profilin-1 antibodies on the surfaces of the carriers by a chemical synthesis method to form the magnetic nanometer probe PF(Profilin)1-PEI-Fe3O4-NP of the targeted profiling-1 protein.

Bump and fabricating process thereof

A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 mum is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.

Interception circuit in radar signal processor and interception method of interception circuit

The invention discloses an interception circuit in a radar signal processor and an interception method of the interception circuit, which are mainly used for solving the problems of pulse compression and low precision of a movable target detection interception module in the conventional radar signal processing. The interception circuit comprises a normalization unit, an amplifying unit and an interception unit, wherein the normalization unit is used for realizing normalization of input data by using a phase inverter, an accumulator and an alternative multi-channel selector, and output data of the normalization unit are taken as input data of the amplifying unit; the amplifying unit is used for realization of selection of a digit capacity of a highest non-zero digit in maximum data in one group of input data by using two input or gates, a data register, an alternative multi-channel selector, a one-in-twenty-five multi-channel selector and a counter, and taking a selection result as input ...

Wafer-level package with bump and method for manufacturing the same

A wafer-level package with bump comprises a first chip, a second chip and a bump ring. The first chip has a semiconductor micro device, a bonding pad ring surrounding the semiconductor micro device, and a plurality of bonding pads disposed outside the bonding pad ring and electrically connected to the semiconductor micro device for electrically connecting to an external circuit. The second chip has a bonding pad ring corresponding to the bonding pad ring of the first chip. The bump ring is disposed between the bonding pad ring of the first chip and the bonding pad ring of the second chip for bonding the first and the second chips so as to form a hermetical cavity.

Semiconductor package and method for manufacturing the same

A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

Semiconductor package with wire protection and method therefor

A semiconductor package includes a semiconductor die mounted on an upper surface of a substrate. A number of wire bonds electrically connect between a number of bonding pads on the upper surface of the substrate and a number of bonding pads on an upper surface of the semiconductor die. A fixing portion surrounds the semiconductor die and covers a mediate portion of each wire bond. Encapsulating material is molded over the semiconductor die and the wire bonds to form an encapsulant. In an alternative embodiment, the fixing portion is provided on the upper surface of the substrate adjacent to a mold gate of the substrate where the wire sweeping is most likely to occur while molding. The fixing portion does not cover the semiconductor die to avoid thermal strain acting on the semiconductor die due to the different coefficients of thermal expansion between the fixing portion and the encapsulant.

Umbrella accessory device structure capable of preventing remained rainwater from dripping

The invention relates to an umbrella accessory device structure capable of preventing remained rainwater from dripping. The umbrella accessory device structure comprises a positioning ring, support strips, clamping rings, arc-shaped grooves, a through hole, a head sleeve, a convex ring and a water storage cavity. The umbrella accessory device structure is characterized in that the through hole is formed in the middle part of the positioning ring, the three support strips are arranged at the exterior of the positioning ring, each clamping ring is arranged on the corresponding support strip, and each arc-shaped groove in the corresponding clamping ring faces outwards; the convex ring is arranged at an opening of the head sleeve; the three arc-shaped grooves form an annular groove, and the annular groove is matched with the convex ring; the head sleeve is made of engineering plastic; the convex ring at the opening of the head sleeve is clamped and fixedly arranged into the annular groove of ...

Semiconductor chip package and manufacturing method thereof

A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Bump and fabricating process thereof

A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 μm is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.

Method of modifying tin to lead ratio in tin-lead bump

A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.

Multi-chip package structure

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting ...

Multi-chip package structure

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting ...

Interference canceller applied to detecting core quadrupole moment resonance signal

The invention discloses an interference canceller applied to detecting a core quadrupole moment resonance signal. The interference canceller comprises a main channel, an auxiliary channel, a space domain interference canceling treatment module between the main channel and the auxiliary channel, and a time domain interference canceling module in the main channel. A master control computer generates an exciting pulse sequence, and the exciting pulse sequence is loaded to a main antenna coil to excite a sample to be detected through a signal generator and a high-power transmitter; an NQR (nuclear quadrupole resonance) signal obtained by excitation is received in the main channel through the main antenna coil, and meanwhile, the space domain interference is received in the auxiliary channel through an auxiliary antenna coil; signals in the main channel and the auxiliary channel enter a space domain interference canceling treatment process through a preamplifier, an analog receiver, A/D (analog ...

Multi-chip package structure

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting ...

Semiconductor package and method for manufacturing the same

A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

Bumping process

A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls are disposed into each opening and melted partially to bond to the metallic layer temporarily by performing a heating process simultaneously. Then, a process of disposing the flux material in the openings to cover the surfaces of the solder balls is performed ...

Wafer bumping process with solder balls bonded to under bump metallurgy layer formed over active surface by forming flux on solder ball surfaces and reflowing the solder

A bumping process, which is a method of forming a plurality of bumps over a wafer, is provided. The wafer has an active surface having a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads on the active surface. An adhesion layer is formed over the active surface of the wafer covering both the bonding pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned, so that the adhesion layer and the metallic layer remain on top of the bonding pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that exposes the metallic layer. Next, solder balls with a solidified material on the surface of each solder ball are disposed into each opening. Then, a reflow process is carried out, so that the solder balls bond with the metallic layer. Finally, the photoresist layer is removed.

Film ball grid array (BGA) semiconductor package

A film BGA package generally comprises a semiconductor chip disposed on a flexible film substrate. The flexible film substrate includes a plurality of solder pads formed on the central area thereof and a plurality of chip connection pads formed on the peripheral area thereof. The semiconductor chip is securely attached onto the upper surface of the flexible film substrate through a nonconductive adhesive and electrically connected to the chip connection pads. The chip connection pads are electrically connected to the corresponding solder pads. The flexible film substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has at least a portion exposed within the corresponding through-hole for mounting a solder ball. The present invention is characterized in that the flexible film substrate is provided with a dam and a stiffener wherein the dam is located between the chip and the chip connection pads thereby preventing the nonconductive adhesive ...

Method for preventing burnt fuse pad from further electrical connection

A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.

Multichip wafer-level package and method for manufacturing the same

A multichip wafer-level package comprises a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding pad ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding pad ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding pad ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding pad ring corresponding to the first bonding pad ring of the first chip. The bump ring is disposed between the first bonding pad ring of the first chip and the second bonding pad ring of the second chip for bonding the first and the second chips so as to ...

Ball grid assembly type semiconductor package having improved chip edge support to prevent chip cracking

This invention moves at least one outer via outwardly to a location under the edge of the chip so as to form an offset via. Since the via is made of copper, the offset via provides sufficient supporting strength for the chip edge during molding process. Further, this invention also disposes a copper mesh on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip. According to another aspect of this invention, dummy via holes are provided for the substrate at the area under the chip edge for supporting the chip. Since the copper mesh, offset via, the dummy via hole are made of copper having sufficient supporting strength for the chip, the crack problem during molding process can be eliminated.

Electrically tunable dual-mode dual-passband filter with constant bandwidth

The invention discloses an electrically tunable dual-mode dual-passband filter with constant bandwidth, which mainly solves the problems of great insertion loss, non-constant bandwidth and poor out-of-band rejection performance of an electrically tunable dual-passband filter. The filter comprises a microstrip dielectric substrate (1), a metal grounding plate (2), two square resonant rings (3), a direct-current biasing circuit (7), grounding holes (6) which are arranged in the metal grounding plate, and a pair of input/output feeder lines (4). A folded square resonant ring (31) and a folded square resonant ring (32) are connected by adopting a symmetrical cascade connection method. Variable capacitance diodes (5) are loaded at the internal corners of each square resonant ring. The direct-current biasing circuit (7) is used for providing variable voltage for the variable capacitance diodes (5). The pair of input/output feeder lines (4) adopt F-shaped coplanar waveguide structures and are ...

Strip of semiconductor package

A strip mainly includes a plurality of guide holes, a plurality of position holes, a plurality of separation holes, a plurality of second slots and a plurality of substrate areas. Guide holes are arranged on two sides of the strip for carrying during processing, and position holes are arranged at four corners of the strip for positioning on the machine during processing. Separation holes and slots are to be contiguous to the substrate areas and separate the substrate areas from one another so that the discontinuous warpage of the substrate area affects the peripheral substrate areas. Therefore, it can reduce the chance of breaking chip in the substrate area. The two ends of the substrate are adjacent to the slots to reduce the stress of other substrates in the longitudinal direction actuating the chip during heat treatment in processing. The strip further includes a metal layer surrounding the substrate areas to increase the stiffness of the entirety of the strip.

Method of making low-profile wire connection

A method of making low profile wire connection comprising steps of: connecting a wire to a first bonding point, moving a capillary straight up a first length, moving the capillary away from a second bonding point thus making the first reverse action to bend the wire in an appropriate angle so as to form the first bent point, again raising the capillary a second length, again moving the capillary in the direction of the second bonding point to bend the wire in an appropriate angle so as to form the second bent point, again raising the capillary a third length, moving the capillary to the second bonding point thus making an action to bend the wire in an appropriate angle so as to form the third bent point, raising the capillary a fourth length by feeding out the wire to a length which is enough to make a wire loop, and then moving the capillary down to the second bonding point where the bonding is performed.

Ball bonding method on a chip

A ball bonding method on a chip mainly comprises steps of: a wire is burned to form a ball on a capillary; the capillary is moved down to a second bonding point for ball bonding; and the capillary is moved up in a vertical direction thereby pulling the tip of the ball to be cut such that the ball has a uniformly body shape and tip height. Therefore, the ball provides uniform body shape and tip height for wire bonding at a second bonding point under lower variability conditions thus increasing the reliability of products.

Preprocessing method of trace uranium samples

The invention discloses a preprocessing method of trace uranium samples, which belongs to the technical field of analytic chemistry. The method comprises the following steps of: (i) adjusting the trace uranium samples to be alkaline; (ii) directly soaking ion exchange fibers into the sample liquor to absorb uranium; (iii) washing the ion exchange fibers, which are taken out of the sample liquor, via detergent; (iv) soaking the washed fibers into a leaching reagent; and (v) taking the leaching reagent out for measurement. The ion exchange method provided by the invention is used for preprocessing the trace uranium samples, and has the advantages of being simple to operate, high in accuracy and analysis speed and capable of eliminating co-existing ion interference effectively.

Multi-chip package structure

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Manufacturing method of roller for ceramic tile kiln

The invention provides a manufacturing method of a roller for a ceramic tile kiln, which comprises the following steps: selecting the following raw materials in percentage by weight: 29-33% of aluminum oxide, 35-49% of silicon carbide, no more than 0.3% of magnesium oxide, no more than 0.4% of iron oxide, no more than 0.8% of calcium oxide, sodium oxide and potassium oxide and the balance of clay; mixing and stirring the selected raw materials, placing in a ball grinder, and grinding to obtain pulp; pressing to obtain a mud cake through a filter press, discharging the mud cake, placing in a mud refiner, and refining to obtain a roller mud blank; placing the mud blank in a pipe extruder, and manufacturing into a pipe-like product; and naturally drying, further drying through waste heat of a kiln, then feeding into the kiln, and firing to obtain a finished roller product. The roller manufactured by the invention is not subjected to heat accumulation, is not heated and can not be deformed ...

Quad flat non-leaded package

The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is disposed around the die pad and is in contact with the semiconductor chip so as to increase the supporting to the semiconductor chip. The area of the semiconductor chip is larger than that of the die pad, and the semiconductor chip is attached to the die pad through its active surface. The molding compound encapsulates the lead frame, semiconductor chip and connecting wires, wherein part of the leads of the lead frame is exposed to the outside of the molding compound so as to be electrically connected to an external device.

Thermal enhance MCM package

A thermal enhance MCM package mainly comprises a first chip, a second chip, a substrate and a thermally conductive device. The first chip and the second chip are electrically connected to the substrate, and the thermally conductive device is mounted on the substrate. The thermally conductive device is exposed to the outside so as to prevent the heat generated from the first chip and the second chip from being accumulated in the substrate and transmitted to the motherboard. Accordingly, the thermal performance of the MCM package will be upgraded.

Semiconductor chip with bumps and method for manufacturing the same

A method for manufacturing a semiconductor chip with bumps comprises providing a semiconductor chip, which defines an active surface and a back surface and has a plurality of pads disposed on the active surface, and a plurality of preformed solder balls. A passivation is disposed on the active surface of the semiconductor chip with the pads exposed. A plurality of UBMs (Under Bump Metallurgy) are disposed on the pads and define a plurality of bump pads. The diameter of the bump pads is about 100% to about 130% of the diameter of the preformed solder balls. The preformed solder balls are placed on the bump pads and then reflowed to form a plurality of bumps on the semiconductor chip.

Semiconductor package

A semiconductor package comprises a first chip, a substrate, a middle layer, a second chip, and an encapsulant. The first chip has an active surface and a high-frequency element defining a high-frequency area on the active surface. The substrate supports the first chip and is electrically connected to the first chip. The middle layer is disposed on the first chip and has a recess corresponding to the high-frequency area. The second chip is disposed on the middle layer and electrically connected to either the first chip or the substrate. The encapsulant encapsulates the first chip, the middle layer, the second chip, and a part of the substrate.

Process for fabricating wafer bumps

A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.

Preparation method of MRI/PET bimodal molecular imaging probe for atherosclerotic vulnerable plaque

The invention relates to a molecular probe in a medical imaging diagnostic reagent, and in particular relates to a preparation method of an MRI/PET bimodal molecular imaging probe for an atherosclerotic vulnerable plaque. According to the probe, molecular imaging can be performed on a new vessel of the atherosclerotic vulnerable plaque, and early warning of an unstable plaque is realized so as to provide a favorable new molecular imaging technology for early diagnosis and prevention of the coronary heart disease and reduction of serious cardiovascular event risk. The preparation method comprises the following step: chemically synthesizing a new vessel specific MRI/PET bimodal molecular imaging probe 68Ga-GEBP11-DMSA (dimercaptosuccinic acid)-MNPs through condensation reaction and chelating reaction by taking GEBP11 short peptide as a targeting tool and DMSA modified magnetic Fe3O4 nanoparticles (DMSA-MNPs) as carriers.

WAFER BUMP FABRICATION PROCESS

A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a baking process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.

Under-ball-metallurgy layer

An under-ball-metallurgy layer between a bonding pad on a chip and a solder bump made with tin-based material is provided. The under-ball-metallurgy layer at least includes an adhesion layer over the bonding pad, a nickel-vanadium layer over the adhesion layer, a wettable layer over the nickel-vanadium layer and a barrier layer over the wettable layer. The barrier layer prevents the penetration of nickel atoms from the nickel-vanadium layer and reacts with tin within the solder bump to form inter-metallic compound. This invention also provides an alternative under-ball-metallurgy layer that at least includes an adhesion layer over the bonding pad, a wettable layer over the adhesion layer and a nickel-vanadium layer over the wettable layer. The nickel within the nickel-vanadium layer may react with tin within the solder bump to form an inter-metallic compound.

Semiconductor chip package

A method of manufacturing a semiconductor chip package includes mechanically and electrically connecting a semiconductor chip to a top surface of a main substrate, securely attaching the semiconductor chip to a recessed cavity on a bottom surface of an interconnection substrate, mechanically and electrically connecting the main substrate to the interconnection substrate, and cutting the main substrate to form a central substrate and a peripheral substrate wherein the semiconductor chip is disposed on the central substrate. The cutting step is conducted either (i) by forming a plurality of slots such that the central substrate and the peripheral substrate are partially conned to each other or (ii) by completely separating the central substrate and the peripheral substrate.

Multichip modules and manufacturing method therefor

A multichip module includes a substrate having two padding strips, a first chip, and a second chip mounted thereon. The padding strips are mounted to two sides of the first chip. The second chip is disposed above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip. In another embodiment of the invention, the substrate includes a recess, a first chip, and a second chip. The first chip is received in the first chip, and the second chip is disposed above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip. A method is provided to manufacture a multichip module by placing a first chip on a substrate and then placing a second chip above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip.

Semiconductor chip package and manufacturing method thereof

A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Correction system for bad driving habit taking accelerator as brake by mistake and using method thereof

The invention provides a correction system for a bad driving habit taking an accelerator as a brake by mistake and a using method of the correction system. According to the confirmation of studies, the main reason why a driver takes the accelerator as the brake is that the driver does not form a good driving habit; if the driver is accustomed to setting the position of the accelerator/brake control foot at will, the driver stretches the foot to jam on the brake in an emergency, and then the driver is likely to step on the accelerator. According to the correction system for the bad driving habit taking the accelerator as the brake by mistake and the using method of the correction system, a forced habit formation way is adopted, and the driver is trained to form the good habits that the driver is trained to firstly put the accelerator/brake control foot at the position where a brake pedal of a vehicle is convenient to control as soon as the driver enters a cab to start the vehicle, and the ...

Wafer-level package with a cavity and fabricating method thereof

A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.

Press plate of wire bond checking system

A press plate mainly includes a plate and a probe. The plate has an opening which corresponds to a chip of the substrate and inner finger thereof, and the probe is elastically attached to the edge of the opening for wire bond checking. After the wire bonding process, the wire connecting the chip and the inner finger of the substrate and the probe of the wire bond checking system form a loop. Then a current is sent to the substrate from the wire bond checking system to check for the occurrence of wire occurring lift bond or missing wire.

Write Enhancement for One Time Programmable (OTP) Semiconductors

A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line. The voltage across an oxide layer between the gate electrode and channel region of the programming element ruptures the oxide layer and effectively programs the programming element.

BONDING STRUCTURE FOR BONDING SUBSTRATES BY METAL STUDS

A bonding structure for bonding two substrates by a metal stud includes a first substrate, a second substrate, at least a metal stud and an adhesive. The bonding structure includes a first substrate, a second substrate, at least a metal stud and an adhesive. The metal stud is arranged between the first substrate and the second substrate and attached to the first substrate. The adhesive is applied between the metal stud and the second substrate to electrically connect the metal stud and the second substrate.

OPTICAL INTEGRATED CIRCUIT ELEMENT PACKAGE AND PROCESS FOR MAKING THE SAME

An optical integrated circuit element package comprises a substrate, an upper chip, a lower chip, an optical-transparent underfill, and a sealing compound. The substrate has a plurality of solder balls disposed on a surface of the substrate, a plurality of bonding pads electrically connected to the solder balls, a cover attached to the other surface of the substrate, and a cavity to expose the cover. The upper chip is provided with a plurality of bumps and is adhered to the exposed cover in the cavity by a thermal gap fill. The lower chip has a plurality of bonding pads electrically connected to the plurality of bumps of the upper chip and has a plurality of bumps electrically connected to the plurality of bonding pads of the substrate. The optical-transparent underfill is disposed between the lower chip and the upper chip. The sealing compound hermetically seals the space between the lower chip and the substrate.

Quad flat non-leaded package

The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is disposed around the die pad and is in contact with the semiconductor chip so as to increase the supporting to the semiconductor chip. The area of the semiconductor chip is larger than that of the die pad, and the semiconductor chip is attached to the die pad through its active surface. The molding compound encapsulates the lead frame, semiconductor chip and connecting wires, wherein part of the leads of the lead frame is exposed to the outside of the molding compound so as to be electrically connected to an external device.

Data backup method and device of cloud storage system

The invention discloses a data backup method and a data backup device of a cloud storage system. The data backup method of the cloud storage system comprises the following steps of: recording modification conditions of a target data set of a client; determining a difference part of current content and backed-up content of the data set according to the recorded modification condition; and after receiving a backup operation trigger instruction, performing backup operation on the determined difference part. By applying the technical scheme provided by the embodiment of the invention, backup of a user file system at the client can be effectively managed, the operation of a user is effectively facilitated in an automatic backup mode, and the manual cost on the user side is reduced. The backup of a large amount of repeated contents each time is avoided in an incremental backup mode, so that the occupation of backup time and backup space is reduced.

Semiconductor wafer and testing method for the same

A semiconductor wafer includes a plurality of areas and an array of dice disposed within each of the areas. The feature of the present invention is that at least two fiducial marks are disposed in each of the areas. The present invention further provides a method of testing a sawed semiconductor wafer.

[UNDER-BALL-METALLURGY LAYER]

An under-ball-metallurgy layer between a bonding pad on a chip and a solder bump made with tin-based material is provided. The under-ball-metallurgy layer at least includes an adhesion layer over the bonding pad, a nickel-vanadium layer over the adhesion layer, a wettable layer over the nickel-vanadium layer and a barrier layer over the wettable layer. The barrier layer prevents the penetration of nickel atoms from the nickel-vanadium layer and reacts with tin within the solder bump to form inter-metallic compound. This invention also provides an alternative under-ball-metallurgy layer that at least includes an adhesion layer over the bonding pad, a wettable over the adhesion layer and a nickel-vanadium layer over the wettable layer. The nickel within the nickel-vanadium layer may react with tin within the solder bump to form an inter-metallic compound.

Semiconductor package structure and method for manufacturing the same

A semiconductor package structure includes a substrate, a semiconductor die, a plurality of wires, and a molding compound. In this case, the semiconductor die is attached to the substrate. Each of the wires respectively has a center conductive layer, a dielectric layer, and a metal layer. Each of the center conductive layers connects the semiconductor die to the substrate. Each of the dielectric layers covers each of the center conductive layers, and the metal layers cover the dielectric layers. The molding compound encapsulates the semiconductor die and the wires. This invention also provides another semiconductor package structure, including a substrate, a semiconductor die, a plurality of wires, and a conductive molding compound. Each of the wires respectively has a center conductive layer and a dielectric layer. The conductive molding compound is made of a conductive material. Furthermore, the invention also provides a method for manufacturing the semiconductor package structure.

Method of making stacked chip package

A method of making a stacked chip package comprises the steps of: (a) placing a first chip onto a substrate in a manner that solder bumps on the first chip are aligned with corresponding flip-chip pads formed on a surface of the substrate; (b) reflowing the solder bumps; (c) attaching a second chip to the first chip through an adhesive layer; (d) curing the adhesive layer; (e) forming an underfill between the first chip and the substrate; (f) curing the underfill; (g) electrically coupling the second chip to corresponding wire-bondable pads formed on the surface of the substrate; and (h) encapsulating the first chip and the second chip against a portion of the surface of the substrate. This invention is characterized in that the adhesive layer is cured before underfilling thereby forming a protection layer on the first chip. Therefore, the cured adhesive layer can help the first chip to resist stresses created during curing process of the underfill, thereby reducing the problem of die cracking.

Multi-chip package structure

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting ...

Forked type four-barb thread hanging needle

The invention discloses a forked type four-barb thread hanging needle. The forked type four-barb thread hanging needle comprises a needle body and is characterized in that the tail portion of the needle body is provided with an opening, two pairs of opposite barbs are arranged at the opening, the tips of each pair of barbs just make contact with each other but do not apply force to each other, and two independent spaces are defined in the needle body by the two pairs of barbs in a surrounded mode; the sewing needle is made of high-strength elastic material perferably. When a thread is placed in the forked type four-barb thread hanging needle in use, two ends of the sewing thread need to be held only, and the middle portion of the sewing thread is pulled towards the inside of the swallow-tailed needle tail. If more than two sewing threads are used simultaneously, the sewing threads can be hung in the two spaces in the needle body respectively, and clamping teeth of the barbs can prevent ...

Multichip wafer-level package and method for manufacturing the same

A multichip wafer-level package includes a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding ring corresponding to the first bonding ring of the first chip. The bump ring is disposed between the first bonding ring of the first chip and the second bonding ring of the second chip for bonding the first and the second chips so as to form a cavity for accommodating ...

Zigzag threading needle

The invention discloses a zigzag threading needle. The zigzag threading needle comprises a needle body and a major forked stem and a minor forked stem of the needle tail, and is characterized in that a needle hole is composed of the major forked stem and the minor forked stem of the needle tail, the major forked stem is wound back in a zigzag mode and contacts the minor forked stem to form the closed needle hole, and the needle hole is matched with the diameter of sewing thread. Preferably, the zigzag threading needle is made of high-strength elastic materials and back bending potions of the major forked stem of the needle tail have good rebound elasticity. When a person threads the zigzag threading needle, the person only needs to put the middle section of the sewing thread into a concave portion where the two forked stems on the side surfaces of the needle tail cross, and pull the middle section of the sewing thread to the inside of the needle. The zigzag threading needle is easy to thread ...

Automatic design platform for sectional type capacitance liquid level meter

The invention relates to an automatic design platform for a sectional type capacitance liquid level meter and aims to achieve rapid design of products similar in structural feature and different in size and number of components. The automatic design platform achieves rapid design and development of the sectional type capacitance liquid level meter by the steps: firstly, establishing a parameterized three-dimensional model for the sectional type capacitance liquid level meter, and performing module division for the capacitance liquid level meter according to functions; secondly, computing liquid level meter parameters in an automatic design module; thirdly, assembling the liquid level meter automatically; and finally, adjusting product design by changing the parameters. Parameters of parts are defined by a parametric design method, size modification of relevant portions in graphs is completed automatically, and the three-dimensional model of the components is driven to regenerate, so that ...

BUMP FABRICATION PROCESS

A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at leastwith an opening that exposes the pre-formed bump. Solder material is deposited into the openings and then a reflow process is conducted fusing the solder ...

Wafer-level package with a cavity and fabricating method thereof

A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.

Bump fabrication method

A bump fabrication method is described. The method comprises the steps of providing a wafer having an active surface and a plurality of bonding pads formed on the active surface; respectively forming an under bump metallurgy layer onto the bonding pads, wherein the under bump metallurgy layer includes at least a wetting layer having an oxidized region and positioned at a top layer of the under bump metallurgy layer; patterning a masking layer on the active surface wherein the masking layer is provided with a plurality of openings to expose the wetting layers; removing the oxidized region of the wetting layer using ionic bombardment; fully forming a flux film on the active layer, wherein at least a portion of the flux film covers onto the wetting layer; filling a solder paste into the openings; performing a re-flow process to form a plurality of bumps after the solder paste melts so that the flux film removes the oxidized region of the wetting layer; and removing the masking layer.

Cleaning method of phosphorous gypsum conveying-pipe-shaped belt

The invention discloses a cleaning method of a phosphorous gypsum conveying-pipe-shaped belt. A motor drives pipe belt machine equipment; after feeding, the pipe-shaped belt conveys materials to the head portion of the pipe belt machine to discharge; a first grade scraper plate sweeper and a second grade scraper plate sweeper are placed on the position of a transmission rolling drum on the head portion of the pipe belt machine to clean the pipe-shaped belt, a cleaning device is installed below the pipe-shaped belt of a transition section of the head portion of the pipe belt machine through a turnabout rolling drum and a second transmission rolling drum to clean and dry the pipe-shaped belt. Dregs and water after the pipe-shaped belt is washed are connected through a water-collecting tank below a cleaning nozzle, and are connected to cycling settling basin through a pipeline. Supernatant water is used as water for cleaning the pipe-shaped belt, and the pipe-shaped belt is cleaned circularly ...

SIGNAL TRANSMITTING DEVICE, SIGNAL RECEIVING DEVICE, SIGNAL TRANSCEIVER DEVICE AND SIGNAL TRANSMISSION METHOD

Signal transmitting device, signal receiving device, signal transceiver device and signal transmission method use a conductive case as a transmission line to transmit/receive a modulated control signal or a sensing signal. The signal transmitting device, the signal receiving device and the signal transceiver device adopt a capacitive coupling unit as a media to transmit/receive the modulated signal, which makes the conductive case as a carrier when coupling the modulated signal onto the conductive case. When the signal is carried on the conductive case, the modulated signal is able to be captured and well transmitted. 1. A signal transmission method , operating on a conductive case , comprises the steps of:coupling a plurality of capacitive interfaces to a plurality of ends of said conductive case;modulating a transmission data as a modulated signal;transmitting said modulated signal to one of the ends of said conductive case through said capacitive interface;capturing said modulated signal from another one of the ends of said conductive case; anddemodulating said modulated signal as said transmission data for controlling a device coupled with said conductive case.2. The signal transmission method according to claim 1 , wherein said capacitive interface is capacitance or a coil.3. A signal transmitting device claim 1 , operating on a conductive case claim 1 , said device comprising:a frequency generation unit, for generating an operation frequency;a modulation unit, coupling to said frequency generation unit, for receiving an input data and using said operation frequency to modulate said input data as a modulated signal; anda capacitive coupling unit, coupling to said modulation unit and said conductive case, for transmitting said modulated signal to said conductive case.4. The signal transmitting device according to claim 3 , wherein said capacitive coupling unit is capacitance or a coil.5. The signal transmitting device according to claim 3 , further comprising ...

SYSTEM AND METHOD FOR EVALUATING TRANSMISSION PERFORMANCE RELATED TO NETWORK NODE, AND RELATED DEVICE

A system and a method for evaluating transmission performance related to a network node, and a related device are disclosed. The system includes a network node and a control node. The network node is configured to obtain a test packet, and process the test packet by using a virtual switch, to generate a mirrored packet corresponding to the test packet. The mirrored packet carries a generation timestamp and generation location information. The control node is configured to receive the mirrored packet from the network node, to evaluate, based on the mirrored packet, transmission performance of at least a part of link that is related to the network node and that is in a path. The control node obtain transmission performance of the network node in the path and the transmission performance of at least a part of link that is related to the network node. 1. A system for evaluating transmission performance related to a network node , wherein the system comprises the network node and a control node coupled to the network node , and the network node belongs to a path; andthe network node is configured to obtain a test packet, wherein the test packet comprises a 5-tuple corresponding to the path, and process the test packet by using a virtual switch, to generate a mirrored packet corresponding to the test packet, wherein the mirrored packet carries a generation timestamp and generation location information, the generation timestamp is used to indicate a timestamp of a time for generating the mirrored packet, and the generation location information is used to indicate a location at which the mirrored packet is generated; andthe control node is configured to receive the mirrored packet from the network node, to evaluate, based on the mirrored packet, the transmission performance of at least a part of a link that is related to the network node and that is in the path.2. The system according to claim 1 , wherein the transmission performance of the at least a part of the link that ...

DATA SHARING ARCHITECTURE

Techniques are disclosed relating to sharing data. A first computer system may receive data shared by a second computer system to permit the first computer system to perform processing of the data according to a set of policies. The first computer system may instantiate a verification environment in which to process the shared data. The first computer system may process a portion of the shared data by executing a set of processing routines to generate a result based on the shared data. The verification environment may verify whether the result is in accordance with the set of policies. The verification environment may determine whether to output the result based on the verifying and may send an indication of an outcome of the determining to the second computer system. The indication may be usable to determine whether to provide the first computer system with continued access to the shared data. 1. A method , comprising:receiving, by a verification environment executing on a data consumer system, shared data that is shared by a data provider system to permit the data consumer system to perform processing of the shared data according to a set of usage policies, wherein the verification environment acts as a sandbox in which processing results derived from the shared data are evaluated according to the set of usage policies before being sent outside the sandbox;processing, by the verification environment, a portion of the shared data using a set of processing routines to generate a processing result;detecting, by the verification environment, that the processing result is non-compliant with respect to the set of usage policies; andproviding, by the verification environment and to the data provider system, a report of the non-compliant processing result, wherein the report enables the data provider system to determine whether to provide the data consumer system with continued access to the shared data.2. The method of claim 1 , wherein the shared data is received in an ...

Method and apparatus for improving a bilingual corpus, machine translation method and apparatus

According to one aspect, there is provided an apparatus for improving a bilingual corpus including a plurality of sentence pairs of a first language and a second language and word alignment information of each of the sentence pairs, the apparatus comprises: an extracting unit for extracting a split candidate from word alignment information of a given sentence pair; a calculating unit for calculating split confidence of said split candidate; a comparing unit for comparing said split confidence and a pre-set threshold; and a splitting unit for splitting said given sentence pair at said split candidate in a case that said split confidence is larger than said pre-set threshold.

LOUDSPEAKER MODULE

Disclosed is a loudspeaker module, which comprises a loudspeaker unit and a module housing for accommodating the loudspeaker unit. The loudspeaker unit comprises a magnetic circuit assembly and a vibration assembly. The module housing comprises a polycarbonate plastic material layer and an elastomeric material layer having a compression amount. The polycarbonate plastic material layer forms an inner layer of the module housing. The elastomeric material layer is at least partially bonded on the outside of the polycarbonate plastic material layer to form the outer layer of the module housing. The polycarbonate plastic material layer and the elastomeric material layer are formed by double-shot injection molding. The loudspeaker module of the present disclosure can effectively solve the problem of the damage to the module housing caused by inflexible contact with other components of the whole machine, and can utilize the outer layer structure to change the resonance frequency, thereby effectively ameliorating the resonance phenomenon of the module housing and optimizing the product performance. 1. A loudspeaker module , comprising a loudspeaker unit and a module housing accommodating the loudspeaker unit , and the loudspeaker unit comprises a magnetic circuit assembly and a vibration assembly , whereinthe module housing comprises a polycarbonate plastic material layer and an elastomeric material layer, the elastomeric material layer having a compression amount;the polycarbonate plastic material layer forms an inner layer of the module housing;at least a part of the elastomeric material layer combines with the outside of the polycarbonate plastic material layer, and forms an outer layer of the module housing; andthe polycarbonate plastic material layer and the elastomeric material layer are formed by double-shot injection molding.2. The loudspeaker module according to claim 1 , wherein at least a part of the module housing is a composite structure of the polycarbonate ...

DATA SHARING ARCHITECTURE

Techniques are disclosed relating to sharing data. A first computer system may receive data shared by a second computer system to permit the first computer system to perform processing of the data according to a set of policies. The first computer system may instantiate a verification environment in which to process the shared data. The first computer system may process a portion of the shared data by executing a set of processing routines to generate a result based on the shared data. The verification environment may verify whether the result is in accordance with the set of policies. The verification environment may determine whether to output the result based on the verifying and may send an indication of an outcome of the determining to the second computer system. The indication may be usable to determine whether to provide the first computer system with continued access to the shared data. 1. A method , comprising:receiving, by a first computer system, data shared by a second computer system to permit the first computer system to perform processing of the data according to a set of policies specified by the second computer system;instantiating, by the first computer system, a verification environment in which to process the shared data;processing, by the first computer system, a portion of the shared data by executing a set of processing routines to generate a result based on the shared data;verifying, by the verification environment of the first computer system, whether the result is in accordance with the set of policies specified by the second computer system;determining, by the verification environment of the first computer system, whether to output the result based on the verifying; andsending, by the verification environment of the first computer system, an indication of an outcome of the determining to the second computer system, wherein the indication is usable by the second computer system to determine whether to provide the first computer system with ...

Brake Pedal Sleeve with Throttle Protection Function and Installation Method for Facilitating Installation

A brake pedal sleeve with throttle protection function for facilitating installation, including a main bracket plate, a auxiliary baffle plate, a protection rod, an anti-slip rubber pad, a brake pedal and an adjusting screw; wherein a supporting head, a square hook strip, a main baffle plate and the anti-slip rubber pad are provided on the main bracket plate; the protection rod is provided with a connecting rod, a limiting ring and a limiting screw, one end of the protection rod supporting shaft is provided with a circular head, and the protection rod supporting shaft passes through a washer, a protection rod through hole, a supporting head through hole and an inner hole of the spring ring, and the main bracket plate and the protection rod are combined together; the installation of the present disclosure is more convenient, quick and more stable. 110203040506011131740101211141319171817151610222320212024203132363034333337381235103060613530302223211516251924505160145051. A brake pedal sleeve with throttle protection function for facilitating installation , comprising a main bracket plate () , an auxiliary baffle plate () , a protection rod () , an anti-slip rubber pad () , a brake pedal () and an adjusting screw (); wherein a supporting head () , a square hook strip () , a main baffle plate () and the anti-slip rubber pad () are provided on the main bracket plate (); a supporting head through hole () is provided on the supporting head () , a square hook strip threaded hole () is provided below the square hook strip () , a main baffle plate threaded hole () is provided on the main baffle plate () , and a main baffle plate tooth () is provided inside the main baffle plate (); a small circular shaft sliding hole () and a large circular shaft sliding hole () are further provided in the main bracket plate (); a small circular shaft () and a large circular shaft () are provided on the auxiliary baffle plate () , an auxiliary baffle plate tooth () is provided on an inner ...

COMPOUND, COMPOSITION AND METHOD FOR TREATING AND/OR AMEOLIORATING KIDNEY DISEASE

Disclosed herein are compositions and methods for the treatment or prophylaxis of a subject having or susceptible to a kidney disease. The method includes the step of administering to the subject a compound of formula (I) in a dose of about 1 to 10 mg/Kg to improve the glomerular filtration rate (GFR) of the subject for at least 4 folds as compared to the GFR of the subject before treatment, 3. The method of claim 2 , further comprising administering to the subject an effective amount of lucidenic acid C (LAC) claim 2 , lucidenic acid B (LAB) claim 2 , lucidenic acid N (LAN) claim 2 , lucidenic acid E(LAE) claim 2 , lucidenic acid A (LAA) claim 2 , and lucidenic acid D(LAD).4. The method of claim 3 , wherein the LAC is administered to the subject in a dose of about 1 to 10 mg/Kg.5. The method of claim 3 , wherein the LAA and LADare respectively administered to the subject in a dose of about 2.5 to 25 mg/Kg.6. The method of claim 3 , wherein the LAEis administered to the subject in a dose of about 1.5 to 15 mg/Kg.7. The method of claim 3 , wherein the LAN and LAB are respectively administered to the subject in a dose of about 0.85 to 8.5 mg/Kg.8. The method of claim 2 , wherein the subject is a human.9. The method of claim 2 , wherein the kidney disease is acute kidney injury or chronic kidney disease. 1. Field of the InventionThe present disclosure relates to methods and compositions for the treatment or prophylaxis of kidney diseases, including acute kidney injury (AKI) and chronic kidney disease (CKD).2. Description of Related ArtAcute kidney injury (AKI) or acute renal failure is a syndrome characterized by the rapid loss of the kidney's excretory function and is typically diagnosed by the accumulation of end products of nitrogen metabolism (urea and creatinine) or decreased urine output, or both. It is the clinical manifestation of disorders such as high blood pressure and diabetes that affect the kidney acutely. AKI is common in hospital patients and very ...

Three-Transistor OTP Memory Cell

An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved. 1. An integrated circuit OTP (One-Time Programmable) memory cell comprising:a programming MOSFET having source/drain regions; andtwo pass transistors symmetrically located with respect to the programming MOSFET and each pass transistor connected to one of the source/drain regions of the programming MOSFET;whereby programmability of the memory cell is enhanced.2. The OTP memory cell of wherein the two pass transistors comprise:a first pass MOSFET having a gate electrode, and first and second source/drain regions in a substrate for the integrated circuit, the first source/drain region connected to a first conducting line, and the gate electrode controlling electrical connection between the first and second source/drain regions, the gate electrode part of a second conducting line;a second pass MOSFET having a gate electrode, and third and fourth source/drain regions in the substrate for the integrated circuit, the fourth source/drain region connected to the first conducting line, and the gate electrode controlling electrical connection between the third and fourth source/drain regions, the gate electrode connected to the second conducting line; and wherein the programming MOSFET comprises:a gate electrode between the second and third source/drain regions.3. The OTP memory cell of wherein the first conducting line comprises a bit line claim 1 , the second and third conducting line comprises word lines for respectively accessing and programming the memory cell.4. The OTP memory cell of wherein the first and second source/drain regions comprise N+ semiconductor regions.5. The OTP memory cell of wherein the second and third conducting ...

Rule set-based authorization for data pool

Techniques are described for pooling data originating from different entities into a data pool managed by a data pool management system for performing accurate and resource-efficient statistical and other data operations by entities. Techniques further include maintaining rule sets that govern access to the data sets of the data pool. The DPMS uses the rule sets to determine whether a particular data set, on which a particular operation is requested to be performed, qualifies as authorized data for the requesting entity. In an embodiment, the DPMS determines, based on one rule set, that the particular data set does not qualify as authorized data for the particular operation. The DPMS further determines that based on another rule set the particular data set does qualify as authorized data for the particular operation. Based on determining that authorizing rule set overrides the non-authorizing rule set, DPMS proceeds to performing the particular operation using the particular data set.

Method of making a low-profile wire connection for stacked dies

A stacked dies include a substrate, a lower chip and an upper chip. A plurality of upper wires have the bent portion at the bonding pad of the substrate to reduce the height and increase the strength of the wire so as to increase the reliability of the product and to increase the space between the lower wire and the upper wire for reduction cross talk. A method of making low profile upper wire connection comprising steps of: after an upper wire is connected to a first bonding point, a capillary is moved straight up a first distance, and then the capilairy is moved away from a second bonding point thus making a first reverse action to bend the wire in an appropriate angle so as to form the first bent point. The capillary is again raised a second distance and moved downward a second reverse action to bend the upper wire by an appropriate angle so as to form the second bent point. The capillary is raised a third distance and then the capillary is moved away the second bonding point thus making an action to bend the wire in an appropriate angle so as to form the third bent point. The capillary is further raised a fourth distance. The capillary is raised to the second bonding point to extend the length of two wire ends which is enough to make a wire loop, amd then the capillary is moved down to the second bonding point where the bonding is performed.

Process for the preparation of a lactic acid-based polyurethane

Thermal-enhance package and manufacturing method thereof

Micromachine package and method for manufacturing the same

A micromachine package includes a first chip, a second chip, a spacer ring, a plurality of bumps, a plurality of leads, and an encapsulant. The first chip has at least one moveable structure. The second chip has at least one electrode for cooperating with the moveable structure of the first chip, and a plurality of pads disposed on one side of the second chip. The spacer ring is disposed between the first chip and the opposite second chip and surrounds the moveable structure. The bumps are disposed on the pads. The lead has a first surface, which is connected to the bumps, and an opposite second surface. The encapsulant encapsulates the first chip, the second chip, the spacer ring, the bumps, and the first surfaces of the leads, and the second surfaces of the leads are exposed out of the encapsulant.

An oil transfer device with anti-sticking wall

The invention discloses an oil transfer device with anti-sticking wall. The device comprises a plurality of storage spaces arranged at intervals, wherein oil storage barrels are arranged in the storage spaces and filled with non-Newtonian fluids. Non-Newtonian fluid is coated on the outer side of the oil storage barrel, and the outlet end of the oil storage barrel extends out of the storage space and is provided with an oil discharge valve. A pressure mechanism including a platen is arranged at the bottom of the oil storage barrel, and the oil storage barrel and the platen are correspondingly arranged up and down. A first sealing sleeve is arranged between the edge of the platen and the inner side wall of the storage space, and the non-Newtonian fluid is located at the top of the platen. The invention can greatly reduce the probability of oil leakage in the event of a collision and reduce the safety risks, and the residual oil can be fully exported by the oil discharge valve, so that there is no residue after the transfer, and by providing the oil storage barrel with an outer barrel, an inner barrel and a limit spring, the collision force can be cushioned in the event of a collision and the oil shaking inside the inner barrel can be reduced. 1 /3 31 3 7 6 12 13 Figure 1. The structural diagram of the oil transfer device with anti sticking wall of the invention 9 10 12 13 6 8 11 20 21 22 29 31 32 q 33 A t 5 H t8 t 1 30 Figure 2. The cross-sectional view of the oil transfer device of the anti sticking wall of the invention

Chip scale package

A chip scale package mainly comprises a semiconductor chip disposed on an upper surface of a substrate and sealed by a package body. The package body comprises a resin base material divided into a first region and a second region. The resin base material contains a plurality of filler particles having the percentage by weight of the filler particles in the first and second regions being different. Thus, in accordance with the present invention, the package provides better buffering effect for stresses due to CTE mismatch between the substrate and the chip, and significantly reduces the moisture from surrounding diffusing into the package thereby reducing the problems of delamination or die-cracking.

Semiconductor package and method for manufacturing the same

A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

Wafer-level package structure

A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

System and method for evaluating transmission performance related to network node and related device

Data sharing architecture

Leadless semiconductor package

A leadless semiconductor package disposed on a substrate comprises a chip, a plurality of leads, wherein each lead has a metal layer and a first molding compound formed on the metal layer, a second molding compound disposed on the first molding compound, and a chip paddle for carrying the chip. The leads are connected to the chip by wire bonding technique. The metal layer is exposed out of the first molding compound; and the second molding compound encapsulates the chip with the chip paddle exposed out of the second molding compound.

Semiconductor package

A semiconductor package has a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. Each tie bar extends from a corner of the die pad to a corresponding corner of the leadless semiconductor package. The semiconductor chip, the leads and the tie bars are encapsulated in a package body wherein the backside surface of the leads is exposed from the lower surface of the semiconductor package. All the tie bars of the semiconductor package are embedded in the package body except a part of at least one tie bar or an odd number of tie bars exposed from the lower surface of the semiconductor package to work as an indicial mark.

Remote controller

Packaging structure and method of semiconductor chip

Compound, composition and method for treating and/or ameoliorating kidney disease

Disclosed herein are compositions and methods for the treatment or prophylaxis of a subject having or susceptible to a kidney disease. The method includes the step of administering to the subject a compound of formula (I) in a dose of about 1 to 10 mg/Kg to improve the glomerular filtration rate (GFR) of the subject for at least 4 folds as compared to the GFR of the subject before treatment, The method further includes the step of administering to the subject an effective amount of lucidenic acid C (LAC), lucidenic acid N (LAN), lucidenic acid E 2 (LAE 2 ), lucidenic acid A (LAA), and lucidenic acid D 2 (LAD 2 ).

Thermal- enhance MCM package

Bump fabrication process

The present invention provides a bump fabrication process. After forming an under bump metallurgy (UBM) layer and bumps in sequence over the substrate, the under bump metallurgy layer that is not covered by the bumps is etched with an etchant. The etchant mainly comprises sulfuric acid and de-ionized water. The etchant can etch the nickel-vanadium layer of the UBM layer without damaging the bumps.

Bi-directional power line led light control system

Semiconductor device capable of avoiding the offset of the wire and its manufacturing method

Grounding device

Continuous wire bonding structure and method

The packaging structure and method for manufacturing the flip-chip having controlled collapse solder bumps on a polymer substrate

Stacked chip package structure

Bi-directional power line LED light control system

Method for preventing burnt fuse pad from further electrical connection

A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed. and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.

Data sharing architecture

Techniques are disclosed relating to sharing data. A first computer system may receive data shared by a second computer system to permit the first computer system to perform processing of the data according to a set of policies. The first computer system may instantiate a verification environment in which to process the shared data. The first computer system may process a portion of the shared data by executing a set of processing routines to generate a result based on the shared data. The verification environment may verify whether the result is in accordance with the set of policies. The verification environment may determine whether to output the result based on the verifying and may send an indication of an outcome of the determining to the second computer system. The indication may be usable to determine whether to provide the first computer system with continued access to the shared data.

Brake pedal sleeve with throttle protection function and installation method for facilitating installation

A brake pedal sleeve with a throttle protection function and for facilitating installation of the throttle protection, including a main bracket plate, an auxiliary baffle plate, a protection rod, an anti-slip rubber pad, a brake pedal and an adjusting screw; wherein a supporting head, a square hook strip, a main baffle plate and the anti-slip rubber pad are provided on the main bracket plate; the protection rod is provided with a connecting rod, a limiting ring and a limiting screw, one end of the protection rod supporting shaft is provided with a circular head, and the protection rod supporting shaft passes through a washer, a protection rod through hole, a supporting head through hole and an inner hole of the spring ring, and the main bracket plate and the protection rod are combined together; the installation of the present disclosure is more convenient, quick and more stable.

Intelligent electronic door lock

Semiconductor package structure with ground and method for manufacturing thereof

訊號發射裝置

[bump and fabricating process thereof]

A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 μm is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.

Manufacturing method for semiconductor chip packaging structure with no outer leads

Rule set-based authorization for data pool

Techniques are described for pooling data originating from different entities into a data pool managed by a data pool management system for performing accurate and resource-efficient statistical and other data operations by entities. Techniques further include maintaining rule sets that govern access to the data sets of the data pool. The DPMS uses the rule sets to determine whether a particular data set, on which a particular operation is requested to be performed, qualifies as authorized data for the requesting entity. In an embodiment, the DPMS determines, based on one rule set, that the particular data set does not qualify as authorized data for the particular operation. The DPMS further determines that based on another rule set the particular data set does qualify as authorized data for the particular operation. Based on determining that authorizing rule set overrides the non-authorizing rule set, DPMS proceeds to performing the particular operation using the particular data set.

Method and structure for forming flip chip with collapse-controlled solder bumps on a substrate

A packaging process providing a die with C4 solder bumps and a polymer substrate first. It then jets the melted second solder onto each of the C4 solder bumps forming a second solder bump. After reflowing and leveling the solder bumps, the die is flipped and combined with the substrate. Then heat treatment proceeds with the combination of the die and the substrate forming a flip chip package with collapse-controlled solder bump on the polymer substrate.

Bumping process

Mobile phone

Multi-chip package structure

Computer front bezel

Testing socket for integrated circuit testing system

Utilizing mould sealing glue ball lattice array sealing packaging element

The molding apparatus and method of the ball grid array semiconductor packaging structure

Heat dissipation enhanced BGA package structure

Substrate structure of ball grid array package body

Computer enclosure

Rule set-based authorization for data pool

Techniques are described for pooling data originating from different entities into a data pool managed by a data pool management system for performing accurate and resource-efficient statistical and other data operations by entities. Techniques further include maintaining rule sets that govern access to the data sets of the data pool. The DPMS uses the rule sets to determine whether a particular data set, on which a particular operation is requested to be performed, qualifies as authorized data for the requesting entity. In an embodiment, the DPMS determines, based on one rule set, that the particular data set does not qualify as authorized data for the particular operation. The DPMS further determines that based on another rule set the particular data set does qualify as authorized data for the particular operation. Based on determining that authorizing rule set overrides the non-authorizing rule set, DPMS proceeds to performing the particular operation using the particular data set.

Ｇｐｓ高速公路計程輔助裝置及其方法

一種GPS高速公路計程輔助裝置，其包括定位單元、顯示單元、儲存單元與處理單元。其中，定位單元接收GPS訊號而產生定位座標資料。儲存單元儲存有計程應用程式與高速公路之位置資料，高速公路之位置資料包含高速公路座標資料與交流道座標資料。處理單元執行計程應用程式後，比對定位座標資料與高速公路之位置資料，當定位座標資料符合高速公路之高速公路座標資料與交流道座標資料其中之一時，開始進行高速公路計程收費之計算，並將結果紀錄於儲存單元，並顯示於顯示單元。

Thermal enhance MCM package and the manufacturing method thereof

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氣密檢驗治具設備

一種氣密檢驗治具設備，係包含了一氣密式蓋體、一氣密裝置及一壓力感測計，其中該氣密式蓋體係配置有一可與待測物規格相符、並覆蓋於待測物上之氣密空間，以使該待測物能夠完全被密合於該氣密空間內，另外該氣密裝置係包含有一相接至該氣密式蓋體之氣管、一真空幫浦及一真空壓力表，其中該氣管一端係與該真空幫浦及該真空壓力表相連接，而該氣管另一端則相接於該氣密式蓋體，因此當該真空幫浦向該氣密空間進行抽真空時，即可藉由該真空壓力表以及與該氣密式蓋體之氣密空間相接之壓力感測計，進行交互比對判斷該待測物是否有達到氣密規格之要求。

Wire bonding method for integrated circuit die

Airtight inspection fixture equipment

Leadless semiconductor chip package structure

Computer front bezel

Electric conveying device for data printing slips of depth sounder

The present invention discloses an electric conveying device for data printing slips of a depth sounder, comprising: a working plate, a micro motor and a foot switch. A first side plate and a second side plate are installed in parallel on both ends of the top surface of the working plate, and a first long hole and a second long hole are respectively arranged on both sides of the top surface; a first circular plate is rotatably installed on the inner side of the first side plate; a second circular plate is rotatably installed on the inner side of the second side plate; the micro motor is fixed on the top surface of the working plate and an output end of the micro motor is fixedly connected with the center of the first circular plate; and the foot switch is electrically connected with the micro motor. In the electric conveying device for the data printing slips of the depth sounder disclosed in the present invention, the starting and closing of the micro motor are controlled through the foot switch. When the micro motor is started, the output shaft drives the first circular plate to rotate and the first circular plate drives the data printing slips of the depth sounder to rotate. The hands of working personnel are freed, and the hands of the working personnel can fully perform verification recording and anomaly marking, thereby increasing the efficiency of data review. Drawings of Description 4 11 2g 133 Fig. 1 1

Front bezel for computer enclosure

Bumping process

Die pad structure

免用鑰匙防盜系統

免用鑰匙防盜系統

智慧型電子暗鎖系統

Computer front bezel

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Semiconductor testing system with precise positioning interface

Computer front bezel

Multi-chip module and method for fabricating the same

Semiconductor testing system with improved precise position auxiliary interface

一种腕式血压检测设备

本实用新型公开了一种腕式血压检测设备，包括第一系带、腕带、电子血压计和第二系带,所述腕带的外表面中部安装有电子血压计，且电子血压计上设置有电子血压计的上表面设置有显示屏幕，所述腕带内部中间设置有检测区，且检测区的左右边均缝制有一组固定区，所述左侧的固定区的左边缝制有第一系带，所述腕带内侧面左侧开设有第五出口和第六出口，且腕带内侧面右侧开设有第三出口和第四出口。该腕式血压检测设备，整体结构设置更加合理，在腕带的左右部设置有弹性的系带结构，通过系带式进行绑定，系上轻松简单，解开更快速，无需费力，还避免了噪音干扰，使用很便捷，适用人群也会更广，更方便用户血压检测，检测体验更轻松舒适。

Computer front bezel

Computer front bezel

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Computer front bezel

Computer front bezel

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Computer front bezel