TOUCH SENSING APPARATUS

The present invention provides a touch sensing apparatus including a plurality of pins, a logic control module, and at least one driving/sensing control module. The logic control module generates a plurality of control signals having different control timings. Each driving/sensing control module is coupled with the logic control module and the pins, wherein the driving/sensing control module receives a first control signal of the control signals from the logic control module and controls the pins to execute a plurality of pin functions according to a first control timing of the first control signal, so that the pins simultaneously sense a plurality of analog data from a conductive thin film sensor. 1. A touch sensing apparatus , comprising:a plurality of pins;a logic control module generating a plurality of control signals having different control timings; andat least one driving/sensing control module coupled with the logic control module and the pins, wherein the driving/sensing control module receives a first control signal of the control signals from the logic control module and controls the pins to execute a plurality of pin functions according to a first control timing of the first control signal, so that the pins simultaneously sense a plurality of analog data from a conductive thin film sensor.2. The touch sensing apparatus of claim 1 , wherein the conductive thin film sensor comprises a plurality of scanning lines claim 1 , the pins respectively scan one of the scanning lines for sensing the analog data.3. The touch sensing apparatus of claim 1 , wherein the pin functions comprise a driving function claim 1 , a sensing function claim 1 , a grounding function claim 1 , and a floating function.4. The touch sensing apparatus of claim 1 , further comprising:at least one storage control module, wherein each storage control module comprises a plurality of storage capacitors, the at least one storage control module is coupled with the logic control module and the ...

Touch sensing apparatus

A touch sensing apparatus is disclosed. The touch sensing apparatus includes a logic control module, at least one storage control module, and at least one decoding control module. The logic control module is used to generate a plurality of control signals having different control timings. The plurality of control signals includes a storage control signal and a decoding control signal. Each storage control module includes a plurality of storage capacitors, and respectively stores each of sensed voltages in different storage capacitors at different times according to a storage control timing of the storage control signal. The sensed voltages are analog data sensed from scan lines of an ITO sensor. The decoding control module is used to decode the sensed voltages stored in the storage capacitors according to a decoding control timing of the decoding control signal to output the decoded analog data.

TOUCH SENSING APPARATUS

A touch sensing apparatus is disclosed. The touch sensing apparatus includes a logic control module, at least one storage control module, and at least one decoding control module. The logic control module is used to generate a plurality of control signals having different control timings. The plurality of control signals includes a storage control signal and a decoding control signal. Each storage control module includes a plurality of storage capacitors, and respectively stores each of sensed voltages in different storage capacitors at different times according to a storage control timing of the storage control signal. The sensed voltages are analog data sensed from scan lines of an ITO sensor. The decoding control module performs analog adding process to the sensed voltages stored in the storage capacitors according to a decoding control timing of the decoding control signal to output decoded analog data with high signal-to-noise ratio (SNR). 1. A touch sensing apparatus , comprising:a logic control module, for generating a plurality of control signals having different control timings, and the plurality of control signals comprising a storage control signal and a decoding control signal;at least one storage control module, coupled to the logic control module, each storage control module comprising a plurality of storage capacitors and respectively storing each of sensed voltages in different storage capacitors at different times according to a storage control timing of the storage control signal, wherein the sensed voltages are analog data sensed from scan lines of an ITO sensor; andat least one decoding control module, coupled to the logic control module and the at least one storage control module, for performing an analog adding process to the sensed voltages stored in the storage capacitors according to a decoding control timing of the decoding control signal to output a decoded analog data with high signal-to-noise ratio.2. The touch sensing apparatus of claim ...

CONTROL DEVICE FOR TOUCH PANEL AND SIGNAL PROCESSING METHOD THEREOF

The present invention discloses a control device for a touch panel. The touch panel comprises a plurality of X-directional sensing lines and a plurality of Y-directional sensing lines arranged in a staggered manner. The control device comprises a clock generation circuit, a selection module, an analog to digital conversion circuit, and a control unit. The selection module selects sensing lines to be measured from the X-directional sensing lines and Y-directional sensing lines. The control unit controls the operation mode of the analog to digital conversion circuit. The analog to digital conversion circuit outputs an n-bit digital signal when it operates in a normal mode, and outputs an m-bit digital signal when it operates in a detecting mode, wherein n>m. According to the control device of the present invention, valid data is output in the presence of noise. 1. A control device for a touch panel , wherein the touch panel comprises a plurality of X-directional sensing lines and a plurality of Y-directional sensing lines , the X-directional sensing lines and the Y-directional sensing lines are arranged in a staggered manner , and the control device comprising:a selection module, selects a plurality of sensing lines to be measured from the X-directional sensing lines and the Y-directional sensing lines;an analog to digital conversion circuit, coupled with the selection module for receiving voltages of the sensing lines to be measured, wherein the analog to digital conversion circuit converts the voltages into different bits of a sequence digital signal, when the analog to digital conversion circuit operates in a normal mode, the analog to digital conversion circuit outputs a n-bit digital signal, when the analog to digital conversion circuit is operates in a detecting mode, the analog to digital conversion circuit outputs a m-bit digital signal, and n>m; anda control unit, configured for controlling the analog to digital conversion circuit to operate either in the ...

DETECTION CIRCUIT AND DETECTION METHOD FOR TOUCH-SENSING PANEL

A detection circuit for a touch-sensing panel includes a successive approximation register analog-to-digital converter (SAR-ADC) and a timing control device. The SAR-ADC is configured to detect a coupling voltage to generate a multi-bit digital detection value. The timing control device is configured to control a detection time of each bit for the SAR-ADC. 1. A detection circuit for a touch-sensing panel , comprising:a successive approximation register analog-to-digital converter (SAR-ADC), configured to detect a coupling voltage to generate a multi-bit digital detection value; anda timing control device, configured to control a detection time of each bit for the SAR-ADC.2. The detection circuit according to claim 1 , further comprises a control register set claim 1 , configured to store the detection time of each bit for the SAR-ADC.3. The detection circuit according to claim 1 , wherein the timing control device is configured to control the detection time of each bit for the SAR-ADC such that the detection time of a more significant bit is longer than that of a less significant bit for the SAR-ADC.4. The detection circuit according to claim 1 , wherein the SAR-ADC generates the multi-bit digital detection value in response to a clock signal.5. The detection circuit according to claim 4 , wherein a duty cycle of the clock signal is controlled by the timing control device.6. A detection method for a touch-sensing panel claim 4 , comprising the steps of:detecting a coupling voltage of the touch-sensing panel, and generating a multi-bit digital detection value, wherein the digital detection value is generated from the most significant bit to the least significant bit in order, and a detection time of a more significant bit of the digital detection value is longer than that of a less significant bit of the digital detection value.7. The detection method according to claim 6 , further comprising the steps of:determining and storing a detection time for each bit of the ...

SHALE GAS OPERATION METHOD

A method for performing shale gas operation is disclosed. The method may include drilling a first well, performing a fracturing operation in the well, recovering shale gas from the first well, supplying at least part of the shale gas recovered from the well to an electrical generator, generating electricity using the generator, and transferring the generated electricity to drilling equipment used to drill a second well. 1. A method for performing shale gas operation , comprising:drilling a first well;performing a fracturing operation in the well;recovering shale gas from the first well;supplying at least part of the shale gas recovered from the well to an electrical generator;generating electricity using the generator;transferring the generated electricity to drilling equipment used to drill a second well.2. A method according to claim 1 , wherein the drilling equipment is also provided with an external power supply.3. A method according to claim 1 , wherein the drilling equipment comprises a first drilling machine and a second drilling machine.4. A method according to claim 3 , comprising:drilling a first substantially straight well section with the first drilling machine at a first location;moving the first drilling machine to a second location;drilling a second substantially straight well section with the first drilling machine at the second location;drilling a first substantially horizontal well section from the substantially straight well section at the first location using the second drilling machine;moving the second drilling machine to the second location; anddrilling a second substantially horizontal well section from the substantially vertical well section at the second location using the second drilling machine.5. A method according to claim 1 , further comprising providing the generated electricity to a fracturing vehicle.6. A method according to claim 5 , wherein the fracturing vehicle comprises hydraulic sand blast perforation equipment claim 5 , the ...

FOURIER TRANSFORM COMPUTATION FOR DISTRIBUTED PROCESSING ENVIRONMENTS

Fourier transform computation for distributed processing environments is disclosed. Example methods disclosed herein to compute a Fourier transform of an input data sequence include performing first processing on the input data sequence using a plurality of processors, the first processing resulting in an output data sequence having more data elements than the input data sequence Such example methods also include performing second processing on the output data sequence using the plurality of processors, the output data sequence being permutated among the plurality of processors, each of the processors performing the second processing on a respective permutated portion of the output data sequence to determine a respective, ordered segment of the Fourier transform of the input data sequence. 1. A method to compute a Fourier transform of an input data sequence , the method comprising:performing first processing on the input data sequence using a plurality of processors, the first processing resulting in an output data sequence having more data elements than the input data sequence; andperforming second processing on the output data sequence using the plurality of processors, the output data sequence being permutated among the plurality of processors, each of the processors performing the second processing on a respective permutated portion of the output data sequence to determine a respective, ordered segment of the Fourier transform of the input data sequence.2. A method as defined in wherein performing the first processing on the input data sequence comprises:convolving the input sequence with a window function; andperforming Fourier transforms on respective segments of a second output data sequence resulting from convolving the input sequence with the window function.3. A method as defined in wherein the window function is specified by an alias error and a condition number claim 2 , and wherein an accuracy of the Fourier transform of the input data sequence is based ...

PROCESSORS, METHODS, AND SYSTEMS FOR A CONFIGURABLE SPATIAL ACCELERATOR WITH PERFORMANCE, CORRECTNESS, AND POWER REDUCTION FEATURES

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. At least one of the plurality of processing elements includes a plurality of control inputs. 118-. (canceled)19. The processor of claim 20 , wherein:the at least one of the plurality of processing elements is configurable as a floating-point multiplier, at least an other of the plurality of processing elements is configurable as a floating-point adder, and the at least one and the at least an other of the plurality of processing elements are coupled together to perform a fused multiply-add.20. A processor comprising:a plurality of processing elements, wherein at least one of the processing elements is to perform a floating-point operation with selectable precision control; andan interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. This invention was made with Government support under contract number H98230A-13-D-0124 awarded by the Department of Defense. The Government has ...

Suppressing Interaction Between Bonded Particles

A method for managing flow of particles into an array of pairwise-point-interaction-module includes receiving a first set of particles into a first queue. The first set is a proper subset of a second set of particles that comprises all particles that are to be passed into an array of pairwise-point-interaction-modules during a current time period. Prior to having received all particles from the second set, particles from the first set are allowed to pass from the first queue into the array. 1. A method for managing flow of particles into an array of pairwise-point-interaction-modules , said method comprising receiving a first set of particles into a first queue , said first set of particles being a proper subset of a second set of particles , wherein said second set of second particles comprises all particles that are to be passed into an array of pairwise-point-interaction-modules during a current time period , and prior to having received all particles from said second set , allowing said particles from said first set to pass from said first queue into said array.2. The method of claim 1 , further comprising continuing to load particles from said first set into said array as additional particles from said second set are received into said first queue.3. The method of claim 1 , further comprising receiving a third set of particles into a second queue claim 1 , wherein said third set of particles comprises all particles that are to only be loaded into said array during said current time period claim 1 , and wherein allowing said particles from said first set to pass from said first queue into said array occurs only after all particles from said third set have been loaded into said array.4. The method of claim 1 , further comprising receiving a third set of particles into second and third queues claim 1 , wherein said third set of particles comprises all particles that are to be loaded into said array during said current time period claim 1 , and wherein allowing ...

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads. 1. A graphics processing unit (GPU) comprising:a plurality of memory controllers;cache memory coupled with the plurality of memory controllers; a register file; and', 'circuitry coupled with the register file, the circuitry including a first core to perform a mixed precision matrix operation and a second core to perform, in response to a single instruction, multiple compute operations, wherein the multiple compute operations include a first operation to perform a fused multiply-add and a second operation to apply a rectified linear unit function to a result of the first operation., 'a graphics multiprocessor coupled with the cache memory and the plurality of memory controllers, the graphics multiprocessor having a single instruction, multiple thread (SIMT) architecture, wherein the graphics multiprocessor includes2. The GPU as in claim 1 , wherein the first operation and the second operation are single instruction multiple data (SIMD) operations.3. The GPU as in claim 1 , wherein the multiple compute operations are performed on input in a 16-bit floating-point format having a 1-bit sign and an 8-bit exponent.4. The GPU as in claim 3 , wherein the second core includes a dynamic precision processing resource that is configurable to automatically convert input in a 32-bit floating point format to the 16-bit floating-point format in conjunction with execution of the single instruction.5. The GPU as in claim 4 , wherein the dynamic precision processing resource includes ...

COMPUTE OPTIMIZATION MECHANISM

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 8-bit and/or 32 bit signed or unsigned integer elements. 1. A graphics processor comprising:a memory controller;a level-two (L2) cache memory coupled with the memory controller; anda multiprocessor coupled to the memory controller, the multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading, the multiprocessor including a scheduler, a plurality of processing cores, and a shared memory coupled to the plurality of processing cores, wherein the scheduler is a hardware scheduler to schedule an instruction for execution by the plurality of processing cores and the plurality of processing cores include a mixed precision core to perform a mixed precision matrix multiply and accumulate operation in response to the instruction, wherein to perform the mixed precision matrix multiply and accumulate operation, the mixed precision core is to perform an operation D=A*B+C, wherein A, B, C, and D are matrix elements, A and B are 8-bit integer elements, and C is a 32-bit integer element.2. The graphics processor as in claim 1 , the multiprocessor additionally including a register file to store operands.3. The graphics processor as in claim 2 , wherein the multiprocessor is to load data associated with operands of the operation D=A*B+C into the register file from memory.4. The graphics processor as in claim 3 , wherein the multiprocessor is to load data associated with operands of the operation D=A*B+C into the register file from shared memory.5. The graphics processor as in claim 4 , wherein the multiprocessor is to load data associated with operands of the operation D=A*B+C into the register file from the L2 cache memory in response to the load from the shared memory.6. The graphics processor of claim 1 , wherein the ...

INTEGRATED CIRCUIT AUTOMATIC TEST SYSTEM AND INTEGRATED CIRCUIT AUTOMATIC TEST METHOD STORING TEST DATA IN SCAN CHAINS

An integrated circuit (IC) automatic test system and an IC automatic test method storing test data in scan chains are revealed. The automatic test system includes at least one scan chain, a test controller and a test decompressor connected. Each scan chain consists of a storage portion with a plurality of scan units and a scan input corrector. The storage portion is for storing test data and the scan input corrector is used to adjust test patterns to be shifted into the scan chains. The test controller is for control of test flow while the test decompressor reconstructs and decompresses the test data stored in the storage portions of the scan chains to generate test patterns for the circuit under test. Thereby the IC electrical test is performed automatically and the test cost and the test cost is reduced. 2. The system as claimed in claim 1 , wherein the scan chains output at least one test data after reset.3. The system as claimed in claim 1 , wherein the test decompressor further includes a buffer used for temporary storage of test data from the scan chains and reconstruction of the test data to generate compressed test pattern.4. The system as claimed in claim 1 , wherein the scan input corrector is selected from the group consisting of an XOR gate and an XNOR gate.5. The system as claimed in claim 1 , wherein the scan input corrector is used to adjust the test pattern to be shifted into the scan chains.6. The system as claimed in claim 1 , wherein the scan input corrector adjusts a test pattern shifted from the decompressor by using shift-out test data from the storage portion after reset of the storage portion; thus a test pattern output from the scan input corrector to the scan units of the storage portion is equal to the test pattern shifted from the decompressor.7. An integrated circuit automated test method that stores test data in scan chains comprising the steps of:Step 1: outputting a reset signal to scan chains by a test controller for resetting the ...

SYSTEMS, METHODS, AND APPARATUSES UTILIZING AN ELASTIC FLOATING-POINT NUMBER

Systems, apparatuses, and methods utilizing an elastic floating-point encoding format are described. In particular, at least one operand of an instruction is to store, or stores, data in the elastic floating-point encoding format. In some implementations, the floating-point encoding format includes a sign bit, a self-identifying field, a mantissa, and a non-overlapping exponent range. 1. An apparatus comprising: an instruction to include an opcode defining at least one operation to be performed and at least two fields to identify a first operand and a second operand, wherein the operands are to store data in a floating-point encoding format that is to include fields for a sign bit, a self-identifying field, a mantissa, and a non-overlapping exponent range, and', 'the identified first and second operands into at least two real values, each real value having a standard exponent and mantissa field;, 'decoder circuitry to decodeexecution circuitry to execute the decoded instruction according to the defined at least one operation to be performed using the at least twos real value of the identified first and second operands.2. The apparatus of claim 1 , wherein the encoded floating-point format is to include a bit pattern to identify an infinite number.3. The apparatus of claim 1 , wherein the encoded floating-point format is to include a bit pattern to identify a sub-normal number.4. The apparatus of claim 1 , wherein the encoded floating-point format is to include a bit pattern to a non-zero mantissa.5. The apparatus of claim 1 , wherein the exponent range is at least 3 bits and the mantissa width is at least 7 bits.6. The apparatus of claim 1 , wherein the floating-point encoding format one or 16-bits claim 1 , 32-bit claim 1 , 64-bit claim 1 , 128-bit claim 1 , and 256-bit in size.7. The apparatus of claim 1 , wherein a most significant bit of the floating point encoding format is the sign bit.8. The apparatus of claim 1 , wherein the opcode is to indicate the use of ...

DRIVING CIRCUIT AND OPERATING METHOD THEREOF

A driving circuit includes a data comparator, a data processor and a driver. The data comparator determines whether a second row of image data is the same with a previous first row of image data. If YES, the data comparator outputs a disable signal, then the data processor stops operating according to the disable signal and outputs an indicating signal, and the driver outputs a previous first row of output image data to a panel according to the indicating signal; if NO, the data comparator outputs the second row of image data to replace the previous first row of image data, then the data processor processes the second row of image data to generate a second row of output image data, and the driver outputs the second row of output image data to the panel to replace the previous first row of output image data. 1. A driving circuit , disposed in a display apparatus and coupled to a display panel , the driving circuit comprising:a data comparator, for determining whether a second row of image data is the same with a previous first row of image data, wherein if the second row of image data is the same with the first row of image data, the data comparator outputs a disable signal; if the second row of image data is different from the first row of image data, the data comparator outputs the second row of image data to replace the first row of image data;a data processor, coupled to the data comparator, wherein when the data processor receives the disable signal from the data comparator, the data processor stops operating according to the disable signal and outputs an indicating signal; when the data processor receives the second row of image data from the data comparator, the data processor processes the second row of image data to generate a second row of output image data; anda driver, coupled between the data processor and the display panel, wherein when the driver receives the indicating signal from the data processor, the driver outputs a previous first row of output ...

Auxiliary oil pump system

An auxiliary oil pump system for a gearbox, comprising: an auxiliary battery; a controller electrically connected to the auxiliary battery; and an auxiliary oil pump driven by the controller using a self-adaptive process, wherein the self-adaptive process comprises: the controller receives current operational pressure signal and compared the current operational pressure signal to a pressure threshold; if the current operational pressure signal is bigger than the pressure threshold, the auxiliary oil pump keeps current rotational speed; if the current operational pressure signal is smaller than the pressure threshold, the auxiliary oil pump improves the rotational speed by a pre-determined speed. 1. An auxiliary oil pump system for a gearbox , comprising:an auxiliary battery;a controller electrically connected to the auxiliary battery; andan auxiliary oil pump driven by the controller using a self-adaptive process, the controller receives current operational pressure signal and compared the current operational pressure signal to a pressure threshold;', 'if the current operational pressure signal is bigger than the pressure threshold, the auxiliary oil pump keeps current rotational speed;', 'if the current operational pressure signal is smaller than the pressure threshold, the auxiliary oil pump improves the rotational speed by a pre-determined speed., 'wherein the self-adaptive process comprises2. The auxiliary oil pump system of claim 1 , wherein the auxiliary oil pump is further driven by the controller using a normal process claim 1 , wherein the controller receives a first signal and a second signal claim 1 , and inquires the corresponding necessary output torque of the auxiliary oil pump claim 1 , and then compares the corresponding necessary output torque of the auxiliary oil pump to a torque threshold.3. The auxiliary oil pump system of claim 2 , wherein the first signal is target rotational speed and the second signal is current operational temperature of oil ...

Fracturing Pump

The invention discloses a fracturing pump, comprising a cooling device and a control device, wherein a motor is connected on an shaft of the fracturing pump, the cooling device comprises an air-cooled device for cooling a rotor of the motor and a water-cooled device for cooling a stator of the motor, and the control device is connected with the motor and the cooling device, respectively. The fracturing pump in the invention adopts a structure directly driven by the motor, thus breaking the form of a transmission structure of a diesel engine of the conventional fracturing pump added with a transmission tank, simplifying the structure of the entire fracturing pump, reducing the apparatus mounted on a fracturing car, decreasing failure rate of the apparatus, and becoming more safe and reliable. 110-. (canceled)11. A fracturing pump comprising a cooling device and a control device , wherein:a pump motor is coupled on a shaft of said fracturing pump,said cooling device comprises an air-cooled device for cooling a rotor of said pump motor and a water-cooled device for cooling a stator of said pump motor, andsaid control device is coupled with said pump motor and said cooling device, respectively.12. A fracturing pump of claim 11 , wherein said cooling device is mounted between said two fracturing pumps.13. A fracturing pump of claim 11 , wherein said pump motor is controlled by a middle-voltage numerical control frequency converter.14. A fracturing pump of claim 12 , wherein said pump motor is controlled by a middle-voltage numerical control frequency converter.15. A fracturing pump of claim 13 , wherein a temperature sensor and a pressure sensor are mounted on said fracturing pump; said temperature sensor claim 13 , said pressure sensor and said frequency converter are connected to a PLC (Programmable Logic Controller) via a field bus cable; and said PLC is connected with a man-machine input device.16. A fracturing pump of claim 14 , wherein a temperature sensor and a ...

Brightness compensation method applied to organic light-emitting diode display

A brightness compensation method applied to an OLED display is disclosed. The brightness compensation method includes following steps of: (a) using a skip frame method or an extend porch method to reduce a display frame rate of the OLED display from a first frame rate to a second frame rate, wherein the first frame rate is higher than the second frame rate; and (b) compensating pulse widths of N light-emitting control pulses corresponding to a repeat frame or an extended porch not refreshed, wherein the N light-emitting control pulses correspond to N compensation values, N≥1 and the N compensation values are positive or negative.

Specialized fixed function hardware for efficient convolution

One embodiment provides for a general-purpose graphics processing unit including a scheduler to schedule multiple matrix operations for execution by a general-purpose graphics processing unit. The multiple matrix operations are determined based on a single machine learning compute instruction. The single machine learning compute instruction is a convolution instruction and the multiple matrix operations are associated with a convolution operation.

DISPLAY PANEL DRIVING METHOD

A display panel driving method is used to drive a display panel including a first display area having a first pixel density and a second display area having a second pixel density. The first pixel density is larger than the second pixel density. There are regular linear boundaries connected to each other between the first display area and the second display area. Each regular linear boundary includes at least one vertical segment and/or at least one horizontal segment having a length larger than or equal to that of adjacent pixels in the first display area. The display panel driving method includes steps of: (a) at the regular linear boundaries, driving pixels in alternate rows and/or alternate columns to display along vertical direction and/or horizontal direction; and (b) in the second display area, driving pixels in alternate rows and/or alternate columns to display along vertical direction and/or horizontal direction. 1. A display panel driving method , applied to drive a display panel comprising a first display area having a first pixel density and a second display area having a second pixel density , the first pixel density being larger than the second pixel density , there being regular linear boundaries connected to each other between the first display area and the second display area; each of the regular linear boundaries comprising at least one vertical segment and/or at least one horizontal segment having a length larger than or equal to that of two adjacent pixels in the first display area , the display panel driving method comprising steps of:(a) at the regular linear boundaries, driving pixels in alternate rows and/or alternate columns to display along a vertical direction and/or a horizontal direction; and(b) in the second display area, driving pixels in alternate rows and/or alternate columns to display along the vertical direction and/or the horizontal direction.2. The display panel driving method of claim 1 , wherein driving pixels in alternate ...

SUPPRESSING INTERACTION BETWEEN BONDED PARTICLES

A method comprising causing a computer to determine that a topological distance between two particles is less than a threshold. 1. A method comprising causing a computer to determine that a topological distance between two particles is less than a threshold.2. The method of claim 1 , further comprising claim 1 , based on said determination claim 1 , causing said computer to suppress computation of an interaction between said two particles.3. The method of claim 1 , further comprising providing a computer-readable graph representing a relationship between said particles claim 1 , wherein said topological distance depends at least in part on a number of edges between said two particles in said graph.4. The method of claim 2 , wherein said particles are first and second atoms and wherein suppressing computation of an interaction between said two particles comprises suppressing computation that claim 2 , if unsuppressed claim 2 , would be carried out by a molecular dynamics simulation system.5. The method of claim 1 , wherein determining that a topological distance between said two particles is less than a threshold comprises tagging a first of said particles with a first topological identifier indicative of a topological relationship between said first particle and a set of particles of which it is a part.6. The method of claim 5 , wherein said first particle is an atom and said set of particles is a molecule formed by covalent bonds between pairs of particles.7. The method of claim 4 , further comprising tagging a second of said particles with a second topological identifier claim 4 , and determining a topological distance between said first and second particles based on said first and second topological identifiers.8. The method of claim 7 , wherein each of said first and second topological identifiers comprises a backbone identifier.9. The method of claim 7 , wherein each of said topological identifiers comprises at least one side-chain identifier.10. The method of ...

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product. 1. An apparatus comprising:an interconnect fabric;a memory interface coupled to the interconnect fabric;an input/output, IO, unit coupled to the interconnect fabric;an array of multiprocessors coupled to the interconnect fabric, a multiprocessor in the array of multiprocessors to execute a mixed-precision instruction in parallel across multiple threads, the multiprocessor in the array of multiprocessors comprising:a plurality of registers to store packed floating-point operand values; andexecution circuitry to execute one or more of the mixed-precision instructions to perform a fused multiply-accumulate operation, the execution circuitry comprising:a 16-bit multiplier to multiply a first 16-bit floating point source value and a second 16-bit floating point source value to generate an intermediate result; anda 32-bit accumulator to add the intermediate result to an accumulated floating point value to generate a new accumulation result.2. The apparatus of further comprising:a parallel processor die comprising the interconnect fabric, memory interface, the input/output (TO) unit, and the array of multiprocessors, the parallel processor die further comprising:a local memory interconnect to couple the memory interface to stacked memory dies, the local memory interconnect comprising ...

DISPLAY DRIVING CIRCUIT AND REFRESH RATE ADJUSTMENT METHOD

A display driving circuit applied to a display includes a detection unit, a counting unit and an adjusting unit. The detection unit is configured to detect N pulses of an emission control signal of the display in a frame and define a frame porch interval increasing unit accordingly. The frame porch interval increasing unit equals to 1/N frame. N is a positive integer. The counting unit is coupled to the detection unit and configured to count frames according to a first refresh rate. The adjusting unit is coupled to the detection unit and the counting unit and configured to insert M frame porch interval increasing units every time when the counting unit counts L frames to adjust the first refresh rate to a second refresh rate, wherein the second refresh rate is lower than the first refresh rate. L and M are positive integers and L≥M. 1. A display driving circuit , applied to a display , the display driving circuit comprising:a detection unit, configured to detect N pulses of an emission control signal of the display in a frame and define a frame porch interval increasing unit accordingly, wherein the frame porch interval increasing unit equals to 1/N frame, and N is a positive integer;a counting unit, coupled to the detection unit and configured to count a plurality of frames according to a first refresh rate; andan adjusting unit, coupled to the detection unit and the counting unit and configured to insert M frame porch interval increasing units every time when the counting unit counts L frames to adjust the first refresh rate to a second refresh rate, wherein the second refresh rate is lower than the first refresh rate, and L and M are positive integers and L≥M.2. The display driving circuit of claim 1 , wherein the display is a self-luminous display.3. The display driving circuit of claim 1 , wherein the second refresh rate equals to the first refresh rate *[(L*N)/(L*N+M)].4. The display driving circuit of claim 1 , wherein the plurality of frames all corresponds ...

Panel Display Position Fine Adjustment Method

A panel display position fine adjustment method is disclosed. The panel display position fine adjustment method includes steps of: (a) providing a fixed first synchronization timing signal; (b) generating a first control signal, a second control signal, and a third control signal according to the first synchronization timing signal, wherein the second control signal is turned on earlier than the first control signal and the third control signal is turned on later than the first control signal; (c) when the first display driver is controlled by the first control signal, the display area is not moved; (d) when the first display driver is controlled by the second control signal, the display area is moved in the first direction; and (e) when the first display driver is controlled by the third control signal, the display area is moved in the second direction opposite to the first direction.

Driving circuit and operating method thereof

A driving circuit, disposed in a display and coupled to a display panel, includes a buffer module, a regenerating module, a data processing module and a driving module. The buffer module is used to receive and temporarily store a first image data. The regenerating module coupled to the buffer module is used to use the first image data to perform dynamic displaying process on an original image data according to a control signal to generate a second image data. The data processing module coupled to the regenerating module is used to perform data processing process on the second image data to generate an output image data. The driving module coupled to the data processing module and the display panel is used to output the output image data to the display panel. The dynamic displaying process is to dynamically superimpose the first image data on the original image data. 1. A driving circuit , disposed in a display and coupled to a display panel , comprising:a buffer module, for receiving a first image data and temporarily storing the first image data;a regenerating module, coupled to the buffer module, for using the first image data to perform a display operating process on an original image data according to a control signal to generate a second image data;a data processing module, coupled to the regenerating module, for performing a data processing process on the second image data to generate an output image data; anda driving module, coupled to the data processing module and the display panel, for outputting the output image data to the display panel.2. The driving circuit of claim 1 , wherein the display panel is an organic light-emitting diode (OLED) display panel.3. The driving circuit of claim 1 , further comprising:a transmission interface, for receiving an input image data from outside; andanother data processing module, coupled between the input interface and the buffer module, for performing the data processing process on the input image data to generate the ...

Driving circuit and operating method thereof

A driving circuit includes a buffer module, a regenerating module, a data processing module and a driving module. The buffer module receives and temporarily stores a first image data which is a small image or color block. The regenerating module coupled to the buffer module uses the first image data to perform dynamic displaying process on an original image data according to a control signal to generate a second image data. The data processing module coupled to the regenerating module performs data processing process on the second image data to generate an output image data. The driving module coupled to the data processing module and a panel outputs the output image data to the panel. The dynamic displaying process is to dynamically superimpose the first image data on the original image data. When the panel displays the output image data, dynamic changes have continuously occurred in different small regions. 1. A driving circuit , disposed in a display and coupled to a display panel , comprising:a buffer module, for receiving a first image data and temporarily storing the first image data, wherein the first image data is a small image or a color block;a regenerating module, coupled to the buffer module, for using the first image data to perform a dynamic displaying process on an original image data according to a control signal to generate a second image data;a data processing module, coupled to the regenerating module, for performing a data processing process on the second image data to generate an output image data; anda driving module, coupled between the data processing module and the display panel, for outputting the output image data to the display panel;wherein the dynamic displaying process comprises dynamically superimposing the first image data on the original image data, and dynamic changes have continuously occurred in different small regions when the display panel displays the output image data.2. The driving circuit of claim 1 , wherein the display ...

Driving circuit and operating method thereof

A driving circuit, disposed in a display and coupled to a display panel, includes a buffer module, a regenerating module, a data processing module and a driving module. The buffer module is used to receive and temporarily store a first image data. The regenerating module coupled to the buffer module is used to use the first image data to perform dynamic displaying process on an original image data according to a control signal to generate a second image data. The data processing module coupled to the regenerating module is used to perform data processing process on the second image data to generate an output image data. The driving module coupled to the data processing module and the display panel is used to output the output image data to the display panel. The dynamic displaying process is to dynamically superimpose the first image data on the original image data. 1. A driving circuit , disposed in a display and coupled to a display panel , comprising:a buffer module, for receiving a first image data and temporarily storing the first image data;a regenerating module, coupled to the buffer module, for using the first image data to perform a dynamic displaying process on an original image data according to a control signal to generate a second image data;a data processing module, coupled to the regenerating module, for performing a data processing process on the second image data to generate an output image data; anda driving module, coupled to the data processing module and the display panel, for outputting the output image data to the display panel;wherein the dynamic displaying process comprises dynamically superimposing the first image data on the original image data.2. The driving circuit of claim 1 , wherein the display panel is an organic light-emitting diode (OLED) display panel.3. The driving circuit of claim 1 , further comprising:a transmission interface, for receiving an input image data from outside; andanother data processing module, coupled between ...

MIXED INFERENCE USING LOW AND HIGH PRECISION

One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks. 1. A general-purpose graphics processing unit comprising: a first processing block including a first processing core having a first floating-point data path and a second processing core having a first integer data path, the first integer data path independent of the first floating-point data path, wherein the first integer data path is to enable execution of a first instruction and the first floating-point data path is to enable execution of a second instruction, the first instruction to be executed concurrently with the second instruction;', 'a second processing block including a third processing core having a second floating-point data path and a fourth processing core having a second integer data path, the second integer data path independent of the second floating-point data path, wherein the second integer data path is to enable execution of a third instruction and the second floating-point data path is to enable execution of a fourth instruction, the third instruction to be executed concurrently with the fourth instruction; and', 'a memory coupled with the first processing block and the second processing block., 'a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading, wherein the streaming multiprocessor comprises2. The general-purpose graphics processing unit as in claim 1 , wherein the memory is shared between the first processing block and the second processing block.3 ...

Driving circuit and operating method thereof

A driving circuit and operating method thereof are disclosed. The driving circuit is coupled to a display panel. The driving circuit includes a memory. The method includes: (a) the driving circuit receives an image data including N frames, N is a positive integer; (b) during a first period, writing a first frame of image data into the memory along a first direction; and (c) during a second period, reading the first frame from the memory along a second direction and outputting it to the display panel and then writing a second frame of image data into the memory along the second direction. Wherein, since the second period is later then the first period and the second direction is opposite to the first direction, the first frame read from the memory in step (c) and the first frame written into the memory in step (b) are upside down each other. 1. A driving circuit operating method for operating a driving circuit coupled to a display panel , the driving circuit comprising a memory , the driving circuit operating method comprising steps of:(a) the driving circuit receiving an image data comprising N frames, wherein N is a positive integer;(b) during a first period, writing a first frame of the image data into the memory along a first direction; and(c) during a second period, reading the first frame from the memory along a second direction and outputting the first frame to the display panel and then writing a second frame of the image data into the memory along the second direction;wherein, since the second period is later then the first period and the second direction is opposite to the first direction, the first frame read from the memory in step (c) and the first frame written into the memory in step (b) are upside down each other.2. The driving circuit operating method of claim 1 , wherein the display panel is an organic light-emitting diode (OLED) display panel.3. The driving circuit operating method of claim 1 , wherein the first direction and the second direction ...

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads. 1. An apparatus comprising:a memory interface; a register file to store data; and', hardware logic to convert a first plurality of data elements of a first multidimensional source matrix and a second plurality of data elements of a second multidimensional source matrix from a 32-bit floating point data format to a reduced precision floating point format having a 1-bit sign, an 8-bit exponent, and a mantissa, the mantissa of the reduced precision floating point format having fewer bits than a mantissa of the 32-bit floating point data format; and', 'a plurality of multiply-add circuits to perform parallel fused multiply-add operations to multiply the first plurality of data elements in the reduced precision floating point format by corresponding data elements of the second plurality of data elements in the reduced precision floating point format to generate a plurality of products, and to add the plurality of products to corresponding 32-bit floating point values to generate corresponding 32-bit floating point data elements of the multidimensional result matrix., 'execution circuitry coupled to the register file, the execution circuitry to execute the fused multiply-add instruction to generate a multidimensional result matrix, the execution circuitry comprising], 'an array of multiprocessors coupled to the memory interface, at least one multiprocessor in the array of multiprocessors to execute a fused multiply-add instruction in parallel across multiple threads, the at least one ...

REMOTE CUTTING SYSTEM AND CONTROL METHOD OF CUTTING DEVICE

A remote cutting system includes a cutting device and a control device. The cutting device includes a control unit, a wireless communication unit, a drive unit and a knife. The control device includes a processor, an accelerometer, a first button, a second button and a wireless connect unit. The accelerometer is connected with the processor for recording a move information. When the first button or the second button is pressed, a move command or a cutting command is generated according to the move information by the processor. A wireless connection is established between the wireless connect unit and the wireless communication unit for transmitting the move command or the cutting command, and then the drive unit is controlled by the control unit to drive the knife, so that the knife is driven to move or cut. Therefore, the manufacturing cost is reduced, and simultaneously the convenience is enhanced. 1. A remote cutting system , comprising: a control unit;', 'a wireless communication unit connected with the control unit;', 'a drive unit connected with the control unit; and', 'a knife connected with the drive unit; and, 'a cutting device, comprising a processor;', 'an accelerometer connected with the processor for sensing and recording a move information of the control device;', 'a first button connected with the processor, wherein when the first button is pressed, a move command is generated according to the move information by the processor;', 'a second button connected with the processor, wherein when the second button is pressed, a cutting command is generated according to the move information by the processor; and', 'a wireless connect unit connected with the processor, wherein a wireless connection is established between the wireless connect unit and the wireless communication unit for transmitting the move command or the cutting command from the wireless connect unit to the wireless communication unit, and then the drive unit is controlled by the control unit ...

IDENTITY AUTHENTICATION METHOD, APPARATUS, AND SYSTEM

A method may be performed using a server. The method may include receiving an identity authentication request associated with a user, generating authentication information based on the identity authentication request, and generating candidate information based on the authentication information such that the authentication information is a subset of the candidate information. The candidate information may be displayed at a randomly selected location. The user may provide input through a graphic input interface to select the authentication information from among the candidate information. 1. A method including: receiving an identity authentication request associated with a user;', 'generating authentication information based on the identity authentication request;', 'generating candidate information based on the authentication information, where the candidate information includes the authentication information and randomly generated information, such that the authentication information is a subset of the candidate information;', 'causing a first display of the candidate information at a display location selected randomly from among preset locations on a graphic input interface;', 'causing a first display of at least a portion of the authentication information on an authentication interface different from the graphic input interface;', 'receiving, from user input via the graphic input interface, a input selection from among the candidate information;', 'determining whether the input selection is matched to the authentication information;', 'at a time that the input selection is matched to the authentication information, causing issuance an authentication request success message; and', 'at a time that the input selection is not matched to the authentication information, causing issuance of an authentication request rejection., 'at a server2. The method of claim 1 , where the identity authentication request defines an order for the authentication information.3. The ...

Function approximation based on statistical properties

Embodiments of techniques and systems for approximating a function are described. In embodiments, a computing device may receive one or more statistical properties associated with application of an approximation function of a function over a target domain. The computing device may formulate one or more constraints on one or more parameters of a functional form of the approximation function, based at least in part on the one or more statistical properties. The computing device may then determine the one or more parameters subject to the constraints and out put results of the determination. In embodiments, the one or more parameters may be determined through application of an optimization procedure. Other embodiments, may be described and claimed.

Cost-optimal cluster configuration analytics package

Systems, methods, and computer-readable media for identifying an optimal cluster configuration for performing a job in a remote cluster computing system. In some examples, one or more applications and a sample of a production load as part of a job for a remote cluster computing system is received. Different clusters of nodes are instantiated in the remote cluster computing system to form different cluster configurations. Multi-Linear regression models segmented into different load regions are trained by running at least a portion of the sample on the instantiated different clusters of nodes. Expected completion times of the production load across varying cluster configurations are identified using the multi-linear regression models. An optimal cluster configuration of the varying cluster configurations is determined for the job based on the identified expected completion times.

DISTRIBUTION TRANSFORMER TERMINAL AND METHOD FOR MONITORING A STATE OF A DISTRIBUTION TRANSFORMER COURT DEVICE

Disclosed are a distribution transformer terminal and a method for monitoring a state of a distribution transformer court device. The distribution transformer terminal includes an ARM core processor, a carrier communication module connected to a court device, a sub-G wireless communication module connected to the court device and a GPS module connected to the court device. The ARM core processor is connected to the carrier communication module, the sub-G wireless communication module and the GPS module. The ARM core processor is configured to identify a phase of the court device and a court to which the court device belongs acquire an operating state and fault information of the court device through the sub-G wireless communication module, and acquire geographical location information of the court device through the GPS module. 1. A distribution transformer terminal , comprising an advanced reduced instruction set computer machines (ARM) core processor , a carrier communication module , a sub-G wireless communication module and a global positioning system (GPS) module , wherein the ARM core processor is connected to the carrier communication module , the carrier communication module is arranged to be connected to a court device , the ARM core processor is configured to identify a phase of the court device and a court to which the court device belongs; the ARM core processor is further connected to the sub-G wireless communication module , the sub-G wireless communication module is arranged to be connected to the court device , and the ARM core processor is further configured to acquire an operating state and fault information of the court device through the sub-G wireless communication module; the ARM core processor is further connected to the GPS module , the GPS module is arranged to be connected to the court device , and the ARM core processor is further configured to acquire geographical location information of the court device through the GPS module; the ARM ...

CONVOLUTIONAL NEURAL NETWORK OPTIMIZATION MECHANISM

Embodiments provide systems and methods which facilitate optimization of a convolutional neural network (CNN). One embodiment provides for a non-transitory machine-readable medium storing instructions that cause one or more processors to perform operations comprising processing a trained convolutional neural network (CNN) to generate a processed CNN, the trained CNN having weights in a floating-point format. Processing the trained CNN includes quantizing the weights in the floating-point format to generate weights in an integer format. Quantizing the weights includes generating a quantization table to enable non-uniform quantization of the weights and quantizing the weights from the floating-point format to the integer format using the quantization table. The operations additionally comprise performing an inference operation utilizing the processed CNN with the integer format weights. 1. One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that , when executed by one or more processors , cause the one or more processors to perform operations comprising: generating a quantization table to enable non-uniform quantization of the weights, and', 'quantizing the weights from the floating-point format to the integer format using the quantization table; and, 'processing a trained convolutional neural network (CNN) to generate a processed CNN, the trained CNN having weights in a floating-point format, wherein processing the trained CNN includes quantizing the weights in the floating-point format to generate weights in an integer format, wherein quantizing the weights includesperforming an inference operation utilizing the processed CNN with the weights in the integer format.2. The one or more storage mediums of claim 1 , wherein the quantization table is structured to maintain accuracy of inference by the processed CNN after quantization of the weights of the trained CNN.3. The one or more storage mediums ...

Processing Method for Poultry Oil

The invention discloses a processing method for poultry oil. The method comprises: placing a crude poultry oil at a predetermined temperature for forming a mixture containing liquid-type oil and solid-type oil; and harvesting the liquid-type oil from the mixture at the predetermined temperature. The predetermined temperature is set between 13° C. and 17° C., and the tolerance for the temperature measurement is ±2° C. Accordingly, compared to the crude poultry oil, the processed poultry oil has a good commercial appearance without solid precipitation at room temperature. 1. A processing method for poultry oil , comprising: placing a crude poultry oil at a predetermined temperature for forming a mixture containing liquid-type oil and solid-type oil; and harvesting the liquid-type oil from the mixture at the predetermined temperature , wherein the predetermined temperature is set between 13° C. and 17° C. , and the tolerance for the temperature measurement is ±2° C.2. The processing method for poultry oil as claimed in claim 1 , wherein the predetermined temperature is set at 13° C. claim 1 , and the tolerance for the temperature measurement is ±0.5° C.3. The processing method for poultry oil as claimed in claim 1 , wherein the predetermined temperature is set at 17° C. claim 1 , and the tolerance for the temperature measurement is ±0.5° C.4. The processing method for the poultry oil as claimed in claim 1 , wherein the liquid-type oil is harvested by filtering out the solid-type oil of the mixture at the predetermined temperature.5. The processing method for poultry oil as claimed in claim 4 , wherein filtering out the solid-type oil comprises loading the mixture in a filter bag then centrifuging at 80 rpm for 20 minutes to collect the liquid-type oil.6. The processing method for the poultry oil as claimed in claim 1 , wherein the liquid-type oil is harvested by standing the mixture for a predetermined period of time to precipitate the solid-type oil claim 1 , and to ...

Driving method for display

A display driving method is disclosed. The display driving method includes the following steps: (A) generating a gate driving signal having a turn-on period by a gate driver; (B) generating a source driving signal by a source driver; the source driving signal has a first waveform corresponding to a first region and has a second waveform corresponding to a second region; (C) outputting, by a controller of a display device, a first control signal to allow the second waveform to be similar to the first waveform in the turn-on period.

Compute optimizations for low precision machine learning operations

One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction. The at least one single instruction is to cause at least a portion of the GPU to perform a floating point operation on input having differing precisions. The floating point operation is a two-dimensional matrix multiply and accumulate operation.

MAGNON SPIN VALVE, MAGNON SENSOR, MAGNON FIELD EFFECT TRANSISTOR, MAGNON TUNNEL JUNCTION AND MAGNON MEMORY

The present disclosure relates to a magnon spin valve device, a magnon sensor, a magnon field effect transistor, a magnon tunnel junction and a magnon memory. A magnon spin valve device may comprise a first ferromagnetic insulation layer, a non-magnetic conductive layer disposed on the first ferromagnetic insulation layer, and a second ferromagnetic insulation layer disposed on the non-magnetic conductive layer. 1. A magnon spin valve device comprising:a first ferromagnetic insulation layer;a non-magnetic conductive layer disposed on the first ferromagnetic insulation layer; anda second ferromagnetic insulation layer disposed on the non-magnetic conductive layer.2. The magnon spin valve device of claim 1 , wherein each of the first ferromagnetic insulation layer and the second ferromagnetic insulation layer comprises one or more of the following materials: RFeO claim 1 , MFeO claim 1 , FeO claim 1 , BaFeO claim 1 , SrFeO claim 1 , and doped compounds thereof claim 1 , where R is Y claim 1 , Pr claim 1 , Nd claim 1 , Sm claim 1 , Eu claim 1 , Gd claim 1 , Tb claim 1 , Dy claim 1 , Ho claim 1 , Er claim 1 , Tm claim 1 , Yb or Lu claim 1 , and M is Mn claim 1 , Zn claim 1 , Cu claim 1 , Ni claim 1 , Mg or Co claim 1 , andwherein the non-magnetic conductive layer comprises one or more of the following materials: Cu, Ru, Ag, Cr, and Au.3. The magnon spin valve device of claim 1 , wherein the first ferromagnetic insulation layer has a relatively fixed magnetic moment claim 1 , and the second ferromagnetic insulation layer has a free magnetic moment that is free to change with an external magnetic field.4. The magnon spin valve device of claim 1 , wherein the non-magnetic conductive layer has a thickness smaller than three times of its spin diffusion length.5. The magnon spin valve device of claim 1 , wherein the magnon spin valve device is used as a magnon sensor.6. A magnon field effect transistor comprising:a first ferromagnetic region, a second ferromagnetic region, ...

SYSTEMS AND METHODS FOR NONLINEAR TOOTH MODELING

Systems and methods of generating an orthodontic model are disclosed. The method may include: generating an initial model of a patient dentition; generating a target model of the patient dentition; defining a plurality of caps and a plurality of links, wherein each link connects two of the plurality of caps; generating a relaxed model of a dental appliance from the plurality of caps and the plurality of links; generating a deformed model of a dental appliance from the plurality of caps and plurality of links; and determining a plurality of movements, wherein the plurality of moments transform the relaxed model to the deformed model and wherein the moments are configured to direct the patient dentition from the initial model to the target model. 1. A computer-implemented method of generating an orthodontic model of tooth movements , the computer-implemented method comprising:generating an initial model of a patient dentition, the initial three-dimensional model comprising a first, three-dimensional representation of the patient dentition at a stage of a treatment plan;generating a target model of the patient dentition, the target three-dimensional model comprising a second, three-dimensional representation of the patient dentition after the stage of the treatment plan;defining a plurality of caps and a plurality of links, wherein each cap of the plurality of caps represents a set of contact points on a tooth of the dentition, and wherein each link of the plurality of links represents a connection between two of the plurality of caps;generating a relaxed model of a dental appliance from the plurality of caps and the plurality of links, the relaxed model of the dental appliance representing physical properties of the dental appliance at a first state;generating a deformed model of a dental appliance from the plurality of caps and plurality of links, the deformed model of the dental appliance representing the physical properties of the dental appliance at a second state ...

GRAPHICS PROCESSING INTEGRATED CIRCUIT PACKAGE

An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations. 120-. (canceled)21. An integrated circuit (IC) package comprising:a plurality of graphics processing unit (GPU) chips, each GPU chip of the plurality of GPU chips being coupled with memory for storage of data;a plurality of channels between GPU chips of the plurality of GPU chips, the plurality of channels to facilitate exchange of data between the GPU chips; anda priority mechanism, the priority mechanism to establish a plurality of priority levels for the data exchanged between the plurality of GPU chips.22. The IC package of claim 21 , wherein the plurality of channels includes a plurality of separate physical connections between GPU chips of the plurality of GPU chips.23. The IC package of claim 21 , wherein the plurality of channels includes a plurality of virtual channels between GPU chips of the plurality of GPU chips.24. The IC package of claim 21 , further comprising an activation component to activate the plurality of channels based on data traffic type and priority level.25. The IC package of claim 24 , wherein the activation component is to determine which memory surfaces of the memory can be attached to a particular priority level of the plurality of priority levels.26. The IC package of claim 25 , wherein data traffic types and memory surfaces are mapped into particular priority levels of the plurality of priority levels to enable data flow with non-blocking conditions.27. The IC package of claim 21 , wherein each of the plurality of GPU chips includes a plurality of processing elements.28. The IC package of claim 27 , wherein the processing elements of one or more of the plurality of GPU chips include streaming multiprocessors (SMs).29. The IC package of claim 21 , further comprising a central ...

PERSON TRACKING AND PRIVACY AND ACCELERATION OF DATA USING AUTONOMOUS MACHINES

A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data. 120-. (canceled)21. An apparatus comprising:one or more processors including a graphics processing unit (GPU);a memory to store data, the data including data for a neural network; andone or more field programmable gate array (FPGA) units; receive application code for compilation, the application including a machine learning operation;', 'identify one or more mathematics operations to be mapped to the one or more FPGA units;', 'detecting one or more instances of the identified mathematics operations in the received application code; and', 'generating compiled code for the application, wherein generating the compiled code includes replacing the detected one or more instances of the identified mathematics operations with send messages to access blocks of the one or more FPGA units., 'wherein the apparatus is to22. The apparatus of claim 21 , wherein identifying the one or more mathematics operations to be mapped to the one or more FPGA units including determining the one or more mathematics operations from the application.23. The apparatus of claim 21 , wherein the identified mathematics operations include operations for deep learning to be accelerated by the one or more FPGA units.24. The apparatus of claim 23 , wherein the identified mathematical operations include one or more commonly used math functions to ...

METHOD AND SYSTEM FOR MANAGING MOBILE AND PORTABLE TWO-WAY RADIO COLLABORATION

A method and apparatus for collaboration among two-way radio devices allows a portable two-way radio device and a mobile two-way radio device to each enter into a collaboration mode while the are paired with each other over a short range wireless radio network. While in the collaboration mode, when the user keys the portable two-way radio device audio is routed from the portable two-way radio device to the mobile two-way radio device over the short range wireless network and the mobile two-way radio device transmits the audio on behalf of the portable two-way radio device. 1. A method for collaboration among two-way radio devices , comprising:pairing a mobile two-way radio device and a portable two-way radio device over a short range wireless network link;detecting a push to talk (PTT) event at the portable two-way radio device;transmitting a PTT request from the portable two-way radio device to the mobile two-way radio device over the short range wireless network link in response to detecting the PTT event,receiving a PTT grant at the portable two-way radio device from the mobile two-way radio device over the short range wireless network link in response to transmitting the PTT request;in response to receiving the PTT grant, the portable two-way radio device providing a talk permit alert, opening a microphone receive path, and routing audio received via the microphone receive path to the mobile two-way radio device over the short range wireless network link, wherein the mobile two-way radio device transmits the audio using a channel setting of the portable two-way radio device, and wherein the channel setting of the portable two-way radio device is different than a channel setting of the mobile two-way radio device.2. The method of claim 1 , further comprising the portable two-way radio device transmitting to the mobile two-way radio device the channel setting of the portable two-way radio device over the short range wireless network link.3. The method of claim 2 , ...

DYNAMIC RENDERING OF GEOGRAPHIC DATA

Computer systems, methods, and computer storage media for dynamically rendering geographic data. Geographic data is dynamically rendered as a digital map such that changes to the corresponding geographic data are automatically applied to the map and the map is automatically updated to show the changes to the geographic data. The map is rendered to give the most effective view of the corresponding geographic data by determining a least common ancestor of identified geographic entities. The least common ancestor is the lowest ranked geographic entity, within a geographic hierarchy, that is still common to all of the identified geographic entities within a set of geographic data.

OBJECT TRACKING METHOD AND APPARATUS, STORAGE MEDIUM AND ELECTRONIC DEVICE

An object tracking method includes: obtaining at least one image acquired by at least one image acquisition device; obtaining a first appearance feature of a target object and a first spatial-temporal feature of the target object based on the at least one image; obtaining an appearance similarity and a spatial-temporal similarity between the target object and each global tracking object in a currently recorded global tracking object queue; based on determining that the target object matches a target global tracking object based on the appearance similarity and the spatial-temporal similarity, allocating a target global identifier corresponding to the target global tracking object to the target object; determining, using the target global identifier, a plurality of associated images acquired by a plurality of image acquisition devices associated with the target object; and generating, based on the plurality of associated images, a tracking trajectory matching the target object. 1. An object tracking method , executed by an electronic device , the method comprising:obtaining at least one image acquired by at least one image acquisition device, the at least one image comprising a target object;obtaining, based on the at least one image, a first appearance feature of the target object and a first spatial-temporal feature of the target object;obtaining an appearance similarity and a spatial-temporal similarity between the target object and each global tracking object in a currently recorded global tracking object queue, the appearance similarity being a similarity between the first appearance feature of the target object and a second appearance feature of a global tracking object, and the spatial-temporal similarity being a similarity between the first spatial-temporal feature of the target object and a second spatial-temporal feature of the global tracking object;based on determining that the target object matches a target global tracking object in the global tracking ...

GRAPHICS PROCESSING INTEGRATED CIRCUIT PACKAGE

An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations. 1. An integrated circuit (IC) package comprising:one or more processing units; anda bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.2. The IC package of claim 1 , further comprising a stack of one or more high bandwidth memory (HBM) devices mounted on the bridge.3. The IC package of claim 2 , further comprising a substrate mounted below the silicon bridge.4. The IC package of claim 2 , wherein the processing unit generates and dispatches one or more instructions to initiate the atomic operations at the one or more ALUs.5. The IC package of claim 4 , wherein the processing unit further dispatches one or more memory addresses with the one or more instructions to initiate the atomic operations at the one or more ALUs.6. The IC package of claim 1 , further comprising:a front end IC;an IC including one or more execution units; anda memory IC.7. The IC package of claim 1 , further comprising:a first graphics processing unit (GPU) IC;a second GPU IC; anda memory IC.8. The IC package of claim 1 , further comprising:a central processing unit (CPU) IC;a GPU IC; anda memory IC.9. The IC package of claim 8 , further comprising an accelerator IC.10. An integrated circuit (IC) package comprising:a plurality of graphics processing units (GPUs); anda plurality of virtual channels coupled between the plurality of GPUs.11. The IC package of claim 10 , further comprising activation logic to activate the virtual channels.12. The IC package of claim 11 , wherein the activation logic activates virtual channels based on content and a priority level.13. The IC package of claim 12 , wherein the activation determines data guidelines as to a surface that ...

AUTONOMOUS VEHICLE NEURAL NETWORK OPTIMIZATION

Methods and apparatus relating to autonomous vehicle neural network optimization techniques are described. In an embodiment, the difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network is detected. The second training dataset is authenticated in response to the detection of the difference. The neural network is used to assist in an autonomous vehicle/driving. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:logic, at least a portion of which is in hardware, to detect a difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network,wherein the logic is to cause the second training dataset to be authenticated in response to the detection of the difference, wherein the neural network is to assist in an autonomous vehicle or autonomous driving.2. The apparatus of claim 1 , wherein the logic is to detect the difference between the first training dataset and the second training dataset based at least in part on a comparison of one or more characteristics of the first training dataset and the second training dataset.3. The apparatus of claim 2 , wherein the one or more characteristics are to comprise one or more of: pixel color content claim 2 , pixel color depth claim 2 , pixel luminance claim 2 , result of spectral analysis of input image(s) claim 2 , or video and/or audio stream(s).4. The apparatus of claim 1 , comprising logic to generate a first hash value for the first training dataset based at least in part on one or more characteristics of the first training dataset and to generate a second hash value for the first training dataset based at least in part on the one or more characteristics of the first training dataset.5. The apparatus of claim 4 , wherein the logic is to detect the difference between the first training dataset and the second training dataset based at least in ...

PERSON TRACKING AND PRIVACY AND ACCELERATION OF DATA USING AUTONOMOUS MACHINES

A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data. 1. An apparatus comprising:detection/observation logic, as facilitated by or at least partially incorporated into a processor, to facilitate a camera associated with one or more trackers to detect a person within a physical vicinity, wherein detecting includes capturing one or more images the person;person tracking engine, as facilitated by or at least partially incorporated into the processor, to facilitate the one or more trackers to track the person based on the one or more images of the person, wherein the person tracking engine to collect tracking data relating to the person; anddecision/storage logic, as facilitated by or at least partially incorporated into the processor, to select a tracker of the one or more trackers as a preferred tracker based on the tracking data.2. The apparatus of claim 1 , further comprising evaluation/recognition logic claim 1 , as facilitated by or at least partially incorporated into the processor claim 1 , to evaluate the one or images to extract relevant information from the one or more images claim 1 , wherein the relevant information includes one or more of video frames claim 1 , bounding boxes claim 1 , and personal label claim 1 , wherein the video frames include a current video frame claim 1 , and wherein the bounding boxes include one or more of a torso bounding box ...

CONVOLUTIONAL NEURAL NETWORK OPTIMIZATION MECHANISM

An apparatus to facilitate optimization of a convolutional neural network (CNN) is disclosed. The apparatus includes optimization logic to receive a CNN model having a list of instructions and including pruning logic to optimize the list of instructions by eliminating branches in the list of instructions that comprise a weight value of 0. 1. An apparatus to facilitate optimization of a convolutional neural network (CNN) , comprising:a graphic processing unit having a plurality of execution units to perform NN operations; andoptimization logic to receive a CNN model having a list of instructions and optimize the list of instructions by eliminating branches in the list of instructions that comprise a first weight value.2. The apparatus of claim 1 , wherein the optimization logic comprises pruning logic to optimize the list of instructions by disregarding branches in the CNN model that comprise a second weight value.3. The apparatus of claim 2 , wherein the pruning logic further optimizes the list of instructions by eliminating branches in the CNN model having a weight value within a predetermined threshold of the first weight value.4. The apparatus of claim 2 , wherein the pruning logic expands the CNN model into elementary operations upon receiving the CNN model.5. The apparatus of claim 4 , wherein the pruning logic compresses a representation of instructions in the optimized instruction list.6. The apparatus of claim 4 , wherein the pruning logic generates an executable application to perform the instructions in the optimized instruction list.7. The apparatus of claim 1 , wherein the optimization logic comprises a set of quantization primitives to convert floating point numbers to perform convolution operations provided at the CNN.8. The apparatus of claim 7 , wherein the optimization logic further comprises a set of de-quantization primitives to convert floating point and integer numbers.9. The apparatus of claim 1 , wherein the optimization logic comprises window ...

MIXED INFERENCE USING LOW AND HIGH PRECISION

One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and a simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision. 1. A compute apparatus to perform machine learning operations , the compute apparatus comprising: an instruction decoder to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions; and', 'a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform, at the first logic unit, a first instruction operation at a first precision on a first set of operands of the multiple operands and perform, at the second logic unit, a second instruction operation at a second precision on a second set of operands of the multiple operands, the first instruction operation performed within the general-purpose graphics compute unit in parallel with the second instruction operation., 'a processor comprising2. The compute apparatus as in claim 1 , wherein the general-purpose graphics compute unit is to output multiple results for the single instruction ...

MIXED INFERENCE USING LOW AND HIGH PRECISION

One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation. 1. A graphics processing unit (GPU) to accelerate machine learning operations , the GPU comprising:an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional mixed precision floating-point operation, and the second instruction to cause the GPU to perform an integer operation, wherein the integer operation corresponds to an address calculation to update a memory address; anda general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit including a first functional unit and a second functional unit, the first functional unit to execute a thread of the first instruction and the second functional unit to execute a thread of the second instruction during execution of the thread of the first instruction, wherein the general-purpose graphics compute unit is to dynamically configure the first functional unit to execute the multi-dimensional mixed precision floating-point operation for the thread of the first instruction.2. The GPU as in claim 1 , wherein the multi-dimensional mixed precision floating-point operation is a two-dimensional matrix multiply operation.3. The ...

DYNAMIC PRECISION FOR NEURAL NETWORK COMPUTE OPERATIONS

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed. 1. An apparatus comprising:a compute engine comprising a high precision component and a low precision component; and receive instructions in the compute engine;', 'select at least one of the high precision component or the low precision component to execute the instructions; and', 'apply a gate to at least one of the high precision component or the low precision component to execute the instructions., 'logic, at least partially including hardware logic, to2. The apparatus of claim 1 , wherein:the gate comprises a clock gate.3. The apparatus of claim 1 , wherein:the gate comprises a power gate.4. An apparatus comprising:at least one execution unit;at least one FPGA communicatively coupled to the at least one execution unit; and determine workload requirements for at least one of a workload or a thread; and', 'remap the at least one of the workload or the thread to the FPGA on a selective basis., 'logic, at least partially including hardware logic, to5. The apparatus of claim 4 , wherein:the at least one FPGA is integrated into the at least one execution unit.6. The apparatus of claim 4 , wherein:the at least one FPGA is communicatively coupled to the at least one execution unit by a wide, low-latency communication interface.7. The apparatus of claim 4 , wherein:low-load operations are mapped to the at least one FPGA.8. The apparatus of claim 4 , further comprising a FPGA synthesizer comprising logic claim 4 , at least partially including hardware logic claim 4 , ...

SPECIALIZED FIXED FUNCTION HARDWARE FOR EFFICIENT CONVOLUTION

One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to perform one or more machine learning operations, wherein the decode unit, based on parameters of the one or more machine learning operations, is to request a scheduler to schedule the one or more machine learning operations to one of an array of programmable compute units and a fixed function compute unit. 1. A compute apparatus to perform machine learning operations , the compute apparatus comprising:a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to perform one or more machine learning operations, wherein the decode unit, based on parameters of the one or more machine learning operations, is to request a scheduler to schedule the one or more machine learning operations to one of an array of programmable compute units and a fixed function compute unit.2. The compute apparatus as in claim 1 , wherein the decode unit includes fetch logic to fetch the single instruction.3. The compute apparatus as in claim 2 , wherein the single instruction is a machine learning compute instruction.4. The compute apparatus as in claim 3 , wherein the machine learning compute instruction is a convolution instruction and the one or more machine learning operations include a convolution operation.5. The compute apparatus as in claim 4 , wherein the convolution operation includes multiple matrix operations.6. The compute apparatus as in claim 5 , wherein the decode unit is to request the scheduler to schedule the multiple matrix operations to one of the array of programmable compute units and the fixed function compute unit based on a size of a convolution filter.7. The compute apparatus as in claim 6 , wherein the decode unit is to request the scheduler to schedule the multiple matrix operations to the fixed function compute units ...

COMPUTE OPTIMIZATION MECHANISM

An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations. 1. An apparatus to facilitate compute optimization , comprising a graphics processor including sorting logic to sort floating point processing threads into thread groups based on bit depth of floating point thread operations.2. The apparatus of claim 1 , wherein the sorting logic sorts further comprises a plurality of bins to store the sorted threads claim 1 , wherein each of the plurality of bins is associated with a bit depth.3. The apparatus of claim 2 , wherein the plurality of bins comprise:a first bin to store floating point thread operations having a first bit depth; anda second bin to store floating point thread operations having a second bit depth.4. The apparatus of claim 3 , further comprising one or more floating point units to process the floating point thread operations.5. The apparatus of claim 1 , wherein the graphics processor further comprises floating logic to process threads into floating point thread operations having a higher bit depth.6. The apparatus of claim 5 , wherein the floating point logic comprises:a first component to process a lower half of a bit depth of the floating point thread operations; anda second component to process an upper half of a bit depth of the floating point thread operations.7. The apparatus of claim 6 , wherein the floating point logic processes floating point thread operations having a lower bit depth at the first component.8. The apparatus of claim 7 , wherein the floating point logic deactivates the second component during processing of the floating point thread operations having the lower bit depth at the first component.9. The apparatus of claim 1 , wherein the graphics processor further comprises logic to provide variable precision support in a math instruction.10. The apparatus of claim 9 , wherein the logic ...

COMPUTE OPTIMIZATION MECHANISM

An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations. 1. A multiprocessor comprising:a register file to store operands; and multiply a first 16-bit floating point (FP16) operand with a second FP16 operand to obtain a 32-bit floating point (FP32) intermediate product;', 'multiply a third FP16 operand with a fourth FP16 operand to obtain a second FP32 intermediate product; and', 'add the second FP32 intermediate product with the FP32 intermediate product to generate a FP32 sum result., 'a plurality of processing cores, each core having execution logic to perform mixed precision multi-dimensional matrix fused multiply-accumulate (FMAC) operations, the execution logic to execute one or more instructions to2. (canceled)3. The multiprocessor of claim 1 , wherein the register file stores the first FP16 operand claim 1 , the second FP16 operand claim 1 , and the first and second FP32 intermediate products.4. The multiprocessor of claim 1 , further comprising an instruction cache to store the one or more instructions.5. The multiprocessor of claim 4 , further comprising a dispatch unit to dispatch the one or more instructions for execution at the execution logic.6. The multiprocessor of claim 1 , further comprising a scheduler to schedule the FMAC operations.7. A method to facilitate execution of mixed precision multi-dimensional matrix fused multiply-accumulate (FMAC) operations comprising:receiving a first 16-bit floating point (FP16) operand and a second FP16 operand at one or more processing cores;multiplying the first FP16 operand with the second FP16 operand to obtain a 32-bit floating point (FP32) intermediate product;multiply a third FP16 operand with a fourth FP16 operand to obtain a second FP32 intermediate product; andadding the second FP32 intermediate product with the FP32 intermediate product to generate a FP32 sum ...

COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS

Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions. 1. A graphics processor comprising:a memory device;a level-two (L2) cache memory and a raster operations unit (ROP) coupled with the memory device;a compressor to perform lossless compression on data to be written to the memory device; anda streaming multiprocessor coupled with the memory device, the streaming multiprocessor to concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions;wherein the multiple instructions include a first instruction to cause at least a first portion of the streaming multiprocessor to perform a floating-point operation on multiple floating-point input operands and a second instruction to cause at least a second portion of the streaming multiprocessor to perform an integer operation on multiple integer operands, the first instruction to execute concurrently with the second instruction; andwherein the streaming multiprocessor includes a mixed precision core to perform operations for at least a third instruction of the multiple instructions, the mixed precision core to perform a first operation of the third instruction at a first precision and a second operation of the third instruction at a second precision, the first operation is a ...

Compute optimization mechanism

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 16-bit and/or 32 bit floating-point elements.

COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions. 1. A general-purpose graphics processing unit comprising:a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.2. The general-purpose graphics processing unit as in claim 1 , wherein the dynamic precision floating-point unit includes a set of registers to store input data and intermediate data at multiple precisions.3. The general-purpose graphics processing unit as in claim 2 , wherein the set of registers includes an error accumulator to track an accumulated error over a set of floating point operations.4. The general-purpose graphics processing unit as in claim 1 , the dynamic precision floating point unit including a significand block to perform a significand portion of a floating-point computation claim 1 , the significand block including a dynamic precision adder configurable to add or subtract input data at multiple precisions.5. The general-purpose graphics processing unit as in claim 4 , the significand block including a dynamic precision multiplier configurable to add or multiply or divide input data at multiple precisions.6. The general-purpose graphics processing unit as in claim 5 , the dynamic precision floating point unit including an exponent block to perform an exponent portion of a floating-point computation claim 5 , the exponent block including a dynamic precision adder configurable to ...

COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS

One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction; the at least one single instruction to cause at least a portion of the GPU to perform a floating-point operation on input having differing precisions; and the floating-point operation is a two-dimensional matrix multiply and accumulate operation. 1. An accelerator on a multi-chip module , the accelerator comprising:a memory stack including multiple memory dies; anda graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction, the at least one single instruction to accelerate a linear algebra subprogram associated with a machine learning framework;the at least one single instruction to cause at least a portion of the GPU to perform a floating-point operation on input having differing precisions, the floating-point operation a two-dimensional matrix multiply and accumulate operation;wherein at least a portion of the plurality of multiprocessors include a mixed precision core, the mixed precision core to execute a thread of the at least one single instruction, the mixed precision core including a floating-point unit to perform a first operation of the thread at a first precision and a second operation of the thread at a second precision; andwherein the first operation is a multiply having at least one 16-bit floating-point input and the second operation is an accumulate having a 32-bit floating-point input.2. The accelerator as in claim 1 , the memory stack including high bandwidth ...

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation. 1. A machine-learning hardware accelerator comprising:a compute unit having an adder and a multiplier that are shared between an integer datapath and a floating-point datapath, the multiplier configured to gate upper bits of input operands during floating-point operation to enable computation of a mantissa product based on a first operand and second operand2. The machine-learning hardware accelerator as in claim 1 , the compute unit having a mode input to switch the compute unit between integer operation and floating-point operation.3. The machine-learning hardware accelerator as in claim 2 , the compute unit including an exponent unit and a mantissa unit claim 2 , wherein the exponent unit and the mantissa unit are included in the floating-point datapath and the integer datapath.4. The machine-learning hardware accelerator as in claim 3 , wherein the mode input is to enable a switch to provide a sign and an exponent of a first operand and second operand to the exponent unit to be processing during floating-point operation.5. The machine-learning hardware accelerator as in claim 4 , wherein the exponent unit includes an incrementer to increment upper bits of a sum output by the adder during integer operation claim 4 , the incrementer shared between floating point operation and integer operation.6. The machine-learning hardware accelerator as in claim 1 , the compute unit switchable between floating-point operation and integer operation on a per cycle basis.7. The machine-learning hardware accelerator as in claim 1 , the multiplier of the compute unit perform a multiply operation during a first stage of a fused multiply accumulate operation and an add operation during a second ...

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product. 1. A graphics processing unit to accelerate machine-learning operations , the graphics processing unit comprising:a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction across multiple threads of the multiprocessor, wherein at least a portion of a register file is dedicated to each of the multiple threads; anda first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.2. The graphics processing unit as in claim 1 , the multiprocessor to execute parallel threads of a thread group claim 1 , each thread of the thread group having independent thread state.3. The graphics processing unit as in claim 2 , the multiprocessor including a scheduler to schedule the parallel threads of the thread group to multiple compute units within the multiprocessor.4. The graphics processing unit as in claim 3 , the multiple compute units within the multiprocessor ...

GAMMA CURVE CORRECTION CIRCUIT AND GAMMA CURVE CORRECTION METHOD

A gamma curve correction circuit including a mapping module and a correction module. The mapping module maps data to be outputted into original mapped data via original bonding points on a gamma curve. The original bonding points at least include a first original bonding point, a second original bonding point, and a third original bonding point. The second original bonding point is located between the first original bonding point and third original bonding point. A first line between the first original bonding point and second original bonding point has a first slope; a second line between the second original bonding point and third original bonding point has a second slope. The correction module obtains a third line according to a first interpolating point on first line and a second interpolating point on second line. The third line has a third slope between the first slope and second slope. 1. A gamma curve correction circuit disposed in a display apparatus , the gamma curve correction circuit comprising:a mapping module configured to map a data to be outputted into an original mapped data via a plurality of original bonding points on a gamma curve, wherein the plurality of original bonding points at least comprises a first original bonding point, a second original bonding point and a third original bonding point; the second original bonding point is located between the first original bonding point and the third original bonding point; a first line between the first original bonding point and the second original bonding point has a first slope; a second line between the second original bonding point and third original bonding point has a second slope; anda correction module coupled to the mapping module and configured to obtain a third line according to a first interpolating point on the first line and a second interpolating point on the second line, wherein the third line has a third slope and the third slope is between the first slope and the second slope.2. The ...

Method of processing food and a product thereof

A method of processing food suitable for dysphagia patient comprising the steps of processing a food material into food puree, introducing first thickening agent and second thickening agent, mixing the food puree, the first and second thickening agents to form a food paste, inserting the food paste into a container with a preferred shape, and allowing the food paste to set; and a product manufactured by said method.

UNLOCKING CONTROL SYSTEM, METHOD AND WEARABLE DEVICE USING THE SAME

An unlocking control method is applied in a wearable device and a lockable electronic device. The wearable device communicates with the electronic device and can be bound to it. The wearable device can produce an unlocking setting instruction to set an unlocking mode of the electronic device, and can send the unlocking setting instruction to the bound electronic device. The wearable device can set the unlocking mode of the electronic device and produce an unlocking control instruction, sending the unlocking control instruction to the electronic device. The electronic device receives the unlocking control instruction, and is controlled to unlock itself according to the received unlocking control instruction and the unlocking mode of the electronic device. 1. A wearable device comprising:a communication unit;at least one processing unit electrically coupled to the communication unit; and communicate with an electronic device having an unlocking function;', 'bind the electronic device with the wearable device;', 'produce an unlocking setting instruction to set an unlocking mode of the electronic device;', 'send the unlocking setting instruction to the electronic device bound with the wearable device; and', 'produce an unlocking control instruction and send the unlocking control instruction to the electronic device to unlock the electronic device., 'a non-transitory storage medium coupled to the at least one processing unit and configured to store a plurality of instructions, the plurality of instructions causing the wearable device to2. The wearable device as recited in claim 1 , further comprising a display unit claim 1 , wherein the non-transitory storage medium stores a first identifier representing identification information of the wearable device claim 1 , the electronic device stores a second identifier representing identification information of the electronic device claim 1 , and the plurality of instructions further cause the wearable device to:display a ...

DISPLAY DRIVING APPARATUS

A display driving apparatus is disclosed. The display driving apparatus includes a data processing unit, a first setting unit, a second setting unit, a mapping unit and a source driving unit. The data processing unit receives and processes an image data including data lines. The first setting unit generates a first setting signal corresponding to a first gamma value. The second setting unit generates a second setting signal corresponding to a second gamma value. The mapping unit maps the first gamma value and second gamma value to odd-numbered data lines and even-numbered data lines of the data lines respectively according to the first setting signal and second setting signal. The source driving unit outputs the first gamma value and second gamma value to odd-numbered display lines and even-numbered display lines of display lines of a display panel respectively. 1. A display driving apparatus , coupled to a display panel and driving the display panel , the display panel comprising a plurality of display lines , the display driving apparatus comprising:a data processing unit, for receiving and processing an image data, wherein the image data comprising a plurality of data lines;a first setting unit, for generating a first setting signal corresponding to a first gamma value;a second setting unit, for generating a second setting signal corresponding to a second gamma value;a mapping unit, coupled to the data processing unit, the first setting unit and the second setting unit, for mapping the first gamma value and the second gamma value to odd-numbered data lines and even-numbered data lines of the plurality of data lines according to the first setting signal and the second setting signal respectively; anda source driving unit, coupled between the mapping unit and the display panel, for outputting the first gamma value and the second gamma value to odd-numbered display lines and even-numbered display lines of the plurality of display lines of the display panel ...

Display Driving Apparatus And Operating Method Thereof

A display driving apparatus includes a compression module, a storing module, a reading control module and a decompression module. The compression module performs 1-bit compression on an input data signal to generate a 1-bit compressed data and non-black data and store them in the storing module. The non-black data includes color information of each non-black bit in the input data signal. The reading control module reads the 1-bit compressed data from the storing module and the decompression module performs 1-bit decompression on the 1-bit compressed data to generate an output data signal. When the decompression module performs 1-bit decompression, the decompression module determines whether each bit of the 1-bit compressed data corresponds to black. If yes, the bit is displayed in black; if no, the reading control module reads a color corresponding to the bit from the non-black data stored in the storing module and the bit is displayed in the color. 1. A display driving apparatus , coupled to a display panel , the display driving apparatus comprising:a compression module, for performing 1-bit compression on an input data signal to generate a 1-bit compressed data and a non-black data, wherein the non-black data comprises color information of each non-black bit in the input data signal;a storing module, coupled to the compression module, for storing the 1-bit compressed data and the non-black data;a reading control module, coupled to the storing module; anda decompression module, coupled to the reading control module, wherein the reading control module reads the 1-bit compressed data from the storing module and the decompression module performs 1-bit decompression on the 1-bit compressed data to generate an output data signal;wherein when the decompression module performs the 1-bit decompression on the 1-bit compressed data, the decompression module determines whether each bit of the 1-bit compressed data corresponds to black respectively; if yes, the bit is directly ...

PERSON TRACKING AND PRIVACY AND ACCELERATION OF DATA USING AUTONOMOUS MACHINES

A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

FAX AND PRINT METHOD AND FAX SYSTEM USING SAME

A fax and print method includes steps of providing a first fax device, a second fax device and a portable communication device, allowing the first fax device to send a fax password and a document to the second fax device and a data message and a text message corresponded to the fax password to the portable communication device, allowing the portable communication device to receive the text message and the data message, allowing the second fax device to receive the fax password and the document, generating a wireless connection between the portable communication device and the second fax device, judging if the text message is matched with the fax password, and printing the document when the result of the judgement is True. Therefore, the risk of being stolen is reduced through a transmission without the internet. The user does not have to remember any password. The user experiences are enhanced. 1. A fax and print method , comprising steps of:(a) providing a first fax device, a second fax device and a portable communication device;(b) allowing the first fax device to send a fax password and a document to the second fax device and send a text message, which is corresponded to the fax password, and a data message to the portable communication device, wherein the text message and the data message is transmitted to the portable communication device through Public Switched Telephone Network by the first fax device;(c) allowing the portable communication device to receive the text message and the data message;(d) allowing the second fax device to receive the fax password and the document;(e) generating a wireless connection between the portable communication device and the second fax device;(f) judging if the text message is matched with the fax password; and(g) printing the document,wherein when the result of the judgement of the step (f) is True, the step (g) is performed after the step (f).2. The fax and print method according to further comprising steps claim 1 , after ...

OPTICAL COMPENSATION APPARATUS APPLIED TO PANEL AND OPERATING METHOD THEREOF

An optical compensation apparatus applied to a panel is disclosed. The panel includes sub-pixels for displaying a display data. The optical compensation apparatus includes an optical measurement module, a data processing module and an optical compensation module. The optical measurement module is used to measure optical measurement values corresponding to the sub-pixels of the panel. The data processing module is coupled to the optical measurement module and used for determining whether the sub-pixels are abnormal according to the optical measurement values. If the above determining result is yes, the data processing module generates at least one optical compensation value corresponding to at least one abnormal sub-pixel according to a specific processing rule. The optical compensation module is coupled to the data processing module and used for outputting the optical compensation value to perform optical compensation on the display data. 1. An optical compensation apparatus , applied to a panel comprising a plurality of sub-pixels for displaying a display data , the optical compensation apparatus comprising:an optical measurement module, for measuring a plurality of optical measurement values corresponding to the plurality of sub-pixels of the panel;a data processing module, coupled to the optical measurement module, for determining whether the plurality of sub-pixels is abnormal according to the plurality of optical measurement values, wherein if a determining result of the data processing module is yes, the data processing module generates at least one optical compensation value corresponding to at least one abnormal sub-pixel of the plurality of sub-pixels according to a specific processing rule; andan optical compensation module, coupled to the data processing module, for outputting the at least one optical compensation value to perform optical compensation on the display data.2. The optical compensation apparatus of claim 1 , wherein the panel is an organic ...

OPTICAL COMPENSATION APPARATUS APPLIED TO PANEL AND OPERATING METHOD THEREOF

An optical compensation apparatus applied to a panel is disclosed. The panel includes sub-pixels for displaying a display data. The optical compensation apparatus includes an optical measurement module, a data processing module and an optical compensation module. The optical measurement module measures optical measurement values corresponding to the sub-pixels. The data processing module determines first optical compensation values needed for the sub-pixels according to the optical measurement values respectively, divides the sub-pixels into optical compensation regions according to at least one threshold compensation value and the first optical compensation values, and then generates second optical compensation values corresponding to the optical compensation regions respectively. The optical compensation module outputs the second optical compensation values to perform optical compensation on the display data. 1. An optical compensation apparatus , applied to a panel comprising a plurality of sub-pixels for displaying a display data , the optical compensation apparatus comprising:an optical measurement module, for measuring a plurality of optical measurement values corresponding to the plurality of sub-pixels of the panel;a data processing module, coupled to the optical measurement module, for determining first optical compensation values needed for the plurality of sub-pixels according to the plurality of optical measurement values respectively, dividing the plurality of sub-pixels into a plurality of optical compensation regions according to at least one threshold compensation value and the plurality of first optical compensation values, and then generating a plurality of second optical compensation values corresponding to the plurality of optical compensation regions respectively; andan optical compensation module, coupled to the data processing module, for outputting the plurality of second optical compensation values to perform optical compensation on the ...

IDENTITY AUTHENTICATION METHOD, APPARATUS, AND SYSTEM

When a security authentication request sent by a terminal is received, an identity authentication solution includes acquiring network environment information and user behavior data according to the security authentication request, then determining, according to the network environment information and the user behavior data, whether a current operation is a machine attack, and acquiring a CAPTCHA of a predetermined type according to a predetermined policy and delivering the CAPTCHA to the terminal if the current operation is a machine attack, to perform identity authentication, or determining that security authentication succeeds if the current operation is not a machine attack. 1. An identity authentication method , the method comprising:receiving a security authentication request sent by a computing device;acquiring network environment information and user behavior data according to the security authentication request;detecting a current operation on the computing device;determining, according to the network environment information and the user behavior data, whether the current operation is a machine attack; andacquiring a CAPTCHA of a predetermined type according to a predetermined policy;delivering the CAPTCHA to the computing device when the current operation is determined to be the machine attack, wherein the CAPTCHA is used to perform identity authentication; anddetermining that security authentication is successful when the current operation is determined not to be the machine attack.2. The method according to claim 1 , wherein acquiring the CAPTCHA of the predetermined type according to the predetermined policy comprises:evaluating a possibility that the current operation is the machine attack; andacquiring the CAPTCHA having a corresponding type according to a result of the evaluating.3. The method according to claim 1 , wherein acquiring the CAPTCHA of the predetermined type according to the predetermined policy comprises:acquiring a service identifier ...

HEADPHONE STRUCTURE FOR ADJUSTING AUDIO FREQUENCIES

A headphone structure for adjusting audio frequencies is provided, which comprises a front housing, a rear housing, a sound-producing unit in the front housing and an elastic ear-contacting body sleeving the front housing. The front housing has at least one slot or recess, and the elastic ear-contacting body sleeves the front housing to form at least one gap. The headphone structure for adjusting audio frequencies of the present invention has better results for the adjustment of bass frequencies. In addition, the headphone structure of the present invention is not complicated and is easy to manufacture. The headphone structure of the present invention can be applied to various types of headphone, such as in-ear headphones and circumaural headphones. 1. A headphone structure for adjusting audio frequencies , comprising a front housing , a rear housing , a sound-producing unit in the front housing and an elastic ear-contacting body sleeving the front housing , characterized in that the front housing is provided with at least one slot or recess , and the elastic ear-contacting body sleeves the front housing to form at least one gap.2. The headphone structure for adjusting audio frequencies as claimed in claim 1 , characterized in that the headphone is an in-ear headphone claim 1 , the elastic ear-contacting body is an elastic plug claim 1 , and the in-ear headphone further comprises a mesh cap for covering the front housing of the headphone.3. The headphone structure for adjusting audio frequencies as claimed in claim 2 , characterized in that the elastic plug is provided with a base ring claim 2 , the front housing is provided with a step for engaging with the base ring claim 2 , and a contacting surface of the base ring and the step is a concave-convex surface.4. The headphone structure for adjusting audio frequencies as claimed in claim 1 , characterized in that the headphone is a circumaural headphone claim 1 , and the elastic ear-contacting body is an elastic ...

OPTICAL COMPENSATION APPARATUS APPLIED TO PANEL AND OPERATING METHOD THEREOF

An optical compensation apparatus applied to panels is disclosed. A panel of the panels includes sub-pixels. The optical compensation apparatus includes an optical measurement module, a data processing module and an optical compensation module. The optical measurement module measures optical measurement values corresponding to the sub-pixels. The data processing module determines first optical compensation values needed for the sub-pixels according to the optical measurement values, determines an overall compensation operation reference of the panel accordingly, determines a demura algorithm suitable for the panel according to at least one threshold compensation value and the overall compensation operation reference and obtains second optical compensation values accordingly. Then, the optical compensation module outputs the second optical compensation values to perform optical compensation on a display data provided to the panel. 1. An optical compensation apparatus , applied to a plurality of panels , a first panel of the plurality of panels comprising a plurality of sub-pixels for displaying a display data , the optical compensation apparatus comprising:an optical measurement module, for measuring a plurality of first optical measurement values corresponding to the plurality of sub-pixels of the first panel;a data processing module, coupled to the optical measurement module, for determining a plurality of first optical compensation values needed for the plurality of sub-pixels according to the plurality of first optical measurement values respectively, determining a first overall compensation operation reference of the first panel according to the plurality of first optical compensation values, determining a first demura algorithm suitable for the first panel according to at least one adjustable threshold compensation value and the first overall compensation operation reference and obtaining a plurality of second optical compensation values according to the first ...

COMPUTE OPTIMIZATION MECHANISM

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 8-bit and/or 32 bit signed or unsigned integer elements. 1. An apparatus comprising:an interconnect fabric comprising one or more fabric switches;a memory controller coupled to the interconnect fabric;an input/output (IO) interface coupled to the interconnect fabric; a plurality of packed data registers to store first, second, third, and fourth packed floating-point source values at a first precision using a first number of bits, and to store at least one packed floating-point value at a second precision using a second number of bits equal to at least twice the first number of bits; and', 'mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising:', 'multiplying the first packed floating point source value and the second packed floating point source value to generate a first intermediate product at the second precision,', 'multiplying the third packed floating-point source value and the fourth packed floating-point source value to generate a second intermediate product at the second precision, and', 'generating a result value at the second precision comprising a sum of at least the first intermediate product and the second intermediate product., 'an array of multiprocessors coupled to the interconnect fabric to process mixed-precision instructions, at least one multiprocessor comprising2. The apparatus of further comprising:a semiconductor substrate;a parallel processor die comprising the interconnect fabric, memory controller, input/output (IO) interface, and array of multiprocessors mounted on the semiconductor substrate;a 3D memory stack comprising a plurality of stacked memory dies mounted on the semiconductor substrate; anda local memory interconnect to couple the ...

COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS

Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple precisions. 1. An apparatus comprising:a semiconductor substrate;a 3D memory stack comprising a plurality of stacked memory dies integrated on the semiconductor substrate;a parallel processor die mounted on the semiconductor substrate;a local memory interconnect to couple the parallel processor die to the 3D memory stack, the local memory interconnect comprising a plurality of memory interfaces, each memory interface associated with a memory die of the plurality of stacked memory dies; an interconnect fabric comprising one or more crossbar switches;', 'a memory controller coupled to the local memory interconnect via the memory interfaces to provide access to the 3D memory stack, the memory controller coupled to the interconnect fabric;', {'b': '0', 'an input/output (I) interface coupled to the interconnect fabric;'}, 'an array of multiprocessors coupled to the interconnect fabric to process mixed-precision dot-product instructions, at least one multiprocessor comprising:, 'the parallel processor die comprisinga plurality of packed data registers to store a plurality of packed data elements at a first precision; andmixed-precision execution circuitry to execute the mixed-precision dot-product instructions, the mixed-precision execution circuitry to perform a plurality of multiplications of different pairs of the plurality of packed data elements to generate a ...

Display driving apparatus and operating method thereof

A display driving apparatus applied to a panel. The panel displays a first image with a first refresh rate. A first refresh cycle corresponding to the first refresh rate includes a refresh period and at least one non-refresh period. The display driving apparatus includes a real-time determination module and a data processing module. The real-time determination module is coupled to the panel and used to immediately determine whether the panel wants to replace the originally displayed first image with a second image during the first refresh cycle. The data processing module is coupled to the real-time determination module and the panel. If a determination result of the real-time determination module is yes, the data processing module immediately controls the panel to start to display the second image at a first time during the first refresh cycle.

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product. 1. A graphics processing unit to accelerate machine-learning operations , the graphics processing unit comprising:a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; anda first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.2. The graphics processing unit as in claim 1 , the multiprocessor to execute parallel threads of a thread group claim 1 , each thread of the thread group having independent thread state.3. The graphics processing unit as in claim 2 , the multiprocessor including a scheduler to schedule the parallel threads of the thread group to multiple compute units within the multiprocessor.4. The graphics processing unit as in claim 3 , the multiple compute units within the multiprocessor including a second compute unit to perform an integer operation claim 3 , the scheduler to schedule a floating-point operation to the ...

Instructions and logic to perform floating point and integer operations for machine learning

One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.

Field-Effect Transistor (FET) Based Synchronous Rectifier For Emulating Diode

A field-effect transistor (FET) based synchronous rectifier for emulating a diode, comprising: a first terminal () and a second terminal (); a first FET (M) and a second ELT (M), wherein the second FET (M) is adapted to control operation of the first FET (M) to thereby allow unidirectional current flow when the two terminals () are connected with an external circuit; and wherein the FET based synchronous rectifier comprises a fully integrated single-chip device () adapted to emulate a diode. 1. A field-effect transistor (FET) based synchronous rectifier , comprising:a first terminal and a second terminal;{'b': 1', '2, 'a first FET (M) and a second FET (M),'}{'b': 2', '1, 'wherein the second FET (M) is adapted to control operation of the first FET (M) to thereby allow unidirectional current flow when the two terminals are connected with an external circuit; and'}wherein the FET based synchronous rectifier comprises a fully integrated single-chip device adapted to emulate a diode.2. The FET based synchronous rectifier according to claim 1 , wherein the fully integrated single-chip device comprises equal to or less than 15 discrete electronic devices or components integrated in said chip.3. The FET based synchronous rectifier according to claim 1 , wherein the first terminal is provided on a first or top metal surface of the fully integrated single-chip device and the second terminal is provided on a second or bottom metal surface of the fully integrated single-chip device.4. The FET based synchronous rectifier according to claim 3 , wherein the first or top metal surface of the fully integrated single-chip device comprises an anode and the second or bottom metal surface of the fully integrated single-chip device comprises a cathode.5. The FET based synchronous rectifier for emulating a diode according to claim 1 , wherein the single-chip device has only two terminals.612. The FET based synchronous rectifier according to claim 1 , wherein the first FET (M) comprises a ...

System and method for a moveable barrier operator

A communication protocol is employed between a movable barrier operator and an associated wall button using the traditional signaling wires connecting them. Implementing the communication protocol using the existing signaling wires also allows backward compatibility with the traditional push wall buttons that have a physical contact switch. In one embodiment, the communication protocol allows bi-directional communication between the moveable barrier operator and the wall button. The bi-directional embodiment of the protocol allows further communications, such as handshaking, signal confirmation and more advanced control between the wall unit and the barrier operator.

Converting mathematical functions to power series

A processor based system may convert a mathematical function to a power series converging on that function. One or more sets of coefficients for the power series may be pre-computed and stored in machine readable storage medium. In response to a request to execute the mathematical function, the processor obtains coefficients of the terms of the power series from storage and sums up the terms.

Photographic material and process comprising a bicyclic pyrazolo coupler

Novel bicyclic pyrazolo couplers containing a ballast group of formula (I): ##STR1## are useful in photographic materials and processes. The couplers exhibit increased coupling activity, and provide formation of dyes having improved maximum magenta image dye density, hue, and dye light stability when employed in color photographic materials and processes.

Multiple image projection apparatus

Fourier transform computation for distributed processing environments

Fourier transform computation for distributed processing environments is disclosed. Example methods disclosed herein to compute a Fourier transform of an input data sequence include performing first processing on the input data sequence using a plurality of processors, the first processing resulting in an output data sequence having more data elements than the input data sequence Such example methods also include performing second processing on the output data sequence using the plurality of processors, the output data sequence being permutated among the plurality of processors, each of the processors performing the second processing on a respective permutated portion of the output data sequence to determine a respective, ordered segment of the Fourier transform of the input data sequence.

Multicore processor each core having independent floating-point datapath and integer datapath

A general-purpose graphics processing unit is described. The graphics processing unit includes a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading, wherein the streaming multiprocessor comprises a first processing block including a first processing core having a first floating-point data path and a second processing core having a first integer data path, the first integer data path independent of the first floating-point data path, wherein the first integer data path is to enable execution of a first instruction and the first floating-point data path is to enable execution of a second instruction, the first instruction to be executed concurrently with the second instruction; a second processing block including a third processing core having a second floating-point data path and a fourth processing core having a second integer data path, the second integer data path independent of the second floating-point data path, wherein the second integer data path is to enable execution of a third instruction and the second floating-point data path is to enable execution of a fourth instruction, the third instruction to be executed concurrently with the fourth instruction; and a memory coupled with the first processing block and the second processing block.

Instructions and logic to perform floating-point and integer operations for machine learning

One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.

Multi-core processor, each core featuring a separate floating point data path and independent integer data path

Una unidad de procesamiento de gráficos de propósito general (214), que incluye: un multiprocesador de transmisión continua (234, 1400) que tiene una arquitectura de tipo "una sola instrucción, múltiples subprocesos", SIMT, que incluye múltiples subprocesos de hardware, donde el multiprocesador de transmisión continua (234, 1400) comprende: múltiples conjuntos de unidades de cálculo (1411-1418), presentando cada unidad de cálculo (1411-1418) una unidad lógica de coma flotante (1411B - 1418B) configurada para realizar operaciones de coma flotante y una unidad lógica de números enteros (1411A - 1418A) configurada para realizar operaciones de números enteros; y una memoria (270, 272) acoplada a los múltiples conjuntos de unidades de cálculo, caracterizada por que en una unidad de cálculo, la unidad lógica de números enteros está habilitada para ejecutar un subproceso de una primera instrucción, mientras que la unidad lógica de coma flotante está habilitada para ejecutar un subproceso de una segunda instrucción, siendo la segunda instrucción diferente de la primera instrucción y ejecutándose el subproceso de la primera instrucción simultáneamente con el subproceso de la segunda instrucción. A general purpose graphics processing unit (214), including: a streaming multiprocessor (234, 1400) having a "single instruction, multi-threaded" architecture, SIMT, including multiple hardware threads, wherein the streaming multiprocessor (234, 1400) comprises: multiple sets of computing units (1411-1418), each computing unit (1411-1418) having a floating point logic unit (1411B-1418B) configured to perform operations floating point and integer logic unit (1411A - 1418A) configured to perform integer operations; and a memory (270, 272) coupled to the multiple sets of calculation units, characterized in that in a calculation unit, the integer logic unit is enabled to execute a thread of a first instruction, while the logic unit of floating point is enabled to execute ...

Continuous automatic stamping die

本实用新型公开了一种连续自动冲压模具，包括下模座，所述下模座的顶面固定安装有限位导柱，所述限位导柱的顶部活动套接有限位导套，所述限位导套的上表面固定安装有上模座，所述上模座顶面的中部固定安装有连接座，所述上模座的底面固定安装有凸模固定板，所述凸模固定板的底部固定安装有凸模。该连续自动冲压模具，通过拉动把手，即可带通过连接挡板和工件承纳板带动限位柱滑动，使限位球与限位凹孔孔壁挤压，向收纳槽内部滑动并挤压弹簧，当限位球与另一限位凹孔重合时，即可在弹簧作用下弹出插入限位凹孔内，从而使工件承纳板移动并再次固定，从而达到了便于更换工件以进行连续冲压操作的效果，操作起来更加灵活，更加方便。

Method for renewing program code in an embedded micro-controller unit

The embedded micro-controller unit includes a serial interface according to the present invention. A program control device connects the embedded micro-controller unit. The serial interface will send a request signal to a micro-processor while renewing program codes. The micro-processor will transfer the power of controlling program memory to the serial interface and then go into idle state or halt state after receiving the request signal. The program control device may directly write new program codes into the program memory through the serial interface.

Bending die with springback compensation function

本实用新型公开了一种具有回弹补偿功能的折弯模具，包括工作台，所述工作台的上表面对称固定连接有支撑柱，两个所述支撑柱之间设有底模，两个所述支撑柱的顶端均固定连接有同一个横板，所述横板的底部开设有安装槽，所述安装槽的顶部内表面固定连接有液压缸，所述液压缸的底部设有液压杆，所述液压杆的底端固定连接有升降板，所述升降板与两个所述支撑柱之间滑动连接，所述升降板的下表面固定连接有顶模座，所述顶模座的下表面固定连接有冲压块。本实用新型设计简单，操作方便，可以防止工件在自身弹性的作用下发生回弹现象的发生，使得折弯的产品能够合格，并且还可以方便工件能够脱离冲压腔，便于卸料。

Graphics processing integrated circuit package

An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Instructions and logic to perform floating point and integer operations for machine learning

Una unidad de procesamiento de gráficos, GPU, para acelerar operaciones de aprendizaje automático, comprendiendo la GPU: un multiprocesador (1400) en donde el multiprocesador (1400) ha de ejecutar una misma instrucción para múltiples hilos y de ejecutar hilos paralelos de un grupo de hilos, teniendo cada hilo del grupo de hilos un estado de hilo independiente, siendo la instrucción para hacer que una primera unidad de cómputo (1411,..., 1418) realice al menos una operación de multiplicación de matrices bidimensionales; en donde la operación se realiza sobre tres operandos de entrada enteros sin signo de 16 bits a, b y c, e incluye computar, por un multiplicador de 16 bits × 16 bits con signo, un producto intermedio de 32 bits entre un operando entero sin signo de 16 bits a y un operando de entrada entero sin signo de 16 bits b y computar, por un sumador de 32 bits, una suma de 32 bits basándose en el producto intermedio de 32 bits y en un operando de entrada entero sin signo de 16 bits c. A graphics processing unit, GPU, for accelerating machine learning operations, the GPU comprising: a multiprocessor 1400 wherein the multiprocessor 1400 is to execute a single instruction for multiple threads and to execute parallel threads from a group of threads, each thread of the thread group having an independent thread state, the instruction being to cause a first computing unit (1411,..., 1418) to perform at least one two-dimensional matrix multiplication operation; where the operation is performed on three 16-bit unsigned integer input operands a, b, and c, and includes computing, by a signed 16-bit × 16-bit multiplier, a 32-bit intermediate product between an unsigned integer operand of 16-bit a and a 16-bit unsigned integer input operand b and compute, by a 32-bit adder, a 32-bit sum based on the 32-bit intermediate product and a 16-bit unsigned integer input operand c.

Photographic material and process comprising a bicyclic pyrazolo coupler

Novel bicyclic pyrazolo couplers contain a sulfone group of formula (I):         -L-NHC(=O)-(L) n -B-SO₂-R¹   I wherein:    each L is independently a divalent group linking the adjacent groups;    n is 0 or 1;    B is a divalent group selected from aryl, aryloxy, aryloxyalkyl, and -C(R²)(R³)- wherein R² and R³ are independently hydrogen or alkyl; and    R¹ is a substituted or unsubstituted alkyl having 1 to 22 carbon atoms These couplers are useful in photographic materials and processes. They exhibit improved color reproduction and dye light stability when employed in color photographic materials and processes.

Systems and methods for nonlinear tooth modeling

Systems and methods of generating an orthodontic model are disclosed. The method may include: generating an initial model of a patient dentition; generating a target model of the patient dentition; defining a plurality of caps and a plurality of links, wherein each link connects two of the plurality of caps; generating a relaxed model of a dental appliance from the plurality of caps and the plurality of links; generating a deformed model of a dental appliance from the plurality of caps and plurality of links; and determining a plurality of movements, wherein the plurality of moments transform the relaxed model to the deformed model and wherein the moments are configured to direct the patient dentition from the initial model to the target model.

Biochemical reagent

ABSTRACT A biochemical reagent comprises an oligosaccharide, preferably one which has been liberated from an immunogenic glycoprotein or proteoglycan, which is immobilized on a carrier via an intermediate spacer molecule such as a lipid. The lipid molecule should preferably have at least two long lipid tails so that the oligosaccharide is held in spaced relationship to the carrier where is exhibits antibody-binding ability which is almost indistinguishable from that of the original glycoprotein or proteoglycan. The reagent has its application in biochemical teating of oligosaccharides and systems which bind to them.

Photographic dye-forming coupler, emulsion layer, element, and process

The invention provides a photographic light sensitive silver halide emulsion layer having associated therewith a pyrazolotriazole dye-forming coupler having formula: ##STR1## wherein: R 1 is a substituent bonded to the pyrazolotriazole nucleus by a fully substituted carbon atom; X is hydrogen or a coupling-off group; R 2 , R 3 , R 4 , and R 6 are independently hydrogen or substituent groups; q is from 1 to 3; R 5 and R 7 are independently alkyl, alkoxy, aryl, or aryloxy groups; G is a substituent group and n is from 0 to 3; and Y is a substituent group and m is 0 to 4. The invention also provides a coupler compound, a photographic element containing the emulsion layer of the invention, and an imaging process.

A battery

A battery 230 comprises electrode assemblies 210 arranged substantially in parallel with each other. A current collector plate 220 is arranged to be directly electrically in contact with first ends of the plurality of electrode assemblies. The electrical contact may be achieved by means of laser welding, for example. A further battery comprises at least one “jelly-roll” electrode assembly having a first end formed such that edge portions of one of a number of separated electrode layers are overlapped to form a layered electrode structure (18, Figure 2) wherein a current collector plate is in direct electrical contact with a first end of the jelly-roll by laser welding onto the layered electrode structure. A further battery comprises an electrode assembly positioned in a housing by means of an electrode assembly holder 240 having a peripheral wall conforming to an inside surface of the housing wherein an upper peripheral wall section of the holder 240U is adapted to engage a battery terminal, for example by means of screw-threading. A nickel based battery comprises a plurality of electrode assemblies arranged within a housing and a current collector plate electrically connected to the plurality of electrode assemblies.

Apparatus and method for remainder calculation using short approximate floating-point quotient

An apparatus and method for creating lookup tables of approximate floating-point quotients which exactly represent the underlying value, within the range of the specified precision. The lookup tables are created without any extraneous data beyond what is needed and also without sacrificing numerical accuracy, and may be creating for any radix.

Dynamic precision for neural network compute operations

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Multicore processor each core having independent floating-point datapath and integer datapath