GAAS INGOT, METHOD FOR MANUFACTURING GAAS INGOT, AND GAAS WAFER

The present invention provides a GaAs ingot that enables the acquisition of a low-dislocation density GaAs wafer, said GaAs wafer having a carrier concentration of 5.5×1017cm-3 or less and an average dislocation density of 500/cm2 or less, by adding thereto Si together with a small amount of In. The GaAs ingot wherein the seed side and center of the drum part thereof have each a silicon concentration of 2.0×1017 cm-3 or more and less than 1.5×1018 cm-3, an indium concentration of 1×1017 cm-3 or more and less than 6.5×1018cm-3, a carrier concentration of 5.5×1017cm-3 or less, and an average dislocation density of 500/cm2 or less.

ULTRAVIOLET-LIGHT-RECEIVING ELEMENT

Provided is an ultraviolet-light-receiving element that has light-receiving sensitivity effective for a target wavelength in the ultraviolet region. A Schottky-junction-type ultraviolet-light-receiving element, wherein: there is a light-receiving sensitivity peak wavelength in the ultraviolet ray region of 230-320 nm (inclusive); and the rejection rate, which is the ratio (Rp/Rv) of a responsivity Rp at the light-receiving sensitivity peak wavelength to an average value Rv of the responsivity of the visible region of 400-680 nm (inclusive), is 105 or greater.

GaAs WAFER AND METHOD FOR PRODUCING GaAs INGOT

Provided are a GaAs wafer that is particularly suitable for LiDAR sensor production and a method for producing a GaAs ingot that enables obtaining this GaAs wafer. This GaAs wafer includes: a silicon concentration of 5.0 x 1017 cm-3 or greater but less than 3.5 x 1018 cm-3; an indium concentration of 3.0 x 1017cm-3 or greater but less than 3.0 x 1019 cm-3; and a boron concentration of 1.0 x 1018 cm-3 or greater. The average dislocation density is 1500 dislocations/cm2 or less.

VERTICALLY STRUCTURED GROUP III NITRIDE SEMICONDUCTOR LED CHIP AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing vertically structured Group III nitride semiconductor LED chips includes a step of forming a light emitting laminate on a growth substrate; a step of forming a plurality of separate light emitting structures by partially removing the light emitting laminate to partially expose the growth substrate; a step of forming a conductive support on the plurality of light emitting structures; a step of lifting off the growth substrate from the plurality of light emitting structures; and a step of cutting the conductive support thereby singulating a plurality of LED chips each having the light emitting structure. The step of partially removing the light emitting laminate is performed such that each of the plurality of light emitting structures has a top view shape of a circle or a 4n-gon en” is a positive integer) having rounded corners. 1. A method for manufacturing vertically structured Group III nitride semiconductor LED chips , comprising:a light emitting laminate formation step of forming a light emitting laminate by sequentially stacking a first conductivity type Group III nitride semiconductor layer, a light emitting layer, and a second conductivity type Group III nitride semiconductor layer on a growth substrate, the second conductivity type being different from the first conductivity type;a light emitting structure formation step of forming a plurality of separate light emitting structures by partially removing the light emitting laminate to partially expose the growth substrate;a step of forming an ohmic electrode layer and a connection layer on the plurality of light emitting structures;a step of forming a conductive support which also serves as a lower electrode on the connection layer;a separation step of lifting off the growth substrate from the plurality of light emitting structures; anda cutting step of cutting the conductive support between the light emitting structures thereby singulating a plurality of LED chips each having the ...

METHOD OF PRODUCING GROUP III NITRIDE SEMICONDUCTOR GROWTH SUBSTRATE

An object of the present invention is to provide a method for producing a Group III nitride semiconductor epitaxial substrate, a Group III nitride semiconductor element, and a Group III nitride semiconductor free-standing substrate, which have good crystallinity, with not only AlGaN, GaN, and GaInN the growth temperature of which is 1050° C. or less, but also with AlGaN having a high Al composition, the growth temperature of which is high; a Group III nitride semiconductor growth substrate used for producing these, and a method for efficiently producing those. The present invention provides a Group III nitride semiconductor growth substrate comprising a crystal growth substrate including a surface portion composed of a Group III nitride semiconductor which contains at least Al, and a scandium nitride film formed on the surface portion are provided. 1. A method of producing a Group III nitride semiconductor growth substrate , comprising:a step of forming a metal layer made of a Sc material on a crystal growth substrate including a surface portion composed of a Group III nitride semiconductor which contains at least Al, anda step of performing a nitriding process by heating the metal layer in an ambient gas containing an ammonia gas, thereby forming a scandium nitride film.2. The method of producing a Group III nitride semiconductor growth substrate claim 1 , according to claim 1 , wherein the ambient gas containing the ammonia gas is a mixed gas further containing one or more selected from an inert gas and a hydrogen gas.3. The method of producing a Group III nitride semiconductor growth substrate claim 1 , according to claim 1 , wherein a highest temperature for heating the metal layer is in the range of 850° C. to 1300° C. claim 1 , and heating time at 850° C. or higher is 1 min to 120 min.4. The method of producing a Group III nitride semiconductor growth substrate claim 1 , according to claim 1 , further comprising a step of forming an initial growth layer ...

SEMICONDUCTOR DEVICE ASSEMBLY AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing, at a reduced cost, a semiconductor device assembly and a semiconductor device, having a conductive support which is not eroded by an etchant for a lift-off layer even when the lift-off layer is made of a material for which no suitable selective etching solution has been found is provided. In the method of manufacturing the semiconductor device assembly, a plating step of forming a conductive support is carried out such that a first metal which is dissolved with an etchant is encapsulated in second metal which are not dissolved with the etchant, and through-holes for supplying etchant are formed in the second metal. 1. A method of manufacturing a semiconductor device assembly , comprising:a step of forming a lift-off layer and a semiconductor layer in this order on a growth substrate;a step of partially removing the semiconductor layer to form grooves in the bottom of which the growth substrate or the lift-off layer is partially exposed, thereby forming a plurality of separate semiconductor structures;a plating step of forming a conductive support for integrally supporting the plurality of the semiconductor structures by plating; anda chemical lift-off step of separating the growth substrate from the plurality of semiconductor structures by removing the lift-off layer using a given etchant,wherein the plating step is performed such that a first metal which can be dissolved in the etchant is encapsulated in a second metal which are not dissolved in the etchant in the conductive support, and through-holes communicating with the grooves are formed in the second metal, andthe etchant is supplied to the grooves through the though holes in the chemical lift-off step.2. The method of manufacturing a semiconductor device assembly according to claim 1 , wherein the plating step comprises the steps of:forming a first plating layer made of the second metal on the semiconductor structure;forming a second plating layer made of the first metal partially ...

Vertically structured group iii nitride semiconductor led chip and method for manufacturing the same

A method for manufacturing vertically structured Group III nitride semiconductor LED chips includes a step of forming a light emitting laminate on a growth substrate; a step of forming a plurality of separate light emitting structures by partially removing the light emitting laminate to partially expose the growth substrate; a step of forming a conductive support on the plurality of light emitting structures; a step of lifting off the growth substrate from the plurality of light emitting structures; and a step of cutting the conductive support thereby singulating a plurality of LED chips each having the light emitting structure. The step of partially removing the light emitting laminate is performed such that each of the plurality of light emitting structures has a top view shape of a circle or a 4n-gon (“n” is a positive integer) having rounded corners.

Semiconductor device and manufacturing method therefor

The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are aequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

LIGHT-EMITTING ELEMENT CHIP AND MANUFACTURING METHOD THEREFOR

There is provided a light-emitting element chip which can be safely assembled and a manufacturing method therefor. A light-emitting element chip has a semiconductor layer including a luminescent layer on a supporting portion . The supporting portion has a concave shape, providing a support substrate in this light-emitting element chip , and being connected to one electrode on the semiconductor layer . The outer peripheral portion of the supporting portion (a supporting portion outer peripheral portion ) surrounds the semiconductor layer , and is protruded to be set at a level higher than the other face and the n-side electrode of the semiconductor layer 1. A light-emitting element chip , comprising a configuration in which a semiconductor layer having a luminescent layer is formed on a conductive supporting portion , said supporting portion being connected to one electrode connected to one face of said semiconductor layer ,irregularities being formed on the other face of said semiconductor layer, and the other electrode being formed on said other face,said supporting portion having an outer peripheral portion surrounding the periphery of the other face of said semiconductor layer, with the outer peripheral portion being protruded to above the other face of said semiconductor layer and said other electrode.2. The light-emitting element chip according to claim 1 , wherein the top portion of said outer peripheral portion is located higher than the surface of said other electrode by 0.2 μm or over.3. The light-emitting element chip according to claim 1 , wherein the side face of said semiconductor layer is tapered claim 1 , being adjacent to the outer peripheral portion of said supporting portion with at least an insulator layer being sandwiched therebetween.4. The light-emitting element chip according to claim 1 , wherein said supporting portion is integrally formed by a dry or wet deposition method claim 1 , being made of a metal or an alloy.5. The light-emitting ...

III NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided is a III nitride semiconductor device higher heat dissipation performance, and a method of manufacturing a III nitride semiconductor device which makes it possible to fabricate such a III nitride semiconductor device at higher yield. In a method of a III nitride semiconductor device, a semiconductor structure obtained by sequentially stacking an n-layer, an active layer, and a p-layer is formed on a growth substrate; a support body including a first support electrically connected to an n-layer to serve as an n-side electrode, a second support electrically connected to a p-layer to serve as a p-side electrode, and structures made of an insulator for insulation between first and second supports is formed on the p-layer side of the semiconductor structure; and the growth substrate is separated using a lift-off process. The first support and the second support are grown by plating. 1. A method of manufacturing a III nitride semiconductor device , comprising:a first step of forming semiconductor structures obtained by sequentially stacking a first conductivity type III nitride semiconductor layer, an active layer, and a second conductivity type III nitride semiconductor layer on a growth substrate;a second step of partly exposing the first conductivity type III nitride semiconductor layer by partly removing the second conductivity-type III nitride semiconductor layer and the active layer;a third step of forming first contact layers on exposed portions of the first conductivity type III nitride semiconductor layer and forming second contact layers on exposed portions of the second conductivity type III nitride semiconductor layer;a fourth step of forming an insulating layer on the semiconductor structures, the first contact layers, and the second contact layers that are exposed, with part of the first contact layers and part of the second contact layers being exposed;a fifth step of forming a first structure made of an insulator on part of the insulating layer ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The method of manufacturing a semiconductor device according to the present invention includes: a step of forming a semiconductor laminate on a growth substrate with a lift-off layer therebetween; a step of providing grooves in a grid pattern in the semiconductor laminate, thereby forming a plurality of semiconductor structures each having a nearly quadrangular transverse cross-sectional shape; a step of forming a conductive support body; and a step of removing the lift-off layer using a chemical lift-off process, in which step, in supplying an etchant to the grooves via through-holes provided in a portion above the grooves, the lift-off layer is etched from only one side surface of each semiconductor structure. 1. A method of manufacturing a semiconductor device , comprising:a first step of forming a semiconductor layer on a growth substrate with a lift-off layer therebetween;a second step of partially removing the semiconductor layer to form grooves in a grid pattern such that the growth substrate is partially exposed at the bottom of the grooves, thereby forming a plurality of semiconductor structures each having a nearly quadrangular transverse cross-sectional shape;a third step of forming a conductive support body for integrally supporting the plurality of the semiconductor structures; anda fourth step of removing the lift-off layer using a chemical lift-off process;a fifth step of dividing the conductive support body between the semiconductor structures thereby singulating a plurality of semiconductor devices having the respective semiconductor structures supported by the conductive support body,wherein in the fourth step, in supplying an etchant to the grooves via through-holes in the conductive support body, which through-holes provided in a portion above the grooves, the lift-off layer is etched from only one of the side surfaces of each of the semiconductor structures.2. The method of manufacturing a semiconductor device according to claim 1 , wherein ...

VERTICALLY STRUCTURED GROUP III NITRIDE SEMICONDUCTOR LED CHIP AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a vertically structured Group III nitride semiconductor LED chip includes a first step of forming a light emitting structure laminate; a second step of forming a plurality of separate light emitting structures by partially removing the light emitting structure laminate to partially expose the growth substrate; a third step of forming a conductive support, which conductive support integrally supporting the light emitting structures; a fourth step of separating the growth substrate by removing the lift-off layer; and a fifth step of dividing the conductive support between the light emitting structures thereby singulating a plurality of LED chips each having the light emitting structure. A first through-hole is formed to open in a central region of each of the light emitting structures such that at least the lift-off layer is exposed, and an etchant is supplied from the first through-hole in the fourth step. 1. A method for manufacturing a vertically structured Group III nitride semiconductor LED chip , comprising:a first step of forming a light emitting structure laminate by sequentially stacking a first conductivity type Group III nitride semiconductor layer, a light emitting layer, and a second conductivity type Group III nitride semiconductor layer on a growth substrate with a lift-off layer provided therebetween, the second conductivity type being different from the first conductivity;a second step of forming a plurality of separate light emitting structures by partially removing the light emitting structure laminate to partially expose the growth substrate;a third step of forming a conductive support having a lower electrode, which conductive support integrally supporting the plurality of the light emitting structures;a fourth step of separating the growth substrate from the plurality of the light emitting structures by removing the lift-off layer using a chemical lift-off process; anda fifth step of dividing the conductive support ...

III NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided is a high quality III nitride semiconductor device in which, not only X-shaped cracks extending from the vicinity of the corners of semiconductor structures to the center portion thereof, but also crack spots at the center portion can be prevented from being formed and can provide a method of efficiently manufacturing the III nitride semiconductor device. The III nitride semiconductor device of the present invention includes a support and two semiconductor structures having a nearly quadrangular transverse cross-sectional shape that are provided on the support. The two semiconductor structures are situated such that one side surface of one of the two semiconductor structures is placed to face one side surface of the other of them. The support covers the other three side surfaces and of the four sides of the semiconductor structures. 1. A method of manufacturing a III nitride semiconductor device , comprising the steps of:a step of forming a semiconductor laminate obtained by sequentially stacking a first conductivity type III nitride semiconductor layer, an active layer, and a second conductivity type III nitride semiconductor layer on a growth substrate with a lift-off layer provided therebetween;a step of partly removing the semiconductor laminate to form a plurality of grooves in a grid pattern such that the growth substrate is partly exposed at the bottom of the grooves, thereby forming a plurality of semiconductor structures having a nearly quadrangular transverse cross-sectional shape;a step of filling up alternate lines of the plurality of grooves in one direction with a filler,a step of forming a support for integrally supporting the plurality of semiconductor structures by plating;a step of forming through-holes in the support, the through-holes communicating with the filler;a step of forming gaps by removing the filler,a step of supplying an etchant to the gaps from the through-holes, thereby etching the lift-off layer from only one side of each ...

Semiconductor device and process for production thereof

Semiconductor device and process for production thereof

The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are sequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

Improved structure of rear portion of automotive vehicle body

A rear body (1) of an automotive vehicle includes three parts: a front body structural element (2), an intermediate body structural element (3), and a rear body structural element (4) which are castings, joined together. The rigidity of the rear body (1) increases from the rear body structural element (4) to the front body structural element (2), thereby facilitating the ease of collapse of the rear body structural element in response to input of a rear-end collision impact, for the purpose of ensuring a protective structural area at a front side of the rear body.

III nitride semiconductor device and method of manufacturing the same

Provided is a high quality III nitride semiconductor device in which, not only X-shaped cracks extending from the vicinity of the corners of semiconductor structures to the center portion thereof, but also crack spots at the center portion can be prevented from being formed and can provide a method of efficiently manufacturing the III nitride semiconductor device. The III nitride semiconductor device of the present invention includes a support and two semiconductor structures having a nearly quadrangular transverse cross-sectional shape that are provided on the support. The two semiconductor structures are situated such that one side surface of one of the two semiconductor structures is placed to face one side surface of the other of them. The support covers the other three side surfaces and of the four sides of the semiconductor structures.

Notched compound semiconductor wafer

There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10-1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0-10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00-1] when a notch is formed in a direction of [0-10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0-10] when a notch is formed in a direction of [00-1].

A group III nitride semiconductor semiconductor substrate, a group III nitride semiconductor device, and a group III nitride semiconductor device, and a group III nitride semiconductor self-supporting substrate, and a method of manufacturing the same

GaAs INGOT AND METHOD OF PRODUCING GaAs INGOT, AND GaAs WAFER

Provided is a GaAs ingot with which a GaAs wafer having a carrier concentration of 5.5×10 17 cm −3 or less and low dislocation density with an average dislocation density of 500/cm 2 or less can be obtained by adding a small amount of In with Si. A seed side end and a center portion of a straight body part of the GaAs ingot each have a silicon concentration of 2.0×10 17 cm −3 or more and less than 1.5×10 18 cm −3 , an indium concentration of 1.0×10 17 cm −3 or more and less than 6.5×10 18 cm −3 , a carrier concentration of 5.5×10 17 cm −3 or less, and an average dislocation density of 500/cm 2 or less.

Vertical group iii nitride semiconductor light-emitting element and production method therefor

Notched compound semiconductor wafer

GaAs WAFER AND METHOD OF PRODUCING GaAs INGOT

Provided is a GaAs wafer that can suitably be used to produce LiDAR sensors in particular and a method of producing a GaAs ingot that can be used to obtain such a GaAs wafer. The GaAs wafer has a silicon concentration of 5.0×1017 cm−3 or more and less than 3.5×1018 cm−3, an indium concentration of 3.0×1017 cm−3 or more and less than 3.0×1019 cm−3, and a boron concentration of 1.0×1018 cm−3 or more. The average dislocation density of the GaAs wafer is 1500/cm2 or less.

Ｉｉｉ族窒化物半導体及びｉｉｉ族窒化物半導体成長用基板

【課題】III族窒化物半導体の転位密度の更なる低減と同時に、自立基板製造時および半導体素子製造時のケミカルリフトオフ所要時間の大幅な短縮が可能なIII族窒化物半導体を提供する。 【解決手段】基板上にＡｌＮ単結晶層またはＡｌを含むIII族窒化物単結晶層を０．００５μm以上１０μm以下の厚みで形成したＡｌＮテンプレート基板又はサファイア基板を窒化処理したＡｌＮテンプレート基板、もしくはＡｌＮ単結晶基板上に、ストライプ状の開口部を有するパターンマスクと、前記開口部に形成された金属窒化物層と、前記金属窒化物層上に形成されたIII族窒化物半導体層を有し、前記III族窒化物半導体層は前記金属窒化物層を核としたＥＬＯ成長による連続膜である、III族窒化物半導体。 【選択図】図１

Ｉｉｉ族窒化物半導体縦型構造ｌｅｄチップ

【課題】発光構造部にクラックの少ない、高品質の縦型ＬＥＤチップを提供する。 【解決手段】下部電極を兼ねる導電性サポート部と、該サポート部上に設けられた接続層と、該接続層上に設けられたオーミック電極層と、第２伝導型III族窒化物半導体層、該第２伝導型III族窒化物半導体層の上に設けられた発光層、および、該発光層の上に設けられた前記第２伝導型とは異なる伝導型の第１伝導型III族窒化物半導体層を有する発光構造部とを一対の電極で挟んだ構造を有し、前記発光構造部の平面が、円またはコーナーに丸みを有する４ｎ角形状(ｎは正の整数とする。)であり、かつ前記サポート部の平面は、前記発光構造部の平面よりも大きくかつ異なる形状を有することを特徴とする。 【選択図】図５

Ｉｉｉ族窒化物半導体縦型構造ｌｅｄチップの製造方法

【課題】発光構造部にクラックの少ない、高品質の縦型ＬＥＤチップを提供する。 【解決手段】下部電極を兼ねる導電性サポート部と、該サポート部上に設けられた接続層と、該接続層上に設けられたオーミック電極層と、第２伝導型III族窒化物半導体層、該第２伝導型III族窒化物半導体層の上に設けられた発光層、および、該発光層の上に設けられた前記第２伝導型とは異なる伝導型の第１伝導型III族窒化物半導体層を有する発光構造部とを一対の電極で挟んだ構造を有し、前記発光構造部の平面が、円またはコーナーに丸みを有する４ｎ角形状(ｎは正の整数とする。)であり、かつ前記サポート部の平面は、前記発光構造部の平面よりも大きくかつ異なる形状を有することを特徴とする。 【選択図】図５

化合物半導体単結晶の製造装置及び製造方法，化合物半導体単結晶

(57)【要約】 【課題】 温度をより正確に把握でき，また，温度を均 一に制御しやすい化合物半導体単結晶の製造装置と方法 を提供する。 【解決手段】 るつぼ状容器１１の周囲に配置したヒー タ１３により加熱し，化合物半導体単結晶を製造するに 際し，るつぼ状容器１１とヒータ１３との間に，熱を伝 導させる均熱部材１３を設けることにより，るつぼ状容 器１１への熱伝導を制御する。均熱部材１２を回転させ ても良い。均熱部材１３によって発熱ムラを均一にし， るつぼ状容器１１の周囲を均等に加熱できるようにな る。また，種付け部分など温度を正確に把握して温度制 御できるようになる。

Lighting element

半導体インゴットのキャリア濃度評価方法

【課題】半導体インゴットのキャリア濃度を非破壊で精度良く評価することができる半導体インゴットのキャリア濃度評価方法を提供する。 【解決手段】単結晶インゴットの結晶成長方位に応じてファセット成長が生じない部分及びファセット成長領域を取り除いた部分のいずれかである単結晶インゴット側面の結晶学的な面を特定する第１過程と、特定した面に基づく照射面に励起光を照射する第２過程と、励起光によるフォトルミネッセンススペクトルに基づいてキャリア濃度を評価する第３過程とからなる。ＧａＡｓでは５×１０ １６ ／ｃｍ ３ 〜３×１０ １９ ／ｃｍ ３ の範囲を非破壊な状態で、ホール測定と同等な精度で評価可能である。 【選択図】 図３

Gaas ingot, method for manufacturing gaas ingot, and gaas wafer

車両用冷却装置

(57)【要約】 【課題】 走行時の冷却性能を向上させると共に、アイ ドル時は熱気吹き返しによる空気の温度を低下させて、 冷却性能を向上させる車両用冷却装置を提供すること。 【解決手段】 エアコン用のコンデンサ２とエンジン冷 却水冷却用のラジエータ１が車両前部側から後方に向け て順に配置され、冷却空気が車両前方よりエンジンルー ム内に導入される車両用冷却装置において、これらのコ ンデンサ２、ラジエータ１の車両前方側に、冷媒が封入 され、自己内のみに冷媒経路を有し、他の冷却装置や機 関とは冷媒を共有しない、第三の熱交換器７を配設す る。

樹脂製フェンダーのスライド構造

(57)【要約】 （修正有） 【課題】 樹脂フェンダーの気温変化による伸縮を吸収 し、樹脂フェンダーの面外剛性を高くすることができ、 さらには取り付けやすい樹脂製フェンダーのスライド構 造を提供する。 【解決手段】 熱可塑性樹脂で形成されたフェンダー１ を、軽合金などの鋳物によって形成された車体パネル２ の外側に取り付ける構造にあって、長手方向に配された フランジの取り付け部４ａ，４ｂは長穴による取り付け 等のスライド機構とし、長手方向の稜線７ａ，７ｂ，７ ｃおよびキャラクターライン８の裏側には、薄肉化され た脆弱部を有し、該脆弱部の少なくとも一方の側近に は、肉厚化された補強リブを有し、該補強リブは前記車 体パネルから突出した尖状突起と係合する構成とする。

基板の接合方法および基板接合装置

【課題】１組の被接合基板から製造できる電子デバイスの歩留まりが高い、基板の接合方法および基板接合装置を提供する。 【解決手段】電子デバイスを備える成長用基板と支持基板との組基板を、上部治具および下部治具を用いて押圧し、接合基板を得る接合方法であって、同径を有する前記成長用基板と支持基板との１組以上の基板を、前記下部治具に設けられた、前記組基板の全てを内部に直列的に収納可能な円筒形状の凹部に装填する工程と、前記上部治具および下部治具を用いて、前記直列的に収納された組基板を押圧し、前記成長用基板と支持基板とを接合させて接合基板を得る工程とを、有することを特徴とする基板の接合方法を提供する。 【選択図】図１

Ultraviolet light receiving device

Provided is an ultraviolet light receiving device having photosensitivity effective to target wavelengths in the ultraviolet region. A Schottky junction ultraviolet light receiving device has the photosensitivity peak wavelength in an ultraviolet region of 230 nm or more and 320 nm or less, and exhibits a rejection ratio of 10 5 or more, the rejection ratio being the ratio of the responsivity Rp to the peak photosensitivity wavelength to the average of the responsivity Rv to a visible region of 400 nm or more and 680 nm or less (Rp/Rv).

半導体発光素子およびその製造方法

【課題】第２接合層の露出面における絶縁性保護膜との密着性を向上させることにより、半導体発光素子の耐久性および製造歩留まりを向上させる。 【解決手段】成長基板上に、ｐ側電極層および第１接合層を有する独立した発光構造体を形成する工程と、支持部材の表面全体に、Ｐｔ基合金バリア層ならびにＡｕおよびＳｎを含有する第２接合層を形成する工程と、上記第１接合層と上記第２接合層とを熱接合する接合工程と、上記成長基板を、上記発光構造体からリフトオフにより剥離する剥離工程と、上記支持部材の表面の、上記第１接合層が接合されていない非接合領域における上記第２接合層のＡｕ含有層をエッチングにより除去する第１除去工程とを具えることを特徴とする。 【選択図】図４

半導体の特性評価装置

【課題】口径の異なるインゴットに対しても複雑な光学系の調整が不要で、インゴットのフォトルミネッセンススペクトルの分布を求め得る半導体の特性評価装置を提供する。 【解決手段】インゴット１の半導体結晶を保持するインゴット保持機構６と、ウェハ９の半導体結晶を保持するウェハ保持機構９とを備え、インゴット保持機構６とウェハ保持機構９とが交換可能に設けられる。インゴット１の口径が異なっても半導体結晶への励起光としてのレーザ光の照射及びフォトルミネッセンス光ＰＬ１の集光を行う光学系の調整をしないでインゴット１を保持できる。半導体インゴットやウェハのキャリア濃度やその一次元及び二次元の分布測定を、容易に、高速で、かつ、高精度で行うことができる。 【選択図】図１

Gaas wafer, gaas wafer group, and method for producing gaas ingot

Provided is a GaAs wafer having suppressed carrier concentration and low dislocation density, as well as a large proportion of the area of a region with zero dislocation density to the GaAs wafer surface. The GaAs wafer has a silicon concentration of 1.0 × 10¹⁷ cm^-3 or more and less than 1.1 × 10¹⁸ cm^-3; an indium concentration of 3.0 × 10¹⁸ cm^-3 or more and less than 3.0 × 10¹⁹ cm^-3; a boron concentration of 2.5 × 10¹⁸ cm^-3 or more; a carrier concentration of 1.0 × 10¹⁶ cm^-3 or more and 4.0 × 10¹⁷ cm^-3 or less; and a proportion of the area of a region with zero dislocation density to the wafer surface of 91.0% or more.

金属被膜Ｓｉ基板ならびに接合型発光素子およびその製造方法

【課題】素子製造過程において高温の熱処理を施した場合であっても、Ｓｉ基板上に形成されたＡｕ層のＡｕがＳｉ基板に拡散することのない金属被膜Ｓｉ基板、ならびに、この金属被膜Si基板を用いた接合型発光素子およびその製造方法を提供する。 【解決手段】Ｓｉ基板と、前記Ｓｉ基板上の、接着層およびＰｔ層が順に形成された初期積層体と、前記初期積層体上の、Ａｕを含む第１金属層とを有する金属被膜Ｓｉ基板において、上記初期積層体と上記Ａｕを含む第１金属層との間に、ＴａＮ層およびＷ層からなる拡散防止積層体を介挿させ、前記ＴａＮ層の厚さが３０ｎｍ超えで、かつ前記Ｗ層の厚さが２００ｎｍ未満であることを特徴とする。 【選択図】図１

Vertically structured group III nitride semiconductor LED chip and method for manufacturing the same

A method for manufacturing a vertically structured Group III nitride semiconductor LED chip includes a first step of forming a light emitting structure laminate; a second step of forming a plurality of separate light emitting structures by partially removing the light emitting structure laminate to partially expose the growth substrate; a third step of forming a conductive support, which conductive support integrally supporting the light emitting structures; a fourth step of separating the growth substrate by removing the lift-off layer; and a fifth step of dividing the conductive support between the light emitting structures thereby singulating a plurality of LED chips each having the light emitting structure. A first through-hole is formed to open in a central region of each of the light emitting structures such that at least the lift-off layer is exposed, and an etchant is supplied from the first through-hole in the fourth step.