Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 39. Отображено 31.
18-04-2023 дата публикации

Amorphous metal strip and method for producing an amorphous metal strip

Номер: US0011629413B2
Автор: Christian Polak, Thomas Strache
Принадлежит: VACUUMSCHMELZE GMBH & CO. KG, Vacuumschmelze GmbH & Co. KG

A method for the production of a metal strip is provided. The method includes providing an amorphous metal strip having a first main surface and a second, opposing main surface. The first and/or the second main surface are treated with a wet-chemical etching process and/or a photochemical etching process.

Подробнее
Номер записи: 1
05-01-2017 дата публикации

De-coupling capacitance placement

Номер: US20170004239A1
Автор: Harry Barowski, Joachim Keinert, Sourav Saha, Thomas Strach
Принадлежит: International Business Machines Corp

A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Подробнее
Номер записи: 2
05-01-2017 дата публикации

De-coupling capacitance placement

Номер: US20170004248A1
Автор: Harry Barowski, Joachim Keinert, Sourav Saha, Thomas Strach
Принадлежит: International Business Machines Corp

A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Подробнее
Номер записи: 3
25-01-2018 дата публикации

Discrete electronic device embedded in chip module

Номер: US20180027659A1
Автор: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
Принадлежит: International Business Machines Corp

The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

Подробнее
Номер записи: 4
30-01-2020 дата публикации

DISTRIBUTED ON CHIP NETWORK TO MITIGATE VOLTAGE DROOPS

Номер: US20200033927A1
Автор: Lobo Preetham M., Strach Thomas, Webel Tobias
Принадлежит:

A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit. 1. A semiconductor circuit comprising:a first subcircuit;at least one second subcircuit; andpower management circuitry, wherein the power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the at least one second subcircuit.2. The semiconductor circuit according to claim 1 , wherein the first subcircuit comprises a pipeline of a processing unit and wherein the power management circuitry is operable for estimating the power supply current of the first subcircuit based on activity indicators related to at least one part of the pipeline.3. The semiconductor circuit according to claim 2 , wherein the at least one part of the pipeline includes at least one of an arithmetic unit claim 2 , a load/store unit claim 2 , a cache access unit claim 2 , an instruction sequencing unit and an instruction decode unit.4. The semiconductor circuit according to claim 1 , wherein the power management circuitry is operable for estimating the cross current based on current increments calculated from the metric.5. The semiconductor circuit according to claim 1 , wherein estimating the metric is further based on at least one external supply current.6. The semiconductor circuit according to claim 1 , wherein the power management circuitry comprises a grid of power management units claim 1 , and wherein a power management unit is assigned to a subcircuit selected from the group consisting of: the first ...

Подробнее
Номер записи: 5
18-02-2021 дата публикации

Amorphous metal strip and method for producing an amorphous metal strip

Номер: US20210047738A1
Автор: Christian Polak, Thomas STRACHE
Принадлежит: Vacuumschmelze GmbH and Co KG

A method for the production of a metal strip is provided. The method includes providing an amorphous metal strip having a first main surface and a second, opposing main surface. The first and/or the second main surface are treated with a wet-chemical etching process and/or a photochemical etching process.

Подробнее
Номер записи: 6
22-02-2018 дата публикации

Increasing the resolution of on-chip measurement circuits

Номер: US20180052200A1
Автор: Christos VEZYRTZIS, Phillip J. Restle, Robert L. Franch, Scott F. Warnock, Thomas Strach
Принадлежит: Computer Task Group Inc, International Business Machines Corp

A method for increasing a resolution of an on-chip measurement circuit is provided. The method includes propagating a first signal through the on-chip measurement circuit to generate a first output. The method also includes propagating a second signal through the on-chip measurement circuit to generate a second output. The second signal includes a delay. The method also includes reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit. The resolution of the on-chip measurement circuit increases in correspondence with a fineness of a step of the delay.

Подробнее
Номер записи: 7
05-06-2014 дата публикации

Reducing power grid noise in a processor while minimizing performance loss

Номер: US20140157033A1
Автор: Huajun Wen, Lee E. Eisen, Michael S. Floyd, Thomas Strach, Tingdong Zhou
Принадлежит: International Business Machines Corp

In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Подробнее
Номер записи: 8
05-06-2014 дата публикации

REDUCING POWER GRID NOISE IN A PROCESSOR WHILE MINIMIZING PERFORMANCE LOSS

Номер: US20140157277A1
Автор: Eisen Lee E., Floyd Michael S., Strach Thomas, Wen Huajun, Zhou Tingdong
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations. 1. A method for managing a processor , comprising:monitoring, by a processor, for an increase in logical operation activity from a low level to a high level during a sampling window across a plurality of cores sharing a common supply rail of the processor;responsive to the processor detecting the increase in logical operation activity from the low level to the high level during the sampling window, limiting, by the processor, the logical operations executed on the plurality of cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level; andresponsive to the lower activity period ending, gradually decreasing, by the processor, the limit on the logical operations executed on the plurality of cores to resume normal operations.2. The method of claim 1 , wherein monitoring claim 1 , by a processor claim 1 , for an increase in logical operation activity from a low level to a high level during a sampling window across a plurality of cores sharing a common supply rail of the processor claim 1 , wherein the processor comprises at least one decoupling capacitor ...

Подробнее
Номер записи: 9
29-03-2018 дата публикации

DISTRIBUTED ON CHIP NETWORK TO MITIGATE VOLTAGE DROOPS

Номер: US20180088650A1
Автор: Lobo Preetham M., Strach Thomas, Webel Tobias
Принадлежит:

A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit. 1. A semiconductor circuit comprising:a first subcircuit;at least one second subcircuit; andpower management circuitry, wherein the power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the at least one second subcircuit.2. The semiconductor circuit according to claim 1 , wherein the first subcircuit comprises a pipeline of a processing unit and wherein the power management circuitry is operable for estimating the power supply current of the first subcircuit based on activity indicators related to at least one part of the pipeline.3. The semiconductor circuit according to claim 2 , wherein the at least one part of the pipeline includes at least one of an arithmetic unit claim 2 , a load/store unit claim 2 , a cache access unit claim 2 , an instruction sequencing unit and an instruction decode unit.4. The semiconductor circuit according to claim 1 , wherein the power management circuitry is operable for estimating the cross current based on current increments calculated from the metric.5. The semiconductor circuit according to claim 1 , wherein estimating the metric is further based on at least one external supply current.6. The semiconductor circuit according to claim 1 , wherein the power management circuitry comprises a grid of power management units claim 1 , and wherein a power management unit is assigned to a subcircuit selected from the group consisting of: the first ...

Подробнее
Номер записи: 10
19-04-2018 дата публикации

Layout effect characterization for integrated circuits

Номер: US20180107771A1
Автор: Antje Mueller, Jens Kuenzer, Martin Eckert, Otto A. Torreiter, Thomas Gentner, Thomas Strach
Принадлежит: International Business Machines Corp

A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.

Подробнее
Номер записи: 11
27-04-2017 дата публикации

EMBEDDING A DISCRETE ELECTRICAL DEVICE IN A PRINTED CIRCUIT BOARD

Номер: US20170118842A1
Автор: Chamberlin Bruce J., HUBER Andreas, Huels Harald, Strach Thomas, WINKEL Thomas-Michael
Принадлежит:

Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section. 119-. (canceled)20. A printed circuit board with a discrete electrical device embedded therein , the printed circuit board comprising:a horizontal top surface and a horizontal bottom surface;a plurality of horizontal core sections vertically arranged above each other between the horizontal top and bottom surfaces, each horizontal core section comprising a lower and an upper horizontal electrically conductive layer, and a horizontal electrically non-conductive core layer arranged between the lower and the upper electrically conductive layers;the discrete electrical device being disposed in a vertical via provided in the printed circuit board, the vertical via having the form of a blind hole extending from one of the horizontal top or bottom surfaces of the printed circuit board to an electrically conductive structure in a first layer, the first layer being one of the layers of a first core section of the plurality of the horizontal core sections;the discrete electrical device extending from the electrically conductive structure in the first layer along the ...

Подробнее
Номер записи: 12
27-04-2017 дата публикации

EMBEDDING A DISCRETE ELECTRICAL DEVICE IN A PRINTED CIRCUIT BOARD

Номер: US20170118844A1
Автор: Chamberlin Bruce J., HUBER Andreas, Huels Harald, Strach Thomas, WINKEL Thomas-Michael
Принадлежит:

Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section. 1. A method for embedding a discrete electrical device in a printed circuit board , the method comprising:providing a vertical via in the form of a blind hole from a horizontal surface of the printed circuit board to an electrically conductive structure in a first layer, the first layer being one layer of a first horizontal core section of a plurality of horizontal core sections vertically arranged above each other, each core section comprising a lower and an upper horizontal electrically conductive layer, and a horizontal electrically non-conductive core layer arranged between the lower and the upper electrically conductive layers;inserting the discrete electrical device into the via, the discrete electrical device extending from the electrically conductive structure in the first layer along the longitudinal axis of the vertical via within at least two of the horizontal core sections;establishing a first electrical connection between a first electrical contact of the discrete electrical device and the electrically conductive structure in the first layer; ...

Подробнее
Номер записи: 13
25-06-2020 дата публикации

PREDICTIVE ON-CHIP VOLTAGE SIMULATION TO DETECT NEAR-FUTURE UNDER VOLTAGE CONDITIONS

Номер: US20200201407A1
Автор: Lobo Preetham M., Strach Thomas, Webel Tobias
Принадлежит:

Embodiments of the present disclosure relate to detecting undervoltage conditions at a subcircuit. A power supply current of a first subcircuit is determined over a first number of previous clock cycles. A cross current flowing between the first subcircuit and a second subcircuit is determined over the first number of previous clock cycles. An estimated momentary supply voltage present at the first subcircuit is then determined based on the power supply current of the first subcircuit over the first number of previous clock cycles and the cross current flowing between the first subcircuit and the second subcircuit over the first number of previous clock cycles. 1. A semiconductor circuit comprising:a first subcircuit;a second subcircuit; anda power management circuitry, wherein the power management circuitry is configured to determine an estimated momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit over a first number of previous clock cycles and a cross current flowing between the first subcircuit and the a second subcircuit over the first number of previous clock cycles.2. The semiconductor circuit of claim 1 , wherein a maximum value of the power supply current over the first number of previous clock cycles and a maximum value of cross current over the first number of previous clock cycles are considered to determine the estimated momentary supply voltage.3. The semiconductor circuit of claim 2 , wherein the first number of previous clock cycles is eight.4. The semiconductor circuit of claim 1 , wherein an average value of the power supply current over the first number of previous clock cycles and an average value of the cross current over the first number of previous clock cycles are considered to determine the estimated momentary supply voltage.5. The semiconductor circuit of claim 1 , wherein the power management circuitry is further configured to estimate a momentary supply voltage present at the ...

Подробнее
Номер записи: 14
25-06-2020 дата публикации

FINE RESOLUTION ON-CHIP VOLTAGE SIMULATION TO PREVENT UNDER VOLTAGE CONDITIONS

Номер: US20200201413A1
Автор: Lobo Preetham M., Strach Thomas, Webel Tobias
Принадлежит:

Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs. 1. A semiconductor circuit comprising:a first subcircuit including a measurement input configured to receive a measured voltage value describing a measured supply voltage at the first subcircuit, wherein the measured voltage value has a first resolution;a simulator input configured to receive a selected metric indicative of a supply voltage present at the first subcircuit, wherein the selected metric has a second resolution, wherein the second resolution is higher than the first resolution; anda calibration circuit configured to calibrate the selected metric to obtain a calibrated metric when a transition of the measured voltage value occurs.2. The semiconductor circuit of claim 1 , wherein the calibration circuit comprises a sampling register claim 1 , wherein the calibration circuit is configured to register the selected metric in the sampling register when the transition of the measured voltage value occurs.3. The semiconductor circuit of claim 1 , wherein the transition of the measured voltage value corresponds to a change of the measured voltage value from a predefined value (N) to a value (N−1) less than the predefined value (N).4. The semiconductor circuit of claim 1 , wherein the first subcircuit further comprises a throttle signal generator configured to generate a subcircuit throttle signal to throttle the first subcircuit based on the calibrated ...

Подробнее
Номер записи: 15
23-10-2014 дата публикации

POWER NOISE HISTOGRAM OF A COMPUTER SYSTEM

Номер: US20140316725A1
Автор: ECKERT Martin, HARRER HUBERT, Strach Thomas
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method is provided for determining a power noise histogram of a computer system. The computer system includes a skitter circuit with multiple skitter bins, each skitter bin of the multiple skitter bins being connected to a signal line at one or more clock cycles. The method includes: connecting each skitter bin to an individual counter circuit; and incrementing a counter when the respective skitter bin is enabled. 1. A method comprising: connecting each skitter bin to an individual counter circuit; and', 'incrementing a counter when the respective skitter bin is enabled., 'determining a power noise histogram of a computer system, said computer system comprising a skitter circuit with multiple skitter bins, said skitter bins each being connected to a signal line at one or more clock cycles, the determining comprising2. The method of claim 1 , further comprising:calibrating the skitter bins by determining a voltage corresponding to each skitter bin;defining a critical voltage limit;measuring a voltage distribution during computer system operation for a range of skitter bins;extrapolating the voltage distribution beyond the boundaries of the range of skitter bins; andcalculating a probability of the computer system from the extrapolated voltage distribution to reach the predefined voltage limit.3. The method of claim 2 , further comprising sampling the voltage distribution with an on-chip skitter counter circuit.4. The method of claim 2 , further comprising predicting a probability for the computer system to fail based on the extrapolated voltage distribution.5. The method of claim 4 , further comprising calculating a correlation between the critical voltage limit and the probability for the computer system to fail.6. The method of claim 1 , further comprising determining a voltage corresponding to each skitter bin by measuring a distribution of counts for the multiple skitter bins of the skitter circuit for a signal with a defined voltage.7. The method of claim 1 , ...

Подробнее
Номер записи: 16
09-08-2018 дата публикации

Discrete electronic device embedded in chip module

Номер: US20180228028A1
Автор: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
Принадлежит: International Business Machines Corp

The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

Подробнее
Номер записи: 17
26-09-2019 дата публикации

Discrete electronic device embedded in chip module

Номер: US20190295938A1
Автор: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
Принадлежит: International Business Machines Corp

The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

Подробнее
Номер записи: 18
28-07-2020 дата публикации

Distributed on chip network to mitigate voltage droops

Номер: US10725517B2
Автор: Preetham M. Lobo, Thomas Strach, Tobias Webel
Принадлежит: International Business Machines Corp

A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.

Подробнее
Номер записи: 19
21-02-2023 дата публикации

Fine resolution on-chip voltage simulation to prevent under voltage conditions

Номер: US11586267B2
Автор: Preetham M. Lobo, Thomas Strach, Tobias Webel
Принадлежит: International Business Machines Corp

Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.

Подробнее
Номер записи: 20
16-07-2019 дата публикации

Discrete electronic device embedded in chip module

Номер: US10354946B2
Автор: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
Принадлежит: International Business Machines Corp

The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

Подробнее
Номер записи: 21
22-05-2018 дата публикации

Discrete electronic device embedded in chip module

Номер: US9980385B2
Автор: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
Принадлежит: International Business Machines Corp

The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

Подробнее
Номер записи: 22
29-09-2015 дата публикации

Reducing power grid noise in a processor while minimizing performance loss

Номер: US9146772B2
Автор: Huajun Wen, Lee E. Eisen, Michael S. Floyd, Thomas Strach, Tingdong Zhou
Принадлежит: International Business Machines Corp

In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

Подробнее
Номер записи: 23
23-10-2014 дата публикации

Histogramm des leistungsrauschens eines computersystems

Номер: DE102014101114A1
Автор: Hubert Harrer, Martin Eckert, Thomas Strach
Принадлежит: International Business Machines Corp

Die Erfindung bezieht sich auf ein Verfahren zum Festlegen eines Histogramms des Leistungsrauschens eines Computersystems, wobei das Computersystem eine Skitter-Schaltung (40) mit mehreren Skitter-Bins (48) aufweist, wobei der Skitter-Bin (48) jeweils mit einer Signalleitung (49) bei einem oder mehreren Taktzyklen verbunden ist, wobei das Verfahren aufweist: (i) Verbinden jedes Skitter-Bin (48) mit einer einzelnen Skitter-Schaltung (64); (ii) Erhöhen eines Zählers (64), wenn der entsprechende Skitter-Bin (48) freigegeben ist.

Подробнее
Номер записи: 24
27-02-2018 дата публикации

Layout effect characterization for integrated circuits

Номер: US09904748B1
Автор: Antje Mueller, Jens Kuenzer, Martin Eckert, Otto A. Torreiter, Thomas Gentner, Thomas Strach
Принадлежит: International Business Machines Corp

A layout effect characterization circuit includes a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.

Подробнее
Номер записи: 25
05-12-2017 дата публикации

Embedding a discrete electrical device in a printed circuit board

Номер: US09839131B2
Автор: Andreas Huber, Bruce J. Chamberlin, Harald Huels, Thomas Strach, Thomas-Michael Winkel
Принадлежит: International Business Machines Corp

Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

Подробнее
Номер записи: 26
31-10-2017 дата публикации

Power noise histogram of a computer system

Номер: US09804231B2
Автор: Hubert Harrer, Martin Eckert, Thomas Strach
Принадлежит: Globalfoundries Inc

A method is provided for determining a power noise histogram of a computer system. The computer system includes a skitter circuit with multiple skitter bins, each skitter bin of the multiple skitter bins being connected to a signal line at one or more clock cycles. The method includes: connecting each skitter bin to an individual counter circuit; and incrementing a counter when the respective skitter bin is enabled.

Подробнее
Номер записи: 27
22-08-2017 дата публикации

Layout effect characterization for integrated circuits

Номер: US09740813B1
Автор: Antje Mueller, Jens Kuenzer, Martin Eckert, Otto A. Torreiter, Thomas Gentner, Thomas Strach
Принадлежит: International Business Machines Corp

An aspect includes forming a layout effect characterization circuit by incorporating a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain in an integrated circuit layout. A low pass filter is coupled to an output of the inverting device chains to produce a filtered output. An output capture circuit is coupled to the filtered output to enable a comparison of a captured filtered output of the one or more chains having the different inverting device arrangement to a captured filtered output of the reference chain.

Подробнее
Номер записи: 28
20-06-2017 дата публикации

De-coupling capacitance placement

Номер: US09684759B2
Автор: Harry Barowski, Joachim Keinert, Sourav Saha, Thomas Strach
Принадлежит: International Business Machines Corp

A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Подробнее
Номер записи: 29
13-06-2017 дата публикации

De-coupling capacitance placement

Номер: US09679099B2
Автор: Harry Barowski, Joachim Keinert, Sourav Saha, Thomas Strach
Принадлежит: International Business Machines Corp

A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

Подробнее
Номер записи: 30
06-06-2017 дата публикации

Discrete electronic device embedded in chip module

Номер: US09673179B1
Автор: Andreas Huber, Harald Huels, Stefano S. Oggioni, Thomas Strach, Thomas-Michael Winkel
Принадлежит: International Business Machines Corp

The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

Подробнее
Номер записи: 31