VERTICAL BIT VECTOR SHIFT IN MEMORY

Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector. 120-. (canceled)21. A method for shifting data , comprising: performing shift operations, wherein each of the shift operations shift elements of the bit vectors by a number of positions indicated by a vertical shift bit vector; and', 'wherein each bit vector is stored in memory cells coupled to a sense line and a plurality of access lines; and each bit vector is separated by at least one sense line from a neighboring bit vector., 'shifting elements of bit vectors stored in a memory array by22. The method claim 21 , including storing the vertical shift bit vector in memory cells that are coupled the sense line that is coupled to memory cells storing a corresponding bit vector.23. The method of claim 21 , wherein performing the shift operations includes shifting elements of each of the bit vectors that are coupled to a common access line by an amount indicated by the vertical shift bit vector.24. The method of claim 21 , wherein performing the shift operations includes performing a shift iteration on each element of each of the bit vectors that are coupled to a common access line by an amount indicated by elements of the vertical shift bit vector.25. The method claim 21 , performing the shift operations includes performing a first AND operation with an element of the vertical shift bit vector and an element of the bit vector that is being shifted.26. The method of claim 21 , wherein performing the shift operations includes performing at ...

Comparison operations in memory

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

DATA SHIFT BY ELEMENTS OF A VECTOR IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line. 1. A method , comprising:performing a shift operation on a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array,wherein the shift operation includes shifting the first element by a number of bit positions defined by a second element without transferring data via an input/output (I/O) line, wherein the second element is stored in a second group of memory cells coupled to a second access line and a the number of sense lines of the memory array.2. The method of claim 1 , wherein performing the shift operation comprises performing a number of AND operations claim 1 , OR operations claim 1 , SHIFT operations claim 1 , and INVERT operations without a sense line address access.3. The method of claim 1 , further comprising storing a result of the shift operation in a third group of memory cells coupled to a third access line.4. The method of claim 3 , wherein the result of the shift operation is stored in at least one of the first group of memory cells coupled to the first access line and the second group of memory cells coupled to the second access line.5. The method of claim 1 , wherein the number of operations are performed using sensing circuitry coupled to each of a number of columns ...

Division operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

Vertical bit vector shift in memory

Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.

Data shift by elements of a vector in memory

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

Apparatuses and methods for performing corner turn operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.

Method of reducing glycosylation of proteins, processes and proteins thereof

The disclosure relates to method of reducing O-glycosylation levels of the insulin or insulin analog precursor molecule produced by Pichia sp. The present disclosure provides genetically engineered knock-out strains of methylotrophic yeast including Pichia and especially Pichia pastoris by disruption of Protein mannosyl transferase (PMT) genes and rendering them capable of producing heterologous proteins with reduced glycosylation. Vectors, which comprise coding sequences for PMT1, PMT2, PMT4, PMT5, and PMT6 genes, for transforming methylotrophic yeasts are contemplated by the present disclosure. PMT inactivated strains of this disclosure have been deposited at MTCC, Chandigarh. The strains are PMT1/GS115 (MTCC 5515), PMT4/GS115 (MTCC 5516), PMT5/GS115 (MTCC 5517) and PMT6/GS115 (MTCC 5518).

LOOP STRUCTURE FOR OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

SPAN MASK GENERATION

Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth. 1. A method for generating span masks , comprising:creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth.2. The method of claim 1 , wherein the method includes indicating the particular mask depth and wherein the particular mask depth is less than or equal to half of the size of the number of bit vectors.3. The method of claim 1 , wherein creating the number of bit vectors includes creating 1+log(mask depth) bit vectors.4. The method of claim 1 , wherein each of the number of bit vectors are created during performance of one of a number iterations of a span mask generation algorithm.5. The method of claim 1 , wherein creating the number of bit vectors includes shifting bits of an element mask to the right by 1 position a number of times.6. The method of claim 5 , wherein the bits of the element mask are shifted 2times claim 5 , where i indicates which iteration of a span mask generation algorithm is being performed.7. The method of claim 1 , wherein creating the number of bit vectors includes shifting bits of an element mask span mask to the right by a number of positions based on a copy bit ratio.8. The method of claim 7 , wherein the bits of the element mask are shifted 2*i positions when 1 minus the copy bit ration is greater than 0 claim 7 , where i indicates which iteration of a span mask generation algorithm is being performed.9. The method of claim 1 , wherein the method includes storing each of the number of bit vectors in an array of memory cells.10. The method of claim 1 , wherein the ...

Comparison operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

Signed division in memory

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line.

Loop structure for operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

Division operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

DIVISION OPERATIONS ON VARIABLE LENGTH ELEMENTS IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing variable bit-length division operations in a memory. An example method comprises performing a variable length division operation on a first vector comprising variable length elements representing a number of dividends and stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second vector comprising variable length elements representing a number of divisors stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include dividing the first vector by the second vector by performing a number of operations. The method can include performing at least one of the number of operations without transferring data via an input/output (I/O) line. 1. A method for performing division operations comprising: a first vector comprising at least two elements that are different in length representing a number of dividends and initially stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and', 'a second vector comprising at least two elements that are different in length representing a number of divisors and initially stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;, 'performing a division operation onwherein the division operation includes dividing the first vector by the second vector by performing a number of operations and at least one of the number of operations are performed without transferring data via an input/output (I/O) line.2. The method of claim 1 , wherein performing at least one of the number of operations without transferring data via an I/O line comprises performing a number of AND operations claim 1 , OR operations claim 1 , and INVERT operations without a sense line address access.3. The method of claim 1 , wherein a result ...

DATA SHIFT BY ELEMENTS OF A VECTOR IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

Division operations on variable length elements in memory

Examples of the present disclosure provide apparatuses and methods for performing variable bit-length division operations in a memory. An example method comprises performing a variable length division operation on a first vector comprising variable length elements representing a number of dividends and stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second vector comprising variable length elements representing a number of divisors stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include dividing the first vector by the second vector by performing a number of operations. The method can include performing at least one of the number of operations without transferring data via an input/output (I/O) line.

DATA GATHERING IN MEMORY

Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line. 1. A method for gathering data , comprising:storing a first element in memory cells coupled to a first sense line and a plurality of access lines;storing a second element in memory cells coupled to a second sense line and the plurality of access lines, wherein the memory cells coupled to the first sense line are separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines; andtransferring the second element from being stored in the memory cells coupled to the second sense line to being stored in the memory cells coupled to the third sense line.2. The method of claim 1 , wherein transferring the second element comprises reorganizing a data unit in a first position of the second element stored in a memory cell coupled to a first of the plurality of access lines and the second sense line to be stored in a memory cell coupled to the first of the plurality of access lines and the third sense line.3. The method of claim 2 , wherein transferring the second element comprises reorganizing a data unit of the second element from being stored in a non-adjacent memory cell to being stored in an adjacent memory cell in relation to a memory cell storing a data unit of the first element.4. The method of claim 3 , wherein the non-adjacent memory cell claim 3 , the adjacent memory ...

Data shift by elements of a vector in memory

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

LOOP STRUCTURE FOR OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

Data gathering in memory

Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

Comparison operations in memory

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

SIGNED DIVISION IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line.

Comparison operations in memory

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

COMPARISON OPERATIONS IN MEMORY

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel. 120-. (canceled)21. An apparatus , comprising:a first group of memory cells coupled to a first access line and configured to store a plurality of elements; the elements stored in the first group and the second group each include a first element and a second element having different bit lengths; and', 'the first element stored in the first group has a bit length equal to a bit length of the first element stored in the second group and the second element stored in the first group has a bit length equal to a bit length of the second element stored in the second group; and, 'a second group of memory cells coupled to a second access line and configured to store a plurality of elements; wherein a first element pair to be compared by controlling sensing circuitry to perform a number of operations, the first element pair comprising the first element stored in the first group and the first element stored in the second group; and', 'a second element pair to be compared in parallel with the first element pair, the second element pair comprising the second element stored in the first group and the second element stored in the second group., 'a controller configured to cause22. The apparatus of claim 21 , wherein the number of operations ...

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

VECTOR POPULATION COUNT DETERMINATION IN MEMORY

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array. 1. A method , comprising:determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.2. The method of claim 1 , wherein the determining of the vector population count is performed in the memory array.3. The method of claim 1 , wherein determining the vector population count includes performing a number of AND claim 1 , OR claim 1 , and shift operations claim 1 , wherein the number of AND and shift operations is based on a length of the number of fixed length elements.4. The method of claim 2 , wherein the number of AND claim 2 , OR claim 2 , and shift operations are performed using sensing circuitry coupled to each of a number of columns of complementary sense lines.5. The method of claim 1 , wherein the determining of the vector population count includes determining how many bits of each of the number of fixed length elements have a particular value.6. The method of claim 5 , wherein the particular value includes a bit value of 1.7. The method of claim 5 , wherein the particular value includes a bit value of 0.8. The method of claim 1 , wherein the vector is stored in a group of memory cells coupled to a particular access line.9. The method of claim 8 , including determining the vector population count and storing a result of the determination of the vector population count in a group of memory cells coupled to a different particular access line of the memory array without performing a sense line address access.10. The method of claim 1 , wherein determining the vector population count includes creating an elemental mask that indicates a most significant bit of each of the number of fixed length elements. ...

NOVEL FUSION PROTEINS AND METHOD OF EXPRESSION THEREOF

The present invention relates to novel Prolipase-Bovine trypsinogen (PLBTR) fusion proteins, the genes encoding them, and the production and uses thereof. More specifically, the present invention relates to methods of producing in optimal quantities PLBTR fusion proteins which comprise a heterologous polypeptide which is normally susceptible to autocatalytic activity. More particularly, the present invention relates to fusion proteins which comprise an heterologous polypeptide, such as a serine protease, fused to a lipase signal sequence, which can be expressed by recombinant host cells in desired amounts. The present invention further relates to polynucleotides encoding such fusion proteins, to expression vectors for expression of such fusion proteins, to host cells transformed with such polynucleotides/vectors, and to methods of generating such fusion proteins. 1. A fusion polypeptide comprising at least one serine protease fused to a lipase signal sequence , said fusion polypeptide being expressed in a methyloptrophic yeast wherein said fusion polypeptide has an amino acid sequence at least 80 percent homologous to SEQ ID NO: 2.2. The fusion polypeptide as claimed in claim 1 , wherein the amino acid sequence corresponds to a nucleotide sequence at least 80 percent homologous to SEQ ID NO: 1.3. The fusion polypeptide as claimed in claim 1 , wherein said polypeptide enables conversion of precursor form of insulin or insulin analogs or insulin derivatives to their corresponding active forms affording a step yield of at least 70%.4Pichia pastoris.. The fusion polypeptide as claimed in claim 1 , wherein said methylotrophic yeast is5. A method of obtaining a fusion polypeptide comprising at least one serine protease fused to a prolipase signal sequence in a methylotrophic yeast wherein said fusion polypeptide has an amino acid sequence at least 80% homologous to SEQ ID No 2 claim 1 , said method comprising acts of:a. fusing serine protease to a prolipase signal ...

METHOD OF REDUCING GLYCOSYLATION OF PROTEINS, PROCESSES AND PROTEINS THEREOF

The disclosure relates to method of reducing O-glycosylation levels of the insulin or insulin analog precursor molecule produced by sp. The present disclosure provides genetically engineered knock-out strains of methylotrophic yeast including and especially by disruption of Protein mannosyl transferase (PMT) genes and rendering them capable of producing heterologous proteins with reduced glycosylation. Vectors, which comprise coding sequences for PMT1, PMT2, PMT4, PMT5, and PMT6 genes, for transforming methylotrophic yeasts are contemplated by the present disclosure. PMT inactivated strains of this disclosure have been deposited at MTCC, Chandigarh. The strains are PMT1/GS115 (MTCC 5515), PMT4/GS115 (MTCC 5516), PMT5/GS115 (MTCC 5517) and PMT6/GS115 (MTCC 5518). 1. A method of reducing glycosylation of a protein produced from a methylotrophic yeast enabled through inactivation of at least one or more genes selected from the group comprising PMT1 , PMT2 , PMT4 , PMT5 and PMT6 genes having a nucleotide sequence that is at least 80% homologous to nucleotide sequence represented by SEQ ID Nos. 1 , 2 , 3 , 4 and 5 respectively , said sequences encoded for the protein mannosyl transferase or a functional part thereof.2Pichia. The method according to claim 1 , wherein said methylotrophic yeast belongs to sp.3Pichia pastoris.. The method according to claim 2 , wherein said methylotrophic yeast is5. The method according to claim 1 , wherein the mode of glycosylation is O-glycosylation.6. The method according to claim 1 , wherein glycosylation is reduced by at least 10% to about 99%7. The method according to claim 6 , wherein glycosylation is reduced by 25%.8. The method according to claim 6 , wherein glycosylation is reduced by 65%.9. A vector containing the protein mannosyl transferase gene or a functional part thereof selected from the group comprising PMT1 claim 6 , PMT2 claim 6 , PMT4 claim 6 , PMT5 and PMT6 genes having a nucleotide sequence that is at least 80% ...

MULTIPLICATION OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line. 120.-. (canceled)21. A method , comprising: one of a plurality of first elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and', 'one of a plurality of second elements stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array;', 'wherein multiplying the plurality of element pairs, in parallel, comprises performing a number of logical operations between constituent bits of the respective plurality of first elements and constituent bits of a mask bit vector stored in the memory array; and', 'wherein the number of logical operations are performed using sense amplifiers coupled to the number of sense lines and compute components coupled to the sense amplifiers; and, 'multiplying, in parallel and on a memory device, a plurality of element pairs stored in a memory array, wherein the plurality of element pairs each compriseproviding multiplication results corresponding to the respective element pairs.22. The method of claim 21 , wherein providing multiplication results corresponding to the respective element pairs comprises storing the multiplication results in the memory array.23. The method of claim 22 , wherein storing the multiplication results in the memory array comprises storing the multiplication results in a third group of memory cells coupled to a third access ...

Signed division in memory

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

SMALLEST OR LARGEST VALUE ELEMENT DETERMINATION

Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value. 1. A method , comprising:storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array;performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector;updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; andproviding an indication of which of the plurality of elements have one of a smallest value and a largest value.2. The method of claim 1 , wherein performing the logical operation comprises loading the first vector from the array to a plurality of sensing components of the sensing circuitry claim 1 , wherein each of the plurality of sensing components comprises a sense amplifier and a compute component.3. The method of claim 1 , wherein the method further comprises performing the logical operation without transferring data via an input/output line coupled to the sensing circuitry.4. The method of claim 1 , wherein the second vector is an inverted elements vector claim 1 , and wherein the method further comprises: loading the elements ...

Memory sub-system event log management

A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.

DIVISION OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line. 1. An apparatus comprising:a first group of memory cells coupled to a first access line and configured to store a dividend element;a second group of memory cells coupled to a second access line and configured to store a divisor element; anda controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.2. The apparatus of claim 1 , wherein the number of operations comprises a number of AND operations claim 1 , OR operations claim 1 , and SHIFT operations.3. The apparatus of claim 2 , wherein the sensing circuitry comprises a number of transistors formed on pitch with the memory cells.4. The apparatus of claim 3 , wherein the sensing circuitry comprises a sense amplifier and a compute component.5. The apparatus of claim 4 , wherein the sense amplifier comprises a primary latch and the compute component comprises a secondary latch.6. A method for performing division operations claim 4 , comprising: a plurality of dividend elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and', 'a plurality of divisor elements stored in a second group of memory cells coupled to a second access line and to the ...

MULTIPLICATION OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line. 1. A method for performing multiplication operations comprising: a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and', 'a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;, 'performing a multiplication operation onwherein the multiplication operation includes a number of operations performed without transferring data via an input/output (I/O) line.2. The method of claim 1 , wherein performing the number of operations without transferring data via an I/O line comprises performing a number of AND operations claim 1 , OR operations claim 1 , SHIFT operations claim 1 , and INVERT operations without a sense line address access.3. The method of claim 1 , further comprising storing a result of the multiplication operation in the group of memory cells coupled to a third access line claim 1 , wherein the group of memory cells comprises at least one of the group of memory cells coupled to the first access line and the group of memory cells coupled to the second access line.4. The method of claim 1 , wherein the number of operations are performed using sensing circuitry coupled to each of a number of columns of the number of sense lines.5. The method of claim 4 , wherein the sensing circuitry comprises a sense amplifier and a compute component.6. The method of ...

MULTIPLICATION OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line. 1. A method for performing multiplication operations comprising: a first vector comprising a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and', 'a second vector comprising a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;, 'performing a multiplication operation onwherein the multiplication operation includes performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.2. The method of claim 1 , wherein performing the number of AND operations claim 1 , OR operations and SHIFT operations without transferring data via an I/O line comprises performing the number of AND operations claim 1 , OR operations and SHIFT operations without a sense line address access.3. The method of claim 1 , further comprising storing a result of the multiplication operation is in a group of memory cells coupled to a third access line.4. The method of claim 1 , further comprising storing a result of the multiplication operation in at least one of the group of memory cells coupled to ...

COMPARISON OPERATIONS IN MEMORY

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel. 1. An apparatus comprising:a first group of memory cells coupled to a first access line and configured to store a plurality of first elements;a second group of memory cells coupled to a second access line and configured to store a plurality of second elements; and the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line; and', 'the plurality of first elements and the plurality of second elements to be compared in parallel., 'a controller configured to cause2. The apparatus of claim 1 , wherein the number of operations comprises a number of AND operations claim 1 , OR operations claim 1 , INVERT operations claim 1 , and SHIFT operations.3. The apparatus of claim 1 , wherein the sensing circuitry comprises a number of transistors formed on pitch with the memory cells.4. The apparatus of claim 3 , wherein the sensing circuitry comprises a sense amplifier and a compute component.5. The apparatus of claim 4 , wherein the sensing circuitry comprises a sense amplifier comprising a primary latch and a compute component comprising a secondary latch.6. A method for comparing elements ...

Fermentation Medias and Processes Thereof

The present invention demonstrates the utility of carbonic acid amides such as urea or its derivatives, carbamates, carbodiimides & thiocarbamides as nitrogenous supplements in fermentation media for production of recombinant proteins to achieve enhanced bioconversion rates and peptides like insulin and insulin analogues, exendin and enzymes such as lipase using methanol inducible fungal expression systems such as 1. A fermentation medium for production of a recombinant protein or a derivative or analog thereof or a secondary metabolite by improving phosphate uptake through fermentation using microorganism , said medium characterized in that residual concentration of urea is maintained in a range of about 0.5 g/L to about 3 g/L , varying concentration of basal salts and trace elements from about 0.1× to about 5× of control medium , and methanol feeding rate ranges from about 6 g/L/h to about 20 g/L/h.2E. coli, StreptomycesAspergillusRhizopusPenilliumRhizomucor. The fermentation medium according to claim 1 , wherein the urea is selected from the group comprising urea claim 1 , or a derivative of urea including dimethylurea claim 1 , diethylurea claim 1 , N-acetylphenyl urea claim 1 , isopropylpylideneurea claim 1 , phenylurea and any combinations thereof; and wherein the urea is added in liquid claim 1 , spray claim 1 , powder or pellet form claim 1 , and wherein the microorganism is selected from the group comprising sp claim 1 , sp claim 1 , sp claim 1 , sp claim 1 , and sp.3. The fermentation medium according to claim 1 , wherein the recombinant protein is selected from group comprising G-CSF claim 1 , streptokinase and lipase; and wherein the secondary metabolite is pravastatin.4. The fermentation medium according to claim 1 , wherein the recombinant protein or a derivative or analog thereof yield a maximum product titre of above 0.5 g/L; and wherein the secondary metabolite effectuates bioconversion of compactin to pravastatin by at least 35%.5. A process for ...

Comparison operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

VECTOR POPULATION COUNT DETERMINATION IN MEMORY

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array. 1. A method , comprising: creating an elemental mask that indicates a most significant bit of each of the number of fixed length elements; and', {'sub': '2', 'performing a number of comparison iterations, wherein the number of comparison iterations are based on a logof a number of bits in the number of fixed length elements.'}], 'determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array by2. The method of claim 1 , wherein performing the number of comparison iterations comprises determining a reduction vector for each of the number of comparison iterations.3. The method of claim 1 , wherein performing the number of comparison iterations comprises determining a pattern mask for each of the number of comparison iterations.4. The method of claim 1 , wherein the determining of the vector population count is performed in the memory array.5. The method of claim 1 , wherein determining the vector population count includes performing a number of AND claim 1 , OR claim 1 , and shift operations claim 1 , wherein the number of AND and shift operations are based on a length of the number of fixed length elements.6. The method of claim 5 , wherein the number of AND claim 5 , OR claim 5 , and shift operations are performed using sensing circuitry coupled to each of a number of columns of complementary sense lines.7. The method of claim 1 , wherein the determining of the vector population count includes determining how many bits of each of the number of fixed length elements have a particular value.8. The method of claim 7 , wherein the particular value includes a bit value of 1.9. The method of claim 7 , wherein the ...

Element value comparison in memory

The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater.

APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY

The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry. 114.-. (canceled)15. An apparatus comprising:a first group of memory cells coupled to a particular access line and to a plurality of sense lines;a second group of memory cells coupled to a plurality of access lines and to one of the plurality of sense lines, wherein the particular access line is one of the plurality of access lines; anda controller configured to cause a corner turn operation to be performed on an element stored in the first group of memory cells such that the corner turn operation results in the element being stored in the second group of memory cells;wherein the controller is configured to cause performance of the corner turn operation by controlling sensing circuitry coupled to the plurality of sense lines to perform a plurality of logical operations using data units corresponding to the element as inputs.16. The apparatus of claim 15 , wherein the plurality of logical operations comprises at least one of:a number of AND operations;a number of OR operations; anda number of XOR operations.17. The apparatus of claim 16 , wherein the controller is configured to cause performance of the corner turn operation by performing the plurality of logical operations without transferring data external to the sensing circuitry.18. The apparatus of claim 16 , wherein the ...

NETWORK DEVICE VULNERABILITY PREDICTION

The vulnerability of network devices may be predicted by performing a survival analysis on big data. A prediction algorithm may be built by considering historical data from heterogeneous data sources. The operating state of the network devices on a network may be predicted. The services potentially affected by a predicted outage may be determined and displayed. Alternatively or in addition, the number of clients potentially affected by a predicted outage may be determined and displayed. 1. A system comprising:a processor configured to:detect an outage of a network device;determining the outage of the network device is an actual outage based on an indication that a human confirmed the outage of the network device was an actual outage;predict a vulnerability of the network device based on a survival analysis; andcause the vulnerability of the network device to be displayed.2. The system of claim 1 , wherein the processor is further configured to identify one or more services that would be affected by a predicted outage of the network device.3. The system of claim 1 , wherein the processor is further configured to determine a number of customers that would be affected by a predicted outage of the network device.4. The system of claim 1 , wherein the processor is further configured to determine a cause of the outage of the network device based on an anomaly in a performance indicator of the network device.5. The system of claim 1 , wherein the processor is further configured to determine a cause of the outage of the network device based on an anomaly in configuration data of the network device.6. The system of claim 1 , wherein the survival analysis is performed on data collected from at least a fault management system and a performance management system.7. The system of claim 1 , wherein the processor is configured to perform the survival analysis based on variables that include a number of clients connected to the network device claim 1 , a percentage of usage of a ...

ON-DEMAND FAULT REDUCTION FRAMEWORK

A computer-implemented method for correlating alarms that are generated with relation to a computer network is disclosed. The alarms represent faults of the computer network and/or faults of components of the computer network. The computer-implemented method comprises: displaying, on a display device, a graphical user interface that allows a user to select a type of correlation between one or more alarms and a type of fault which causes the one or more alarms from among a plurality of types of correlation; receiving, via the graphical user interface, a user input indicating the type of correlation selected by the user; storing, in a database, at least one rule based on the selected correlation; receiving, by a server, a plurality of alarms generated with relation to the computer network; correlating, by a correlation engine, the plurality of alarms received by the server according to the at least one rule stored in the database to identify a fault which has caused the one or more alarms; and displaying, on the display device, the at least one identified fault. 1. A computer-implemented method for correlating alarms that are generated with relation to a computer network , wherein the alarms represent faults of the computer network and/or faults of components of the computer network , the computer-implemented method comprising:presenting, on a display device, a graphical user interface that allows a user to select a type of correlation between one or more alarms and a type of fault which causes the one or more alarms from among a plurality of types of correlation;receiving, via the graphical user interface, a user input indicating the type of correlation selected by the user;storing, in a database, at least one rule based on the type of correlation selected by the user;receiving, by a server, a plurality of alarms generated with relation to the computer network;correlating, by a correlation engine, the plurality of alarms received by the server according to the at ...

MULTIPLICATION OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line. 120.-. (canceled)21. A system , comprising:a processing resource; and sensing circuitry coupled to an array of memory cells; and', 'a controller configured to control the sensing circuitry to multiply a first element stored in a first group of memory cells coupled to a first access line of the array by a second element stored in a second group of memory cells coupled to a second access line of the array without transferring data from the sensing circuitry via activation of column decode lines coupled thereto., 'a memory device coupled to the processing resource, wherein the memory device comprises22. The system of claim 21 , wherein the controller is configured to control the sensing circuitry to multiply the first element by the second element by controlling the sensing circuitry to perform a plurality of logical operations without transferring data from the array to the controller.23. The system of claim 21 , wherein controlling the sensing circuitry to perform the plurality of logical operations includes controlling the sensing circuitry to perform at least one AND operation between a bit vector stored in the array and a bit vector stored in the sensing circuitry.24. The system of claim 21 , wherein the processing resource is external to the memory device.25. The system of claim 24 , wherein the processing resource comprises a processor of a host to which the memory device is coupled.26. The system of claim ...

LONGEST ELEMENT LENGTH DETERMINATION IN MEMORY

Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array. 1. A method , comprising:determining, using a controller that controls sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.2. The method of claim 1 , wherein determining the length of the longest element comprises an AND operation and a shift operation claim 1 , wherein the AND operation and the shift operation is are based on the length of the longest element.3. The method of claim 2 , wherein the determining of the length of the longest element is performed in the memory array.4. The method of claim 2 , wherein the AND operation and the shift operation are each performed using sensing circuitry coupled to each of a number of columns of complementary sense lines.5. The method of claim 1 , wherein the determining of the length of the longest element comprises determining whether one or more of bits of each of the plurality of variable length elements includes a particular value.6. The method of claim 5 , wherein the particular value includes a bit value of 1.7. The method of claim 1 , comprising performing an operation on at least one element of the plurality of elements based on the length of the longest element.8. The method of claim 7 , wherein the operation is performed after the length of the longest element is determined.9. The method of claim 7 , wherein the operation is performed concurrent with the determination of the length of the longest element.10. The method of claim 1 , wherein the vector is stored in a group of memory cells coupled to a particular access line.11. The method of claim 10 , wherein a result of the determination of the length of the longest ...

MULTIPLICATION OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line. 120.-. (canceled)21. A system , comprising:a processing resource; and an array of memory cells; and', 'sensing circuitry coupled to the array;, 'a memory device coupled to the processing resource, wherein the memory device compriseswherein the memory device is configured to multiply, in parallel, a plurality of element pairs stored in the array by controlling the sensing circuitry to perform logical operation processing on data without moving the data out of the sensing circuitry via activation of column decode lines coupled thereto.22. The system of claim 21 , wherein the array comprises:a first group of cells coupled to a plurality of sense lines to a first access line, wherein the first group of cells are configured to store a plurality of first elements of the plurality of element pairs; anda second group of cells coupled to the plurality of sense lines to a second access line, wherein the second group of cells are configured to store a plurality of second elements of the plurality of element pairs.23. The system of claim 21 , wherein the logical operation processing includes performing a number of AND logical operations on data without moving the data out of the sensing circuitry via activation of column ...

Data migration system

A system for migrating data from a legacy system to a target system includes an input/output (IO) processor configured to receive legacy data from a plurality of different types of legacy systems and to communicate target data to a plurality of different types of target systems; a staging area database configured to store legacy data according to a common database schema; a localized database configured to store target data according to a target schema that is associated with a target system type; a processor in communication with the interface, the staging area database, and the localized database; and non-transitory computer readable media in communication with the processor that stores instruction code. The instruction codes is executed by the processor and causes the processor to: determine a target schema associated with a target system type; convert the legacy data stored in the staging area database to localized data according to the determined target schema; store the localized data in the localized database; and communicate the localized data to the target system.

SIGNED DIVISION IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line. 114.-. (canceled)15. A system , comprising:a first processing resource; and [ store a signed dividend element in a group of memory cells coupled to a first access line of the array; and', 'store a signed divisor element stored in a group of memory cells coupled to a second access line of the array; and, 'an array of memory cells configured to, 'sensing circuitry coupled to the array and operated as a second processing resource to divide the signed dividend element by the signed divisor element by performing a number of logical operations without transferring data to the first processing resource., 'a memory device coupled to the processing resource, wherein the memory device comprises16. The system of claim 15 , wherein the first processing resource comprises a processor.17. The system of claim 15 , wherein the first processing resource comprises a processing resource of a host and is coupled to the memory device via a bus.18. The system of claim 15 , wherein the sensing circuitry is operated to divide the signed dividend element by the signed divisor element by performing the number of logical operations without moving data out of the sensing circuitry via activation of column decode lines coupled thereto.19. The system of claim 15 , wherein the memory ...

Longest element length determination in memory

Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.

COMPARISON OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line. 117-. (canceled)18. An apparatus comprising:a first group of memory cells coupled to a first access line of an array of memory cells and configured to store a first element;a second group of memory cells coupled to a second access line of the array of memory cells and configured to store a second element;a plurality of sense amplifiers coupled to respective columns of the array corresponding to the first group of memory cells and the second group of memory cells; anda controller coupled to the plurality of sense amplifiers and configured to control the plurality of sense amplifiers and a plurality of compute components to compare the first element to the second element by performing a number of AND operations, OR operations, shift operations, and invert operations.19. The apparatus of claim 18 , wherein the controller is further configured control the plurality of sense amplifiers and the plurality of compute components to perform the number of AND operations claim 18 , OR operations claim 18 , invert operations claim 18 , and shift operations without performing a sense line address access.20. The apparatus of claim 18 , wherein the plurality of sense amplifiers are coupled to a plurality of sense lines of the array of memory cells and to the plurality of compute components.21. The apparatus of ...

SPAN MASK GENERATION

Examples of the present disclosure provide apparatuses and methods for span mask generation. An example method comprises creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth. 1. A method for generating span masks , comprising:creating, using sensing circuitry, a number of bit vectors, wherein each of the number of bit vectors includes a repeating pattern based on a size of the number of bit vectors and a particular mask depth, wherein the particular mask depth is checked by performing a left shift on a binary representation of the particular mask depth and comparing the result to a width of the number of bit vectors.2. The method of claim 1 , wherein the method includes indicating the particular mask depth and wherein the particular mask depth is less than or equal to half of the size of the number of bit vectors.3. The method of claim 1 , wherein creating the number of bit vectors includes creating 1+log(mask depth) bit vectors.4. The method of claim 1 , wherein each of the number of bit vectors are created during performance of one of a number iterations of a span mask generation algorithm.5. The method of claim 1 , wherein creating the number of bit vectors includes shifting bits of an element mask to the right by 1 position a number of times.6. The method of claim 5 , wherein the bits of the element mask are shifted 2times claim 5 , where i indicates which iteration of a span mask generation algorithm is being performed.7. The method of claim 1 , wherein creating the number of bit vectors includes shifting bits of an element mask span mask to the right by a number of positions based on a copy bit ratio.8. The method of claim 7 , wherein the bits of the element mask are shifted 2*i positions when 1 minus the copy bit ration is greater than 0 claim 7 , where i indicates which iteration of a span mask generation ...

QUALITY OF SERVICE MANAGER FOR NETWORK SLICES OF A NETWORK

A device determines, from a network slice template associated with a network slice, a quality of service (QoS) profile for the network slice that includes performance metrics for corresponding QoS parameters associated with providing a service. The device monitors performance of the network slice in association with the QoS profile, and determines, based on the performance, that a performance indicator for a QoS parameter of the network slice is outside a threshold range of a performance metric. The device determines, based on the performance information and the QoS profile, a slice modification to the network slice template for the network slice, where the slice modification is configured to cause the performance indicator to be within the threshold range of the performance metric. The device causes a network slice orchestrator to update an instantiation of the network slice according to the slice modification and the network slice template. 1. A method , comprising: 'wherein the network slice is instantiated according to the network slice template;', 'receiving, by a device, information identifying a network slice template associated with a network slice of a network,'} 'wherein the QoS profile includes a plurality of performance metrics for corresponding QoS parameters associated with providing a service;', 'determining, by the device and from the network slice template, a quality of service (QoS) profile for the network slice,'}monitoring, by the device, performance of the network slice in association with the QoS profile;determining, by the device and based on performance information associated with the performance, that a performance indicator for a QoS parameter of the network slice is outside of a threshold range of a performance metric of the plurality of performance metrics; 'wherein the slice modification is configured to cause the performance indicator to be within the threshold range of the performance metric; and', 'determining, by the device and based ...

ELEMENT VALUE COMPARISON IN MEMORY

The present disclosure includes apparatuses and methods related to performing a greater vector determination in memory. An example apparatus comprises a first group of memory cells coupled to a sense line and to a number of first access lines and a second group of memory cells coupled to the sense line and to a number of second access lines. The example apparatus comprises a controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater. 1. An apparatus , comprising:a first group of memory cells coupled to a sense line and to a number of first access lines;a second group of memory cells coupled to the sense line and to a number of second access lines; anda controller configured to operate sensing circuitry to compare a value of a first element stored in the first group of memory cells to a value of a second element stored in the second group of memory cells to determine which of the value of the first element and the value of the second element is greater;wherein the comparison comprises comparing the value of the first element to the value of the second element on a bit-by-bit basis.2. The apparatus of claim 1 , wherein the controller configured to operate the sensing circuitry to perform the number of operations comprises the controller configured to operate sensing circuitry to perform at least one of a number of AND operations claim 1 , OR operations claim 1 , and INVERT operations without performing a sense line address access.3. The apparatus of claim 2 , wherein the sensing circuitry comprises a number of sense amplifiers and a number of compute components.4. The apparatus of claim 3 , wherein each of the number of compute components comprises a number of transistors formed on pitch with memory cells corresponding to a ...

Apparatuses and methods for performing corner turn operations using sensing circuitry

The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.

LONGEST ELEMENT LENGTH DETERMINATION IN MEMORY

Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array. 120-. (canceled)21. A method , comprising: 'performing, in the sensing circuitry, a shift operation on an element mask vector indicating most significant bits of the plurality of variable length elements of the vector.', 'determining, using sensing circuitry coupled to a memory array and controlled by a controller, a length of a longest element of a plurality of variable length elements of a vector stored in the memory array by22. The method of claim 21 , wherein determining the length of the longest element comprises an AND operation and the shift operation claim 21 , wherein the AND operation and the shift operation are based on the length of the longest element.23. The method of claim 22 , wherein the AND operation and the shift operation are each performed using the sensing circuitry coupled to each of a number of columns of complementary sense lines.24. The method of claim 21 , wherein the determining of the length of the longest element comprises determining whether one or more of bits of each of the plurality of variable length elements includes a particular value.25. The method of claim 24 , wherein the particular value includes a bit value of 1.26. The method of claim 21 , wherein the vector is stored in a group of memory cells coupled to a particular access line.27. The method of claim 26 , wherein a result of the determination of the length of the longest element is stored in a group of memory cells coupled to a different particular access line of the memory array.28. The method of claim 21 , further comprising performing an invert operation on the element mask vector and performing a different shift operation on the result of the ...

SIGNED DIVISION IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. 1. An apparatus comprising:a first group of memory cells coupled to a sense line and to a number of first access lines;a second group of memory cells coupled to the sense line and to a number of second access lines; anda controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.2. The apparatus of claim 1 , wherein the controller configured to operate the sensing circuitry to perform the number of operations comprises the controller configured to operate sensing circuitry to perform at least one of a number of AND operations claim 1 , OR operations claim 1 , INVERT operations claim 1 , and SHIFT operations without performing a sense line address access.3. The apparatus of claim 2 , wherein the sensing circuitry comprises a number of sense amplifiers and a number of compute components.4. The apparatus of claim 3 , wherein each one of the number of compute components comprises a number of transistors formed on pitch with memory cells corresponding to a particular one of a number of columns of memory cells.5. The apparatus of claim 1 , wherein the signed dividend element is of a signed first value and the signed divisor element is of a signed second value.6. The apparatus of claim 5 , ...

PROCESS FOR EXPRESSION OF RECOMBINANT PROTEINS IN PICHIA PASTORIS USING A FED BATCH MODEL

The present disclosure relates to a comprehensive model for expression of recombinant peptides by . The model uses an easily controllable variable called ‘critical nutrient ratio’ for obtaining a right balance between product synthesis and it's degradation during the fermentation process. The extra cellular concentration of precursor could be increased by about 10 folds and the degradation constants could be reduced by about 10-20 folds for intracellular and extracellular cases respectively by controlling critical nutrient ratio and addition of soya flour hydrolysate and EDTA. 1Pichia pastoris. A process for the expression of recombinant protein in by using a comprehensive model.2. The process as claimed in claim 1 , wherein the comprehensive model is a fed batch model which is dynamically structured with peptide synthesis claim 1 , secretion and degradation.3Pichia pastoris. The process as claimed in claim 1 , wherein the expression of recombinant protein in by controlling critical nutrient ratio (CNR) and addition of soya flour hydrolysate and EDTA.4. The process as claimed in claim 1 , wherein CNR controls intra and extracellular protease activity by controlling protease synthesis rate and release in extracellular medium.5. The process as claimed in claim 1 , wherein the recombinant protein precursor is lispro.6. The process as claimed in claim 1 , wherein the recombinant protein precursor is insulin analogue.7. The process as claimed in claim 1 , wherein the recombinant protein precursor is glargine8. The process as claimed in claim 1 , wherein the recombinant protein is carboxypeptidase.9. The process as claimed in claim 3 , where in the EDTA and soya flour hydrolysate in the concentration ranges of 15-20 g/1 and 5-6% w/v controls degradation due to proteases.10. The process as claimed in claim 4 , wherein the extra cellular concentration of lispro precursor could be increased by about 10 folds and the degradation constants could be reduced by about 10-20 folds ...

USER RETENTION PLATFORM

A device identifies, by using a first model to process a first weighted feature set, users who are predicted to stop using a service provider for one or more services. The device determines, by using a second model to process a second weighted feature set, user scores for the users who represent predicted value that the users provide to the service provider. The device identifies, based on the user scores, particular users, of the users, as targets to be offered additional services. The device determines, by using a third model to process a third weighted feature set, service scores that represent predicted levels of interest of a user, of the particular users, in a set of services. The device selects services based on the service scores. The device causes a services package that includes the services to be provided to a user device or an account associated with the user. 1. A method , comprising:determining, by a device, that a condition is satisfied that causes the device to determine whether to offer additional services to particular users of a group of users who have accounts with a service provider;receiving, by the device, user data associated with the group of users, wherein the user data includes at least one of user account data, user behavioral data, or technical support data;receiving, by the device, a set of network performance indicator (NPI) values that measure network performance of a network that is accessible to user devices associated with the group of users;determining, by the device and by processing the user data and the set of NPI values, a first set of weighted features that affect likelihoods that the group of users will stop using the service provider for one or more services;identifying, by the device and by using a first data model to process the first set of weighted features, a subgroup of users, of the group of users, that are predicted to stop using the service provider for the one or more services;determining, by the device and by ...

COMPARISON OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line. 1. An apparatus comprising:a first group of memory cells coupled to a first access line and configured to store a first element;a second group of memory cells coupled to a second access line and configured to store a second element; andsensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.2. The apparatus of claim 1 , wherein performing the number of AND operations claim 1 , OR operations claim 1 , INVERT operations claim 1 , and SHIFT operations comprises performing the number of AND operations claim 1 , OR operations claim 1 , INVERT operations claim 1 , and SHIFT operations without performing a sense line address access.3. The apparatus of claim 2 , further comprising performing the number of AND operations claim 2 , OR operations claim 2 , INVERT operations claim 2 , and SHIFT operations using sensing circuitry on pitch with a number of columns of complementary sense lines corresponding to the first and second groups of memory cells.4. The apparatus of claim 3 , wherein the sensing circuitry comprises a sense amplifier and a compute component corresponding to each respective one of the number of columns.5. The ...

Division operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

Data gathering in memory

Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

COMPARISON OPERATIONS IN MEMORY

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel. 120-. (canceled)21. A system , comprising:a first group of memory cells coupled to a first access line and configured to store a plurality of elements; the elements stored in the first group and the second group each include a first element and a second element having different bit lengths; and', 'the first element stored in the first group has a bit length equal to a bit length of the first element stored in the second group and the second element stored in the first group has a bit length equal to a bit length of the second element stored in the second group; and, 'a second group of memory cells coupled to a second access line and configured to store a plurality of elements; wherein a first element pair to be compared by controlling sensing circuitry to perform a number of operations, the first element pair comprising the first element stored in the first group and the first element stored in the second group; and', 'a second element pair to be compared in parallel with the first element pair, the second element pair comprising the second element stored in the first group and the second element stored in the second group., 'a controller configured to cause22. The system of claim 21 , further comprising a memory device ...

AUTOMATIC MONITORING, CORRELATION, AND RESOLUTION OF NETWORK ALARM CONDITIONS

A device receives first network information associated with a first portion of a network, and second network information associated with a second portion of the network, and determines, based on the first network information and the second network information, an alarm condition for the network. The device determines, based on correlation rules, whether the alarm condition relates to a currently handled alarm condition or a previously handled alarm condition. The device correlates the alarm condition with network inventory information, network topology information, and network service information, when the alarm condition does not relate to the currently handled alarm condition or the previously handled alarm condition, to generate a correlated alarm condition. The device automatically generates a resolution for the correlated alarm condition based on the correlated alarm condition, and automatically performs one or more actions based on the resolution for the correlated alarm condition. 1. A method , comprising:receiving, by a device, first network information associated with a first portion of a network;receiving, by the device, second network information associated with a second portion of the network that is different than the first portion of the network;determining, by the device and based on the first network information and the second network information, an alarm condition for the network;determining, by the device and based on correlation rules, whether the alarm condition relates to a currently handled alarm condition or a previously handled alarm condition; 'wherein correlating the alarm condition, with the network inventory information, the network topology information, and the network service information, generates a correlated alarm condition;', 'processing, by the device, the alarm condition, network inventory information, network topology information, and network service information, with a machine learning model and when the alarm condition does ...

MULTIPLICATION OPERATIONS IN MEMORY

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line. 1. A system , comprising:a processing resource configured to generate instructions; and an array of memory cells;', 'a plurality of sense amplifiers coupled to the array; and', 'a plurality of compute components coupled to the plurality of sense amplifiers;, 'a memory device coupled to the processing resource and comprisingwherein the memory device is configured to execute the instructions to multiply, in parallel, a plurality of element pairs stored in the array by controlling the plurality of sense amplifiers and the plurality of compute components to perform logical operation processing on data without moving the data to the processing resource.2. The system of claim 1 , wherein the memory device comprises control circuitry configured to provide control signals to the array claim 1 , to the plurality of sense amplifiers claim 1 , and to the plurality of compute components to perform the logical operation processing.3. The system of claim 1 , wherein the processing resource comprises a host processor.4. The system of claim 1 , wherein the array comprises a DRAM array.5. The system of claim 1 , wherein the processing resource is external to the memory devices claim 1 , and wherein the system further comprising ...

Compositions and Methods for the Treatment of Peripheral B-Cell Neoplasms

The present invention is directed to the use of a PDE4 inhibitor and a glucocorticoid to treat peripheral B-cell neoplasms. In particular, the present invention provides a method of treating individuals (e.g. patients) diagnosed with peripheral B-cell leukemias by administering pharmaceutical compositions comprising Type 4 cyclic adenosine monophosphate phosphodiesterase inhibitors and a glucocorticoid. Preferably, the combination of the PDE4 inhibitor and the glucocorticoid has a synergistic effect on apoptosis such that the level of apoptosis induced is greater than the level that would be expected by simply adding a PDE4 inhibitor to a glucocorticoid.

Smallest or largest value element determination

Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.

Fed batch solid state fermentation for the production of mycophenolic acid

The present invention provides a novel method for producing mycophenolic acid, by solid state fermentation using fed-batch technique by culturing microorganisms.

Longest element length determination in memory

A length of a longest element can be determined in a memory device. An example method includes determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array. The determination of the length of the longest element can include performing a number of AND operations, shift operations, and invert operations.

Vector population count determination via comparsion iterations in memory

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

Signed division in memory

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

Fermentation medias and processes thereof

Process for expression of recombinant proteins in pichia pastoris using a fed batch model

Fermentation media and processes thereof.

Intelligent network operation platform for network fault mitigation

Embodiments of the present disclosure provide systems, methods, and computer-readable storage media that leverage artificial intelligence and machine learning to identify, diagnose, and mitigate occurrences of network faults or incidents within a network. Historical network incidents may be used to generate a model that may be used to evaluate real-time occurring network incidents, such as to identify a cause of the network incident. Clustering algorithms may be used to identify portions of the model that share similarities with a network incident and then actions taken to resolve similar network incidents in the past may be identified and proposed as candidate actions that may be executed to resolve the cause of the network incident. Execution of the candidate actions may be performed under control of a user or automatically based on execution criteria and the configuration of the fault mitigation system.

Comparison operations in memory

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

Quantum computing in root cause analysis of 5G and subsequent generations of communication networks

Methods, systems, and apparatus for root cause analysis in a communication network. In one aspect, a method includes providing a quantum computer with data representing a topology of the communication network, the topology comprising a graph of vertices representing network devices and edges representing connections between network devices; receiving, from the quantum computer, data representing a first subset of network devices, wherein the first subset comprises a dominating set of vertices or a vertex cover for the graph; monitoring network devices in the first subset to generate alarm data representing triggered network device alarms; providing the alarm data to a quantum computer; receiving, from the quantum computer, data representing a second subset of network devices, wherein the second subset comprises a set cover for the alarm data and the network devices in the second subset comprise diagnosed sources of failures in the communication network.

Novel prolipase-bovine trypsinogen fusion proteins

The present invention relates to novel Prolipase-Bovine trypsinogen (PLBTR) fusion proteins, the genes encoding them, and the production and uses thereof. More specifically, the present invention relates to methods of producing in optimal quantities PLBTR fusion proteins which comprise a heterologous polypeptide which is normally susceptible to autocatalytic activity. More particularly, the present invention relates to fusion proteins which comprise an heterologous polypeptide, such as a serine protease, fused to a lipase signal sequence, which can be expressed by recombinant host cells in desired amounts. The present invention further relates to polynucleotides encoding such fusion proteins, to expression vectors for expression of such fusion proteins, to host cells transformed with such polynucleotides/vectors, and to methods of generating such fusion proteins.

Process for the production of macrolides using a novel strain, Streptomyces sp. BICC 7522

The present invention discloses a new strain of Streptomyces sp. BICC 7522, its variants or mutants and use of the strain for the production of macrolides, process of production and purification of macrolides.

Process for the production of macrolides using a novel strain, streptomyces sp. bicc 7522

The present invention discloses a new strain of Streptomyces sp. BICC 7522, its variants or mutants and use of the strain for the production of macrolides, process of production and purification of microlides.

Multiplication operations in memory

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

Analyzing a communication network device, based on capacity analyses associated with decommissioning the communication network device, to determine next actions

A device may receive site data identifying a site associated with a telecommunications network. The device may determine handover data identifying handovers of user equipment associated with the site. The device may receive traffic data identifying traffic generated by the user equipment associated with the site. The device may calculate, based on the site data, the handover data, and the traffic data, a plurality of key performance indicators (KPIs) for the site, for a predefined time period, and if the site is decommissioned, wherein the plurality of KPIs include one or more of: resource block utilization data, determining KPI satisfaction data identifying whether one or more of the plurality of KPIs satisfy one or more of a plurality of KPI thresholds, and performing one or more actions based on the KPI satisfaction data.

Process for the production of macrolides using a novel strain, Streptomyces sp. BICC 7522

The present invention discloses a new strain of Streptomyces sp. BICC 7522, its variants or mutants and use of the strain for the production of macrolides, process of production and purification of microlides.

Captions for audio content

This disclosure describes, in part, techniques for providing captions with audio content. For instance, an electronic device may receive first data representing audio content and second data representing captions that are available for the audio content. The electronic device may then select portions of the captions for display while outputting the audio content. In some instances, the electronic device selects the portions using timestamps represented by the second data. For instance, the electronic device may select a portion of the captions such that the portion of the captions begins at a first pause within the audio content and/or ends at a second pause within the audio content. In some instances, the electronic device may also display graphical elements that indicate the current location within the captions.

Streptomyces sp. bicc 7522 and its use for the production of macrolides

Smallest or largest value element determination

Examples of the present disclosure provide apparatuses and methods for smallest value element or largest value element determination in memory. An example method comprises: storing an elements vector comprising a plurality of elements in a group of memory cells coupled to an access line of an array; performing, using sensing circuitry coupled to the array, a logical operation using a first vector and a second vector as inputs, with a result of the logical operation being stored in the array as a result vector; updating the result vector responsive to performing a plurality of subsequent logical operations using the sensing circuitry; and providing an indication of which of the plurality of elements have one of a smallest value and a largest value.

Method of obtaining a purified, biologically active heterologous protein

The invention relates to methods of separation and/or purification of impurities yielding a purified heterologous protein product devoid of related impurities or with substantially minimal quantities of such glycosylated impurities. More specifically, the invention relates to the identification of glycosylated forms of insulin analogues such as glargine impurities characterized post expression in yeast based systems such as Pichia pastoris . The invention also relates to methods used to clone gene encoding the protein insulin glargine; inserting the related gene in a suitable yeast host; producing culture of the recombinant strain, stimulating expression of the heterologous polypeptide, its secretion and purification post fermentation and related enzymatic conversions.

Storage volume creation using performance volumes and capacity volumes

Methods, apparatus, and processor-readable storage media are provided herein for storage volume creation using performance volumes and capacity volumes. An example computer-implemented method includes configuring a storage system with at least first and second storage tiers each comprising a plurality of storage devices; creating a virtual storage volume having a first portion corresponding to at least a portion of the plurality of storage devices of the first storage tier and a second portion corresponding to at least a portion of the plurality of storage devices of the second storage tier; and processing input-output requests from one or more host devices associated with the virtual storage volume, wherein the processing comprises moving data between the first portion and the second portion of the virtual storage volume so that each of the input-output requests is processed using the first portion of the virtual storage volume.

Vector population count determination in memory

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

Analyzing a communication network device, based on coverage analyses associated with decommissioning the communication network device, to determine next actions for 5g rollout

A device may receive site data identifying a site associated with a telecommunications network. The device may receive RF drive test data identifying signal strengths of the site at different location points. The device may receive network KPI data and throughput data associated with the site. The device may assign unique identifiers to the different location points. The device may determine, based on the site data, the RF drive test data, the network KPI data, and the unique identifiers, at least one of reference signal strength data for each of the different location points or downlink channel data for each of the different location points. The device may determine degraded signal strength data identifying a degraded signal strength of each of the different location points, if the site is decommissioned and based on the at least one of the reference signal strength data or the downlink channel data.

Data shift by elements of a vector in memory

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

Data gathering in memory

Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

Intelligent network operation platform for network fault mitigation

Storage volume creation using performance volumes and capacity volumes

Methods, apparatus, and processor-readable storage media are provided herein for storage volume creation using performance volumes and capacity volumes. An example computer-implemented method includes configuring a storage system with at least first and second storage tiers each comprising a plurality of storage devices; creating a virtual storage volume having a first portion corresponding to at least a portion of the plurality of storage devices of the first storage tier and a second portion corresponding to at least a portion of the plurality of storage devices of the second storage tier; and processing input-output requests from one or more host devices associated with the virtual storage volume, wherein the processing comprises moving data between the first portion and the second portion of the virtual storage volume so that each of the input-output requests is processed using the first portion of the virtual storage volume.

Verfahren zur herstellung von mycophenolsäure mit penicillium arenicola bicc7673

Utilizing quantum computing and a power optimizer model to determine optimized power insights for a location

A device may receive input data that includes demographic data, power demand data, power source data, power route data, technology data, industry data, and problem data associated with a geographic location, and may identify a section of the geographic location from the demographic data. The device may identify power sources of the section, and may estimate power generation and power demand for the section. The device may determine whether the power demand is greater than the power generation for the section. The device may utilize a quantum computer and a power optimizer model with the input data associated with the section to determine optimized power insights for the section based on determining that the power demand is greater than the power generation for the section, and may perform actions based on the optimized power insights for the section.

Process for producing mycophenolic acid using Penicillium arenicola BICC 7673

The present invention discloses the manufacture of MPA by fermentation under optimal fermentation parameters using a new strain of Penicillium arenicola.

Process for producing mycophenolic acid using penicillium arenicola bicc7673

The present invention discloses the manufacture of MPA by fermentation under optimal fermentation parameters using a new strain of Penicillium arenicola.

Improved fermentation process for higher yield coefficient of lipase-inhibitor with respect to consumed fatty acid

The invention provides a process for the production of lipase inhibitors via an improvised fermentation process characterized in that a combinatorial feeding of linoleic acid or its esters or salts thereof and an omega-9 fatty acid, preferably oleic acid and/or its derivatives is employed during said process resulting in an improved yield co-efficient, productivity further providing ease of operation.

Process for producing mycophenolic acid using penicillium arenicola bicc7673

The present invention discloses the manufacture of MPA by fermentation under optimal fermentation parameters using a new strain of Penicillium arenicola.

Process for producing mycophenolic acid using penicillium arenicola BICC7673

Disclosed is a biologically pure culture of the fungus, Penicillium arenicola BICC 7673. Further disclosed is the manufacture of mycophenolic acid by fermentation under optimal fermentation parameters using such.

Processo para expressão de proteínas recombinantes em pichia pastoris com o uso de um modelo de alimentação em batelada

processo para expressão de proteínas recombinantes em pichia pastoris com o uso de um modelo de alimentação em batelada. a presente revelação se refere a um modelo abrangente para expressão de peptídeos recombinantes por pichia pastoris. o modelo usa uma variável facilmente controlável chamada de ?razão de nutriente crítica? para obter um equilíbrio certo entre síntese de produto e sua degradação durante o processo de fermentação. a concentração extracelular de precursor pode ser aumentada em cerca de 10 vezes e as constantes de degradação podem ser reduzidas em cerca de 10 a 20 vezes para casos intracelulares e extracelulares, respectivamente, controlando-se razão de nutriente crítica e adição de hidrolisado de farinha de soja e edta.

Intelligent network operation platform for network fault mitigation

Embodiments of the present disclosure provide systems, methods, and computer-readable storage media that leverage artificial intelligence and machine learning to identify, diagnose, and mitigate occurrences of network faults or incidents within a network. Historical network incidents may be used to generate a model that may be used to evaluate real-time occurring network incidents, such as to identify a cause of the network incident. Clustering algorithms may be used to identify portions of the model that share similarities with a network incident and then actions taken to resolve similar network incidents in the past may be identified and proposed as candidate actions that may be executed to resolve the cause of the network incident. Execution of the candidate actions may be performed under control of a user or automatically based on execution criteria and the configuration of the fault mitigation system.

Process for producing mycophenolic acid using penicillium arenicola bicc7673

The present invention discloses the manufacture of MPA by fermentation under optimal fermentation parameters using a new strain of Penicillium arenicola.

Process for producing mycophenolic acid using penicillium arenicola bicc7673

The present invention discloses the manufacture of MPA by fermentation under optimal fermentation parameters using a new strain of Penicillium arenicola.

Utilizing multiple analyses to migrate an application to a cloud computing environment

A device may receive source code and a database to be migrated to a cloud computing environment, and may perform a first stage analysis of the source code to generate a first report. The device may cause a second stage analysis of the source code to be performed based on the first report and to generate refactored and rewritten code, and may perform a third stage analysis of the database to generate a second report. The device may cause a fourth stage analysis of the database to be performed and to generate a refactored and rewritten database, and may perform the first stage analysis of the refactored and rewritten code and the third stage analysis of the refactored and rewritten database to generate a final report. The device may generate a migration strategy based on the final report and may perform actions based on the migration strategy.

Memory sub-system event log management

A system includes a memory device and a processing device coupled to the memory device. The memory processing device can perform operations including receiving data indicative of occurrence of a plurality of events. The processing device can perform operations including determining an event log type for each of the plurality of events. The processing device can perform operations including storing an identifier associated with each of the determined event log types. The processing device can perform operations including updating a counter value associated with each identifier in response to occurrence of an event associated with the respective identifier.