RELAY DEVICE

A relay device includes a switch for switching a combination of an input for receiving traffic data and an output for sending the traffic data; a congestion information processing section for obtaining congestion information indicating a degree of congestion of each of a plurality of traffics from an adjacent relay device which handles the plurality of traffics commonly with the relay device, and congestion information of each traffic in the relay device; a congestion information comparison section for finding information on a congestion level which quantitatively indicates difficulty of flowing of each traffic based on the congestion information obtained from the adjacent relay device and the congestion information of the relay device; a transmission scheduling adjustment section for assigning a transmission band of a bus to each traffic based on the congestion level; and a switch assignment section for shifting the switch based on a result of the assignment. 1. A relay device for , in an integrated circuit including decentralized buses , connecting the plurality of buses , the relay device comprising:a switch for switching a combination of an input for receiving traffic data and an output for sending the traffic data;a congestion information processing section for obtaining congestion information indicating a degree of congestion of each of a plurality of traffics from an adjacent relay device which handles the plurality of traffics commonly with the relay device, and congestion information of each traffic in the relay device;a congestion information comparison section for finding information on a congestion level which quantitatively indicates difficulty of flowing of each traffic on a transmission route based on the congestion information obtained from the adjacent relay device and the congestion information of the relay device;a transmission scheduling adjustment section for assigning a transmission band of the bus to each traffic based on the congestion level ...

BUS CONTROL DEVICE

A bus controller includes: a data receiving section for receiving output status information from other bus controllers on transmission routes available; a route load detecting section for calculating uniformity of distribution index indicating the degree of non-uniformity in transmission flow rate between the routes based on the output status information; a routing section for determining transmission routes, of which the transmission flow rates have been adjusted by reference to the index; a packet assembling section for generating a packet; a data output section for outputting the packet through one of output ports; a header analyzing section for determining which output port is connected to a transmission route chosen by reference to information about the packet receiving end; and a data output section for outputting the packet through the output port.

BUS SYSTEM AND ROUTER

In an NoC bus system, data is transmitted between first and second nodes through a router. The data includes performance-ensuring data which guarantees throughput and/or a permitted time delay. The first node generates packets, each including the data to be transmitted and classification information that indicates the class of that data to be determined according to its required performance, and controls transmission of the packets. The router includes a buffer section configured to store the received packets separately after having classified the packets according to their required performance by reference to the classification information, and a relay controller configured to control transmission of the packets stored in the buffer section at a transmission rate which is equal to or higher than the sum of transmission rates to be guaranteed for every first node associated with the classification information by reference to each piece of the classification information. 1. A bus system for use in a semiconductor circuit to transmit data between a first node and at least one second node through a network of buses and at least one router which is arranged on any of the buses ,the data to be transmitted including performance-ensuring data which guarantees at least one of throughput and a permitted time delay,wherein the first node includes:a packet generator configured to generate a plurality of packets, each of which includes the data to be transmitted and classification information that indicates the class of the data to be transmitted to be determined according to its required performance; anda transmission controller configured to control transmission of the packets, andthe at least one router includes:a buffer section configured to store the received packets separately after having classified the packets according to their required performance by reference to the classification information; anda relay controller configured to control transmission of the packets ...

INTERFACE APPARATUS AND MEMORY BUS SYSTEM

An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order. 1. An interface apparatus which connects together a memory controller that is connected to a memory on an integrated circuit and a bus network that has been formed on the integrated circuit ,wherein the memory controller includes: an arbitrator which provides arbitration in the order of processing of a plurality of request data; and a transmitter which transmits respective response data that have been output from the memory in response to those request data to the interface apparatus, andthe interface apparatus comprises:a de-packetizing processor which performs de-packetize processing on each of the request packets that have been received from the bus network and which extracts and outputs a request header and request data from each said request packet;a header generator which receives, in a first order, the plurality of request headers that the de-packetizing processor has output, sequentially generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order;a packetizing processor which generates response packets based on the response data that has been output from the memory in response to the request data and the response headers that are stored in the header generator and which transmits the response packets to the bus network; anda header order controller which controls the header generator so that if the arbitrator has ...

CONTROLLER

This controller is used in a system in which initiators and targets are connected via distributed buses to control transmission timing of an access request received from the initiators. The controller stores intermittent information including information about an intermittent period in which interference between packets can be restricted and bus operating frequency information indicating a bus operating frequency at which real-time performance is guaranteed for each initiator and which has been generated based on system configuration information and flow configuration information indicating, on a flow basis, a specification required for each initiator to access the target. The controller includes a clock generator; communications circuitry; and transmission interval setting circuitry which sets a time to send transmission permission responsive to a transmission request based on the intermittent period, a time when the transmission request is detected, and a previous transmission time. 1. A controller for use in a system in which initiators and targets are connected together via distributed buses to control transmission timing of an access request that has been received from any of the initiators through the buses , the controller comprising:an intermittent information storage configured to store intermittent period information that has been generated based on system configuration information about the system's configuration and flow configuration information indicating, on a flow basis, a specification required for each said initiator to access one of the targets;communications circuitry configured to obtain a clock signal to be driven at a bus operating frequency that guarantees real-time performance for each said initiator and that has been generated based on the system configuration information and the flow configuration information, configured to packetize data supplied from the initiator, configured to send a packet to a router and configured to record a ...

CONTROLLER

A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus.

BUS CONTROL DEVICE, RELAY DEVICE, AND BUS SYSTEM

A bus control device () includes a storage () that stores a transmission order of data pieces transmitted from a first node () to each second node (); a sorter () that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer () that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller () that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage. 1. A bus control device provided in a bus system in which a first node , a plurality of second nodes and a plurality of relay devices are connected by a packet-exchange-system bus configured on an integrated circuit , the bus control device being provided on a transmission path for data pieces to be transmitted and received between the first node and each of the plurality of second nodes , the bus control device comprising:an order storage that stores a transmission order of data pieces transmitted from the first node to each of the second nodes;a sorter that receives data pieces transferred from each of the second nodes toward the first node and refers to a predefined sorting rule to determine a sorting destination of each of the data pieces;a buffer that stores the sorted data pieces in the state where the sorted data pieces are classified by the second node as a transmission source of each of the data pieces; anda connection controller that refers to change permission/rejection information indicating whether or not the first node permits the transmission order of data pieces included in a transaction on the ...

BUS SYSTEM AND COMPUTER PROGRAM

A bus system () for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device () arranged on the bus. The bus system () includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (), information specifying a priority of transmission. The relay device () converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device () stores packets in a buffer () based on the priority. 1. A bus system for a semiconductor circuit , in which data is transmitted on a networked bus between a first node and at least one second node via a relay device arranged on the bus , wherein:the bus system includes a first bus of a relatively low delay and a second bus of a relatively high delay; a first buffer for storing data; and', 'a packet generator for generating a plurality of packets by attaching, to the data stored in the first buffer, information specifying a priority of transmission at the relay device, which is determined based on a transmission delay of a high-delay bus of a relatively large transmission delay; and, 'the first node includes a priority converter for converting a priority of each of the plurality of packets based on a predetermined priority conversion rule,', 'a buffer allocator for allocating a buffer of a destination relay device to which the packet is to be sent, based on the priority;', 'a sending controller for sending packets in a descending order of the priority; and', 'a second buffer for storing packets based on the priority; and, 'the relay device includeswherein, the buffer allocator allocates a buffer of a destination relay device to which the packet ...

BUS CONTROLLER AND CONTROL UNIT THAT OUTPUTS INSTRUCTION TO THE BUS CONTROLLER

A bus controller is arranged on a plurality of network communication buses that connect together a plurality of bus masters, each sending out a packet, and at least one node, to which the packet is sent from each said bus master, in order to control the transmission route of a packet that is flowing through the plurality of communication buses. The bus controller includes: a route diagram manager configured to manage a plurality of transmission routes and their respective transmission statuses; a parameter generator configured to generate either a parameter that conforms to a predetermined probability distribution or a parameter that follows a predefined rule; a processor configured to select one of the plurality of transmission routes based on the respective transmission statuses of the transmission routes and the parameter; and a relay configured to perform relay processing on the packet that is flowing through the communication bus. 1. A bus controller which is arranged on a plurality of network communication buses that connect together a plurality of bus masters , each sending out a packet , and at least one node , to which the packet is sent from each said bus master , in order to control the transmission route of a packet that is flowing through the plurality of communication buses , the bus controller comprising:a route diagram manager configured to manage a plurality of transmission routes leading from the respective bus masters to the at least one node and their respective transmission statuses;a parameter generator configured to generate either a parameter that conforms to a predetermined probability distribution or a parameter that follows a predefined rule;a processor configured to determine the transmission routes leading from the respective bus masters to the at least one node based on the respective transmission statuses of the transmission routes and the parameter so that the packets sent out from the bus masters are distributed over the plurality of ...

ROUTER, METHOD FOR CONTROLLING THE ROUTER, AND COMPUTER PROGRAM

An exemplary router is provided for an integrated circuit that has distributed buses and is arranged on a transmission route that leads from a transmission node to a reception node on the distributed buses to relay data. The distributed buses include first and second routes, each leading from the router to the reception node. The router includes a notifying section which sends a data transfer permission request to a second router on the first route and a third router on the second route and which determines whether or not the request is approved before a predetermined standby period passes to see if there is any abnormality in the first and second routes.

ROUTER, METHOD FOR CONTROLLING ROUTER, AND COMPUTER PROGRAM

In a bus system including a bus master, a first bus, and a second bus to connect them together, this router is arranged on the second bus to relay packets. The bus master outputs packets including information about at least one of (N+1) predetermined types of quality requirements. The second bus transmits packets designating at most N types of quality requirements. An exemplary router controls sending of the packets, with respect to at most N types of buffers that classify and store the packets by reference to the quality requirement type information and the packets stored in the buffers, so that the packets are sent in the descending order of their level of the quality requirement. The router controls sending schedule of the traffic flows by sensing a difference between the (N+1) different types of quality requirements. 1. A router to be provided for a bus system in order to relay packets , the bus system comprising: at least one bus master; a first bus; and a second bus which connects the at least one bus master and the first bus together and on which the router is arranged ,wherein the at least one bus master outputs packets including information about at least one of (N+1) predetermined types of quality requirements,the second bus transmits packets designating at most N types of quality requirements,the router comprises:an input port configured to receive the packets including the information about the quality requirements;a buffer section including at most N different types of buffers to classify and store the packets by reference to the information about the types of quality requirements which is included in the packets received;a buffer allocating section configured to determine, according to the type of the given quality requirement, in which of a destination router's buffers of the at most N different types the packets need to be stored if a bus type changes at the destination router; anda sending control section configured to control sending the packets by ...

ROUTER

The router is used to relay a packet to be transmitted from one node to another in an integrated circuit that has distributed buses according to a packet exchange method. The router includes: a plurality of buffers, each of which configured to store packets with information indicating their transmission node; a classifying section configured to classify the buffers that store the packets into a number of groups according to the transmission nodes of the packets; a selecting section configured to select at least one of the buffers of each group; and an output port configured to sequentially output the packets that are stored in the selected buffer. 1. A router which relays a packet to be transmitted from one node to another in an integrated circuit that has distributed buses according to a packet exchange method , the router comprising:a plurality of buffers, each of which configured to store packets with information indicating their transmission node;a classifying section configured to classify the buffers that store the packets into a number of groups according to the transmission nodes of the packets;a selecting section configured to select at least one of the buffers of each said group; andan output port configured to sequentially output the packets that are stored in the selected buffer.2. The router of claim 1 , wherein time information is added to the packet claim 1 , andwherein if two or more buffers belong to any of the groups of buffers classified, the selecting section selects, by reference to the time information of the packets that are stored in the respective buffers, one of the two or more buffers as a buffer with the top priority, andwherein if only one buffer belongs to any of the groups of buffers classified, then the selecting section selects the only one buffer as a buffer with the top priority.3. The router of claim 2 , wherein the output port outputs the respective packets that are stored in the buffer with the top priority in each said group in ...

BUS SYSTEM FOR SEMICONDUCTOR CIRCUIT

An exemplary semiconductor circuit bus system includes: a first bus comprised of distributed buses and having a first transfer rate; a second bus with a second transfer rate higher than the first transfer rate; a transmission node; a bus interface (IF) to connect the transmission node to the first bus; a router which connects the first and second buses; and a reception node connected to the second bus. The bus IF controls the flow rate of data flowing through the transmission routes of the first bus by reference to information about the amounts of transmissible data of the transmission routes. The router allocates the amounts of transmissible data to the transmission routes of the first bus and provides information about the amounts of transmissible data of the transmission routes for the bus IF and also controls the flow rate of the data flowing through the second bus. 1. A bus system for a semiconductor circuit , the system comprising:a first bus which has a first transfer rate;a second bus which has a second transfer rate that is higher than the first transfer rate;a first node which transmits data;a bus interface which connects the first node to the first bus;a router which connects the first and second buses together; anda second node which is connected to the second bus and which receives the data,wherein the first bus is comprised of distributed buses which have multiple transmission routes leading from the bus interface to the router,the router includes:an allocator which allocates, in accordance with a predetermined reference, the amounts of transmissible data to the respective transmission routes of the first bus and which provides information about the amounts of transmissible data of the respective transmission routes for the bus interface;a router processor which receives the data flowing through the respective transmission routes of the first bus and transfers the data to the second bus; anda second controller which controls the flow rate of the data ...

BUS CONTROL DEVICE, RELAY DEVICE, AND BUS SYSTEM

A bus control device ( 401 a ) includes a storage ( 408 ) that stores a transmission order of data pieces transmitted from a first node ( 402 ) to each second node ( 403 ); a sorter ( 413 ) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer ( 409 ) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller ( 410 ) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.

SEMICONDUCTOR SYSTEM, RELAY APPARATUS, AND CHIP CIRCUIT

Highly efficient and low latency network transmission in consideration of a difference in the traffic characteristic and a memory access load which changes moment by moment is realized. A relay device transmits data on a networked communication bus between a bus master and a memory. The relay device includes a delay time processor for obtaining information on processing delay time in other relay devices located on a plurality of transmission routes on which the data is transmitted; and a low latency route selector for selecting a memory and one of transmission routes to the memory, among the plurality of transmission routes, based on obtained information on the processing delay time regarding the plurality of transmission routes.

BUS INTERFACE APPARATUS, ROUTER, AND BUS SYSTEM INCLUDING THEM

In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.

ROUTER, METHOD FOR CONTROLLING ROUTER, AND PROGRAM

A router includes a buffer selection section for receiving a flit from an adjacent router and determining whether to store the flit on an input buffer or to store the flit on a bypass buffer. The buffer selection section executes at least one of a first control of, when a bypass process was performed, changing at least one of a transmission path and a transmission flow rate of data based on a transmission state of the router; and a second control of, when a bypass control section did not execute the bypass process, changing at least one of a transmission path and a transmission flow rate of data based on a transmission state of another first router at which data not subjected to the bypass process and data subjected to the bypass process by another second router are joined together.

COMMUNICATION DEVICE, ROUTER HAVING COMMUNICATION DEVICE, BUS SYSTEM, AND CIRCUIT BOARD OF SEMICONDUCTOR CIRCUIT HAVING BUS SYSTEM

A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value. 1. A communication device for use in a bus system of a semiconductor circuit having a sending node and a receiving node and including a bus over which data is transmitted by a packet switching scheme , the communication device comprising:a receiving terminal which receives one or more packets via a bus;a storage device which stores a rule in which a plurality of conditions regarding a bus system operation environment and a plurality of error tolerance schemes are respectively associated with each other, and information regarding a path length;an error processor which determines one error tolerance scheme from among the plurality of error tolerance schemes by referring to the rule based on a given one of the conditions regarding the bus system operation environment so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; anda sending terminal which sends at least one packet including the error tolerance information and the data to the bus,wherein the plurality of conditions regarding the bus ...

ROUTER, METHOD FOR CONTROLLING ROUTER, AND PROGRAM

An router includes: a plurality of data storage sections configured to store input data; and an arbiter configured to compare the availability of at least one of the plurality of data storage sections with respect to data that is stored in that data storage section and that shares at least a part of a transmission path to the availability of another data storage section in an adjacent router with respect to that data that also shares at least that part of the transmission path, thereby determining, based on a result of the comparison, whether or not to output that data. 1. A router for use in a data transfer system that includes a first node from which data is transmitted , a second node at which the data that has been transmitted from the first node is received , and a plurality of routers that relay the data to be transferred between the first and second nodes through a bus , the router comprising:a plurality of data storage sections configured to store input data; andan arbiter configured to compare the availability of at least one of the plurality of data storage sections with respect to data that is stored in that data storage section and that shares at least a part of a transmission path to the availability of another data storage section in an adjacent router with respect to that data that also shares at least that part of the transmission path, thereby determining, based on a result of the comparison, whether or not to output that data.2. The router of claim 1 , wherein the destination of that data is the adjacent router.3. The router of claim 1 , wherein the arbiter is configured to compare the availability of the data storage section of its own router with respect to data that has the same destination address and/or the same source address to the availability of the data storage section in the adjacent router claim 1 , thereby determining claim 1 , based on a result of the comparison claim 1 , whether or not to output that data.4. The router of claim 1 , ...

INTERFACE APPARATUS AND MEMORY BUS SYSTEM

An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header. 1. An interface apparatus which connects together an initiator that is arranged on an integrated circuit and a bus network that has been formed on the integrated circuit ,wherein the bus network is a packet exchange type network, and is designed so that if request data specifying a deadline time has been submitted by the initiator for a node on the bus network, response data to be issued by the node in response to the request data is received by the initiator by the deadline time, andthe interface apparatus comprises:a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted by the initiator, thereby generating corrected deadline time information;a header generator which generates a packet header that stores the corrected deadline time information; anda packetizing processor which generates a request packet based on the request data and the packet header.2. The interface apparatus of claim 1 , wherein if the initiator has submitted a plurality of request data with the same deadline time specified claim 1 , thenthe correcting circuit corrects the deadline time of each said ...

ROUTER, METHOD FOR CONTROLLING ROUTER, AND PROGRAM

A router includes an input section configured to receive data, a buffer section including a plurality of data storage sections and configured to store the data received by the input section, and an output section configured to output the data stored on the buffer section. The router also includes an allocation processing section configured to determine whether or not to store the data on a pre-secured specific data storage section among the plurality of data storage sections, or whether or not to store the data on a pre-secured specific data storage section among a plurality of data storage sections in a buffer section of another router which is an output destination, the determination being made based on information representing burstiness of the data received by the input section. 1. A router usable in a data transfer system which includes a first node for transmitting data , a second node for receiving the data transmitted from the first node , and a plurality of routers for routing the data transferred between the first node and the second node via a bus; the router comprising:an input section configured to receive an input of data;a buffer section including a plurality of data storage sections configured to store the data received by the input section;an output section configured to output the data stored on the buffer section; andan allocation processing section configured to determine whether or not to store the data on a pre-secured specific data storage section among the plurality of data storage sections, or whether or not to store the data on a pre-secured specific data storage section among a plurality of data storage sections in a buffer section of another router which is an output destination, the determination being made based on information representing burstiness of the data received by the input section.2. The router of claim 1 , wherein the information representing burstiness is at least one of a transfer amount per unit time claim 1 , a ...

ROUTER AND CHIP CIRCUIT

Routers in a data transfer system relay data between the first node and each of the second nodes. A router includes a load value processing section and an aggregation decision section. The load value processing section obtains information about a load value of another router connected to a communications bus. The load value is a time delay caused by that another router and/or the throughput of that router. The aggregation decision section chooses one of the second nodes at which the data is to be received, and determines a transmission path between the second node chosen and the first node in accordance with information about the load value obtained from each router and information determined during a design process about the number of stages of routers from the first node through each said second node and/or the length of data to be transferred.

RELAY DEVICE

A relay device includes: an input buffer for receiving data units, each of which includes a header, to which multiple pieces of destination information have been added, and data associated with the header; multiple virtual channels for storing data units, each of the multiple virtual channels storing a data unit in accordance with the destination information; a destination comparing section for determining the order of allocation of virtual channels at a relay device on the receiving end with respect to the data units that are stored on the multiple virtual channels by seeing if their destinations are the same; and an output section for outputting the stored data units preferentially through one of the virtual channels that has already allocated at the relay device on the receiving end. 1. A relay device comprising:an input buffer for receiving data units, each of which includes a header, to which multiple pieces of destination information have been added, and data associated with the header;multiple virtual channels for storing data units, each of the multiple virtual channels storing a data unit in accordance with the destination information;a destination comparing section for determining the order of allocation of virtual channels at a relay device on the receiving end with respect to the data units that are stored on the multiple virtual channels by seeing if their destinations are the same; andan output section for outputting the stored data units preferentially through one of the virtual channels that has already allocated at the relay device on the receiving end.2. The relay device of claim 1 , wherein the destination comparing section sorts the data units by the destination and determines the order of allocation so that if any data is going to be sent to a destination to which no virtual channel has been allocated yet at the relay device on the receiving end claim 1 , some virtual channel is allocated to that data preferentially at the relay device on the ...

Bus controller, bus control system and network interface

In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.

Access controller, router, access controlling method, and computer program

The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a network of buses. The access controller includes: a buffer which receives the data that have been provided by the first nodes with mutually different required qualities and destinations, classifies the data according to their destinations and required qualities, and stores the classified data separately; an inter-class arbitrator which sequentially selects one of the required qualities of the data after another in the order of their severity; an inter-destination arbitrator which selects the destinations of the data to be transmitted and gets the transmission quantities of the data distributed among the destinations; and a transmission controller which controls transmission of the data based on the required qualities selected by the inter-class arbitrator and the destinations selected by the inter-destination arbitrator.

Relay device, method for controlling relay device, and computer program

To transmit traffic flows on which different types of quality requirements are imposed through an NoC (network on chip) while ensuring their quality, the present disclosure provides a router which does not need dedicated buffers to store those traffic flows on a quality requirement basis. In a bus system including a bus master, a first bus, and a second bus to connect them together, this router is arranged on the second bus to relay packets. The bus master outputs packets including information about at least one of (N + 1) predetermined types of quality requirements. The second bus transmits packets designating at most N types of quality requirements. The router controls sending of the packets, with respect to at most N types of buffers that classify and store the packets by reference to the quality requirement type information and the packets stored in the buffers, so that the packets are sent in the descending order of their level of the quality requirement. The router controls sending schedule of the traffic flows by sensing a difference between the (N + 1) different types of quality requirements.

Router, method for controlling router, and program

A router includes a buffer selection section for receiving a flit from an adjacent router and determining whether to store the flit on an input buffer or to store the flit on a bypass buffer. The buffer selection section executes at least one of a first control of, when a bypass process was performed, changing at least one of a transmission path and a transmission flow rate of data based on a transmission state of the router; and a second control of, when a bypass control section did not execute the bypass process, changing at least one of a transmission path and a transmission flow rate of data based on a transmission state of another first router at which data not subjected to the bypass process and data subjected to the bypass process by another second router are joined together.

Data transmission/reception system, terminal, relay device, and data transmission method

The terminal includes: the transmitting and receiving unit (908) transmitting and receiving the observation packet for observing the transmission quality and data; the transmission quality managing unit (906) (i) exchanging the observation packet with another terminal via the transmitting and receiving unit (908), (ii) observing a loss rate of the data between the terminal and the other terminal and writing to the observation packet the degraded state information indicating the loss rate in the case where the terminal receives the data, and (iii) subtracting the congested state information from the degraded state information included in the observation packet collected from the other terminal in order to calculate a transmission error rate of the data in the terminal and the relay device in the case where the terminal transmits the data; and the error correction code processing unit (905) determining a forward error correction capability based on the transmission error rate calculated by the transmission quality managing unit (906) and assigning to the data to be transmitted the forward error correction code according to the forward error correction capability.

Best path selecting device, best path selecting method, and program

A path selecting device of a bus master ( 300 ) includes a path information generating unit ( 302 ) generating path information indicating paths from the bus master ( 300 ) to a bus master ( 400 ), and including a path malfunction predicting unit ( 303 ) predicting a malfunction on each of NoC routers, using a number of flows as a scale for an occurrence of a malfunction on the respective NoC router, at least one of which is determined for each path indicated by the path information. The bus master ( 300 ) also includes a bypass path selecting unit ( 304 ) selecting, when the malfunction is predicted on an NoC router that is a candidate for monitoring, a path that should be used for transmitting the data from the bus master ( 300 ) to the bus master ( 400 ), from the paths indicated by the path information except the path including the NoC router on which the malfunction is predicted.

Printer

(57)【要約】 【課題】 ホスト装置から指定されたアウトラインフォ ントを保有していない場合でも、高速で印刷を行うこと ができるプリンタ装置を提供することにある。 【解決手段】 ホスト装置からアウトラインフォントを 指定して印刷要求を受けた際、指定されたアウトライン フォントがフォントメモリ107 に格納されているか否か を調べ、格納されていない場合には、フォントメモリ10 7 に格納されている内蔵フォントを使用して印刷を行う ように構成した。また、指定されたアウトラインフォン トと内蔵フォントとの関連付けを自動的に判断し、内蔵 フォントの中でホスト装置により指定されたアウトライ ンフォントに最も似ているアウトラインフォントを使用 して印刷を行うようにした。また、指定されたフォント 名称と一致する名称の内蔵フォントを使用したり、指定 されたフォントと文字の太さに関する形態の一致する内 蔵フォントを使用したりするようにも構成した。

Router, method for controlling router, and computer program

In a bus system including a bus master, a first bus, and a second bus to connect them together, this router is arranged on the second bus to relay packets. The bus master outputs packets including information about at least one of (N+1) predetermined types of quality requirements. The second bus transmits packets designating at most N types of quality requirements. An exemplary router controls sending of the packets, with respect to at most N types of buffers that classify and store the packets by reference to the quality requirement type information and the packets stored in the buffers, so that the packets are sent in the descending order of their level of the quality requirement. The router controls sending schedule of the traffic flows by sensing a difference between the (N+1) different types of quality requirements.

Path control device, path control method, and path control program

A path control device included in a terminal device ( 300 ), which includes a path information generating unit ( 302 ) which generates path information indicating paths from a terminal ( 300 ) to a terminal ( 400 ), a path malfunction predicting unit ( 303 ) which predicts a malfunction on each of the relays, using the number of flows as a malfunction occurrence likelihood value, at least one of the relays that is a candidate for monitoring is determined for each path, and a bypass path selecting unit ( 304 ) which selects, when the malfunction is predicted on the at least one relay, a path that should be used for transmitting the data from the terminal ( 300 ) to the terminal ( 400 ), from the paths except the path including the relay on which the malfunction is predicted.

Wireless relay apparatus and wireless relay method

Path control device, path control method, and path control program

A path control device included in a terminal device ( 300 ), which includes a path information generating unit ( 302 ) which generates path information indicating paths from a terminal ( 300 ) to a terminal ( 400 ), a path malfunction predicting unit ( 303 ) which predicts a malfunction on each of the relays, using the number of flows as a malfunction occurrence likelihood value, at least one of the relays that is a candidate for monitoring is determined for each path, and a bypass path selecting unit ( 304 ) which selects, when the malfunction is predicted on the at least one relay, a path that should be used for transmitting the data from the terminal ( 300 ) to the terminal ( 400 ), from the paths except the path including the relay on which the malfunction is predicted.

プリンタ及び該プリンタを備えた画像処理装置

(57)【要約】 【課題】 プリンタの制御基板の交換時に、搭載された 不揮発性メモリの付替えをせずにメモリ保持情報を基板 の付替後に復元できるようにしたプリンタを提供する。 【解決手段】 操作パネル（不図示）から入力操作によ り発生し、プリンタ制御基板上のパネルＩ／Ｆ７を介し て送り込まれた、各印刷ジョブの固有情報や本機に固有 の動作関連情報がＣＰＵ１により不揮発性メモリ６に書 込まれる。その後、書込後の不揮発性メモリ６の記憶デ ータ内容がエンジンＩ／Ｆ５を介して、エンジン制御基 板（不図示）上の不揮発性メモリに書き込まれる。書込 後にエンジン制御基板上の不揮発性メモリの全データ内 容が、エンジンＩ／Ｆ５を介して受け取ったプリンタ制 御基板の不揮発性メモリ６に書き込まれ、両制御基板で 相互にデータを保存し、バックアップが完了する。

情報処理装置および方法

【課題】 装置通電時における電源系統の突入電流のピークを低減させる情報処理装置および方法を提供すること。【解決手段】 各装置の通電するタイミングを変化させることによって、装置が含まれる電源系統の突入電流のピークを低減させる情報処理装置であって、電力の供給が遮断されたことを判定する異常遮断判定部４０４と、異常遮断判定部４０４によって電力の供給が遮断されたと判定された場合に、該遮断された情報を記憶する遮断情報記憶部４０５と、電力の供給が復帰した場合に設定された待機時間が経過した後に、装置に通電させるメイン電源起動部４０３とを含む。【選択図】 図４

画像形成装置

【課題】発電及び蓄電した電力の利用効率を向上させる。【解決手段】画像形成装置は、複数の熱源の熱を集熱する集熱手段と、放熱手段と、集熱手段と放熱手段との温度差に応じて電力を発生する熱電変換手段と、電力を蓄電する蓄電手段１０８と、を有する。ヒートパイプにより伝熱された熱は、高熱伝導シート２１１により集熱され、ゼーベック素子２１２に伝熱される。ゼーベック素子の下方の面が高熱伝導シートと接触し、伝熱が行われる。ゼーベック素子の上方の面はヒートシンク２１３に接触し、両者の温度差により熱電変換が行われる。【選択図】図２

錠剤及びその製造方法

【課題】（Ａ）アセチルサリチル酸と、（Ｂ）アセトアミノフェンとを同一層内に含有する錠剤において、錠剤の側面にキズが入るバインディング等の打錠障害がなく、十分な錠剤硬度を有する錠剤を提供する。【解決手段】（Ａ）アセチルサリチル酸、（Ｂ）アセトアミノフェン、（Ｃ）乾燥水酸化アルミニウムゲル、合成ヒドロタルサイト、メタケイ酸アルミン酸マグネシウム及び酸化マグネシウムから選ばれる１種以上、及び（Ｄ）フマル酸ステアリルナトリウムを同一層に含有する錠剤。【選択図】なし

画像処理装置、画像処理装置の制御方法、制御プログラム及び記録媒体

【課題】ディスク記憶装置の搭載された情報処理装置において、ディスク記憶装置の不具合によって装置が使用不可能となることを防ぐこと。 【解決手段】ＨＤＤ１０９を接続して使用可能な画像処理装置１であって、前記画像処理装置の起動処理を制御する主制御部１１１と、ＨＤＤ１０９を制御するストレージコントローラ１１５を有し、ストレージコントローラ１１５は、画像処理装置１の起動処理においてＨＤＤ１０９に記憶されている情報を読み出し、当該読み出しの速度を測定し、測定結果に基づいてＨＤＤ１０９に不具合が発生していることを判断し、不具合が発生している場合にＨＤＤ１０９の記憶領域を修復することを特徴とする。 【選択図】図１

画像処理装置

【課題】 ＨＤＤを駆動する際に発生する無駄な消費電力を低減することができる画像形成装置を提供することを目的とする。 【解決手段】 複数のＨＤＤ１２を備え、画像データをＨＤＤ１２に蓄積可能な画像処理装置であって、ＨＤＤ１２ごとに電源のオン／オフ制御を行うＨＤＤ電源制御部１１を備え、ＨＤＤ電源制御部１１は処理に応じて電源をオンにするＨＤＤ１２の個数とタイミングを制御するようにした。 【選択図】 図１

電子機器

【課題】 基板の使用状況を確認でき、再度リサイクル使用可能な基板情報を提供することが可能な電子機器を提供する。 【解決手段】 第１の不揮発性記憶媒体７を有する基板１０と、第２の不揮発性記憶媒体１３を有し基板１０に電源を供給する電源供給ユニット１１とを備え、第１の不揮発性記憶媒体７に予め記憶された基板１０の消費電流の情報と、第２の不揮発性記憶媒体１３に予め記憶された電源供給ユニット１１が供給可能な電流の情報を読み取って比較し、その結果どちらか一方の値が大きい時、第１の不揮発性記憶媒体７に予め記憶された基板で使用が許可された機能の情報を書き換える場合に、第１の不揮発性記憶媒体７に書き換えの履歴を合わせて保持しておく制御を行う制御手段１を備えた。 【選択図】 図１

画像形成装置、その制御方法、プログラム、及び記録媒体

【課題】ディスク型記憶装置を搭載する画像形成装置において、画像データ領域としての使用が困難なディスク内周領域を効率的に利用するとともに、ディスク型記憶装置の不具合により画像処理装置が使用不可能となることを防止する。 【解決手段】ディスク型記憶装置から読み出されたデータの転送速度を測定する転送速度測定手段と、転送速度測定手段により測定された転送速度に基づいて異常状態の記憶領域を検出し、ディスク型記憶装置の異常内容を解析する異常内容解析手段と、異常内容解析手段により一部記憶領域について正常なデータ書き込みが行われなかったリードデータ異常と解析されたとき、ディスク型記憶装置の未使用の記憶領域に異常状態の記憶領域の修復用データを保存する修復用データ保存手段と、異常内容解析手段により検出されたディスク型記憶装置の異常状態の記憶領域を修復する記憶領域修復手段と、を有する。 【選択図】図１

クロック信号分配回路、クロック信号分配方法および印刷装置

(57)【要約】 【課題】 プリント配線基板を増設可能な電子機器にお いて、増設用プリント配線基板を未装着であるコネクタ 端子へのクロック信号の分配を抑止し、電磁妨害波の放 射を低減する。 【解決手段】 電子機器のコネクタへのプリント配線基 板の装着の有無を検知し、装着検出信号を生成するプリ ント配線基板装着検知部１０７を有し、該装着検出信号 に基づいて、前記コネクタへのクロック信号の分配を制 御するクロック信号分配制御部１０８をクロック信号供 給回路２１０に備える。

スポット溶接の電極研磨用カッター

(57)【要約】 【課題】 構造簡単にしてエッジが電極の非切削面に対 する食い込みが良く、製作時の切削加工の作業性を向上 させて製作コストの低減を図ることができると共にエッ ジの部分欠損のおそれの少ない新規な構造のスポット溶 接の電極研磨用カッターを提供する。 【解決手段】 基盤部２の表面又は表裏両面に、電極の 適正な先端形状に対応する凹部３、３を形成し、該凹部 ３、３の中心点Ｐに至る９０度以内の２本の半径線内を 切欠４してその両側の稜線をエッジ５、５となすと共に いずれか一方のエッジ５における中心点Ｐ側端に小切欠 ６を設けた。

プリンタ装置

(57)【要約】 【課題】 画像圧縮方式を用い圧縮をおこなった画像デ ータがプリンタ装置のコントローラ内のメモリに収まり きらない際、ユーザーがそのことに対し新たな操作をす る必要がなく、劣化のない画像を出力するプリンタ装置 を提供すること。 【解決手段】 所定ラインの画像データを圧縮してペー ジメモリに格納する（Ｓ１０）。圧縮データがページメ モリに収まる否か判断する（Ｓ１１）。画像データをメ モリに格納する時にメモリ容量が足りないためにエラー となった場合には現状で所定ライン毎にデータを伸張し て印刷する（Ｓ１４）。次に、画像データの容量を検知 （Ｓ１５）し、残りの画像データの再転送の転送方法を 指定（Ｓ１６）する。このため、次回の転送でエラーを 起こすことなく、効率の良い転送をする行うことができ る。

画像形成装置

【課題】電源電圧が低い場合であっても、現像バイアス等の複雑な制御をすることなく、かつ、印刷性能を低下させずに印刷を実行することができる画像形成装置を提供すること。【解決手段】電源の電圧を検出する電圧検出手段と、入力された画像に基づいて印刷データを生成し出力する印刷データ生成手段と、印刷データに基づきトナーを印刷媒体に転写し、電源により加熱される定着ヒータにより加熱して定着させることにより印刷を実行する印刷手段とを有し、印刷データ生成手段は、検出された電圧に応じて印刷データの印刷濃度を変更するよう、画像形成装置を構成する。【選択図】図１

振動装置、および振動装置を備える撮像ユニット

【課題】本開示は、透光体の視野を保ちつつ、透光体に付着した異物を透光体の外に排出することができる振動装置、および振動装置を備える撮像ユニットを提供する。【解決手段】本開示は、透光体の視野を保ちつつ、透光体に付着した異物を透光体の外に排出することができる振動装置、および当該振動装置を備える撮像ユニットである。振動装置１０は、保護カバー１１、第１筒状体１２、板バネ１３、第２筒状体１４、圧電素子１５、および振動板１６を備える。振動装置１０は、貫通方向の透光体の振動を所定の方向へ変位させる非平衡手段をさらに備える。【選択図】図１

プリンタ制御装置

(57)【要約】 【課題】 プリンタ制御基板の故障などによりプリンタ 制御基板を交換する際にも不揮発性メモリを交換するこ となく，利用者独自の情報を保持し，低コストおよび基 板交換作業の簡素化を図ること。 【解決手段】 プリンタを制御するプリンタ制御基板上 に，プリンタに対する機能設定条件および装置固有の情 報を書き込んでおく不揮発性メモリ１０６を搭載したプ リンタ制御装置において，不揮発性メモリ１０６に書き 込まれている情報を，プリンタ制御基板に接続されたバ ックアップ用メモリに書き込んでおく。

画像形成装置

(57)【要約】 【課題】 所定の圧縮方式を用いて画像データを圧縮し た場合に画像メモリに格納することができず、劣化した 画像を出力する場合には、安価な用紙に出力することが できる画像形成装置を提供する。 【解決手段】 、所定ライン毎の分割された画像データ はホストインタフェース３０４から入力され、圧縮器３ ０６によって所定の圧縮方式で圧縮され、ＲＡＭ３０３ に設定されたページメモリ３０８に格納される。ページ メモリ３０８に格納された圧縮データは伸長器３０７に よって伸長され、プリンタエンジンインタフェース３０ ５に送られた後、プリンタエンジンによって印字され る。エラー検知部３０９は、ホストインタフェース３０ ４を介して入力されるホスト装置からの画像データのデ ータ量をエラー検知部３０９で判断し、圧縮してもペー ジメモリ３０８に格納できないと判断した場合には、エ ンジンインタフェース３０５に予め設定された用紙を供 給し、その用紙に印字するように指示する。

Bus system and computer program

A bus system ( 100 ) for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device ( 250 ) arranged on the bus. The bus system ( 100 ) includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer ( 202 ), information specifying a priority of transmission. The relay device ( 250 ) converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device ( 250 ) stores packets in a buffer ( 252 ) based on the priority.

Bus control device, relay device, and bus system

A bus control device ( 401 a ) includes a storage ( 408 ) that stores a transmission order of data pieces transmitted from a first node ( 402 ) to each second node ( 403 ); a sorter ( 413 ) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer ( 409 ) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller ( 410 ) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.

Communication device, router having communication device, bus system, and circuit board of semiconductor circuit having bus system

A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value.

Interface apparatus and memory bus system

An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.

Bus controller, bus control system and network interface

In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.

Access controller, router, access controlling method, and computer program

The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a network of buses. The access controller includes: a buffer which receives the data that have been provided by the first nodes with mutually different required qualities and destinations, classifies the data according to their destinations and required qualities, and stores the classified data separately; an inter-class arbitrator which sequentially selects one of the required qualities of the data after another in the order of their severity; an inter-destination arbitrator which selects the destinations of the data to be transmitted and gets the transmission quantities of the data distributed among the destinations; and a transmission controller which controls transmission of the data based on the required qualities selected by the inter-class arbitrator and the destinations selected by the inter-destination arbitrator.

Bus system for semiconductor circuit

An exemplary semiconductor circuit bus system includes: a first bus comprised of distributed buses and having a first transfer rate; a second bus with a second transfer rate higher than the first transfer rate; a transmission node; a bus interface (IF) to connect the transmission node to the first bus; a router which connects the first and second buses; and a reception node connected to the second bus. The bus IF controls the flow rate of data flowing through the transmission routes of the first bus by reference to information about the amounts of transmissible data of the transmission routes. The router allocates the amounts of transmissible data to the transmission routes of the first bus and provides information about the amounts of transmissible data of the transmission routes for the bus IF and also controls the flow rate of the data flowing through the second bus.

Router, method for controlling router, and program

An router includes: a plurality of data storage sections configured to store input data; and an arbiter configured to compare the availability of at least one of the plurality of data storage sections with respect to data that is stored in that data storage section and that shares at least a part of a transmission path to the availability of another data storage section in an adjacent router with respect to that data that also shares at least that part of the transmission path, thereby determining, based on a result of the comparison, whether or not to output that data.