ONE-TIME PROGRAMMABLE READ-ONLY MEMORY

A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.

Semiconductor methods and structures

A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.

HIGH VOLTAGE TOLERANCE CIRCUIT

A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.

Methods of fabricating a micromechanical structure

Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

Memory array with one shared deep doped region

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

MEMORY ARRAY CAPABLE OF PERFORMING BYTE ERASE OPERATION

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible. 1: A memory array , comprising: [ a floating gate transistor having a first terminal, a second terminal and a floating gate;', 'a source transistor having a first terminal coupled to a source line, a second terminal coupled to the first terminal of the floating gate transistor, and a control terminal coupled to a word line; and', 'a bit transistor having a first terminal coupled to the second terminal of the floating gate transistor, a second terminal coupled to a bit line, and a control terminal coupled to the word line;, 'a floating gate module comprising, 'a control element having a body terminal coupled to a control line, a first terminal coupled to the body terminal, a second terminal coupled to the body terminal, and a control terminal coupled to the floating gate; and', 'an erase element having a first terminal coupled to an erase line, a second terminal coupled to the first terminal of the erase element, a body terminal coupled to the first terminal of the erase element, and a control terminal coupled to the floating gate;, 'a plurality of memory pages, each memory page comprising a plurality of memory bytes, each memory byte comprising a plurality of memory cells, and each memory cell comprisingwherein:memory bytes of a same column are coupled to a same erase line;memory bytes of different columns are coupled to ...

HIGH VOLTAGE SWITCH DEVICE

A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY

A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

High voltage switch device

A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

METHODS OF FABRICATING A MICROMECHANICAL STRUCTURE

Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

Resistive random-access memory cell and associated cell array structure

A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure.

MULTI-CELL PER BIT NONVOLATILE MEMORY UNIT

A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor. 1. A multi-cell per bit nonvolatile memory (NVM) unit , comprising:a semiconductor substrate comprising a first oxide define (OD) region, a second oxide define (OD) region, and a third oxide define (OD) region separated from one another by a trench isolation region, wherein the first, second and third OD regions are in parallel to one another and extend along a first direction, and wherein the first OD region is situated between the second OD region and the third OD region;serially connected single-poly floating gate transistors disposed on the first OD region;wherein each of the serially connected single-poly floating gate transistors comprises a first floating gate extension continuously extending toward the second OD region along a second direction and adjacent to an erase gate region disposed in the second OD region;wherein each of the serially connected storage cells comprises a second floating gate extension continuously extending toward the third OD region along the second direction and wherein the second floating gate extension is capacitively coupled to a control gate region in the third OD region.2. The multi-cell per bit NVM unit according to further comprising a select transistor disposed on the first OD region.3. The multi-cell per bit NVM unit according to further comprising a word ...

Near-memory computation system for analog computing

A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by performing computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

SEMICONDUCTOR STRUCTURES

A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate . A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.

Ink-channel wafer integrated with CMOS wafer for inkjet printhead and fabrication method thereof

An ink-ejection unit of an inkjet printhead integrates an ink-channel wafer onto a CMOS wafer with a heating element fabricated therein. A nozzle film with a nozzle orifice is formed on the backside of the CMOS wafer, which allows two-dimensional ink ejecting from the backside of the CMOS wafer.

Memory cell array of multi-time programmable non-volatile memory

A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.

MEMORY UNIT WITH VOLTAGE PASSING DEVICE

A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal. 1. A memory unit , comprising:a first voltage passing device configured to output voltages according to operations of the memory unit; and a first floating gate transistor having a first terminal configured to receive a first bit line signal, a second terminal, and a floating gate; and', 'a first capacitance element having a first terminal coupled to the first voltage passing device, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a body configured to receive a first control signal;, 'a first memory cell comprisingwherein:the first capacitance element and the first voltage passing device are disposed in a first N-well;the first terminal of the first capacitance element receives a first voltage outputted from the first voltage passing device during a program operation or an erase operation of the first memory cell and receives a second voltage outputted from the first voltage passing device during an inhibit operation of the first memory cell; andthe first voltage is greater than the second voltage.2. The memory unit of claim 1 , wherein the first voltage passing device ...

Process for wafer bonding

The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Memory unit with voltage passing device

A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal.

NONVOLATILE MEMORY STRUCTURE

A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor. 1. A nonvolatile memory structure , comprising:a semiconductor substrate of a first conductivity type having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row along a first direction, wherein the first, second, and third OD regions are separated from one another by an isolation region, and wherein the isolation region comprises a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region;a first select transistor on the first OD region, wherein the first select transistor comprises a select gate extending along a second direction;a floating gate transistor on the second OD region, wherein the floating gate transistor is serially coupled to the first select transistor, and wherein the floating gate transistor comprises a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions; anda ...

NON-VOLATILE MEMORY CELL COMPLIANT TO A NEAR-MEMORY COMPUTATION SYSTEM

A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.

NEAR-MEMORY COMPUTATION SYSTEM FOR ANALOG COMPUTING

A near-memory computation system includes a plurality of computation nodes. Each computation node receives a plurality of input signals and outputs a computing result signal. The computation node includes a plurality of non-volatile memory cells and a processing element. Each non-volatile memory cell stores a weighting value during a program operation and outputs a weighting signal according to the weighting value during a read operation. The processing element is coupled to the plurality of non-volatile memory cells. The processing element receives the plurality of input signals and generates the computing result signal by perform computations with the plurality of input signals and a plurality of weighting signals generated by the plurality of non-volatile memory cells. The plurality of non-volatile memory cells and the processing element are manufactured by different or the same processes.

Three dimensional structure formed by using an adhesive silicon wafer process

A method of making a MEMS device including providing a first substrate with an insulator layer thereon. A holder is attached to the insulator layer, and the first substrate is thinned. Thereafter, cavities are formed in the first substrate and the first substrate is flipped over and bonded to an integrated circuit wafer with the cavities facing the integrated circuit wafer. The holder is removed to provide a first substrate with cavities formed therein facing the integrated circuit wafer and an insulator layer overlying the first substrate.

Non-volatile memory cell compliant to a near memory computation system

A non-volatile memory cell includes a storage transistor having a first terminal, a second terminal, and a gate terminal. During a program operation, the first terminal of the storage transistor receives a data voltage according to a weighting to be stored in the non-volatile memory cell, the second terminal of the storage transistor is floating, and the gate terminal of the storage transistor is coupled to a program voltage. The program voltage is greater than the data voltage.

Semiconductor structures

A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.

High voltage tolerance circuit

A high voltage tolerance circuit includes a first transistor, a second transistor, a third transistor, and a latch-up device. The first transistor and the second transistor are controlled by a control signal. The gate of the third transistor is coupled to a ground through the first transistor. The gate of the third transistor is coupled to an I/O pad through the second transistor. The third transistor is coupled between a power supply and a node. The latch-up device is coupled between the node and the I/O pad.

ONE TIME PROGRAMMABLE READ ONLY MEMORY AND PROGRAMMING METHOD THEREOF

A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.

Micro-lens and micro-lens fabrication method

A method of manufacturing a micro-lens is disclosed. The method includes providing a convex photoresist surface, forming a lens mold on the convex photoresist surface, removing the lens mold from the convex photoresist surface, forming a micro-lens in the lens mold and removing the micro-lens from the lens mold.

Process For Wafer Bonding

The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Ink-channel wafer integrated with CMOS wafer for inkjet printhead and fabrication method thereof

An ink-ejection unit of an inkjet printhead integrates an ink-channel wafer onto a CMOS wafer with a heating element fabricated therein. A nozzle film with a nozzle orifice is formed on the backside of the CMOS wafer, which allows two-dimensional ink ejecting from the backside of the CMOS wafer.

Magnetoresistive random access memory for physically unclonable function technology and associated random code generating method

A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

Semiconductor methods and structures

A method and a structure are provided for preventing lift-off of a semiconductor monitor pattern from a substrate. A semiconductor structure and a semiconductor monitor structure are formed on a substrate. A material layer is formed covering the semiconductor monitor structure. A part of the semiconductor structure is removed without removing the semiconductor monitor structure, by using the material layer as an etch protection layer. A mask for the method is also provided. The mask includes a clear area and a dark area. The dark area prevents a semiconductor monitor structure from being subjected to exposure so as to form a material layer covering the semiconductor monitor structure and prevent removal of the semiconductor monitor structure from the substrate while a part of a semiconductor structure is removed.

Memory array capable of performing byte erase operation

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.

Memory array with one shared deep doped region

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.

Nonvolatile memory structure

A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.

Micro-lens micro-lens fabrication method

A method of manufacturing a micro-lens is disclosed. The method includes providing a convex photoresist surface, forming a lens mold on the convex photoresist surface, removing the lens mold from the convex photoresist surface, forming a micro-lens in the lens mold and removing the micro-lens from the lens mold.

End point detection method for forming a patterned silicon layer

Within a method for selectively etching a second silicon layer with respect to a first silicon layer upon which is formed the second silicon layer there is employed an etch detection layer interposed between a first region of the first silicon layer and the second silicon layer, but not a second region of the first silicon layer and the second silicon layer. The etch detection layer provides for enhanced endpoint detection when selectively etching the second silicon layer with respect to the first silicon layer.

RANDOM BIT CELL WITH NONVOLATILE MEMORY CELL

A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor. 1. A random bit cell comprising:a latch having a first terminal and a second terminal; and a first storage circuit coupled to the first terminal of the latch, the first storage circuit comprising a first floating gate transistor having a first terminal, a second terminal, and a floating gate;', 'a first control element having a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the first floating gate transistor;', 'a first erase element having a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the first floating gate transistor; and', 'a first read circuit coupled to a first bit line, a select gate line, and the floating gate of the first floating gate transistor., 'a first nonvolatile memory cell comprising2. The random bit cell of claim 1 , wherein the first terminal of the first floating gate transistor is coupled to the first terminal of the latch claim 1 , and the second terminal of the first floating gate transistor is floating.3. The random bit cell of claim 2 , wherein during a first stage of an enroll operation:the first bit line, the control line, and the erase line are at a first voltage (0V ...

Methods of fabricating a micromechanical structure

Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

Multi-cell per bit nonvolatile memory unit

A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.

HIGH VOLTAGE SWITCH DEVICE

A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure. 1. A switch device comprising:a P-type substrate;a first gate structure;a first N-well formed in the P-type substrate and partly under a first side of the first gate structure;a shallow trench isolation (STI) structure formed in the first N-well and under the first side of the first gate structure;a first P-well formed in the P-type substrate and under the first gate structure;a second gate structure;a first N-type doped region formed in the P-type substrate and between a second side of the first gate structure and a first side of the second gate structure;a second P-well formed in the P-type substrate and under the second gate structure; anda second N-type doped region formed in the second P-well and partly under the second gate structure.2. The switch device of claim 1 , further comprising a third N-type doped region formed in the first N-well without being covered by the first gate structure claim 1 , wherein a doping concentration of the third N-type doped region is greater than a doping concentration of the first N-well.3. The switch device of claim 1 , wherein the first N-well has a concentration gradient.4. The switch ...

MEMORY ARRAY WITH ONE SHARED DEEP DOPED REGION

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced. 1. A memory array comprising: [ a floating gate transistor, and configured to control the floating gate transistor according to a source line, a bit line and a word line, the floating gate transistor having a first terminal, a second terminal and a floating gate;', 'a source transistor having a first terminal coupled to the source line, a second terminal coupled to the first terminal of the floating gate transistor, and a control terminal coupled to the word line; and', 'a bit transistor having a first terminal coupled to the second terminal of the floating gate transistor, a second terminal coupled to the bit line, and a control terminal coupled to the word line;, 'a floating gate module comprising, 'a control element having a body terminal coupled to a control line, a first terminal coupled to the body terminal, a second terminal coupled to the body terminal, and a control terminal coupled to the floating gate; and', 'an erase element having a body terminal configured to receive a first voltage during a program operation and a program inhibit of the memory cell and receive a second voltage during an erase operation of the memory cell, a first terminal coupled to an erase line, a second terminal coupled to the first terminal of the erase element or being ...

ONE-TIME PROGRAMMABLE READ-ONLY MEMORY

A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.

High voltage switch device

A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

One time programmable read only memory and programming method thereof

A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.

Methods of fabricating a micromechanical structure

Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

Random bit cell with nonvolatile memory cell

A random bit cell includes a latch and a nonvolatile memory cell. The nonvolatile memory cell includes a storage circuit, a control element, an erase element, and a read circuit. The storage circuit is coupled to a first terminal of the latch. The storage circuit includes a floating gate transistor having a first terminal, a second terminal, and a floating gate. The control element has a first terminal coupled to a control line, and a control terminal coupled to the floating gate of the floating gate transistor. The erase element has a first terminal coupled to an erase line, and a control terminal coupled to the floating gate of the floating gate transistor. The read circuit is coupled to a bit line, a select gate line, and the floating gate of the floating gate transistor.

Method for operating one-time programmable read-only memory

A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

MEMORY ARRAY WITH ONE SHARED DEEP DOPED REGION

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced. 1. A memory array comprising: a floating gate module comprising a floating gate transistor, and configured to control the floating gate transistor according to a source line, a bit line and a word line, the floating gate transistor having a first terminal, a second terminal and a floating gate;', 'a control element having a body terminal coupled to a control line, a first terminal coupled to the body terminal, a second terminal coupled to the body terminal, and a control terminal coupled to the floating gate; and', 'an erase element having a body terminal configured to receive a first voltage during a program operation and a program inhibit of the memory cell and receive a second voltage during an erase operation of the memory cell, a first terminal coupled to an erase line, a second terminal coupled to the first terminal of the erase element or being floating, and a control terminal coupled to the floating gate;, 'a plurality of memory pages, each memory page comprising a plurality of memory cells, and each memory cell comprisingwherein:the floating gate module is disposed in a first well;the erase element is disposed in a second well;the control element is disposed in a third well;the first well, the second well and the third well are disposed in a deep doped ...

RESISTIVE RANDOM-ACCESS MEMORY CELL AND ASSOCIATED CELL ARRAY STRUCTURE

A resistive random-access memory cell includes a well region, a first doped region, a second doped region, a third doped region, a first gate structure, a second gate structure and a third gate structure. The first gate structure is formed over the surface of the well region between the first doped region and the second doped region. The second gate structure is formed over the second doped region. The third gate structure is formed over the surface of the well region between the second doped region and the third doped region. A first metal layer is connected with the first doped region and the third doped region. A second metal layer is connected with the conductive layer of the first gate structure and the conductive layer of the third gate structure. 1. A cell array structure comprising a first resistive random-access memory cell , the first resistive random-access memory cell comprising:a well region;a first doped region, a second doped region and a third doped region formed under a surface of the well region;a first gate structure formed over the surface of the well region between the first doped region and the second doped region, wherein the first gate structure comprises a stack structure with a first insulation layer and a first conductive layer;a second gate structure formed over the second doped region, wherein the second gate structure comprises a stack structure with a second insulation layer and a second conductive layer, and the second conductive layer is served as a first source line;a third gate structure formed over the surface of the well region between the second doped region and the third doped region, wherein the third gate structure comprises a stack structure with a third insulation layer and a third conductive layer;a first metal layer connected with the first doped region and the third doped region, wherein the first metal layer is served as a first bit line; anda second metal layer connected with the first conductive layer and the third ...

RANDOM CODE GENERATOR WITH NON-VOLATILE MEMORY

A random code generator includes a differential cell array, a power supply circuit, a first selecting circuit and a current judgment circuit. The power supply circuit receives an enrolling signal and a feedback signal. The first selecting circuit receives a first selecting signal. When the enrolling signal is activated and an enrollment is performed on the first differential cell, the power supply circuit provides an enrolling voltage, and the enrolling voltage is transmitted to a first storage element and a second storage element of the first differential cell through the first selecting circuit. Consequently, the cell current is generated. When a magnitude of the cell current is higher than a specified current value, the current judgment circuit activates the feedback signal, so that the power supply circuit stops providing the enrolling voltage. 1. A random code generator , comprising:a differential cell array comprising plural differential cells, wherein a first differential cell of the plural differential cells comprises a first select transistor, a first storage element and a second storage element, wherein a first source/drain terminal of the first select transistor is connected with a first source line, a gate terminal of the first select transistor is connected with a first word line, the first storage element is connected between a second source/drain terminal of the first select transistor and a first sub-control line of a first control line pair, and the second storage element is connected between the second source/drain terminal of the first select transistor and a second sub-control line of the first control line pair;a power supply circuit receiving an enrolling signal and a feedback signal;a first selecting circuit receiving a first selecting signal, wherein the first selecting circuit is connected with an output terminal of the power supply circuit and the first differential cell; anda current judgment circuit for detecting a cell current from the ...

Method for laying out wide metal lines with embedded contacts/vias

A method for laying out wide metal lines with embedded contacts/vias that has improved process window and an electronic substrate that has having such layout exposed and developed thereon are provided. In the method, the wide metal lines are provided with zig-zag shaped borders in either a waveform or in an interlacing form such that a processing window that is at least 5% larger than the line-to-line spacing for straight-line bordered metal lines is achieved. In a wave form, each one of contacts/vias of the first metal line is positioned juxtaposed to a corresponding contact/via in the second metal line. In the interlacing form, each of the contacts/vias being positioned juxtaposed to a pre-set spacing in between the contacts/vias in the second metal line. Both the wave and interlacing form wide metal lines layout can be used to improve the process window during a photolithographic process.

Resistive memory cell and associated cell array structure

A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region.

Micro-lens and micro-lens fabrication method

Single poly memory array with one shared deep doped region

Non-volatile memory and manufacturing method thereof

An ink-ejection unit of an inkjet printed head and fabrication method thereof, and a printing system

Memory cell array of multi-time programmable non-volatile memory

A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.

Inductor circuit and wireless communication device having inductor circuit integrated on single chip die to save more circuit costs

An inductor circuit includes a receiver inductive circuit, a transmitter inductive circuit, and an antenna inductive circuit which are implemented on a single chip die; the receiver inductive circuit is disposed on a specific ring of a specific plane to form a ring shape; the transmitter inductive circuit and the antenna inductive circuit are disposed inside the specific ring and surrounded by the specific ring of the specific plane; and, a circuit area, occupied by the transmitter inductive circuit, inside the specific ring and on the specific plane, is larger than a circuit area occupied by the receiver inductive circuit and by the antenna inductive circuit.

不揮発性メモリを伴うランダム符号発生器

【課題】ランダム符号発生器を提供する。【解決手段】ランダム符号発生器は、ディフェレンシャルセルアレイ、電源回路、第１の選択回路および電流判定回路を含む。電源回路は、登録信号およびフィードバック信号を受信する。第１の選択回路は、第１の選択信号を受信する。登録信号がアクティブ化され、第１のディフェレンシャルセルについて登録が実行されるとき、電源回路が、登録電圧を提供し、この登録電圧が、第１の選択回路を通して、第１のディフェレンシャルセルの第１の記憶素子および第２の記憶素子に送信される。この結果、セル電流が生成される。セル電流の大きさが、指定の電流値よりも高い場合、電流判定回路が、フィードバック信号をアクティブ化し、これにより、電源回路が、登録電圧の提供を停止する。【選択図】図１

電圧伝達デバイスを有するメモリユニット

【課題】電圧伝達デバイスを有するメモリユニットを提供する。【解決手段】フローティングゲートトランジスタＦＧＴ１は、ビットライン信号を受け取るための第１の端子、第２の端子、及びフローティングゲートを有している。ワードライントランジスタＷＬＴ１は、フローティングゲートトランジスタの第２の端子に接続される第１の端子、第３の電圧ＧＮＤを受け取るように構成される第２の端子、及びワードライン信号を受け取るための制御端子を有している。第１の電圧伝達デバイス１３０は、禁止動作の間の第２の電圧、及びプログラム動作又は消去動作の間の第１の電圧を出力するためのものである。第１のキャパシタンス素子１１０は、第１の電圧伝達デバイス及びフローティングゲートに接続されるとともに、第１の制御信号ＣＳ１を受け取るためのものである。【選択図】図１

Near-memory computation system for analog computing

A near-memory computation system (10) includes a plurality of computation nodes (100). The computation node (100) includes a plurality of non-volatile memory cells (1101 to 110X) and a processing element (120). Each non-volatile memory cell (1101) stores a weighting value during a program operation and outputs a weighting signal (SIG WT1 ) according to the weighting value during a read operation. The processing element (120) is coupled to the plurality of non-volatile memory cells (1101 to 110X). The processing element (120) receives the plurality of input signals (SIG IN1 to SIG INX ) and generates the computing result signal (SIG CR ) by perform computations with the plurality of input signals (SIG IN1 to SIG INX ) and a plurality of weighting signals (SIG WT1 to SIG WTX ) generated by the plurality of non-volatile memory cells (1101 to 110X). The plurality of non-volatile memory cells (1101 to 110X) and the processing element (120) are manufactured by different or the same process.

High voltage tolerance circuit

One time programmable read only memory and programming method thereof

Method for manufacturing micro pipe device

Manufacturing method for nonvolatile charge-trapping memory apparatus

A manufacturing method for a nonvolatile charge-trapping memory apparatus is provided. During the manufacturing process of the nonvolatile memory apparatus, a blocking layer of a storage device is effectively protected. Consequently, the blocking layer is not contaminated or thinned. Moreover, since the well regions of the logic device area and the memory device area are not simultaneously fabricated, it is feasible to fabricate small-sized nonvolatile memory cell in the memory device area and precisely control the threshold voltage of the charge trapping transistor.

記憶體結構及其製造方法

一種記憶體結構的製造方法，包括下列步驟。於基底上形成堆疊結構，堆疊結構由基底起包括電荷儲存結構、第一導體層及犧牲層。在第一導體層及犧牲層定義了特定形狀之後，於堆疊結構所暴露的基底上與第一導體層側壁上形成介電層。於介電層上及堆疊結構側壁上形成第二導體層，第二導體層具有位於堆疊結構側壁的突出部。移除犧牲層。於突出部側壁上形成第一間隙壁。以第一間隙壁為罩幕，移除部份第一導體層與部分第二導體層，而分別形成控制閘極與選擇閘極。移除部份電荷儲存結構，留下位於控制閘極下方的電荷儲存結構。於由控制閘極與選擇閘極所形成的結構兩側的基底中分別形成摻雜區。

One time programmable read only memory and programming method thereof

Resistive memory cell and associated cell array structure

A resistive memory cell includes a P-well region, an isolation structure, an N-well region, a first gate structure, a second gate structure, a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a word line, a bit line, a conductor line and a program line. The third N-type doped region, the fourth N-type doped region and the N-well region are collaboratively formed as an N-type merged region. The bit line is connected with the first N-type doped region. The word line is connected with a conductive layer of the first gate structure. The conductor line is connected with the second N-type doped region and a conductive layer of the second gate structure. The program line is connected with the N-type merged region.

Resistive memory cell and associated cell array structure

A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region.

記憶體結構及其製造方法

一種記憶體結構，包括至少一記憶胞，記憶胞包括基底、電荷儲存結構、控制閘極、選擇閘極、虛擬閘極、介電層及兩摻雜區。電荷儲存結構設置於基底上。控制閘極設置於電荷儲存結構上。選擇閘極設置於控制閘極一側的基底上。虛擬閘極設置於控制閘極另一側的基底上。介電層設置於選擇閘極與控制閘極之間、選擇閘極與基底之間、虛擬閘極與控制閘極之間、及虛擬閘極與基底之間。摻雜區分別設置於由控制閘極、選擇閘極與虛擬閘極所形成的結構兩側的基底中。

Forming control method applied to resistive random-access memory cell array

A forming control method for a resistive random-access memory cell array is provided. While a forming action of the resistive random-access memory cell array is performed, a verification action is performed to judge whether the forming action on the resistive random-access memory cells has been successfully done. By properly changing a forming voltage or a pulse width, the forming actions on all of the resistive random-access memory cells of the resistive random-access memory cell array can be successfully done.

Inductor circuit and wireless communication device having inductor circuit integrated on single chip die to save more circuit costs

An inductor circuit includes a receiver inductive circuit, a transmitter inductive circuit, and an antenna inductive circuit which are implemented on a single chip die; the receiver inductive circuit is disposed on a specific ring of a specific plane to form a ring shape; the transmitter inductive circuit and the antenna inductive circuit are disposed inside the specific ring and surrounded by the specific ring of the specific plane; and, a circuit area, occupied by the transmitter inductive circuit, inside the specific ring and on the specific plane, is larger than a circuit area occupied by the receiver inductive circuit and by the antenna inductive circuit.

Memory cell of charge-trapping non-volatile memory

A memory cell of a charge-trapping non-volatile memory is provided. The memory cell is formed on a well region of a semiconductor substrate. The memory cell includes a storage transistor. A gate structure of the storage transistor includes a first tunneling layer, a second tunneling layer, a trapping layer, a blocking layer and a gate layer. The first tunneling layer is contacted with a surface of the well region. The second tunneling layer covers the first tunneling layer. The trapping layer covers the second tunneling layer. The blocking layer covers the trapping layer. The gate layer covers the blocking layer. The second tunneling layer has gradient nitrogen distribution. A first nitrogen concentration of a first region of the second tunneling layer close to the first tunneling layer is lower than a second nitrogen concentration of a second region of the second tunneling layer close to the trapping layer.

Non-volatile memory and associated control method

A control method for a non-volatile memory is provided. After the non-volatile memory is enabled, a judging step is performed to judge whether the non-volatile memory enters a read mode, a program mode or an erase mode. If the judging result indicates that the non-volatile memory enters the read mode, the program mode or the erase mode, a worst threshold voltage of plural reference cells of the non-volatile memory is searched. Then, at least one of a control voltage for read action, a control voltage for program verify and a control voltage for erase verify is determined. Then, a read action, a program action or an erase action is performed on plural data cells of the non-volatile memory.

Storage transistor of charge-trapping non-volatile memory

A storage transistor of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a gate structure, a spacer, a first doped region and a second doped region. The well region is formed in a surface of the semiconductor substrate. The first doped region and the second doped region are formed in the well region. The gate structure includes a first tunneling layer, a second tunneling layer, a third tunneling layer, a trapping layer, a blocking layer and a gate layer. The first tunneling layer is contacted with the surface of the well region. The second tunneling layer covers the first tunneling layer. The third tunneling layer covers the second tunneling layer. The trapping layer covers the third tunneling layer. The blocking layer covers the trapping layer. The gate layer covers the blocking layer.