SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described. In one illustrative implementation, the sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. In other implementations, an SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. 1. An SRAM memory device comprising:a global bit line; a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; and', 'a pass gate coupled to the local bit line;, 'a sectioned bit line (SBL) comprisingwherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.2. The device of claim 1 , wherein a drain of the pass gate is coupled to the local bit line.3. The device of further comprising a plurality of sectioned bit lines configured along a direction parallel to local bit lines associated with the plurality of sectioned bit lines.4. The device of further comprising a plurality of sectioned bit lines configured along a direction parallel to word lines associated with the plurality of sectioned bit lines.5. The device of further comrpising first modules of sectioned bit lines (SBLs) configured along a direction parallel to local bit lines associated with the sectioned bit lines claim 1 , and second modules of SBLs configured along a direction parallel to word lines associated with the sectioned bit lines.6. The device of claim 1 , wherein the global bit line and local bit line are oriented in a same direction.7. The device of claim 1 , further comprising a plurality of local section lines;wherein the global bit line has ...

SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS, INCLUDING HIERARCHICAL AND/OR OTHER FEATURES

A hierarchical sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line in hierarchy, and associated systems and methods are described. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line, and wherein the sectioned bit lines are arranged in hierarchical arrays. In other implementations, a hierarchical SRAM memory device may be configured involving sectioned bit lines and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. 1. An SRAM memory device comprising: [ a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; &', 'a pass gate coupled to the local bit line;, 'a plurality of sectioned bit lines (SBLs), each comprising, 'a local sense amplifier;', 'a local shared data driver;', 'a global bit line;, 'a local section bit line includingwherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.2. The device of wherein the pass gates are configured to connect and/or isolate the sectioned bit line and local sense line.3. A local section bit line (LSBL) of an SRAM including: a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; and', 'a pass gate coupled to the local bit line;, 'a plurality of sectioned bit lines (SBLs), each comprisinga local shared sense amplifier;a local shared data driver;a global bit line;wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.4. The device of wherein the pass gates are configured to connect and ...

Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line. 1. An SRAM memory device comprising: [ a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; &', 'a pass gate coupled to the local bit line;, 'a plurality of sectioned bit lines (SBLs), each comprising, 'a local sense amplifier;', 'a local shared data driver;', 'a global bit line;, 'a local section bit line includingwherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit line.2. The device of wherein the pass gates are configured to connect and/or isolate the sectioned bit line and local sense line.3. A local section bit line (LSBL) of an SRAM including: a local bit line;', 'one or more memory cells connected to the local bit line;', 'a local complement bit line connected to the memory cell; and', 'a pass gate coupled to the local bit line;, 'a plurality of sectioned bit lines (SBLs), each comprisinga local shared sense amplifier;a local shared data driver;a global bit line;wherein the local sense amplifier is configured to amplify a signal on a local sense line and provide an output to the global bit ...

Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.

Systems and methods of sectioned bit line memory arrays, some including hierarchical and/or other features

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.

Systems and methods of sectioned bit line memory arrays, some including hierarchical and/or other features