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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 904. Отображено 191.
18-06-2009 дата публикации

MEMORY MODULE WITH REDUCED ACCESS GRANULARITY

Номер: US2009157994A1
Автор: HAMPEL CRAIG E, WARE FREDERICK A, HAMPEL CRAIG E., WARE FREDERICK A.
Принадлежит:

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

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Номер записи: 1
29-09-2011 дата публикации

MESOCHRONOUS SIGNALING SYSTEM WITH CORE-CLOCK SYNCHRONIZATION

Номер: US20110239030A1
Автор: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller, WARE FREDERICK A, PALMER ROBERT E, POULTON JOHN W, FULLER ANDREW M, WARE FREDERICK A., PALMER ROBERT E., POULTON JOHN W., FULLER ANDREW M.
Принадлежит:

In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

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Номер записи: 2
08-11-2011 дата публикации

Low energy memory component

Номер: US0008054707B2
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply voltage is used to power a sense amplifier in the DRAM circuit for amplifying a voltage difference between two bit lines coupled to the sense amplifier. As a result, the heat produced by the self-refresh operation is only a fraction of the heat produced by the conventional self-refresh powered by the substantially invariant power supply voltage.

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Номер записи: 3
08-11-2005 дата публикации

Apparatus and method for pipelined memory operations

Номер: US0006963956B2
Автор: Richard M. Barth, Ely K. Tsern, Mark A. Horowitz, Donald C. Stark, Craig E. Hampel, Frederick A. Ware, John B. Dillon, BARTH RICHARD M, TSERN ELY K, HOROWITZ MARK A, STARK DONALD C, HAMPEL CRAIG E, WARE FREDERICK A, DILLON NANCY DAVID, BARTH RICHARD M., TSERN ELY K., HOROWITZ MARK A., STARK DONALD C., HAMPEL CRAIG E., WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

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Номер записи: 4
08-10-2009 дата публикации

Low Energy Memory Component

Номер: US2009251982A1
Автор: WARE FREDERICK A, WARE FREDERICK A.
Принадлежит:

The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply voltage is used to power a sense amplifier in the DRAM circuit for amplifying a voltage difference between two bit lines coupled to the sense amplifier. As a result, the heat produced by the self-refresh operation is only a fraction of the heat produced by the conventional self-refresh powered by the substantially invariant power supply voltage.

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Номер записи: 5
16-04-2001 дата публикации

APPARATUS AND METHOD FOR DEVICE TIMING COMPENSATION

Номер: KR20010031040A
Автор: WARE FREDERICK A., BARTH RICHARD M., STARK DONALD C., HAMPEL CRAIG E., TSERN ELY K., ABHYANKAR ABHIJIT M.
Принадлежит:

An electronic device with device timing constraints includes a set of connections coupled to an interconnect structure that carries row and column commands. A memory core stores data. A memory interface is connected to the set of connections and the memory core. The memory interface includes circuitry for generating memory core timing signals in accordance with the row commands and the column commands. The memory core timing signals have timing constraints to insure correct memory core operation. The memory interface circuitry includes individual delay components for adjusting the timing of selected timing signals of the memory core timing signals. © KIPO & WIPO 2007 ...

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Номер записи: 6
25-12-2012 дата публикации

Signal calibration methods and apparatuses

Номер: US0008339895B2
Автор: Frederick A. Ware, Reza Navid, John W. Poulton, WARE FREDERICK A, NAVID REZA, POULTON JOHN W, WARE FREDERICK A., POULTON JOHN W.
Принадлежит: Rambus Inc., WARE FREDERICK A, NAVID REZA, POULTON JOHN W, RAMBUS INC, WARE FREDERICK A., POULTON JOHN W., RAMBUS INC.

In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree.

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Номер записи: 7
29-01-2013 дата публикации

Unidirectional error code transfer for both read and write data transmitted via bidirectional data link

Номер: US0008365042B2
Автор: Yuanlong Wang, Frederick A. Ware, WANG YUANLONG, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, WANG YUANLONG, WARE FREDERICK A, RAMBUS INC., WARE FREDERICK A.

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

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Номер записи: 8
13-08-2013 дата публикации

Cross-threaded memory system

Номер: US0008510495B2
Автор: Frederick A. Ware, Kishore Kasamsetty, WARE FREDERICK A, KASAMSETTY KISHORE, WARE FREDERICK A.
Принадлежит: Rambus Inc., WARE FREDERICK A, KASAMSETTY KISHORE, RAMBUS INC, WARE FREDERICK A., RAMBUS INC.

In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

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Номер записи: 9
29-03-2016 дата публикации

Memory controller supporting nonvolatile physical memory

Номер: US0009298609B2
Автор: Frederick A. Ware, Ely K. Tsern, WARE FREDERICK A, TSERN ELY K, WARE FREDERICK A., TSERN ELY K.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

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Номер записи: 10
14-06-2011 дата публикации

Bimodal memory controller

Номер: US0007961532B2
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O pin or printed-circuit board connection (depending upon implementation). The remaining signal connector may be left electrically uncoupled from the external, wired electrical path, and, if desired, the corresponding remaining interface circuit may be left unused during operation of the memory controller.

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Номер записи: 11
09-11-2010 дата публикации

Memory system with error detection and retry modes of operation

Номер: US0007831882B2
Автор: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware, TSERN ELY K, HOROWITZ MARK A, WARE FREDERICK A, TSERN ELY K., HOROWITZ MARK A., WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

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Номер записи: 12
01-11-2012 дата публикации

MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE

Номер: US20120275237A1
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит:

A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. 1. A memory controller comprising:first circuitry to drive address bits and a first timing signal to a dynamic random access memory (DRAM), wherein the address bits are associated with one or more edges of the first timing signal, wherein the first timing signal requires a first propagation delay time to propagate from the memory controller to the DRAM, wherein the address bits indicate a location within an array of the DRAM for storage of write data bits;second circuitry to drive the write data bits and to drive a second timing signal to the DRAM, wherein the write data bits are associated with one or more edges of the second timing signal, wherein the second timing signal requires a second propagation delay time to propagate from the memory controller to the DRAM;a delay circuit including a plurality of delay elements coupled in series to provide a plurality of internal delayed timing signals, each delay element providing one of the internal delayed timing signals and each delayed timing signal being a differently delayed version of an internal timing signal; anda ...

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Номер записи: 13
12-02-2008 дата публикации

Memory system having delayed write timing

Номер: US0007330953B2
Автор: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen, BARTH RICHARD M, WARE FREDERICK A, STARK DONALD C, HAMPEL CRAIG E, DAVIS PAUL G, ABHYANKAR ABHIJIT M, GASBARRO JAMES A, NGUYEN DAVID, BARTH RICHARD M., WARE FREDERICK A., STARK DONALD C., HAMPEL CRAIG E., DAVIS PAUL G., ABHYANKAR ABHIJIT M., GASBARRO JAMES A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.

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Номер записи: 14
18-09-2012 дата публикации

Memory controller for non-homogeneous memory system

Номер: US0008271745B2
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., WARE FREDERICK A, RAMBUS INC, WARE FREDERICK A., RAMBUS INC.

A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.

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Номер записи: 15
03-11-2015 дата публикации

Memory access during memory calibration

Номер: US0009176903B2
Автор: Ian Shaeffer, Frederick A. Ware, SHAEFFER IAN, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., SHAEFFER IAN, WARE FREDERICK A, RAMBUS INC, WARE FREDERICK A., RAMBUS INC.

A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

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Номер записи: 16
28-12-2004 дата публикации

Apparatus and method for generating a distributed clock signal using gear ratio techniques

Номер: US0006836521B2
Автор: Frederick A. Ware, Kevin S. Donnelly, Ely K. Tsern, Srinivas Nimmagadda, WARE FREDERICK A, DONNELLY KEVIN S, TSERN ELY K, NIMMAGADDA SRINIVAS, WARE FREDERICK A., DONNELLY KEVIN S., TSERN ELY K.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are "colored", i.e., identified by a number (1st, 2nd, etc.). By using the coloring technique, the appropriate clock edge to perform a data or control signal transfer can be identified. The edges are preferably chosen to minimize the latency of the transfer.

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Номер записи: 17
04-07-2006 дата публикации

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Номер: US0007073035B2
Автор: Frederick A. Ware, Richard E. Perego, Craig E. Hampel, Ely K. Tsern, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E, TSERN ELY K, WARE FREDERICK A., PEREGO RICHARD E., HAMPEL CRAIG E., TSERN ELY K.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections for providing access to the memory module, and a second set of interface connections for providing access to the memory module. The memory controller also comprises memory access circuitry for providing memory access signals to the memory module for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible ...

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Номер записи: 18
20-04-2010 дата публикации

Point-to-point connection topology for stacked devices

Номер: US0007701045B2
Автор: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer, WARE FREDERICK A, TSERN ELY K, SHAEFFER IAN P, WARE FREDERICK A., TSERN ELY K., SHAEFFER IAN P.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

The point-to-point interconnection system for stacked devices includes a device, a substrate, operational circuitry, at least three electrical contacts and a conductor. The substrate has opposing first and second surfaces. A first electrical contact is mechanically coupled to the first surface of the device and electrically coupled to the operational circuitry. The second electrical contact is mechanically coupled to the first surface. The third electrical contact is mechanically coupled to the second surface opposite the first electrical contact. The conductor electrically couples the second electrical contact to the third electrical contact.

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Номер записи: 19
05-07-2012 дата публикации

Method and Apparatus for Delaying Write Operations

Номер: US20120173811A1
Автор: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen, BARTH RICHARD M, WARE FREDERICK A, STARK DONALD C, HAMPEL CRAIG E, DAVIS PAUL G, ABHYANKAR ABHIJIT M, GASBARRO JAMES A, NGUYEN DAVID, BARTH RICHARD M., WARE FREDERICK A., STARK DONALD C., HAMPEL CRAIG E., DAVIS PAUL G., ABHYANKAR ABHIJIT M., GASBARRO JAMES A.
Принадлежит:

An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.

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Номер записи: 20
28-10-2010 дата публикации

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

Номер: US20100271092A1
Автор: Jared L. Zerbe, Frederick A. Ware, ZERBE JARED L, WARE FREDERICK A, ZERBE JARED L., WARE FREDERICK A.
Принадлежит:

Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.

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Номер записи: 21
01-09-2015 дата публикации

Memory component with pattern register circuitry to provide data patterns for calibration

Номер: US0009123433B2
Автор: Craig E. Hampel, Richard E. Perego, Stefanos Sidiropoulos, Ely K. Tsern, Frederick A. Ware, HAMPEL CRAIG E, PEREGO RICHARD E, SIDIROPOULOS STEFANOS, TSERN ELY K, WARE FREDERICK A, HAMPEL CRAIG E., PEREGO RICHARD E., TSERN ELY K., WARE FREDERICK A.
Принадлежит: RAMBUS INC., RAMBUS INC

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

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Номер записи: 22
19-08-2010 дата публикации

Memory System With Point-to-Point Request Interconnect

Номер: US20100211748A1
Автор: Richard E. Perego, Frederick A. Ware, PEREGO RICHARD E, WARE FREDERICK A, PEREGO RICHARD E., WARE FREDERICK A.
Принадлежит: RAMBUS INC.

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

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Номер записи: 23
20-09-2012 дата публикации

Staggered Mode Transitions in a Segmented Interface

Номер: US20120236659A1
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: RAMBUS INC.

A memory integrated circuit comprises first and second memory arrays and first and second interfaces. The first interface receives a signal for accessing a memory location in one of the first and the second memory arrays during a first time interval. The second interface receives a signal for accessing a memory location in one of the first and the second memory arrays during the first time interval. The first interface receives signals for accessing memory locations in the first and the second memory arrays, and the second interface is disabled from accessing the first and the second memory arrays during the second time interval. A signaling rate of a signal received by the second interface, a supply voltage of the second interface, an on-chip termination impedance of the second interface, or a voltage amplitude of a signal received by the second interface is adjusted during the second time interval.

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Номер записи: 24
08-04-2014 дата публикации

Communication channel calibration for drift conditions

Номер: US0008693556B2
Автор: Frederick A. Ware, Richard E. Perego, Craig E. Hampel, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

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Номер записи: 25
03-05-2005 дата публикации

Memory system and method for two step write operations

Номер: US0006889300B2
Автор: Paul G. Davis, Frederick A. Ware, Craig E. Hampel, DAVIS PAUL G, WARE FREDERICK A, HAMPEL CRAIG E, DAVIS PAUL G., WARE FREDERICK A., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

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Номер записи: 26
30-11-2004 дата публикации

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Номер: US0006826657B1
Автор: Frederick A. Ware, Richard E. Perego, Craig E. Hampel, Ely K. Tsern, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E, TSERN ELY K, WARE FREDERICK A., PEREGO RICHARD E., HAMPEL CRAIG E., TSERN ELY K.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component having a memory core for storing data therein, a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory module also comprises access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections. The memory controller provides memory access signals ...

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Номер записи: 27
05-01-2012 дата публикации

Memory Controller for Non-Homogeneous Memory System

Номер: US20120005412A1
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит:

A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices. 1. (canceled)2. A memory system , comprising:a memory controller;a main memory including a range of physical addresses divided between one or more memory devices of a first type and one or more memory devices of a second type, wherein the first type and the second type have different volatility attributes; andaddress translation logic to map virtual addresses onto the physical addresses of the main memory.3. The memory system of claim 2 , where the memory controller is to swap the data from a secondary storage to the main memory claim 2 , to store the data in either first or second type devices claim 2 , depending upon at least one of a field associated with the data or a usage characteristic of the data.4. The memory system of claim 3 , where the at least one of a field or a usage characteristic includes a tag or other data structure associated with each page of the data.5. The memory system of claim 3 , where the at least one of a field or a usage characteristic includes a characteristic that represents one of a read-only attribute or a read-mostly attribute.6. The memory system of claim 2 , where the first type is DRAM ...

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Номер записи: 28
05-05-2009 дата публикации

Asynchronous, high-bandwidth memory component using calibrated timing elements

Номер: US0007529141B2
Автор: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, STARK DONALD C, WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E., STARK DONALD C.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

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Номер записи: 29
23-02-2006 дата публикации

Memory module with termination component

Номер: US2006039174A1
Автор: WARE FREDERICK A, TSERN ELY K, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., TSERN ELY K., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит:

A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal path is coupled to each of the memory devices and the termination component, and extends along the memory devices such that signals propagating on the control signal path propagate past each of the memory devices in succession before reaching the termination component. A unique set of data signal paths is coupled to each of the memory devices.

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Номер записи: 30
01-01-2013 дата публикации

Integrated circuit heating to effect in-situ annealing

Номер: US0008344475B2
Автор: Ian P. Shaeffer, Gary B. Bronner, Brent S. Haukness, Kevin S. Donnelly, Frederick A. Ware, Mark A. Horowitz, SHAEFFER IAN P, BRONNER GARY B, HAUKNESS BRENT S, DONNELLY KEVIN S, WARE FREDERICK A, HOROWITZ MARK A, SHAEFFER IAN P., BRONNER GARY B., HAUKNESS BRENT S., DONNELLY KEVIN S., WARE FREDERICK A., HOROWITZ MARK A.
Принадлежит: Rambus Inc., RAMBUS INC, SHAEFFER IAN P, BRONNER GARY B, HAUKNESS BRENT S, DONNELLY KEVIN S, WARE FREDERICK A, HOROWITZ MARK A, RAMBUS INC., SHAEFFER IAN P., BRONNER GARY B., HAUKNESS BRENT S., DONNELLY KEVIN S., WARE FREDERICK A., HOROWITZ MARK A.

In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.

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Номер записи: 31
23-09-2014 дата публикации

Memory components and controllers that utilize multiphase synchronous timing references

Номер: US0008842492B2
Автор: Ian Shaeffer, Frederick A. Ware, Scott C. Best, SHAEFFER IAN, WARE FREDERICK A, BEST SCOTT C, WARE FREDERICK A., BEST SCOTT C.
Принадлежит: Rambus Inc., SHAEFFER IAN, WARE FREDERICK A, BEST SCOTT C, RAMBUS INC, WARE FREDERICK A., BEST SCOTT C., RAMBUS INC.

Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.

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Номер записи: 32
23-12-2014 дата публикации

Mesochronous signaling system with core-clock synchronization

Номер: US0008918667B2
Автор: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller, WARE FREDERICK A, PALMER ROBERT E, POULTON JOHN W, FULLER ANDREW M, WARE FREDERICK A., PALMER ROBERT E., POULTON JOHN W., FULLER ANDREW M.
Принадлежит: Rambus Inc., WARE FREDERICK A, PALMER ROBERT E, POULTON JOHN W, FULLER ANDREW M, RAMBUS INC, WARE FREDERICK A., PALMER ROBERT E., POULTON JOHN W., FULLER ANDREW M., RAMBUS INC.

In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

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Номер записи: 33
27-03-2007 дата публикации

Integrated circuit memory device having write latency function

Номер: US0007197611B2
Автор: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen, BARTH RICHARD M, WARE FREDERICK A, STARK DONALD C, HAMPEL CRAIG E, DAVIS PAUL G, ABHYANKAR ABHIJIT M, GASBARRO JAMES A, NGUYEN DAVID, BARTH RICHARD M., WARE FREDERICK A., STARK DONALD C., HAMPEL CRAIG E., DAVIS PAUL G., ABHYANKAR ABHIJIT M., GASBARRO JAMES A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

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Номер записи: 34
03-02-2015 дата публикации

Maintenance operations in a DRAM

Номер: US8949520B2
Автор: WARE FREDERICK A, PALMER ROBERT E, POULTON JOHN W, WARE FREDERICK A., PALMER ROBERT E., POULTON JOHN W.
Принадлежит: WARE FREDERICK A, PALMER ROBERT E, POULTON JOHN W, RAMBUS INC, WARE FREDERICK A., PALMER ROBERT E., POULTON JOHN W., RAMBUS INC.

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

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Номер записи: 35
28-08-2014 дата публикации

MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION

Номер: US20140244923A1
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc.

A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

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Номер записи: 36
01-10-2009 дата публикации

Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link

Номер: US2009249139A1
Автор: WANG YUANLONG, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит:

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

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Номер записи: 37
29-01-2002 дата публикации

Method and apparatus for two step memory write operations

Номер: US0006343352B1
Автор: Paul G. Davis, Frederick A. Ware, Craig E. Hampel, DAVIS PAUL G, WARE FREDERICK A, HAMPEL CRAIG E, DAVIS PAUL G., WARE FREDERICK A., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

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Номер записи: 38
27-09-2012 дата публикации

PARTIAL-RATE TRANSFER MODE FOR FIXED-CLOCK-RATE INTERFACE

Номер: US20120243632A1
Автор: Frederick A. Ware, Robert E. Palmer, John Poulton, WARE FREDERICK A, PALMER ROBERT E, POULTON JOHN, WARE FREDERICK A., PALMER ROBERT E.
Принадлежит: RAMBUS INC.

Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.

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Номер записи: 39
10-04-2014 дата публикации

Memory Controller That Enforces Strobe-To-Strobe Timing Offset

Номер: US20140098622A1
Автор: Frederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel, WARE FREDERICK A, TSERN ELY K, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., TSERN ELY K., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит: Rambus Inc.

A memory controller outputs a clock signal to first and second DRAMs disposed on a memory module, the clock signal requiring respective first and second time intervals to propagate to the first and second DRAMs. The memory controller outputs a write command to be sampled by the first and second DRAMs at times indicated by the first clock signal and outputs, in association with the write command, first and second write data to the first and second DRAMs, respectively. The memory controller further outputs first and second strobe signals respectively to the first and second DRAMs, the first strobe signal to time reception of the first and second write data therein. The memory controller adjusts respective transmission times of the first and second strobe signals to be offset from one another by a time interval that corresponds to a difference between the first and second time intervals. 1. A method of operation within a memory controller component , the method comprising:transmitting a clock signal to first and second dynamic random access memory (DRAM) components disposed on a memory module via a clock signal line, the clock signal line being coupled to the first and second DRAM components at different points along its length such that the clock signal propagates past the first DRAM component to the second DRAM component, the clock signal having a first arrival time at the first DRAM and a second arrival time at the second DRAM, the first arrival time preceding the second arrival time;transmitting a write command to the first and second DRAM components via a set of signal lines, the write command to be sampled by the first and second DRAM components at respective times corresponding to one or more transitions of the clock signal, the set of signal lines being coupled to the first and second DRAM components at different points along its length such that the write command propagates past the first DRAM component to the second DRAM component and arrives at the first ...

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Номер записи: 40
12-01-2012 дата публикации

MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOL

Номер: US20120011331A1
Автор: Frederick A. Ware, John Welsford Brooks, Kishore Ven Kasamsetty, Richard E. Perego, WARE FREDERICK A, BROOKS JOHN WELSFORD, KASAMSETTY KISHORE VEN, PEREGO RICHARD E, WARE FREDERICK A., PEREGO RICHARD E.
Принадлежит: RAMBUS INC.

The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device. 1. A method of operation for a semiconductor memory device , the method comprising:receiving, from a memory controller, a request at an interface of the memory device, wherein the request includes independent activate and precharge commands;wherein the activate command is associated with a row address, which identifies a first row for the activate command;in response to the activate command, activating the first row in a first bank in the memory device; andin response to the precharge command, precharging a second bank in the memory device.2. The method of claim 1 , wherein the activate command includes a first bank address claim 1 , which identifies the first bank for the activate command.3. The method of claim 1 , wherein the precharge command includes a second bank address claim 1 , which identifies the second bank for the precharge command.4. The method of claim 1 , wherein the method further comprises:receiving a second request from a memory controller at a memory device, wherein the second request includes a first column-access command and a second column-access command;in response to the first column-access command, performing a first memory operation involving a first column access at the memory device; andin response to the second column-access command, performing a second memory operation involving a second column access at the memory device.5. The method of claim 4 , wherein the first and second column-access commands include:two ...

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Номер записи: 41
02-10-2014 дата публикации

Configurable Width Memory Modules

Номер: US2014293671A1
Автор: PEREGO RICHARD E, STARK DONALD C, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, PEREGO RICHARD E., STARK DONALD C., WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E.
Принадлежит:

Describes is a memory system that utilizes motherboard traces in a way that permits maximum utilization of system data lines while accommodating varying numbers of memory modules. It is possible in a system such as this to utilize all individual sets of point-to-point signaling lines, even when less than all of the available memory sockets are occupied. Memory modules with configurable data widths support a relatively wide mode in which one module utilizes all available system data lines, or a relatively narrow mode in which multiple, narrower modules split the available system data lines between them.

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Номер записи: 42
24-11-2015 дата публикации

Maintenance operations in a DRAM

Номер: US0009196348B2
Автор: Frederick A. Ware, Robert E. Palmer, John W. Poulton, WARE FREDERICK A, PALMER ROBERT E, POULTON JOHN W, WARE FREDERICK A., PALMER ROBERT E., POULTON JOHN W.
Принадлежит: RAMBUS INC., RAMBUS INC

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

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Номер записи: 43
15-07-2010 дата публикации

TECHNIQUES FOR IMPROVED TIMING CONTROL OF MEMORY DEVICES

Номер: US20100180143A1
Автор: Frederick A. Ware, Carl Werner, Ian Shaeffer, WARE FREDERICK A, WERNER CARL, SHAEFFER IAN, WARE FREDERICK A.
Принадлежит: Rambus Inc.

Techniques for improved timing control of memory devices are disclosed. In one embodiment, the techniques may be realized as a memory controller to communicate with a memory device via a communications link. The memory controller may comprise a memory interface to exchange data with the memory device via a set of N conductors according to at least one clock, the data being encoded such that each M bits of data are represented by at least one symbol and each symbol is associated with a combination of signal levels on a group of n conductors, wherein M Подробнее

Номер записи: 44
25-05-2010 дата публикации

Memory controller with multiple delayed timing signals

Номер: US0007724590B2
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third output driver to a third signal path. Rising and falling edge transitions of the timing information indicate times at which subsequent symbols of the write data are valid on the signal path. The timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach the destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path.

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Номер записи: 45
27-10-2011 дата публикации

PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER

Номер: US20110264849A1
Автор: Frederick A. Ware, Holden Jessup, WARE FREDERICK A, JESSUP HOLDEN, WARE FREDERICK A.
Принадлежит: RAMBUS INC.

The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

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Номер записи: 46
07-02-2013 дата публикации

FREQUENCY-AGILE STROBE WINDOW GENERATION

Номер: US20130033946A1
Автор: Frederick A. Ware, Brian S. Leibowitz, Ely Tsern, WARE FREDERICK A, LEIBOWITZ BRIAN S, TSERN ELY, WARE FREDERICK A., LEIBOWITZ BRIAN S.
Принадлежит: RAMBUS INC.

The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.

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Номер записи: 47
12-02-2008 дата публикации

Integrated circuit memory device having delayed write timing based on read response time

Номер: US0007330952B2
Автор: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen, BARTH RICHARD M, WARE FREDERICK A, STARK DONALD C, HAMPEL CRAIG E, DAVIS PAUL G, ABHYANKAR ABHIJIT M, GASBARRO JAMES A, NGUYEN DAVID, BARTH RICHARD M., WARE FREDERICK A., STARK DONALD C., HAMPEL CRAIG E., DAVIS PAUL G., ABHYANKAR ABHIJIT M., GASBARRO JAMES A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.

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Номер записи: 48
03-08-2010 дата публикации

Cross-threaded memory system

Номер: US0007769942B2
Автор: Frederick A. Ware, Kishore Kasamsetty, WARE FREDERICK A, KASAMSETTY KISHORE, WARE FREDERICK A.
Принадлежит: Rambus, Inc., RAMBUS INC, RAMBUS, INC.

In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requester IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

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Номер записи: 49
21-10-2003 дата публикации

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Номер: US0006636935B1
Автор: Frederick A. Ware, Richard E. Perego, Craig E. Hampel, Ely K. Tsern, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E, TSERN ELY K, WARE FREDERICK A., PEREGO RICHARD E., HAMPEL CRAIG E., TSERN ELY K.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory component having a memory core for storing data therein. The memory component comprises a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory component also comprises memory access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.

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Номер записи: 50
14-05-2013 дата публикации

Memory controller with adjustable width strobe interface

Номер: US0008441872B2
Автор: Jade M. Kizer, Yoshihito Koya, Frederick A. Ware, KIZER JADE M, KOYA YOSHIHITO, WARE FREDERICK A, KIZER JADE M., WARE FREDERICK A.
Принадлежит: Rambus Inc., KIZER JADE M, KOYA YOSHIHITO, WARE FREDERICK A, RAMBUS INC, KIZER JADE M., WARE FREDERICK A., RAMBUS INC.

A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.

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Номер записи: 51
30-06-2011 дата публикации

SIGNAL CALIBRATION METHODS AND APPARATUSES

Номер: US20110158031A1
Автор: Frederick A. Ware, Reza Navid, John W. Poulton, WARE FREDERICK A, NAVID REZA, POULTON JOHN W, WARE FREDERICK A., POULTON JOHN W.
Принадлежит:

In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree.

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Номер записи: 52
11-09-2014 дата публикации

Memory Controller Supporting Nonvolatile Physical Memory

Номер: US2014258601A1
Автор: WARE FREDERICK A, TSERN ELY K, WARE FREDERICK A., TSERN ELY K.
Принадлежит:

A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

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Номер записи: 53
19-06-2014 дата публикации

Clock Synchronization In A Memory System

Номер: US20140169110A1
Автор: Jade M. Kizer, John M. Wilson, John Eble, III, Frederick A. Ware, KIZER JADE M, WILSON JOHN M, EBLE III JOHN, WARE FREDERICK A, KIZER JADE M., WILSON JOHN M., EBLE, III JOHN, WARE FREDERICK A.
Принадлежит:

Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.

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Номер записи: 54
05-01-2012 дата публикации

Memory Controller for Controlling Write Signaling

Номер: US20120005437A1
Автор: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen, BARTH RICHARD M, WARE FREDERICK A, STARK DONALD C, HAMPEL CRAIG E, DAVIS PAUL G, ABHYANKAR ABHIJIT M, GASBARRO JAMES A, NGUYEN DAVID, BARTH RICHARD M., WARE FREDERICK A., STARK DONALD C., HAMPEL CRAIG E., DAVIS PAUL G., ABHYANKAR ABHIJIT M., GASBARRO JAMES A.
Принадлежит:

A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data. 1. A memory controller having an interface to convey: a first command that specifies activation of a row of memory cells;', 'a second command that specifies a write operation directed to the row of memory cells;', 'a bit that specifies whether precharging will occur in connection with the write operation;', 'a code that specifies whether data mask information will be issued in connection with the write operation; and', 'if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation; and, 'over a first set of interconnect resourcesover a second set of interconnect resources, separate from the first set of interconnect resource, the write data.2. The memory controller of claim 1 , wherein two consecutive bits of the data mask information are conveyed during a clock cycle of a clock signal that is received by the memory device.3. The memory controller of claim 1 , wherein the first set of interconnect resources conveys a column address that identifies a subset of memory cells in the row.4. The memory controller of claim 3 , wherein the interface conveys ...

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Номер записи: 55
26-08-2010 дата публикации

VOLTAGE-STEPPED LOW-POWER MEMORY DEVICE

Номер: US20100214822A1
Автор: Frederick A. Ware, Yoshihito Koya, WARE FREDERICK A, KOYA YOSHIHITO, WARE FREDERICK A.
Принадлежит: RAMBUS INC.

This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more progressively higher intermediate voltage levels using one or more voltage sources. Specifically, each intermediate voltage level is between the initial voltage and the final voltage, and each voltage source generates a respective intermediate voltage level. Note that charging the capacitive energy storage device through one or more intermediate voltage levels reduces energy dissipation during the charging process.

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Номер записи: 56
06-11-2012 дата публикации

Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift

Номер: US0008305821B2
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., WARE FREDERICK A, RAMBUS INC, WARE FREDERICK A., RAMBUS INC.

A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift.

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Номер записи: 57
04-06-2002 дата публикации

High performance cost optimized memory

Номер: US0006401167B1
Автор: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen, BARTH RICHARD M, WARE FREDERICK A, STARK DONALD C, HAMPEL CRAIG E, DAVIS PAUL G, ABHYANKAR ABHIJIT M, GASBARRO JAMES A, NGUYEN DAVID, BARTH RICHARD M., WARE FREDERICK A., STARK DONALD C., HAMPEL CRAIG E., DAVIS PAUL G., ABHYANKAR ABHIJIT M., GASBARRO JAMES A.
Принадлежит: Rambus Incorporated, RAMBUS INC, RAMBUS INCORPORATED

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

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Номер записи: 58
06-01-2015 дата публикации

Periodic calibration for communication channels by drift tracking

Номер: US0008929424B2
Автор: Craig E. Hampel, Frederick A. Ware, Richard E. Perego, HAMPEL CRAIG E, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E., WARE FREDERICK A., PEREGO RICHARD E.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

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Номер записи: 59
22-05-2014 дата публикации

Configurable, Power Supply Voltage Referenced Single-Ended Signaling with ESD Protection

Номер: US20140140419A1
Автор: John W. Poulton, Frederick A. Ware, Carl W. Werner, POULTON JOHN W, WARE FREDERICK A, WERNER CARL W, POULTON JOHN W., WARE FREDERICK A., WERNER CARL W.
Принадлежит: Rambus Inc.

A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

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Номер записи: 60
10-04-2012 дата публикации

Multi-column addressing mode memory system including an integrated circuit memory device

Номер: US0008154947B2
Автор: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson, WARE FREDERICK A, LAI LAWRENCE, BELLOWS CHAD A, RICHARDSON WAYNE S, WARE FREDERICK A., BELLOWS CHAD A., RICHARDSON WAYNE S.
Принадлежит: RAMBUS Inc., WARE FREDERICK A, LAI LAWRENCE, BELLOWS CHAD A, RICHARDSON WAYNE S, RAMBUS INC, WARE FREDERICK A., BELLOWS CHAD A., RICHARDSON WAYNE S., RAMBUS INC.

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

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Номер записи: 61
27-03-2012 дата публикации

Communication channel calibration for drift conditions

Номер: US0008144792B2
Автор: Frederick A. Ware, Richard E. Perego, Craig E. Hampel, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E, RAMBUS INC, WARE FREDERICK A., PEREGO RICHARD E., HAMPEL CRAIG E., RAMBUS INC.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

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Номер записи: 62
02-08-2012 дата публикации

AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE

Номер: US20120198179A1
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит:

A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure. 1. A method of operation within a memory component , the method comprising:receiving write data exclusively via a first set of signaling-link receivers if a signaling interface of the memory component is set to a first logical width; andreceiving write data exclusively via a second set of signaling-link receivers if the signaling interface of the memory component is set to a second logical width, wherein the second logical width exceeds the first logical width and the first set of signaling-link receivers includes at least one signaling-link receiver not included in the second set of signaling-link receivers.2. The method of wherein the second logical width is twice the first logical width and the second set of signaling-link receivers comprises twice as many signaling-link receivers as the first set of signaling-link receivers.3. The method of wherein the memory component comprises a first number of signaling-link receivers that includes the first and second sets of signaling-link receivers and that defines a maximum width of the signaling interface.4. The method of wherein the first number of signaling-link receivers comprises twice as many signaling-link receivers as the second set of signaling-link receivers.5. The method of further comprising receiving write data exclusively via a third set of signaling-link receivers if the signaling interface of the memory component is set to a third logical width claim 1 , wherein the third logical width exceeds the second logical width claim 1 , ...

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Номер записи: 63
21-07-2015 дата публикации

Memory with merged control input

Номер: US0009087568B1
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Chip selection and internal clocking functions are enabled within an integrated circuit memory component in response to a single chip-enable control signal, thus reducing memory system pin count and wiring complexity relative to designs that require separate chip-select and clock-enable signals. Internal clocking logic may also be provided to generate timing signal edges more precisely limited to the number required to complete a given memory component operation, reducing the number of unnecessary timing events and lowering power consumption. Further, internal read and write clock signals may be speculatively enabled within the memory component to more quickly stabilize those clocks in preparation for data transmission and reception operations, potentially lowering memory access latency.

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Номер записи: 64
25-08-2009 дата публикации

LOW ENERGY MEMORY COMPONENT

Номер: KR1020090090330A
Автор: WARE FREDERICK A.
Принадлежит:

The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply voltage is used to power a sense amplifier in the DRAM circuit for amplifying a voltage difference between two bit lines coupled to the sense amplifier. As a result, the heat produced by the self-refresh operation is only a fraction of the heat produced by the conventional self-refresh powered by the substantially invariant power supply voltage. © KIPO & WIPO 2009 ...

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Номер записи: 65
27-11-2007 дата публикации

Memory systems with variable delays for write data signals

Номер: US0007301831B2
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a write data signal and a corresponding data valid or timing signal (also referred to as a write data valid signal or write data timing signal) and in turn generating multiple delayed versions of the write data signals and delayed valid signals. The memory system selects one of these delayed write data signals and delayed data valid signals for use in writing data to the memory components.

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Номер записи: 66
02-04-2013 дата публикации

Memory apparatus supporting multiple width configurations

Номер: US0008412906B2
Автор: Richard E. Perego, Donald C. Stark, Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, PEREGO RICHARD E, STARK DONALD C, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, PEREGO RICHARD E., STARK DONALD C., WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., PEREGO RICHARD E, STARK DONALD C, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, RAMBUS INC, PEREGO RICHARD E., STARK DONALD C., WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E., RAMBUS INC.

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

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Номер записи: 67
18-08-2009 дата публикации

Upgradable memory system with reconfigurable interconnect

Номер: US0007577789B2
Автор: Richard E. Perego, Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, PEREGO RICHARD E, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, PEREGO RICHARD E., WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

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Номер записи: 68
26-11-2013 дата публикации

Micro-threaded memory

Номер: US0008595459B2
Автор: Frederick A. Ware, Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai, WARE FREDERICK A, HAMPEL CRAIG E, RICHARDSON WAYNE S, BELLOWS CHAD A, LAI LAWRENCE, WARE FREDERICK A., HAMPEL CRAIG E., RICHARDSON WAYNE S., BELLOWS CHAD A.
Принадлежит: Rambus Inc., WARE FREDERICK A, HAMPEL CRAIG E, RICHARDSON WAYNE S, BELLOWS CHAD A, LAI LAWRENCE, RAMBUS INC, WARE FREDERICK A., HAMPEL CRAIG E., RICHARDSON WAYNE S., BELLOWS CHAD A., RAMBUS INC.

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

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Номер записи: 69
30-03-2006 дата публикации

Method, system and memory controller utilizing adjustable write data delay settings

Номер: US2006069895A1
Автор: WARE FREDERICK A, TSERN ELY K, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., TSERN ELY K., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит:

A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

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Номер записи: 70
24-11-2011 дата публикации

MEMORY INTERFACE WITH REDUCED READ-WRITE TURNAROUND DELAY

Номер: US20110289258A1
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: RAMBUS INC.

Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in the memory IC via one of the bidirectional links, or to another queue in the memory controller from a corresponding bank set in the memory IC via another of the bidirectional links. This communication technique reduces or eliminates the turnaround delay that occurs when the memory controller transitions from receiving the read data to providing the write data, thereby eliminating gaps in the data streams on the bidirectional links.

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Номер записи: 71
31-05-2012 дата публикации

Memory Modules and Devices Supporting Configurable Core Organizations

Номер: US20120134084A1
Автор: Richard E. Perego, Donald C. Stark, Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, PEREGO RICHARD E, STARK DONALD C, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, PEREGO RICHARD E., STARK DONALD C., WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E.
Принадлежит: Rambus Inc.

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

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Номер записи: 72
07-09-2010 дата публикации

Interface for a semiconductor memory device and method for controlling the interface

Номер: US0007793039B2
Автор: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen, BARTH RICHARD M, WARE FREDERICK A, STARK DONALD C, HAMPEL CRAIG E, DAVIS PAUL G, ABHYANKAR ABHIJIT M, GASBARRO JAMES A, NGUYEN DAVID, BARTH RICHARD M., WARE FREDERICK A., STARK DONALD C., HAMPEL CRAIG E., DAVIS PAUL G., ABHYANKAR ABHIJIT M., GASBARRO JAMES A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.

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Номер записи: 73
11-01-2011 дата публикации

Memory system and method for two step memory write operations

Номер: US0007870357B2
Автор: Paul G. Davis, Frederick A. Ware, Craig E. Hampel, DAVIS PAUL G, WARE FREDERICK A, HAMPEL CRAIG E, DAVIS PAUL G., WARE FREDERICK A., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.

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Номер записи: 74
29-07-2010 дата публикации

CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM

Номер: US20100188910A1
Автор: Jade M. Kizer, John M. Wilson, John Eble III, Frederick A. Ware, KIZER JADE M, WILSON JOHN M, EBLE III JOHN, WARE FREDERICK A, KIZER JADE M., WILSON JOHN M., WARE FREDERICK A.
Принадлежит: RAMBUS, INC.

A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.

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Номер записи: 75
27-12-2007 дата публикации

Memory Controller for Non-Homogeneous Memory System

Номер: US2007300038A1
Автор: WARE FREDERICK A, WARE FREDERICK A.
Принадлежит:

A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.

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Номер записи: 76
16-01-2014 дата публикации

Reducing Memory Refresh Exit Time

Номер: US20140016423A1
Автор: Frederick A. Ware, Brent Haukness, Ian P. Shaeffer, James E. Harris, WARE FREDERICK A, HAUKNESS BRENT, SHAEFFER IAN P, HARRIS JAMES E, WARE FREDERICK A., SHAEFFER IAN P., HARRIS JAMES E.
Принадлежит: RAMBUS INC

Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

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Номер записи: 77
24-05-2016 дата публикации

Configurable, power supply voltage referenced single-ended signaling with ESD protection

Номер: US0009350421B2
Автор: John W. Poulton, Frederick A. Ware, Carl W. Werner, POULTON JOHN W, WARE FREDERICK A, WERNER CARL W, POULTON JOHN W., WARE FREDERICK A., WERNER CARL W.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

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Номер записи: 78
01-05-2001 дата публикации

Apparatus and method for device timing compensation

Номер: US0006226754B1
Автор: Frederick A. Ware, Richard M. Barth, Donald C. Stark, Craig E. Hampel, Ely K. Tsern, Abhijit M. Abhyankar, WARE FREDERICK A, BARTH RICHARD M, STARK DONALD C, HAMPEL CRAIG E, TSERN ELY K, ABHYANKAR ABHIJIT M, WARE FREDERICK A., BARTH RICHARD M., STARK DONALD C., HAMPEL CRAIG E., TSERN ELY K., ABHYANKAR ABHIJIT M.
Принадлежит: Rambus Incorporated, RAMBUS INC, RAMBUS INCORPORATED

An electronic device with device timing constraints includes a set of connections coupled to an interconnect structure that carries row and column commands. A memory core stores data. A memory interface is connect to the set of connections and the memory core. The memory interface includes circuitry for generating memory core timing signals in accordance with the row commands and the column commands. The memory core timing signals have timing constraints to insure correct memory core operation. The memory interface circuitry includes individual delay components for adjusting the timing of selected timing signals of the memory core timing signals.

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Номер записи: 79
07-09-2004 дата публикации

Asynchronous, high-bandwidth memory component using calibrated timing elements

Номер: US0006788594B2
Автор: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, STARK DONALD C, WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E., STARK DONALD C.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

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Номер записи: 80
06-12-2007 дата публикации

COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS

Номер: US2007280393A1
Автор: WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит:

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

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Номер записи: 81
04-03-2014 дата публикации

Active calibration for high-speed memory devices

Номер: US0008667347B2
Автор: Jared L. Zerbe, Frederick A. Ware, Brian S. Leibowitz, ZERBE JARED L, WARE FREDERICK A, LEIBOWITZ BRIAN S, ZERBE JARED L., WARE FREDERICK A., LEIBOWITZ BRIAN S.
Принадлежит: Rambus Inc., ZERBE JARED L, WARE FREDERICK A, LEIBOWITZ BRIAN S, RAMBUS INC, ZERBE JARED L., WARE FREDERICK A., LEIBOWITZ BRIAN S., RAMBUS INC.

A system for calibrating timing for write operations between a memory controller and a memory device. During operation, the system identifies a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller. The system then transmits a test data pattern to the memory device within the time gap. The system subsequently uses the received test data pattern to calibrate a phase relationship between a received timing signal and data transmitted from the memory controller to the memory device during write operations.

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Номер записи: 82
26-03-2015 дата публикации

Protocol For Refresh Between A Memory Controller And A Memory Device

Номер: US20150085595A1
Автор: Frederick A. Ware, Brent Haukness, WARE FREDERICK A, HAUKNESS BRENT, WARE FREDERICK A.
Принадлежит:

The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

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Номер записи: 83
02-02-2012 дата публикации

PROTOCOL FOR REFRESH BETWEEN A MEMORY CONTROLLER AND A MEMORY DEVICE

Номер: US20120030420A1
Автор: Frederick A. Ware, Brent Haukness, WARE FREDERICK A, HAUKNESS BRENT, WARE FREDERICK A.
Принадлежит: RAMBUS INC.

The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

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Номер записи: 84
04-02-2014 дата публикации

Periodic calibration for communication channels by drift tracking

Номер: US0008644419B2
Автор: Craig E. Hampel, Frederick A. Ware, Richard E. Perego, HAMPEL CRAIG E, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E., WARE FREDERICK A., PEREGO RICHARD E.
Принадлежит: Rambus Inc., HAMPEL CRAIG E, WARE FREDERICK A, PEREGO RICHARD E, RAMBUS INC, HAMPEL CRAIG E., WARE FREDERICK A., PEREGO RICHARD E., RAMBUS INC.

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N-1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

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Номер записи: 85
14-06-2011 дата публикации

Memory controller for non-homogeneous memory system

Номер: US0007962715B2
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.

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Номер записи: 86
13-01-2009 дата публикации

Memory system and device with serialized data transfer

Номер: US0007478181B2
Автор: Richard E. Perego, Frederick A. Ware, PEREGO RICHARD E, WARE FREDERICK A, PEREGO RICHARD E., WARE FREDERICK A.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

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Номер записи: 87
26-05-2016 дата публикации

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

Номер: US20160147281A1
Автор: Frederick A. Ware, Robert E. Palmer, John W. Poulton, Andrew M. Fuller, WARE FREDERICK A, PALMER ROBERT E, POULTON JOHN W, FULLER ANDREW M, WARE FREDERICK A., PALMER ROBERT E., POULTON JOHN W., FULLER ANDREW M.
Принадлежит:

In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.

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Номер записи: 88
13-02-2014 дата публикации

MEMORY MODULE THREADING WITH STAGGERED DATA TRANSFERS

Номер: US2014047155A1
Автор: ZHENG HONGZHONG, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит:

A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

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Номер записи: 89
15-07-2008 дата публикации

Periodic calibration for communication channels by drift tracking

Номер: US0007400671B2
Автор: Craig E. Hampel, Frederick A. Ware, Richard E. Perego, HAMPEL CRAIG E, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E., WARE FREDERICK A., PEREGO RICHARD E.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameters, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N-1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as is fixed codes less than 16 bytes, and for example as short as 2 bytes long.

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Номер записи: 90
22-04-2008 дата публикации

Asynchronous, high-bandwidth memory component using calibrated timing elements

Номер: US0007362626B2
Автор: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, STARK DONALD C, WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E., STARK DONALD C.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

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Номер записи: 91
01-04-2008 дата публикации

Apparatus and method for pipelined memory operations

Номер: US0007353357B2
Автор: Richard M. Barth, Ely K. Tsern, Mark A. Horowitz, Donald C. Stark, Craig E. Hampel, Frederick A. Ware, John B. Dillon, BARTH RICHARD M, TSERN ELY K, HOROWITZ MARK A, STARK DONALD C, HAMPEL CRAIG E, WARE FREDERICK A, DILLON LEGAL REPRESENTATIVE NA, BARTH RICHARD M., TSERN ELY K., HOROWITZ MARK A., STARK DONALD C., HAMPEL CRAIG E., WARE FREDERICK A., DILLON, LEGAL REPRESENTATIVE NANCY DAVID
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.

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Номер записи: 92
12-06-2014 дата публикации

LOW-COST TRACKING SYSTEM

Номер: US20140159961A1
Автор: Frederick A. Ware, Farshid Aryanfar, John Brooks, WARE FREDERICK A, ARYANFAR FARSHID, BROOKS JOHN, WARE FREDERICK A.
Принадлежит: Rambus Inc.

A method of tracking a second electronic device with respect to a first electronic device is disclosed. The method includes transmitting a first waveform of a first frequency along a first fixed path associated with the first device. A second waveform having a frequency based on the first frequency is wirelessly transmitted from the first device to the second device along a first wireless path. The second waveform is wirelessly transmitted from the second device to the first device along a second wireless path. The first and second waveforms are received at the phase comparator circuit. A first phase relationship of the received first waveform is then compared to a second phase relationship of the received re-transmitted waveform. A coordinate of the second device is determined with respect to a reference coordinate based on the comparing.

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Номер записи: 93
06-01-2004 дата публикации

Method and apparatus for coordinating memory operations among diversely-located memory components

Номер: US0006675272B2
Автор: Frederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel, WARE FREDERICK A, TSERN ELY K, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., TSERN ELY K., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., RAMBUS INC, RAMBUS INC.

A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

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Номер записи: 94
07-09-2004 дата публикации

Asynchronous, high-bandwidth memory component using calibrated timing elements

Номер: US0006788593B2
Автор: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, STARK DONALD C, WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E., STARK DONALD C.
Принадлежит: Rambus, Inc., RAMBUS INC, RAMBUS, INC.

Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.

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Номер записи: 95
19-08-2008 дата публикации

Communication channel calibration for drift conditions

Номер: US0007415073B2
Автор: Frederick A. Ware, Richard E. Perego, Craig E. Hampel, WARE FREDERICK A, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит: Rambus, Inc., RAMBUS INC, RAMBUS, INC.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

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Номер записи: 96
05-03-2013 дата публикации

Memory module with termination component

Номер: US0008391039B2
Автор: Frederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel, WARE FREDERICK A, TSERN ELY K, PEREGO RICHARD E, HAMPEL CRAIG E, WARE FREDERICK A., TSERN ELY K., PEREGO RICHARD E., HAMPEL CRAIG E.
Принадлежит: Rambus Inc., WARE FREDERICK A, TSERN ELY K, PEREGO RICHARD E, HAMPEL CRAIG E, RAMBUS INC, WARE FREDERICK A., TSERN ELY K., PEREGO RICHARD E., HAMPEL CRAIG E., RAMBUS INC.

A module having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data thereto, the first data to be stored in a memory array of the first memory device during a write operation. A second signal line is coupled to the second memory device to provide thereto, the second data to be stored in a memory array of the second memory device during the write operation. A control signal path is coupled to the first memory device, the second memory device and the termination component such that a write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component, wherein the write command specifies the write operation.

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Номер записи: 97
24-08-2004 дата публикации

Method and apparatus for controlling a read valid window of a synchronous memory device

Номер: US0006782459B1
Автор: Frederick A. Ware, WARE FREDERICK A, WARE FREDERICK A.
Принадлежит: Rambus, Inc., RAMBUS INC, RAMBUS, INC.

A method and apparatus are shown for increasing a propagation delay that may be tolerated between a memory controller and a memory device. The present invention provides for selection between two data paths for each word, where a first data path latches the data word from a DQS domain on a falling edge of a CLK0 domain and a second data patch latches the data word from the DQS domain on a rising edge of the CLK0 domain. Selection of the first data path permits larger relative propagation delays between the controller and memory to be accommodated without loss of data. Further, multi-cycle source synchronous timing logic may be employed that provides for the capture of data words on rising and falling edges of successive cycles of the DQS domain and storage for an additional cycle of the DQS domain to extend the period of time that each data word from the DQS domain is available and valid for the CLK0 domain. Selection of the first data path may also be used to accommodate shorter relative ...

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Номер записи: 98
16-04-2015 дата публикации

PROTOCOL FOR MEMORY POWER-MODE CONTROL

Номер: US20150103610A1
Автор: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty, ELLIS WAYNE F, RICHARDSON WAYNE S, BANSAL AKASH, WARE FREDERICK A, LAI LAWRENCE, KASAMSETTY KISHORE VEN, ELLIS WAYNE F., RICHARDSON WAYNE S., WARE FREDERICK A.
Принадлежит:

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

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Номер записи: 99
01-07-2014 дата публикации

Memory modules and devices supporting configurable data widths

Номер: US8769234B2
Автор: PEREGO RICHARD E, STARK DONALD C, WARE FREDERICK A, TSERN ELY K, HAMPEL CRAIG E, PEREGO RICHARD E., STARK DONALD C., WARE FREDERICK A., TSERN ELY K., HAMPEL CRAIG E.
Принадлежит: RAMBUS INC, RAMBUS INC.

Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations.

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Номер записи: 100
19-01-2012 дата публикации

Synthetic Pulse Generator for Reducing Supply Noise

Номер: US20120013361A1
Автор: Ware Frederick A.
Принадлежит: RAMBUS INC

A source-terminated transmitter conveys digital signals over a short channel as a voltage signal that transitions between levels for each symbol transition. The transmitter produces each transition by issuing a charge pulse onto the channel, and thus creates a series of charge pulses. The number of charge pulses per unit time is proportional to the transition density of the signal, as no charge pulse is required between like symbols. The supply current used to deliver the pulses is therefore dependent upon the data pattern. This data dependency can induce supply fluctuations, which can in turn cause errors and otherwise reduce performance. The transmitter issues a synthetic charge pulse for each adjacent pair of like symbols to reduce the data dependency of the supply current. The synthetic pulses can be scaled to match the charge required for symbol transitions on a given channel. 1. An integrated circuit comprising:a data source having a data node to convey symbols as a serial data stream; an input node, coupled to the data node, to receive the serial data stream;', 'first and second output nodes to convey the serial data stream as a series of symbols;', 'a first termination resistor connected between the first output node and a first signal pad; and', 'a second termination resistor connected between the second output node and a second signal pad;, 'a transmitter coupled to first and second power-supply nodes, the transmitter havinga control circuit coupled to the first and second power-supply nodes and including a current-control port, the control circuit to draw charge from the first power-supply node to the second power-supply node responsive to a current-control signal; anda decoder coupled to the data source and the current-control port, the decoder to adjust the current-control signal to alter the charge drawn over time in proportion to a concentration of adjacent like symbols in the serial data stream.2. The integrated circuit of claim 1 , further ...

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Номер записи: 101
16-02-2012 дата публикации

ASYNCHRONOUS PIPELINED MEMORY ACCESS

Номер: US20120039138A1
Автор: Hampel Craig E., Stark Donald C., Tsern Ely K., Ware Frederick A.
Принадлежит:

A plurality of control signals are asserted within an asynchronous integrated circuit memory device in response to each transition of a memory access initiation signal to effect pipelined memory access operations. 1. A method of operation within an integrated circuit memory device , the method comprising:asserting a plurality of control signals in response to a first transition of a memory access initiation signal to effect a first memory read operation, including asserting a first control signal, a second control signal, a third control signal and a fourth control signal after respective delays relative to the first transition of the memory access initiation signal;storing a first address within a first address register in response to the assertion of the first control signal;transferring the first address from the first address register to a second address register in response to the assertion of the second control signal;providing the first address from the second address register to a memory core to enable the memory core to provide first read data corresponding to the first address;storing the first read data from the memory core within a read register in response to the assertion of the third control signal; andenabling an output driver to output the first read data onto an external signaling path in response to the assertion of the fourth control signal.2. The method of wherein the first address comprises a first column address and wherein providing the first address to the memory core to enable the memory core to provide the first read data comprises providing the first column address to the memory core to enable retrieval of a column of data from sense amplifiers of the memory core.3. The method of wherein asserting the plurality of control signals in response to the first transition of a memory access initiation signal further includes asserting a fifth control signal after a respective delay relative to the first transition of the memory access initiation ...

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Номер записи: 102
08-03-2012 дата публикации

Configurable, Power Supply Voltage Referenced Single-Ended Signaling with ESD Protection

Номер: US20120057261A1
Автор: Poulton John W., Ware Frederick A., Werner Carl W.
Принадлежит: RAMBUS INC.

A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply. 1. A circuit to be coupled to a power supply , comprising:first and second terminals, the second terminal to be at a power supply voltage after being coupled to the power supply; anda transmitter configured to transmit a signal via the first terminal, the signal having a voltage level that is referenced to the power supply voltage and that swings substantially symmetrically above and below the power supply voltage.2. The circuit of claim 1 , wherein the second terminal is part of a signal return path for the signal.3. The circuit of claim 1 , wherein the power supply voltage is a ground voltage.4. The circuit of claim 1 , wherein the power supply voltage is other than a ground voltage.5. The circuit of claim 1 , wherein the circuit transmits the signal while drawing a power supply current from the power supply that is substantially independent of the voltage level of the signal.6. The circuit of claim 1 , further comprising:a first charge pump drawing a first supply current from the power supply while the voltage level of the signal is at or near a first voltage; anda second charge pump drawing a second current from the power supply while the voltage level of the signal is at or near a second voltage, the first voltage and the second voltage being substantially symmetrical with respect to the power supply voltage and the second current being substantially equal to the first current.7. The circuit of claim 1 , wherein the circuit is formed on a semiconductor substrate mounted on a packaging substrate having a power plane ...

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Номер записи: 103
15-03-2012 дата публикации

SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

Номер: US20120063524A1
Автор: Hampel Craig E., Stott Bret G., Ware Frederick A.
Принадлежит:

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information. 1. A signaling system comprising:a first integrated circuit (IC) chip to receive a data signal and a strobe signal and having circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device;a signaling link; anda second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip, the second IC chip having delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.2. The signaling system of wherein the first IC chip comprises a dynamic random access memory (DRAM) IC chip claim 1 , and the second IC chip comprises a memory controller IC chip.3. The signaling system of wherein the circuitry to sample the data signal comprises oversampling circuitry.4. The signaling system of wherein the strobe signal has respective ...

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Номер записи: 104
21-06-2012 дата публикации

COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS

Номер: US20120155526A1
Автор: Hampel Craig E., Perego Richard E., Ware Frederick A.
Принадлежит: Rambus, Inc.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component. 1. A method for calibrating a parameter of a communication channel , the method comprising:establishing an operation value for the parameter using a first calibration sequence transmitted across the communication channel;communicating data over the communication channel using the operation value;tracking adjustment information using second calibration sequences transmitted two or more times interspersed with said communicating data, across the communication channel;computing a drift value for the parameter using the adjustment information; andadjusting the operation value for the parameter using the drift value.2. The method of claim 1 , including storing requests to communicate data over the communication channel in a cache memory during said second calibration sequences.3. The method of claim 1 , including using said second calibration sequences N times during said operation of the communication channel claim 1 , and producing a pass or fail determination during each use of the second calibration sequences; andafter the Nth second calibration sequence, decrementing ...

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Номер записи: 105
21-06-2012 дата публикации

Memory Module With Reduced Access Granularity

Номер: US20120159061A1
Автор: Craig E. Hampel, Frederick A. Ware
Принадлежит: RAMBUS INC

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

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Номер записи: 106
05-07-2012 дата публикации

MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE

Номер: US20120170399A1
Автор: Bellows Chad A., Lai Lawrence, Richardson Wayne S., Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. 1. A memory device , comprising:a request interconnect operable to receive commands from a master device;first, second, third and fourth storage arrays;a first data interconnect operable to output data to the master device from the first and third storage arrays;a second data interconnect operable to output data to the master device from the second and fourth storage arrays;row access circuitry operable to open a corresponding row in each of the first and fourth storage arrays in response to a first common row access command received at the request interconnect, and to open a corresponding row in each of the second and third storage arrays in response to a second common row access command received at the request interconnect; andcolumn access circuitry operable to access first data in the opened row in the first storage array according to a first externally-supplied column address, second data in the opened row in the second storage array according to a second externally-supplied column address, third data in the opened row in the third storage array according to a third externally-supplied column address, ...

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Номер записи: 107
05-07-2012 дата публикации

Method and Apparatus for Indicating Mask Information

Номер: US20120173810A1
Автор: Abhyankar Abhijit M., Barth Richard M., Davis Paul G., Gasbarro James A., Hampel Craig E., Nguyen David, Stark Donald C., Ware Frederick A.
Принадлежит:

An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data. 1. An apparatus for controlling a dynamic random access memory (DRAM) , the apparatus comprising: a first code to indicate that first data is to be written to the DRAM, wherein the first code is to be registered by the DRAM at one or more edges of an external clock signal received by the DRAM;', 'a column address to indicate a column location of a memory core in the DRAM where the first data is to be written, wherein the column address is to be registered by the DRAM at one or more edges of the external clock signal;', the mask information indicates whether certain portions of the first data is to be transmitted to the DRAM; and', 'if the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent over the subset of wires after the second code is sent over the subset of wires, wherein the mask information is to be registered by the DRAM at one or more edges of the external clock signal; and, 'a second code to indicate whether mask information for the first data will be sent to the DRAM, the second code being sent over a subset of wires of the first plurality of wires, wherein, 'the interface to ...

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Номер записи: 108
12-07-2012 дата публикации

Memory Component Having Write Operation with Multiple Time Periods

Номер: US20120179866A1
Автор: Davis Paul G., Hampel Craig E., Ware Frederick A.
Принадлежит:

A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period. 1. A method of operation of a memory controller chip that controls the operation of a memory chip that includes a memory core having dynamic random access memory cells , the method comprising:sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation;after sending the write command, waiting for a first time period corresponding to a time period during which the write command is stored by the memory chip; andsending data associated with the write operation to a second interface of the memory chip, wherein sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.2. The method of claim 1 , further comprising sending mask information that indicates to the memory chip whether to mask portions of the data to be written to the memory core of the memory chip during the write operation.3. The method of claim 2 , ...

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Номер записи: 109
12-07-2012 дата публикации

SHARED ACCESS MEMORY SCHEME

Номер: US20120179880A1
Автор: Kuchibhotla Venu M., Linstadt John E., Ware Frederick A.
Принадлежит:

A memory device loops back control information from one interface to another interface to facilitate sharing of the memory device by multiple devices. In some aspects, a memory controller sends control and address information to one interface of a memory device when accessing the memory device. The memory device may then loop back this control and address information to another interface that is used by another memory controller to access the memory device. The other memory controller may then use this information to determine how to access the memory device. In some aspects a memory device loops back arbitration information from one interface to another interface thereby enabling controller devices that are coupled to the memory device to control (e.g., schedule) accesses of the memory device. 1. A memory controller device , comprising:a first memory interface configured to receive first control information from a first memory device, wherein the first control information indicates that another memory controller device accesses the first memory device;a second memory interface; andan access control circuit configured to access the first memory device via the first memory interface based on the first control information, and further configured to access a second memory device via the second memory interface.2. The memory controller device of claim 1 , wherein:in a first configuration, the access control circuit is configured to receive the first control information from the first memory device via the first memory interface and send second control information to the second memory device via the second memory interface; andin a second configuration, the access control circuit is configured to send third control information to the first memory device via the first memory interface and receive fourth control information from the second memory device via the second memory interface.3. The memory controller device of claim 1 , wherein the first control information ...

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Номер записи: 110
26-07-2012 дата публикации

DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATION

Номер: US20120191943A1
Автор: Ware Frederick A.
Принадлежит: RAMBUS INC.

A dynamic serialized command and address (CA) protocol with cycle-accurate matching between the PHY interface and the DFI interface is described. This CA protocol facilitates the use of a common memory-controller control logic with different CA bus configurations. With this CA protocol, CA packets for different memory operations have different formats. The size and the position of the CA packets vary relative to boundaries of DFI clock cycles, and the CA packets can extend beyond DFI clock cycle boundaries. In addition, there are at least two possible formats for a read or write memory operation. The appropriate format is selected based on the immediately preceding memory operation. 1. A memory device , comprising:a memory core including a plurality of memory cells; andan interface circuit to receive a memory operation command that specifies a memory operation pertaining to an access of the memory core, wherein the memory operation command is specified in a packet that includes the memory operation command multiplexed with address information corresponding to the access; andwherein a framing position marking the start of the packet is adjusted based at least on one prior received packet, received by the interface circuit.2. The memory device of claim 1 , wherein the interface circuit comprises a packet delineation mechanism to dynamically determine the format of the packet.3. The memory device of claim 2 , wherein the packet delineation mechanism determines the format of a received packet based at least on a corresponding memory operation specified in the packet.4. The memory device of claim 2 , wherein the packet delineation mechanism determines the format of a received packet based at least on the memory operation specified in an immediately preceding packet.5. The memory device of claim 1 , wherein the memory operation includes one of an activate claim 1 , precharge claim 1 , read claim 1 , and write operation.6. The memory device of claim 5 , wherein memory ...

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Номер записи: 111
23-08-2012 дата публикации

MEMORY CONTROLLER

Номер: US20120213020A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal. 1. A memory controller component that generates a timing signal , the memory controller component to control a dynamic random access memory component (DRAM) , the memory controller component comprising: write data to be sampled by the DRAM on one more edges of the timing signal, the timing signal requiring a first time interval to propagate from the memory controller component to the DRAM;', 'a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and', 'a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data; and, 'transmit circuitry to transmit, to the DRAMadjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust transmit timing of the write data and timing of the timing signal based on a difference between the first and second time intervals such that a rising edge of the timing signal at the DRAM is aligned with a rising edge of the first clock signal at the DRAM.2. The memory controller component of claim 1 , wherein the write data accompanies the timing signal while the write data and the timing signal propagate from the memory controller component to the DRAM.3. The memory controller component of claim 1 , wherein the timing signal is a strobe signal.4. The ...

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Номер записи: 112
23-08-2012 дата публикации

METHOD OF OPERATION OF A MEMORY DEVICE AND SYSTEM INCLUDING INITIALIZATION AT A FIRST FREQUENCY AND OPERATION AT A SECOND FREQUENCEY AND A POWER DOWN EXIT MODE

Номер: US20120216059A1
Автор: Barth Richard M., Bystrom Todd W., Davis Paul G., Hampel Craig E., May Bradley A., Tsern Ely K., Ware Frederick A.
Принадлежит: RAMBUS INC.

Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device. 1. A method of operation of an integrated circuit controller device that controls a dynamic random access memory (DRAM) device that has an array of DRAM memory cells , the method comprising:providing a value to the DRAM device, wherein the value represents a time at which the DRAM device is ready to receive a command when exiting from a power down mode, wherein the DRAM device stores the value in a programmable register; andproviding the command to the DRAM device, wherein the command specifies an access to the array.2. The method of claim 1 , wherein the command specifies activation of a row of the array.3. The method of claim 1 , wherein the command specifies a write operation and the method further comprises:providing an address of the array, the address being associated with the command that specifies the write operation; andproviding data to the DRAM device, wherein the data is associated with the command that specifies the write operation, wherein the data is to be stored at the address of the array.4. The method of claim 1 , wherein the command specifies a read operation and the method further comprises:providing an address of the array, the address being associated with the command that specifies the read operation; andreceiving data from the DRAM device, wherein the data is associated with the command that specifies a read operation, wherein the data is stored at the ...

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Номер записи: 113
30-08-2012 дата публикации

RECONFIGURABLE MEMORY CONTROLLER

Номер: US20120221769A1
Автор: Kuchibhotla Venu Madhav, Linstadt John Eric, Ware Frederick A.
Принадлежит: RAMBUS INC.

Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data. 1. A memory controller , comprising:signal connectors to electrically couple to a communication path that includes multiple links; andan interface circuit electrically coupled to the signal connectors, wherein, in a first operating mode, the interface circuit is to communicate with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path; andwherein, in a second operating mode, the interface circuit is to communicate with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.2. The memory controller of claim 1 , wherein the first memory device is of a different type than the second memory device.3. The memory controller of claim 1 , wherein the first memory device includes dynamic random access memory (DRAM) and the second memory device includes flash memory.4. The memory controller of claim 1 , further comprising a register to store information specifying a given operating mode claim 1 , which can be the first operating mode or the second ...

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Номер записи: 114
30-08-2012 дата публикации

Bit-replacement technique for dram error correction

Номер: US20120221902A1
Автор: Ely Tsern, Frederick A. Ware, Thomas Vogelsang
Принадлежит: RAMBUS INC

The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.

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Номер записи: 115
20-09-2012 дата публикации

Memory system with independently adjustable core and interface data rates

Номер: US20120239898A1
Автор: Frederick A. Ware
Принадлежит: Individual

An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

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Номер записи: 116
20-09-2012 дата публикации

Unidirectional Error Code Transfer for Both Read and Write Data Transmitted via Bidirectional Data Link

Номер: US20120240010A1
Автор: Wang Yuanlong, Ware Frederick A.
Принадлежит:

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition. 1. (canceled)2. A memory controller integrated circuit , comprising:a bidirectional link interface operable to transmit write data to a memory device and to receive read data from the memory device;encoder logic operable to compute a memory-controller-version of error-detection information for each of the write data and the read data; anda unidirectional link interface operable to receive a memory-device-version of error-detection information from the memory device for each of the write data and the read data;wherein the memory controller integrated circuit is operable to perform asymmetric error detection by comparing each memory-controller-version of error-detection information with a corresponding memory-device-version of error-detection information received via the unidirectional link interface, and by indicating an error condition in the event of mismatch.3. The memory controller integrated circuit of claim 2 , wherein each memory-controller-version of error-detection information and each memory-device-version of the error-detection information comprises a ...

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Номер записи: 117
18-10-2012 дата публикации

CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM

Номер: US20120262998A1
Автор: Eble, III John, Kizer Jade M., Ware Frederick A., Wilson John M.
Принадлежит: RAMBUS INC.

Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal. 1. (canceled)2. An integrated circuit device comprising: a clock signal,', 'control signals including first and second control signals, the first control signals encoding a write command to indicate that write data be written to the DRAM, the second control signals encoding a read command to indicate that read data be output from the DRAM, the control signals being registered by the DRAM at one or more edges of the clock signal, and', 'a timing reference signal, the write data being registered by the DRAM at one or more edges of the timing reference signal, and', 'the first interface to receive, from the DRAM, a write calibration signal that indicates a phase difference between the clock signal and the timing reference signal; and, 'a first interface configured to transmit, to a dynamic random access memory (DRAM)a second interface configured to transmit the write data associated with the write command and sample the read output from the DRAM, wherein the write data is transmitted using a first internal clock signal having a phase offset that is set based on the received write calibration signal, and the read data is sampled using a second internal clock signal having a phase offset based on a transmitted pattern received from the DRAM.3. The device of claim 2 , wherein the second interface includes a read data receive circuit configured to adjust the phase offset of the second internal clock signal based on results derived from sampling the transmitted pattern received from the DRAM.4. The ...

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Номер записи: 118
08-11-2012 дата публикации

Low Power Memory Device

Номер: US20120281489A1
Автор: Hampel Craig E., Tsern Ely K., Ware Frederick A.
Принадлежит: RAMBUS INC.

“A method of operation within a memory device comprises receiving address information and corresponding enable information. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled.” 1. (canceled)2. A memory device comprising a request interface , a bank of memory , and circuitry operable to service memory commands received at the request interface , the memory device further comprising a register operable to store information and circuitry operable to perform refresh for a variable portion of the bank of memory according to the state of the information stored in the register.3. The memory device of claim 2 , where the request interface is operable to receive a refresh command and where the memory device is operable to limit application of the refresh command received at the request interface according to the state of the information.4. The memory device of claim 2 , where the request interface is operable to receive a self-refresh command and where the memory device is operable to limit application of the received self-refresh command to the variable portion according to the state of the information.5. The memory device of claim 2 , where the request interface is operable to receive an auto-refresh command and where the memory device is operable to limit application of the received auto-refresh command to the variable portion according to the state ...

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Номер записи: 119
15-11-2012 дата публикации

MEMORY CONTROLLER WITH SELECTIVE DATA TRANSMISSION DELAY

Номер: US20120287725A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A DRAM controller component generates a timing signal and transmits, to a DRAM, (i) write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, (ii) a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and (iii) a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval. 1. A memory controller component that generates a timing signal , the memory controller component to control a dynamic random access memory component (DRAM) , the memory controller component comprising: write data to be sampled by the DRAM on one or more edges of the timing signal, the write data requiring a first time interval to propagate from the memory controller component to the DRAM;', 'a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and', 'a write command to be sampled by the DRAM on one or more edges of the first clock signal, the write command associated with the write data;, 'transmit circuitry to transmit, to the DRAMa plurality of delay elements coupled in series to respectively generate a plurality of incrementally delayed signals; anda multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.2. The memory controller component of claim 1 , wherein the delay of ...

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Номер записи: 120
24-01-2013 дата публикации

MEMORY CONTROLLER WITH ADJUSTABLE WIDTH STROBE INTERFACE

Номер: US20130021857A1
Автор: Kizer Jade M., Koya Yoshihiro, Ware Frederick A.
Принадлежит:

A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices. 123-. (canceled)24. A method of operation in a memory controller comprising:generating a mode control signal to specify at least one of a first and second mode; (i) issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, the first data transfer involving a full data width of the first memory device; and', '(ii) generating a strobe signal to accompany data associated with the first data transfer; and, 'wherein for the first mode, the memory controller is configured to operate by (i) issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices, the second data transfer involving a full width that includes data widths of both the first and second memory devices; and', '(ii) issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices., 'wherein for the second mode, the controller is configured to operate by25. The method of wherein the first ...

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Номер записи: 121
07-02-2013 дата публикации

Techniques for Interconnecting Stacked Dies Using Connection Sites

Номер: US20130032950A1
Автор: Tsern Ely, Vogelsang Thomas, Ware Frederick A.
Принадлежит: RAMBUS INC.

An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites. 1. An integrated circuit die , comprising:conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof; anda first core circuit located outside the contiguous region, wherein the first core circuit is coupled to at least one of the connection sites.2. The integrated circuit die of claim 1 , wherein the contiguous region is configured as a connection stripe extending across the integrated circuit die.3. The integrated circuit die of claim 1 , further comprising:alignment circuitry dynamically configurable to couple a first subset of the connection sites to the first core circuit and to decouple a second subset of the connection sites from the first core circuit.4. The integrated circuit die of claim 3 , wherein the alignment circuitry is additionally dynamically configurable to decouple the first subset of the connection sites from the first core circuit and to couple the second subset of the connection sites to the first core circuit.5. The integrated circuit die of claim 3 , wherein the alignment circuitry is dynamically configurable to decouple the second subset of the connection sites from every core circuit on the integrated circuit die.6. The integrated circuit die of claim 3 , further comprising:a second core circuit, wherein the alignment circuitry is additionally dynamically configurable to couple the first subset of the connection sites to the second core circuit and to couple the second subset of the connection sites to the first core circuit.7. The integrated circuit die of claim 6 , wherein the alignment circuitry is additionally dynamically configurable to decouple the first ...

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Номер записи: 122
14-03-2013 дата публикации

Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data to Account for Receive-Clock Drift

Номер: US20130064023A1
Автор: Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift. 1. A memory controller to control a memory device , the memory controller comprising:a write circuit operable to transmit at least one of a write-timing reference signal and a write-data signal having a write-signal phase;a read circuit operable to receive a read signal having a read-signal phase from the memory device; anda phase comparator coupled to the write circuit and operable to control the write-signal phase responsive to the read-signal phase.2. The memory controller of claim 1 , wherein the write circuit transmits the write-timing reference signal and the write-data signal claim 1 , and maintains a fixed phase relationship between the write-timing reference signal and the write-data signal.3. The memory controller of claim 2 , wherein the write-timing reference signal is a strobe signal.4. The memory controller of claim 1 , wherein the phase comparator is coupled to the read circuit and operable to control a read-clock phase responsive to the read-signal phase.5. The memory controller of claim 1 , wherein the write circuit is operable to time the write-data signal to the write-timing reference signal.6. The memory controller of claim 5 , wherein the write circuit further comprises a skip circuit to retime the write-data signal from a first clock domain to a second clock domain established by the write-timing reference signal.7. The memory controller of claim 6 , wherein the read signal includes a read-timing reference signal and a ...

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Номер записи: 123
04-04-2013 дата публикации

FAST-WAKE MEMORY

Номер: US20130083611A1
Автор: Leibowitz Brian S., Ware Frederick A., Zerbe Jared L.
Принадлежит:

One or more timing signals used to time data and command transmission over high-speed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different-frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links. 1. A method of operation within a memory controller , the method comprising:outputting a first memory access command via a first command signaling interface in response to a first clock signal during an exit from a first power mode; andoutputting a second memory access command via a second command signaling interface in response to a second clock signal during a second power mode.2. The method of wherein the memory controller consumes more power in the second power mode than in the first power mode.3. The method of wherein the first clock signal has a lower frequency ...

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Номер записи: 124
23-05-2013 дата публикации

MEMORY CONTROLLER AND METHOD FOR TUNED ADDRESS MAPPING

Номер: US20130132704A1
Автор: Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory system maps physical addresses to device addresses in a way that reduces power consumption. The system includes circuitry for deriving efficiency measures for memory usage and selects from among various address-mapping schemes to improve efficiency. The address-mapping schemes can be tailored for a given memory configuration or a specific mixture of active applications or application threads. Schemes tailored for a given mixture of applications or application threads can be applied each time the given mixture is executing, and can be updated for further optimization. Some embodiments mimic the presence of an interfering thread to spread memory addresses across available banks, and thereby reduce the likelihood of interference by later- introduced threads. 1. A method of operation in a memory controller , the method comprising:relating a physical-address field to memory-device addresses using a first mapping;measuring a first access energy associated with the first mapping;relating the physical-address field to the memory-device addresses using a second mapping;measuring a second access energy associated with the second mapping; andselecting between the first and second mappings based upon the first and second access energies.2. The method of claim 1 , wherein measuring the first access energy includes determining a ratio of row-activate commands to memory transactions.3. The method of claim 1 , further comprising translating physical addresses in the physical-address field to the memory-device addresses according to the first and second mappings.4. The method of claim 3 , further comprising translating virtual addresses to the physical addresses in the physical-address field claim 3 , the translating including copying portions of the virtual addresses into a subfield of the physical-address field.5. The method of claim 4 , wherein the first and second mappings apply only to the subset of the physical-address field.6. The method of claim 1 , wherein the ...

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Номер записи: 125
30-05-2013 дата публикации

Unidirectional Error Code Transfer for Both Read and Write Data Transmitted Via Bidirectional Data Link

Номер: US20130139019A1
Автор: Wang Yuanlong, Ware Frederick A.
Принадлежит:

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition. 1. A memory device integrated circuit , comprising:a bidirectional link interface operable to transmit read data to a memory controller and to receive write data from the memory controller;encoder logic operable to compute a memory-device-version of error-detection information for each of the write data and the read data;a unidirectional link interface operable to transmit the memory-device-version of error-detection information to the memory controller for each of the write data and the read data; anderror detection logic to disable a write operation by the memory device integrated circuit when a comparison of first write-mask error-detection information received via a link from the memory controller with second write-mask error-detection information generated within the memory device integrated circuit indicates that an error has occurred.2. The memory device integrated circuit of claim 1 , further comprising:a sideband link interface operable to receive the first write-mask error-detection information from the memory controller.3. The memory device integrated ...

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Номер записи: 126
30-05-2013 дата публикации

Memory System With Error Detection And Retry Modes Of Operation

Номер: US20130139032A1
Автор: Horowitz Mark A., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data. 1. A memory integrated circuit to receive write data from a memory controller over a first external link and to receive control information from a memory controller over a second external link , the control information including at least one of control information associated with the write data , the memory integrated circuit comprising:a storage array to store the write data;a first electrical contact to couple to the first external signal link;a second electrical contact to couple to the second external signal link;circuitry to convey the write data from the first electrical contact to the storage array in association with the control information;logic to detect error in the control information; andlogic to detect error in the write data;wherein the memory device is to permit storage of the write data notwithstanding error in the write data but is to block storage of the write data in the storage array in response to error in the control information.2. The memory integrated circuit of claim 1 , further comprising at least one transmitter to transmit an error indication to the memory ...

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Номер записи: 127
13-06-2013 дата публикации

Reducing Power Consumption in a Memory System

Номер: US20130148447A1
Автор: Shaeffer Ian P., Ware Frederick A., Zerbe Jared L.
Принадлежит:

Components of a memory system, such as a memory controller or memory device, that operate in different power states to reduce the overall power consumption of the memory system. In some of the power states, distribution circuitry that distributes a timing signal within the components may be powered on when the output of the distribution circuitry is needed. In other power states, the distribution circuitry may be powered off when the output of the distribution circuitry is not needed. Additionally, power states in the memory device may be triggered off memory access commands issued by the memory controller. 1. A memory device comprising:a memory core;data interface circuitry to transfer data between the memory core and one or more ports of the memory device;distribution circuitry to distribute a timing reference signal to the data interface circuitry; andcontrol circuitry to power on the distribution circuitry in response to a memory access command that specifies access to the memory core.2. The memory device of claim 1 , wherein the distribution circuitry comprises current mode logic (CML) distribution circuitry and further comprising:bias circuitry to generate a bias voltage for the CML distribution circuitry, andwherein the control circuitry powers on the distribution circuitry by powering on the bias voltage for the CML distribution circuitry.3. The memory device of claim 1 , further comprising:a clock generation circuit to generate the timing reference signal,wherein the distribution circuitry distributes the timing reference signal generated by the clock generation circuit to the data interface circuitry, andwherein the control circuitry also powers on the clock generation circuit in response to the memory access command.4. The memory device of claim 1 , wherein the distribution circuitry comprises at least one of a clock buffer or a digitally controlled delay line (DCDL) that is powered on by the control circuitry in response to the memory access command.5. ...

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Номер записи: 128
04-07-2013 дата публикации

Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated Circuits

Номер: US20130168674A1
Автор: Ellis Wayne, Franzon Paul D., Vogelsang Thomas, Ware Frederick A.
Принадлежит: RAMBUS INC.

A three-dimensional integrated circuit (3D-IC) includes a stack of semiconductor wafers, each of which includes a substrate and a device layer. Programmable components, such as memory arrays or logic circuits, are formed within the device layers. Some of the programmable components are redundant, and can be substituted for defective components by programming passive memory elements in a separate conductive layer provided for this purpose. The separate conductive layer is devoid of active devices, and is therefore relatively reliable and inexpensive. 1. A three-dimensional integrated circuit (3D-IC) comprising:a first semiconductor substrate having a first device layer, the first device layer including first programmable components and a first control port coupled to the first programmable components, the first control port to selectively enable the first programmable components;a second semiconductor substrate disposed on and bonded to the first semiconductor substrate, the second semiconductor substrate having a second device layer that includes second programmable components and a second control port coupled to the second programmable components, the second control port to selectively enable the second programmable components, the second semiconductor substrate including conductive vias extending from the first control port through the second semiconductor substrate; anda conductive layer devoid of active devices and including first passive memory elements coupled to the first control port by the conductive vias and second passive memory elements coupled to the second control port.2. The 3D-IC of claim 1 , wherein the conductive layer is disposed on a third substrate bonded to the second semiconductor substrate.3. The 3D-IC of claim 2 , wherein the second substrate is of a semiconductor.4. The 3D-IC of claim 2 , wherein the conductive layer is in contact with the third substrate.5. The 3D-IC of claim 1 , wherein the first and second semiconductor substrates ...

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Номер записи: 129
04-07-2013 дата публикации

Facilitating Error Detection And Recovery In A Memory System

Номер: US20130173991A1
Автор: Leibowitz Brian S., Ware Frederick A.
Принадлежит:

The disclosed embodiments relate to a system for accessing a data word in a memory. During operation, the system receives a request to access a data word, wherein the request includes a physical address for the data word. Next, the system translates the physical address into a mapped address, wherein the translation process spreads out the data words and intersperses groups of consecutive error information between groups of consecutive data words. Finally, the system uses the mapped address to access the data word and corresponding error information for the data word from the memory. 1. A memory controller , comprising: a first address identifying a first memory array to store first data, and', 'a second address identifying a second memory array to store second data; and, 'a circuit to generate'} for storage in the first memory array, the first data and error information associated with second data, and', 'for storage in the second memory array, the second data and error information associated with first data., 'an interface to provide'}2. The memory controller of claim 1 , wherein the memory controller is configured to access a first data word from the first memory array in parallel with accessing error information for the first data word from the second memory array.3. The memory controller of claim 1 , wherein the memory controller further comprises circuitry for generating and checking the error information.4. The memory controller of claim 1 , wherein:the memory controller is configured to store unprotected data words without error information;data words with error information are stored in a first region of memory; andthe unprotected data words without error information are stored in a second region of memory.513-. (canceled)14. The memory controller of claim 1 , wherein:the memory controller further comprises an address-translation circuit that translates a physical address for a memory reference into a mapped address; andthe translation process intersperses ...

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Номер записи: 130
11-07-2013 дата публикации

STACKED MEMORY WITH REDUNDANCY

Номер: US20130176763A1
Автор: Franzon Paul D., Ware Frederick A.
Принадлежит: RAMBUS INC.

A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and stacked with a second integrated circuit memory chip. A redundant memory is shared by the first and second integrated circuit memory chips and has redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips. The stacked memory also includes a pin interface for coupling to an external integrated circuit memory controller and respective first and second signal paths. The first signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface. The second signal path is formed through the first and second integrated circuit memory chips and is coupled to the redundant memory and to the pin interface via the first signal path. 1. A stacked memory comprising:a first integrated circuit memory chip having first storage locations;a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip, the second integrated circuit memory chip having second storage locations;a redundant memory shared by the first and second integrated circuit memory chips, the redundant memory having redundant storage locations that selectively replace corresponding storage locations in the first or second integrated circuit memory chips;a pin interface for coupling to an external memory controller;a first signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the first signal path coupled to the pin interface; anda second signal path formed through the first and second integrated circuit memory chips and coupled to the redundant memory, the second signal path coupled to the pin interface via the first signal path.2. The stacked memory according to wherein the redundant memory comprises a redundant integrated ...

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Номер записи: 131
11-07-2013 дата публикации

MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE

Номер: US20130176800A1
Автор: Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. 120-. (canceled)21. A memory controller comprising: address information indicating a storage address for first write data; and', 'a first timing signal to time reception of the address information within a first dynamic random access memory (DRAM), the first timing signal requiring a first propagation time to propagate from the memory controller to the first DRAM;, 'first circuitry to output a chain of delay elements to generate a plurality of delayed timing signals, and', 'first select circuitry to select, as a transmission timing source of the second timing signal, a first one of the delayed timing signals, wherein the memory controller is operable in a calibration mode to enable the first select circuitry to select the first one of the delayed timing signals to time transmission of the second timing signal, wherein, during the calibration mode, the second circuitry outputs multiple delayed versions of the timing signals and selects, as the first one of the delayed timing signals, one of the delayed timing signals that compensates for mismatch between the first and ...

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Номер записи: 132
01-08-2013 дата публикации

Early Read After Write Operation Memory Device, System And Method

Номер: US20130194879A1
Автор: Perego Richard E., Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path. 1. (canceled)2. A memory controller to control operation in a memory device having bank groups , the memory controller comprising:an interface to output commands to the memory device, the commands including at least three commands comprising a write command to a bank of a first bank group, a second command, and a read command to a bank of a second bank group, the commands ordered in the manner stated prior to being output; andlogic to selectively reorder output of the commands, such that the interface is to output the read command prior to the second command.3. The memory controller of claim 2 , wherein the memory controller is to transmit each of the commands to the memory device over an interconnect in an associated time slot claim 2 , and wherein the logic to selectively reorder the output of the commands is to adjust order in which commands are transmitted to the memory device so as to advance the read command to an earlier time slot dependent on a condition where the read command is directed to a different bank group than the write command.4. The memory controller of claim 2 , ...

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Номер записи: 133
08-08-2013 дата публикации

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

Номер: US20130201770A1
Автор: Harris James Edward, Shaeffer Ian P., Vogelsang Thomas, Ware Frederick A.
Принадлежит:

Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. 1. A method of operation within a memory component , the method comprising:receiving, during a first command reception interval, a row command and a row address, the row address indicating a row of storage cells within the memory component;decoding the row address upon receiving the row command to select a row of storage cells within the memory component;receiving, during a second command reception interval and after decoding the row address has commenced, a first column command and a first column address, the first column address indicating a first column of data within a first subrow of storage cells included within the row of storage cells, and the first column command indicating a memory access operation to be carried out with respect to the first column of data; andtransferring a first subrow of data, including the first column of data, from the first subrow of storage cells to a first set of sense amplifiers in response to the first column command.2. The method of further comprising executing the memory access operation indicated by the first column command with respect to the first column of data after transferring the first subrow of data from the first subrow of storage cells to the first set of sense amplifiers.3. The method of wherein executing the memory access operation comprises transferring the first column of data from the first set of sense amplifiers to an output driver of the memory component in a memory read operation claim 2 , the output driver to output the first column of data from the memory component claim 2 , wherein an elapsed time between receipt of the first column ...

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Номер записи: 134
15-08-2013 дата публикации

MEMORY COMPONENTS AND CONTROLLERS THAT UTILIZE MULTIPHASE SYNCHRONOUS TIMING REFERENCES

Номер: US20130208818A1
Автор: Best Scott C., Shaeffer Ian, Ware Frederick A.
Принадлежит: RAMBUS INC.

Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal. 1. A memory device , comprising:a first circuit to receive a first external timing reference signal;a second circuit to receive a second external timing reference signal, the second timing reference signal to have a quadrature phase relationship with respect to the first timing reference signal; and,a plurality of receiver circuits to receive signals synchronously with respect to the first external timing reference signal and the second external timing reference signal, such that a first signal value is resolved using the first external timing reference signal and a second signal value is resolved using the second external timing reference signal.2. The memory device of claim 1 , wherein the first signal value is to be received during a first interval.3. The memory device of claim 1 , wherein the first external timing reference signal and the second external timing reference signal are clock signals.4. The memory device of claim 1 , wherein said quadrature phase relationship comprises a first edge of said first external timing reference signal occurring approximately halfway between a first edge of said second external timing reference signal and a successive second edge of said second ...

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Номер записи: 135
15-08-2013 дата публикации

Techniques for Storing Data and Tags in Different Memory Arrays

Номер: US20130212331A1
Автор: Frederick A. Ware
Принадлежит: RAMBUS INC

A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

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Номер записи: 136
29-08-2013 дата публикации

MEMORY ACCESS DURING MEMORY CALIBRATION

Номер: US20130227183A1
Автор: Shaeffer Ian, Ware Frederick A.
Принадлежит: RAMBUS INC.

A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus. 1. A method of controlling first and second ranks of memory devices , coupled to a memory controller , via data buses that include at least a first data bus and a second data bus both of which are coupled to a first memory device in the first memory rank and a second memory device in the second memory rank , the method comprising:performing a calibration operation that pertains to transmission of data between the first memory device and the memory controller via the first data bus; andwhile performing the calibration operation, transferring data, via the second data bus, between the second memory device and the memory controller.2. The method of claim 1 , wherein the data is transferred between the memory controller and a storage location of a selected sub-bank claim 1 , wherein the selected sub-bank is a sub-bank of a plurality of sub-banks of the second memory device.3. The method of claim 2 , further comprising transmitting a control signal to the second memory device claim 2 , the control signal specifying accessing claim 2 , via the second data bus claim 2 , the storage location of the selected sub-bank.4. The method of claim 1 , further comprising transmitting a control signal to the second memory device claim 1 , the control signal specifying settings of a routing circuit in the second memory device claim 1 , the routing circuit permitting access to a sub-bank of a plurality of sub-banks of the ...

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Номер записи: 137
05-09-2013 дата публикации

COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS

Номер: US20130230122A1
Автор: Hampel Craig E., Perego Richard E., Ware Frederick A.
Принадлежит: RAMBUS INC.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component. 1. A method of operation of an integrated circuit component , the method used for calibrating a parameter associated with transmission of data on a communication channel , the method comprising:transmitting a calibration sequence used to establish an operation value that represents the parameter;transmitting data in accordance with the operation value;determining adjustment information for the parameter, interspersed with said transmitting data over the communication channel;adjusting the operation value for the parameter using said adjustment information.2. The method of claim 1 , wherein the adjustment information indicates drift of the parameter during operation of the integrated circuit component.3. The method of claim 1 , including storing requests to transmit data over the communication channel during said determining.4. The method of claim 1 , comprising using a portion of addressable memory space of the integrated circuit component as a storage block to store patterns received in the calibration sequence.5. The method of claim 1 , wherein said determining ...

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Номер записи: 138
26-09-2013 дата публикации

MEMORY MODULE

Номер: US20130250706A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory module having memory components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective memory components, and the address/control signal path and clock signal path are coupled in common to all the memory components. The address/control signal path extends along the memory components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components. 1. A memory module comprising:a circuit board;a first plurality of memory components disposed on the circuit board, each of the memory components having an address/control input, a clock input, a data input and a strobe input;a termination structure disposed on the circuit board;an address/control signal path that extends from an edge of the circuit board to the termination structure, the address/control signal path being coupled along its length to the address/control input of each of the memory components such that control signals propagating toward the termination structure on the address/control signal path arrive at the address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components;a clock signal path extending from the circuit board edge and coupled along its length to the clock input of each of the memory components such that a clock signal propagating on the clock signal path arrives at the clock inputs of respective memory components at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the memory components, the clock signal indicating to the memory components respective times at which to sample the control ...

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Номер записи: 139
03-10-2013 дата публикации

MEMORY MODULE HAVING A WRITE-TIMING CALIBRATION MODE

Номер: US20130262757A1
Автор: Ware Frederick A.
Принадлежит: RAMBUS INC.

In memory module populated by memory components having a write-timing calibration mode, control information that specifies a write operation is received via an address/control signal path and write data corresponding to the write operation is received via a data signal path. Each memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the address/control signal path and outputting the write data on the data signal path. 1. A memory module comprising:a circuit board having a connector interface that enables the circuit board to be removably inserted into an interconnect socket, the circuit board including an address/control signal path, an address/control timing path, a plurality of data signal paths and a plurality of data timing paths; and a core of dynamic random access memory cells;', 'first circuitry coupled to the address/control signal path to receive control information that specifies a write operation and coupled to the address/control timing path to receive a clock signal that controls reception of the control information;', 'second circuitry coupled to the respective one of the data signal paths to receive write data corresponding to the write operation and coupled to a respective one of the data timing paths to receive a timing signal indicating that the write data is valid, the second circuitry being operable in a calibration mode to receive multiple delayed versions of the timing signal; and', 'third circuitry to output signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay time between outputting the control information on the address/control signal path and outputting the write data on the respective data signal ...

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Номер записи: 140
10-10-2013 дата публикации

Micro-Threaded Memory

Номер: US20130265842A1
Автор: Bellows Chad A., Hampel Craig E., Lai Lawrence, Richardson Wayne S., Ware Frederick A.
Принадлежит:

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval. 1. (canceled)2. A synchronous memory device , comprising:first and second bank groups, each comprising at least two storage arrays; and the request interface having row control circuitry to service two row activate commands addressed to respective storage arrays in different ones of the bank groups with a shorter intervening interval than the row control circuitry can service two row activate commands addressed to respective storage arrays in a same one of the bank groups,', 'the request interface having column control circuitry to service two column access commands directed to respective, active rows in respective storage arrays in different ones of the bank groups with a shorter intervening interval than the column control circuitry can service two column access commands directed to one or more active rows in a same one of the bank groups., 'a request interface to receive external commands corresponding to memory transactions, including row activate commands and column access commands, each addressed to one of the storage arrays,'}3. The synchronous memory device of claim 2 , further comprising a first data serialization register to receive read data responsive to column access commands addressed to the first bank group claim 2 , and a second data serialization register to receive read data responsive to column access commands addressed to the second bank group.4. The ...

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Номер записи: 141
24-10-2013 дата публикации

Memory Component with Terminated and Unterminated Signaling Inputs

Номер: US20130279278A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory component has a signaling interface, data input/output (I/O) circuitry, command/address (CA) circuitry and clock generation circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. The clock generation circuitry generates the first clock signal with a phase that establishes alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal. 1. A memory component comprising:a signaling interface having an on-die terminated data input/output (I/O), an unterminated input to receive command/address (CA) signals, a strobe input and a clock input, each to be coupled to a respective external signaling link;data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write date bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O;CA circuitry to sample the CA signals at the CA input, the sampling of the CA signals being timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively; andclosed-loop clock generation circuitry coupled to receive the second clock signal via the clock input and to generate the first clock signal with a phase that establishes, at the signaling interface, an ...

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Номер записи: 142
24-10-2013 дата публикации

STACKED MEMORY DEVICE WITH REDUNDANT RESOURCES TO CORRECT DEFECTS

Номер: US20130279280A1
Автор: Erickson Evan Lawrence, Franzon Paul Damian, Vogelsang Thomas, Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory device includes a stack of circuit layers, each circuit layer having formed thereon a memory circuit configured to store data and a redundant resources circuit configured to provide redundant circuitry to correct defective circuitry on at least one memory circuit formed on at least one layer in the stack. The redundant resources circuit includes a partial bank of redundant memory cells, wherein an aggregation of the partial bank of redundant memory cells in each of the circuit layers of the stack includes at least one full bank of redundant memory cells and wherein the redundant resources circuit is configured to replace at least one defective bank of memory cells formed on any of the circuit layers in the stack with at least a portion of the partial bank of redundant memory cells formed on any of the circuit layers in the stack. 1. A device , comprising: a memory circuit configured to store data; and', 'a redundant resources circuit configured to provide redundant circuitry to replace defective circuitry on at least one memory circuit arranged on at least one layer in the stack;, 'a stack of circuit layers, each circuit layer having formed thereonwherein the at least one layer can be a layer other than the layer having formed thereon the redundant resources circuit.2. The device of claim 1 ,wherein the memory circuit comprises at least one bank of memory cells;wherein the redundant resources circuit comprises a partial bank of redundant memory cells;wherein an aggregation of the partial bank of redundant memory cells in a plurality of the circuit layers of the stack comprises at least one full bank of redundant memory cells; andwherein the at least one full bank of redundant memory cells is configured to replace at least one bank of memory cells arranged on any of the circuit layers in the stack.3. The device of claim 2 , wherein the partial bank of redundant memory cells comprises a size that is 1/64 claim 2 , 1/32 claim 2 , 1/16 claim 2 , ⅛ claim 2 , ¼ ...

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Номер записи: 143
31-10-2013 дата публикации

Memory Modules and Devices Supporting Configurable Data Widths

Номер: US20130286706A1
Автор: Hampel Craig E., Perego Richard E., Stark Donald C., Tsern Ely K., Ware Frederick A.
Принадлежит:

Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations. 1. (canceled)2. An integrated-circuit memory device comprising:an input to receive memory-width configuration value;data terminals to exchange data with another device;a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; anda data control circuit coupling the physical banks with the data terminals, the data control circuit supporting first and second width configurations responsive to the configuration value; in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data terminals, and the plurality of physical banks collectively provide a first memory depth, and', 'in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks per read operation and the data terminals, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and', 'wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operation in the first width configuration and loads a second page of sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page., 'wherein3 ...

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Номер записи: 144
14-11-2013 дата публикации

PROTOCOL FOR MEMORY POWER-MODE CONTROL

Номер: US20130305074A1
Автор: Bansal Akash, Ellis Wayne F., Kasamsetty Kishore Ven, Lai Lawrence, Richardson Wayne S., Ware Frederick A.
Принадлежит: RAMBUS INC.

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command. 1. A memory device having a memory core , the memory device comprising:input receivers to receive commands and data; anda register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal.2. The memory device of claim 1 , wherein the input receivers include:a first set of receivers for receiving the commands; anda second set of receivers for receiving the data, wherein the subset of input receivers that are powered down are the second set of receivers.3. The memory device of claim 2 , wherein claim 2 , at a time in which the second set of receivers are powered down claim 2 , the first set of receivers receive a command.4. The memory device of claim 1 , wherein each input receiver of the input receivers comprises a current source; andwherein when a respective receiver is powered down, the current source corresponding to the respective receiver is powered down.5. The memory device of claim 1 , further including transmitters to output data claim 1 , wherein the register stores information that indicates whether the transmitters are powered down in response to the control signal.6. (canceled)7. The memory device of claim 1 ,wherein while the memory core is in one of a self-refresh state, an idle ...

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Номер записи: 145
14-11-2013 дата публикации

Memory Component that Samples Command/Address Signals in Response to Both Edges of a Clock Signal

Номер: US20130305079A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory component has a signaling interface, data input/output (I/O) circuitry and command/address (CA) circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. 1. A memory component comprising:a signaling interface having an on-die terminated data input/output (I/O), an unterminated input to receive command/address (CA) signals and a strobe input, each to be coupled to a respective external signaling link;data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write data bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O; andCA circuitry to sample CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively.2. The memory component of further comprising:a clock input within the signaling interface; andclosed-loop clock generation circuitry coupled to receive the second clock signal via the clock input and to generate the first clock signal with a phase that establishes, at the signaling interface, an alignment between a leading edge of the bit time for each read data bit and a respective transition of the ...

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Номер записи: 146
05-12-2013 дата публикации

METHODS AND APPARATUS FOR TESTING INACCESSIBLE INTERFACE CIRCUITS IN A SEMICONDUCTOR DEVICE

Номер: US20130321022A1
Автор: Ware Frederick A.
Принадлежит: RAMBUS INC.

A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion. 1. A system comprising:a test-signal generator to generate first and second test signals having an adjustable first timing relationship; a sequential element;', 'a data contact pad to communicate an external data signal;', 'a data pass gate coupled between the sequential element and the data contact pad to selectively pass the data signal between the sequential element and the data contact pad responsive to the first test signal to provide a delayed data signal;', 'a clock contact pad to communicate an external clock signal; and', 'a clock pass gate coupled between the sequential element and the clock contact pad to selectively pass the clock signal between the sequential element and the data contact pad responsive to the second test signal to provide a delayed clock signal;, 'a semiconductor die havingwherein the delayed data signal and the delayed clock signal have a second timing relationship, and wherein adjusting the first timing relationship proportionally adjusts the second timing relationship.2. The system of claim 1 , wherein the sequential element transmits the external data signal to the data contact pad via the data pass gate.3. The system of claim 1 , wherein the test-signal generator is instantiated on the semiconductor die.4. The system of claim 1 , ...

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Номер записи: 147
19-12-2013 дата публикации

Cross-threaded memory system

Номер: US20130339631A1
Автор: Frederick A. Ware, Kishore Kasamsetty
Принадлежит: RAMBUS INC

In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

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Номер записи: 148
26-12-2013 дата публикации

Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration

Номер: US20130346685A1
Автор: Hampel Craig E., Perego Richard S., Sidiropoulos Stefanos, Tsern Ely K., Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. 1. A memory component comprising;a memory core comprising dynamic random access memory (DRAM) storage cells;a first circuit to receive external commands, the external commands including a read command that specifies transmitting data accessed from the memory core, and a write command that specifies storing data, provided to the memory component, in the memory core;a second circuit to transmit data onto an external bus in response to a read command;pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern, wherein, during the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration, wherein the pattern register circuitry includes at least first and second pattern registers to provide the first and second data patterns, respectively, wherein at least one of the first and second data pattern registers is loaded with at least one of the first and second data patterns in response to a ...

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Номер записи: 149
26-12-2013 дата публикации

ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION

Номер: US20130346822A1
Автор: Kizer Jade M., Luo Lei, Ware Frederick A., Wilson John, Zerbe Jared L.
Принадлежит:

Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition. 1. An integrated circuit (IC) device comprising:transmit circuitry to transmit N symbols encoded as M symbols over M links to a second IC device;a receiver to receive error information from the second IC device, the error information associated with the transmitted symbols; andcontrol logic operative to carry out a remedial operation based on the received error information.2. The integrated circuit device according to claim 1 , wherein:the encoding results in the symbols being transmitted as a balanced codeword; andthe error information results from detection of an imbalance in the codeword at the second IC device.3. The integrated circuit device according to claim 1 , wherein the remedial operation involves re-transmitting at least a portion of the M symbols.4. The integrated circuit device according to claim 1 , wherein the remedial operation involves storing information regarding one or more links associated with the error information.5. The integrated circuit device according to claim 1 , wherein the remedial operation involves adjusting a transmit parameter associated with the transmit circuitry.6. The integrated circuit according to claim 5 , wherein the transmit parameter is selected from the group consisting of amplitude claim 5 , ...

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Номер записи: 150
02-01-2014 дата публикации

Multi-column addressing mode memory system including an integrated circuit memory device

Номер: US20140003131A1
Автор: Chad A. Bellows, Frederick A. Ware, Lawrence Lai, Wayne S. Richardson
Принадлежит: RAMBUS INC

A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

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Номер записи: 151
30-01-2014 дата публикации

Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration

Номер: US20140032830A1
Автор: Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Richard S. Perego, Stefanos Sidiropoulos
Принадлежит: RAMBUS INC

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

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Номер записи: 152
13-02-2014 дата публикации

MEMORY MODULE THREADING WITH STAGGERED DATA TRANSFERS

Номер: US20140047155A1
Автор: Ware Frederick A., Zheng Hongzhong
Принадлежит: RAMBUS INC.

A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus. 1. A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width , the primary data bus to route data of a primary data transfer continuous throughput between the module and the controller , the memory module including plural memory device groups coupled to a buffer via corresponding secondary data bus paths each having a continuous throughput smaller than the primary data transfer continuous throughput , the method comprising:accessing a first one of the memory device groups via a corresponding secondary data bus path in response to a threaded memory request from the memory controller, the accessing resulting in data groups collectively forming a first data thread transferred across the corresponding secondary data bus path;transferring the first data thread across the primary data bus width over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval; andduring the first time interval, transferring at least one data group from a second data thread on the primary data bus.2. The method of wherein transferring the first data thread ...

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Номер записи: 153
06-03-2014 дата публикации

SELECTIVE REFRESH WITH SOFTWARE COMPONENTS

Номер: US20140068172A1
Автор: Tringali James, Ware Frederick A., Zheng Hongzhong
Принадлежит: RAMBUS INC.

A method of refreshing a memory is disclosed. The method includes accessing from active memory an active memory map. The active memory map is generated by software and identifies addresses corresponding to the active memory and associated refresh criteria for the addresses. The refresh criteria are evaluated for a portion of the active memory, and an operation initiated to refresh a portion of the active memory is based on the refresh criteria. 1. A method of refreshing a memory , the method comprising:accessing from active memory an active memory map, the active memory map generated by software and identifying addresses corresponding to the active memory and associated refresh criteria for the addresses;evaluating the refresh criteria for a portion of the active memory; andinitiating an operation to refresh a portion of the active memory based on the refresh criteria.2. The method of wherein the software comprises operating system software.3. The method of wherein the operation comprises a software instruction claim 1 , and the method further comprises:decoding the software instruction to generate one or more memory refresh commands; andrefreshing the portion of the active memory in response to the one or more memory refresh commands.4. The method of wherein accessing the active memory map comprises accessing an allocated page table.5. The method of wherein accessing the allocated page table comprises:tabulating plural active memory page addresses; andtracking the refresh status for each active memory page address.6. The method of wherein tracking the refresh status comprises:sorting the active memory page addresses by the refresh criteria.7. The method of and further comprising: loading information representing the active memory map into an addressable storage element of a memory device; and', 'activating hardware in the memory device to selectively self-refresh the active memory of the memory device based on the loaded information., 'selectively initiating a self ...

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Номер записи: 154
13-03-2014 дата публикации

MEMORY SYSTEM USING ASYMMETRIC SOURCE-SYNCHRONOUS CLOCKING

Номер: US20140075237A1
Автор: Ware Frederick A.
Принадлежит:

The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant. 1. An integrated circuit , comprising:operational circuitry to operate at different rates responsive to respective reference clock frequencies;a timing generation circuit to generate a timing signal having a burst of plural timing events in response to each one of plural repetitions of a reference clock timing event, wherein frequency of repetition of the reference clock timing event corresponds to a currently-used one of the different rates, a first time interval between at least two of the plural timing events being substantially invariant notwithstanding change between the reference clock frequencies, a second time interval between bursts varying in response to change between the reference clock frequencies; andan interface to exchange data with another device at a data rate defined by the timing signal.23-. (canceled)4. The integrated circuit of claim 1 , where the integrated circuit transmits data to the other device claim 1 , and where a strobe signal based on the timing signal is transmitted to the other device to provide source synchronous timing to the other device to time sampling of the data transmitted to the other device claim 1 , and where the other device is a memory device and where:the integrated circuit further comprises a memory controller;the operational circuitry forms part of the memory controller, the operational circuitry ...

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Номер записи: 155
07-01-2016 дата публикации

MEMORY DEVICE WITH RETRANSMISSION UPON ERROR

Номер: US20160004593A1
Автор: Wang Yuanlong, Ware Frederick A.
Принадлежит:

A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition. 1. A solid state memory device comprising: receiver circuitry to receive command information that specifies a read operation of a group of read data bits, and first error detection information associated with the command information, from a controller device; and', 'transmit circuitry to transmit the group of read data bits, the group of read data bits being transmitted time multiplexed with second error-detection information; and,, 'a link interface configurable to transfer bidirectional signals in a first configuration, and to transfer unidirectional signals in a second configuration, wherein the link interface includesan encoder to generate the second error-detection information from the group of read data bits, wherein the transmit circuitry is operable to retransmit the group of read data bits and the second error detection information in the event that an error condition associated with the group of read data bits is detected.2. The solid state memory device of claim 1 , wherein the second error-detection information is to include a cyclic redundancy check ( ...

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Номер записи: 156
07-01-2016 дата публикации

Controller device with retransmission upon error

Номер: US20160004594A1
Автор: Frederick A. Ware, Yuanlong Wang
Принадлежит: RAMBUS INC

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

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Номер записи: 157
07-01-2016 дата публикации

Memory Controller With Error Detection And Retry Modes Of Operation

Номер: US20160004597A1
Автор: Horowitz Mark A., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data. 1. A memory controller , comprising:a plurality of transmitters to transmit write data and an error detection code to a memory device, the error detection code encoded by the memory controller in connection with the write data, wherein the plurality of transmitters are operable to transmit the write data in accordance with one of a plurality of modes, a first mode including data comprising symbols respectively transferred on rising and falling edges per clock cycle of a clock signal, and a second mode including data transferred with one symbol per clock cycle;circuitry to identify if the transmitted write data as received by the memory device reflects an error condition dependent on at least one error in the write data; andthe memory controller to re-transmit the write data to the memory device in the event that the circuit identifies that the error condition exists.2. The memory controller of claim 1 , wherein the error detection code transmitted from the memory controller is a cyclic code.3. The memory controller of claim 1 , wherein claim 1 , in the event of the error condition ...

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Номер записи: 158
07-01-2021 дата публикации

Multi-Mode Memory Module and Memory Component

Номер: US20210004337A1
Автор: Linstadt John Eric, Ware Frederick A., Wright Kenneth Lee
Принадлежит:

A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length. 1. A memory module comprising:an address buffer circuit;a command/address channel; and a plurality of memory component data ports that are shared between the first memory component and the second memory component;', 'a respective memory core to store data; and', 'a respective data interface to transfer data between the respective memory core and the plurality of memory component data ports, the respective data interface supporting a first data width mode in which the respective data interface transfers data at a first bit width and a first burst length via a first set of the plurality of memory component data ports, the respective data interface supporting a second data width mode in which the respective data interface transfers data at a second bit width and second burst length via a second set of the plurality of memory component data ports;, 'a memory rank controlled by the address buffer circuit via the command/address channel, the memory rank including a plurality of memory components, wherein the plurality of memory components includes a first memory component and a second memory component, each of the first memory ...

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Номер записи: 159
27-01-2022 дата публикации

MEMORY WITH VARIABLE ACCESS GRANULARITY

Номер: US20220027093A1
Автор: Ware Frederick A.
Принадлежит:

An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit- serial data signals over M of the N external signaling links, where M is less than N. 1. An integrated-circuit memory component comprising:a first data interface to transmit up to N bit-serial data signals in parallel via N external signaling links; receive, as part of a first memory read transaction, a first column access command that identifies a first volume of data;', 'enable the first data interface, in response to the first column access command, to transmit the first volume of data as N parallel bit-serial data signals over the N external signaling links;', 'receive, as part of a second memory read transaction, a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data; and', 'enable the first data interface, in response to the second column read command, to transmit the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N., 'control circuitry to2. The integrated-circuit memory component of wherein the first volume of data is constituted by a first quantity (Q1) of bits and the second volume of data is constituted by a second quantity (Q2) of bits claim ...

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Номер записи: 160
14-01-2021 дата публикации

PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER

Номер: US20210011866A1
Автор: Jessup Holden, Ware Frederick A.
Принадлежит:

The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request. 1. (canceled)2. An integrated circuit (IC) memory device , comprising:a command interface to receive memory access commands from a memory controller, the memory access commands to include a read command that specifies a read operation;a data interface to output read data, associated with the read command, during the read operation; anda circuit to perform a calibration operation, associated with the read operation, during an intervening time between receipt of the read command and the associated output of the read data.3. The IC memory device according to claim 2 , further comprising a flash memory core to store the read data.4. The IC memory device according to claim 2 , wherein the circuit to perform the calibration operation comprises circuitry to adjust a timing phase relationship between calibration data transmitted to a memory controller and a read timing reference signal.5. The IC memory device according to claim 4 , further comprising:a locked loop circuit to provide the read timing reference signal; andtest pattern circuitry to provide the calibration data.6. The IC memory device according to claim 5 , wherein the locked-loop circuit comprises:one of a phase-locked loop (PLL) or a delay-locked loop (DLL).7. The IC memory device according to claim 5 , wherein the test pattern circuitry ...

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Номер записи: 161
14-01-2016 дата публикации

STACKED SEMICONDUCTOR DEVICE

Номер: US20160012910A1
Автор: Ware Frederick A.
Принадлежит:

A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies. 1. A packaged semiconductor device comprising:multiple integrated circuit (IC) chips arranged as a stack, each chip including multiple input/output (I/O) pads, each I/O pad selectively coupled to an input/output (I/O ) circuit;wherein the I/O pads for each chip in the stack are vertically aligned with corresponding I/O pads in the other stacked chips to define vertically aligned sets of I/O pads;wherein a given vertically aligned set of I/O pads for the stacked chips is electrically coupled via a conductive path; andwherein less than all of the I/O circuits corresponding to a given vertically aligned set of I/O pads are electrically coupled to the conductive path.2. The packaged semiconductor device according to claim 1 , wherein the multiple IC chips comprise dynamic random access memory (DRAM) devices.3. The packaged semiconductor device according to claim 1 , wherein each path comprises through-silicon-vias formed through each chip.4. The packaged semiconductor device according to claim 1 , wherein each conductive path is coupled to no more than one I/O circuit.5. The packaged semiconductor device according to claim 1 , further comprising a programmable element to ...

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Номер записи: 162
09-01-2020 дата публикации

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

Номер: US20200012332A1
Автор: Fuller Andrew M., Palmer Robert E., Poulton John W., Ware Frederick A.
Принадлежит:

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices. 120-. (canceled)21. A memory controller component comprising:a clock transmitter to transmit a first clock signal to a dynamic random access memory device (DRAM), the DRAM having (i) command/address receive circuitry to receive read commands and write commands, (ii) read-data transmit circuitry to transmit, in response to the read commands, read data using the first clock signal, and (iii) write-data receive circuitry to sample, in response to the write commands, write data using the first clock signal;a command/address transmitter to transmit the read commands and the write commands to the DRAM in response to a second clock signal;a write-data transmitter to transmit the write data to the DRAM in response to a third clock signal;a read-data receiver to sample the read data transmitted by the DRAM in response to a fourth clock signal; and phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal and', 'circuitry to generate the second clock signal at a lower frequency than the third and fourth clock signals; and', 'clock-pause circuitry to halt transmission of the first clock signal to the DRAM during a first interval to conserve power and to re- ...

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Номер записи: 163
11-01-2018 дата публикации

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

Номер: US20180012643A1
Автор: Hampel Craig E., Perego Richard E., Sidiropoulos Stefanos, Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. 1. (canceled)2. A controller to control operations of a memory component , the controller comprising: a first command that specifies a first data pattern to be stored in a first register of the memory component;', 'a second command that specifies a second data pattern to be stored in a second register of the memory component; and,', 'a third command to select one of the first data pattern or the second data pattern to be output by the memory component;, 'a first circuit to transmit commands to the memory component, the commands includinga second circuit to receive, from the memory component as a received data pattern, the one of the first data pattern or the second data pattern output by the memory component, as selected by the third command; and,calibration circuitry to based on the received data pattern, adjust a timing of a timing reference signal for sampling data at the second circuit.3. The controller of claim 2 , wherein the commands transmitted by the first circuit include a fourth command that specifies data to be accessed from a memory core of the memory component claim 2 , ...

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Номер записи: 164
11-01-2018 дата публикации

MEMORY CONTROLLER

Номер: US20180012644A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: first circuitry to transmit a write command to a dynamic random access memory device (DRAM), the write command to be sampled by the DRAM in response to a first timing signal; and', 'second circuitry to transmit first write data to the DRAM, the first write data to be sampled by the DRAM in response to a second timing signal; and, 'a signaling interface, includingadjustment circuitry to offset the first and second timing signals from one another at the signaling interface to compensate for skew between their arrival times at the DRAM.22. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset a phase of the second timing signal from a phase of the first timing signal.23. The memory controller of wherein the adjustment circuitry to offset the first and second timing signals from one another comprises circuitry to offset the first and second timing signals at the signaling interface by a time interval that corresponds to a difference in respective propagation times claim 21 , from the memory controller component to the DRAM claim 21 , of the first and second timing signals.24. The memory controller of wherein the second circuitry to transmit the first write data to the DRAM comprises circuitry to output at least part of the first write data onto an external data signaling link at one or more times indicated by the second timing signal.25. The memory controller of wherein the circuitry to ...

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Номер записи: 165
09-01-2020 дата публикации

ADJUSTABLE ACCESS ENERGY AND ACCESS LATENCY MEMORY SYSTEM AND DEVICES

Номер: US20200012429A1
Автор: Linstadt John Eric, Ware Frederick A.
Принадлежит:

Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed. 1. (canceled)2. A method of operating a memory controller , comprising:transmitting a plurality of commands, to a memory device, the plurality of commands to access, utilizing at least a first plurality and a second plurality of memory array tiles, respective blocks of data having a first size, the respective blocks of data being stored in different formats, the first plurality and the second plurality to be different numbers of memory array tiles.3. The method of claim 2 , wherein the second plurality of memory array tiles includes at least twice the number of memory array tiles as the first plurality of memory array tiles.4. The method of claim 2 , wherein the first plurality and second plurality of memory array tiles include sense amplifiers claim 2 , and accessing the memory array tiles includes a row access that places data stored by a sub-row of storage cells into sense amplifiers of a utilized memory array tile claim 2 , and accessing the memory array tiles also includes a column access operation that moves data between the sense amplifiers and an interface.5. The method of claim 4 , wherein accessing utilizing the first plurality of memory array tiles comprises at least twice the number of column ...

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Номер записи: 166
17-04-2014 дата публикации

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

Номер: US20140104935A1
Автор: Amirkhany Amir, Hekmat Mohammad, Patil Dinesh, RAJAN SURESH, Ware Frederick A.
Принадлежит: RAMBUS INC.

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams. 1. A semiconductor memory system , comprising: a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and', 'a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams; and, 'a first semiconductor memory die, comprisinga second semiconductor memory die comprising a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.2. The semiconductor memory system of claim 1 , wherein:the primary data interface of the first semiconductor die is to receive the input data stream at double data rate (DDR) during the write operations; andthe first plurality of data streams comprises a first single data rate (SDR) data stream and a second SDR data stream.3. The semiconductor memory system of claim 1 , wherein:the first and second semiconductor memory die each comprise a command and address (C/A) interface to be coupled to a C/A bus;the first semiconductor memory die is to receive a first chip-select signal from the C/A bus; andthe second semiconductor memory die is to receive a second chip-select signal from the C/A bus, the second chip-select signal being distinct from the first chip- ...

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Номер записи: 167
17-01-2019 дата публикации

Configurable, Power Supply Voltage Referenced Single-Ended Signaling with ESD Protection

Номер: US20190020373A1
Автор: Poulton John W., Ware Frederick A., Werner Carl W.
Принадлежит:

A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply. 1. (canceled)2. An integrated circuit to be coupled to a power supply , comprising:first and second terminals, the second terminal to be at a power supply voltage after being coupled to the power supply;a transmitter configured to transmit a signal via the first terminal, the signal having a voltage level that is referenced to the power supply voltage and that swings substantially symmetrically above and below the power supply voltage;a first charge pump drawing a first supply current from the power supply while the voltage level of the signal is at or near a first voltage; anda second charge pump drawing a second current from the power supply while the voltage level of the signal is at or near a second voltage, the first voltage and the second voltage being substantially symmetrical with respect to the power supply voltage and the second current being substantially equal to the first current.3. The integrated circuit of claim 2 , wherein the second terminal is part of a signal return path for the signal.4. The integrated circuit of claim 2 , wherein the power supply voltage is a ground voltage.5. The integrated circuit of claim 2 , wherein the power supply voltage is other than a ground voltage.6. The integrated circuit of claim 2 , wherein the transmitter transmits the signal while the first charge pump and the second charge pump draw a total power supply current from the power supply that is substantially independent of the voltage level of the signal.7. The integrated circuit of claim 2 , further comprising:a receiver ...

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Номер записи: 168
28-01-2016 дата публикации

Memory Access During Memory Calibration

Номер: US20160026583A1
Автор: Shaeffer Ian, Ware Frederick A.
Принадлежит:

A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus. 1. A method of operation in a memory system including a plurality of ranks of memory devices including at least a first memory device in a first memory rank and a second memory device in a second memory rank , each memory device being coupled to both a first data bus and second data bus , the method comprising:receiving, by the first memory device, a first command that specifies a calibration operation; andreceiving, by the second memory device, a second command that specifies a memory access operation, such that the memory access operation is performed by the second memory device while the calibration operation is performed by the first memory device.2. The method of claim 1 , wherein the second command specifies the second memory device to transfer data between a memory controller and a storage location of a selected sub-bank claim 1 , wherein the selected sub-bank is a sub-bank of a plurality of sub-banks in the second memory device.3. The method of claim 2 , further comprising receiving claim 2 , by the second memory device claim 2 , a control signal specifying accessing claim 2 , via the second data bus claim 2 , the storage location of the selected sub-bank.4. The method of claim 1 , further comprising receiving claim 1 , by the second memory device claim 1 , a control signal specifying settings of a routing circuit in the second memory device claim 1 , the routing circuit permitting access to a ...

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Номер записи: 169
28-01-2016 дата публикации

Reduced refresh power

Номер: US20160027498A1
Автор: Brent S. Haukness, Frederick A. Ware, Gary B. Bronner, Scott C. Best
Принадлежит: RAMBUS INC

N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives refresh commands (e.g., auto-refresh commands) from the command-address channel, but does not issue a proportion of these commands to the DRAMs on the module. This reduces the power consumed by refresh operations. The buffer may replace some auto-refresh (REF) commands with activate (ACT) and precharge (PRE) commands directed to specific rows. These rows may have known ‘weak’ cells that require refreshing more often than a majority of the other rows on the module (or component). By ignoring some auto-refresh commands, and directing some others to specific rows that have ‘weak’ cells, the power consumed by refresh operations can be reduced.

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Номер записи: 170
10-02-2022 дата публикации

Low latency memory access

Номер: US20220043758A1
Автор: Frederick A. Ware
Принадлежит: RAMBUS INC

A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

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Номер записи: 171
10-02-2022 дата публикации

High-Performance, High-Capacity Memory Systems and Modules

Номер: US20220043762A1
Автор: Best Scott C., Giovannini Thomas J., Hampel Craig E., Linstadt John Eric, Tsern Ely, Ware Frederick A., Yan John
Принадлежит:

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities. 1. A motherboard comprising:a memory-controller component;a first memory-module socket adjacent the memory-controller component;a second memory-module socket adjacent the first memory-module socket on a side of the first memory-module socket opposite the memory-controller component;a third memory-module socket adjacent the second memory-module socket on a side of the second memory-module socket opposite the first memory-module socket;a fourth memory-module socket adjacent the third memory-module socket on a side of the third memory-module socket opposite the second memory-module socket;a first data-link group coupling the memory-controller component to the first memory module socket and the third memory-module socket, the first data-link group extending past the second memory-module socket; anda second data-link group extending past the first memory-module socket and the third memory-module socket, the second data-link group coupling the memory-controller component to the second memory module socket and the fourth memory-module socket.2. The motherboard of claim 1 , further comprising a first memory module in the first memory-module socket and a second memory module in the second memory-module socket claim 1 , the memory controller to direct a memory transaction to the first memory module and the second memory module via the respective first data-link group and the second data-link group.3. The motherboard of claim 2 , further comprising a third memory module in the third memory-module socket and a fourth memory module in the fourth memory-module socket claim 2 , the ...

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Номер записи: 172
24-01-2019 дата публикации

PROTOCOL FOR MEMORY POWER-MODE CONTROL

Номер: US20190027210A1
Автор: Bansal Akash, Ellis Wayne F., Kasamsetty Kishore Ven, Lai Lawrence, Richardson Wayne S., Ware Frederick A.
Принадлежит:

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command. 1. A dynamic random access memory (DRAM) device comprising:a memory core having a plurality of memory cells;a command/address (CA) interface to receive command and address information;a driver circuit to output data in response to a command received via the CA interface;an interface to receive a power mode signal; anda register to store a value that sets a first mode in which (i) the driver circuit is powered down in response to a transition in the power mode signal, and (ii) the CA interface is to remain powered up in response to the transition in the power mode signal.2. The DRAM device of claim 1 , further comprising:a clock receiver to receive a clock signal, wherein the CA interface is to receive the command and address information synchronously with respect to the clock signal.3. The DRAM device of claim 2 , wherein the CA interface is to receive a command that instructs the DRAM device to change operation from a first clock frequency of the clock signal to a second clock frequency of the clock signal.4. The DRAM device of claim 3 , further comprising:a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal, the plurality of clock frequencies including the first clock ...

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Номер записи: 173
10-02-2022 дата публикации

CONFIGURABLE, POWER SUPPLY VOLTAGE REFERENCED SINGLE-ENDED SIGNALING WITH ESD PROTECTION

Номер: US20220045719A1
Автор: Poulton John W., Ware Frederick A., Werner Carl W.
Принадлежит:

A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply. 1. (canceled)2. A circuit to be coupled to a power supply , comprising:first and second terminals, the second terminal to be at a power supply voltage after being coupled to the power supply, the circuit being formed on a semiconductor substrate to be mounted on a packaging substrate having a power plane and the second terminal is to be connected to the power plane; anda receiver configured to receive a signal via the first terminal, the signal having a voltage level that is referenced to the power supply voltage and that swings substantially symmetrically above and below the power supply voltage.3. The circuit of claim 2 , wherein the second terminal is part of a signal return path for the signal.4. The circuit of claim 2 , wherein the power supply voltage is a ground voltage.5. The circuit of claim 2 , wherein the power supply voltage is other than a ground voltage.6. The circuit of claim 1 , wherein the packaging substrate is a ball grid array.7. The circuit of claim 6 , wherein the second terminal is connected to an inner ball of the ball grid array.8. The circuit of claim 2 , further comprising a pair of cross-coupled diodes couple between the first terminal and the second terminal to prevent electrostatic discharge damage to the circuit.9. A circuit to be coupled to a power supply claim 2 , comprising:a first terminal and a second terminal, the second terminal to be at a power supply voltage after being coupled to the power supply;a receiver to receive a signal via the first terminal, the signal to have a voltage ...

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Номер записи: 174
28-01-2021 дата публикации

MEMORY CONTROLLER

Номер: US20210027825A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM. 120-. (canceled)21. A memory controller component comprising: a first timing signal that requires a first time interval to propagate to the memory component;', 'write data to be sampled by the memory component synchronously with respect to the first timing signal;', 'a second timing signal that requires a second time interval to propagate to the DRAM; and', 'a write command, corresponding to the write data, to be sampled by the memory component synchronously with respect to the second timing signal; and, 'transmit circuitry to transmit to a memory componentcontrol circuitry to adjust transmit timing of at least one of the first and second timing signals based on a difference between the first and second time intervals to render phase-aligned arrival of the first and second timing signals at the memory component.22. The memory controller component of wherein the second timing signal is a clock signal and the first timing signal is a strobe signal.23. The memory controller component of wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second timing signals at the memory component comprises circuitry to render alignment claim 21 , at the memory component claim 21 , between respective rising edges of the first and second timing signals.24. The memory controller component of wherein the control circuitry to adjust transmit timing of at least one of the first and second timing signals to render phase-aligned arrival of the first and second ...

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Номер записи: 175
17-02-2022 дата публикации

DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY AT HIGH SIGNALING RATES

Номер: US20220051705A1
Автор: Ware Frederick A.
Принадлежит:

An IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio. For a second operating mode, the first and second read data are received after respective second and third delays following transmission of the first and second read commands. The second and third delays are different from the first delays and from each other. The first and second data are received at a second serialization ratio that is different than the first serialization ratio. 1. An integrated circuit (IC) memory controller , comprising:a first command/address (C/A) interface to transmit, to a first memory C/A interface of a first bank group of memory, first and second read commands for first and second read data;a second command/address (C/A) interface to transmit, to a second memory C/A interface of a second bank group of memory, third and fourth read commands for third and fourth read data;receiver circuitry to receive the first and second read data via a first data link interface and to receive the third and fourth read data via the second data link interface, the third and fourth read data received in a pipelined fashion with respect to the first and second read data;wherein for a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and wherein the first and second data are received at a first serialization ratio; andwherein for a second operating mode, the first ...

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Номер записи: 176
31-01-2019 дата публикации

Maintenance Operations in a DRAM

Номер: US20190034099A1
Автор: Palmer Robert E., Poulton John W., Ware Frederick A.
Принадлежит:

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order. 1. A dynamic random access memory (DRAM) device comprising:a plurality of banks each including DRAM memory cells;an on-die termination circuit having a termination resistance;an output driver to transmit data, the output driver having an output drive strength;a command interface to receive a refresh command from a memory controller, wherein the refresh command specifies a refresh operation of the plurality of banks, the refresh operation to occur during a time interval; anda circuit to perform a calibration operation of the termination resistance and the output drive strength during the time interval and in response to the refresh command.2. The DRAM device of claim 1 , wherein the calibration operation of the termination resistance and the output drive strength is performed during the time interval as specified by an operation code received at the command interface claim 1 , wherein the operation code is received with the refresh command.3. The DRAM device of claim 1 , wherein the refresh command includes a plurality of bits to identify at least one bank as a first bank ...

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Номер записи: 177
04-02-2021 дата публикации

MEMORY CONTROLLER WITH INTEGRATED TEST CIRCUITRY

Номер: US20210033665A1
Автор: Ware Frederick A.
Принадлежит:

A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion. 1. (canceled)2. A memory system comprising:a test-signal generator to issue a data test signal; a test-signal wire coupled to the test-signal generator to convey the data test signal;', 'a write-data transmit interface to output a write data signal, the write-data transmit interface including at least one gating transistor to gate the write data signal responsive to the data test signal; and', 'a first data contact pad to communicate the gated write data signal away from the memory controller IC; and, 'a memory controller integrated-circuit (IC) device having 'a second data contact pad bonded to the first data contact pad to receive the gated write data signal from the memory controller IC.', 'a memory IC device having3. The memory system of claim 2 , the write-data transmit interface further comprising a sequential element having a clock terminal claim 2 , coupled to a clock gate claim 2 , and a data output terminal claim 2 , the sequential element to transmit the write data signal from the data output terminal responsive to a gated clock signal.4. The memory system of claim 3 , the write-data transmit interface further comprising a data gate coupled to the data output terminal claim 3 , the data gate to gate the write data signal ...

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Номер записи: 178
17-02-2022 дата публикации

COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS

Номер: US20220052802A1
Автор: Hampel Craig E., Perego Richard E., Ware Frederick A.
Принадлежит:

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component. 1. (canceled)2. A controller to control a memory component , the controller comprising:interface circuitry to transfer information with the memory component, via at least one link, wherein the interface circuitry is to time the transfer the information according to edges of a clock signal; andphase adjustment circuitry to vary a phase of the edges of the clock signal;wherein the phase adjustment circuitry is to establish an operating value of the phase during a calibration operation, the operating value to be applied to the transfer of the information, and wherein the phase adjustment circuitry is to from-time-to-time adjust the operating value in response to drift between the operating value and a timing point for transfer of the information used by the memory device, the drift being detected subsequent to establishment of the operating value.3. The controller of wherein the interface circuitry comprises a transmitter and wherein the information is to be transmitted by the transmitter to the memory device according to the edges of the clock signal.4. The controller ...

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Номер записи: 179
17-02-2022 дата публикации

MEMORY SUBSYSTEM FOR A CRYOGENIC DIGITAL SYSTEM

Номер: US20220053667A1
Автор: Linstadt John Eric, Vogelsang Thomas, Ware Frederick A.
Принадлежит:

The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first non-cryogenic temperature domain, a second component located in a second temperature domain that is lower in temperature than the first cryogenic temperature domain, and a third component located in a cryogenic temperature domain that is lower in temperature than the second cryogenic temperature domain. 1. (canceled)2. A computer system comprising:a plurality of stacks of memory devices in a first temperature domain;memory controller logic in the first temperature domain, wherein the memory controller logic is coupled to the plurality of stacks of memory devices over a first link; anda buffer component in a second temperature domain that is lower in temperature than the first temperature domain, wherein the buffer component is coupled to the memory controller logic over a second link.3. The computer system of claim 2 , wherein the memory controller logic is configured to direct data to and from the respective stack of the plurality of stacks of memory devices and a physical interface coupled to the second link.4. The computer system of claim 2 , wherein the memory devices of the plurality of stacks of memory devices are dynamic random access memory (DRAM) devices claim 2 , and wherein the first temperature domain has a cool temperature range having a lower temperature limit set by an operating temperature range of the DRAM device.5. The computer system of claim 2 , wherein the memory devices of the plurality of stacks of memory devices are dynamic random access memory (DRAM) devices claim 2 , and wherein the first temperature domain has a cool temperature range having an upper temperature limit set by a retention time of the DRAM device.6. The computer system of claim 2 , further comprising a coolant fluid circulation system to transfer heat generated by the plurality of stacks of memory devices in the first temperature domain to a fluid medium.7. The ...

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Номер записи: 180
04-02-2021 дата публикации

FLOATING BODY DRAM WITH REDUCED ACCESS ENERGY

Номер: US20210035623A1
Автор: Linstadt John Eric, LU Zhichao, Ware Frederick A., Wright Kenneth Lee
Принадлежит:

Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command. 1. (canceled)2. A memory controller , comprising:a transfer interface to transmit a read command to access first read data stored in a first group of floating body storage cells;conditional writeback circuitry coupled to the transfer interface, the conditional writeback circuitry to generate a writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a first sense characteristic; andwherein the transfer interface is configured to conditionally perform a writeback operation of sensed data associated with the read command in response to the writeback command generated by the conditional writeback circuitry.3. The memory controller of :wherein the conditional writeback circuitry generates the writeback command randomly based on the predetermined probability.4. The memory controller of claim 3 , wherein the conditional writeback circuitry further comprises:a control register to store a value N corresponding to the predetermined probability.5. The memory controller of claim 4 , wherein the conditional writeback circuitry further comprises:a random signal generator configured to generate the writeback command with the predetermined probability based on the relationship 1/N.6. The memory controller of claim 1 , wherein the conditional writeback circuitry further ...

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Номер записи: 181
08-02-2018 дата публикации

ADJUSTABLE ACCESS ENERGY AND ACCESS LATENCY MEMORY SYSTEM AND DEVICES

Номер: US20180039416A1
Автор: Linstadt John Eric, Ware Frederick A.
Принадлежит:

Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed. 1. A method of operating a memory component , comprising:accessing, utilizing a first number of memory subarrays, a first block of data having a first size, the first block of data being stored in the memory subarrays in a first format; and,accessing, utilizing a second number of memory subarrays, a second block of data having the first size, the second block of data being stored in the memory subarrays in a second format, the first number being different from the second number.2. The method of claim 1 , wherein the second number is twice the first number.3. The method of claim 1 , wherein the memory subarrays include sense amplifiers claim 1 , and accessing the memory subarrays includes a row access that places data stored by a sub-row of storage cells into sense amplifiers of a utilized memory subarray claim 1 , and accessing the memory subarrays also includes a column access operation that moves data between the sense amplifiers and an interface.4. The method of claim 3 , wherein the accessing utilizing the first number of memory subarrays comprises at least twice the number of column access operations per subarray than the accessing utilizing the second number of memory subarrays.5. The method of claim 4 ...

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Номер записи: 182
12-02-2015 дата публикации

Memory module

Номер: US20150043290A1
Автор: Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Richard E. Perego
Принадлежит: RAMBUS INC

A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

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Номер записи: 183
09-02-2017 дата публикации

MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION

Номер: US20170040047A1
Автор: Ware Frederick A.
Принадлежит:

A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals. 120-. (canceled)21. A method of operation within a memory controller integrated circuit (IC) that controls operation of a memory IC , the method comprising:outputting an address/control timing signal that requires a first time interval to propagate to the memory IC;outputting, after respective first and second write timing delays, first and second write data timing signals that require respective second and third time intervals to propagate to the memory IC, the first write timing delay compensating for a difference between the first and second time intervals, and the second write timing delay compensating for a difference between the first and third time intervals, and the first write timing delay being independent from and free to be different from the second write timing delay; andoutputting first and second write data signals to the first memory IC via the first and second data lines, respectively, the first write data signal to be sampled by the memory IC at a time corresponding to the first write-data timing signal, and the second write data signal to be sampled by the memory ...

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Номер записи: 184
24-02-2022 дата публикации

Configurable MAC Pipelines for Finite-Impulse-Response Filtering, and Methods of Operating Same

Номер: US20220057994A1
Автор: Wang Cheng C., Ware Frederick A.
Принадлежит: Flex Logix Technologies, Inc.

An integrated circuit comprising a plurality MAC pipelines wherein each MAC pipeline includes: (i) a plurality of MACs connected in series and (ii) a plurality of data paths including an accumulation data path, wherein each MAC includes a multiplier to multiply to generate product data and an accumulator to generate sum data. The integrated circuit further comprises a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with a MAC pipeline, wherein each control/configure circuit includes an accumulation data path which is configurable to directly connect to the accumulation data path of the MAC pipeline to form an accumulation ring when the control/configure circuit is configured in an accumulation mode, and an output data path configurable to directly connect to the output of the accumulation data path of the MAC pipeline when the control/configure circuit is configured in an output data mode. 1. An integrated circuit comprising:{'claim-text': ['a multiplier to multiply first data by multiplier weight data and generate product data, and', 'an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second data and the product data of the associated multiplier to generate sum data;'], '#text': 'a plurality MAC pipelines wherein each MAC pipeline includes: (i) a plurality of multiplier-accumulator circuits connected in series to perform a plurality of concatenated multiply and accumulate operations and (ii) a plurality of data paths including an accumulation data path, and wherein each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits of each MAC pipeline includes:'}{'claim-text': ['an accumulation data path which is configurable to directly connect to an input and an output of the accumulation data path of the associated MAC pipeline to form an accumulation ring when the associated control/configure circuit is configured in an ...

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Номер записи: 185
18-02-2021 дата публикации

Memory Controller For Selective Rank Or Subrank Access

Номер: US20210049115A1
Автор: Hampel Craig E., Ware Frederick A.
Принадлежит:

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands. 1. (canceled)2. A memory controller comprising:circuitry to determine whether a memory comprising memory arrays is to be operated in a first mode or a second mode; andcircuitry to issue memory access commands; in the first mode, the circuitry to issue is to transmit first memory access command to the memory which selects read data in a first one of the memory arrays and read data in a second one of the memory arrays, and', 'in the second mode, the circuitry to issue is to transmit a second memory access command to the memory which selects read data in the first one of the memory arrays and, prior to output by the memory of the read data from the first one of the memory arrays, is to transmit a third memory access command to the memory which selects read data in the second one of the memory arrays., 'wherein'}3. The memory controller of claim 2 , wherein:the memory controller is to couple to both of the first one of the memory arrays and the second one of the memory arrays via a common control path;the circuitry to issue is to transmit first, second and third memory access commands to the memory via the common control path;the memory controller is to couple to the first one of the memory arrays via a first data path and to the second one of the memory arrays via a second data path;the memory controller comprises further comprises circuitry to receive the read data ...

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Номер записи: 186
07-02-2019 дата публикации

Protocol For Refresh Between A Memory Controller And A Memory Device

Номер: US20190043555A1
Автор: Haukness Brent, Ware Frederick A.
Принадлежит:

The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller. 1. (canceled)2. A memory controller integrated circuit (IC) to control a dynamic random access memory (DRAM) device , the memory controller IC comprising:interface circuitry to command the DRAM device to perform a refresh operation on a selected bank of the DRAM device;wherein the memory controller IC is to observe a first time interval from completion of the refresh operation on the selected bank before sending a command directed to the selected bank via the interface circuitry; andwherein the interface circuitry is to issue a command directed to a bank of the DRAM device other than the selected bank using a second time interval from completion of the refresh operation on the selected bank, the second time interval being shorter than the first time interval.3. The memory controller IC of claim 2 , wherein:the interface circuitry is to exchange the commands with the DRAM device via calibrated links, each calibrated link operating at a first data rate;in a low power state, the DRAM device is to disable exchange of commands with the interface circuitry at the first data rate; andin the low power state, the DRAM device is to perform a self-refresh operation.4. The memory controller IC of claim 3 , wherein:the interface circuitry ...

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Номер записи: 187
03-03-2022 дата публикации

MEMORY CONTROLLER PARTITIONING FOR HYBRID MEMORY SYSTEM

Номер: US20220066672A1
Автор: Linstadt John Eric, Ware Frederick A.
Принадлежит:

A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.

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Номер записи: 188
03-03-2022 дата публикации

SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION

Номер: US20220069975A1
Автор: Hampel Craig E., Stott Bret G., Ware Frederick A.
Принадлежит:

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

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Номер записи: 189
23-02-2017 дата публикации

OPTIMIZING POWER IN A MEMORY DEVICE

Номер: US20170052584A1
Автор: Amirkhany Amir, Aquil Farrukh, Kaviani Kambiz, Patil Dinesh, Ware Frederick A.
Принадлежит:

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. 1. (canceled)2. A memory device comprising:a first circuit to receive an external clock signal and generate a reduced clock signal, such that, during a given interval, a number of pulses of the reduced clock is less than a number of pulses of the external clock signal;a delay-locked loop (DLL) circuit to receive the reduced clock signal as an input and generate a second clock signal based on the reduced clock signal;a first latency counter clocked by the reduced clock signal; anda second latency counter clocked by the second clock signal, wherein the first and second latency counters to indicate a time for outputting data from the memory device relative to a received read command.3. The memory device of claim 2 , further comprising:an input buffer to receive the read command and to receive a first mode command from a memory controller, the first mode command to cause the memory device to enter an idle mode.4. The memory ...

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Номер записи: 190
13-02-2020 дата публикации

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

Номер: US20200050561A1
Автор: Amirkhany Amir, Hekmat Mohammad, Patil Dinesh, RAJAN SURESH, Ware Frederick A.
Принадлежит:

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams. 1. (canceled)2. A DRAM integrated circuit (IC) chip comprising:DRAM storage cells formed on the DRAM IC chip;a primary interface formed on the DRAM IC chip for transferring data signals with a first IC chip;a secondary interface formed on the DRAM IC chip for transferring the data signals with a second DRAM IC chip;a command/address (C/A) interface formed on the DRAM chip for transferring C/A signals directly with the first IC chip via a C/A signal path, the C/A signal path directly coupling the first IC chip with the second DRAM IC chip;configuration circuitry for configuring use of the secondary interface between a first mode of operation and a second mode of operation; andwherein the C/A interface receives the C/A signals from the DRAM IC chip for both the first and second modes of operation.3. The DRAM IC chip according to claim 2 , wherein the configuration circuitry configures use of the secondary interface to retransmit write data in the first mode of operation.4. The DRAM IC chip according to claim 3 , further comprising:buffer circuitry coupled to the secondary interface, the buffer circuitry to, in the first mode of operation, retransmit the write data received by the primary interface to the second DRAM IC chip via the secondary interface.5. The DRAM IC chip according to claim 4 , wherein the first IC chip comprises ...

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Номер записи: 191