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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 84. Отображено 84.
21-07-2016 дата публикации

Radio Frequency Bitstream Generator and Combiner Providing Image Rejection

Номер: US20160211885A1
Принадлежит:

A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering. 1. A circuit for combining a plurality of digital bitstreams , the circuit comprising:first and second bitstream generators, the first bitstream generator being operative to receive a first analog signal and to generate a first digital bitstream as a function of the first analog signal, the second bitstream generator being operative to receive a second analog signal and to generate a second digital bitstream as a function of the second analog signal, the first and second bitstream generators being configured to maintain a substantially ninety-degree phase difference between the first and second digital bitstreams; anda directional coupler configured to receive, at a first port, a first input signal comprising the first digital bitstream, and configured to receive, at a second port, a second input signal comprising the second digital bitstream, the directional coupler maintaining a substantially ninety-degree phase difference between the first and second input signals, the directional coupler including a third port that is terminated, ...

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24-06-2014 дата публикации

BiCMOS gate driver for class-S radio frequency power amplifier

Номер: US0008760225B1
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the Class-S RF-PA. The drive circuit provides a high slew-rate, large-swing, quasi-digital gate drive circuit to drive the significant gate capacitance of the RF-PA with sufficient rise times. A combination of bipolar transistor current switches and cascoded CMOS devices is employed to attain requisite performance. For example, the driving circuit is well suited for use with Class-S RF-PAs used in wireless communication systems.

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29-04-2014 дата публикации

Preamplifier-to-channel communication in a storage device

Номер: US0008711502B1
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a plurality of interconnects and (b) the first bus. The controller may be configured to send/receive the digital control signals over the interconnects. The apparatus may be configured to (i) read/write the analog data signals to the drive and (ii) generate the digital control signals, in response to one or more input/output requests received from a drive interface.

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01-05-2014 дата публикации

Laser Power Control in a Heat-Assisted Magnetic Recording System

Номер: US20140119164A1
Принадлежит: LSI CORPORATION

A heat-assisted magnetic recording system may include, but is not limited to: at least one magnetic recording read/write head; at least one laser diode configured to illuminate at least a portion of at least one magnetic recording medium; at least one laser power level sensor configured to detect a power level of the at least one laser diode; and a controller configured to modify one or more power level settings associated with the at least one laser diode in response to one or more output signals of the at least one laser power level sensor. 1. A heat-assisted magnetic recording system comprising:at least one magnetic recording read/write head;at least one laser diode configured to illuminate at least a portion of at least one magnetic recording medium; configuring the at least one laser diode at a first non-zero power level setting during at least one magnetic recording write operation by the magnetic recording read/write head, and', 'configuring the at least one laser diode at a second non-zero power level setting at a time other than during at least one magnetic recording write operation by the magnetic recording read/write head;, 'a laser diode controller programmed forat least one laser power level sensor configured to detect a power level of the at least one laser diode configured at the second non-zero power level at the time other than during at least one magnetic recording write operation by the magnetic recording read/write head; andthe laser diode controller being further programmed for modifying at least one power level setting of the at least one laser diode in response to at least one output signal of the at least one laser power level sensor.2. The system of claim 1 , wherein the at least one laser diode is configured to illuminate at least one magnetic recording medium in a region of a magnetic recording/read write operation.3. The system of claim 1 , wherein the at least one laser power level sensor includes:at least one photodiode.4. The system of ...

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26-04-2016 дата публикации

Radio frequency composite Class-S power amplifier having discrete power control

Номер: US0009325284B2

A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The combiner couples filtered signals provided by the channels to form a composite output signal. A method of providing digitally selectable amplification includes steps of: selectively coupling a digital bitstream to a plurality of channels in the amplifier; amplifying the digital bitstream to provide an amplified signal associated with a corresponding one of the channels; filtering amplified signals associated with the channels to provide corresponding filtered signals; and combining the filtered signals ...

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10-03-2015 дата публикации

Low-distortion class S power amplifier with constant-impedance bandpass filter

Номер: US0008976898B1
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

An amplification system and an integrated circuit include a bandpass filter and an amplifier. The bandpass filter filters an input digital bitstream or an amplified signal to provide a filtered signal. The bandpass filter exhibits constant input impedance over a passband associated with the input digital bitstream, and a stopband associated with shaped-noise energy, thereby increasing signal-to-noise ratio and/or signal-to-distortion ratio associated with the filtered signal. The amplifier amplifies at least one of the filtered signal and the input digital bitstream to provide the amplified signal. A method of providing amplification includes bandpass filtering an input digital bitstream or an amplified signal to provide a filtered signal, providing constant input impedance over a passband and a stopband by the bandpass filtering, and amplifying at least one of the filtered signal and the input digital bitstream to provide the amplified signal.

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10-05-2016 дата публикации

Pseudo-differential shared-pin reader for two-dimensional magnetic recording

Номер: US0009336803B1

An apparatus for two-dimensional magnetic recording includes a storage medium, an array of magnetoresistive read heads disposed adjacent the storage medium and spaced to read a data track, wherein the array of magnetoresistive read heads share a common terminal, a number of leads connected to the array of magnetoresistive read heads, with one lead for each of the magnetoresistive read heads, plus a common lead connected to the common terminal, wherein each of the plurality of leads other than the at least one common lead are referenced to the at least one common lead, and a preamplifier connected to the array of magnetoresistive read heads by the plurality of leads and operable to perform pseudo-differential sensing or single-ended sensing of signals from the array of magnetoresistive read heads.

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05-07-2016 дата публикации

Cascaded viterbi bitstream generator

Номер: US0009385837B2

A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input ...

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01-05-2014 дата публикации

Method and Apparatus for High Density Pulse Density Modulation

Номер: US20140119427A1
Принадлежит: LSI CORPORATION

A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.

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10-07-2014 дата публикации

BICMOS GATE DRIVER FOR CLASS-S RADIO FREQUENCY POWER AMPLIFIER

Номер: US20140191801A1
Принадлежит: LSI CORPORATION

The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the Class-S RF-PA. The drive circuit provides a high slew-rate, large-swing, quasi-digital gate drive circuit to drive the significant gate capacitance of the RF-PA with sufficient rise times. A combination of bipolar transistor current switches and cascoded CMOS devices is employed to attain requisite performance. For example, the driving circuit is well suited for use with Class-S RF-PAs used in wireless communication systems. 1. A gate driver circuit for driving gates of output transistors of a switching radio frequency power amplifier , comprising:an input stage operative for receiving a bitstream digital data signal comprising a baseband digital data signal frequency-translated to a desired carrier frequency and converting the bitstream digital data signal into a pair of output stage input signals encoding the digital data signal;an output stage operative for receiving the output stage input signals and generating nominally complementary output pulse signals at a pair of output gates encoding the digital data signal; andwherein the output stage comprises a pair of cascoded CMOS gate drivers connected in a push-pull configuration.2. The gate driver circuit of claim 1 , further comprising a skew controller operative for introducing relative skew shifts between the nominally complementary output pulse signals.3. The gate driver circuit of claim 2 , wherein the skew controller is further operative to compensate for one or more of asymmetries in a monolithic microwave integrated circuit ( ...

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19-06-2014 дата публикации

TAG MULTIPLICATION VIA A PREAMPLIFIER INTERFACE

Номер: US20140168809A1
Принадлежит: LSI CORPORATION

An apparatus having a controller and a preamplifier is disclosed. The controller may be configured to generate information on a serial bus coupled to a preamplifier interface. The preamplifier may be configured to (i) generate a count value in response to a clock signal synchronized to a recording medium and (ii) generate a plurality of tag signals based on the information and the count value. The tag signals may gate a read operation and a write operation of the preamplifier.

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24-06-2014 дата публикации

Systems and methods for data write loopback based timing control

Номер: US0008760977B2
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

Systems and methods related to writing data to a storage medium. In some cases, a heat assisted loopback circuit is used that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The loopback circuit is operable to selectively couple a derivative of a heat output to a read output and to selectively couple a derivative of a write output to the read output.

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03-07-2014 дата публикации

Hybrid Digital/Analog Power Amplifier

Номер: US20140184323A1
Принадлежит: LSI CORPORATION

The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA. 11214. A radio frequency predriver [] for driving a high power radio frequency amplifier [] in a transmission direction , comprising:{'b': 20', '16', '18', '21', '16, 'a bitstream generator [] operative for receiving a baseband digital data signal [] and a desired carrier frequency [] and generating an input bitstream [] at the desired carrier frequency encoding the digital data signal [];'}{'b': 26', '25, 'a low-jitter, low phase noise carrier frequency oscillator [] operative for creating a master clock signal [];'}{'b': 24', '27', '16', '21', '25, 'a resynchronizing digital-to-analog converter [] operative for generating a resynchronized bitstream signal [] encoding the digital data signal [] based on the input bitstream [] and the master clock signal [];'}{'b': 28', '29', '27, 'a band pass filter [] operative for generating a filtered bitstream signal [] based on the resynchronized bitstream signal []; and'}{'b': 30', '31', '29', '14, 'a medium power amplifier [] operative for generating an output bitstream [] based on the filtered bitstream signal [] configured to drive ...

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07-07-2015 дата публикации

Low inductance flex bond with low thermal resistance

Номер: US0009078352B2

A electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.

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31-12-2009 дата публикации

Systems and Methods for Controlling a DC Motor

Номер: US2009322266A1
Принадлежит:

Various systems and methods for controlling DC motors are disclosed herein. For example, one method provides for controlling a polyphase, brushless DC motor. The method includes providing a DC motor that has a plurality of phases. Such a DC motor operates by inducing a current in the plurality of phases in accordance with a plurality of commutation states. In the example, six commutation states are discussed, but fewer than or more than six commutation states may exist. The method further includes initializing a count, inducing a current in the plurality of phases in accordance with a first commutation state, and incrementing the count until the current achieves a threshold in the first commutation state. Then, a current is induced in the plurality of phases in accordance with a second commutation state, and the count is decremented until the current achieves the threshold in the second commutation state. The sign bit of the count is stored, and a desired initial commutation state is determined ...

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09-12-2014 дата публикации

Hybrid digital/analog power amplifier

Номер: US0008908798B2
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.

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31-03-2015 дата публикации

Method and apparatus for high density pulse density modulation

Номер: US0008995521B2
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.

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18-03-2008 дата публикации

Signal processing in a disc drive

Номер: US0007345839B2

A disc drive system, such as a magnetic or optical recording and/or playback system, for low-data rate applications implements one or more circuit operations, such as read signal detection and related servo functions, as software-based digital signal processing steps in a dedicated software-based processor. The drive system incorporates increased buffering, modified input sample processing techniques, multiplexing of processing functions, and modified automatic gain control techniques to allow circuit operations to be performed with software-based digital signal processing techniques.

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20-01-2016 дата публикации

SERIAL PORT COMMUNICATION FOR STORAGE DEVICE USING SINGLE BIDIRECTIONAL SERIAL DATA LINE

Номер: KR1020160007421A
Принадлежит:

Provided is a method for enabling communication between a controller and a pre-amplifier in a storage device. For example, the method includes a step of materializing a serial port which is configured to transmit digital signals through a single bidirectional serial data line between the controller and the pre-amplifier. The serial port is controlled to selectively transmit the digital signals through the bidirectional serial data line in either a first direction from the controller to the pre-amplifier or a second direction from the pre-amplifier to the controller. COPYRIGHT KIPO 2016 (100) System-on-chip (102) Hard disk controller (104) Host interface controller (106) Motor control circuit (108) Memory controller (110) Recording channel circuit (112) Series port control circuit(Master) (114) Buffer memory (118) Host interface connector (122) Sub-interface (130) Pre-amplifier circuit (132) Series port control circuit(Slave) (140) Random access memory (150) Head/ Disk assembly (160) Spindle ...

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06-12-2007 дата публикации

Head-specific standby modes for disk drive preamplifiers and the like

Номер: US2007279785A1
Принадлежит:

A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.

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11-11-2015 дата публикации

MULTIPLEXED COMMUNICATION IN STORAGE DEVICE

Номер: KR1020150126307A
Принадлежит:

For example, provided is a method for performing multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of a read data circuit unit inside the recording channel is switchably connected to a first analog line of the analog bus to receive a read data transmitted from the preamplifier to the recording channel through the first analog line during read operation. In addition, a write data output of a write data circuit unit inside the recording channel is switchably connected to the first analog line of the analog bus to transmit a write data from the recording channel to the preamplifier through the first analog line during write operation. COPYRIGHT KIPO 2016 (100) System on chip (102) Hard disk controller (104) Host interface controller (106) Motor controller (108) Memory controller (110) Recording channel circuit unit (112) Synchronization series circuit port control circuit unit (114) Buffer memory (118) Host interface ...

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11-11-2015 дата публикации

MULTIPLEXED SYNCHRONOUS SERIAL PORT COMMUNICATION HAVING SKEW CONTROL FOR STORAGE DEVICE

Номер: KR1020150126304A
Принадлежит:

Provided is a method for performing multiplexed communication between a controller and a preamplifier inside a storage device. For example, the multiplexed communication comprises the following steps of: selectively transmitting digital signals in a first direction from the controller to the preamplifier or in a second direction from the preamplifier to the controller by controlling a bidirectional serial data line of a digital bus in response to a direction control signal; and synchronizing transferring and processing of the digital signals transmitted from the bidirectional serial data line by transmitting a synchronous clock signal through a clock signal line of the digital bus from the controller to the preamplifier. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus. COPYRIGHT KIPO 2016 (100) System on chip (102) Hard disk controller (104) Host interface controller ...

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06-04-2010 дата публикации

Method and apparatus for measuring resistance of a resistive sensor

Номер: US0007692887B2

An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.

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26-04-2016 дата публикации

Single-sideband transmitter using class-S amplifier

Номер: US0009325356B2

An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.

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03-03-2015 дата публикации

Interleaved multipath digital power amplification

Номер: US0008970406B2
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

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12-06-2014 дата публикации

SWITCHING POWER AMPLIFIER SYSTEM FOR MULTI-PATH SIGNAL INTERLEAVING

Номер: US20140159991A1
Принадлежит: LSI CORPORATION

A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

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01-11-2012 дата публикации

Systems and Methods for Laser Write Control

Номер: US20120275279A1
Принадлежит: LSI Corporation

Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted data write circuit is discussed that includes a heat write output, a magnetic write output, and a variable phase shift circuit operable to modify a relative phase of the heat write output to the magnetic write output.

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06-01-2015 дата публикации

Offset-tolerant low noise amplifier

Номер: US0008929012B1
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

The disclosure is directed to a low noise amplifier (LNA) configuration that compensates for DC offsets of incoming signals from a magnetoresistive head. According to various embodiments, the LNA includes a shunt-feedback differential pair of amplifiers adaptively biased according to a detected input DC voltage offset of the incoming signals from the magnetoresistive head. The LNA is thus enabled to amplify the AC signal component substantially unaffected by the DC offset. The DC component in the LNA output signal is then removable via offset compensating circuitry located between the LNA and subsequent stages without significant signal-to-noise ratio (SNR) penalty.

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01-05-2014 дата публикации

Digital Radio Frequency Clocking Methods

Номер: US20140119470A1
Принадлежит: LSI CORPORATION

A method and system for synchronous transfer of bitstream data between a power-driver chip and a digital signal processing chip in a digital radio frequency transmit system is disclosed. A master phase-locked-loop located in the power-driver chip is utilized to provide master clocking control for the digital radio frequency transmit system. Furthermore, the clocking method and system is configurable to secure precise carrier frequency positioning of a digitally-generated radio frequency signal based on predetermined chip frequencies unrelated to the carrier frequency, assuring low bitstream phase noise at the output of the power driver chip.

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17-04-2014 дата публикации

PREAMPLIFIER-TO-CHANNEL COMMUNICATION IN A STORAGE DEVICE

Номер: US20140104716A1
Принадлежит: LSI Corporation

An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a plurality of interconnects and (b) the first bus. The controller may be configured to send/receive the digital control signals over the interconnects. The apparatus may be configured to (i) read/write the analog data signals to the drive and (ii) generate the digital control signals, in response to one or more input/output requests received from a drive interface. 1. An apparatus comprising:a preamplifier configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus;a channel configured to (i) connect to said first and second bus, and (ii) send/receive said plurality of digital control signals through (a) a plurality of interconnects and (b) said first bus; anda controller configured to send/receive said digital control signals over said interconnects, wherein said apparatus is configured to (i) read/write said analog data signals to said drive and (ii) generate said digital control signals, in response to one or more input/output requests received from a drive interface.2. The apparatus according to claim 1 , wherein said preamplifier is fabricated on a first integrated circuit and said channel and said controller are generated on a second integrated circuit.3. The apparatus according to claim 2 , wherein said first integrated circuit is implemented using a bi-CMOS processing technology and said second ...

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18-09-2014 дата публикации

INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION

Номер: US2014269978A1
Принадлежит:

In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

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06-01-2015 дата публикации

Storage system with pattern dependent write

Номер: US0008929013B1
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

A storage system with pattern dependent write includes a magnetic write head, a magnetic storage medium, a read channel operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data and an associated clock from the read channel, to generate a pattern dependent write control signal based on a pattern in the write data and on the clock, and to set a write current level through the magnetic write head to a number of different current levels based on the pattern dependent write control signal.

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22-10-2013 дата публикации

Systems and methods for data write loopback based timing control

Номер: US0008565047B2

Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

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12-03-2015 дата публикации

Cascaded Viterbi Bitstream Generator

Номер: US2015074501A1
Принадлежит:

A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input ...

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01-08-2006 дата публикации

System and method for reducing circumferential transition incoherence in servowriting operations and magnetic disk drive incorporating the same

Номер: US0007085089B2

For use with a servowriter that includes a writer core having a plurality of transistors that route servowriting current in response to a servo write signal, a write transition controller, a method of operating the same and a magnetic disk drive incorporating the controller or the method. In one embodiment, the controller includes: (1) logic circuitry, coupled to the writer core, that selectively blocks the servo write signal based on a state of a write current control signal and (2) current shunt circuitry, coupled to the writer core, that operates concurrently with the logic circuitry selectively to shunt current around the writer core based on the state.

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21-04-2015 дата публикации

Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system

Номер: US0009013816B2
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

The disclosure is directed to a system and method of a system and method for determining fundamental bit cell duration of a data record, which can be used for pattern-dependent write (PDW) current control. According to various embodiments of the disclosure, at least a first portion of a data record is fed through a plurality of delay units. A binary output of each delay unit is stored in at least one register when the delay units have received the first portion of the data record. The register contents are then decoded to determine fundamental bit cell duration of the data record based upon the stored binary outputs.

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01-05-2014 дата публикации

Low Inductance Flex Bond with Low Thermal Resistance

Номер: US20140118966A1
Принадлежит: LSI CORPORATION

A electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.

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29-09-2009 дата публикации

Head-specific standby modes for disk drive preamplifiers and the like

Номер: US0007595951B2

A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.

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12-02-2015 дата публикации

High-Voltage Voltage-Switched Class-S Amplifier

Номер: US2015042403A1
Принадлежит:

A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal.

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15-01-2015 дата публикации

RADIO FREQUENCY COMPOSITE CLASS-S POWER AMPLIFIER HAVING DISCRETE POWER CONTROL

Номер: US2015015329A1
Принадлежит:

A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The combiner couples filtered signals provided by the channels to form a composite output signal. A method of providing digitally selectable amplification includes steps of: selectively coupling a digital bitstream to a plurality of channels in the amplifier; amplifying the digital bitstream to provide an amplified signal associated with a corresponding one of the channels; filtering amplified signals associated with the channels to provide corresponding filtered signals; and combining the filtered signals ...

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06-10-2015 дата публикации

Cross-talk measurement in array reader magnetic recording system

Номер: US0009153249B1
Принадлежит: LSI Corporation, LSI CORP, LSI CORPORATION

An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.

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05-03-2015 дата публикации

Adaptive Pattern Detection for Pattern-Dependent Write Current Control in a Magnetic Recording System

Номер: US20150062737A1
Принадлежит: LSI Corporation

The disclosure is directed to a system and method of a system and method for determining fundamental bit cell duration of a data record, which can be used for pattern-dependent write (PDW) current control. According to various embodiments of the disclosure, at least a first portion of a data record is fed through a plurality of delay units. A binary output of each delay unit is stored in at least one register when the delay units have received the first portion of the data record. The register contents are then decoded to determine fundamental bit cell duration of the data record based upon the stored binary outputs. 1. A system for determining fundamental bit cell duration of a data record , comprising:a plurality of delay units configured to receive at least a first portion of a data record;at least one register configured to store a binary output of each delay unit of the plurality of delay units when the plurality of delay units have received the first portion of the data record; anda decoder configured to determine a fundamental bit cell duration based upon the stored binary outputs of the plurality of delay units.2. The system of claim 1 , wherein the first portion of the data record includes at least a portion of a preamble of the data record.3. The system of claim 2 , wherein the preamble of the data record includes bit cells with uniform durations.4. The system of claim 1 , wherein the first portion of the data record includes a bit cell with a duration that is a multiple of the fundamental bit cell duration.5. The system of claim 4 , wherein the fundamental bit cell duration is half of the duration of the bit cell of the first portion of the data record.6. The system of claim 1 , wherein each delay unit of the plurality of delay units is configured to provide a delay of approximately t claim 1 , where t is a substantially fixed duration.7. The system of claim 6 , wherein the decoder is configured to determine the fundamental bit duration as a function of t ...

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20-11-2012 дата публикации

Heat assisted magnetic recording system

Номер: US0008315128B1

Various embodiments of the present invention provide apparatuses, systems and methods for heat assisted magnetic recording. For example, an apparatus is disclosed that includes a signal generator operable to generate laser trigger pulses at the transition rate of the magnetic write data signal, a variable delay element operable to control an alignment between the laser pulse control signal and the magnetic write data signal, a phase difference detector operable to control the variable delay element, a triggerable pulse generator circuit operable to generate a laser pulse control signal based on the laser trigger pulses, a magnetic write head operable to record data to a magnetic storage medium under control of the magnetic write data signal, and a laser diode operable to heat the magnetic storage medium under control of the laser pulse control signal.

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23-01-2014 дата публикации

Systems and Methods for Data Write Loopback Based Timing Control

Номер: US20140022876A1
Принадлежит: LSI Corporation

Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output. 1. A method for performing phase alignment in a recording channel , the method comprising:coupling a write output to a read data;determining a first delay from the write output to the read data;coupling a heat output to the read data;determining a second delay from the heat output to the read data;calculating a phase delay value corresponding to a difference between the first delay and the second delay; andmodifying a heat data path providing the heat output to delay the heat output by an amount corresponding to the phase delay value.2. The method of claim 1 , wherein the method further comprises:providing a write head operable to magnetize a storage medium, wherein a derivative of the write output is operable to excite the write head; andproviding a heat source operable to heat the storage medium, wherein a derivative of the heat output is operable to excite the heat source.3. The method of claim 2 , wherein the heat source is a laser claim 2 , and wherein the write is a magneto resistive write head.4. The method of claim 1 , wherein determining the first delay from the write output to the read data comprises:writing a pattern via a write data input;detecting the pattern in the read data; ...

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13-11-2012 дата публикации

High speed writer

Номер: US0008310776B2

An apparatus comprising a control circuit, a driver circuit and a write head. The control circuit may be configured to generate a plurality of control signals in response to a data input signal. The driver circuit may be configured to generate a differential write control signal in response to the plurality of control signals. The driver circuit may receive the plurality of control signals through a flexible bus. The driver circuit may be located remotely from the control circuit. The write head may be configured to write information by physically moving above one of a plurality of tracks on a disk in response to the write control signal. The driver circuit may be configured to move along with the write head.

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22-10-2013 дата публикации

Unipolar current driver

Номер: US0008565048B1

Various embodiments of the present invention provide single-ended and differential current drivers for heat assisted magnetic recording and other applications. For example, a current driver is disclosed that includes an upper output terminal and lower output terminal, a number of current switches operable to selectively contribute electrical currents through the upper and lower output terminals, a control input for each of the current switches operable to control the electrical currents, and a voltage supply operable to establish a voltage across the upper and output terminals.

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24-03-2015 дата публикации

Pre-amplifier input stage for multi-element magneto-resistive heads

Номер: US0008988803B1

Individual magneto-resistive read elements are connected to the pre-amplifier through a multi-conductor transmission line; one side of each magneto-resistive read element is taken to a single common lead which is also received in the read pre-amplifier. Amplification and bias control are performed by the read pre-amplifier. A low-noise input stage amplifier configuration accommodates a shared common lead in a multi-head environment. Means for independently biasing the magneto-resistive read elements are also provided. Feedback loops are employed to regulate the operating points of the input stages, and to set the potential of the common head terminal. Two-dimensional magnetic recording system testability is enhanced by ability to multiplex any head to a single system output.

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01-11-2012 дата публикации

Systems and Methods for Data Write Loopback Based Timing Control

Номер: US20120275278A1
Принадлежит: LSI Corporation

Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

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23-01-2007 дата публикации

Over-writing data in a recording system

Номер: US0007167330B2

A recording system stores recording cycle information identifying the parameters for recording user data on a particular data sector. During a subsequent operation, the recording system employs the recording cycle information to select a different set of parameters for recording new user data at the particular data sector. One of the parameters might identify a recorded pattern in a balance pad at the data sector, and another one of the parameters might identify a scrambler seed value. By employing a different set of recording parameters for each occurrence of recording user data at the particular sector, sample timing of, for example, a read channel might be based on an average of easy and hard transitions.

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29-07-2014 дата публикации

Storage device with driver controller providing pattern-dependent write functionality

Номер: US8792197B1
Принадлежит: LSI CORP, LSI CORPORATION

A hard disk drive or other storage device comprises a storage medium, a write head, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising write pulses responsive to write data, and a driver controller configured to adjust overshoot amplitudes of respective ones of the write pulses utilizing a segmented digital-to-analog converter. The overshoot amplitudes are adjusted by detecting patterns in the write data, decoding a first portion of a base overshoot value to identify a corresponding number of base overshoot segments, combining the base overshoot value and a differential overshoot value, decoding a first portion of the combined base overshoot and differential overshoot values to identify a corresponding number of enhanced overshoot segments, and selecting between the number of base overshoot segments and the number of enhanced overshoot segments responsive to detection of a particular pattern.

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06-09-2011 дата публикации

Systems and methods for controlling a DC motor

Номер: US0008013552B2

Various systems and methods for controlling DC motors are disclosed herein. For example, one method provides for controlling a polyphase, brushless DC motor. The method includes providing a DC motor that has a plurality of phases. Such a DC motor operates by inducing a current in the plurality of phases in accordance with a plurality of commutation states. In the example, six commutation states are discussed, but fewer than or more than six commutation states may exist. The method further includes initializing a count, inducing a current in the plurality of phases in accordance with a first commutation state, and incrementing the count until the current achieves a threshold in the first commutation state. Then, a current is induced in the plurality of phases in accordance with a second commutation state, and the count is decremented until the current achieves the threshold in the second commutation state. The sign bit of the count is stored, and a desired initial commutation state is determined ...

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18-09-2014 дата публикации

INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION

Номер: US2014266820A1
Принадлежит:

In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

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15-03-2012 дата публикации

HIGH SPEED WRITER

Номер: US20120063025A1
Принадлежит:

An apparatus comprising a control circuit, a driver circuit and a write head. The control circuit may be configured to generate a plurality of control signals in response to a data input signal. The driver circuit may be configured to generate a differential write control signal in response to the plurality of control signals. The driver circuit may receive the plurality of control signals through a flexible bus. The driver circuit may be located remotely from the control circuit. The write head may be configured to write information by physically moving above one of a plurality of tracks on a disk in response to the write control signal. The driver circuit may be configured to move along with the write head. 1. An apparatus comprising:a control circuit configured to generate a plurality of control signals in response to a data input signal;a driver circuit configured to generate a differential write control signal in response to said plurality of control signals, wherein said driver circuit (i) receives said plurality of control signals through a flexible bus and (ii) is located remotely from the control circuit; anda write head configured to write information by physically moving above one of plurality of tracks on a disk in response to said write control signal, wherein said driver circuit moves along with said write head.2. The apparatus according to claim 1 , wherein said differential write control signal comprises a center tap connected to a ground signal.3. The apparatus according to claim 1 , wherein said driver circuit is implemented with a plurality of NPN devices.4. The apparatus according to claim 1 , wherein said apparatus comprises a plurality of write heads and a plurality of corresponding driver circuits.5. The apparatus according to claim 4 , wherein each of said driver circuits receives (i) one or more control signals specific to said drive circuit and (ii) one or more control signals common to all of said driver circuits.6. The apparatus according ...

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13-03-2008 дата публикации

Method and apparatus for measuring resistance of a resistive sensor

Номер: US2008062551A1
Принадлежит:

An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.

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17-05-2016 дата публикации

Serial port communication for storage device using single bidirectional serial data line

Номер: US0009343103B2

A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.

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01-09-2005 дата публикации

Method and apparatus for write head demagnetization

Номер: US2005190476A1
Принадлежит:

An apparatus and method for demagnetizing a write head of a disc drive. Under control of a clock oscillator, synthetic demagnetizing pulses are generated and applied to a writer-driver bridge. Also under control of the clock oscillator, a write current produced by the writer-driver bridge incorporates the demagnetizing pulses and ramps down to about zero. The train of demagnetizing pulses and the write current ramp down demagnetizes the head, reducing write head magnetic bias that may influence the proximate read head of the disc drive head.

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11-08-2015 дата публикации

Switching power amplifier system for multi-path signal interleaving

Номер: US0009106207B2

A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

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23-05-2013 дата публикации

Magnetic Recording System With Multi-Level Write Current

Номер: US20130128375A1
Принадлежит:

Various embodiments of the present invention provide apparatuses, systems and methods for magnetic recording with a multi-level write current waveform. For example, an apparatus for magnetic recording with a multi-level write current waveform is disclosed that includes a pattern detection circuit operable to detect patterns in data to be written by the magnetic write head and to yield a pattern indicator signal, and a write driver operable to generate the multi-level write current waveform for the magnetic write head. At least one electrical characteristic of the multi-level write current waveform is based upon the patterns detected by the pattern detection circuit. 1. An apparatus for magnetic recording with a multi-level write current waveform comprising:a magnetic write head;a pattern detection circuit operable to detect patterns in data to be written by the magnetic write head and to yield a pattern indicator signal; anda write driver operable to generate the multi-level write current waveform for the magnetic write head, wherein at least one electrical characteristic of the multi-level write current waveform is based upon the patterns detected by the pattern detection circuit.2. The apparatus of claim 1 , wherein the patterns in the data to be written by the magnetic write head represent a magnetic saturation level of the magnetic write head.3. The apparatus of claim 2 , wherein the write driver is operable to generate a first write current level for a transition in the data to be written when the magnetic saturation level of the magnetic write head is above a particular saturation level and to generate a second write current level when the magnetic saturation level of the magnetic write head is below the particular saturation level claim 2 , wherein the first write current level is more aggressive than the second write current level.4. The apparatus of claim 1 , wherein the pattern detection circuit is operable to detect at least a first run length and a ...

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14-01-2016 дата публикации

SERIAL PORT COMMUNICATION FOR STORAGE DEVICE USING SINGLE BIDIRECTIONAL SERIAL DATA LINE

Номер: US20160012846A1
Принадлежит:

A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller. 1. A method to provide communication between a controller and a preamplifier in a storage device , comprising:implementing a serial port that is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line; andcontrolling the serial port to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.2. The method of claim 1 , wherein controlling the serial port comprises:transmitting a serial bit stream over the bidirectional serial data line from the controller to the preamplifier;generating a clock signal in the preamplifier using a phase-locked loop circuit, wherein the clock signal is generated based on a bit rate of the serial bit stream received by the preamplifier; andusing the clock signal to receive and deserialize the serial bit stream received by the preamplifier.3. The method of claim 2 , wherein controlling the serial port further comprises:transmitting a direction switch control signal over the bidirectional serial data line to the preamplifier; and generating a control signal to suspend phase and frequency adjustments of the phase-locked loop circuit of the preamplifier and maintain a static clock signal output from the phase-locked loop circuit of the preamplifier;', 'assuming control of the bidirectional ...

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15-01-2015 дата публикации

RADIO FREQUENCY COMPOSITE CLASS-S POWER AMPLIFIER HAVING DISCRETE POWER CONTROL

Номер: US20150015329A1
Принадлежит: LSI Corporation

A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The combiner couples filtered signals provided by the channels to form a composite output signal. A method of providing digitally selectable amplification includes steps of: selectively coupling a digital bitstream to a plurality of channels in the amplifier; amplifying the digital bitstream to provide an amplified signal associated with a corresponding one of the channels; filtering amplified signals associated with the channels to provide corresponding filtered signals; and combining the filtered signals to generate a composite output signal. 1. A composite amplifier that provides digitally selectable amplification , the composite amplifier comprising: a digitally controllable selector;', 'a Class-S power amplifier, the digitally controllable selector being operative to selectively couple a digital bitstream to the Class-S power amplifier, the Class-S power amplifier being operative to amplify the digital bitstream, thereby providing an amplified signal; and', 'a bandpass filter coupled with the Class-S power amplifier, the bandpass filter being operative to filter the amplified signal, thereby providing a filtered signal; and, 'a plurality of channels, each of the plurality of channels comprisinga combiner operative to couple filtered signals associated with the plurality of channels and to generate a composite output signal as a function of the filtered signals.2. The composite amplifier defined by claim 1 , further comprising a driver operatively coupling the digital bitstream to ...

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12-02-2015 дата публикации

High-Voltage Voltage-Switched Class-S Amplifier

Номер: US20150042403A1
Принадлежит:

A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal. 1. A voltage-switched class-S amplifier circuit , comprising:an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal; anda driver circuit coupled with the output stage, the driver circuit being configured to receive an input bit stream signal and being operative to generate the at least one control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the at least one control signal.2. The amplifier circuit of claim 1 , wherein the driver circuit comprises an isolation circuit connected in a signal path between the output stage and the input bit stream signal claim 1 , the isolation circuit being operative to electrically isolate the input bit stream signal from the at least one control signal.3. The amplifier circuit of claim 2 , wherein the isolation circuit comprises a voltage level shifter circuit including a first stage referenced to a first voltage supply and a second stage referenced to a second voltage supply claim 2 , the voltage level shifter circuit including a signal path between the first and second stages that is electrically isolated from one another.4. The amplifier circuit of claim 3 , further comprising a signal generator circuit operative to receive an input signal supplied to the amplifier circuit and to generate the second voltage supply as a ...

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25-02-2016 дата публикации

Single-sideband transmitter using class-s amplifier

Номер: US20160056848A1

An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.

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12-03-2015 дата публикации

Cascaded Viterbi Bitstream Generator

Номер: US20150074501A1
Принадлежит:

A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal. 1. A bitstream generator , comprising:at least first and second bitstream generator stages connected in a cascaded arrangement, the first bitstream generator stage including a first adder adapted to receive an input signal supplied to the bitstream generator and operative to generate a first error signal indicative of a difference between the input signal and a first bitstream candidate that represents a closest approximation to the input signal among a plurality of bitstream candidates generated by the first bitstream generator stage, the second bitstream generator stage including a second adder adapted to receive the first error signal generated by the first adder and operative to generate a second error signal indicative of a difference between the first error signal and a second bitstream candidate that represents a closest approximation to the input signal among a plurality of bitstream candidates generated by the second bitstream generator stage; anda third adder ...

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18-09-2014 дата публикации

Interleaved multipath digital power amplification

Номер: US20140266820A1
Принадлежит: LSI Corp

In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

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22-06-2017 дата публикации

Magnetic Recording System With Ternary Pattern Dependent Write Signaling

Номер: US20170178670A1
Принадлежит:

A storage system includes a magnetic write head, a magnetic storage medium, a write data circuit having a write data output and a magnet length signal output, and a preamplifier that receives the write data and a magnet length signal from the write data circuit, and sets at least one write current characteristic through the magnetic write head based at least in part on the magnet length signal. The write data circuit processes write data to be recorded on the magnetic storage medium by the magnetic write head. The magnet length signal output communicates magnet lengths in the write data. 1. A storage system , comprising:a magnetic write head;a magnetic storage medium;a write data circuit comprising a write data output to output write data and a magnet length signal output to output a magnet length signal that communicates magnet lengths in the write data, wherein the write data circuit is operable to process the write data to be recorded on the magnetic storage medium by the magnetic write head, and wherein at least some states of the magnet length signal are mapped to the magnet lengths to communicate the magnet lengths; anda preamplifier operable to receive the write data and the magnet length signal from the write data circuit, and to set at least one write current characteristic through the magnetic write head based at least in part on the magnet length signal.2. The storage system of claim 1 , wherein the write data circuit comprises a pattern detector operable to detect the magnet lengths in the write data.3. The storage system of claim 1 , wherein the preamplifier comprises a pattern dependent write controller operable to sample the magnet length signal to retrieve the magnet lengths.4. The storage system of claim 3 , wherein the pattern dependent write controller comprises a sampling clock enable signal operable to preclude the pattern dependent write controller from sampling the magnet length signal at transitions of the write data identified by previous ...

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18-09-2014 дата публикации

INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION

Номер: US20140269978A1
Принадлежит: LSI Corporation

In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects. 1. A system comprising: a fractional-delay array adapted to receive the first digital input signal and output a plurality of fractionally delayed digital output signals;', 'a bit-stream generation array adapted to receive the plurality of fractionally delayed digital output signals and output a plurality of corresponding bit-streams; and', 'a serializer block adapted to receive the plurality of corresponding bit-streams and interleave the bit-streams to generate the switching signal, wherein the frequency of the switching signal is higher than the frequency of the first digital input signal., 'an interleaved bit-stream generator adapted to receive a first digital input signal and output a switching signal, the interleaved-bit-stream generator comprising2. The system of claim 1 , wherein the frequency of the switching signal is higher than the frequency of all of the plurality of corresponding bit-streams.3. The system of claim 1 , wherein:the fractional-delay array comprises M fractional-delay filters, where M is an integer greater than 1;the bit-stream generator ...

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29-06-2017 дата публикации

Magnetic recording system using pattern dependent writer having register pages for storing write currents

Номер: US20170186448A1

A storage system includes a magnetic write head, a magnetic storage medium, a channel circuit comprising a write data output, wherein the channel circuit is operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data from the channel circuit, wherein the preamplifier comprises a number of register pages configured to store pattern dependent write current characteristics for a variety of magnet lengths, and wherein the preamplifier is operable to retrieve the write current characteristics based on magnet lengths and to record data bits on the magnetic storage medium using the write current characteristics.

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29-06-2017 дата публикации

Magnetic recording system including differentiated write current emphasis signal generator circuit

Номер: US20170186449A1

A storage system includes a magnetic storage medium, a magnetic write head, a channel circuit and a preamplifier. The channel circuit includes a write data input, a differentiated edge emphasis signal generator, a write data output and a differentiated edge emphasis signal output. The preamplifier includes a write data input configured to receive write data from the channel circuit write data output, an edge emphasis signal input configured to receive a differentiated edge emphasis signal from the channel circuit differentiated edge emphasis signal output, and a write current edge emphasis controller configured to generate a write current to the magnetic write head based at least in part on the write data and on the differentiated edge emphasis signal.

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22-10-2015 дата публикации

Cross-Talk Measurement In Array Reader Magnetic Recording System

Номер: US20150302887A1
Принадлежит: LSI Corp

An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.

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05-11-2015 дата публикации

MULTIPLEXED COMMUNICATION IN A STORAGE DEVICE

Номер: US20150318014A1
Принадлежит: LSI Corporation

A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation. 1. A method to implement multiplexed communication between a recording channel and a preamplifier in a storage device , comprising:switchably connecting a first input of read data circuitry within the recording channel to a first analog line of an analog bus to receive first read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation; andswitchably connecting a write data output of write data circuitry within the recording channel to the first analog line to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.2. The method of claim 1 , further comprising:switchably connecting a second input of the read data circuitry to a second analog line of the analog bus to receive second read data transmitted from the preamplifier to the recording channel over the second analog line during the read operation; andswitchably connecting a write control output of the write data circuitry to the second analog line to transmit a write control signal from the recording channel to the preamplifier over the second analog line during the write operation.3. The method of claim 2 , wherein the write control signal comprises a clock signal.4. The method of claim 3 , wherein the ...

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05-11-2015 дата публикации

MULTIPLEXED SYNCHRONOUS SERIAL PORT COMMUNICATION WITH SKEW CONTROL FOR STORAGE DEVICE

Номер: US20150318030A1
Принадлежит: LSI Corporation

A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus. 1. A method to implement multiplexed communication between a controller and a preamplifier in a storage device , comprising:controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal; andconcurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus,wherein the direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.2. The method of claim 1 , wherein the digital signals transmitted in the first direction include register data claim 1 , and write mode and read mode control signals claim 1 , and wherein the digital signals transmitted in the ...

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24-01-2018 дата публикации

Low inductance flex bond with low thermal resistance

Номер: EP2725611A3
Принадлежит: LSI Corp

An electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.

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10-07-2013 дата публикации

Heat assisted magnetic recording system

Номер: EP2613317A1
Принадлежит: LSI Corp

Various embodiments of the present invention provide apparatuses, systems and methods for heat assisted magnetic recording. For example, an apparatus is disclosed that includes a signal generator operable to generate laser trigger pulses (240) at the transition rate of the magnetic write data signal (216), a variable delay element (446) operable to control an alignment between the laser pulse control signal (240) and the magnetic write data signal (216), a phase difference detector (262) operable to control the variable delay element (446), a triggerable pulse generator circuit operable to generate a laser pulse control signal (264) based on the laser trigger pulses (240), a magnetic write head (232) operable to record data to a magnetic storage medium under control of the magnetic write data signal (216), and a laser diode (242) operable to heat the magnetic storage medium under control of the laser pulse control signal (264).

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24-07-2014 дата публикации

High-voltage voltage-switched class-s amplifier

Номер: WO2014113027A1
Принадлежит: LSI Corporation

A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal.

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25-03-2015 дата публикации

Storage device with driver controller providing pattern-dependent write functionality

Номер: EP2851899A1
Принадлежит: LSI Corp

A hard disk drive or other storage device comprises a storage medium, awrite head, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising write pulses responsive to write data, and a driver controller configured to adjust overshoot amplitudes of respective ones of the write pulses utilizing a segmented digital-to-analog converter. The overshoot amplitudes are adjusted by detecting patterns in the write data, decoding a first portion of a base overshoot value to identify a corresponding number of base overshoot segments, combining the base overshoot value and a differential overshoot value, decoding a first portion of the combined base overshoot and differential overshoot values to identify a corresponding number of enhanced overshoot segments, and selecting between the number of base overshoot segments and the number of enhanced overshoot segments responsive to detection of a particular pattern.

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02-09-2014 дата публикации

Laser power control in a heat-assisted magnetic recording system

Номер: US8824085B2
Принадлежит: LSI Corp

A heat-assisted magnetic recording system may include, but is not limited to: at least one magnetic recording read/write head; at least one laser diode configured to illuminate at least a portion of at least one magnetic recording medium; at least one laser power level sensor configured to detect a power level of the at least one laser diode; and a controller configured to modify one or more power level settings associated with the at least one laser diode in response to one or more output signals of the at least one laser power level sensor.

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30-08-2016 дата публикации

Preamplifier common-mode noise rejection for two-dimensional magnetic recording

Номер: US9431050B1

An apparatus for two-dimensional magnetic recording includes an array reader with a number of magnetoresistive read sensors configured to read data from a storage medium. The magnetoresistive read sensors have a number of connection terminals, with at least one of the connection terminals being shared by more than one of the magnetoresistive read sensors. The apparatus also includes a number of low-noise amplifiers connected to the connection terminals, each configured to amplify a differential signal from a different one of the magnetoresistive read sensors. The apparatus also includes a number of impedance balancing networks connected to a subset of the connection terminals.

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06-12-2007 дата публикации

Head-specific standby modes for disk drive preamplifiers and the like

Номер: US20070279785A1
Принадлежит: Agere Systems LLC

A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.

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05-09-2017 дата публикации

Magnetic recording system with ternary pattern dependent write signaling

Номер: US09754610B2

A storage system includes a magnetic write head, a magnetic storage medium, a write data circuit having a write data output and a magnet length signal output, and a preamplifier that receives the write data and a magnet length signal from the write data circuit, and sets at least one write current characteristic through the magnetic write head based at least in part on the magnet length signal. The write data circuit processes write data to be recorded on the magnetic storage medium by the magnetic write head. The magnet length signal output communicates magnet lengths in the write data.

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01-08-2017 дата публикации

Magnetic recording system including differentiated write current emphasis signal generator circuit

Номер: US09721588B2

A storage system includes a magnetic storage medium, a magnetic write head, a channel circuit and a preamplifier. The channel circuit includes a write data input, a differentiated edge emphasis signal generator, a write data output and a differentiated edge emphasis signal output. The preamplifier includes a write data input configured to receive write data from the channel circuit write data output, an edge emphasis signal input configured to receive a differentiated edge emphasis signal from the channel circuit differentiated edge emphasis signal output, and a write current edge emphasis controller configured to generate a write current to the magnetic write head based at least in part on the write data and on the differentiated edge emphasis signal.

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25-07-2017 дата публикации

Magnetic recording system using pattern dependent writer having register pages for storing write currents

Номер: US09715887B2

A storage system includes a magnetic write head, a magnetic storage medium, a channel circuit comprising a write data output, wherein the channel circuit is operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data from the channel circuit, wherein the preamplifier comprises a number of register pages configured to store pattern dependent write current characteristics for a variety of magnet lengths, and wherein the preamplifier is operable to retrieve the write current characteristics based on magnet lengths and to record data bits on the magnetic storage medium using the write current characteristics.

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06-06-2017 дата публикации

Radio frequency bitstream generator and combiner providing image rejection

Номер: US09673859B2

A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering.

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18-10-2016 дата публикации

High-voltage voltage-switched class-S amplifier

Номер: US09473086B2

A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal.

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06-09-2016 дата публикации

Magnetoresistive reader for two-dimensional magnetic recording

Номер: US09437219B1

An apparatus for two-dimensional magnetic recording includes a storage medium, an array of magnetoresistive read heads disposed adjacent the storage medium and spaced to read a data track, a number of leads connected to the array of magnetoresistive read heads, and number of bias circuits connected to the array of read heads by the leads. The bias circuits can be configured to independently bias each of the array of read heads with the array of read heads connected in series or in parallel.

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