Semiconductor device and manufacturing method therefor

A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much. Because the bumps are not formed on the defective units, Schottky-barrier-side electrodes 3 are connected in parallel to the exterior of the device through the bumps 11, and a wiring layer 13 and an external lead 13a of a wiring substrate 12; thus, only the external output electrodes 4 of the non-defective units ...

Verfahren zur Herstellung einer Siliziumkarbid-Halbleitervorrichtung

Verfahren zum Herstellen von einer Siliziumkarbid-Halbleitervorrichtung, welches die Schritte enthält: (a) Vorbereiten eines Siliziumkarbid-Substrats (1) mit eine ersten und zweiten Hauptoberfläche; (b) Ausbilden von einer Epitaxieschicht (2) auf der ersten Hauptoberfläche von dem Siliziumkarbid-Substrat (1); (c) Ausbilden von einem SiO2 Film als Schutzfilm (10) auf der Epitaxieschicht (2); (d) Ausbilden von einer ersten Metallschicht (6) auf der zweiten Hauptoberfläche von dem Siliziumkarbid-Substrat (1); (e) Anwenden, nach dem Schritt (d), von einer Wärmebehandlung auf das Siliziumkarbid-Substrat (1) bei einer vorbestimmten Temperatur, um eine Ohmsche Verbindung zwischen der ersten Metallschicht (6) und der zweiten Hauptoberfläche von dem Siliziumkarbid-Substrat (1) auszubilden; (f) gänzliches Entfernen des Schutzfilms (10) nach dem Schritt (e); (g) Ausbilden, nach dem Schritt (f), einer Ti-Schicht (5) auf der Epitaxieschicht (2); und (i) Anlegen von einer Musterung auf die Ti-Schicht (5), nach dem Schritt (g), durch Nass-Ätzung. (h) Anwenden, nach dem Schritt (i), von einer Wärmebehandlung auf das Siliziumkarbid-Substrat (1) bei einer Temperatur von 400°C bis 600°C, um eine Schottky-Verbindung von gewünschten Eigenschaften zwischen der zweiten Metallschicht (5) und der Epitaxieschicht (2) auszubilden. (j) Anlegen eines Oberflächen-Dichtungsmittels (8) auf die Epitaxieschicht (2) und auf die Ti-Schicht (5), und Anwenden von einer Wärmebehandlung auf das Oberflächen-Dichtungsmittel (8) bei einer Temperatur, welche um zumindest 50°C geringer als die Temperatur von der Wärmebehandlung in dem Schritt (h) ist.

Festkörper-Bildaufnahmevorrichtung

Halbleiterbauelement und Verfahren zu dessen Herstellung

In einem Zellenbereich einer ersten Hauptoberfläche eines Halbleitersubstrats eines ersten Leitfähigkeitstyps befindet sich eine erste Mulde eines zweiten Leitfähigkeitstyps in einer oberen Oberfläche. Ein Diffusionsbereich eines ersten Leitfähigkeitstyps befindet sich in der oberen Oberfläche in der ersten Mulde. Eine erste Gateisolierschicht befindet sich an der ersten Mulde und eine erste Gateelektrode an der ersten Gateisolierschicht. Eine zweite Mulde eines zweiten Leitfähigkeitstyps befindet sich in der oberen Oberfläche der ersten Hauptoberfläche an einem Umfangsbereich des Zellenbereichs. Eine zweite Gateisolierschicht befindet sich an der zweiten Mulde, und eine dicke Feldoxidschicht befindet sich an der Umfangsseite der zweiten Gateisolierschicht. Eine zweite Gateelektrode befindet sich sequentiell an der zweiten Gateisolierschicht und der Feldoxidschicht und ist mit der ersten Gateelektrode elektrisch verbunden. Eine erste Elektrode ist mit der ersten Mulde, der zweiten Mulde ...

Halbleitervorrichtung

Die Aufgabe der vorliegenden Erfindung besteht darin, eine Halbleitervorrichtung anzugeben, die einen Leckstrom und einen Einschaltwiderstand verringern kann, und mit der beim Schalten ein Betrieb mit hoher Geschwindigkeit möglich ist. Gemäß der vorliegenden Erfindung wird eine Halbleitervorrichtung angegeben, die eine Zellenanordnung (Cell-Array) aufweist, in welcher normale Zellen (6) angeordnet sind, und in welcher Kontaktzellen (7) verstreut um die Anordnung von normalen Zellen (6) herum angeordnet sind. Die Halbleitervorrichtung weist folgendes auf: eine Halbleiterschicht (2) vom n-Typ, die auf einem Halbleitersubstrat (1) vom n+-Typ ausgebildet ist; eine eingebettete Schicht (5) vom p-Typ, die innerhalb der Halbleiterschicht (2) vom n-Typ eingebettet ist; und eine Oberflächenschicht (4) vom p-Typ, die in dem mittleren Bereich einer jeden der normalen Zellen (6) und der Kontaktzellen (7) angeordnet ist. In der Kontaktzelle (7) steht die eingebettete Schicht (5) vom p-Typ mit der Oberflächenschicht ...

Siliziumcarbid-Halbleitervorrichtung

Eine SiC-Halbleitervorrichtung enthält ein Halbleiterelement, das in einem SiC-Substrat 1 ausgebildet ist, eine Sourceelektrode 15 und eine Gateanschlussfläche 16, die unter Verwendung einer Verdrahtungsschicht ausgebildet sind und an deren Unterseiten ein Barrierenmetall 14 vorhanden ist, und ein Temperaturmessungs-Widerstandselement 20, das unter Verwendung eines Teilabschnitts des Barrierenmetalls 14 in der Verbindungsleitung ausgebildet ist.

Method of manufacturing silicon carbide semiconductor device

A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V.

Halbleiterbauelement und Verfahren zu dessen Herstellung

Halbleiterbauelement, das folgendes aufweist: ein Halbleitersubstrat (10) eines ersten Leitfähigkeitstyps, das eine erste Hauptoberfläche und eine zweite Hauptoberfläche hat, die einander gegenüber liegen; eine erste Mulde (22) eines zweiten Leitfähigkeitstyps in einer oberen Oberfläche einer Driftschicht (20), welche auf der ersten Hauptoberfläche in einem Zellenbereich (12) der ersten Hauptoberfläche gebildet ist; einen Diffusionsbereich (24, 76) eines ersten Leitfähigkeitstyps in der oberen Oberfläche der Driftschicht (20) in der ersten Mulde (22); eine erste Gateisolierschicht (36) an der ersten Mulde (22); eine erste Gateelektrode (38) an der ersten Gateisolierschicht (36); eine zweite Mulde (28) eines zweiten Leitfähigkeitstyps in der oberen Oberfläche der Driftschicht (20) an einem Umfangsbereich des Zellenbereichs (12); eine zweite Gateisolierschicht (40) an der zweiten Mulde (28); eine Feldoxidschicht (42) an der zweiten Mulde (28) an der Umfangsseite der zweiten Gateisolierschicht ...

Halbleitervorrichtung und Verfahren zur Fertigung derselben

Zur Verfügung gestellt wird eine Halbleitervorrichtung, die einen aktiven Bereich, der in einer Halbleiterschicht einer ersten Leitfähigkeitsart vorgesehen ist, und einen Terminierungsbereich, der um den aktiven Bereich vorgesehen ist, aufweist. Ein MOS-Transistor, durch welchen ein Hauptstrom in einer Dickenrichtung der Halbleiterschicht fließt, ist in dem aktiven Bereich ausgebildet. Der Terminierungsbereich weist eine Defekterkennungsvorrichtung auf, die entlang des aktiven Bereichs vorgesehen ist. Die Defekterkennungsvorrichtung weist eine Diode auf, die eine erste Hauptelektrode, die entlang des aktiven Bereichs auf einer ersten Hauptoberfläche der Halbleiterschicht vorgesehen ist, und eine zweite Hauptelektrode, die auf einer zweiten Hauptoberflächenseite der Halbleiterschicht vorgesehen ist, aufweist.

SILICON CARBIDE SEMICONDUCTOR DEVICE

A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode. 1. A silicon carbide semiconductor device comprising:a drift layer of a first conduction type;a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer;a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region;a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; anda surface electrode pad on the Schottky electrode,wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.2. The silicon carbide semiconductor device according to claim 1 , wherein the outer peripheral end of the surface electrode pad exists above the guard ring region.3. The silicon carbide semiconductor device according to claim 1 , further comprising a high-concentration region of the second conduction type having an impurity concentration higher than an impurity concentration in the guard ring region and formed in the guard ring region from a surface of the guard ring region.4. The silicon carbide semiconductor device according to claim 1 , ...

PRESSURE SENSOR

A pressure sensor comprises a diaphragm (6) with a first surface that receives pressure, and a thermal detector (3) having a heat-sensitive resistor opposed to the diaphragm with a spacer between. Since the quantity of displacement of the diaphragm due to the change in pressure is detected as the change in the state of heat equilibrium in the thermal detector, the diaphragm surface that receives pressure directly from the fluid for measurement does not require any treatment, such as filming and photochemical treatments. Therefore, main parts of the thermal pressure detector can be made in great quantities on a silicon wafer in a simple manufacturing process. This provides low-cost pressure sensors while improving the accuracy and reliability of thermal pressure detector elements. © KIPO & WIPO 2007 ...

Silicon carbide semiconductor device and method of manufacturing the same

It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.

SILICON CARBIDE SEMICONDUCTOR DEVICE

An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.

Festkörper-Bildaufnahmevorrichtung

PRESSURE SENSOR

A pressure sensor comprises a diaphragm (6) with a first pressure-sensitive surface, a first thermal detector (3) having a heat-sensitive resistor opposed to a central portion of the diaphragm with a spacer (7), and a second thermal detector having a heat- sensitive resistor opposed to a diaphragm portion where a pressure change causes little or no displacement. The difference between the signals from the first sensor for pressure measurement and the second sensor for reference output is amplified and provided as output. The diaphragm area opposed to the second sensor (8) and the diaphragm area opposed to the first sensor (3) have the same film thickness, and the change in output with abrupt change in ambient temperature is fairly small, allowing pressure measurements with high accuracy. © KIPO & WIPO 2007 ...

Silicon carbide semiconductor device

A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.

Verfahren zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung

Zum Ausbilden eines Metallfilms auf einem Siliziumkarbidwafer (10) wird ein Target (23) aus einem Metallmaterial zerstäubt. Zu diesem Zeitpunkt wird der Metallfilm unter der Randbedingung ausgebildet, dass eine Auftreffenergie des Auftreffens des an dem Target (23) zerstäubten Metallmaterials und eines durch eine Gaseinlassöffnung (27) einfließenden Sputtergases auf den Siliziumkarbidwafer (10) niedriger ist als eine Bindungsenergie des Siliziumkarbids und spezieller niedriger ist als 4,8 eV. Beispielsweise wird der Metallfilm ausgebildet, während eine an eine Kathode (21) und eine Anode (22) angelegte Hochfrequenzspannung auf einen Wert gesetzt ist, der größer oder gleich 20 V und kleiner oder gleich 300 V ist.

FESTKOERPERBILDSENSOR

EPITAXIAL-WAFER UND HALBLEITERELEMENT

Ein Siliciumkarbid-Halbleiterelement (101) weist folgendes auf: ein n-leitendes Siliciumkarbid-Substrat (1), in das ein Dotierstoff mit einer durch Dotieren abnehmenden Gitterkonstante, wie z. B. Stickstoff, mit einer Konzentration C dotiert ist; eine n-leitende, epitaxial aufgewachsene Siliciumkarbid-Schicht (3), in die der gleiche Dotierstoff wie bei dem Siliciumkarbid-Substrat (1) mit einer geringeren Konzentration als der Konzentration des Siliciumkarbid-Substrats dotiert ist; und eine n-leitende Pufferschicht, in die der Dotierstoff dotiert ist, zwischen dem Siliciumkarbid-Substrat (1) und der epitaxial aufgewachsenen Siliciumkarbid-Schicht (3). Eine Pufferschicht (2) ist mit einer mehrlagigen Struktur ausgebildet, die zwei oder mehr aufeinander geschichtete Lagen mit der gleichen Dicke aufweist, wobei die Pufferschicht derart ausgebildet ist, dass eine Dotierungskonzentration einer K-ten Schicht ausgehend von der Seite der epitaxial aufgewachsenen Siliciumkarbid-Schicht (3) C·K/(N ...

SILICON CARBIDE SEMICONDUCTOR DEVICE INCLUDING AN ELEMENT FOR DETECTING TEMPERATURE WITH EXCELLENT HEAT RESISTANCE

PURPOSE: A silicon carbide semiconductor device is provided to be used in a high temperature by using a temperature measurement resistor including barrier metal. CONSTITUTION: A p-well region(3) is selectively formed in the upper surface of an epitaxial layer(2). An n-type source region(5) is formed in the surface part of the p-well region. A terminal p-well region(4) is formed in the upper surface of the epitaxial layer. A gate oxide film(8) covering an active area and a field oxide film(9) covering a termination region are formed on the epitaxial layer. A gate electrode(10) is formed over the p-well region. COPYRIGHT KIPO 2013 ...

Pressure sensor

A pressure sensor includes a first diaphragm having a first surface receiving pressure, a first thermal detection section located opposite a central section of the first diaphragm, and a second thermal detection section having little displacement by pressure, and located opposite the first diaphragm The pressure sensor amplifies and outputs a difference between the first thermal detection section for pressure measurement and the second thermal detection section for reference output. Since the diaphragm to which the second thermal detection section is opposed is equal in thickness to the diaphragm to which the first thermal detection section is opposed, pressure can be accurately measured relative to a sudden change in atmospheric temperature.

Silicon carbide semiconductor device

An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.

Semiconductor device including a cell array having first cells and second cells interspersed around the arrangement of the first cells

A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n-type semiconductor layer. The anode electrode forms a Schottky junction with the n-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.

Pressure sensor

A pressure sensor includes a diaphragm having a first surface receiving pressure, and a first thermal detection section opposed to a central section of the diaphragm through a spacer and having a thermo-sensitive resistance section, and a second thermal detection section opposed to an end section of the diaphragm and having a thermo-sensitive resistance section, wherein the first thermo-sensitive resistance section and second thermo-sensitive resistance section are connected to independent, adjustable constant-current sources, respectively, and are connected to a differential amplifier which amplifies a difference between (i) a voltage of the first thermal detection section, which detects a displacement quantity of the diaphragm due to pressure change as a displacement quantity of a thermal equilibrium state by the thermal detection section, and (ii) a voltage of the second thermal detection section, which does not change according to pressure. The sensor can measure pressure with high ...

Siliziumcarbid-Halbleitervorrichtung

Eine Siliziumcarbid-Halbleitervorrichtung umfasst Folgendes: eine Driftschicht (1b) eines ersten Leitungstyps; einen Schutzringbereich (2) eines zweiten Leitungstyps, der in einer Ringform in einem Abschnitt von einer Oberfläche der Driftschicht ausgebildet ist; einen Feldisolationsfilm (3), der auf der einen Oberfläche der Driftschicht ausgebildet ist und den Schutzringbereich umgibt; eine Schottky-Elektrode (4), die den Schutzringbereich und die Driftschicht umgibt, die innerhalb des Schutzringbereichs freiliegt, und ein äußeres Umfangsende aufweist, das auf dem Feldisolationsfilm liegt; und eine Oberflächenelektroden-Kontaktstelle (5) auf der Schottky-Elektrode, wobei ein äußeres Umfangsende der Oberflächenelektroden-Kontaktstelle mit dem Feldisolationsfilm über dem äußeren Umfangsende der Schottky-Elektrode in Kontakt kommt. A silicon carbide semiconductor device includes: a drift layer (1b) of a first conductivity type; a guard ring portion (2) of a second conductivity type formed in a ring shape in a portion of a surface of the drift layer; a field insulating film (3) formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode (4) surrounding the guard ring portion and the drift layer exposed within the guard ring portion and having an outer peripheral end lying on the field insulating film; and a surface electrode pad (5) on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.

Halbleitervorrichtung und Herstellungsverfahren dafür

Es wird eine Halbleitervorrichtung erhalten, bei der hervorragende Eigenschaften erzielt werden, die Zuverlässigkeit verbessert ist und für die Herstellung auch ein SiC-Wafer verwendet werden kann. Eine Mehrzahl von Schottky-Barrierendiodeneinheiten 10 ist auf einem SiC-Chip 9 ausgebildet und jede der Einheiten 10 hat eine externe Ausgangseleketrode 4 unabhängig von den anderen. Bumps 11 (der Durchmesser reicht von einigen 10 bis einigen 100 mum) sind lediglich auf den externen Ausgangselektroden 4 der nicht defekten Einheiten unter den Einheiten 10, die auf dem SiC-Chip 9 ausgebildet sind, ausgebildet, während Bumps nicht ausgebildet sind auf den externen Ausgangselektroden 4 der defekten Einheiten, bei denen die Spannungsfestigkeit zu niedrig ist oder der Leckstrom zu hoch ist. Da die Bumps nicht auf den defekten Einheiten ausgebildet sind, sind Schottky-Barriereseitige Elektroden 3 über die Bumps 11 und eine Verdrahtungsschicht 13 und eine externe Leitung 13a eines Verdrahtungssubstrats ...

Halbleitervorrichtung

Halbleitervorrichtung, die eine Zellenanordnung aufweist, wobei erste Zellen (6) angeordnet sind und zweite Zellen (7) verstreut um die Anordnung von ersten Zellen herum angeordnet sind, wobei die Halbleitervorrichtung Folgendes aufweist:- eine Halbleiterschicht (2) von einem ersten Leitfähigkeitstyp, wobei die Halbleiterschicht (2) epitaxial auf einem Halbleitersubstrat (1) vom ersten Leitfähigkeitstyp ausgebildet ist;- eine eingebettete Schicht (5), die aus einem Halbleiter von einem zweiten Leitfähigkeitstyp gebildet ist, wobei die eingebettete Schicht (5) innerhalb der Halbleiterschicht (2) eingebettet ist, und wobei die eingebettete Schicht (5) in einem peripheren Bereich der ersten Zelle (6) vorgesehen ist und überall im gesamten Bereich der zweiten Zelle (7) vorgesehen ist;- mindestens einen der folgenden Bestandteile:- eine erste Oberflächenschicht (4, 4a, 4b), die aus einem Halbleiter vom zweiten Leitfähigkeitstyp gebildet ist, und- eine Kontaktschicht (8, 8a), die aus einem Halbleiter ...

Verfahren zur Herstellung einer Siliziumkarbid-Halbleitervorrichtung

Es ist eine Aufgabe von der Erfindung, ein Verfahren zum Herstellen von einer Siliziumkarbid-Halbleitervorrichtung bereitzustellen, welche konstante Eigenschaften mit reduzierten Schwankungen in Durchlasskennlinien hat. Das Verfahren zum Herstellen von der Siliziumkarbid-Halbleitervorrichtung gemäß der Erfindung enthält die Schritte: (a) Vorbereiten eines Siliziumkarbid-Substrats; (b) Ausbilden von einer Epitaxieschicht auf einer ersten Hauptoberfläche von dem Siliziumkarbid-Substrat; (c) Ausbilden von einem Schutzfilm auf der Epitaxieschicht; (d) Ausbilden von einer ersten Metallschicht auf einer zweiten Hauptoberfläche von dem Siliziumkarbid-Substrat; (e) Anwenden von einer Wärmebehandlung auf das Siliziumkarbid-Substrat bei einer vorbestimmten Temperatur, um eine Ohmsche Verbindung zwischen der ersten Metallschicht und der zweiten Hauptoberfläche von dem Siliziumkarbid-Substrat auszubilden; (f) Entfernen des Schutzfilms; (g) Ausbilden von einer zweiten Metallschicht auf der Epitaxieschicht ...

Verfahren zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung

Verfahren zum Herstellen einer Siliziumkarbid-Schottky-Diode, wobei das Verfahren folgende Schritte aufweist: (a) Ausführen einer Ionenimplantation an einer Siliziumkarbidschicht (2), die eine (0001)-Siliziumoberfläche oder eine (000-1)-Kohlenstoff-Oberfläche aufweist; (b) Ausführen einer Aktivierungswärmebehandlung an der ionenimplantierten Siliziumkarbidschicht (2); (c) Entfernen einer Oberflächenschicht (5a) der Siliziumkarbidschicht (4), an der die Aktivierungswärmebehandlung ausgeführt worden ist, durch Trockenätzen; (d) Bilden einer Opferoxidschicht (6) auf einer Oberflächenschicht der Siliziumkarbidschicht (2), an der das Trockenätzen ausgeführt worden ist, durch Ausführen einer Opferoxidation an dieser; und (e) Entfernen der Opferoxidschicht (6) durch Naßätzen. wobei die Dicke der Siliziumkarbidschicht, die durch Bilden und Entfernen der Opferoxidschicht (6) entfernt wird, 20 nm bis 40 nm beträgt.

Verfahren zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung

Ein Ziel besteht in der Angabe eines Verfahrens zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung, bei dem die zum Entfernen einer Opferoxidschicht erforderliche Zeit verkürzt werden kann und eine Beschädigung einer Oberfläche der Siliziumkarbidschicht vermindert werden kann. Das Verfahren zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung weist folgende Schritte auf: (a) Ausführen einer Ionenimplantation an einer Siliziumkarbidschicht; (b) Ausführen einer Aktivierungswärmebehandlung an der ionenimplantierten Siliziumkarbidschicht; (c) Entfernen einer Oberflächenschicht der Siliziumkarbidschicht, an der die Aktivierungswärmebehandlung ausgeführt worden ist, durch Trockenätzen; (d) Bilden einer Opferoxidschicht auf einer Oberflächenschicht der Siliziumkarbidschicht, an der das Trockenätzen ausgeführt worden ist, durch Ausführen einer Opferoxidation an dieser; und (e) Entfernen der Opferoxidschicht durch Naßätzen.

SiC-Halbleitervorrichtung und Herstellungsverfahren dafür

Halbleitervorrichtung mit: einer Mehrzahl von Halbleitereinheiten (10), die auf einem Halbleiterchip (9) unter Verwendung eines SiC-Wafers ausgebildet sind, externen Ausgangselektroden (4), die unabhängig voneinander auf den Halbleitereinheiten ausgebildet sind, jede auf einer der Einheiten, gekennzeichnet durch Bumps (11), die selektiv auf den externen Ausgangselektroden (4) der nicht defekten Halbleitereinheiten unter den Halbleitereinheiten, die nicht defekte und defekte Einheiten beinhalten, ausgebildet sind, einem Verdrahtungssubstrat (12), das mit einer elektrisch mit den Bumps verbundenen Verdrahtungsschicht (13) versehen ist, und Dummy-Bumps (11a), die auf einer anderen Region als den externen Ausgangselektroden (4) ausgebildet sind, zum Verbinden der Region mit dem Verdrahtungssubstrat (12).

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching. 1. A method for manufacturing a silicon carbide Schottky diode , the method comprising:(a) implanting ions, in an ion implantation, a silicon carbide layer having a silicon surface or a carbon surface to obtain an ion-implanted silicon carbide layer;(b) annealing, in an activation annealing, the ion-implanted silicon carbide layer to obtain an annealed silicon carbide layer;(c) removing a first surface layer of the annealed silicon carbide layer by a dry etching to obtain a dry etched silicon carbide layer;(d) forming a sacrificial oxide film on a second surface layer of the dry etched silicon carbide layer by performing sacrificial oxidation thereto; and(e) removing the sacrificial oxide film by wet etching.2. The method of claim 1 ,wherein the activation annealing is performed to the ion-implanted silicon carbide layer by forming a graphite film on a surface of the ion-implanted silicon carbide layer.3. The method of claim 1 ,wherein a thickness of the second surface layer that is removed by forming and removing the sacrificial oxide film is from 20 nm to 40 nm.4. The method of claim 1 ,wherein a thickness of the first surface layer that is removed by ...

PRESSURE SENSOR

A pressure sensor comprises a diaphragm (6) with a first pressure-sensitive surface, a first thermal detector (3) having a heat-sensitive resistor opposed to a central portion of the diaphragm with a spacer (7), and a second thermal detector having a heat- sensitive resistor opposed to a peripheral portion of the diaphragm where a pressure change causes little or no displacement. The first and second thermal sensors are connected to constant-current sources (23,28), respectively, which are independently controlled. A differential amplifier is connected to receive the voltage produced by the first sensor that detects the diaphragm displacement with a change in pressure as a change in thermal equilibrium and the voltage produced by the second sensor and being invariable with changes in pressure. This pressure sensor allows pressure measurements with high accuracy. © KIPO & WIPO 2007 ...

SILIZIUMCARBID-HALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN EINER SILIZIUMCARBID-HALBLEITERVORRICHTUNG

Siliziumcarbid-Halbleitervorichtung mit:einem Halbleiterelement, das in einem Siliziumcarbidsubstrat (1) ausgebildet ist,einer Verdrahtungsschicht (15, 16, 18, 21), die auf dem Siliziumcarbidsubstrat (1) ausgebildet ist und an deren Unterseite ein Barrierenmetall (14) vorhanden ist, undeinem Temperaturmessungs-Widerstandselement (14, 20), das als Temperaturerfassungselement wirkt und unter Verwendung eines Teilabschnitts des Barrierenmetalls (14) in der Verdrahtungsschicht (15, 16, 18, 21) ausgebildet ist.

Infrared solid-state image sensor

A proposed infrared solid-state image sensor comprises a plurality of infrared sensor elements (100a), each of which has a p-type silicon substrate (1), a metallic electrode (3) which is connected to the silicon substrate (1) and defines a Schottky junction zone situated between them, and a p<+>-type region (11) situated in the region of the silicon substrate (1). The Schottky junction zone has a higher impurity concentration than that of the silicon substrate (1). Siting the p<+>-type region (11) having a higher impurity concentration at a region interfacing with the Schottky junction zone increases the magnitude of the electric field at the surface, thereby lowering the effective height of the Schottky barrier. As a consequence, the maximum wavelength of the light which can be detected with the infrared sensor element (100a) becomes longer. ...

Siliziumkarbidhalbleitervorrichtung und Verfahren zu ihrer Herstellung

Es wird erwartet, dass sowohl die Verringerung des Widerstandswerts eines Sourcebereichs als auch die Verringerung eines Leckstroms in einer Gateoxidschicht in einem MOSFET in einer Siliziumkarbidhalbleitervorrichtung erzielt werden kann. Ein Leckstrom, der in einer Gateoxidschicht 6 des MOSFET auftreten kann, wird unterdrückt durch Verringern einer Rauigkeit an einer Grenzfläche zwischen einem Sourcebereich 4 und der Gateoxidschicht 6. Wenn eine Dotierungskonzentration an einem Oberflächenabschnitt des Sourcebereichs 4 hoch wird, wird die Gateoxidschicht 6 durch Trockenoxidation oder einen CVD-Prozess gebildet. Wenn die Gateoxidschicht 6 durch Nassoxidation gebildet wird, wird die Dotierungskonzentration an dem Oberflächenabschnitt des Sourcebereichs 4 auf einen niedrigen Pegel gesteuert.

Method for fabricating oxide superconducting device

A method for fabricating an oxide superconducting device includes the steps of: forming a V-shaped groove on a substrate by a converging ion beam and forming a barrier with reduced superconductivity on the oxide superconducting thin-film on the groove to form a Josephson Junction, wherein the irradiation ion amount of the converging ion beam is varied according to the position of the beam within the groove in such a manner that an inclination angle of the inclined portion of the substrate is fixed. An oxide superconducting device (a Josephson Junction device) having a high degree of flexibility in arrangement and with high reproducibility, and having a high degree of uniformity is provided.

Method for manufacturing silicon carbide semiconductor device

An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C. to form ...

Semiconductor device and method of manufacturing the same

Provided is a semiconductor device including an active region provided in a first conductivity type semiconductor layer and a termination region provided around the active region. A MOS transistor through which a main current flows in a thickness direction of the semiconductor layer is formed in the active region. The termination region includes a defect detection device provided along the active region. The defect detection device includes a diode including a first main electrode provided along the active region on a first main surface of the semiconductor layer, and a second main electrode provided on a second main surface side of the semiconductor layer.

EPITAXIAL WAFER AND SEMICONDUCTOR ELEMENT

A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1). 1. An epitaxial wafer , comprising:a silicon carbide substrate of a first conductivity type, wherein the substrate is doped with a dopant at a concentration C, and has a lattice constant that decreases with doping;ii) a buffer layer of the first conductivity type located on the substrate, which is doped with the dopant; andiii) a silicon carbide epitaxially-grown layer of the first conductivity type located on the buffer layer, which is doped with the dopant at a concentration smaller than the concentration of the substrate,wherein the buffer layer has a multi-layer structure comprising two or more layers having approximately the same thickness which are laminated together, andwherein a doping concentration of a K-th layer of the buffer layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1), where wherein N represents is the number of layers in the multi-layer structure.2. The epitaxial wafer of claim 1 , wherein the dopant is nitrogen.3. The epitaxial wafer of claim 1 , wherein the buffer layer has a thickness of 100 nm or smaller.4. A semiconductor element claim 1 , comprising:i) a silicon carbide substrate of a first conductivity type, wherein the substrate is doped with ...

Pressure sensor with a thermal pressure detecting element

A pressure sensor of the present invention comprises a diaphragm 6 having a first surface which receives pressure and a thermal detecting portion 3 with a heat sensitive portion disposed as to oppose the diaphragm through a spacer, wherein displacement values of the diaphragm owing to variations in pressure are detected at the thermal detecting portion as variation values of thermal equilibrium state. With this arrangement, a surface of the diaphragm which directly receives pressure from measuring fluid does not need to undergo film forming or photolithographic processes whereby main portions of thermal pressure detecting elements might be formed onto a silicon substrate by large quantities in a lump sum through simple manufacturing processes so that it is possible to improve accuracy and reliability of the thermal pressure detecting elements and to obtain a pressure sensor of low cost.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided is a semiconductor device including an active region provided in a first conductivity type semiconductor layer and a termination region provided around the active region. A MOS transistor through which a main current flows in a thickness direction of the semiconductor layer is formed in the active region. The termination region includes a defect detection device provided along the active region. The defect detection device includes a diode including a first main electrode provided along the active region on a first main surface of the semiconductor layer, and a second main electrode provided on a second main surface side of the semiconductor layer. 1. A semiconductor device comprising:an active region provided in a first conductivity type semiconductor layer, a MOS transistor through which a main current flows in a thickness direction of said semiconductor layer being formed in the active region; anda termination region provided around said active region,wherein said termination region includes a defect detection device provided along said active region,said defect detection device includes a diode including:a first main electrode provided along said active region on a first main surface of said semiconductor layer; anda second main electrode provided on a second main surface side of said semiconductor layer.2. The semiconductor device according to claim 1 , wherein said diode is a Schottky barrier diode in which said first main electrode makes a Schottky contact with said semiconductor layer.3. The semiconductor device according to claim 1 , wherein said diode is one of a PN diode and a PiN diode including a second conductivity type impurity region selectively provided in an upper layer of said semiconductor layer so as to be in contact with said first main electrode.4. The semiconductor device according to claim 1 , wherein said diode includes:one of a PN diode region and a PiN diode region including a second conductivity type impurity region selectively ...

Semiconductor device and method for manufacturing the same

In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side of the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first well, the second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is ...

Silicon carbide semiconductor device and method for manufacturing same

In an MOSFET of this silicon carbide semiconductor device, both the resistance of a source region and the leak current in a gate oxide film are reduced. A leak current generated in a gate oxide film (6) of an MOSFET is suppressed by reducing roughness of an interface between a source region (4) and the gate oxide film (6). In the case of increasing impurity concentration in a surface portion of the source region (4), the gate oxide film (6) is formed by means of dry oxidation or a CVD method. In the case of forming the gate oxide film (6) by means of wet oxidation, impurity concentration in the surface portion of the source region (4) is suppressed to be low.

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level. 1. A silicon carbide semiconductor device comprising an MOSFET that includes:a well region formed in an upper surface portion of a silicon carbide semiconductor layer;a source region formed in an upper surface portion of said well region;a gate oxide film formed on said well region and said source region; anda gate electrode formed on said gate oxide film,{'sup': 18', '−3, 'wherein an impurity concentration at an upper surface portion of said source region is 1×10cmor less.'}2. The silicon carbide semiconductor device according to claim 1 , wherein the impurity concentration at the upper surface portion of said source region is 5×10cmor less.3. The silicon carbide semiconductor device according to claim 1 , wherein a peak of the impurity concentration in said source region is 1×10cmor more.4. The silicon carbide semiconductor device according to claim 1 , wherein said gate oxide film is formed by one or more of wet oxidation claim 1 , dry oxidation claim 1 , and CVD process.5. The silicon carbide semiconductor device according to claim 1 , wherein nitrogen is introduced into an interface between said well region and said gate oxide film.6. The silicon carbide semiconductor device according to claim 1 , wherein impurities forming said source region are nitrogen or phosphorous.7. A silicon carbide semiconductor ...

Semiconductor device and method for manufacturing the same

In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is ...

Semiconductor device

In a termination structure provided with a JTE layer, a level and a defect existing on the interface of a semiconductor layer and an insulating film or a trace of external impurities intruding up to the interface of a semiconductor through the insulating film from the inside or outside thereof becomes a source of leakage current or a yield point thus degrading breakdown voltage. Disclosed is a semiconductor device comprising an n--type semiconductor layer (2) formed on an n+-type semiconductor substrate (1), a first electrode (3) formed on the n--type semiconductor layer to function as a Schottky electrode, a GR layer (4) of a first p-type semiconductor layer formed at the end (3E) of the first electrode and the surface of the n--type semiconductor layer on the periphery thereof, a JTE layer (5) consisting of a second p-type semiconductor layer formed on the bottom (9B) and the side face (9S) of grooves (9) arranged in the shape of a ring around the GR layer while spaced apart therefrom ...

Semiconductor device and manufacturing method therefor

Semiconductor device having a groove and a junction termination extension layer surrounding a guard ring layer

In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an n type semiconductor layer formed on an n+ type semiconductor substrate; a first electrode that is formed on the n type semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the n type semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in ...

Semiconductor device and manufacturing method therefor

A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much. Because the bumps are not formed on the defective units, Schottky-barrier-side electrodes 3 are connected in parallel to the exterior of the device through the bumps 11, and a wiring layer 13 and an external lead 13a of a wiring substrate 12; thus, only the external output electrodes 4 of the non-defective units ...

Epitaxial wafer and semiconductor element

A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).

Method for manufacturing silicon carbide semiconductor device

An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.

Method of manufacturing silicon carbide semiconductor device

A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V.

SEMICONDUCTOR DEVICE

A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n-type semiconductor layer. The anode electrode forms a Schottky junction with the n-type semiconductor layer and forms an ohmic junction with the p-type contact layer. 1. A semiconductor device including a cell array in which first cells are arranged and second cells are interspersed around the arrangement of the first cells , said semiconductor device comprising:a semiconductor layer having a first conductive type, said semiconductor layer being epitaxially formed on a semiconductor substrate having the first conductive type;a buried layer made of a semiconductor having a second conductive type, said buried layer being buried within said semiconductor layer, said buried layer being provided in a peripheral portion of said first cell and provided throughout an entire region of said second cell;at least one of a first surface layer made of a semiconductor having the second conductive type and a contact layer made of a semiconductor having the second conductive type, said first surface layer being formed in a central portion of said second cell on a surface of said semiconductor layer, said contact layer being formed in a central portion of said second cell on the surface of said semiconductor layer; anda second surface layer made of a semiconductor having the second conductive type, said second surface layer being formed in a central portion of said first cell on the surface of said semiconductor layer,whereinin said second cell, said buried layer is ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode. 1. (canceled)2. A semiconductor device comprising:a semiconductor substrate having a first major surface and a second major surface facing each other;a drift layer of a first conductivity type on the first major surface;a first well of a second conductivity type in an upper portion of the drift layer disposed in a center of the semiconductor device;a diffusion layer of a first conductivity type in an upper portion of the first well;a second well of a second conductivity type in another upper portion of the drift layer disposed in a peripheral region of the semiconductor device;a first electrode above the first major surface of the semiconductor substrate that is electrically connected to the first well and the second well;a second electrode under the second major surface ...

Pressure sensor

Solid-state image sensor

The sensor uses a Charge Sweep Device as a vertical transfer device (3) and comprises a plurality of pixels (10) each of which is formed on a single photo-electro transforming element (1) and a single transfer gate (4) for transferring a signal charge from the photo-electro transforming element into the Charge Sweep Device (3). The transfer gate (4) is equal to, or larger than, the photo-electro transforming element (1) in width along the direction of charge transfer in the Charge Sweep Device (3).

Patent DE3335117C2

Thermal sensor and method for manufacturing the same

A thermal sensor in which heaters (2) arranged on the surface of a planar substrate (1) of 150μm thick or above and wiring (3) required for output signal are connected electrically with through wiring (4) formed from the surface to the rear surface of the substrate (3) and further connected electrically with an I/O wiring part (12) formed on the rear surface of the substrate. Since the I/O part which must be separated sufficiently from the detecting part on the surface of the substrate in prior art can be formed on the rear surface of the substrate and can be arranged freely with respect to the detecting part, size of the element can be reduced and the manufacturing cost can be reduced.

EPITXIAL WAFER AND SEMICONDUCTOR ELEMENT

Epitaxial-Wafer, der Folgendes aufweist:- ein Siliciumkarbid-Substrat (1) eines ersten Leitfähigkeitstyps, in das ein Dotierstoff mit einer Konzentration C dotiert ist, wobei der Dotierstoff eine Gitterkonstante aufweist, die durch Dotieren geringer wird;- eine Pufferschicht (2) des ersten Leitfähigkeitstyps, die sich auf dem Siliciumkarbid-Substrat (1) befindet und in die der Dotierstoff dotiert ist; und- eine epitaxial aufgewachsene Siliciumkarbid-Schicht (3) des ersten Leitfähigkeitstyps, die sich auf der Pufferschicht (2) befindet und in die der Dotierstoff mit einer geringeren Konzentration dotiert ist als der Konzentration des Siliciumkarbid-Substrats (1), wobei die Pufferschicht (2) derart ausgebildet ist, dass sie eine mehrlagige Struktur aufweist, die zwei oder mehr geschichtete Lagen mit etwa der gleichen identischen Dicke beinhaltet, und wobei eine Dotierungskonzentration einer K-ten Schicht ausgehend von der Seite der epitaxial aufgewachsenen Siliciumkarbid-Schicht (3) C • K / (N + 1) beträgt, wobei N die Anzahl der Lagen der mehrlagigen Struktur darstellt. An epitaxial wafer comprising:- a silicon carbide substrate (1) of a first conductivity type doped with a dopant having a concentration C, the dopant having a lattice constant which is reduced by doping;- a buffer layer (2) of the first conductivity type, which is on the silicon carbide substrate (1) and in which the dopant is doped; and- an epitaxially grown silicon carbide layer (3) of the first conductivity type, which is located on the buffer layer (2) and in which the dopant is doped at a lower concentration than the concentration of the silicon carbide substrate (1), the buffer layer ( 2) is formed to have a multi-layer structure including two or more layered layers having approximately the same identical thickness, and wherein an impurity concentration of a K-th layer from the silicon carbide epitaxial growth layer (3) side is C • K / (N + 1), where N represents the number of layers of the ...

Semiconductor device and manufacturing method therefor

A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9 , and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of μm) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9 , meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much. Because the bumps are not formed on the defective units, Schottky-barrier-side electrodes 3 are connected in parallel to the exterior of the device through the bumps 11 , and a wiring layer 13 and an external lead 13 a of a wiring substrate 12 ; thus, only the external output electrodes 4 of the non-defective units 10 are connected in parallel with each other.

Solid-state image sensor

A solid-state image sensor comprises photoelectric converting devices (22) formed on a p type semiconductor substrate (1), transfer gates (26) for reading signal charges therefrom, scanning lines (21) for selecting the transfer gates (26), and transfer electrodes (11) of the first layer and transfer electrodes (12) of the second layer alternately disposed for transferring in the vertical direction the read signal charges. All the electrodes of the transfer gates (26) are formed integrally with the transfer electrodes (12) of the second layer, with the result that all the electrodes of the transfer gates (26) are common to the transfer electrodes of the same layer (the second layer). Although the potential wall (340) is formed in the transfer channel (3) beneath the transfer electrode (12) connected to the transfer gate (26), the same is insulated from adjacent the transfer electrode (11) on the charge transfer direction side. As a result, when a voltage is applied to the transfer electrode adjacent thereto, the signal charges are fully transferred.

Siliziumcarbid-Halbleitervorrichtung

Siliziumcarbid-Halbleitervorrichtung, die Folgendes umfasst:eine Driftschicht (1b) eines ersten Leitungstyps;einen Schutzringbereich (2) eines zweiten Leitungstyps, der in einer Ringform in einem Abschnitt einer Oberfläche der Driftschicht (1b) ausgebildet ist;einen Feldisolationsfilm (3), der auf der einen Oberfläche der Driftschicht (1b) ausgebildet ist und den Schutzringbereich (2) umgibt;eine Schottky-Elektrode (4), die den Schutzringbereich (2) und die Driftschicht (1b) bedeckt, die innerhalb des Schutzringbereichs (2) freiliegt, und ein äußeres Umfangsende aufweist, das auf dem Feldisolationsfilm (3) liegt; undeine ein äußeres Umfangsende aufweisende Oberflächenelektroden-Kontaktstelle (5) auf der Schottky-Elektrode (4),wobei das äußere Umfangsende der Oberflächenelektroden-Kontaktstelle (5) mit dem Feldisolationsfilm (3) in Kontakt kommt und das äußere Umfangsende der Schottky-Elektrode (4) im äußeren Umfangsbereich der Siliziumcarbid-Halbleitervorrichtung bedeckt undwobei das äußere Umfangsende der Oberflächenelektroden-Kontaktstelle (5) und das äußere Umfangsende der Schottky-Elektrode (4) über dem Schutzringbereich (2) liegen,wobei ein Ätzrückstand (4a) als spitziger äußerster Endabschnitt der Schottky-Elektrode (4) ausgebildet ist, undwobei die Oberflächenelektroden-Kontaktstelle (5) den Ätzrückstand (4a) bedeckt.

Verfahren zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung

Verfahren zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung, wobei das Verfahren einen Metallfilm-Ausbildungsschritt des Ausbildens eines Metallfilms durch die folgenden Schritte aufweist: Erzeugen einer an ein Paar von Elektroden (21, 22), das eine Anode (22) und eine Kathode (21) aufweist, die einander gegenüberliegend angeordnet sind, anzulegenden Hochfrequenzspannung in einer Kammer (25) mit Absaugung durch eine Vakuumpumpe (26), um dadurch die Erzeugung eines Plasmas eines Sputtergases zwischen dem Paar von Elektroden (21, 22) zu bewirken; Zerstäuben eines auf der Kathode (21) platzierten Metallmaterials mit Ionen in dem erzeugten Plasma und Bewirken einer Abscheidung des zerstäubten Metallmaterials auf einem Siliziumkarbidwafer (10), der auf der Anode (22) so angeordnet ist, dass er dem Metallmaterial gegenüberliegt,wobei in dem Metallfilm-Ausbildungsschritt der Metallfilm unter der Randbedingung ausgebildet wird, dass eine Auftreffenergie beim Auftreffen des Metallmaterials und des Sputtergases auf den Siliziumkarbidwafer (10) niedriger ist als eine Bindungsenergie des Siliziumkarbids,wobei in dem Metallfilm-Ausbildungsschritt der Metallfilm ausgebildet wird, während das Sputtergas von einem Edelgas mit einer kleinen Masse zu einem Edelgas mit einer großen Masse umgewechselt wird.

método relacional para apoio à decisão com fluxo de aprendizagem

método relacional para apoio à decisão com fluxo de aprendizagem refere-se a presente invenção a um método para apoio à decisão, baseado no fornecimento de subsídios para a tomada de decisões informadas, com uma visão integrada, mediante o provimento de um método para ambiente decisório sistêmico, também designada como metodologia ads. compreender as etapas de elaboração e aplicação de mapa sistêmico; preparação; avaliação da qualidade da informação; modelagem do ambiente analítico; regras de negócios; referência; experimentação; análise de risco e ciclo de aprendizagem.