10-06-2021 дата публикации
Номер: US20210173989A1
Автор:
Kaipeng LIN,
Yanrong LI,
Yucheng WANG,
LIN KAIPENG,
LI YANRONG,
WANG YUCHENG,
LIN, Kaipeng,
LI, Yanrong,
WANG, Yucheng
Принадлежит:
The present invention discloses a simulation signal viewing method and system for a digital product. Firstly, a controller controls a FPGA to perform a first simulation verification by reading and recording status data of all external ports of the digital product in real time, and reading and recording all internal status data of the digital product once at each interval. After the simulation is completed, if data of a certain clock cycle of the digital product needs to be viewed in a backtracking manner, the controller reads the internal status data of the digital product stored at a last time point before the certain clock cycle and the status data of the external ports at the last time point, and, using the read data as initial operating status data for a second simulation verification, starts the FPGA to operate to one clock cycle before the certain clock cycle. 1. A simulation system for a digital product , comprising:a field programmable gate array (FPGA), configured to load the digital product and perform a plurality of simulation verifications, wherein the simulation verifications comprise, in a sequential order, a first simulation verification and a second simulation verification;a controller, configured to control the FPGA to perform the simulation verifications; anda storage device, configured to store simulated data read and recorded by the controller, read external port status data of all external ports of the digital product in real time, and meanwhile read all internal status data of the digital product once at each interval; and', 'after the first simulation verification is completed, in response to determining that data of a certain clock cycle of the digital product needs to be viewed in a backtracking manner, read the internal status data of the digital product stored at a last time point before said certain clock cycle and the external port status data of the external ports at said last time point from the recorded simulated data;, 'wherein the ...
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