III-nitride epitaxial structure

An epitaxial structure includes a substrate, a buffer layer, a channel layer, an intermediate layer, and a barrier layer. The buffer layer is disposed on the substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, and the intermediate layer is disposed between the channel layer and the barrier layer. The chemical composition of the barrier layer is Alx1Iny1Gaz1N, and the chemical composition of the intermediate layer is Alx2Iny2Gaz2N. The lattice constant of the barrier layer is greater than the lattice constant of the intermediate layer. The aluminum (Al) content of at least a portion of the intermediate layer is greater than the Al content of the barrier layer.

Epitaxy substrate and method of manufacturing the same

An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (Å) and 500 angstroms.

III-NITRIDE EPITAXIAL STRUCTURE

An epitaxial structure includes a substrate, a buffer layer, a channel layer, an intermediate layer, and a barrier layer. The buffer layer is disposed on the substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, and the intermediate layer is disposed between the channel layer and the barrier layer. The chemical composition of the barrier layer is AlInGaN, and the chemical composition of the intermediate layer is AlInGaN. The lattice constant of the barrier layer is greater than the lattice constant of the intermediate layer. The aluminum (Al) content of at least a portion of the intermediate layer is greater than the Al content of the barrier layer. 1. An epitaxial structure , comprising:a substrate;a buffer layer disposed on the substrate;a channel layer disposed on the buffer layer;{'sub': x1', 'y1', 'z1, 'a barrier layer disposed on the channel layer, wherein a chemical composition of the barrier layer is AlInGaN, and x1+y1+z1=1, 0≤x1≤0.3, and 0.3≤y1≤0.7; and'}{'sub': x2', 'y2', 'z2, 'an intermediate layer disposed between the channel layer and the barrier layer, wherein a chemical composition of the intermediate layer is AlInGaN, and x2+y2+z2=1, 0.5≤x2≤1, and 0≤y2≤0.5, wherein an aluminum content of at least a portion of the intermediate layer is greater than an aluminum content of the barrier layer, and a lattice constant of the barrier layer is greater than a lattice constant of the intermediate layer.'}2. The epitaxial structure of claim 1 , wherein the aluminum content of the barrier layer is a fixed value claim 1 , and the aluminum content of the barrier layer is 10% to 30%.3. The epitaxial structure of claim 2 , wherein the aluminum content of the intermediate layer is a fixed value claim 2 , and the aluminum content of the intermediate layer is greater than 30%.4. The epitaxial structure of claim 2 , wherein the aluminum content of the intermediate layer is linearly reduced along a growth ...

Wafer carrier

A wafer carrier for processing a plurality of wafers includes a carrier body which rotatable about a central axis, and a plurality of pockets formed in the carrier body. Each of the pockets has an access opening and an inner periphery surface extending from the access opening to terminate at a floor surface. A lower periphery region of the inner periphery surface has a most distal region which is most distal from the central axis. When the carrier body is rotated about the central axis, a corresponding one of the wafers is less likely to be damaged due to a centrifugal force applied to the corresponding one of the wafers.

EPITAXIAL STRUCTURE AND SEMICONDUCTOR DEVICE

An epitaxial structure and a semiconductor device are provided in which the epitaxial structure includes at least a SiC substrate, a nucleation layer, and a GaN layer. The nucleation layer is formed on the SiC substrate. The material of the nucleation layer is aluminum gallium nitride doped with a dopant, the Al content in the nucleation layer changes from high to low in the thickness direction, the lattice constant of the nucleation layer is between 3.08 Å and 3.21 Å, and the doping concentration of the nucleation layer changes from high to low in the thickness direction. The GaN layer is formed on the nucleation layer.

EPITAXIAL STRUCTURE

An epitaxial structure including at least a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a P-type aluminum indium gallium nitride layer is provided. The nucleation layer is formed on the substrate; the buffer layer is formed on the nucleation layer; the channel layer is formed on the buffer layer; the barrier layer is formed on the channel layer; and the P-type aluminum indium gallium nitride layer is formed on the barrier layer. The material of the P-type aluminum indium gallium nitride layer is AlInGaN with a P-type dopant, in which the contents of Al, In and Ga all change stepped-periodically or stepped-periodical-gradually in the thickness direction, and the doping concentration of the P-type dopant changes stepped-periodically or stepped-periodical-gradually in the thickness direction.

SEMICONDUCTOR EPITAXY STRUCTURE

A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

Epitaxial structure

An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al(1-x)InxN, where 0≤x≤1. A maximum value of the x value in the plurality of regions is the same, a minimum value of the x value in the plurality of regions is the same, and an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm. A thickness of the nucleation layer is less than a thickness of the buffer layer. A roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.

EPITAXY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (Å) and 500 angstroms.

MELT GAP MEASURING APPARATUS, CRYSTAL GROWTH APPARATUS AND MELT GAP MEASURING METHOD

A melt gap measuring apparatus is adapted to measure the gap between the bottom of the heat insulating cover and the surface of the raw material melt inside a crucible. The melt gap measuring apparatus includes a first light-guiding probe having a first upper side and a first bottom side which are opposite to each other. The first upper side is exposed to an inner wall of the heat insulating cover, and the first bottom side protrudes from the bottom side of the heat insulating cover. An image capturing device is disposed above the heat insulating cover to capture the image of the first upper side. Moreover, a crystal growth apparatus and a method of measuring the melt gap are also provided.

Wafer rotating apparatus

A wafer rotating apparatus includes a base, a carrying device, a first shaft gear, a power unit, a roller, a second shaft gear and a driving assembly. The base has an accommodating space which the carrying device is disposed in to accommodate the wafer. The first shaft gear is disposed on a side surface of the base. The power unit is assembled to a top of the base and connected to the first shaft gear. The roller is located under the carrying device and supports an edge of the wafer. The second shaft gear is disposed on the side surface of the base and connected to the roller. The driving assembly is connected between the first shaft gear and the second shaft gear. The power unit provides a power through the first gear, the driving unit and the second shaft gear to drive the roller to rotate the wafer.

CRUCIBLE STRUCTURE AND METHOD FOR FORMING ISOLATING LAYER OF CRUCIBLE

A method for forming an isolating layer of a crucible includes placing a round crucible sideways with a bottom surface of an inside thereof perpendicular to a horizontal plane, and then performing a plurality of spraying processes to form the isolating layer on the bottom surface and a wall surface of the round crucible. Each spraying process includes spraying a slurry on the bottom surface; using an optical positioner to set a spraying range the same as one of a plurality of partial areas divided from the wall surface; aligning one of the plurality of partial areas with the spraying range; fixing the round crucible and spraying the slurry in the spraying range; stopping the spraying; and rotating the round crucible to move another partial area to the spraying range. Then, the steps are repeated until the spraying of all the partial areas is completed.

EPITAXIAL STRUCTURE

An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al (1-x) In x N, where 0≤x≤1. A maximum value of the x value in the plurality of regions is the same, a minimum value of the x value in the plurality of regions is the same, and an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm. A thickness of the nucleation layer is less than a thickness of the buffer layer. A roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.

Nanostructured chip and method of producing the same

A nanostructured chip includes a substrate and a nanostructured layer, wherein the substrate has a first surface and a second surface on which the nanostructured layer is formed. A method of producing the nanostructured chip includes the step of forming the nanostructured layer on the second surface of the substrate. Whereby, the nanostructured layer effectively disperses a stress to increase the flexural strength of the nanostructured chip. Therefore, during the subsequent procedures to form an epitaxial layer on the first surface, the nanostructured layer is helpful to prevent the epitaxial layer from generating cracks, and prevent the substrate from bowings, or fragments.

EPITAXIAL STRUCTURE

An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al(1−X)InXN, where 0≤x≤1. A maximum value of the x value in the regions decreases along the thickness direction, and the x value in the chemical composition of each two regions consists of a fixed region and a gradient region, wherein a gradient slope of the gradient regions is −0.1%/nm to −50%/nm, and a stepwise slope of the fixed regions is −0.1%/loop to −50%/loop. A thickness of the nucleation layer is less than that of the buffer layer. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.

BONDING WAFER STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm 2 to 20,000 ea/cm 2 , a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

Epitaxial structure

An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer. The nucleation layer is disposed on the substrate, and the nucleation layer consists of a plurality of regions in a thickness direction, wherein a chemical composition of the region is Al(1−x)InxN, where 0≤x≤1. The buffer layer is disposed on the nucleation layer, and a thickness of the nucleation layer is less than a thickness of the buffer layer. The nitride layer is disposed on the buffer layer, wherein a roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.

EPITAXIAL STRUCTURE

An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer. The nucleation layer is disposed on the substrate, and the nucleation layer consists of a plurality of regions in a thickness direction, wherein a chemical composition of the region is AlInN, where 0≤x≤1. The buffer layer is disposed on the nucleation layer, and a thickness of the nucleation layer is less than a thickness of the buffer layer. The nitride layer is disposed on the buffer layer, wherein a roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer. 1. An epitaxial structure comprising:a substrate;{'sub': (1−x)', 'x, 'a nucleation layer disposed on the substrate, wherein the nucleation layer consists of a plurality of regions in a thickness direction, and a chemical composition of the plurality of regions is AlInN, where 0≤x≤1;'}a buffer layer disposed on the nucleation layer, wherein a thickness of the nucleation layer is less than a thickness of the buffer layer; anda nitride layer disposed on the buffer layer, wherein a roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.2. The epitaxial structure according to claim 1 , wherein a maximum value of the x value in the plurality of regions is the same claim 1 , a minimum value of the x value in the plurality of regions is the same claim 1 , and an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm.3. The epitaxial structure according to claim 1 , wherein a maximum value of the x value in the plurality of regions decreases along the thickness direction claim 1 , a minimum value of the x value in the plurality of regions is the same claim 1 , an absolute value of a gradient slope of each of the regions is 0.1%/nm to 50%/nm claim 1 , and a ...

MANUFACTURING METHOD OF HIGH ELECTRON MOBILITY TRANSISTOR

A manufacturing method of a high electron mobility transistor includes providing an epitaxial stacked structure, wherein the epitaxial stacked structure includes a semiconductor substrate, a buffer layer formed on the semiconductor substrate, a channel layer formed on the buffer layer, an intermediate layer formed on the channel layer, and a barrier layer formed on the intermediate layer; forming a source and a drain on the barrier layer; performing a microwave annealing process, wherein the conditions of the microwave annealing process include a temperature between 450° C. and 550° C., a frequency between 5.8 GHz and 6.2 GHz, and a time between 150 seconds and 250 seconds; and forming a gate on the barrier layer between the source and the drain. 1. A manufacturing method of a high electron mobility transistor , comprising:providing an epitaxial stacked structure, wherein the epitaxial stacked structure comprises a semiconductor substrate, a buffer layer formed on the semiconductor substrate, a channel layer formed on the buffer layer, an intermediate layer formed on the channel layer, and a barrier layer formed on the intermediate layer;forming a source and a drain on the barrier layer;performing a microwave annealing process, wherein conditions for the microwave annealing process comprise: a temperature between 450° C. and 550° C., a frequency between 5.8 GHz and 6.2 GHz, and a time between 150 seconds and 250 seconds; andforming a gate on the barrier layer between the source and the drain.2. The manufacturing method of claim 1 , wherein a power of the microwave annealing process is between 2.7 kW and 2.9 kW.3. The manufacturing method of claim 1 , wherein an atmosphere of the microwave annealing process is nitrogen (N).4. The manufacturing method of claim 1 , wherein a root mean square roughness (RMS) of the source and the drain is between 4.56 nm and 6.79 nm.5. The manufacturing method of claim 1 , wherein when a voltage applied to the drain is 10 V claim 1 , a ...

SEMICONDUCTOR EPITAXIAL STRUCTURE AND METHOD OF FORMING THE SAME

Provided is a semiconductor epitaxial structure including a nucleation layer disposed on a substrate; a buffer layer disposed on the nucleation layer; a semiconductor layer disposed on the buffer layer; a barrier layer disposed on the semiconductor layer; and a cap layer disposed on the barrier layer. In a case where a bowing of the semiconductor epitaxial structure is less than or equal to +/−30 μm, a maximum value or a minimum value of a ratio of a thickness of the buffer layer to a thickness of the semiconductor layer is represented as following formula: Y=aX1−bX2+cX3, X1≥0 nm, X2≥750 nm, X3≥515 nm, wherein X1 is a thickness of the nucleation layer, X2 is the thickness of the buffer layer, X3 is the thickness of the semiconductor layer, a, b and c are constants respectively, and Y is a ratio of X3 to X2. 1. A semiconductor epitaxial structure , comprising:a substrate;a nucleation layer disposed on a substrate;a buffer layer disposed on the nucleation layer;a semiconductor layer disposed on the buffer layer;a barrier layer disposed on the semiconductor layer; and {'br': None, 'i': Y=aX', 'bX', 'cX', 'X', 'X', 'X, '1−2+3, 1≥0 nm, 2≥750 nm, 3≥515 nm,'}, 'a cap layer disposed on the barrier layer, wherein in a case where a bowing of the semiconductor epitaxial structure is less than or equal to +/−30 μm, a maximum value or a minimum value of a ratio of a thickness of the semiconductor layer to a thickness of the buffer layer is represented as a formula ofwherein X1 is a thickness of the nucleation layer, X2 is the thickness of the buffer layer, X3 is the thickness of the semiconductor layer, a, b and c are constants respectively, and Y is the ratio of the thickness of the semiconductor layer to the thickness of the buffer layer (X3/X2) and falls between the maximum value or the minimum value.2. The semiconductor epitaxial structure according to claim 1 , wherein the maximum value of the ratio of the thickness of the semiconductor layer to the thickness of the buffer ...

Epitaxy substrate and method of manufacturing the same

An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a device substrate and a handle substrate. The device substrate has a first surface and a second surface opposite to each other, and a bevel disposed between the first and the second surfaces. The handle substrate is bonded to the second surface of the device substrate, wherein the oxygen content of the device substrate is less than the oxygen content of the handle substrate, and a bonding angle greater than 90° is between the bevel of the device substrate and the handle substrate.

Epitaxial structure

An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al(1−x)InxN, where 0≤x≤1. A maximum value of the x value in the regions decreases along the thickness direction, and the x value in the chemical composition of each two regions consists of a fixed region and a gradient region, wherein a gradient slope of the gradient regions is −0.1%/nm to −50%/nm, and a stepwise slope of the fixed regions is −0.1%/loop to −50%/loop. A thickness of the nucleation layer is less than that of the buffer layer. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a transistor and a heat dissipation structure. The substrate includes first and second semiconductor layers, and includes an insulating layer disposed between the first and second semiconductor layers. The substrate has a recess extending into the insulating layer from a surface of the first semiconductor layer. The transistor includes a hetero-junction structure, a gate electrode, a drain electrode and a source electrode. The hetero-junction structure is disposed on the second semiconductor layer. The gate, drain and source electrodes are disposed over the hetero-junction structure. The gate electrode is located between the drain electrode and the source electrode, and an active area of the hetero-junction structure located between the drain electrode and the source electrode is overlapped with the recess of the substrate. The heat dissipation structure is disposed on ...

EPITAXIAL STRUCTURE

An epitaxial structure includes a substrate, a buffer layer, a back diffusion barrier layer, a channel layer formed on the back diffusion barrier layer, and a barrier layer formed on the channel layer. The buffer layer is formed on the substrate. The back diffusion barrier layer is formed on the buffer layer. The chemical composition of the back diffusion barrier layer is AlInGaN, wherein 0≤x≤1 and 0≤y≤1. The lattice constant of the back diffusion barrier layer is between 2.9 Å and 3.5 Å. The back diffusion barrier layer is composed of a plurality of regions in the thickness direction, and the aluminum (Al) content and the indium (In) content of the back diffusion barrier layer are changed stepwise or gradually changed stepwise along the thickness direction. The back diffusion barrier layer further includes carbon, and the carbon concentration is changed stepwise or gradually changed stepwise along the thickness direction. 1. An epitaxial structure , comprising:a substrate;a buffer layer formed on the substrate;{'sub': x', 'y', '1-x-y, 'a back diffusion barrier layer formed on the buffer layer, wherein a chemical composition of the back diffusion barrier layer is AlInGaN, and 0≤x≤1 and 0≤y≤1, a lattice constant of the back diffusion barrier layer is between 2.9 Å and 3.5 Å, the back diffusion barrier layer is composed of a plurality of regions in a thickness direction, an aluminum (Al) content and an indium (In) content of the back diffusion barrier layer are changed stepwise or gradually changed stepwise along the thickness direction, the back diffusion barrier layer further comprises a carbon, and a carbon concentration is changed stepwise or gradually changed stepwise along the thickness direction;'}a channel layer formed on the back diffusion barrier layer; anda barrier layer formed on the channel layer.2. The epitaxial structure of claim 1 , wherein in the back diffusion barrier layer claim 1 , the aluminum content is increased stepwise along the thickness ...

Epitaxial structure having super-lattice laminates

An epitaxial structure includes a substrate, a lower super-lattice laminate, a middle super-lattice laminate, an upper super-lattice laminate and a channel layer. The lower super-lattice laminate includes a plurality of first lower film layers and a plurality of second lower film layers stacked alternately. The first lower film layer includes aluminum nitride. The second lower film layer includes aluminum gallium nitride. The middle super-lattice laminate includes a plurality of first middle film layers and a plurality of second middle film layers stacked alternately. The first middle film layer includes aluminum nitride. The second middle film layer includes gallium nitride doped with a doping material. The upper super-lattice laminate includes a plurality of first upper film layers and a plurality of second upper film layers stacked alternately. The first upper film layer includes gallium nitride doped with the doping material. The second upper film layer includes gallium nitride.

WAFER ROTATING APPARATUS

A wafer rotating apparatus includes a base, a carrying device, a first shaft gear, a power unit, a roller, a second shaft gear and a driving assembly. The base has an accommodating space which the carrying device is disposed in to accommodate the wafer. The first shaft gear is disposed on a side surface of the base. The power unit is assembled to a top of the base and connected to the first shaft gear. The roller is located under the carrying device and supports an edge of the wafer. The second shaft gear is disposed on the side surface of the base and connected to the roller. The driving assembly is connected between the first shaft gear and the second shaft gear. The power unit provides a power through the first gear, the driving unit and the second shaft gear to drive the roller to rotate the wafer. 1. A wafer rotating apparatus , applied in a wafer processing equipment , the wafer rotating apparatus comprising:a base, having an accommodating space;a carrying device, disposed in the accommodating space and used to accommodate a wafer;a first shaft gear, disposed on a side surface of the base;a power unit, assembled to a top of the base, wherein the first shaft gear is connected to the power unit;a roller, located under the carrying device and supporting an edge of the wafer;a second shaft gear, disposed on the side surface and connected to the roller; anda driving assembly, connected between the first shaft gear and the second shaft gear, wherein when the power unit provides a power to enable the first shaft gear and the driving assembly to rotate, the second shaft gear rotates to drive the roller to rotate, so as to rotate the wafer.2. The wafer rotating apparatus according to claim 1 , wherein the roller has a wrapping layer wrapping around the roller to increase friction between the roller and the edge of the wafer.3. The wafer rotating apparatus according to claim 2 , wherein a material of the wrapping layer is rubber.4. The wafer rotating apparatus according ...

Crucible structure and method for forming isolating layer of crucible

A method for forming an isolating layer of a crucible includes placing a round crucible sideways with a bottom surface of an inside thereof perpendicular to a horizontal plane, and then performing a plurality of spraying processes to form the isolating layer on the bottom surface and a wall surface of the round crucible. Each spraying process includes spraying a slurry on the bottom surface; using an optical positioner to set a spraying range the same as one of a plurality of partial areas divided from the wall surface; aligning one of the plurality of partial areas with the spraying range; fixing the round crucible and spraying the slurry in the spraying range; stopping the spraying; and rotating the round crucible to move another partial area to the spraying range. Then, the steps are repeated until the spraying of all the partial areas is completed.

METHOD OF MANUFACTURING EPITAXY SUBSTRATE

A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 μm and less than 200 μm. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 μm and 800 μm.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a transistor and a heat dissipation structure. The substrate includes first and second semiconductor layers, and includes an insulating layer disposed between the first and second semiconductor layers. The substrate has a recess extending into the insulating layer from a surface of the first semiconductor layer. The transistor includes a hetero-junction structure, a gate electrode, a drain electrode and a source electrode. The hetero-junction structure is disposed on the second semiconductor layer. The gate, drain and source electrodes are disposed over the hetero-junction structure. The gate electrode is located between the drain electrode and the source electrode, and an active area of the hetero-junction structure located between the drain electrode and the source electrode is overlapped with the recess of the substrate. The heat dissipation structure is disposed on the surface of the first semiconductor layer, and extends into the recess.

SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF

A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate has an epitaxy region located at a central portion of a main plane of the semiconductor substrate, a periphery region surrounding the epitaxy region and an injured region distributed inside the periphery region.

Semiconductor substrate and manufacturing method thereof

A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate has an epitaxy region located at a central portion of a main plane of the semiconductor substrate, a periphery region surrounding the epitaxy region and an injured region distributed inside the periphery region.

Epitaxial structure and semiconductor device

An epitaxial structure and a semiconductor device are provided in which the epitaxial structure includes at least a SiC substrate, a nucleation layer, and a GaN layer. The nucleation layer is formed on the SiC substrate. The material of the nucleation layer is aluminum gallium nitride doped with a dopant, the Al content in the nucleation layer changes from high to low in the thickness direction, the lattice constant of the nucleation layer is between 3.08 Å and 3.21 Å, and the doping concentration of the nucleation layer changes from high to low in the thickness direction. The GaN layer is formed on the nucleation layer.

EPITAXIAL STRUCTURE

An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer orderly. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al(1−x)InxN, where 0≤x≤1. The x value consists of four sections of variation along the thickness direction, in which a first fixed region has a maximum value, a first gradient region gradually changes from the maximum value to a minimum value, a second fixed region has the minimum value, and a second gradient region gradually changes from the minimum value to the maximum value. An absolute value of a gradient slope of the first and second gradient regions is 0.1%/nm to 50%/nm. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.

EPITAXY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a device substrate and a handle substrate. The device substrate has a first surface and a second surface opposite to each other, and a bevel disposed between the first and the second surfaces. The handle substrate is bonded to the second surface of the device substrate, wherein the oxygen content of the device substrate is less than the oxygen content of the handle substrate, and a bonding angle greater than 90° is between the bevel of the device substrate and the handle substrate. 1. An epitaxy substrate , comprising:a device substrate, having a first surface and a second surface opposite to each other, and a bevel disposed between the first surface and the second surface; anda handle substrate, bonded to the second surface of the device substrate, wherein an oxygen content of the device substrate is less than an oxygen content of the handle substrate, and a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate.2. The epitaxy substrate of claim 1 , wherein a resistivity of the device substrate is greater than a resistivity of the handle substrate.3. The epitaxy substrate of claim 1 , wherein a resistivity of the device substrate is greater than 100 ohm-cm.4. The epitaxy substrate of claim 1 , wherein a thickness of the device substrate is between 100 μm and 200 μm.5. The epitaxy substrate of claim 1 , wherein an error value of crystal orientation of the device substrate is less than ±0.05 degree.6. The epitaxy substrate of claim 1 , wherein the bonding angle is 100° to 170°.7. The epitaxy substrate of claim 1 , wherein a projection length of the bevel toward the handle substrate is between 600 μm and 800 μm.8. The epitaxy substrate of claim 1 , wherein the oxygen content of the device substrate is less than 5 ppma.9. The epitaxy substrate of claim 1 , further comprising a bonding layer disposed between the ...

Epitaxial structure

An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer orderly. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al(1−x)InxN, where 0≤x≤1. The x value consists of four sections of variation along the thickness direction, in which a first fixed region has a maximum value, a first gradient region gradually changes from the maximum value to a minimum value, a second fixed region has the minimum value, and a second gradient region gradually changes from the minimum value to the maximum value. An absolute value of a gradient slope of the first and second gradient regions is 0.1%/nm to 50%/nm. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.

Method of manufacturing epitaxy substrate

A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 μm and less than 200 μm. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 μm and 800 μm.

Bonding wafer structure and method of manufacturing the same

A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm2to 20,000 ea/cm2, a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

Epitaxial structure

An epitaxial structure includes a substrate, a buffer layer, a back diffusion barrier layer, a channel layer formed on the back diffusion barrier layer, and a barrier layer formed on the channel layer. The buffer layer is formed on the substrate. The back diffusion barrier layer is formed on the buffer layer. The chemical composition of the back diffusion barrier layer is AlxInyGa1-x-yN, wherein 0≤x≤1 and 0≤y≤1. The lattice constant of the back diffusion barrier layer is between 2.9 Å and 3.5 Å. The back diffusion barrier layer is composed of a plurality of regions in the thickness direction, and the aluminum (Al) content and the indium (In) content of the back diffusion barrier layer are changed stepwise or gradually changed stepwise along the thickness direction. The back diffusion barrier layer further includes carbon, and the carbon concentration is changed stepwise or gradually changed stepwise along the thickness direction.

WAFER CARRIER

A wafer carrier for processing a plurality of wafers includes a carrier body which rotatable about a central axis, and a plurality of pockets formed in the carrier body. Each of the pockets has an access opening and an inner periphery surface extending from the access opening to terminate at a floor surface. A lower periphery region of the inner periphery surface has a most distal region which is most distal from the central axis. When the carrier body is rotated about the central axis, a corresponding one of the wafers is less likely to be damaged due to a centrifugal force applied to the corresponding one of the wafers. 1. A wafer carrier for processing a plurality of wafers each having a top bevel edge and an orientation flat , said wafer carrier comprising:a carrier body which is rotatable about a central axis, and which has an upper surface and a lower surface opposite to said upper surface in a direction of the central axis; and an uppermost region which extends from said access opening to terminate at a circumferential juncture area,', 'a circumferential inclined ceiling region which extends downwardly from said circumferential juncture area and radially and outwardly from the pocket axis to terminate at a joint region, and which is configured to confront the top bevel edge of the corresponding one of the wafers, and', 'a lower periphery region extending upwardly from a marginal edge of said floor surface to terminate at an upper edge which is leveled with said joint region, said lower periphery region having a most distal zone which is most distal from the central axis, and which is configured such that only said most distal zone is permitted to be engaged with the corresponding one of the wafers when said carrier body is rotated about the central axis., 'a plurality of pockets which are angularly displaced from each other about the central axis, each of said pockets defining a pocket axis, and having an access opening formed in said upper surface, and an ...

N-type polysilicon crystal, manufacturing method thereof, and N-type polysilicon wafer

An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (Ω·cm), the slope of resistivity is 0 to −1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.

N-TYPE POLYSILICON CRYSTAL, MANUFACTURING METHOD THEREOF, AND N-TYPE POLYSILICON WAFER

An N-type polysilicon crystal, a manufacturing method thereof, and an N-type polysilicon wafer are provided. The N-type polysilicon crystal has a slope of resistivity and a slope of defect area percentage. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to resistivity presented by a unit of Ohm·cm (Ω·cm), the slope of resistivity is 0 to −1.8 at the solidified fraction of 0.25 to 0.8. When the horizontal axis is referred to solidified fraction and the vertical axis is referred to defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8. 1. An N-type polysilicon crystal , wherein:the N-type polysilicon crystal has a slope of resistivity, and when a horizontal axis is referred to a solidified fraction and a vertical axis is referred to the resistivity presented by a unit of Ohm·cm (Ω·cm), the slope of resistivity is 0 to −1.8 at the solidified fraction of 0.25 to 0.8; andthe N-type polysilicon crystal has a slope of defect area percentage, and when the horizontal axis is referred to the solidified fraction and the vertical axis is referred to the defect area percentage (%), the slope of defect area percentage is less than 2.5 at the solidified fraction of 0.4 to 0.8.2. The N-type polysilicon crystal of claim 1 , wherein an average value of a minority carrier lifetime of the N-type polysilicon crystal measured via a μ-PCD method is greater than 20 μs.3. The N-type polysilicon crystal of claim 1 , wherein the N-type polysilicon crystal is doped with gallium and phosphorous claim 1 , a doping amount of the gallium is 0.3 ppma to 3 ppma claim 1 , a doping amount of the phosphorous is 0.02 ppma to 0.2 ppma claim 1 , and an atomic ratio of the gallium with respect to the phosphorous is between 10 and 20.4. The N-type polysilicon crystal of claim 1 , wherein the N-type polysilicon crystal comprises an ingot claim 1 , a brick claim 1 , or a wafer.5. The N-type ...

Method of manufacturing substrate for epitaxy

A method of manufacturing a substrate for epitaxy is disclosed, including the following steps. Dispose a buffer layer on a base, wherein the buffer layer is constituted by stacked nitride layers formed by the process of atomic layer deposition. The buffer layer could alternatively be constituted by stacked at least one first buffer sub-layer and at least one second buffer sub-layer, wherein the first and second buffer sub-layers are respectively constituted by layered first nitride layers and layered second nitride layers, which are both formed by the process of atomic layer deposition. While forming the buffer layer, perform ion bombardment each time a single layer of the nitride layer, the first nitride layer, or the second nitride layer is formed. Whereby, the base and the buffer layer constitute the substrate for epitaxy, which effectively enhances the crystallinity of the buffer layer.

EPITAXIAL STRUCTURE HAVING SUPER-LATTICE LAMINATES

An epitaxial structure includes a substrate, a lower super-lattice laminate, a middle super-lattice laminate, an upper super-lattice laminate and a channel layer. The lower super-lattice laminate includes a plurality of first lower film layers and a plurality of second lower film layers stacked alternately. The first lower film layer includes aluminum nitride. The second lower film layer includes aluminum gallium nitride. The middle super-lattice laminate includes a plurality of first middle film layers and a plurality of second middle film layers stacked alternately. The first middle film layer includes aluminum nitride. The second middle film layer includes gallium nitride doped with a doping material. The upper super-lattice laminate includes a plurality of first upper film layers and a plurality of second upper film layers stacked alternately. The first upper film layer includes gallium nitride doped with the doping material. The second upper film layer includes gallium nitride. 1. An epitaxial structure having super-lattice laminates , comprising:a substrate;a lower super-lattice laminate disposed on the substrate; wherein the lower super-lattice laminate includes: a plurality of first lower film layers and a plurality of second lower film layers stacked alternately with each other, each of the first lower film layers includes aluminum nitride (AlN), and each of the second lower film layers includes aluminum gallium nitride (AlGaN);a middle super-lattice laminate disposed on the lower super-lattice laminate; wherein the middle super-lattice laminate includes: a plurality of first middle film layers and a plurality of second middle film layers stacked alternately with each other, each of the first middle film layers includes aluminum nitride (AlN), and each of the second middle film layers includes gallium nitride doped with a doping material (doped-GaN);an upper super-lattice laminate disposed on the middle super-lattice laminate; wherein the upper super- ...

NANOSTRUCTURED CHIP AND METHOD OF PRODUCING THE SAME

A nanostructured chip includes a substrate and a nanostructured layer, wherein the substrate has a first surface and a second surface on which the nanostructured layer is formed. A method of producing the nanostructured chip includes the step of forming the nanostructured layer on the second surface of the substrate. Whereby, the nanostructured layer effectively disperses a stress to increase the flexural strength of the nanostructured chip. Therefore, during the subsequent procedures to form an epitaxial layer on the first surface, the nanostructured layer is helpful to prevent the epitaxial layer from generating cracks, and prevent the substrate from bowings, or fragments. 1. A nanostructured chip , which is adapted to have an epitaxial layer formed thereon , comprising:a substrate having a first surface and a second surface opposite to the first surface, wherein the nanostructured chip is adapted to have the epitaxial layer formed on the first surface; anda nanostructured layer formed on the second surface.2. The nanostructured chip of claim 1 , wherein the nanostructured layer comprises a plurality of nanopillars; the length of each of the plurality of nanopillars is between 10 and 10000 nm.3. The nanostructured chip of claim 2 , wherein the length of each of the plurality of nanopillars is not less than 4000 nm.4. The nanostructured chip of claim 1 , wherein the nanostructured layer comprises a plurality of nanopillars; the width of each of the plurality of nanopillars is between 10 and 10000 nm.5. The nanostructured chip of claim 4 , wherein the width of each of the plurality of nanopillars is less than 500 nm.6. The nanostructured chip of claim 1 , wherein the nanostructured layer comprises a plurality of nanopillars; axes of the plurality of nanopillars are in parallel.7. The nanostructured chip of claim 1 , wherein the nanostructured layer comprises a plurality of nanopillars which cover more than 50% of a total area of the second surface.8. The ...

LINK PAD STRUCTURE AND METHOD OF MANUFACTURING THEREOF

Une structure de plaquette de liaison (100) inclut un substrat de support (102), une couche de liaison (104), et une couche de carbure de silicium (SiC) (106). La couche de liaison (104) est formée sur une surface du substrat de support (102), et la couche de SiC (106) est liée à la couche de liaison (104), dans laquelle une surface carbone (106a) de la couche de SiC (106) est en contact direct avec la couche de liaison (104). La couche de SiC (106) présente une dislocation de plan basal (BPD) de 1000 ea/cm2 à 20 000 ea/cm2, une variation de l’épaisseur totale (TTV) supérieure à celle du substrat de support (102), et un diamètre inférieur ou égal à celui du substrat de support (102). La structure de plaquette de liaison (100) présente une TTV inférieure à 10 µm, un arc inférieur à 30 µm et un gauchissement inférieur à 60 µm. Figure de l’abrégé : Figure 1

Wafer transfer apparatus and wafer transfer method thereof

一種晶圓轉換裝置，可供一第一承載架及一第二承載架放置，該第一承載架形成有複數個上下相間隔排列的第一容置槽，各該第一容置槽用以容置一晶圓，該第二承載架形成有複數個上下相間隔排列的第二容置槽，該等第一容置槽的數量與該等第二容置槽的數量不同，該晶圓轉換裝置包含一基座、一第一定位架、一第二定位架、一高度調整機構，及一頂推機構。該第一承載架及該第二承載架分別放置於該第一、第二定位架，該高度調整機構可帶動該第一承載架在一第一高度位置及一第二高度位置間轉換，再藉由該頂推機構將第一承載架中的晶圓推送至該第二承載架中。

Silicon carbide substrate for epitaxy and semiconductor wafer

一種磊晶用碳化矽基板及半導體晶片，其中碳化矽基板具有一表面及自該表面凸起形成的多數個圖案化結構，該表面的晶面為(0001)面；該些圖案化結構的寬度係由下往上逐漸減小且形成傾斜的至少一側面，側面的晶面為(-1,0,1,2)面。碳化矽基板的頂部設置有一氮化鎵磊晶層以構成該半導體晶片。藉此，氮化鎵磊晶層的底部形成側向延伸的差排缺陷，不易形成往上延伸的穿透差排缺陷，讓氮化鎵磊晶層具有良好的磊晶品質。

Wafer conversion device

一種晶圓轉換裝置，適用於供一第一晶圓載具及一第二晶圓載具放置。該第一晶圓載具包含多個第一容置槽，每一第一容置槽適用於容置一晶圓。該第二晶圓載具包含多個第二容置槽，每一第二容置槽適用於容置一晶圓。該晶圓轉換裝置包含一基座、一導引單元及一頂推機構。該導引單元包括一具有多個垂直間隔排列的第一導引槽的第一導引架。該頂推機構可受控以頂推與該等第二容置槽對齊的該等第一容置槽中的該等晶圓，使該等晶圓由該等第一容置槽通過該導引單元的該第一導引架經由該等第一導引槽最終移動至該等第二容置槽內。

Structure de plaquette de liaison et son procédé de fabrication

Une structure de plaquette de liaison (100) inclut un substrat de support (102), une couche de liaison (104), et une couche de carbure de silicium (SiC) (106). La couche de liaison (104) est formée sur une surface du substrat de support (102), et la couche de SiC (106) est liée à la couche de liaison (104), dans laquelle une surface carbone (106a) de la couche de SiC (106) est en contact direct avec la couche de liaison (104). La couche de SiC (106) présente une dislocation de plan basal (BPD) de 1000 ea/cm2 à 20 000 ea/cm2, une variation de l’épaisseur totale (TTV) supérieure à celle du substrat de support (102), et un diamètre inférieur ou égal à celui du substrat de support (102). La structure de plaquette de liaison (100) présente une TTV inférieure à 10 µm, un arc inférieur à 30 µm et un gauchissement inférieur à 60 µm. Figure de l’abrégé : Figure 1

承載裝置

拆卸裝置

Semiconductor structure

A semiconductor structure, including a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer, is provided. The first nitride layer is located on the substrate. The polarity inversion layer is located on a surface of the first nitride layer to convert a non-metallic polarity surface of the first nitride layer into a metallic polarity surface of the polarity inversion layer. The second nitride layer is located on the polarity inversion layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer include iron element.

Wafer grinding parameter optimization method and electronic device

A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.

半導体構造

【課題】本発明は、寄生チャネルの発生を抑制することができる半導体構造を提供する【解決手段】基板と、第１の窒化物層と、極性反転層と、第２の窒化物層と、第３の窒化物層と、を含む半導体構造が提供される。前記第１の窒化物層は、前記基板上に配置される。極性反転層は、第１の窒化物層の表面上に配置され、第１の窒化物層の非金属極性表面を極性反転層の金属極性表面に変換する。第２の窒化物層は、極性反転層上に配置される。第３の窒化物層は、第２の窒化物層上に配置される。基板、第１の窒化物層、極性反転層、および第２の窒化物層は、鉄元素を含む。【選択図】図１

換油裝置

ウェーハ回転装置

【課題】ウェーハの歩留まりを改善するためのウェーハ回転装置を提供する。 【解決手段】ウェーハ回転装置１００は、ベース１１０、キャリア装置１２０、第一のシャフトギア１３０、電源ユニット、ローラー、第二のシャフトギア１６０、駆動アセンブリ１７０を備える。ベースは、ウェーハ１２２を収容するためのキャリア装置が配置される収容空間を有する。第一のシャフトギアはベースの側面に配置される。電源ユニットは、ベースの上部に組み立てられ、第一のシャフトギアに接続される。ローラーは、キャリア装置の下方に位置し、ウェーハの端部を支持する。第二のシャフトギアは、ベースの側面に配置され、ローラーに接続される。駆動アセンブリは、第一のシャフトギアと第二のシャフトギアとの間に接続される。電源ユニットは、第一のシャフトギア、駆動アセンブリおよび第二のシャフトギアを経て電力を供給し、ローラーを駆動してウェーハを回転させる。 【選択図】図１

Epitaxial structure

An epitaxial structure includes a substrate, a buffer layer, a channel layer, a barrier layer, a diffusion barrier layer, and a P-type gallium nitride layer sequentially stacked from bottom to top. The P-type gallium nitride layer has a first lattice constant. The diffusion barrier layer includes a chemical composition of Inx1Aly1Gaz1N, where x1+y1+z1=1, 0≤x1≤0.3, 0≤y1≤1.0, and 0≤z1≤1.0. The chemical composition of the diffusion barrier layer has a proportional relationship so that the diffusion barrier layer has a second lattice constant that matches the first lattice constant, and the second lattice constant is between 80% and 120% of the first lattice constant.

Semiconductor epitaxy structure

A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiN x ) layers and a plurality of aluminum gallium nitride (Al x Ga 1-x N) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

マイクロナノ化チップおよびその製造方法

【課題】応力をきちんと分散し、曲げ強さを高め、後続のエピタキシ作業においてひび割れ、基板の曲がりまたは破片が生じるのを防げるようになるマイクロナノ化チップを提供する。 【解決手段】 発明の提供するマイクロナノ化チップは、一つの基板と一つのナノ構造層から構成される一つのエピタキシ層を配置するために用いられる。このうち、基板は互いに向かい合う一つの第１面と一つの第２面とを備え、第１面はエピタキシ層が配置される面で、ナノ構造層は第２面上に形成されている。本発明の提供するマイクロナノ化チップの製造方法では、Ａ．互いに向かい合う一つの第１面と一つの第２面とを備える一枚の基板を提供する。Ｂ．第２面に一つのナノ構造層を配置してマイクロナノ化チップを形成する二つのプロセスがあり、これにより基板の第１面にエピタキシ層が配置される。 【選択図】図１

Silicon carbide seed crystal

A silicon carbide seed crystal includes a first silicon carbide substrate, a second silicon carbide substrate, a metal layer, and a first adhesion layer. The first silicon carbide substrate has a carbon surface and a silicon surface opposite to each other; the second silicon carbide substrate has a carbon surface and a silicon surface opposite to each other, in which the carbon surface of the second silicon carbide substrate is a surface utilized for crystal growth. The metal layer is disposed between the silicon surface of the second silicon carbide substrate and the silicon surface of the first silicon carbide substrate, and the first adhesion layer is disposed between the silicon surface of the first silicon carbide substrate and the metal layer, in which a material of the first adhesion layer has a property of easily forming silicide with silicon.

Silicon carbide substrate and manufacturing method thereof

A silicon carbide substrate includes an N-type silicon carbide substrate having a first surface and a second surface opposite to the first surface. The N-type silicon carbide substrate includes a semi-insulating silicon carbide region and an N-type silicon carbide region. The semi-insulating silicon carbide region extends inward from the first surface into the N-type silicon carbide substrate to a depth. The semi-insulating silicon carbide region includes nitrogen and a first dopant. The first dopant includes at least one of group VB elements, group VIIA elements, argon and silicon. The N-type silicon carbide region is adjacent to the semi-insulating silicon carbide region and includes nitrogen element.

晶圓承載裝置

一種晶圓承載裝置，供多個晶圓置放，該晶圓承載裝置包含一盤體，表面凹陷形成多個容置槽，每一容置槽供一晶圓置放且由一側槽壁及一底槽壁配合界定而成，該側槽壁包括一供該晶圓靠抵的凸部，及一連接該凸部上方且不接觸該晶圓的凹部，該凸部與該凹部之交界位於該晶圓遠離該底槽壁之一面的下方，本發明藉由凸部以及凹部使得容置槽內的晶圓在該盤體旋轉時受壓均勻分佈，避免因受離心力擠壓而導致邊緣或表面產生缺陷、損傷，使得晶圓品質下降。