SEMICONDUCTOR PROCESS

First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C. 1. A semiconductor process , comprising:providing a substrate with at least one recess;forming an embedded semoconductive epitaxial layer comprising an epitaxial SiGe material which fills up said recess in said substrate;performing a pre-amorphization implant (PAI) procedure on said embedded semoconductive epitaxial layer to form an amorphous region;performing a source/drain implanting procedure on said embedded semoconductive epitaxial layer to form a source doping region and a drain doping region; andperforming a source/drain annealing procedure to form a source and a drain in said substrate, wherein at least one of said pre-amorphization implant procedure and said source/drain implanting procedure is performed in a cryogenic procedure below −30° C.2. The semiconductor process of claim 1 , wherein said embedded semoconductive epitaxial layer comprises a plurality of said epitaxial SiGe materials of different concentrations.3. The semiconductor process of claim 1 , performing said pre-amorphization implant (PAI) procedure before performing said source/drain implanting procedure.4. The semiconductor process of claim 2 , wherein said pre-amorphization implant (PAI) procedure is performed to reach different depths in the embedded semoconductive ...

METHOD FOR FABRICATING EMBEDDED STATIC RANDOM ACCESS MEMORY

The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.

LAYOUT CONFIGURATION FOR MEMORY CELL ARRAY

A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated. 1. A layout configuration for a memory cell array comprising:at least a comb-like doped region having a first conductivity type; anda fishbone-shaped doped region having a second conductivity type, the second conductivity type and the first conductivity type being complementary; wherein the comb-like doped region and the fishbone-shaped doped region are interdigitated.2. The layout configuration for a memory cell array according to claim 1 , wherein the comb-like doped region comprises a plurality of tooth portions and a base portion.3. The layout configuration for a memory cell array according to claim 2 , further comprising a plurality of first diffusion regions formed in the base portion of the comb-like doped region.4. The layout configuration for a memory cell array according to claim 3 , wherein the first diffusion regions comprise the second conductivity.5. The layout configuration for a memory cell array according to claim 2 , wherein the fishbone-shaped doped region comprises a plurality of branch-like portions and a stem-like portion.6. The layout configuration for a memory cell array according to claim 5 , wherein the base portion of the comb-like doped region and the stem-like portion of the fishbone-shaped doped region are parallel with each other.7. The layout configuration for a memory cell array according to claim 5 , wherein the tooth portions of the comb-like doped region and the branch-like portions of the fishbone-shaped doped region are alternately arranged.8. The layout configuration for a memory cell array according to claim 5 , further comprising a plurality of second diffusion ...

Probe Calibration Device and Calibration Method

A calibration device applied for a test apparatus with at least a first probe and a second probe, the calibration device comprising: a first testing region and a second testing region, the first testing region and the second testing region divides into n×n sensing units respectively, the first testing region for generating n×n average electricity corresponding to a contact degree of the first probe contacted with the calibration device, and the second testing region for generating another n×n average electricity corresponding to a contact degree of the second probe contacted with the calibration device, and the pitch is the distance between the center of the first testing region to the center of the second testing region that is the same as that of the center of the first probe to the center of the second probe.

Semiconductor chip and manufacturing method thereof

A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

LAYOUT CONFIGURATION FOR MEMORY CELL ARRAY

A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated. 1. A layout configuration for a memory cell array comprising:at least a comb-like doped region having a first conductivity type; anda fishbone-shaped doped region having a second conductivity type, the second conductivity type and the first conductivity type being complementary; wherein the comb-like doped region and the fishbone-shaped doped region are interdigitated.2. The layout configuration for a memory cell array according to claim 1 , wherein the comb-like doped region comprises a plurality of tooth portions and a base portion.3. The layout configuration for a memory cell array according to claim 2 , further comprising a plurality of first diffusion regions formed in the base portion of the comb-like doped region.4. The layout configuration for a memory cell array according to claim 3 , wherein the first diffusion regions comprise the second conductivity.5. The layout configuration for a memory cell array according to claim 2 , wherein the fishbone-shaped doped region comprises a plurality of branch-like portions and a stem-like portion.6. The layout configuration for a memory cell array according to claim 5 , wherein the base portion of the comb-like doped region and the stem-like portion of the fishbone-shaped doped region are parallel with each other.7. The layout configuration for a memory cell array according to claim 5 , wherein the tooth portions of the comb-like doped region and the branch-like portions of the fishbone-shaped doped region are alternately arranged.8. The layout configuration for a memory cell array according to claim 5 , further comprising a plurality of second diffusion ...

Inverter structure and method for fabricating the same

An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.

INVERTER STRUCTURE AND METHOD FOR FABRICATING THE SAME

An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.

Method for fabricating embedded static random access memory

The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.

Semiconductor process

First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below 30° C.

Layout configuration for memory cell array

A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

Manufacturing method of semiconductor chip

A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

Semiconductor chip and manufacturing method thereof

A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

Manufacturing method of semiconductor chip

A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

Calibration method and probe calibration device

一種校正裝置，應用於至少具有第一探針與第二探針之測試裝置，該校正裝置包含：第一測試區域及第二測試區域，第一測試區域及第二測試區域係分別具有nxn個感測單元，其係因應第一探針及第二探針之接觸程度而產生對應於第一測試區域之nxn個平均電性值及對應於第二測試區域之另一nxn個平均電性值，第一測試區域的中心到第二測試區域中心之間的距離等於第一探針的中心到第二探針的中心之間的距離。

Inverter structure and method for fabricating the same

Semiconductor chip

A semiconductor chip includes a substrate and a transistor. The transistor is formed on the substrate and includes an insulation layer and a fin. The fin includes a base portion and a protrusion connected with the base portion, wherein the protrusion is projected with respect to an upper surface of the base portion and has a recess recessed with respect to the upper surface.

半導體製程

一種半導體製程，首先提供包含凹穴之基材。其次，在基材中形成嵌入矽鍺層。此嵌入矽鍺層包含填滿凹穴之矽鍺磊晶材料。然後，對於嵌入矽鍺層進行一預非晶化摻雜步驟，而形成一非晶化區域。繼續，對於嵌入矽鍺層進行源極/汲極摻雜步驟，而形成源極摻雜區與汲極摻雜區。再來，進行一源極/汲極退火步驟，而在基材中形成源極與汲極。此預非晶化摻雜步驟與源極/汲極摻雜步驟其中之至少一者，係在低於零下30度之低溫下進行。

Method for fabricating embedded static random access memory

Semiconductor chip and manufacturing method thereof

Method for fabricating embedded static random access memory