КАМЕРА ДЛЯ ЭЛЕКТРОКЛИМАТИЧЕСКИХ ИСПЫТАНИЙ

Сущность изобретения: устройство содержит программный блок, задающий блок климатических характеристик, климатический регулятор, формирователь характеристик электропитания, блок обратной связи, клеммы для подключения объекта испытаний, блок синхронизации, блок контроля работоспособности, коммутатор с соответствующими связями. 2 ил.

Устройство допускового контроля

Устройство для прогнозирования надежности

Способ контроля интегральных микросхем памяти

Изобретение относится к контрольно- измерительной технике. Может использоваться для контроля микросхем (МКС) но- лупроводниковой памяти или других МКС, содержащих триггерные ячейки. Цель изобретения - расширение функциональных возможностей способа - достигается путем обеспечения возможности прогнозирования работоспособности МКС в диапазоне температур и отбраковки потенциально негодных МКС и повышения достоверности за счет исключения пропуска МКС, потенциально негодных в диапазоне температур. Способ предусматривает кратковременное отключение напряжения питания на время tc.n - время снятия питания, что позволяет выявить потенциально негодные МКС полупроводниковой памяти, к числу которых относятся МКС, ячейки памяти которых успевают переключиться за время tc.n. Величину с.п определяют по математической формуле, приведенной в описании изобретения. Способ предусматривает также запись проверочных кодов в ячейках памяти, их считывание и сравнение полученных кодов с эталонными . i л 1C ...

Устройство для измерения запаса надежности электронных дискретных схем

Устройство для испытания наНАдЕжНОСТь дВуХОбМОТОчНыХ элЕКТРО-МАгНиТНыХ РЕлЕ

Способ оценки надежности радиоэлектронных устройств

Изобретение относится к области контроля изделий электронной техники и может быть использовано при прогнозировании надежности. Цель изобретения - повышение точности оценки надежности радиоэлектронных устройств. Для проведения контроля используют сравнение параметров устройства - эталона и контролируемого устройства. Начальные запасы устойчивости определяются для устройства эталона и контролируемого устройства при плавном изменении воздействующих факторов. После этого вырабатывают некоторую, например сотую, долю ресурса контролируемых устройств и определяют средние скорости изменения запасов устойчивости. Контроль радиоэлектронных устройств как по запасу устойчивости, так и по скорости его изменения при использовании предложенного способа обеспечивает более высокую точность.

Устройство для контроля и селекции изделий по надежности

... 1. УСТРОЙСТВО ДЛЯ КОНТРОЛЯ И СЕЛЕКЦИИ. ИЗДЕЛИЙ ПО НАДЕЖНОСТИ, содержащее блок ввода, соединенный входом с входной клеммой устройства, выходом - с первым входом первого классификатора, соединенного первым выходом с первым входом первого накопителя , о тличающееся тём что, с целью повышения достоверности контроля и надежности его, в устройство введены второй классификатор, второй накопитель, блок вьтода и программный блок, соединенный входами с соответствующими первыми входами второго классификатора, второго накопителя и блока вывода и с вторыми входами блока ввода первого классификатора и первого накопителя, второй выход первого классификатора соединен с вторым входом второго классификатора, третий вход которого соединен с первым выходом первого накопителя, соединенного вторым выходом с первым входом блока вывода , соединенного выходом с выходной клеммой устройства, вторым входом с выходом второго накопителя, соединенного вторым входом с выходом второго классификатора.

Устройство для прогнозирования постепенных отказов электронных приборов

Auf-dem-Chip-Oszillator und Testverfahren dafür

Schaltungsanordnung zum UEberwachen von Fernmeldeeinrichtungen

Verfahren und System zur Schätzung des Leistungsverbrauchs von digitalen Schaltungen und zugehöriges Rechnerprogrammprodukt

Verfahren zum Berechnen einer Verzögerungszeit und Einrichtung zum Durchführen des Verfahrens

Verfahren zur beschleunigtenPrüfung von Halbleitervorrichtungen

Faulty block detector for semiconductor device testing

The system for detecting in failing function block consists of a number of logic blocks (B1, B2...) and a table to store the correspondence between a number of functional test patterns (FTP (ADD)) and the logic blocks. A device is provided to generate test patterns and transfer them to the semiconductor device. The system also includes a detector (8) for abnormal current (Iqqd) flowing in the semiconductor device, and a circuit (9) to determine the failure block according to the correspondence table.

Semiconductor device simulating apparatus, simulates and outputs current value based on input test signal and various parameters

A setting unit sets various parameters to measure voltage or current value which changes due to internal resistance of semiconductor device. An input unit inputs the test signal to examined semiconductor device. Based on test signal and parameter, a simulating unit simulates and outputs current value. An Independent claim is also included for program debug apparatus for semiconductor testing.

Quiescent current frequency and magnitude analysis for CMOS IC fault indication

Quick detection of CMOS integrated circuit troubles with a simple system is realized. A tester repeatedly applies a test pattern to a CMOS integrated circuit under test, and a power supply unit supplies current through a current detection unit to the CMOS integrated circuit. The current detection unit outputs a detection signal, which is coupled through an amplifier to a power spectrum analyzing unit to derive its power spectrum. When the CMOS integrated circuit has a trouble, a quiescent supply current which is set apart from the transistor switching current is caused in specific sub-patterns in the test pattern for every (NT+T0) seconds. A checking unit detects the power of the detection signal in the neighborhood of 1/(NT+T0) ?Hz! and thus checks for a quiescent current, i.e., checks for a trouble in the CMOS integrated circuit under test.

Apparatus and method for determining effect of on-chip noise on signal propagation

Analysis module, integrated circuit, system and method for testing an integrated circuit

A system (5) for testing and failure analysis of an integrated circuit (10) is provided using failure analysis tools (40, 50, 60). An analysis module (30) having a number of submodule test structures is incorporated into the integrated circuit design. The test structures are chosen in dependence upon the failure analysis tools: such as a laser voltage probe 40, time resolved emission microscope 50 and infrared emission microscope 60, to be used. The rest of the integrated circuit contains function modules (20) arranged to provide normal operating functions. By analysing the submodule test structures of the analysis module (30) using the failure analysis tools(40, 50, 60), physical parameters of the integrated circuit (10) are obtained and used in subsequent testing of the function modules (20) by the failure analysis tools(40, 50, 60), thus simplifying the testing of the integrated circuit (10) and reducing the time taken to perform a failure analysis procedure.

Test chip circuit for on-chip timing characterization

The inventive system and method determines path delay of at least one test path (101, 102) of logic gates (204). The invention uses a toggle register (104) to generate a toggling signal, that is sent out onto the path by a launch register (105). A capture register (106) receives the signal from the other end of the path. A logic gate (109) compares the received signal from a prior launched signal with an inverted launched signal (116). Since the signal is a toggling signal the prior received signal should be the same as an inverted launched signal. A latch register (107) determines whether the logic gate has detected a match between inverted launched signal and the received signal from a prior launch signal within a predetermined time clock period. As the clock period is shortened (112), the launched signal will fail to traverse the path and be captured by the capture register (107) within the clock period. This will cause a mis-match in the logic gate. The clock period at the point of ...

TESTING OF SEMICONDUCTOR INTEGRATED CIRCUITS

... 1425190 Measuring semi-conductor parameters INTERNATIONAL BUSINESS MACHINES CORP 10 Dec 1973 [29 Dec 1972] 57139/73 Heading G1U In an integrated circuit 12 individual elements 10 are temporarily inter-connected into a test circuit 18, the voltage supplies to the elements are provided and the propagation delay of a signal through the circuit is measured. In the device shown the elements 10 are inverting gates (e.g. NAND or NOR) and an odd number are connected in a loop which oscillates when the power supply is provided. The oscillation half-period is the sum of the individual delays in the gates 10 forming the loop. If the total delay is satisfactory, the temporary inter-connections are broken and the gates connected into the final circuit configuration. The inter-connections may be metal or may be made via photo-sensitive inputs which are sensitized during the test but kept in the dark when the final circuit is formed and used.

Scan testable double edge triggered scan cell

Integrated circuit testing

PROCEDURE AND SYSTEM FOR DEBUGGING USING DUPLICATED LOGIC

HIGHLY SENSITIVE MAGNETIC INSERTING CURRENT SENSOR

PROCEDURE AND SWITCHING CONFIGURATION FOR THE SELF CHECK OF A REFERENCE TENSION IN ELECTRONIC COMPONENTS

SEMICONDUCTOR COMPONENT WITH TEST-STRUCTURE AND TEST PROCEDURE FOR A SEMICONDUCTOR COMPONENT

PROCEDURE AND CIRCUIT FOR THE PROTECTION OF TEST CONTACTS DURING THE HIGH CURRENT MEASUREMENT OF SEMICONDUCTOR COMPONENTS

PARAMETRIC SCAN REGISTER, DIGITAL CIRCUIT AND PROCEDURE FOR EXAMINING A DIGITAL CIRCUIT USING SUCH A REGISTER

PROCEDURE AND SYSTEM FOR DEBUG AND TEST USING MADE A REPLICATION LOGIC

Prüfgerät und Verfahren zum Prüfen einer Steuereinheit einer Schaltvorrichtung einer Schaltanlage

Um eine verbesserte Funktionsprüfung einer Steuereinheit (6) der Schaltvorrichtung (5) einer elektrischen Schaltanlage (4) zu ermöglichen, wird ein Prüfgerät (10) angegeben, das einen Signaleingang (9) und eine gesteuerte Stromsenke (20) aufweist, wobei die Stromsenke (20), mit dem Signaleingang (9) verbunden ist und vom Signaleingang (9) einen Eingangsstrom (iq) abzweigt, um eine dynamisch einstellbare Eingangsimpedanz (Z) zu realisieren. Die gesteuerte Stromsenke (20) kann mittels eines gesteuerten Regelkreises realisiert werden, in dem eine gesteuerte Spannungsquelle (Uq) und ein Shunt (R1) vorhanden sind, wobei die Höhe des Eingangsstroms (20) der gesteuerten Stromsenke (20) vom einem über den Shunt (R1) fließenden Strom (i1) eingestellt wird, wobei der Strom (i1) von der gesteuerten Spannungsquelle (Uq) eingestellt wird. Es wird zudem ein Verfahren zum Prüfen der Steuereinheit (6) beschrieben, wobei das Prüfgerät (10) einen Signaleingang (9) aufweist, an dem eine Eingangsspannung ( ...

PROCEDURE FOR THE CHARACTERISATION OF THE SENSITIVITY OF AN ELECTRONIC COMPONENT CONCERNING ENERGETIC RECIPROCAL EFFECTS

METHOD FOR THE EXECUTION OF THERMAL SHOCK TESTS IN THE ELECTRONICS AREA.

ENTRANCE BUFFER AND VOLTAGE LEVEL DETECTION PROCEDURE

PROCEDURE AND MECHANISM FOR THE QUIESCENT CURRENT REGULATION

DYNAMIC REGISTER WITH THE ABILITY FOR THE EXAMINATION OF THE QUIESCENT CURRENT ADMISSION (IDDQ)

TEST CHAMBER WITH CHANGEABLE VOLUME

A method and apparatus for iddq measuring

Compositions and methods for helper-free production of recombinant adeno-associated viruses

Method and system for wafer and device-level testing of an integrated circuit

A METHOD FOR TESTING THE OPERATIONAL EFFICIENCY OF A COMPONENT OF AN ELECTRONIC CIRCUIT

VDDQ INTEGRATED CIRCUIT TESTING SYSTEM AND METHOD

A method and system for Vddq Integrated (IC) testing are described herein. The method includes the positioning of a resistive element between a voltage source and the power supply terminal of the IC under test and the approximation of the voltage value at the power supply terminal when the IC is generally at steady state. Depending on the approximated voltage value, the IC may be determined faulty or not.

ELECTRICALLY CONDUCTIVE KELVIN CONTACTS FOR MICROCIRCUIT TESTER

Terminals of a device under test are connected to corresponding contact pads or leads by a series of electrically conductive contacts. Each terminal testing connects with both a "force" contact and a "sense" contact. In one embodiment, the sense contact partially or completely laterally surrounds the force contact, so that it need not have its own resiliency. The sense contact has a forked end with prongs that extend to opposite sides of the force contact. Alternatively, the sense contact surrounds the force contact and slides laterally to match a lateral translation component of a lateral cross-section of the force contact during longitudinal compression of the force contact. Alternatively, the sense contact includes rods that have ends on opposite sides of the force contact, and extend parallel.

CHECKING FOR UNDESIRABLE MULTIPLICITY OF MATRIX PATHS

SELF-TEST METHOD AND APPARATUS

DIAGNOSTING RELIABILITY OF VIAS BY E-BEAM PROBING

Electronic devices, such as IC devices, are tested by determining a failure net within the electronic device that is causing a device failure. After identifying the failure net, the failure net is locally stressed. The stress is applied so that only the net being tested is subjected to the stress, and the remaining nets and components of the device are not stressed. A change in a signal produced by the failure net is observed while the failure bet is being subjected to the stress. The testing in this manner assists in identifying the failure net as a failure source of the device.

APPARATUS AND METHOD FOR INLINE TESTING OF ELECTRICAL COMPONENTS

An apparatus (10) for inline testing of a product (15) includes an environmental chamber (20), a conveyor (40), a stimulation means (60), and a monitoring means (80). The environmental chamber (20) provides thermal shock to the product (15) and includes a hot zone (22) and a cold zone (24). The conveyor (40) transports the product (15) through the hot (22) and cold zones (24) of the environmental chamber (20). The stimulation means (60) provides continuous electric stimulation to the product (15) during transport of the product (15) through the environmental chamber (20). The monitoring means (80) continuously monitors the effect of the stimulation means (60) on the product (15) during transport of the product (15) through the environmental chamber (20).

DELAY TESTING OF HIGH-PERFORMANCE DIGITAL COMPONENTS BY A SLOW-SPEED TESTER

High speed testing of a digital circuit may be performed although the rated frequency of the circuit exceeds the frequency capability of the test equipment. A digital circuit may be designed such that a controllable delay may be introduced in the timing paths of the circuit during testing using test stimuli which are applied at a clock rate that is less than the rated frequency of the circuit. By adding delay to the combinational signal path, testing of the circuit for operation at the maximum operating frequency is achieved during testing at a clock rate which is within the capability of the test equipment. The controllable delay may be incorporated as a delay element into a single-clock circuit and controlled by manipulation of the duty-cycle of a clock waveform which is applied to the circuit. The delay circuit is so designed that its function is also testable. In a multiclock circuit, the delay is added to the circuit by skewing one clock signal with respect to the other clock signals ...

SMART BATTERY

A battery and circuitry for monitoring state of charge of the battery are housed in a single housing. A display may be provided for displaying an indication of the state of charge, and a communication circuit may be provided for communicating electrical signals representing the state of charge to the exterior of the housing. Preferably, the battery module additionally includes a switch device for connecting the battery to terminals external to the housing arid control circuitry responsive to the monitoring circuitry for causing the battery to be connected to and disconnected from the terminals. The control circuitry operates in accordance with thresholds to prevent deep discharge and overcharge.

VARIABLE VOLUME TEST CHAMBER

A variable volume test apparatus (10) utilizes an adjustable ceiling (18) to vary the volume of the chamber (20). The ceiling (18) is sealed in its new position through the use of an inflatable bladder (26). Adjustable vents (58) are positioned in the ceiling (18) and walls (24) to direct fluid flow into the chamber (20). Floating joints (84) within the chamber doors (16) allow the doors' inner walls (80) to contract or expand relative to the outer walls (84) without creating a corresponding stress on the outer walls (84) or the rivets (86). As a safety feature, the door locks (150) are computer controlled so that the doors (16) cannot be unlocked from the outside until the test chamber (20) reaches an operator safe condition. One door (16), however, has an override button (250) that allows the operator to open the door (16) from the inside of the test chamber (20). A retractable, vibration table (100) with shock absorbers (138, 140) and a hand brake (128) is also provided.

AUTOMATIC SAFETY TEST EQUIPMENT FOR PRINTED CIRCUIT BOARD

When one performs an interpart short-circuit test where short-circuit is made between the terminals of the parts mounted on the printed circuit board 1 to find out the existence of fuming, firing and red heating, a spacing test that verifies if the distance between the patterns of the printed circuit board meets the prescribed insulating clearance, and an interpattern short-circuit test that verifies the existence of fuming and firing by shorting between the patterns that do not satisfy the prescribed insulating distance, an automatic tester receives the printed circuit board 1 to carry on the safety test, a control unit outputs the signal that controls said automatic tester and inputs the data of the test results, a detecting means detects the respective test results of fuming, firing and red heating, the memory incorporated into the control unit stores the data, and a recording means records the test results.

METHOD FOR TESTING ELECTRONIC COMPONENTS

The invention features a device (1) comprising processing means (13) capable of controlling test equipment (2) to carry out repeatedly some at least of its steps, each time reducing the duration of at least one of them until satisfying a final criterion taking into account the distribution of the electric variables measured by the said equipment for each reduced duration value, and to set a new duration value at most equal to its initial value, for which the measured electric variable distribution satisfies one selected dispersion condition. It further comprises a function generator (14), capable of providing a function applicable to at least one of the terms of a comparison executed during one of the said steps, so that the said function operates on a measurement executed after the new duration.

Uberwachungsschaltung für ein oder mehrere impulsgesteuerte Glieder

Prüfschaltung für Stromimpulse mit Selbstkontrolle

VERFAHREN ZUM PRUEFEN VON SYSTEMEINHEITEN EINES MODULAR AUFGEBAUTEN PROGRAMMGESTEUERTEN VERARBEITUNGSSYSTEMS.

Voltage limit test system and auxiliary test jig

The invention discloses a voltage limit test system which is used for being connected with an internal memory on a main board so as to test the limit voltage of the internal memory, wherein the voltage limit test system comprises a voltage limit test jig and a first auxiliary test jig, wherein the voltage limit test jig comprises a first button; the first auxiliary test jig comprises a first timer, a first relay and a second relay; the first relay is used for receiving the state signal of the main board, and controls whether a voltage is provided for the first timer according to the state signal; the second relay is used for receiving a pulse signal output by the first timer so as to trigger the first button to regulate the power supply of the internal memory according to a reference time at intervals; and when the operating main board stops operating, the voltage of the internal memory is the first limit voltage value of the internal memory voltage. According to the invention, the automatic ...

Tester

The invention discloses a tester which comprises a discrete device detecting module, an integrated circuit detecting module and a control module. The output end of the control module is connected with the driving input ends of the discrete device detecting module and the integrated circuit detecting module, and according to the model number of a current detecting device, the discrete device detecting module or the integrated circuit detecting module is driven to carry out detecting. Accordingly, the problem that multi-type electronic devices are not convenient to detect is solved. Detecting on two types of devices is achieved, corresponding detecting programs are set according to different types of integrated circuits, and accordingly detecting of various integrated circuits is achieved. Accordingly, the reliability and the consistency of electronic device detecting are improved, detecting cost of the electronic devices is lowered, and the production efficiency and the reliably of electronic ...

Method of testing and electronic circuit compositing flipelop with master and slave

Universal input data sampling circuit and method thereof

Heater power control circuit and burn-in apparatus using the same

DEVICE OF MEASUREMENT OF Leakage current Of an INTEGRATED CIRCUIT

Appareil de mesure du courant de fuite des broches d'entree d'un dispositif sous test

Un appareil de mesure de courants de fuite de broches d'entree d'un dispositif electronique sous test 20, comprend un ensemble de circuits de mesure de courant 24 connectes aux broches d'entree et fournissant des signaux de sortie analogiques correspondants; un multiplexeur 26 qui selectionne sequentiellement l'un des signaux de sortie analogiques; et un convertisseur analogique-numerique 48 qui fournit un signal de sortie numerique representant le courant de fuite. On utilise une memoire de correction 32, 34 pour corriger le signal de sortie du multiplexeur en fonction des facteurs de gain et de decalage de chaque circuit de mesure de courant.

Device for monitoring the phase difference between two clock signals.

Validation circuit for verifying the models used in logic simulations

L'invention concerne un circuit destiné à mesurer le temps de propagation d'un front de signal entre une entrée (A) et une sortie (Z) d'une cellule logique. Il comprend plusieurs cellules logiques de même type connectées en anneau, une même entrée à tester de chaque cellule étant reliée à la sortie d'un multiplexeur respectif (12) ayant une entrée de sélection reliée à la sortie de la cellule précédente, et deux entrées de donnée mises à des états fixes différents.

DATA GENERATOR

Device and method for testing semiconductor integrated circuit

CIRCUIT ARRANGEMENT AND METHOD FOR TESTING A RESET CIRCUIT

Load circuit for integrated circuit tester

웨이퍼에 임베디드된 공정 모니터링 회로

... 본 발명은 공정 모니터링 기술에 있어서, 특히 챔버 내부 및 챔버에 로딩된 웨이퍼를 실시간으로 모니터링을 위해 웨이퍼에 임베디드된 공정 모니터링 회로에 관한 것으로, 웨이퍼의 정해진 센싱 위치에 내장되는 다수 개의 센서와, 상기 다수 개의 센서에서 센싱된 센싱 값을 상기 웨이퍼의 각 위치 별 센싱 값으로 교정하는 마이크로제어유닛과, 상기 마이크로제어유닛으로부터 주기적으로 전달되는 상기 각 위치 별 센싱 값을 무선으로 송신하는 무선데이터통신회로를 포함하되, 상기 마이크로제어유닛은 상기 다수 개의 센서와 전기적으로 연결되게 상기 웨이퍼에 내장되고, 상기 무선데이터통신회로는 상기 마이크로제어유닛과 전기적으로 연결되게 상기 웨이퍼에 내장되는 것이 특징인 발명이다.

LOGICAL DEVICE TESTER AND METHOD THEREOF

PURPOSE: A logical device tester and a method thereof are provided to test a badness of a logical device generated by a noise by applying a noise by intension with a source voltage or an input voltage. CONSTITUTION: A logical device tester includes a source supplying part or an input voltage supplying part(10), a noise supplying part(12), and a signal mixing part(14). The source supplying part or an input voltage supplying part(10) generates a source voltage or an input voltage, and outputs the source voltage or the input voltage to the signal mixing part(12). The noise supplying part(12) generates a virtual noise mixed by the signal mixing part(14). At this time, the noise supplying part(12) is a clock generating part generating a clock signal as a noise, having a variable amplitude and a variable frequency, or is an analog signal generator. The signal mixing part(14) mixes the source signal and the input signal and the virtual noise, and outputs a mixed signal to a source voltage input ...

Adaptive voltage scaling in a receiver

SEMICONDUCTOR DEVICE AND MOUNTING METHOD THEREOF

PURPOSE: To provide a semiconductor chip semiconductor device and a mounting method thereof capable of easily gaining a KGD and retaining the quality without being influenced by the circumferential environment. CONSTITUTION: In this semiconductor device, an electrode formed on the surface of a first resin sealed package having a semiconductor chip sealed therein with resin is connected to the electrode of the semiconductor chip, and a mounting area to be connected to a mounting object and a testing area for connecting a testing apparatus are provided thereon. © KIPO & JPO 2002 ...

Method of measuring and assessing a probe card with an inspection device

System and method for measuring time dependent dielectric breakdown

An integrated circuit, in accordance with one embodiment is disclosed and includes a first device under test (DUT) module coupled to a first ring, oscillator module and a second DUT module coupled to a second ring oscillator module. A dielectric layer of the first DUT is stressed during a first mode, thereby causing tin-Le dependent dielectric breakdown in the first dielectric layer. A dielectric layer of the second DUT is maintained as a reference. The operating frequency of the first ring oscillator module, during a second mode, is a function of a gate leakage current of the stressed dielectric layer. The operating frequency of the second ring oscillator module, during the second mode, is a function of a gate leakage current the reference dielectric layer. The integrated circuit may also include a comparator module for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator modules.

Semiconductor device and its manufacturing method

The subject of the present invention is to provide semiconductor device and its manufacturing method, which are capable of examining short-circuit type fault of memory circuit in high precision and effectively examining short-circuit of memory circuit. For the memory circuit formed by disposing memory cells at the interesting points between plural word lines and plural bit lines, the operation of adding the desired electric potential to the mutually adjacent plural word lines or bit lines is conducted in the test mode. Plural word lines are set as the selection state; and the operation of grounding potential is then conducted onto the entire plural word lines. All plural bit lines are set as the electric potential corresponding to the selection levels of the word lines. The entire plural bit lines are set as the non-selecting state; and the shot-circuit fault among the mutual word lines, the mutual bit lines, and among the word line and the bit line are then examined through the current ...

Testing device and testing method

A testing device includes a first signal comparator, which obtains the values of the output patterns according to the result compared by the output signal voltage and the first threshold voltage existed in a first strobe timing, and as well as obtains the first output pattern row; a second signal comparator, which obtains the values of the output patterns according to the result compared by the output signal voltage and the second threshold voltage existed in a second strobe timing, and then obtains the second output pattern row; a header pattern row detection section, which detects that the first output pattern row is already consistent with the header pattern row; and an expectation value comparison section, which outputs the comparison result between the second output pattern row and the expectation value pattern row obtained by means of the second signal comparator, when the consistence between the first output pattern row and the header pattern row is detected.

Internal power supply voltage control apparatus having two internal power supply reference voltage generating circuits

In an internal power supply voltage control apparatus, reference voltage generating circuit (1) generates a reference voltage (VRO). A first internal power supply reference voltage generating circuit (2' ) generates a first internal power supply reference voltage (VREF) in accordance with the reference voltage, and a second internal power supply reference voltage generating circuit (9) generates a second internal power supply reference voltage (VREF) in accordance with a voltage applied to a predetermined pad (NC, OE, CS). A test mode selecting circuit (7) activates one of the first and second internal power supply reference voltage generating circuits in accordance with a control signal (PLVCC2). An internal power supply voltage generating circuit (3) generates an internal power supply voltage (VINT) in accordance with one of the first and second internal power supply reference voltages generated from an activated one of the first and second internal power supply reference voltage generating ...

Leakage testing of integrated circuits

A test configuration for testing a leakage current of a device under test (DUT) of an integrated circuit is provided including a logarithmic transducer electrically connected to the DUT and a voltmeter electrically connected to the logarithmic transducer.

Testing a device

A test apparatus for testing a device under test (DUT) to detect a defect comprises a measurement circuit (ME), a threshold circuit (TH), and a control circuit (CG). The measurement circuit (ME) comprises a counter (C1) which counts clock pulses (CLK) during a count period (TC) to obtain a counted number (N) of clock pulses (CLK). The count period (TC) has a start determined by the start (t1) of a testing cycle which occurs at the instant a switch (S) which is coupled to a terminal (IN) of the device under test (DUT) removes a power supply voltage (VDD) from the terminal (IN) and the voltage (VDD') at the terminal (IN) starts decaying. An end of the count period (TC) is determined by an instant (t2) a comparator (COM1) detects that the voltage (VDD') at the terminal (IN) crosses a reference value (VREF). The control circuit (CG) generates the clock signal (CLK) and/or a reference number (NTH) taking into account the variability of the manufacturing process of the circuit under test (CUT ...

Low temperature probing apparatus

THERMAL PRE-SCANNING OF ELECTRIC CIRCUITS USING THERMALLY-TRIMMABLE RESISTORS

There is described a method to change the value of a thermally-trimmable resistor in a non-permanent way by raising the temperature of the thermally- trimmable resistor to a level that is somewhere between room temperature and trimming temperature. By doing this, the trimming range that is available via true thermal trimming may be explored without actually trimming the value of the resistor. This is possible when the thermal Iy- trimmable resistor, or a portion thereof, has an essentially non-zero temperature coefficient of resistance (TCR).

SIGNAL INTEGRITY SELF-TEST ARCHITECTURE

A method suitable for testing an integrated circuit device is disclosed, the device comprising at least one module (47), wherein the at least one module incorporates at least one associated module monitor (49, 51, 53, 55) suitable for monitoring a device parameter such as temperature, supply noise, cross-talk etc. within the module.

METHOD OF INSPECTING SEMICONDUCTOR DEVICE, APPARATUS FOR INSPECTING THE SAME, AND METHOD OF MANUFACTURING THE SAME

In the inspection of a semiconductor device having internal elements including MISFETs, especially complementary MISFETs, whether the semiconductor device is good or defective is judged by static currents flowing through the device in a state that the internal elements are fixed. A stuck-at fault, a fault sensed using conventional fault-simulation of MISFETs, etc., and further a fault relative to the reliability in a long term can be sensed jointly by using a group of patterns which controls the states of the nodes of the internal elements or ON-OFF states of the MISFETs constituting the internal elements as a group of test patterns for the inspection. In the inspection according to the static currents, because of no necessity of considering the observability of faults at an output terminal, the number of the test patterns used for the inspection is small, and the creation thereof is easy too.

INTEGRATED CIRCUIT TESTER HAVING PATTERN GENERATOR CONTROLLED DATA BUS

An integrated circuit tester includes a host computer (36), a pattern generator (46) and a set of tester circuits (40). The tester circuits perform test activities on an integrated circuit (12) in response to sequences of test control data arriving via a set of data lines (47). The host computer may write parameter control data into the tester circuits via a bus (38) telling the tester circuits how to adjust various parameters of test activities to be performed in response to a next arriving sequence of test control data. The host computer is also linked to the pattern generator via that same bus and writes pattern control data into the pattern generator via the bus. The pattern control data tells the pattern generator to generate alternating sequences of test control data and pattern control data. As it is generated, each test control data sequence is delivered to the tester circuits via the data lines to tell the tester circuits how to carry out a sequence of test activities. As each ...

Input buffer and method for voltage level detection

An improved input buffer circuit and method configured for voltage detection is provided that can facilitate use of a mid-level voltage for testing purposes. An exemplary input buffer configured for voltage detection comprises a reference generator and a multi-state detector. The reference generator is configured to generate at least two reference voltages to be provided as input signals to the multi-state detector. The multi-state detector is suitably configured to receive an input reference signal, and through comparison of the input reference signal to the two reference voltages, provide output signals to three output terminals representing a high, low and mid-level state of operation. An exemplary input buffer circuit can comprise two differential pairs of transistors configured in a back-to-back arrangement and sharing a common node, thus resulting in lower current requirements. In addition, the input buffer can provide for multiple operations from the same die pad without requiring ...

Apparatus and method for IDDQ tests

A method for conducting IDDQ tests for a device having a plurality of test sites is disclosed. The method includes identifying voltage ranges for each of the plurality of test sites, closing a switch in each of a plurality of voltage drop setup circuits, and setting each of the plurality of test sites to one of a plurality of logic states. Each of the plurality of voltage drop setup circuits includes a resistor parallelly coupled to the switch. One terminal of each voltage drop setup circuit is coupled to a voltage source and the other terminal of each voltage drop setup circuit is coupled to respective tester channels of each of the plurality of test sites. After opening the switch in each of the plurality of voltage drop setup circuits, the voltage drop across the resistor in each voltage drop setup circuit is measured.

Method and apparatus for testing an immunity to electromagnetic interference and apparatus for irradiating radio wave for immunity test

An apparatus for measuring an electromagnetic wave stress of an article includes an electromagnetic wave irradiation unit comprising a plurality of radiation probes being adjacent to each other along a surface of the article at least on one side thereof so as to permit the probes to irradiate independently electromagnetic waves on divided local areas on a surface of the article corresponding to the locations of the probes. The apparatus also includes a control unit electrically connected to the article for receiving output signals having information as to existences of any abnormalities in individual divided local areas in the article exposed to an electromagnetic wave irradiation, the control unit being electrically connected to the transmitted unit for controlling operations of the transmitter unit to control independently an excitation of each radiation probe.

Semiconductor circuit system, method for testing semiconductor integrated circuits, and method for generating a test sequence for testing thereof

Logic blocks are placed between a power supply terminal and a grounding terminal. Each logic block has a logic circuit in which low-threshold voltage transistors are arranged, and high-threshold voltage transistors, pHVth- and nHVth-Tr's, are placed between each terminal and the logic circuit. At the time of receiving a test signal Sdt to perform testing of wiring arranged outside the logic circuit, and HVth-Tr's, a state control unit controls each HVth-Tr to turn off and an electric current at each terminal is measured, which makes it possible to detect faulty products resulting from the malfunction of HVth-Tr's and the short-circuiting of wires. It is possible to perform failure detection with making a distinction between failure occurring in the logic circuit and failure occurring outside the logic circuit.

Programmable compensating device to optimize performance in a DRAM controller chipset

A programmable compensating device for optimizing performance in a DRAM controller chipset, comprising process monitors for measuring process speeds of integrated circuits in the chipset, evaluation means for comparing the measured process speeds and identifying a slowest integrated circuit, and delay modules for reducing measured process speeds as necessary to match the process speed of the slowest integrated circuit, whereby DRAM access time is minimized to permit more frequent DRAM accesses, thereby optimizing chipset performance.

Potential detecting circuit which suppresses the adverse effects and eliminates dependency of detected potential on power supply potential

A potential detecting circuit comprises a MOSFET, a constant current circuit, a reference potential generating circuit and a comparing circuit. A power supply potential is applied to a drain of the MOSFET and a subject potential to be detected is applied to the gate of the MOSFET. The constant current circuit is connected to a source of the MOSFET. The comparing circuit compares a reference potential output from the reference potential generating circuit with a source potential of the MOSFET. A detection output is obtained on the basis of the comparison result. The source potential of the MOSFET is increased in accordance with an increase of the subject potential. When the source potential coincides with the reference potential output from the reference potential generating circuit, the level of the source potential is detected as a detection level.

MOS master-slave flip-flop with reduced number of pass gates

A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances IDDQ -testability with respect to known flip-flops.

Controllably adjusting voltage for operating an integrated circuit within specified limits

Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.

On-chip operating condition recorder

An operation recorder that stores the operating conditions of an integrated circuit chip. The recorder includes an on-chip oscillator and an external reference clock. The frequencies of these two sources are compared and a value indicating chip operating conditions is output to a memory. The memory contains a number of values which store the operating history of the chip.

Semiconductor integrated circuit device having input circuit without influence on reliability of diagnosis

A semiconductor integrated circuit device receives an input signal from an external wiring through an input transistor coupled to one of external leads, and a transfer gate is coupled between the external lead and a constant voltage source so as to provide a terminal resistance to the external wiring; however, the transfer gate is turned off in a test to see whether or not the input transistor is defective so as to enhance the reliability of the diagnosis.

Integrated circuit die suitable for wafer-level testing and method for forming the same

A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in the die. A conductive path is disposed beneath the insulator layer and is coupled to the circuit, the conductive path having an end portion that is located substantially at the edge of the substrate. The wafer on which the die is disposed has one or more signal lines that run along the scribe lines of the wafer. Before the die is scribed from the wafer, the conductive path couples the circuit on the die to one of these signal lines. The end portion of the conductive path is formed when the die is scribed from the wafer.

Test head cooling system

The present invention provides a test head cooling system for cooling test heads of a semiconductor IC test apparatus in an enclosed structure. A sealed housing is provided in a test head wherein an air duct is formed in a wall of the sealed box so that cooling air flow effectively. Several thousands of cables are connected to sockets of a plurality of boards. The boards are fixed in board racks by inserting the boards to sockets of the board racks. Gaps between the boards are arranged to provide good ventilation. A cooling pipe is connected to two heat exchangers for circulating cooling medium. A flexible hose for circulating the cooling medium is connected to one of the heat exchangers. The flexible hose is connected to an outside cooling apparatus so as to freely control the temperature of the cooling medium circulating inside the heat exchanger.

PSEUDO-RANDOM NOISE SIGNAL GENERATOR

A noise generating device comprises a generator (1) including a shift register (1a) which performs shift operations to sequentially shift a bit in an input stage to a next higher significant stage. An exclusive-OR circuit (1b) performs exclusive-OR operations between a pair of bits from selected stages of the shift register and feeds back to the input stage of the shift register. A filter (2) receives the pseudo-random data and outputs an analog signal. The filter comprises an operational amplifier (2a). Respective outputs of the stages of the shift register are alternately applied to non-inverting and inverting inputs of the operational amplifier through respective resistors (R1, . . . ,R23).

Precision solder resist registration inspection method

A method is disclosed for operating a machine vision inspection system to determine a fluorescent imaging height for acquiring a fluorescent image for repeatably determining the location of a feature within the fluorescent material. The height of an exposed workpiece portion exposed outside of the fluorescent material is determined (e.g., using a height sensor or autofocus operations). The determined height is repeatable. The exposed portion has a characteristic height relative to the fluorescent material and/or features located therein. The fluorescent imaging height, which may be inside the fluorescent material, is determined relative to the determined height of the exposed portion. The fluorescent imaging height is determined such that it enhances the detection of the desired feature located within the fluorescent material in the resulting fluorescent image. For a variety of workpieces, the method provides automatic acquisition of appropriately focused fluorescent image more reliably than previously known methods.

Element Substrate, Inspecting Method, and Manufacturing Method of Semiconductor Device

A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a semiconductor layer of the invention has a closed-loop circuit in which an antenna coil and a semiconductor element are connected in series, and a surface of an area over which the circuit is formed is covered with an insulating film. By using such a circuit, a contactless inspection can be carried out. Further, a ring oscillator can be substituted for the closed-loop circuit.

Device for disturbing the operation of an integrated circuit

A system for injecting faults by laser beams into an electronic circuit including: at least two lasers capable of emitting approximately parallel beams; at least one optical system receiving, on the magnifying side, the beams; and a support of the integrated circuit placed on the reducing side of the optical system.

Pattern measurement apparatus and pattern measurement method

A pattern measurement apparatus scans an observation region of a sample surface with an electron beam and detects secondary electrons emitted from the sample surface with the irradiation of the electron beam, by using a plurality of electron detectors arranged around the optical axis of the electron beam. Images are taken in two directions that are orthogonal to a pattern extending direction, and are opposite to each other across the optical axis. Then, profiles of a line orthogonal to each of edges are extracted from the images, and a subtraction between the line profiles is taken to obtain a subtractive profile. The position of an upper end of each edge is detected based on a descending portion of the subtractive profile, and the position of a lower end of the edge is detected based on a rising portion or a descending portion of one of the line profiles.

Board inspection apparatus

A board inspection apparatus includes an irradiation unit, an imaging unit, and an image processing unit. The image processing unit includes a three-dimensional measurement unit configured to perform three-dimensional measurement of the surfaces of the solder and the resist film by a certain three-dimensional measurement method based on the image data, a virtual standard surface setting unit configured to set a virtual standard surface corresponding to a contacting surface of a certain component mounted in a certain area of the printed board, a protrusion amount calculation unit configured to calculate a protrusion amount from the virtual standard surface for each solder printed and formed in the certain area, and a determination unit configured to determine whether the printed state of the solder passes or fails based on each of the protrusion amounts of the solder.

Semiconductor device, method of manufacturing thereof, signal transmission/reception method using such semiconductor device, and tester apparatus

A semiconductor device includes a substrate, a bonding pad provided above the substrate, a first signal transmitting/receiving portion provided above the substrate and below the bonding pad, and a transistor provided over the substrate. The transistor is connected to the first signal transmitting/receiving portion.

Device analysis

Performing an analysis of an electronic device sample by measuring a property at a plurality of points of said electronic device sample, and in advance of said analysis subjecting said plurality of points to at least one treatment that increases the difference in said property between at least two elements of said electronic device sample.

SYSTEM AND METHOD FOR MODULATION MAPPING

An apparatus for providing modulation mapping is disclosed. The apparatus includes a laser source, a motion mechanism providing relative motion between the laser beam and the DUT, signal collection mechanism, which include a photodetector and appropriate electronics for collecting modulated laser light reflected from the DUT, and a display mechanism for displaying a spatial modulation map which consists of the collected modulated laser light over a selected time period and a selected area of the IC. 1. A laser probing system for testing an integrated circuit microchip having silicon substrate and active devices therein , comprising:a laser source providing a laser beam;beam optics configured for receiving said laser beam and focusing said laser beam through the silicon substrate and onto at least one active device on said microchip;a photosensor receiving modulated laser light that is reflected from said microchip after being modulated by the active device, and providing a corresponding electrical signal;collection electronics receiving the electrical signal from said photosensor and providing an output signal;an analysis system receiving said output signal over a specified period of time and providing a total power signal corresponding to total radiation power of the modulated laser light received by the photosensor over the specified period of time; and,a display presenting the total power signal.2. The system of claim 1 , further comprising a scanner for scanning the laser beam over a selected area of the microchip and wherein the display presents a spatial modulation map which corresponds to total power signal of collected modulated laser light over a selected time period and a selected area of the microchip.3. The system of claim 1 , wherein the display presents the total power corresponding to modulated laser light reflected from a fixed position of the microchip.4. The system of claim 1 , wherein said active device comprises a transistor having a gate claim 1 ...

Specimen Testing Device and Method for Creating Absorbed Current Image

Proposed is a technique of emphasizing a change in absorbed current obtained from a faulty part in a wiring section as a testing target more than in other parts of the wiring section. A specimen testing device is configured to output an image of absorbed current output from two probes during scanning of an electron beam so as to be operatively associated with the scanning of the electron beam and includes the following mechanism. When a faulty part of a wiring section on the specimen side with which two probes are in contact is irradiated with an electron beam, the resistance value at the faulty part changes more than that of irradiation of a normal wiring section with the electron beam. Such a change in resistance value is detected as a change in ratio between a resistance value of the wiring section specified by the two probes and a known resistance value. With this method, an absorbed current image corresponding to the faulty part can be made easily distinguishable from an absorbed current image of other parts of the wiring section.

NON-CONTACT TESTING OF PRINTED ELECTRONICS

Apparatus and methods for non-contact testing of electronic components printed on a substrate () are provided. Test circuits () are printed on the substrate () at the same time as the desired electronic component. The test circuits () are all optical and include a first portion () for providing electrical energy for the test circuit () and a second portion () for generating a detectable optical signal that is indicative of at least one electrical property of the electronic component. The test circuits are used in real time and minimize the production of unusable scrap in the printing of such products as ePaper. 111.-. (canceled)12. A substrate comprising (i) a printed electronic component and (ii) a printed test circuit , where the test circuit comprises:(a) a first portion configured to generate electrical energy for the test circuit;(b) a second portion for generating a detectable optical signal, said signal being indicative of at least one electrical property of the electronic component; and(c) a circuit connecting the first and second portions.13. The substrate of wherein the substrate is in roll form.14. The substrate of wherein the test circuit emits optical energy at the second portion.15. The substrate of wherein the test circuit is configured to produces a change in an optical absorption property at the second portion.16. The substrate of wherein the test circuit transforms optical energy into electrical energy at the first portion.17. The substrate of wherein the test circuit transforms chemical energy into electrical energy at the first portion.18. The substrate of wherein the test circuit comprises a common material which (i) transforms optical energy into electrical energy at the first portion and produces optical energy at the second portion or (ii) transforms chemical energy into electrical energy at the first portion and produces a change in an optical absorption property at the second portion.19. The substrate of wherein the circuit is selected from ...

ACCURATE MEASUREMENT OF EXCESS CARRIER LIFETIME USING CARRIER DECAY METHOD

A method is described for accurate measuring of the excess carrier lifetime on a semiconductor sample from the carrier decay after termination of the excitation pulse imposed on the steady-state carrier excitation. The method includes determining a quality of decay parameter using progressing segments in each carrier decay; establishing an accurate lifetime measurement multiparameter domain for experimental variables whereby the quality of decay parameter falls within prescribed limits from the ideal exponential decay value of QD=1; and determining an excess carrier lifetime for the semiconductor sample based on experimental measurement conditions within the domain and the quality of decay value within the predetermined range indicative of an accurate excess carrier lifetime measurement. 1. A method of accurate determination of excess carrier lifetime of a semiconductor sample based on measurement of excess carrier decay; method comprising:exciting of excess carriers in a semiconductor sample with a steady bias light illumination that generates steady-state excess carrier concentration;exciting additional excess carriers with a light pulse imposed on a background steady-state illumination;after termination of light pulse excitation, measuring a decay signal represents the excess carriers decay to a steady-state background value;determining a quality of decay parameter from a ratio of successive time increment values corresponding to a drop of decay signal by a predetermined factor C in a progressing excess carrier decay; anddetermining an excess carrier lifetime for the semiconductor sample based on a measured decay where the quality of decay value is within a predetermined range indicative of an accurate excess carrier lifetime measurement.2. The method of claim 1 , wherein a predetermined signal drop factor C is larger than 1.3. The method of claim 1 , wherein the predetermined range corresponds to the quality of decay value being at or close to one.4. The method ...

METHODS AND PROCESSES FOR OPTICAL INTERFEROMETRIC OR HOLOGRAPHIC TEST IN THE DEVELOPMENT, EVALUATION, AND MANUFACTURE OF SEMICONDUCTOR AND FREE-METAL DEVICES UTILIZING ANISOTROPIC AND ISOTROPIC MATERIALS

Analysis and characterization of semiconductor and free-metal devices using a plurality of “live” and stored interference patterns or data detected to determine or generate two-dimensional or three-dimensional information of at least one internal stress or signal, or determining the effects thereof of internal or external stresses acting upon or within the electrical signals applied to a device under test or evaluation having exterior surfaces, interior structures, electronic features as well as determining the effects thereof of chemicals, bioelectric materials, or substances, placed adjacent to the surface of the devices under test. 1. A method for testing , developing , and evaluating a device under test , or evaluating the manufacture thereof comprising:(a) providing a beam of light from at least one light source having a first wavelength; the beam having at least one of the following attributes; a wavelength, a coherence, a phase, a polarization, an amplitude, or a phase-conjugate waveform,(b) imposing said beam of light on a test device having at least a surface, a volume, an interior surface, or an interior structure, over a spatial region within said device substantially greater than said first wavelength or equal to said first wavelength,(c) imposing said beam of light on a test device over a spatial region within or incident to said device wherein said test device has a first state of stress,(d) imposing said beam of light on said test device over a spatial region within said test device substantially greater than said first wavelength or equal to said first wavelength, wherein said test device has a second state of stress,(e) adjusting the angle of the second beam relative to the first beam to the device under test or adjusting the angle of the second beam to the detection device or devices relative to the first beam incident to the device under test,(f) obtaining data resulting from the interference of first said beam and said second beam within or ...

BOARD INSPECTION APPARATUS AND METHOD

An inspection method includes photographing a measurement target to acquire image data for each pixel of the measurement target, acquiring height data for each pixel of the measurement target, acquiring visibility data for each pixel of the measurement target, multiplying the acquired image data by at least one of the height data and the visibility data for each pixel to produce a result value, and setting a terminal area by using the produced result value. Thus, the terminal area may be accurately determined. 1. A board inspection apparatus comprising:a stage transferring a board;a first illumination section illuminating a light for aligning the board onto an inspection target;a projecting section projecting a grating pattern light for acquiring height data of the board onto the inspection target;a second illumination section illuminating a light for setting a terminal area of a component mounted on the board onto the inspection target;a third illumination section located nearer to the board than the second illumination section;an image photographing section photographing a first image of the board by light illumination of the second illumination section and photographing a second image of the board by grating pattern light illumination of the projecting section; anda control section discriminating the terminal area by using the first image and the second image photographed by the image photographing section.2. The board inspection apparatus of claim 1 , wherein the second illumination section is installed between the image photographing section and the projecting sections.3. The board inspection apparatus of claim 1 , wherein the second illumination section illuminates the light at an angle ranging from about 17° to about 20° with respect to a normal line perpendicular to a flat plane of the board.4. The board inspection apparatus of claim 1 , wherein the control section generates a contrast map by using at least one of visibility data and height data acquired ...

Apparatus for monitoring operating parameters of integrated circuits and integrated circuit with operating parameter monitoring

A device for monitoring operating parameters of integrated circuits. A signal is generated at least at one output of a comparison element by comparing switching states of input signals at the at least two inputs of the comparison element, which signal indicates that the at least one operating parameter has fallen below or has exceeded a predefined threshold. The two input signals are generated by at least two operating parameter-dependent devices, and the switching behavior thereof is subject to a time delay depending on the current value of the at least one operating parameter. A predefined time delay has a value such that when the predefined threshold of the operating parameter is exceeded, one of the input signals changes its switching state at the times predefined for the comparison element by the clock signal on the basis of the time delay.

APPARATUS AND METHOD FOR ACTIVE VOLTAGE COMPENSATION OF ELECTROSTATIC DISCHARGE OF A SUBSTRATE

A voltage compensation assembly adapted for apparatus having a prober for contacting the electronic elements on a substrate is described. The voltage compensation assembly includes a controller connected to the prober and adapted for active voltage compensation, and a voltage measuring unit connected to the controller and for measuring a voltage on the substrate. 1. A voltage compensation assembly adapted for a system having a prober configured to contact electronic elements on a substrate; the voltage compensation assembly comprising:a controller connected to the prober and adapted for active voltage compensation to the electronic elements via the prober;a voltage measuring unit connected to the controller and configured to measure a static voltage on the substrate, wherein the controller is configured to provide, via the prober, a voltage to the electronic elements in order to actively compensate the voltage on the substrate measured by the voltage measuring unit; andwherein the voltage measuring unit is configured to measure electronic field flux lines of the static voltage for measuring the static voltage of the substrate.2. The voltage compensation assembly according to claim 1 , wherein the voltage measuring unit is adapted for measuring an absolute value of the static voltage.3. The voltage compensation assembly according to claim 1 , wherein the voltage measuring unit is a static voltmeter.4. The voltage compensation assembly according to claim 1 , wherein the voltage measuring unit includes an oscillating piezo-crystal measuring the electronic field flux lines.5. The voltage compensation assembly according to claim 1 , wherein the system is a test system for the electronic elements on the substrate.6. An apparatus for testing or processing a substrate with electronic elements formed thereon claim 1 , comprising:a chamber;a substrate support configured to support the substrate within the chamber;a prober positioned to contact the substrate disposed on the ...

Chip control method and device

A chip control method, The method includes: acquiring a required frequency of the chip; detecting a current temperature of the chip, and determining a temperature range [T m , T m+1 ] to which the current temperature belongs, where T indicates a temperature, and m is a natural number; determining, through comparison according to ascending order of sorting the n voltage ranks, whether a frequency at which the chip can work at each temperature point of an analytical temperature range in an i th voltage rank is higher than the required frequency, where the analytical temperature range has a margin δ relative to the temperature range [T m , T m+1 ], δ≧0, and i=0, 1, . . . , n−1; and if yes, using the i th voltage rank as a working voltage of the chip, and using the required frequency as a working frequency of the chip.

APPARATUS AND METHOD FOR INSPECTING PCB-MOUNTED INTEGRATED CIRCUITS

A method and apparatus for testing the mounting of an integrated circuit on a printed circuit board using a ball grid array comprises directing an inclined laser beam from a line scan laser sensor at the integrated circuit, detecting the position of the lower edge of the integrated circuit from laser light backscattered from the integrated circuit and printed circuit board, determining through a trigonometric calculation the height of the integrated circuit above the printed circuit board following soldering of the ball grid array and comparing the height with reference data. The integrated circuit is deemed to have been successfully mounted to the printed circuit board if the height falls within a predetermined range. 1. A method of inspecting the mounting of an electronic component on a substrate , comprising:positioning a laser measurement device horizontally offset from the electronic component;tilting the laser measurement device through a predetermined angle relative to the vertical;operating the laser measurement device to direct an optical beam at the electronic component, the beam being inclined at the predetermined angle;measuring the distance of each of a plurality of points on the electronic component from the laser measurement device by detection of backscattered light from said points; andcalculating the height of the electronic component above the substrate in dependence on the measured distances and the predetermined angle.2. A method as claimed in wherein the laser measurement device comprises a line-scan laser sensor or the like arranged to project a laser line onto the electronic component and/or the substrate.3. A method as claimed in comprising projecting the line onto one or more of:a portion of a side surface of the electronic component;a portion of the substrate adjacent to the electronic component;a portion of the substrate underneath the component; or{'b': '16', 'a portion of an upper surface of the component ().'}4. A method as claimed in ...

Test Case Crash Recovery

A safe operating region of a complex integrated circuit may be determined by selecting an operating point for the integrated circuit (IC) at a first voltage and first frequency. A test program is executed by a central processing unit (CPU) comprised within the IC to test a portion of the IC. Communication activity between the IC and a host system is recorded to form a data log while the test program is being executed. A crash is detected by storing and examining the data log periodically, and assuming that the test program has crashed when any one of a predetermined set of crash conditions is detected during examination of the data log. The operating point may be iteratively changed and execution of the test program repeated while continuing to check for a crash until a crash is detected.

Charge sharing testing of through-body-vias

In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described.

SEMICONDUCTOR INTEGRATED CIRCUIT

There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S) and a predetermined linearity condition (S). 17-. (canceled)8. A semiconductor integrated circuit comprising:a first variable delay circuit;a first delay control circuit including a first digital analog conversion circuit configured to convert a digital signal to the amount of current and controlling the delay of the first variable delay circuit by voltage according to the amount of current; anda first test circuit for the first delay control circuit;wherein the first digital analog conversion circuit includes a plurality of unit current sources selected according to the value of a digital signal and the first test circuit determines that the value of a current flowing into each of the plurality of the unit current sources falls within a predetermined range to determine whether the first delay control circuit is normal or abnormal.9. The semiconductor integrated circuit according to claim 8 , further comprising:a second variable delay circuit;a second delay control circuit including a second digital analog conversion circuit configured to convert a digital signal to the amount of current and controlling the delay of the second variable delay circuit by voltage according to the amount of current; anda second test circuit for the second delay control circuit;wherein the second digital analog conversion circuit includes a plurality of unit current sources selected according to the value of a digital signal and the second test circuit determines whether the value of a current flowing into each of the plurality of the unit current sources falls within a predetermined range to ...

MODULAR WIRELESS COMMUNICATION DEVICE TESTING SYSTEM

Arrangements and techniques for testing mobile devices within a test module. The test modules are portable and may be stacked to provide a modular testing system. A pulley system may be used to move an actuator arm horizontally in the X and Y directions. The actuator arm may be moved vertically in the Z direction such that a tip may engage a touchscreen of a mobile device being tested or a user interface element of the mobile device. 1. A test module for testing mobile devices , the test module comprising:a frame;a test bed coupled to the frame;a device platform coupled to the test bed and configured to hold a Device Under Test (DUT); a first belt and a second belt;', 'a first set of pulleys and a second set of pulleys; and', 'a first motor and a second motor,', 'wherein the first belt is engaged with the first set of pulleys and the first motor, and', 'wherein the second belt is engaged with the second set of pulleys and the second motor;, 'a motion system coupled to the frame and configured to move a carriage assembly horizontally along an X axis and a Y axis, the motion system comprisingan actuator arm coupled to the carriage assembly;an actuator arm mount coupled to the actuator arm, the actuator arm mount configured to move vertically along a Z axis and engage the DUT, the actuator arm mount comprising a tip configured to engage a screen of the DUT and one or more User Interface (UI) elements of the DUT; anda controller configured to control the motion system and the actuator arm to perform various tests with respect to the DUT.2. The test module of claim 1 , wherein the actuator arm mount comprises a shaft and a coil spring coupled to the tip.3. The test module of claim 1 , wherein the tip comprises a capacitive tip.4. The test module of claim 1 , further comprising:a sliding drawer movably coupled to the frame below the test bed, the sliding drawer being configured to slide at least partially out from below the test bed,wherein the controller is mounted on ...

WIRELESS ELECTRONIC-CONTROL SYSTEM

Various embodiments include methods and apparatuses to test production tools and related electrical components therefor including individual printed-circuit boards (PCBs). In one example, a test-plug hardware-platform includes at least one input/output (I/O) connector, and a configurable control system to provide command and operational signals through the I/O connector and collect data through the I/O connector from at least one PCB under test. A wireless-mesh network within the test-plug hardware-platform can interface wirelessly with at least the PCB under test. The at least one PCB operating within a production tool or other piece of equipment. Other methods and systems are disclosed. 1. A test-plug hardware-platform , comprising:at least one input/output (I/O) connector;a configurable control system to provide command and operational signals through the I/O connector, the control system further to collect data through the I/O connector from at least one electrical component under test, the at least one electrical component configured to generate and receive a plurality of signals selected from signals including digital signals and analog signals; anda wireless-mesh network configured within the test-plug hardware-platform to interface wirelessly with at least the at least one electrical component under test.2. The test-plug hardware-platform of claim 1 , wherein the configurable control system is configured to capture actual input/output signals to and from the at least one electrical component under test.3. The test-plug hardware-platform of claim 1 , wherein the configurable control system further comprises universal I/O circuitry to interface with the at least one I/O connector claim 1 , one or more programmable logic devices (PLDs) to build reconfigurable digital circuits claim 1 , one or more microcontroller units (MCUs) to direct data received from and sent to the at least one electrical component claim 1 , and a radio source.4. The test-plug hardware- ...

TEST SYSTEM

A reflectometer for allowing a test of a device, the reflectometer comprising: a source of pulsed radiation; a first photoconductive element configured to output a pulse in response to irradiation from the pulsed source; a second photoconductive element configured to receive a pulse; and a transmission line arrangement configured to direct the pulse from the first photoconductive element to the device under test and to direct the pulse reflected from the device under test to the second photoconductive element. At least one of the first and second photoconductive elements is provided on a different substrate to that of the transmission line arrangement. 1. A reflectometer for allowing a test of a device , the reflectometer comprising:a source of pulsed radiation;a first photoconductive element configured to output a pulse in response to irradiation from said pulsed source;a second photoconductive element configured to receive a pulse; anda transmission line arrangement configured to direct the pulse from the first photoconductive element to the device under test and to direct the pulse reflected from the device under test to the second photoconductive element;wherein at least one of said first and second photoconductive elements is provided on a different substrate to that of the transmission line arrangement.2. A reflectometer according to claim 1 , wherein the at least one of the first and second photoconductive elements is provided on a substrate with a dielectric constant that is higher than the substrate on which the transmission line arrangement is formed.3. A reflectometer according to claim 1 , wherein the first photoconductive element and the second photoconductive element are spatially separated.4. A reflectometer according to wherein the transmission line is formed on a first substrate claim 1 , the first photoconductive element is formed on a second substrate and the second photoconductive element is formed on a third substrate.5. A reflectometer ...

Integrated time dependent dielectric breakdown reliability testing

Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

Fiber attach assembly and test automation

An approach compatible with high volume manufacturing for assembling a photonic chip with integrated optical fibers involving placing a die on an assembly station, providing one or more optical fibers, placing the one or more optical fibers into corresponding one or more grooves of the die, bonding the one or more optical fibers to the die and performing an optical test of the die using the one or more optical fibers, and severing the one or more optical fibers. The die can be removed from the assembly station while retaining a predetermined length of each severed optical fiber and the one or more optical fibers can be prepared for assembly to a next die.

TEST PROBE AND APPARATUS FOR TESTING PRINTED CIRCUIT BOARD

The present disclosure provides a test probe and an apparatus for testing a printed circuit board, wherein the test probe comprises a test pin; and an insulating protection sleeve with adhesive attached therein, wherein the insulating protection sleeve is sleeved on the test pin, and wherein a first end of the test pin protrudes from the insulating protection sleeve. 1. A test probe , comprising:a test pin; andan insulating protection sleeve with adhesive attached therein,wherein the insulating protection sleeve is sleeved on the test pin, andwherein a first end of the test pin protrudes from the insulating protection sleeve.2. The test probe according to claim 1 , wherein a second end of the test pin is an electrical connector.3. An apparatus for testing a printed circuit board claim 1 , comprising:a test pin;an insulating protection sleeve with adhesive attached therein; anda wire,wherein the insulating protection sleeve is sleeved on the test pin,wherein a first end of the test pin protrudes from the insulating protection sleeve, andwherein a second end of the test pin is connected to a first end of the wire.4. The apparatus according to claim 3 , wherein a second end of the wire is connected to a test instrument.5. The apparatus according to claim 3 , further comprising:a first test pad,wherein a second end of the wire is connected to the first test pad.6. The apparatus according to claim 5 , wherein the area of the first test pad is larger than that of a second test pad on the printed circuit board to be tested.7. The apparatus according to claim 5 , further comprising:a ground pad located close to the first test pad.8. The apparatus according to claim 7 , wherein the first test pad and the ground pad are located on the same insulating plate.9. The apparatus according to claim 4 , further comprising:a test instrument configured to test electrical characteristics of the printed circuit board. This application claims priority to the Chinese Patent Application No. ...

System and Method for Parallel Testing of Electronic Device

Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

Method of detecting irregular current flow in an integrated circuit device and apparatus therefor

A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.

DETECTION OF MIS-SOLDERED CIRCUITS BY SIGNAL ECHO CHARACTERISTICS

One embodiment of the present invention sets forth a method for detecting defective solder balls that includes configuring a transmitter pad to transmit a pulse signal, transmitting the pulse signal, configuring transmitter pad to receive a pulse reflection, receiving a pulse reflection, analyzing the pulse reflection; and determining whether the pulse reflection is indicative of a defective solder ball. One advantage of the disclosed method is that solder ball defects may be detected more accurately than in the trial and error approach. 1. A method for detecting one or more defective solder ball connections , the method comprising:configuring, via logic included within a processing unit, a transmitter pad to transmit a pulse signal and to receive a pulse reflection,transmitting the pulse signal,determining whether a pulse reflection is received in response to the pulse signal; andif a pulse reflection is received, then analyzing the pulse reflection to identify where a defective solder ball connection is located; orif a pulse reflection is not received, then indicating that a defective solder ball connection has not been detected.2. The method of claim 1 , wherein analyzing the pulse reflection comprises determining an amount of delay between the point in time when the pulse signal is transmitted and the point in time when the pulse reflection is received.3. The method of claim 2 , wherein a small amount of delay indicates that the defective solder ball connection is proximate to the processing unit claim 2 , and a large amount of delay indicates that the defective solder ball connection is proximate to a device that receives the pulse signal.4. The method of claim 3 , wherein the processing unit comprises a graphics processing unit claim 3 , and the device that receives the pulse signal comprises a memory device.5. The method of claim 1 , further comprising transmitting a configuration instruction along with the pulse signal.6. The method of claim 5 , wherein the ...

Inspection method and inspection system

An inspection method includes a step S20 of electrically connecting electrical signal terminals of a semiconductor device to electric connectors, and optically connecting optical signal terminals of the semiconductor device to optical connectors, a step S30 of measuring a test light output signal output from a monitoring element provided in an inspection object in response to a test input signal having been input to the monitoring element while adjusting conditions of a position and an inclination of the inspection object, and extracting conditions in which an optical intensity of the test light output signal is a predetermined determination value or greater as inspection conditions, and a step S40 of inspecting the semiconductor device under the inspection conditions.

ELECTRICAL CURRENT MEASUREMENT SYSTEM

A test system for measuring electrical current consumption of a device under test (DUT) includes a capacitor with power and ground terminals; a voltage regulator with input and output terminals; first and second switching elements; and a controller. The voltage regulator generates a DUT operating voltage based on its input voltage. The first switching element is arranged between a direct current (DC) voltage source and the regulator input, and the second switching element is arranged between the DC voltage source and the capacitor. The controller operates the switching elements to charge the capacitor, and to configure the test system for measuring operating current of the DUT using the capacitor as the power source. 1. A test system for measuring electrical current consumption of a device under test (DUT) , the test system comprising:a power capacitor comprising a power terminal and a ground terminal, the power capacitor configured to provide capacitor voltage at the power terminal;a voltage regulator comprising a regulator input terminal and a regulator output terminal, the voltage regulator configured to generate a DUT operating voltage at the regulator output terminal based on an input voltage at the regulator input terminal;a switching circuit to regulate electrical connections between a direct current (DC) voltage source, the power capacitor, and the voltage regulator; and control the switching circuit to place the test system into a charging state to charge the power capacitor with the DC voltage source;', 'after the power capacitor has reached a charged voltage, control the switching circuit to place the test system into a measurement state such that the power capacitor provides the capacitor voltage to the voltage regulator; and', 'after the power capacitor has reached a discharged voltage in response to loading, calculate electrical current provided by the power capacitor in a time period recorded during operation of the test system in the measurement ...

System and method for surface inspection

Systems and methods for surface inspection for imaging an object via an optical coherence tomography (OCT) imaging modality are provided. The system includes an OCT imaging module for generating imaging data from a surface under inspection, including: an electromagnetic radiation source for interrogating the object with light; an optical system having an interferometer for generating an interference pattern corresponding to the light backscattered from the object; and a detector for detecting the interference pattern and generating imaging data therefrom; a motion controller device for moving at least one component of the OCT imaging module relative to the object, the motion controller device moving the OCT imaging module such that a surface of the object is within a depth of field of the OCT imaging module; and a computational module for: aggregating the imaging data; and determining the presence or absence of surface defects in the imaging data.

Aging-sensitive recycling sensors for chip authentication

Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

OPTICAL TO OPTICAL TIME AND SPATIAL RESOLUTION ENHANCEMENTS FOR IMPROVING CHARACTERIZATION OF SECONDARY ELECTRON EMISSION AND CONTROL FOR ETCH-, ELECTRON-, AND ION-BEAM DEVICES

In decreasing the electron beam duration required for increased time resolution, the average beam current decreases, degrading measurement sensitivity and limiting practical systems to a time resolution of several hundred picoseconds. Optical non-invasive or non-destructive enhancements permits femto-second measurements and a new regime of internal device and process evaluation and quality control in integrated circuit (IC) manufacture, at every stage from the initial wafer to the point at which the wafer is diced into individual ICs. 1. An optical image detection method for enhancing time and spatial resolution in internal integrated circuit testing in at least one phase of evaluation and manufacture , using a first infrared or optical imaging device that is sensitive to an incident electron or ion beam or X-ray beam or an illumination which stimulates a secondary electron emission or creates a photocurrent or changes in electric field or stresses within or acting upon the first imaging device , and a second infrared imaging device that is illuminated by light incident to the first imaging device which is reflected to the second imaging device which images optical changes in phase or polarization or amplitude or birefringence or intensity within the first imaging device , the method comprising:imposing an optical beam over the spatial area of stimulation of secondary electron emission from surface metallization by the incident electron or ion-beam or X-ray beam or an illumination optically modulating the optical beam;directing the optical beam incident to the area of stimulation of secondary electron or photon emission to the a first infrared or optical imaging device; andadjusting the duration or modulation or attributes of the incident optical beam relative to the feature or duration or intensity or movement or target area of the electron or ion beam or X-ray beam or an ultraviolet illumination to enhance the sampling time resolution or spatial attributes of the ...

METHOD OF INSPECTING A SPECIMEN AND SYSTEM THEREOF

Data indicative of location information of a potential defect of interest revealed in a specimen and of one or more layers of the specimen corresponding to the potential defect of interest may be received. A die layout clip may be generated in accordance with the data by deriving the die layout clip based on the location information of the potential defect of interest and the one or more layers of the specimen corresponding to the potential defect of interest. The die layout clip may include information indicative of one or more patterns characterizing an inspection area that includes the potential defect of interest of the specimen. The generated die layout clip may be transmitted to a semiconductor inspection unit where an inspection by the semiconductor inspection unit of a semiconductor wafer that includes the specimen corresponding to the potential defect of interest is based on the one or more patterns of the die layout clip. 1. A system comprising:a memory; and receive data indicative of location information of a potential defect of interest revealed in a specimen and of one or more layers of the specimen corresponding to the potential defect of interest;', 'generate a die layout clip in accordance with the data by deriving the die layout clip based on the location information of the potential defect of interest and the one or more layers of the specimen corresponding to the potential defect of interest, the die layout clip comprising information indicative of one or more patterns characterizing an inspection area that includes the potential defect of interest of the specimen; and', 'transmit the generated die layout clip to a semiconductor inspection unit, wherein an inspection by the semiconductor inspection unit of a semiconductor wafer that includes the specimen corresponding to the potential defect of interest is based on the one or more patterns of the die layout clip., 'a processor, operatively coupled with the memory, to2. The system of claim 1 , ...

APPARATUS TO PERFORM A NON-CONTACT TEST OF A SEMICONDUCTOR PACKAGE

An apparatus to test a semiconductor package includes a vertical illuminator to supply vertical illumination in the same axial direction as a measurement target and a vertical image unit to capture a vertical image of the measurement target so that a testing apparatus may 2-dimensionally determine information on the shape, size, or position of a solder ball. An inclined illuminator may supply inclined illumination in a different axial direction from the measurement target, and an inclined image capture unit may capture a side image of the measurement target so that the testing apparatus may 3-dimensionally determine information on a state of contact of the solder ball with the ball land. The inclined image capture unit may include a color camera using color information, thereby markedly increasing test reliability and yield. 1. A method of testing a tested device , the method comprising:positioning the tested device to have a length axis parallel to a first direction;emitting a first light to travel in the first direction to contact a test area of the tested device;capturing a first image of the test area generated by the first light reflected off of the test area of the tested device at a 180° angle with respect to the first direction;emitting a second light to travel in a second direction that is not parallel to the first direction; andcapturing a second image of the test area generated by the second light reflected off of the test area at a second angle that is not parallel to the first direction,wherein capturing the second image comprises capturing the second image including an information which is different from an information included in the first image.2. The method according to claim 1 , further comprising:capturing color data of the second image.3. The method according to claim 2 , wherein the color data corresponds to red claim 2 , green claim 2 , and blue color of the test area.4. The method according to claim 2 , wherein capturing the second image ...

System and method for built-in self-test of electronic circuits

In described examples of a device with built-in-self-test, a multiplexer has at least first and second input terminals and is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and selection signals. Also, the multiplexer is coupled to output: the first input signal in response to a first combination of the selection signals; the second input signal in response to a second combination of the selection signals; and an analog summation of the first and second input signals in response to a third combination of the selection signals.

Probe station for the simultaneous measurement of thermal and electrical characteristics of thermoelectric module

The present invention relate to a probe station system which can measure thermal distribution and thermographic images, and more particularly, to such an probe station which can detect an electrical characteristics change according to the supply of heat to an element, for example a thermoelectric element to measure the characteristics of the element. The probe station for the simultaneous measurement of thermal and electrical characteristics of a thermoelectric element includes: a chamber, a base, a platform, a probe unit, a heat source, and an infrared image detection unit and the thermographic image and the voltage signal of the element are synchronized in real time.

Image Sensor Testing Probe Card

A method of increasing uniformity in light from a light source at a plurality of targets of the light includes locating a plurality of movable aperture elements between the light source and the targets. Each aperture element defines an aperture through which the light passes from the light source to an associated one of the plurality of targets associated with the aperture element along a longitudinal axis of the aperture element. The method also includes moving at least one of the aperture elements along its longitudinal axis to change a feature of light incident on the target associated with the aperture element. 1. A method of increasing uniformity in light from a light source at a plurality of targets of the light , the method comprising:locating a plurality of movable aperture elements between the light source and the targets, each aperture element defining an aperture through which the light passes from the light source to an associated one of the plurality of targets associated with the aperture element along a longitudinal axis of the aperture element; andmoving at least one of the aperture elements along its longitudinal axis to change a feature of light incident on the target associated with the aperture element.2. The method of claim 1 , wherein the feature of the light changed by moving one of the plurality of aperture elements is illuminance of the light incident on the associated target.3. The method of claim 2 , wherein at least one of the plurality of aperture elements is moved such that uniformity of illuminance of the light incident on the plurality of targets is increased.4. The method of claim 2 , wherein each aperture has a selectable inside diameter such that the illuminance at the associated target is adjustable.5. The method of claim 2 , wherein each aperture element is movable such that a distance between the aperture element and the light source is adjustable claim 2 , such that the illuminance at the associated target is adjustable.6. The ...

Method and Apparatus for Testing a Semiconductor Device

The present disclosure provides methods for testing and evaluating electrical parameters of electronic circuits. An exemplary method includes providing a device-under-test electrically coupled to a testing apparatus; and determining an optimum value of a first electrical parameter and an optimum value of a second parameter by testing the device-under-test according to a set of first electrical parameter values and a set of second electrical parameter values. The optimum value of the first electrical parameter and the optimum value of the second parameter are determined based on an electrical noise response of the device-under-test. 1. A method comprising:providing a device-under-test electrically coupled to a testing apparatus; anddetermining an optimum value of a first electrical parameter and an optimum value of a second parameter by testing the device-under-test according to a set of first electrical parameter values and a set of second electrical parameter values, wherein the optimum value of the first electrical parameter and the optimum value of the second parameter are determined based on an electrical noise response of the device-under-test.2. The method of claim 1 , wherein the first electrical parameter corresponds to a supply voltage and the second electrical parameter corresponds to a device terminal voltage.3. The method of claim 1 , wherein the optimum value of the first electrical parameter and the optimum value of the second electrical parameter are determined using a first set of contacts of the device-under-test claim 1 , the method further comprising:testing the device-under test using a second set of contacts of the device-under-test according to at least one of the optimum value of the first electrical parameter or the optimum value of the second electrical parameter.4. The method of claim 1 , wherein the values of the set of first electrical parameter values are at a coarser interval than the values of the set of second electrical parameter ...

ANALYSIS METHOD AND ANALYSIS SYSTEM OF VOLTAGE CONTRAST DEFECT

A voltage contrast defect analysis method including the following steps is provided. A voltage contrast defect detection is performed on a die to be tested by using an electron beam inspection machine to find out a defect address of a voltage contrast defect. A first scanning electron microscope image at the defect address of the die to be tested is obtained by using a scanning electron microscope. A first critical dimension of the first scanning electron microscope image at the defect address of the die to be tested is measured. The first critical dimension on the die to be tested is compared with a corresponding second critical dimension on a reference die where no voltage contrast defect occurs at the defect address to determine whether the first critical dimension and the second critical dimension are the same. 1. A voltage contrast defect analysis method , comprising:performing a voltage contrast defect detection on a die to be tested by using an electron beam inspection machine to find out a defect address of a voltage contrast defect;obtaining a first scanning electron microscope image at the defect address of the die to be tested by using a scanning electron microscope;measuring a first critical dimension of the first scanning electron microscope image at the defect address of the die to be tested; andcomparing the first critical dimension on the die to be tested with a corresponding second critical dimension on a reference die where no voltage contrast defect occurs at the defect address to determine whether the first critical dimension and the second critical dimension are the same.2. The voltage contrast defect analysis method according to claim 1 , wherein the die to be tested and the reference die are derived from the same wafer.35100. The voltage contrast defect analysis method according to claim 1 , wherein an inspection coverage of the voltage contrast defect detection is % to % of a device region to be tested on the die to be tested.4. The voltage ...

CONTROL METHOD OF INSPECTION APPARATUS AND INSPECTION APPARATUS

A control method of an inspection apparatus including a mounting stage on which a substrate having a plurality of inspection objects is mounted, a plurality of sections being formed with respect to the mounting stage and a heater controllable to heat for each of the sections includes when inspecting a first inspection object to be inspected among the plurality of inspection objects, causing the heater to heat a section corresponding to the first inspection object and a section corresponding to a second inspection object to be inspected next. 1. A control method of an inspection apparatus includinga mounting stage on which a substrate having a plurality of inspection objects is mounted, a plurality of sections being formed with respect to the mounting stage anda heater controllable to heat for each of the sections,wherein the control method comprises:when inspecting a first inspection object to be inspected among the plurality of inspection objects, causing the heater to heat a section corresponding to the first inspection object and a section corresponding to a second inspection object to be inspected next.2. The control method of the inspection apparatus according to claim 1 , wherein the second inspection object is arranged next to the first inspection object on the substrate.3. The control method of the inspection apparatus according to claim 1 ,wherein the inspection apparatus includes a temperature sensor configured to detect a temperature of an inspection object, andwherein when heating a section corresponding to the inspection object, the heater is controlled so that the temperature of the inspection object becomes a target temperature based on the temperature of the inspection object detected by the temperature sensor.4. The control method of the inspection apparatus according to claim 3 , further comprising:upon an elapse of a threshold time after the temperature of the inspection object has stabilized at the target temperature, determining that ...

PATTERN DEFECT DETECTION METHOD

A pattern defect detection method capable of detecting a pattern defect of a semiconductor integrated circuit with higher accuracy is disclosed. The pattern defect detection method includes: extracting an image of an inspection target pattern from an image of a specimen; identifying a reference pattern from design data, the reference pattern having the same shape and the same position as those of the inspection target pattern; calculating a brightness index value indicating a brightness of an entirety of the inspection target pattern; repeating said extracting an inspection target pattern, said identifying a reference pattern, and said calculating a brightness index value, thereby building mass data containing brightness index values of inspection target patterns and corresponding reference patterns; determining a standard range of brightness index value based on the brightness index values contained in the mass data; and detecting a defect of the inspection target pattern based on whether or not the calculated brightness index value is within the standard range. 1. A pattern defect detection method comprising:generating an image of a specimen with a scanning electron microscope;extracting an image of an inspection target pattern from the image of the specimen;identifying a reference pattern from design data, the reference pattern having the same shape and the same position as those of the inspection target pattern;calculating a brightness index value indicating a brightness of an entirety of the inspection target pattern;repeating said extracting an inspection target pattern, said identifying a reference pattern, and said calculating a brightness index value, thereby building mass data containing brightness index values of inspection target patterns and corresponding reference patterns;determining a standard range of brightness index value based on the brightness index values contained in the mass data; anddetecting a defect of the inspection target pattern based ...

Systems and Methods for Diagnostic Circuit Testing

An integrated circuit including a first multiplexor configured to receive one of a plurality of diagnostic signals from circuitry under test (DUT), the first multiplexor responsive to diagnostic signals provided thereto and configured to selectively output one of the diagnostic signals in response to a control signal, a second multiplexor configured to receive one of a plurality of reference signals from one of a plurality of nodes on a reference circuit, the second multiplexor configured to selectively output one of the diagnostic signals in response to a control signal, and a comparator configured to compare the diagnostic signal elicited from the first multiplexor with the reference signal elicited from the second multiplexor, the comparator further configured to output the result of the comparison between the diagnostic signal and the reference signal. 1. An integrated circuit comprising:a reference circuit configured to provide a plurality of reference signals;a first circuit having a first plurality of inputs with at least some of the first plurality of inputs configured to receive a corresponding one of a second plurality of diagnostic signals from circuitry under test, wherein in response to a control signal provided to an input thereof, said first circuit is configured to provide at an output thereof a selected one of the diagnostic signals on the first plurality of inputs;a second circuit having a third plurality of inputs with each of the third plurality of inputs coupled to said reference circuit with at least some of the third plurality of inputs configured to receive corresponding ones of the plurality of reference signals from said reference circuit and wherein, in response to a control signal provided thereto, said second circuit is configured to provide at an output thereof a selected one of the reference signals; anda comparator having a first input coupled to the output of said first circuit and having a second input coupled to the output of said ...

Inspection apparatus and inspection method

In accordance with an embodiment, an inspection apparatus includes first and second charged particle beam application units to apply charged particle beams to a sample, a detector, an image acquiring unit, and a judgment unit. The sample includes a stack structure in which electrically conductive films and insulating films are alternately stacked, electrically conductive layers, first and second contact plugs. The first charged particle beam application unit controls the potential of each electrically conductive film by applying a first charged particle beam to the second contact plugs. The second charged particle beam application unit applies a second charged particle beam to the first contact plugs. The detector detects secondary charged particles from the stack structure and outputs a signal. The image acquiring unit processes the signal to acquire a first image of the sample surface. The judgment unit judges an abnormality of the sample from the acquired first image.

OPTICAL TESTING OF A MULTI QUANTUM WELL SEMICONDUCTOR DEVICE

A pump light pulse is generating a strain pulse in a sample that includes quantum wells. A signal is measured using a probe light pulse. The probe light pulse is delayed in relation to the pump light pulse. The signal derives from a change in an optical property of the sample, which optical property responds to the generated strain pulse. One may deduce parameters of interest of the sample, including the quantum wells, from the characteristics of the signal. For discerning between various components of the stress in the quantum wells a lead pump pulse, preceding the pump light, pulse my also be used. A system for the application of such methods is also disclosed. 1. A method , comprising:accepting a sample, wherein said sample comprises quantum wells sandwiched in-between two semiconductor layers, wherein said sample has an optical property, and has a parameter of interest;creating a strain pulse inside said sample by directing a pump light pulse onto said sample and selecting the wavelength of said pump light pulse in such manner that said quantum wells absorb said pump light pulse whereby generating electron/hole pairs in said quantum wells, wherein said quantum wells are piezoelectric whereby said strain pulse is responsive to an electric field created by said electron/hole pairs, and wherein said optical property is responsive to said strain pulse;measuring a signal using a probe light pulse, wherein said probe light pulse is directed onto said sample with a time delay in relation to said pump light pulse, and said probe light pulse is responsive to said optical property, wherein said signal derives from a change in said optical property as function of said time delay, wherein said signal has an amplitude, an said amplitude is responsive to said electric field; andderiving said parameter of interest from a characteristic of said amplitude.2. The method of claim 1 , wherein said pump light pulse has an intensity and said characteristic of said amplitude is a ...

Measuring power consumption of ciruit component operating in ultra-low power mode

By powering an electronic component operating in an ultra-low power mode from a pre-charged measuring capacitor and measuring the time to discharge the capacitor to a trip voltage level, measurement data can be obtained. In some implementations, the capacitance of the capacitor can be obtained by adding a known current to the unknown current drawn from the capacitor and calculating the capacitance using a mathematical formula.

INSPECTION DEVICE AND INSPECTION METHOD

An inspection device is provided, which is capable of detecting a short circuit failure even when a connector is provided on a wiring board. The inspection device is configured to inspect a short circuit failure generated at any connected part of a plurality of pins to a wiring board via solder. The plurality of pins is included in a connector provided on the wiring board. The inspection device includes: a wiring connected to certain pins of the plurality of pins ; a second wiring connected to remaining pins of the plurality of pins ; and a tester unit connected to the first wiring and to the second wiring so as to inspect insulation between the certain pins and the remaining pins 1. An inspection device configured to inspect a short circuit failure generated at any connected part of a plurality of pins to a wiring board via solder , the plurality of pins being included in a connector provided on the wiring board , the inspection device comprising:a first wiring connected to certain pins of the plurality of pins;a second wiring connected to remaining pins of the plurality of pins; andan inspection unit connected to the first wiring and to the second wiring so as to inspect insulation between the certain pins of the plurality of pins and the remaining pins of the plurality of pins.2. The inspection device according to claim 1 , whereinthe plurality of pins is arranged in a matrix in plan view,the first wiring is connected to pins in odd-numbered columns out of the plurality of pins,the second wiring is connected to pins in even-numbered columns out of the plurality of pins, andthe inspection unit is configured to inspect insulation between the pins in the odd-numbered columns and the pins in the even-numbered columns.3. The inspection device according to claim 1 , whereinthe plurality of pins is arranged in a matrix in plan view,the first wiring is connected to pins in odd-numbered rows out of the plurality of pins,the second wiring is connected to pins in even- ...

Combined Transmitted and Reflected Light Imaging of Internal Cracks in Semiconductor Devices

A first light source is directed at an outer surface of a workpiece in an inspection module. The light from the first light source that is reflected from the outer surface of the workpiece is directed to the camera via a first pathway. The light from the first light source transmitted through the workpiece is directed to the camera via a second pathway. A second light source is directed at the outer surface of the workpiece 180° from that of the first light source. The light from the second light source that is reflected from the outer surface of the workpiece is directed to the camera via the second pathway. The light from the second light source transmitted through the workpiece is directed to the camera via the first pathway. 1. A system comprising:a vacuum pump;a nozzle in fluid communication with the vacuum pump, wherein the nozzle is configured to hold a workpiece;a nozzle actuator configured to move the nozzle; and a first light source;', 'a second light source;', 'a first mirror that is disposed to receive light from the first light source, wherein the first mirror directs the light from the first light source at an outer surface of the workpiece;', 'a second mirror that is disposed to receive light from the second light source, wherein the second mirror directs the light from the second light source at the outer surface of the workpiece;', 'a first semi-mirror disposed between the first light source and the first mirror, wherein the first semi-mirror receives the light from the first light source that is reflected from the outer surface of the workpiece and the light from the second light source that is transmitted through the workpiece;', 'a second semi-mirror disposed between the second light source and the second mirror, wherein the second semi-mirror receives the light from the second light source that is reflected from the outer surface of the workpiece and the light from the first light source that is transmitted through the workpiece;', 'a camera ...

INSPECTION METHOD AND INSPECTION APPARATUS

An inspection apparatus includes a tester unit that applies a stimulus signal to a semiconductor apparatus, an MO crystal arranged to face a semiconductor apparatus, a light source that outputs light, an optical scanner that irradiates the MO crystal with light output from light source, a light detector that detects light reflected from the MO crystal arranged to face the semiconductor apparatus D and outputs a detection signal, and a computer that generate phase image data based on a phase difference between a reference signal generated based on a stimulus signal and the detection signal, the phase image data including a phase component indicating the phase difference, and generates an image indicating a path of a current from the phase image data. 1. An inspection method for acquiring a path of a current generated in a measurement target by applying a stimulus signal to the measurement target , the inspection method comprising:applying a stimulus signal to the measurement target;irradiating a magneto-optical crystal disposed facing the measurement target with light;detecting light reflected from the magneto-optical crystal, according to the irradiated light, and outputting a detection signal;generating phase image data based on a phase difference between a reference signal generated based on the stimulus signal and the detection signal, the phase image data comprising a phase component indicating the phase difference; andgenerating an image indicating a path of the current based on the phase image data.2. The inspection method according to claim 1 ,wherein generating the image indicating the path of the current comprises generating statistical value image data indicating a statistical value of the phase component based on the phase image data, and generating the image indicating the path of the current based on the statistical value image data.3. The inspection method according to claim 1 ,wherein generating the image indicating the path of the current comprises ...

TEST BOARD FOR SEMICONDUCTOR PACKAGE, TEST SYSTEM, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

A test board includes: a board substrate; a device under test (DUT) socket connected to the board substrate and configured to accommodate a semiconductor package; a test controller; a wireless signal unit configured to wirelessly exchange signals with a server; and a wireless power unit configured to be wirelessly charged by an external source and configured to supply electric power to the test controller and the DUT socket, wherein the test controller is configured to independently perform a test on the semiconductor package accommodated in the DUT socket in response to a test pattern command being wirelessly received from the server via the wireless signal unit. 1. A test board comprising:a board substrate;a device under test (DUT) socket connected to the board substrate and configured to accommodate a semiconductor package;a test controller;a wireless signal unit configured to wirelessly exchange signals with a server; anda wireless power unit configured to be wirelessly charged by an external source and configured to supply electric power to the test controller and the DUT socket,wherein the test controller is configured to independently perform a test on the semiconductor package accommodated in the DUT socket in response to a test pattern command being wirelessly received from the server via the wireless signal unit.2. The test board of claim 1 , wherein the test controller is attached to a first surface of the board substrate.3. The test board of claim 1 , wherein the wireless signal unit comprises a wireless signal transceiver that is attached to a first surface of the board substrate claim 1 , and a power receiver attached to a second surface opposite to the first surface of the board substrate; and', 'a power storage and supply unit configure to store and to supply the electric power received by the power receiver from the external source., 'wherein the wireless power unit comprises47.-. (canceled)8. The test board of claim 1 , wherein the test controller ...

OPTO ELECTRICAL TEST MEASUREMENT SYSTEM FOR INTEGRATED PHOTONIC DEVICES AND CIRCUITS

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data. 1. An integrated circuit including a testing circuit , said testing circuit comprising an optical test circuit having:an optical input configured to receive an optical test signal;a test channel configured to receive said optical test signal and produce an optical test output signal in response to processing of the optical test signal through at least one optical device under test circuit, said test channel further including a photodetector coupled to receive said optical test output signal and generate an electrical signal; andan electrical output for outputting said electrical signal.2. The integrated circuit of claim 1 , wherein the test channel comprises a plurality of series coupled optical device under test circuits.3. The integrated circuit of claim 1 , wherein the test channel comprises a further photodetector coupled to receive optical test signal and generate a further electrical signal claim 1 , the optical test circuit further including a further electrical output for outputting said further electrical signal.4. The integrated circuit of claim 1 , wherein the test channel comprises a further photodetector coupled to receive the optical test output signal and generate a further electrical signal claim 1 , the ...

Semiconductor inspection device

An inspection system includes a light source, a mirror, Galvano mirrors, a casing that holds the mirror and the Galvano mirrors inside and includes an attachment portion for attaching an optical element, and a control unit that controls a deflection angle of the Galvano mirrors, wherein the control unit controls the deflection angle so that an optical path optically connected to a semiconductor device is switched between a first optical path passing through the Galvano mirrors and the mirror, and a second optical path passing through the Galvano mirrors and the attachment portion, and controls the deflection angle so that the deflection angle when switching to the first optical path has been performed and the deflection angle when switching to the second optical path has been performed do not overlap.

SYSTEMS AND METHODS FOR AUTOMATED TESTING OF POWER SUPPLY UNITS

An automated testing system for power supply units includes a frame, automated test equipment supported by the frame, a test jig supported by the frame and coupled with the automated test equipment, and a robotic arm coupled to the frame. The robotic arm is configured to move a power supply unit onto the test jig to interface with the automated test equipment. The automated test equipment is configured to perform one or more tests on the power supply unit when the power supply unit is interfaced with the automated test equipment, and the robotic arm is configured to move the power supply unit off of the test jig after the one or more tests are completed. Methods of performing automated testing for power supply units are also disclosed. 1. An automated testing system for power supply units , the system comprising:a frame;automated test equipment supported by the frame;a test jig supported by the frame and coupled with the automated test equipment; anda robotic arm coupled to the frame, the robotic arm configured to move a power supply unit onto the test jig to interface with the automated test equipment, the automated test equipment configured to perform one or more tests on the power supply unit when the power supply unit is interfaced with the automated test equipment, and the robotic arm configured to move the power supply unit off of the test jig after the one or more tests are completed.2. The automated testing system of claim 1 , wherein the test jig is a first test jig and the power supply unit is a first power supply unit claim 1 , the system further comprising a second test jig claim 1 , the robotic arm configured to move a second power supply unit to the second jig while the first power supply unit is interfaced with the automated test equipment claim 1 , the automated test equipment configured to perform the one or more tests on the second power supply unit after completing the one or more tests on the first power supply unit.3. The automated testing ...

On-wafer testing of photonic chips

A method for on-wafer testing of optical structures of photonic chips that include edge couplers as input/out ports includes defining, in test a test area of the wafer, an edge coupler pair formed of two edge couplers separated by a test gap, which may have a width that is close to the width of a chip-fiber gap during normal operation of the photonic chips. Test areas may include chains of different numbers of the edge coupler pairs for determining coupling loss per edge coupler.

ELECTRO-OPTICAL CIRCUIT BOARD FOR CONTACTING PHOTONIC INTEGRATED CIRCUITS

An electro-optical circuit board can provide probe card functionality. The electro-optical circuit board includes at least one electrical conductor track and at least one optical beam path. 1. A system , comprising: an electrical conductor track extending between first and second sides of the electro-optical circuit board; and', 'an optical beam path extending between the first and second sides of the electro-optical circuit board; and, 'an electro-optical circuit board, comprising a light source; and', 'a scanning device,, 'an optical testing device, comprising is the optical testing device is configured to drive the light source and the scanning device to emit a light beam to the electro-optical circuit board;', 'the electrical conductor track is configured to contact an electrical interface of a photonic integrated circuit adjacent the second side of the electrical conductor track; and', 'the optical beam path is configured to contact an optical interface of the photonic integrated circuit adjacent the second side of the electrical conductor track., 'wherein2. The system of claim 1 , wherein the optical testing device is configured to drive the scanning device to position the light beam with respect to a plurality of optical coupling points on the first side of the electro-optical circuit board.3. The system of claim 1 , wherein the optical testing device is configured to drive the scanning device to positioning the light beam within an optical coupling point on the first side of the electro-optical circuit board.4. The system of claim 3 , wherein the optical testing device is configured to drive the scanning device to position the light beam within the optical coupling point with a search pattern.5. The system of claim 1 , wherein the optical beam path has an aperture that is larger than a cross section of the light beam.6. The system of claim 1 , wherein the scanning device further comprises at least one member selected from the group consisting of a moveable ...

AUTOMATIC CIRCUIT BOARD TEST SYSTEM AND AUTOMATIC CIRCUIT BOARD TEST METHOD APPLIED THEREIN

An automatic circuit board test system includes at least one switch module of board under test connected with a test board, a control module and a test process module. The test board includes a first signal interface, a second signal interface and a third signal interface and a repeater. The second signal interface and the third signal interface are mutually connected by a signal cable. The first signal interface is connected with the repeater. The at least one switch module of board under test is connected with the second signal interface and the third signal interface. The control module is connected with the at least one switch module of board under test. The control module controls the at least one switch module of board under test. The test process module is connected with the control module and the first signal interface by at least two serial port buses. 1. An automatic circuit board test system , comprising:at least one switch module of board under test connected with a test board, the test board including a first signal interface, a second signal interface and a third signal interface and a repeater, the second signal interface and the third signal interface being mutually connected by a signal cable, the first signal interface being connected with the repeater, the at least one switch module of board under test being connected with the second signal interface and the third signal interface, respectively, the at least one switch module of board under test including a plurality of relays;a control module connected with the at least one switch module of board under test by a control interface bus, the control module controlling the at least one switch module of board under test; anda test process module for receiving encryption result data tested by the test board, the test process module being connected with the control module and the first signal interface, respectively by at least two serial port buses,wherein the test process module transmits a control ...

ANTENNA-IN-PACKAGE PRODUCTION TEST

A test assembly for testing an antenna-in-package (AiP) device includes a socket over a circuit board, where the socket includes an opening for receiving the AiP device; a plunger configured to move along sidewalls of the opening, where during testing of the AiP device, the plunger is configured to cause the AiP device to be pressed towards the circuit board such that the AiP device is operatively coupled to the circuit board via input/output connections of the AiP device and of the circuit board; and a loadboard disposed within the socket and between the plunger and the AiP device, where the loadboard includes a coupling structure configured to be electromagnetically coupled to a transmit antenna and to a receive antenna of the AiP device, so that testing signals transmitted by the transmit antenna are conveyed to the receive antenna externally relative to the AiP device through the coupling structure. 1. A test assembly for testing an antenna-in-package (AiP) device , the test assembly comprising:a socket over a first surface of a circuit board, wherein the socket comprises an opening for receiving the AiP device during testing of the AiP device;a plunger configured to move along sidewalls of the opening of the socket, wherein during the testing of the AiP device, the plunger is configured to cause the AiP device to be pressed towards the circuit board such that the AiP device is operatively coupled to the circuit board via input/output (I/O) connections of the AiP device and of the circuit board; anda loadboard disposed within the socket and between the plunger and the AiP device, wherein the loadboard comprises a coupling structure configured to be electromagnetically coupled to a transmit antenna of the AiP device and to a receive antenna of the AiP device, so that testing signals transmitted by the transmit antenna of the AiP device are conveyed to the receive antenna of the AiP device externally relative to the AiP device through the coupling structure.2. The ...

METHOD AND DEVICE FOR TESTING AT A SPECIFIC CHANNEL CONDITION

A method for testing a device under test at a specific channel condition is provided. The method comprises the steps of initiating a communication with the device under test and receiving a transmission frame from the device under test with a header portion comprising a specific transmission rate information. It also comprises analyzing the header portion of the transmission frame in order to determine whether the device under test is transmitting with the specific transmission rate information. 1. A method for testing a device under test at a specific channel condition comprising the steps of:initiating a communication with the device under test,receiving a transmission frame from the device under test with a header portion comprising a specific transmission rate information, andanalyzing the header portion of the transmission frame in order to determine whether the device under test is transmitting with the specific transmission rate information.2. The method according to claim 1 ,wherein the method further comprises the step of processing the transmission frame if the header portion comprises the specific transmission rate information.3. The method according to claim 1 ,wherein the method further comprises the step of cancelling the reception of the transmission frame if the device under test is not transmitting with the specific transmission rate information.4. The method according to claim 1 ,wherein the method further comprises the step of withholding the processing of the transmission frame if the header portion does not comprise the specific transmission rate information.5. The method according to claim 1 ,wherein the specific transmission rate information comprises information regarding a selective modulation or coding scheme or bandwidth or the number of spatial streams or a combination thereof.6. The method according to claim 1 ,wherein the method further comprises the step of receiving the transmission rate information from the device under test during ...

Metrology Apparatus and Method for Determining a Characteristic of One or More Structures On a Substrate

Disclosed is a method for obtaining a computationally determined interference electric field describing scattering of radiation by a pair of structures comprising a first structure and a second structure on a substrate. The method comprises determining a first electric field relating to first radiation scattered by the first structure; determining a second electric field relating to second radiation scattered by the second structure; and computationally determining the interference of the first electric field and second electric field, to obtain a computationally determined interference electric field. 115.-. (canceled)16. A method for obtaining a computationally determined interference electric field describing scattering of radiation by a pair of structures comprising a first structure and a second structure on a substrate , the method comprising:determining a first electric field relating to first radiation scattered by the first structure;determining a second electric field relating to second radiation scattered by the second structure; andcomputationally determining the interference of the first electric field and second electric field, to obtain a computationally determined interference electric field.17. The method of claim 16 , wherein:the computationally determining comprises combining the first electric field and second electric field, andthe combining the first electric field and second electric field comprises summing the first electric field and second electric field.18. The method of claim 16 , wherein the computationally determining comprises modeling their interference using a scattering model or an inverse scattering model of the first electric field and second electric field.19. The method of claim 16 , wherein the method comprises:performing intensity measurements of the first radiation and second radiation; anddetermining phase information relating to the first radiation and second radiation,wherein the phase information comprises at least the ...

DEFECT ISOLATION METHODS AND SYSTEMS

A test system and method for testing integrated circuits with improved defect localization is disclosed. A laser is used to perturb a device under test (DUT) at a test location. A tester tests the DUT with a test pattern and compares test results with compare vectors in a prior failure log. When a failure signature is matched, a failure signal is generated, indicating that the test location is a failed location. Comparing the test results with the compare vectors in the prior failure log and generating the failure signal when the failure signature is detected reduces artifacts from testing, shortening debug turnaround time. 1. A test system for testing devices comprising:a scanning microscope module, the scanning microscope module, when testing a device under test (DUT), is configured to perturb the DUT with a laser at a test (pixel) location; and a test unit,', 'a reference failure log containing prior failing compare vectors of interest,', a first in first out storage logic for storing the failing compare vectors of the reference failure log, and', 'a comparator logic for comparing the failing compare vectors with the test result vectors from the tester unit, the comparator logic generates the failure signal if the test result matches a prior failure signature, and, 'a comparator unit, wherein the comparator unit comprises'}, perform a test run at the test location of the DUT with a test pattern,', 'compare test result vectors of the test run with the prior failing compare vectors of interest in the reference failure log by the comparator unit, and', 'generate a comparator trigger pulse if failing test vectors match a prior failure signature, the trigger pulse indicates that the test location of the DUT is a failed location., 'wherein the test unit is configured to'}], 'a test module, the test module comprises'}2. The test system of wherein the scanning microscope module comprises:a stage for mounting the DUT when testing the DUT;a laser source unit for generating ...

Non-contact test system

Electronic device structures such as structures containing antennas, connectors, welds, electronic device components, conductive housing structures, and other structures can be tested for faults using a non-contact test system. The test system may include a vector network analyzer or other test unit that generates radio-frequency tests signals in a range of frequencies. The radio-frequency test signals may be transmitted to electronic device structures under test using an antenna probe that has one or more test antennas. The antenna probe may receive corresponding radio-frequency signals. The transmitted and received radio-frequency test signals may be analyzed to determine whether the electronic device structures under test contain a fault.

CROSSTALK SUPPRESSION IN WIRELESS TESTING OF SEMICONDUCTOR DEVICES

An integrated circuit is fabricated on a semiconductor material die and adapted to be at least partly tested wirelessly. Circuitry for setting a selected radio communication frequency to be used for the wireless test of the integrated circuit is integrated on the semiconductor material die. 1. An apparatus , comprising:a wireless probe card having a plurality of wireless units, the plurality of wireless units including at least a first wireless unit and a second wireless unit;wherein the first wireless unit is configured to wirelessly communicate with a first integrated circuit die from among a plurality of integrated circuit dies under test at a first frequency, the first integrated circuit die being integrated within a single wafer and including a radio frequency selector configured to select the first frequency for use by the first integrated circuit die from among a plurality of radio frequencies,wherein the second wireless unit is configured to wirelessly communicate with a second integrated circuit die from among the plurality of integrated circuit dies under test at a second frequency different than the first frequency, the second integrated circuit die being integrated within the single wafer and including a radio frequency selector configured to select the second frequency for use by the second integrated circuit die from among the plurality of radio frequencies.2. The apparatus of claim 1 , wherein the plurality of wireless units further includes a third wireless unit; wherein the third wireless unit is configured to wireless communicate with a third integrated circuit die from among the plurality of integrated circuit dies under test at a third frequency different than the second frequency claim 1 , the third integrated circuit die being integrated within the single wafer and including a radio frequency selector configured to select the third frequency for use by the third integrated circuit die from among the plurality of radio frequencies.3. The ...

MICROELECTROMECHANICAL SYSTEMS SENSOR TESTING DEVICE, SYSTEM AND METHOD

A microelectromechanical system (MEMS) sensor testing device, system and method are provided. The testing device includes a socket having a plurality of pads configured to receive a respective plurality of pins of the MEMS sensor, a body having a plurality of operable positions associated with a respective plurality of orientations of the MEMS sensor and circuitry which performs a method for testing the MEMS sensor in the plurality of operable positions. The method includes, for each position of the plurality of operable positions, outputting an indication of the position to the plurality of operable positions, receiving one or more measurements made by the MEMS sensor at the respective position and determining whether the one or more measurements satisfy a reliability criterion. The method includes generating a report based on the plurality of measurements and indicating whether the plurality of measurements satisfy a plurality of reliability criteria, respectively. 1. A device , comprising:a socket configured to be coupled to a microelectromechanical system (MEMS) sensor;a body having a plurality of operable positions associated with a respective plurality of orientations of the MEMS sensor; and [ outputting an indication of the position to the plurality of operable positions;', 'receiving one or more measurements made by the MEMS sensor at the respective position of the plurality of operable positions; and', 'determining whether the one or more measurements satisfy a reliability criterion of a plurality of reliability criteria;, 'for each position of the plurality of operable positions, 'generating a report based on the plurality of measurements and indicating whether the plurality of measurements satisfy the plurality of reliability criteria, respectively; and', 'outputting the report., 'circuitry which, in operation, performs a method for testing the MEMS sensor in the plurality of operable positions, the method including2. The device of claim 1 , wherein the ...

SYSTEM AND METHOD FOR OPTICAL INSPECTION OF ELECTRONIC CIRCUITS

An optical inspection system for an electronic circuit comprises sensors of images of the electronic circuit, at least two supports on which are intended to rest two parts of the electronic circuit and a device for modifying the position of each support, independently of one another. 1. An optical inspection system for an electronic circuit comprising sensors of images of the electronic circuit , at least two supports having two portions of the electronic circuit intended to rest thereon , and a device for modifying the position of each support , independently from each other.2. The system of claim 1 , wherein the electronic circuit comprises a printed circuit claim 1 , each support being intended to support a lateral edge of the printed circuit.3. The system of claim 1 , comprising a first conveyor capable of transporting the electronic circuit along a first direction claim 1 , the supports extending parallel to the first direction.4. The system of claim 3 , comprising a second conveyor capable of transporting the image sensors along a second direction claim 3 , non-parallel to the first direction claim 3 , and claim 3 , particularly claim 3 , perpendicular to the first direction.5. The system of claim 4 , wherein the device is capable of displacing each support claim 4 , independently from each other claim 4 , along a third direction claim 4 , non-parallel to the first and second directions claim 4 , and claim 4 , particularly claim 4 , perpendicular to the first and second directions.6. The system of claim 1 , comprising a device for locking the portions of the electronic circuit on the supports.7. A method of optical inspection of an electronic circuit claim 1 , at least two portions of the electronic circuit resting on two supports claim 1 , the method comprising successive acquisitions of images of the electronic circuit by image sensors and the modification of the position of each support claim 1 , independently from each other claim 1 , between successive ...

Capacitive opens testing of low profile components

A probe assembly for capacitive testing electrical connections of a low profile component to a circuit assembly. The probe assembly is configured to reduce coupling of noise signals from the circuit assembly to the capacitive probe. The probe assembly includes a sensing member with a geometry that allows the probe to preferentially couple to test signals from the pins of a component under test rather than conductive structures on the circuit assembly, such as pads, and signal traces to which those pins are attached. The sensing member may be a vertical capacitive sense plate such that coupling is to an edge of the plate. The sensing member alternatively may be a horizontal capacitive sense plate with an active area of the probe surrounded by an isolation ring. Measurements made with such capacitive probes may provide test measurements that yield a reliable discrimination between a properly attached pin and an open pin.

PUMP AND PROBE TYPE SECOND HARMONIC GENERATION METROLOGY

Various approaches to can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. 1107.-. (canceled)108. An optical interrogation apparatus comprising:a pump optical source configured to emit pumping radiation to be directed onto a semiconductor wafer;a probe optical source configured to emit probing radiation with variable energy to be directed onto said wafer;an optical detector configured to detect a Second Harmonic Generation (SHG) effect signal at a first location and a second location generated by at least one of the pumping radiation and the probing radiation; and cause the probe optical source to provide probing radiation to a first location on the wafer;', 'cause raster scanning of the probing radiation or the wafer to cause the probe optical source to provide providing probing radiation to a second location on the wafer; and', 'to detect a region where the SHG effect signal changes when the wavelength of the pumping radiation is varied to determine a threshold injection carrier energy., 'electronics configured to109. The optical interrogation apparatus of claim 108 , wherein the pumping radiation has an average optical power greater than about 100 mW.110. The optical interrogation apparatus of claim 108 , wherein the pumping radiation has an average optical power less than about 10 W.111. The optical interrogation apparatus of claim 108 , wherein the pumping radiation has a wavelength between about 80 nm and about 1000 nm.112. The optical interrogation apparatus of claim 108 , wherein the probing radiation has an average optical power less than about 150 mW.113. The optical interrogation apparatus of claim 108 , wherein the probing radiation has a peak optical power greater than about 10 kW.114. The ...

PROBE CARD

A probe card for detecting a wafer. The probe card includes a light-output element, which is connected to a positioning element. The light-output element is set within a through hole of an electrical detection substrate. The light-output element is connected to a light source controller by an optical fiber, thereby an output light can be transmitted from the light source controller to the light-output element. The positioning element can move the light-output element in three-dimensional space or adjust an emitting angle from an axis of the light-output element. Therefore, an optical measurement and an electrical measurement can be implemented at the same time in the silicon photonic wafer test. 1. A probe card for detecting a wafer , comprising:an electrical detection substrate with a through hole, wherein the electrical detection substrate is used to perform an electrical measurement;a light-output element set within the through hole;a positioning element configured to drive the light-output element to move in three-dimensional space or to adjust an emitting angle deviated from an axis of the light-output element; anda light source controller connected to the light-output element by an optical fiber to provide an output light.2. The probe card of claim 1 , wherein the positioning element is connected to the light-output element and the electrical detection substrate.3. The probe card of claim 1 , further comprising a platform to receive the electrical detection substrate.4. The probe card of claim 3 , wherein the positioning element is connected to the light-output element and the electrical detection substrate.5. The probe card of claim 3 , wherein the positioning element is connected to the light-output element and the platform.6. The probe card of claim 1 , further comprising a Z-axis displacement sensing element claim 1 , wherein the Z-axis displacement sensing element is set within the through hole to sense a distance between the light output element and the ...

OPTIMIZED WAVELENGTH PHOTON EMISSION MICROSCOPE FOR VLSI DEVICES

A method for emission testing of a semiconductor device (DUT), by mounting the DUT onto an test bench of an emission tester, the emission tester having an optical detector; electrically connecting the DUT to an electrical tester; applying electrical test signals to the DUT while keeping test parameters constant; inserting an optical filters into an optical path of the emission tester and collecting emission test signal from the optical detector; removing the filter from the optical path and collecting emission test signal from the optical detector. Comparing the images obtained with and without the filter. The filter may be shortpass to obtain emission signal, a bandpass for detecting forward bias, or longpass to obtain thermal signal. 1. A method for testing an integrated circuit (DUT) , comprising:placing the DUT on a tester having an optical arrangement defining an optical path and having an imager;inserting into the optical path an optical filter configured to block light beyond a defined cut-off wavelength from reaching the imager;imaging photon emission from the DUT through the optical filter;removing the optical filter from the optical path and imaging photon emission from the DUT without the optical filter;comparing the imaging with and without the optical filter so as to identify a specific failure type of elements within the DUT.2. The method of claim 1 , wherein the optical filter comprises a bandpass filter centered at 1150 nm claim 1 , with a bandwidth of 300 nm.3. The method of claim 1 , wherein the optical filter comprises a shortpass filter having cut-off selected from: 1300 nm claim 1 , 1550 nm claim 1 , 1800 nm claim 1 , 1900 claim 1 , and 2000 nm.4. The method of claim 1 , wherein said optical filter comprises shortpass having cutoff at 1550 nm.5. The method of claim 1 , wherein said imager has a low wavelength cut-on at 900 nm.6. The method of claim 1 , further comprising inserting a cold aperture into the optical path.7. The method of claim 6 , ...

THREE-DIMENSIONAL MEASUREMENT APPARATUS AND THREE-DIMENSIONAL MEASUREMENT METHOD

A three-dimensional measurement apparatus measures measurement targets placed in a target measurement area on a measurement object. The apparatus includes: a measurement module that: is positioned with respect to the target measurement area, and includes: a first irradiator that irradiates the target measurement area with predetermined light for height measurement; a second irradiator that irradiates the target measurement area with predetermined patterned light for three-dimensional measurement; and an imaging device that takes an image of the target measurement area; and a control device that moves the measurement module in a height direction and successively positions the measurement module at a predetermined height position determined by mapping, and performs, based on image data taken by irradiating the target measurement area with predetermined patterned light, three-dimensional measurement to the measurement targets at the predetermined height position.

Electrical Inspection of Electronic Devices Using Electron-Beam Induced Plasma Probes

A non-mechanical contact signal measurement apparatus includes a first conductor on a structure under test and a gas in contact with the first conductor. At least one electron beam is directed into the gas so as to induce a plasma in the gas where the electron beam passes through the gas. A second conductor is in electrical contact with the plasma. A signal source is coupled to an electrical measurement device through the first conductor, the plasma, and the second conductor when the plasma is directed on the first conductor. The electrical measurement device is responsive to the signal source.

METHOD OF INSPECTING A LEAD OF AN ELECTRIC DEVICE

A method of inspecting leads of an electric device, which is capable of improve reliability of inspection regardless of noises induced by regions near the lead. The method uses a height or a brightness of a shoulder region of the lead to inspect existence or nonexistence or a height or a brightness of a tip region of the lead to inspect fastening or unfastening. Therefore, reliability of inspection is improved in comparison with a conventional inspection using colors of lead region. 1. A method of inspecting leads of an electric device , through which the electric device is mounted on a printed circuit board , the method comprising:capturing images of lead regions of the electric device;measuring heights of interest regions of leads in the image; anddetermining whether each lead is existent or nonexistent by comparing heights of interest regions.2. The method of claim 1 , wherein determining whether each lead is existent or nonexistent comprises:calculating average of heights of interest regions of leads;comparing each of the heights of the interest regions of leads with the average; anddetermining whether each of the heights of the interest regions is within a maximum permission tolerance in comparison with the average.3. The method of claim 2 , wherein each of the interest regions is a shoulder region of a lead.4. A method of inspecting leads of an electric device claim 2 , through which the electric device is mounted on a printed circuit board claim 2 , the method comprising:capturing an image of a lead region of the electric device;measuring height of interest region of the lead in the image; anddetermining existence and nonexistence or fastening and unfastening of the lead by determining whether heights of the interest regions are within a previously set reference height by comparing each of the heights of interest regions of leads with the previously set reference height.5. The method of claim 4 , wherein the reference height is set between minimum permission ...

SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PERFORMING COMPREHENSIVE FUNCTIONAL AND DIAGNOSTIC CIRCUIT CARD ASSEMBLY (CCA) TESTING

The system includes an integrated sequenced arrangement of parametric type instruments, automated guided prober test instruments, and a test instrument system using analog signature analysis for identifying faults in circuit card assemblies, under control of a software system with a mass interconnect system. 1. An integrated system for testing the function of circuit card assemblies , comprising:one or more parametric type test instruments providing stimulus signals and obtaining measurements to identify circuit areas containing possible faults;one or more guided prober test instruments to test circuit areas identified by the parametric testing and/or an analog signature analysis system test instrument for the unit under test to identify faults in the circuit areas identified by the parametric testing and/or the guided prober test instruments;an interface system for connecting the test instruments to the circuit card assembly under test; anda software system for controlling and integrating the operation of the parametric type instruments, the guided probers and the analog signature analysis to produce a diagnostic test result.2. A system of claim 1 , wherein the interface system is a mass interconnect system.3. A system of claim 1 , wherein the parametric test instruments connect to the circuit card assembly under test by an edge connector.4. A system of claim 1 , wherein the software system includes test executive software for controlling the sequence of operation of the parametric test instruments relative to the circuit card under test claim 1 , software for controlling the guided prober and software for controlling the analog signature analysis test instrument.5. A system of claim 1 , wherein the parametric test instruments test each system of the credit card assembly.6. The system of claim 1 , wherein the mass interconnect system includes a test adaptor assembly integrated therewith.7. The system of claim 1 , wherein the mass interconnect system includes a test ...

SYSTEM AND METHOD FOR THE POSITIONING AND OPTICAL INSPECTION OF AN OBJECT

The invention concerns a method of optical, inspection of an electronic circuit (Card) including the acquisition of images of the electronic circuit by image sensors (C), the use of the images to determine the offset between the position of the electronic circuit (Card) and an inspection position, and the use of said images in at least another step of the method. 1. A method of optical inspection of an electronic circuit comprising the acquisition of images of the electronic circuit by image sensors , the use of the images to determine the offset between the position of the electronic circuit and an inspection position comprising comparing , for each image sensor among some of the image sensors , the image acquired by the image sensor with at least one reference image of the electronic circuit and the use of said images in at least another step of the method.2. The method of claim 1 , comprising modifying the position of the electronic circuit when said offset is greater than a threshold.3. The method of claim 1 , comprising comparing claim 1 , for each image sensor among some of the image sensors claim 1 , the acquired image with at least one additional reference image obtained from the reference image.4. The method of claim 3 , comprising comparing claim 3 , for each image sensor among some of the image sensors claim 3 , the image acquired by the image sensor with a first reference image and with a second reference image obtained by blurring of the first reference image.5. The method of claim 4 , comprising comparing claim 4 , for each image sensor among some of the image sensors claim 4 , the image acquired by the image sensor with a third reference image obtained by extraction of contours of the first reference image.6. The method of claim 5 , comprising comparing claim 5 , for each image sensor among some of the image sensors claim 5 , the image acquired by the image sensor with a fourth reference image obtained by blurring of the third reference image.7. The ...

FIELD-BIASED NONLINEAR OPTICAL METROLOGY USING CORONA DISCHARGE SOURCE

Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation while other utilize four wave-mixing or multi-wave mixing. Corona discharge may be applied to the sample to provide additional information. Some approaches involve determining current flow from a sample illuminated with radiation. 1. A method of optical interrogation of a sample having a top side and a bottom side , the method comprising:applying probing radiation from a probing optical source to a surface of the sample;depositing different amounts of electrical charge to the top side of the sample using a corona gun;detecting using an optical detector, a Second Harmonic Generation (SHG) effect signal generated by the probing radiation for different amounts of electrical charge deposited on the top side of the sample; anddetermining a characteristic of the variation of the detected SHG effect signal for the different amounts of electrical charge deposited on the top side of the sample.2. The method of claim 1 , used to determine interfacial charging states at corresponding band bending of the sample as a function of surface charge.3. The method of claim 1 , further comprising:applying pumping radiation from a pumping optical source to the surface of the sample;detecting a SHG effect signal generated by at least one of the pumping radiation and the probing radiation using an optical detector; anddetermining a characteristic of the detected SHG effect signal in the presence of said charge and the pumping radiation.4. The method of claim 3 , used to determine carrier dynamics at corresponding band bending of the sample as a function of surface charge.5. (canceled)6. The method of claim 1 , further comprising determining the different amounts of electrical charge deposited on the top side of the sample.7. (canceled)8. (canceled)9. (canceled)10. A system for optically interrogating a ...

OVER-THE-AIR MEASUREMENT SYSTEM

An over-the-air measurement system for performing over-the-air measurements on a device under test is described. The measurement system comprises a measurement device having several measurement antennas, several waveguides, wherein at least one waveguide is assigned to each measurement antenna, several waveguide-to-cable adapters, and a positioning unit assigned to the measurement antennas. The number of the waveguide-to-cable adapters is at least identical to the number of the measurement antennas. The positioning unit is configured to move the measurement antennas with respect to the waveguide-to-cable adapters. 1. An over-the-air measurement system for performing over-the-air measurements on a device under test , said measurement system comprising a measurement device , said measurement device further comprising:several measurement antennas;several waveguides, wherein at least one waveguide is assigned to each measurement antenna;several waveguide-to-cable adapters; anda positioning unit assigned to said measurement antennas,wherein the number of said waveguide-to-cable adapters is at least identical to the number of said measurement antennas, andwherein said positioning unit is configured to move said measurement antennas with respect to said waveguide-to-cable adapters.2. The over-the-air measurement system according to claim 1 , wherein said positioning unit is configured to move all measurement antennas simultaneously such that claim 1 , in an operation position claim 1 , one of said measurement antennas is connected via said at least one waveguide with at least one of said waveguide-to-cable adapters assigned to said respective measurement antenna.3. The over-the-air measurement system according to claim 1 , wherein said waveguide-to-cable adapters are stationary whereas said measurement antennas are movable.4. The over-the-air measurement system according to claim 1 , wherein said measurement antennas are fixedly attached to a main body that is moved by ...

CREATING TIME-RESOLVED EMISSION IMAGES OF INTEGRATED CIRCUITS USING A SINGLE-POINT SINGLE-PHOTON DETECTOR AND A SCANNING SYSTEM

A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to update the time-dependent map of the emissions based on combinations of the emissions of light at certain locations. 1. A method of improving time-resolved emission (TRE) waveforms representing an electronic device , wherein the TRE waveforms represent photons detected by a photodetector at respective scan locations on the electronic device , the method comprising:obtaining a list of the scan locations, wherein each scan location corresponds to a pixel of interest;constructing a first waveform for an initial one of the scan locations, wherein the first waveform represents a measurement of the photons detected by the photodetector at the initial one of the scan locations;constructing a second waveform by combining a measurement of the photons detected at a subsequent location in the list of scan locations and those used in constructing the first waveform; andadvancing to a next location in the list of scan locations and updating the first waveform to be equal to the second waveform upon determining that a signal-to-noise ratio of the first waveform is less than or equal to a signal-to-noise ratio of the second waveform.2. The method of claim 1 , further comprising updating a pseudo image of the electronic device generated from the TRE waveforms claim 1 , wherein the pseudo image includes the pixel of interest claim 1 , which has at ...

SCANNING METHODS FOR CREATING TIME-RESOLVED EMISSION IMAGES OF INTEGRATED CIRCUITS USING A SINGLE-POINT SINGLE-PHOTON DETECTOR AND A SCANNING SYSTEM

A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. Updating the time-dependent map of the emissions based on variable dwell times at respective locations of the DUT. 1. A method of scanning an integrated circuit using single-point single photon detector , the method comprising:obtaining a list of scan locations;initializing an image acquisition with an initial acquisition time determined for each location;scanning each location using an initial dwell time to acquire a respective signal for each location, wherein, during the initial dwell time the method further comprises changing the initial dwell time for at least a first location of the scan locations; andgenerating an image of the integrated circuit using emissions of the integrated circuit emitted during the scanning.2. The method of claim 1 , wherein the initial dwell time is extended upon determining that the first location corresponds to a location of interest.3. The method of claim 2 , further comprising detecting the first location based on a layout of the integrated circuit.4. The method of claim 1 , wherein the initial dwell time is extended upon determining that an emission of the location exceeds a threshold for total intensity.5. The method of claim 1 , wherein the initial dwell time is extended upon performing a time-windowed analysis on an emission of the location.6. The method of claim 1 , wherein the initial dwell time is extended upon performing a ...

TEST ARRANGEMENT AND TEST METHOD

Summarizing, the present invention relates to a test arrangement in the test method for acquiring test data in the surrounding of a device under test. At least two measurement devices are arranged in the surrounding of the device under test, wherein the two measurement devices are communicatively coupled for phase locking. At least one of the measurement devices can be moved around the device under test for acquiring measurement data, wherein the measurement devices comprise a measurement antenna and the vectorial measurement receiver. Accordingly, during the measurements, the at least one vectorial measurement receiver is moved around together with the measurement antenna, wherein the spatial relationship between the measurement antenna and the vectorial measurement receiver is remained constant during the movement. 1. A test arrangement for testing a device under test , the test arrangement comprising:a first measurement device comprising a first measurement antenna for measuring first signals emitted by the device under test and a first vectorial measurement receiver for vectorially analysing the measured first signals;a second measurement device comprising a second measurement antenna for measuring second signals emitted by the antenna under test and a second vectorial measurement receiver for vectorially analysing the measured second signals, wherein the second measurement device is communicatively coupled to the first measurement device for exchanging phase information or phase synchronisation or phase locking; anda mechanical positioning structure that carries the first measurement device and controllably moves the first measurement antenna and the first vectorial measurement receiver of the first measurement device around the device under test.2. The test arrangement of claim 1 , wherein the spatial alignment between the first measurement antenna and the first vectorial measurement receiver of the first measurement device remains constant when the first ...

DETECTOR DEVICE FOR FUNCTIONAL CERTIFICATION

A detector device for functional certification includes a probe, a waveguide and a first micro-antenna. The probe includes a tip portion and a through-portion, wherein an end of the through-portion penetrates a first surface of the probe to form a first opening, and an opposite end of the through-portion penetrates the tip portion to form a second opening. The waveguide is disposed in the through-portion. The first micro-antenna is installed in the second opening and electrically connected with the waveguide. 1. A detector device for functional certification comprising:a probe including a tip portion and a through-portion, wherein an end of the through-portion penetrates a first surface of the probe to form a first opening, and an opposite end of the through-portion penetrates the tip portion to form a second opening;a waveguide disposed in the through-portion; anda first micro-antenna installed in the second opening and electrically connected with the waveguide.2. The detector device according to claim 1 , wherein the first micro-antenna is a horn micro-antenna.3. The detector device according to claim 2 , wherein the probe further includes a second surface claim 2 , wherein the first surface has a first edge and a second edge opposite to the first edge claim 2 , the second surface has the second edge and a third edge opposite to the second edge claim 2 , wherein the first edge is longer than the second edge claim 2 , the second edge is longer than the third edge.4. The detector device according to claim 3 , wherein the probe further includes a third surface and a fourth surface claim 3 , wherein the third surface and the second surface jointly have the third edge claim 3 , and the third surface and the fourth surface jointly have the a fourth edge opposite to the third edge claim 3 , wherein the first surface and the fourth surface have the same extending direction claim 3 , and the third surface and the fourth surface are corporately formed as the tip portion.5. ...

Method and Apparatus for Detection of Counterfeit, Defective or Damaged Devices

Methods and apparatus are provided for determining if an embedded system or integrated circuit is operating correctly, or if the device is faulty or counterfeit. Measurements of power consumption are used to determine the state of the device under test, these measurements being performed at multiple operating or environmental conditions to increase the ability of the apparatus to detect faulty and counterfeit devices. 1. Apparatus for determining if a device under test (DUT) is , or includes , a counterfeit , damaged or defective device , the apparatus including a computer-readable medium on which are stored program instructions that , when executed by one or more processors ,configure the DUT to perform a signature operation under at least a first environmental condition;generate a first dataset indicative of at least a first signature of the DUT during the performance of the signature operation under the at least first environmental condition;configure the DUT to perform the signature operation under at least a second environmental condition;generating a second dataset indicative of at least a second signature of the DUT during the performance of the signature operation under the at least second environmental condition;compare the first and second datasets to first and second reference datasets, respectively, the first and second reference datasets being indicative of the signature of a known-good device performing the signature operation under the at least first and second environmental conditions, respectively; andgenerate a signal designating the DUT as being potentially defective or counterfeit in response to there being predetermined differences between at least one of a) the first dataset and the first reference dataset and b) the second dataset and the second reference dataset.2. The apparatus of wherein the first and second datasets are samples of the at least first signature generated at a sample rate that is sufficient to ensure that said predetermined ...

Current sensor and method for sensing a strength of an electric current

Examples relate to a current sensor and to a method for sensing a strength of an electric current using two groups of magnetic sensing probes. The current sensor includes a first group and a second group of magnetic sensing probes. The current sensor comprises sensor circuitry coupled to the first and the second group of magnetic sensing probes. The sensor circuitry is configured to determine a first differential magnetic field measurement of a magnetic field using probes of the first group of magnetic sensing probes. The sensor circuitry is configured to determine a second differential magnetic field measurement of the magnetic field using probes of the second group of magnetic sensing probes. The sensor circuitry is configured to determine a strength of the electric current based on a difference between the first differential magnetic field measurement and the second differential magnetic field measurement.

INSPECTION TOOL AND METHODOLOGY FOR THREE DIMENSIONAL VOLTAGE CONTRAST INSPECTION

A system and method for improved voltage contrast inspection is disclosed. In one embodiment the temporal response to voltage contrast is considered to find an optimal acquisition time. In another embodiment, multiple optimal acquisition times are identified. The identified acquisition times are used in voltage contrast inspection of semiconductor fabrication, and are well-suited to SOI technology. 112-. (canceled)13. A system for performing voltage contrast inspection , comprising:an electron microscope, the electron microscope configured and disposed to acquire a plurality of voltage contrast images, each voltage contrast image corresponding to a different acquisition time;an image analysis module, the image analysis module comprising a central processing unit, and non-transistory storage containing instructions that when executed, computes a number of defect counts in each voltage contrast image, thereby establishing a number of defect counts corresponding to each acquisition time, and subsequently generates a voltage contrast inspection configuration.14. The system of claim 13 , further comprising an image compression module claim 13 , the image compression module configured and disposed to receive a plurality of voltage contrast images from the electron microscope and perform image compression on the voltage contrast images claim 13 , thereby creating compressed voltage contrast images.15. The system of claim 14 , wherein the image compression module configured and disposed to perform MPEG compression on the voltage contrast images from the electron microscope.16. The system of claim 14 , wherein the image compression module configured and disposed to perform JPEG compression on the voltage contrast images from the electron microscope.17. A system for performing voltage contrast inspection claim 14 , comprising:a scanning electron microscope, the scanning electron microscope configured and disposed to acquire a plurality of uncompressed voltage contrast images ...

A TRANSMISSION LINE

A transmission line arrangement having a first end and a second end, the transmission line arrangement being configured to transmit a signal between the first end and the second end, the transmission line arrangement comprising a signal conductor extending between the first end and the second end of the transmission line arrangement, a first conducting sheet and a second conducting sheet positioned on two opposing sides of the signal conductor, an insulating material separating the first and second conducting sheets from the signal conductor and a plurality of pieces of conducting material extending between the first and second conducting sheets and arranged at different positions between the first and second ends of the transmission line arrangement, wherein the pieces of conducting material and the conducting sheets are arranged to substantially surround the signal conductor for at least part of its length between the first and second ends of the transmission line arrangement. 1. A transmission line arrangement having a first end and a second end , the transmission line arrangement being configured to transmit a signal between the first end and the second end , the transmission line arrangement comprising:a signal conductor extending between the first end and the second end of the transmission line arrangement;a first conducting sheet and a second conducting sheet positioned on two opposing sides of the signal conductor;an insulating material separating the first and second conducting sheets from the signal conductor; anda plurality of pieces of conducting material extending between the first and second conducting sheets and arranged at different positions between the first and second ends of the transmission line arrangement, wherein the pieces of conducting material and the conducting sheets are arranged to substantially surround the signal conductor for at least part of its length between the first and second ends of the transmission line arrangement.2. The ...

METHOD FOR IDENTIFYING PCB CORE-LAYER PROPERTIES

A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance. 1. A method comprising:locating a first reference via in a first set of plated vias on a printed circuit board;applying a reference lead to the first reference via;locating a first test via in the first set of plated vias;applying a test lead to the first test via;measuring a first electrical conductance between the first reference via and the first test via; andidentifying a first property of a first core layer of the printed circuit board based on the first electrical conductance.2. The method of claim 1 , further comprising:applying the test lead to a second test via in the set of plated vias; andmeasuring a second electrical conductance between the first reference via and the second test via.3. The method of claim 2 , wherein the identifying comprises:recording the first electrical conductance as a first value in a core lot code;recording the second electrical conductance as a second value in the core lot code; andcomparing the core lot code to a set of reference core lot codes.4. The method of claim 1 , further comprising:generating a core lot code that reflects the property of the core layer; andprinting the core lot code on the surface of the printed circuit board.5. The method of claim 1 , further comprising:applying the reference lead to a second reference via;applying the test lead to a second test via in the set of plated vias; andmeasuring a second electrical conductance between the second reference via and the second test via.6. The method of claim 1 , further comprising:locating a second reference via in a second set of plated vias on the printed ...

NON-DESTRUCTIVE DETERMINATION OF COMPONENTS OF INTEGRATED CIRCUITS

One or more contacts are detected in an electron microscope image corresponding to a region of interest on an integrated circuit. One or more standard cells are identified based on the detected one or more contacts in the electron microscope image. One or more components of the integrated circuit are determined based on the identified one or more standard cells. 1. A method , comprising:detecting one or more contacts in an electron microscope image corresponding to a region of interest on an integrated circuit;identifying one or more standard cells based on the detected one or more contacts in the electron microscope image; anddetermining one or more components of the integrated circuit based on the identified one or more standard cells;wherein the detecting, identifying and determining steps are performed by at least one processor coupled to a memory.2. The method of claim 1 , wherein the electron microscope image is a mosaic comprising a plurality of electron microscope images for the region of interest.3. The method of claim 2 , further comprising stitching the plurality of electron microscope images into the mosaic.4. The method of claim 3 , wherein stitching the plurality of electron microscope images comprises utilizing a feature detection algorithm.5. The method of claim 3 , further comprising rectifying the stitched mosaic.6. The method of claim 5 , wherein rectifying the stitched mosaic comprises aligning the images at least one of horizontally and vertically.7. The method of claim 1 , wherein detecting the one or more contacts comprises utilizing a Hough transform.8. The method of claim 1 , further comprising creating a contacts constellation for the region of interest based on the one or more detected contacts.9. The method of claim 8 , wherein the contacts constellation comprises the arrangement of the contacts in the region of interest.10. The method of claim 8 , further comprising creating one or more contact reference maps from a standard cell library ...

PHYSICAL LAYER DEVICE AND METHOD FOR PERFORMING PHYSICAL LAYER OPERATIONS IN A COMMUNICATIONS NETWORK

Embodiments of a method and a device are disclosed. In an embodiment, a method for performing physical layer operations at a network node in a communications network is disclosed. In an embodiment, the method involves identifying a fault status at the network node, embedding an indication of the fault status into a bit stream at the physical layer of the network node, and transmitting the bit stream from the network node. In an embodiment, embedding an indication of the fault status into a bit stream at the physical layer includes embedding an operations, administration, and management (OAM) word into the bit stream to communicate the indication of the fault status. 1. A method for performing physical layer operations at a network node in a communications network , the method comprising:identifying a fault status at the network node;embedding an indication of the fault status into a bit stream at the physical layer of the network node; andtransmitting the bit stream from the network node.2. The method of claim 1 , wherein embedding an indication of the fault status into a bit stream at the physical layer comprises embedding an operations claim 1 , administration claim 1 , and management (OAM) word into the bit stream to communicate the indication of the fault status.3. The method of claim 2 , wherein the OAM word is embedded into the bit stream at a physical coding sublayer transmitter (PCS-TX) of the network node.4. The method of claim 1 , wherein identifying a fault status at the network node comprises detecting a low voltage condition at the physical layer.5. The method of claim 1 , wherein identifying a fault status at the network node comprises detection an open/short circuit condition at the physical layer.6. The method of claim 1 , wherein identifying a fault status at the network node comprises performing a loop test at the network node.7. The method of claim 1 , wherein identifying a fault status at the network node comprises reading a register at the ...

RAPID ANALYSIS OF BUFFER LAYER THICKNESS FOR THIN FILM SOLAR CELLS

A method and apparatus for measuring thickness of a film in a solar cell provides for directing light emitted at multiple emission wavelengths, to a surface of the solar cell. Each emission results in the generation of a responsive photo current. The photo currents are read by a current meter having one contact coupled to a surface of the solar cell and another contact coupled to another surface. The currents associated with each of the different light emissions are identified and the thickness of a film in the solar cell is calculated based on the two currents or associated quantum efficiencies, and associated absorption coefficients. In one embodiment, the film thickness is the thickness of a CdS or other buffer film in a thin film solar cell. 1. A method for measuring thickness of a solar cell film , said method comprising:providing a solar cell that includes a buffer layer with a wavelength dependent absorption coefficient;generating light having a plurality of emission wavelengths;exposing said solar cell to at least two wavelengths of said light;measuring photovoltaic currents generated in said solar cell responsive to said exposing, for each of said wavelengths of said light;mathematically calculating thickness of said buffer layer based on said measured photovoltaic currents; anddelivering an output signal of said calculated thickness to a further device.2. The method as in claim 1 , wherein said buffer layer comprises CdS.3. The method as in claim 1 , wherein said mathematically calculating includes using a ratio of said measured photovoltaic currents and dividing said ratio by a difference in absorption coefficients associated with each of said at least two wavelengths of light claim 1 , to obtain said thickness.4. The method as in claim 1 , wherein said further device comprises a controller that displays said calculated thickness and communicates with a buffer layer deposition system.5. The method as in wherein said generating light comprises using a ...

Interposer testing device and method thereof

The disclosure provides an interposer testing device for testing an interposer and a method thereof which includes a heat source, a thermal image capturing device and a comparing device. The heat source is adapted for heating an area to be tested on the interposer. The thermal image capturing device is adapted for capturing a thermal image of the interposer after the interposer is heated. The comparing device is adapted for comparing the thermal image with a standard thermal image to output a comparison result.

Visible laser circuit fault isolation

A transparent coversheet intervenes between a lens and a thinned die in a visible light fault analysis tool so that the thinned die is robust to fractures. In addition, the transparent coversheet has a greater thermal mass than the thinned die and thus acts as a heat sink to prevent active circuitry in the thinned die from overheating during the visible light fault analysis.

Techniques for Testing PLP Capacitors

A solid state drive (SSD) with improved techniques for testing power loss protection (PLP) capacitors and a method for testing PLP capacitors of SSDs is disclosed. In one embodiment, the SSD includes a memory controller and one or more non-volatile memory devices and a volatile memory device coupled to the memory controller. The SSD also includes a PLP capacitor configured to supply a first voltage to the memory controller, the one or more non-volatile memory devices, and the volatile memory device in the event of a power loss or failure of the SSD. In one embodiment, the PLP capacitor is further configured to increase the first voltage to a second voltage prior to testing the PLP capacitor. In another embodiment, the memory controller is configured to reduce a volume of data stored in the volatile memory device prior to testing the PLP capacitor. 1. A solid state drive (SSD) comprising:a memory controller;one or more non-volatile memory devices communicatively coupled to the memory controller;a volatile memory device communicatively coupled to the memory controller; anda power loss protection (PLP) capacitor electrically coupled to the memory controller, the one or more non-volatile memory devices, and the volatile memory device, and configured to supply a first voltage to the memory controller, the one or more non-volatile memory devices, and the volatile memory device in the event of a power loss or failure of the SSD, whereinthe PLP capacitor is further configured to increase the first voltage to a second voltage prior to performing a test of an amount of energy stored by the PLP capacitor, the increase in voltage to the second voltage offsetting at least a part of an energy lost by the PLP capacitor during testing of the PLP capacitor.2. The SSD of claim 1 , wherein the test is a discharge test.3. The SSD of claim 1 , wherein the PLP capacitor is a de-rated capacitor.4. The SSD of claim 1 , wherein the PLP capacitor is restored to the first voltage after ...

PROBE-BASED DATA COLLECTION SYSTEM WITH ADAPTIVE MODE OF PROBING CONTROLLED BY LOCAL SAMPLE PROPERTIES

A method for testing an integrated circuit (IC) using a nanoprobe, by using a scanning electron microscope (SEM) to register the nanoprobe to an identified feature on the IC; navigating the nanoprobe to a region of interest; scanning the nanoprobe over the surface of the IC while reading data from the nanoprobe; when the data from the nanoprobe indicates that the nanoprobe traverse a feature of interest, decelerating the scanning speed of the nanoprobe and performing testing of the IC. The scanning can be done at a prescribed nanoprobe tip force, and during the step of decelerating the scanning speed, the method further includes increasing the nanoprobe tip force. 1. An apparatus for performing probing on an integrated circuits (IC) , comprising:a stage configured for supporting the IC and configured to enable connecting an IC tester to front side of the IC to conduct tests on the sample;a prober having a probe tip;an actuator activating the prober to position the probe tip at a region of interest (ROI) at a back side of the sample, wherein the probe tip is acting as an antenna which amplifies electro-magnetic (EM) field, thereby amplifying electro-optical emission from operating devices within the sample;collection optics positioned at the backside of the sample and collect photons in proximity to the probe tip;a controller collecting data signals from the collection optics synchronized with the prober position, and generating map of electro-optical emission over the IC.2. The apparatus of claim 1 , wherein the controller is further preprogrammed to read a CAD design data corresponding to the sample claim 1 , and to further control the actuating signals according to the CAD design data indicating dielectric regions and conductive regions.3. The apparatus of claim 1 , wherein the controller is further preprogrammed to register the prober to an image obtained by a scanning electron microscope outside of an area of interest.4. The apparatus of claim 1 , wherein the ...

TEST SYSTEMS AND METHODS FOR CHIPS IN WAFER SCALE PHOTONIC SYSTEMS

A qualification apparatus for a photonic chip on a wafer that leaves undisturbed an edge coupler that provides an operating port for the photonic devices or circuits on the chip during normal operation in order to not introduce extra loss in the optical path of the final circuit. The qualification apparatus provides an optical path that is angled with regard to the surface of the chip, for example by using a grating coupler. The qualification apparatus can be removed after the chip is qualified. Optionally, the qualification apparatus can be left in communication with the chip and optionally employed as an input port for the chip after the chip has been separated from other chips on a common substrate. 1. A qualification apparatus for a photonic chip on a substrate , comprising:a wafer having constructed thereon at least one photonic chip, said photonic chip comprising a circuit having an operating port configured to be used during normal operation of said photonic chip, said photonic chip configured to be separated from other photonic chips on said wafer;said wafer having constructed thereon a test port comprising a grating coupler in optical communication with said circuit, said grating coupler configured to interact with optical radiation that propagates at an angle to a free surface of said wafer, said grating coupler configured to be used during a qualification test of said photonic chip which is conducted prior to said photonic chip being separated from other photonic chips on said wafer.2. The qualification apparatus for a photonic chip on a substrate of claim 1 , wherein said operating port comprises an edge coupler in optical communication with said circuit.3. The qualification apparatus for a photonic chip on a substrate of claim 1 , wherein said operating port comprises said grating coupler in optical communication with said circuit.4. The qualification apparatus for a photonic chip on a substrate of claim 1 , wherein said grating coupler in optical ...

TESTING OF MICROELECTRONICS DEVICE AND METHOD

A device and method to test microelectronic parts to determine whether the parts are compromised by active illumination in a testing fixture by analysis of emission metrics. 1. An apparatus for determining a state and/or condition and/or reliability of an unpowered microelectronic part specimen under test (PSUT) using active illumination , comprising:a transmission chain;a testing fixture having a capacitive member, the capacitive member is connected to the transmission chain;an input and output RF voltage line connected to the capacitive member having current when testing the PSUT;a testing fixture positioned near the capacitive member receiving the PSUT;a shielded enclosure around the testing fixture having an interior and exterior;a receiving antenna positioned within the interior of the enclosure;a receiving chain connected to the receiving antenna; anda signature analyzer.2. The apparatus of claim 1 , wherein said transmission chain has:a function generator;a RF amplifier connected to the signal generator; andat least one filter connected to the RF amplifier.3. The apparatus of claim 1 , wherein the receiving chain has one or a more of a high pass claim 1 , low pass claim 1 , band-reject claim 1 , and band filters claim 1 , amplifier claim 1 , and sensitive receiver.4. The apparatus of claim 1 , wherein the PSUT is connected to a one or more of a of a ground and clock source.5. The apparatus of claim 1 , wherein the capacitive member has at least two (2) capacitive plates each separately having an RF voltage line claim 1 , when RF voltage is applied there is an electric field between the capacitive plates.6. The apparatus of claim 1 , wherein a processing unit and a memory unit are connected to each other and to the signature analyzer.7. The apparatus of claim 1 , wherein a processing unit and a memory unit are connected to each other and to the analyzer claim 1 , the processing unit claim 1 , the memory unit storing an RF spectrum signature database of one or ...

DEGRADED FEATURE IDENTIFICATION APPARATUS, DEGRADED FEATURE IDENTIFICATION SYSTEM, DEGRADED FEATURE IDENTIFICATION METHOD, DEGRADED FEATURE IDENTIFICATION PROGRAM, AND COMPUTER-READABLE RECORDING MEDIUM RECORDING DEGRADED FEATURE IDENTIFICATION PROGRAM

An object of the present invention is to provide a degraded feature identification apparatus and the like that can identify a degraded feature from a large number of features. The present invention receives light emitted from a moving object and reflected by a feature, acquires reflection intensity data measured at the moving object, and identifies a degraded feature based on acquired reflection intensity data. 1. A degraded feature identification apparatus comprising:an acquisition unit that acquires reflection intensity data based on light emitted from an emission unit and reflected by a feature; andan identification unit that identifies a degraded feature based on the reflection intensity data acquired by the acquisition unit,wherein the acquisition unit further acquires measurement date and time information indicating measurement date and time of the reflection intensity data, andthe identification unit selects the reflection intensity data measured in a predetermined period based on the measurement date and time information, and identifies the degraded feature based on the selected reflection intensity data.2. The degraded feature identification apparatus according to claim 1 , whereinthe acquisition unit further acquires feature type information indicating a type of a feature for which the reflection intensity data is measured, andthe identification unit determines whether a feature is degraded based on a threshold, and changes the threshold according to a type of the feature.3. The degraded feature identification apparatus according to claim 1 , whereinthe acquisition unit further acquires accompanying information including weather information indicating a weather at the time of measurement of the reflection intensity data, andthe identification unit identifies the degraded feature after correcting the reflection intensity data according to the accompanying information.4. (canceled)5. The degraded feature identification apparatus according to claim 1 , ...

SOFT ERROR INSPECTION METHOD, SOFT ERROR INSPECTION APPARATUS, AND SOFT ERROR INSPECTION SYSTEM

A soft error inspection method for a semiconductor device includes: irradiating and scanning the semiconductor device with a laser beam or an electron beam; and measuring and storing a time of bit inversion for each of areas irradiated with the laser beam or the electron beam of the semiconductor device. 1. A soft error inspection method for a semiconductor device , comprising:irradiating and scanning the semiconductor device with a laser beam or an electron beam; andmeasuring and storing a time of bit inversion for each of areas irradiated with the laser beam or the electron beam of the semiconductor device.2. The soft error inspection method according to claim 1 , further comprising calculating an endurance time by multiplying the time of bit inversion stored claim 1 , by a predetermined acceleration factor.3. The soft error inspection method according to claim 2 , wherein the predetermined acceleration factor is obtained from a relationship between an amount of radiation of an environment in which the semiconductor device is used and the laser beam or the electron beam radiated to the semiconductor device.4. The soft error inspection method according to claim 1 , wherein an area to be used in the semiconductor device is set on a basis of information on the time of bit inversion measured.5. The soft error inspection method according to claim 4 , wherein the area to be used is set corresponding to an elapsed time or a purpose of use.6. The soft error inspection method according to claim 4 , wherein information regarding the area to be used or the time of bit inversion is stored in the semiconductor device or a different semiconductor device from the semiconductor device.7. The soft error inspection method according to claim 1 , wherein quality of the semiconductor device is determined on a basis of information on the time of bit inversion measured.8. The soft error inspection method according to claim 1 , wherein the semiconductor device is two-dimensionally ...

DEFECT LOCALIZATION IN EMBEDDED MEMORY

A system and method for defect localization in embedded memory are provided. Embodiments include a system including automated testing equipment (ATE) interfaced with a wafer probe including a diagnostic laser for stimulating a DUT with the diagnostic laser at a ROI. The ATE is configured to simultaneously perform a test run at a test location of the DUT with a test pattern during stimulation of the DUT. Failing compare vectors of a reference failure log of a defective device are stored. A first profile module is configured to generate a first 3D profile from each pixel of a reference image of the defective device. A second profile module is configured to generate a second 3D profile from each pixel of the ROI of the DUT. A cross-correlation module is configured to execute a pixel-by-pixel cross-correlation from the first and second 3D profiles and generate an intensity map corresponding to a level of correlation between the DUT and defective device. 1. A method comprising:generating a log file comprising fail pins and cycles based upon test vectors on a defective device;generating a three-dimensional (3D) profile of a reference image based upon the log file of the defective device;stimulating a device under test (DUT) with a laser from a wafer probe, and simultaneously generating a log file corresponding to each pixel in a region of interest of the DUT;generating a 3D-profile from each pixel of the region of interest of an image of DUT; andperforming a pixel-by-pixel cross-correlation to generate a technical signal image that correspond to a level of correlation between the defective device and DUT.2. The method according to claim 1 , comprising:generating the log file comprising fail pins and cycles based upon memory test vectors on the defective device,wherein the 3D profile comprises fail pins, fail cycles and cycle repeats based upon memory test vectors on the defective device, and the fail cycles are represented on an X-axis of the 3D profile, fail pins ...

METHOD AND APPARATUS FOR TESTING LIGHT-EMITTING DEVICE

Disclosed is a method for testing a light-emitting device comprising the steps of: providing a light-emitting device comprising a plurality of light-emitting diodes; driving the plurality of the light-emitting diodes with a current; generating an image of the light-emitting device; and determining a luminous intensity of each of the light-emitting diodes; wherein the magnitude of the current is determined such that the current density driving each of the light-emitting diodes is smaller than or equal to 300 mA/mm. 1. A method for testing a light-emitting device comprising the steps of:providing a light-emitting device comprising a plurality of light-emitting diodes;driving the plurality of the light-emitting diodes with a current;generating an image of the light-emitting device; anddetermining a luminous intensity of each of the light-emitting diodes;{'sup': '2', 'wherein the magnitude of the current is determined such that the current density driving each of the light-emitting diodes is smaller than or equal to 300 mA/mm.'}2. The method as claimed in claim 1 , wherein the magnitude of the current is a substantially constant value.3. The method as claimed in claim 1 , wherein the light-emitting device comprises only two pads for the current to be provided.4. The method as claimed in claim 1 , wherein the luminous intensity is determined according to a gray level of the image.5. The method as claimed in claim 1 , wherein the step of generating the image of the light-emitting device comprises providing an image receiving device and receiving the image of the light-emitting device from the image receiving device.6. The method as claimed in claim 5 , wherein the image receiving device is a microscope.7. The method as claimed in claim 5 , wherein the image receiving device further comprises an image sensor to capture the image of the light-emitting device.8. The method as claimed in claim 5 , wherein the image receiving device further comprises a filter for filtering off ...

THROUGH-SILICON VIA CRACK DETECTING APPARATUS, DETECTING METHOD, AND SEMICONDUCTOR DEVICE FABRICATION METHOD HAVING THE SAME

The present disclosure relates to a through-silicon via (TSV) crack detecting apparatus, a detecting method, and a fabricating method of the semiconductor device. The TSV crack detecting apparatus includes a test TSV, a conductive liner, a second dielectric liner, a first contact, and a second contact. The test TSV is disposed within a semiconductor substrate, including a conductive channel and a first dielectric liner for isolating the conductive channel and the semiconductor substrate. The conductive liner surrounds the first dielectric liner. The second dielectric liner surrounds the conductive liner. The first contact is connected to the conductive channel. The second contact is connected to the conductive liner. A voltage difference between the first contact and the second contact is used to determine whether a TSV within a predetermined range to the test TSV has a crack based on a conductive state between the first contact and the second contact. 1. A method for detecting a TSV crack , comprising:providing a plurality of TSVs and a TSV crack detecting apparatus on a semiconductor substrate;detecting whether a test TSV in the TSV crack detecting apparatus has a crack; and the test TSV disposed within the semiconductor substrate, wherein the test TSV comprises a conductive channel and a first dielectric liner for isolating the conductive channel and the semiconductor substrate;', 'a conductive liner disposed within the semiconductor substrate and surrounding the first dielectric liner;', 'a second dielectric liner disposed within the semiconductor substrate and surrounding the conductive liner;', 'a first contact disposed on the semiconductor substrate and electrically connected to the conductive channel; and', 'a second contact disposed on the semiconductor substrate and electrically connected to the conductive liner., 'determining whether the plurality of TSVs within a predetermined distance to the test TSV has a crack in accordance with the detection, wherein ...

OPERATING GENERAL PURPOSE HARDWARE AS RADIO

Embodiments includes an apparatus and method that intentionally illuminate a device with RF energy having specific characteristics (e.g., frequency, power, waveform, directionality, duration, etc.) to make a conductor of the device a transmitter. A method can include identifying data to be transmitted by the one or more conductors and providing a signal to the electrical or electronic circuitry to cause the electrical or electronic circuitry to change state and produce a first signal on the one or more conductors. The one or more conductors can produce a forced non-linear emission (FNLE) that is a mixture of the first signal and an electromagnetic wave incident thereon that, when decoded by an external device, corresponds to the data. 1. A device comprising:electrical or electronic circuitry;one or more conductors including one or more wires or traces electrically coupled to the electrical or electronic circuitry; identifying data to be transmitted by the one or more conductors; and', 'providing a signal to the electrical or electronic circuitry to cause the electrical or electronic circuitry to change state and produce a first signal on the one or more conductors; and, 'processing circuitry electrically coupled to the one or more conductors and electrical or electronic circuitry, wherein the processing circuitry is configured to perform operations comprisingwherein the one or more conductors produce a forced non-linear emission (FNLE) that is a mixture of the first signal and an electromagnetic wave incident thereon that, when decoded by an external device, corresponds to the data.2. The device of claim 1 , wherein the operations further include detecting the electromagnetic wave incident thereon.3. The device of claim 2 , wherein providing the signal to the electrical or electronic circuitry is in response to detecting the electromagnetic wave incident thereon.4. The device of claim 1 , wherein providing the signal to the electrical or electronic circuitry is in ...