ОБНАРУЖЕНИЕ КОНФЛИКТОВ В СИСТЕМАХ ШИН EIA-485

Изобретение относится к области передачи данных через системы шин в соответствии со стандартом RS-485 и, в частности, к обнаружению конфликта сообщений в таких системах. Технический результат заключается в более простом обнаружении конфликта сообщений, т.е. наложения сигналов сообщений, передаваемых от передатчиков, подключенных к одной линии передачи и находящихся на удалении один от другого, с достаточно высокой надежностью. Изобретение характеризуется интеллектуальной аппаратной поддержкой, которая допускает обычную функцию обнаружения программного конфликта для обнаружения конфликтов независимо от расположения источников сообщений на линии передачи данных. Аппаратная поддержка допускает режим «возбуждения сильного сигнала» и режим «возбуждения слабого сигнала». В «слабом» режиме между передатчиком или источником напряжения и линией передачи данных временно включается резистор для смещения, или затухания сигнала, или для деления напряжения. 3 н. и 3 з.п. ф-лы, 7 ил.

ОПТИЧЕСКИЙ ПРОЦЕССОР ВЕРБ-1 АЛЕКСАНДРА ВЕРБОВЕЦКОГО

Изобретение относится к компьютерной и информационной технике, а именно к вычислительным устройствам, выполненным на оптоэлектронной элементной базе. Техническим результатом является повышение производительности, помехозащищенности и отказоустойчивости заявленного устройства в условиях воздействия мощных электромагнитных полей на аппаратуру как наземного, так и бортового базирования, используемую в разнообразных компьютерных и информационных технологиях. Для этого процессор содержит блок управления внешней памятью, блок местной памяти, блок микропрограммного управления, блок управляющей памяти, оптическую общую системную шину, блоки кэш памятей, блоки арифметико-логических операций с плавающей точкой, блоки арифметико-логических операций с фиксированной точкой, блоки конвейерных операций, блок управления процессора, оптический блок ввода/вывода сигналов процессора, внутренняя оптическая магистраль ввода/вывода сигналов процессора, местные шины ввода/вывода, оптические блоки ввода/вывода ...

СПОСОБ И СИСТЕМА ДЛЯ ПЕРЕДАЧИ IP-ПАКЕТОВ ПУТЕМ ОБЪЕДИНЕНИЯ НЕСКОЛЬКИХ КАНАЛОВ РАДИОСВЯЗИ ДЛЯ ВЫСОКОСКОРОСТНОЙ ПЕРЕДАЧИ ДАННЫХ

Изобретение относится к системам радиосвязи и, в частности, к системам радиосвязи, работающим в сетевой среде передачи данных. Сущность состоит в том, что мобильный радиотерминал (MWT) принимает IP-пакеты, предназначенные для наземной сети в заданном порядке следования, фрагментирует каждый из IP-пакетов на более мелкие фрагменты пакетов, добавляет идентификационную информацию в каждый из фрагментов пакетов и передает фрагменты пакетов параллельно друг другу по одновременно действующим спутниковым каналам. Принимающая станция принимает фрагменты пакетов, переданные от MWT, пересылает принятые фрагменты пакетов в наземный контроллер по сетевому соединению на основании идентифицирующей информации, добавленной во фрагменты пакетов. Наземный контроллер объединяет фрагменты пакетов в реконструированные IP-пакеты на основании идентифицирующей информации, добавленной во фрагменты, а также упорядочивает реконструированные IP-пакеты в заданном порядке следования на основании идентифицирующей информации ...

СХЕМА АРБИТРАЖА ДОСТУПА К ШИНЕ

Изобретение относится к системам обработки данных и, в частности, к схеме арбитража доступа к шине в системе обработки данных. Техническим результатом является предоставление выделенной пропускной способности при удовлетворении требований относительно времени задержки для устройств обработки, подключенных к шине. Система обработки данных содержит шину, множество устройств обработки, соединенных с шиной, и арбитр шины. Арбитр шины присваивает весовой коэффициент первой категории каждому из устройств обработки из первой категории и весовой коэффициент второй категории каждому из устройств обработки из второй категории. Арбитр шины последовательно предоставляет доступ к шине одному или большему количеству устройств обработки в течение начальной части интервала доступа к шине на основании присвоенных весовых коэффициентов второй категории и предоставляет доступ к шине любому из устройств обработки в течение этой начальной части интервала доступа к шине в ответ на запрос, поступивший от упомянутого ...

КОМПЬЮТЕРНАЯ СИСТЕМА, УСТРОЙСТВО И СПОСОБ ИНИЦИАЛИЗАЦИИ ШИННОГО СРЕДСТВА

Изобретение относится к области компьютерных системных шин, а именно к инициализации средств в системе шин. Техническим результатом является повышение быстродействия компьютерной системы. Компьютерная система содержит одно или более шинных средств, логическое устройство для управления шиной, причем шинное средство содержит арбитражный счетчик, логическое устройство инициализации. Способ инициализации шинного средства заключается в том, что подают сигнал инициализации на шинное средство, определяют идентификатор для шинного средства, определяют начальное значение арбитражного счетчика на основе идентификатора и максимального количества шинных средств, которые могут быть подсоединены к шине. Устройство для инициализации реализует указанный способ. 3 с. и 19 з.п.ф-лы. 4 ил., 3 табл.

СИСТЕМА ПЕРЕДАЧИ ДВУПОЛЯРНОГО СИГНАЛА

Изобретение относится к системам передачи двуполярного сигнала для передачи двоичного сигнала в обоих направлениях. Техническим результатом изобретения является расширение области применения, повышение дальности передачи, обеспечение гибкости управления направлением передачи, упрощение системы. Технический результат достигается тем, что система включает в себя приемопередающий блок, соединенный с адаптером, подключенным к линии связи, блок питающего напряжения, приемопередающий блок состоит из элемента, понижающего сопротивление цепи, и приемный элемент, подключенные к одному выводу адаптера сигналов. В систему введен по крайней мере один нагрузочный резистор, включенный между блоком питающего напряжения, другим выводом адаптера сигналов и линией связи, адаптер сигналов содержит первый элемент, понижающий сопротивление цепи, элемент управления направлением передачи, включенный последовательно в линию связи соответственно первым и вторым выводами и выход которого соединен с управляющим входом ...

УСТРОЙСТВО УПРАВЛЕНИЯ ДОСТУПОМ К МАГИСТРАЛИ В ЛОКАЛЬНЫХ СЕТЯХ С МАГИСТРАЛЬНОЙ АРХИТЕКТУРОЙ

Изобретение относится к вычислительной технике и может быть использовано в качестве устройства управления доступом к магистрали при построении локальных сетей с магистральной архитектурой. Цель изобретения - повышение надежности и производительности устройства. Она достигается введением в блок сопряжения устройства постоянной памяти (ППЗУ), управляющего регистра, буферного регистра, регистра отключения, триггера отказа, дешифратора, второго счетчика, элемента И, блока элементов И - ИЛИ, элемента ИЛИ, элемента задержки, формирователя импульсов, а также их связей, что позволяет производить отключение абонента управляющей магистрали и его блока сопряжения любым абонентом, если только абонент превышает выделенное время работы или находится в неисправном состоянии, и вырабатывать управляющие сигналы на отключение данным блоком сопряжения других абонентов. Сущность изобретения состоит в том, что по каждому импульсу, вырабатываемому блоком управления, происходит захват шины управляющей магистрали ...

ОПТИЧЕСКИЙ ПРОЦЕССОР ВЕРБ-1 Александра ВЕРБОВЕЦКОГО

... 1. Оптический процессор ВЕРБ-1 Александра Вербовецкого содержащий блок управления внешней памятью, блок местной памяти, блок микропрограммного управления, блок управляющей памяти, отличающийся тем, что в процессор введены оптическая общая системная шина, блоки кэш памятей, блоки арифметико-логических операций с фиксированной точкой, блоки арифметико-логических операций с плавающей точкой, блоки конвейерных операций, блок управления процессора, оптический блок ввода/вывода сигналов процессора, внешняя магистраль ввода/вывода сигналов процессора, внутренняя оптическая магистраль ввода/вывода сигналов процессора, местные шины ввода/вывода, оптические блоки ввода/вывода, оптические шины ввода/вывода, оптические блоки дешифрации входных/выходных сигналов, местные шины связи с общей системной шиной, причем входы/выходы каждого блока управления внешней памятью, блока местной памяти, блока микропрограммного управления, блока управляющей памяти, блока кэш памятей, блоков арифметико-логических операций ...

Многоканальное устройство приоритета

Изобретение относится к вычислительной технике и может быть использовано для реализации процедуры доступа абонентов к общей магистрали вычислительной сети. Цель изобретения - повышение производительности путем сокращения времени арбитража запросов. Устройство содержит счетчик , три триггера, два элемента И, элемент ИЛИ, элемент НЕ и элемент развязки . При появлении запроса в одном из кана лов устройства происходит переключение счетчиков каналов в режим счета из режима занесения. После выявления наиболее приоритетного канала по линии связи передается сигнал, блокирующий во всех каналах режим арбитража . 1 ил.

Устройство для сопряжения магистрали ЭВМ с периферийными устройствами

Изобретение относится к вычислительной технике, в частности к устройствам обмена информацией между магистралью ЭВМ типа M-BUS и группой интеллектуал й ных периферийных устройств, работающих в стандарте интерфейса SCSJ Цель - расширение области применения путем обеспечения работы периферийных устройств в стандарте интерфейса SCSJ Устройство содержит шинные формирователи, регистры, дешифраторы, счетчик, инверторы, триггеры , элементы И, элементы ИЛИ-НЕ, И-НЕ, элементы ИЛИ, элемент И-ИЛИ, элементы задержки. Сущность изобретения заключается в том, что за счет введения новых элементов и их связей которые обеспечивают преобразование управляющих, адресных и информационныхь сигналов системой магистрали ЭВМ в управляющие сигналы для периферийных устройств, с одной стороны и формирования из сигналов оповещения периферийных устройств сигналов запросов системной магистрали и байта состояния устройства, описывающего режим и фазу его работы, с другой стороны, расширена область его применения 5 ил , 3 ...

Многоканальное устройство для подключения абонентов к общей магистрали

Изобретение относится к вычислительной технике и может быть использовано в системах обмена данными многопроцессорных вычислительных комплексов реального времени. Цель изобретения - повышение функциональной надежности устройства за счет исключения рассогласования фаз тактовых импульсов каналов устройства. Многоканальное устройство для подключения абонентов к общей магистрали содержит каналы, а каждый канал - делитель частоты, селектор импульсов, счетчик адреса, схему сравнения, элемент задержки, триггер, два элемента И, элемент ИЛИ - НЕ. В устройстве производится периодическая установка делителей частоты, что исключает рассогласование фаз тактовых импульсов. 1 з.п. ф-лы, 5 ил.

Многоканальное устройство для подключения абонентов к общей магистрали

Изобретение относится к вычислительной технике, в частности к приоритетным устройствам, и может быть использовано для организации обращения от нескольких абонентов к общему ресурсу, в частности к общей магистрали. Цель изобретения - повышение быстродействия устройства за счет продолжения арбитража запросов после захвата магистрали. Устройство содержит перед первым каналом элемент задержки, два одновибратора и в каждом из М каналов, два триггера, два элемента задержки , два элемента И, три элемента ИЛИ, счетчик, регистр, элемент ИЛИ-НЕ, схему сравнения, два одновибратора. Работаетус- тройство следующим образом. После захвата магистрали канал абонента, совершающего обмен, возобновляет опрос каналов. При появлении запроса в другом канале этот канал выдает пакет на магистраль сразу после освобождения магистрали, за счет того, что в каждом канале отслеживается момент завершения обмена информацией по моноканалу. Таким образом, не требуется дополнительного арбитража запросов . 1 ил. (Л С ...

Устройство приоритетного доступа к общей шине

Изобретение относится к вычислительной технике, в частности к устройствам приоритета , и может быть применено при управлении очередностью- обращения нескольких микропроцессоров к общему ресурсу вычислительных систем. Цель изобретения - повышение быстродействия устройства . Устройство приоритетного доступа к общей шине содержит блок 5 переключения процессоров и блок 6 разрешения доступа к шине. Кроме того, многопроцессорная система , в которой используется предложенное устройство, содержит ПЗУ 1, ОЗУ 2, устройство 3 ввода-вывода и процессоры 7. Блок 5 включает программно-доступный регистр , два дешифратора, N+2 регистров (N - число процессоров), три схемы сравнения, два счетчика, N+2 элементов ИЛИ, а блок 6 - группу узлов доступа к устройству, каждый из которых содержит пять регистров, две схемы сравнения, элемент И, два одновиб- ) ратора и шинный формирователь. 3 ил.

Многоканальное устройство для подключения абонентов к общей магистрали

Изобретение относится к вычислительной технике, в частности к приоритетным устройствам, и может быть использовано для организации обращения от нескольких ресурсов к общей магистрали . Цель изобретения - расширение области применения и повышение производительности устройства за счет реализации приоритетного режима обслужи- вания запросов. Устройство содержит К каналов, перед наиболее приоритетным каналом - триггер, элемент задержки, одновибратор; перед каждым каналом - элемент ИЛИ и в каждом канале - три элемента задержки, четыре мультиплексора , элемент НЕ, элемент И, два триггера, элемент ИЛИ, элемент 2 И- ИЛИ, переключатель, два одновибратора, два блока элементов И с открытым коллектором , блок элементов ИЛИ. В устройстве реализуется приоритетный режим обслуживания запросов для адаптируемых к потоку запросов структур систем, основанных на динамической сегментации моноканала, по которому одновременно могут совершать обмен информацией несколько пар абонентов.. Это позволяет добиться наивысшей ...

Система коммутации

Изобретение относится к вычислительной технике, решает задачу уменьшения времени восстановления системы при отказах информационных шин линий. Система коммутации содержит коммутаторы 1, соединенные между собой и с абонентами 2 информационными шинами, устройства 4 управления обменом, связанные с абонентами 2 адресными шинами, а между собой и с блоком 9 восстановления линией опроса . Сущность изобретения состоит в введении блока 9 восстановления, соединенного с двумя коммутаторами 1 информационными шинами, также соединенного с устройствами 4 управления обменом цепью сброса и линией опроса , а со всеми коммутаторами линиями индикации отказов. Это позволяет реализовать процедуру оперативно- го восстановления любой информационной шины при отказе информационной линии, входящей в состав шины. 5 ил. с jO (Л 00 ел со 00 00 (рие.1 ...

Устройство предоставления магистрали

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DEVICE FOR SUBSCRIBERS CONNECTION TO INFORMATION CHANNEL

MULTICHANNEL DEVICE FOR CONNECTION OF SUBSCRIBERS TO COMMON TRUNK

DEVICE FOR CONNECTION OF SUBSCRIBERS TO COMMON TRUNK LINE

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МНОГОКАНАЛЬНОЕ УСТРОЙСТВО . ПРИОРИТЕТА, еодерхацее элемент ШН а 8 каждом канале nepBii и второй элементы И, причем вход запроса канала соединен с прямым входом первого элемента И, выход которого соединен с соответствувяцим входом , 1. K.K.-v,, ,..Г Р- V..:..- .::. JS элемента ИЛИ, а выход второго эле . мента И является выходом опроса кана- ла и соединен со входом опроса следующего канала, отличающееся тем, что,, с целью повышения быстродействия, в кгикдый канал введены элемент задержки и третий элемент И, первый прямой вход которого соединен с входом запроса канала , второй прямой вход соединен со входом опроса кангша, первый инверсный вход третьего элемента И соединен с выходом элемента ИЛИ, а второй инверсный вход - с выходом опроса канала, выход третьего элемента И соеданен с инверсным входом второго элемента И и является выходом разрешения канала, вход элемента задержки соединен со вхояом опроса кангшов, а выход соединен с пря: мым входом второго элемента И, вход опроса кг1ждого канала ...

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EIN KOMMUNIKATIONSKNOTENPUNKT MIT EINER ERSTEN BUSKONFIGURATION FÜR ARBITRIERUNG UND EINER ZWEITEN BUSKONFIGURATION FÜR DATENÜBERTRAGUNG

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VERTEILTES STEUER- UND ÜBERWACHUNGSSYSTEM

Bus-Master, Bussystem und Bussteuerungsverfahren

Es wird zur Verfügung gestellt: eine Zugriffsgenerierungseinheit (111), die ein Befehlsdatenelement erzeugt, das eine Übertragungsart einschließt, die eine Übertragungsart angibt, die eine Datenübertragung und eine Übertragungszieladresse eines Busslave, an den die Übertragungsanforderung gerichtet ist, anfordert; eine Befehlswarteschlange (112), die eine Vielzahl der Befehlsdatenelemente speichert, die von der Zugriffsgenerierungseinheit (111) generiert wurden; eine Einheit zum Steuern der Ausgabesequenz der Übertragungsanfragen (114), die als Ausgabezielbefehlsdatenelement ein zweites aus der Vielzahl von in der Befehlswarteschlange (112) gespeicherten Befehlsdatenelementen auswählt, wobei das zweite Befehlsdatenelement eine Übertragungszieladresse enthält, die von einem zweiten Busslave besessen wird, der langsamer als ein erster Busslave antwortet, der die Übertragungszieladresse besitzt, die im ersten Befehlsdatenelement enthalten ist; und eine Einheit zum Ausgeben der Übertragungsanfragen ...

Datenverarbeitungssystem sowie Verfahren dafür

KANALPRIORITAETSNUMMER-ZUWEISUNGSVORRICHTUNG.

System zur Steuerung der Datenübertragung.

Halbleiterbauelement mit Systembus und externem Bus sowie zugehörige Verfahren und Vorrichtungen

Die Erfindung bezieht sich auf ein Halbleiterbauelement mit einem Systembus (410) und einem externen Bus (415) sowie auf zugehörige Verfahren und Vorrichtungen zum Betrieb solcher Bauelemente, insbesondere zur Zuweisung programmierbarer Prioritäten für beide Datenbusse unter Verwendung eines Buszuteilers. DOLLAR A Erfindungsgemäß sind z. B. durch einen einzelnen Mehrentscheidungs-Buszuteiler (495) programmierbare Ranganordnungen zur Zuweisung von Prioritäten zu Anfragen von Blöcken vorgesehen, die übergeordnete Einheiten für einen jeweiligen der beiden Busse sind. Die Anfragen werden dahingehend untersucht, zu welchem der Busse sie gehören, und Prioritäten werden dann so zugewiesen, dass die Busnutzung möglichst groß wird, verbunden mit einer erhöhten Betriebsgeschwindigkeit für ein System auf einem Chip. DOLLAR A Verwendung z. B. für sogenannte SOC (Systeme auf einem Chip), insbesondere auf einem Halbleiterchip.

SYSTEM UND GERÄT ZUR BUSSTEUERUNG

Bussteuerung in einem Datenprozessor

ANORDNUNG ZUR WAHLFREIEN, STOCHASTISCHEN UND KOLLOSIONSFREIEN BELEGUNG EINES KOPPELBUSSES

Automatische Datenvorausladung in einem Rechnersystem

Eingebauter Prozessor mit direkter Verbindung von Sicherheitsvorrichtungen für verbesserte Sicherheit

Integrierte Schaltung (212), umfassend: eine Schnittstellen-Logikschaltung (216) eines ersten Busses zur Verbindung mit einem ersten externen Bus (215); eine Mikrosteuerung (320), welche geeignet konfiguriert ist, um ein Eingangssignal von einer Sicherheitsvorrichtung (720) über eine direkte Eingangsleitung (710), welche von dem ersten externen Bus (215) verschieden ist, zu empfangen, wobei die Mikrosteuerung (320) ferner geeignet konfiguriert ist, um eine Anforderung zu empfangen und die Sicherheitsvorrichtung (720) über die direkte Eingangsleitung (710) zu befragen.

Control chipsets for use with data transaction process in computer system, stores data length to be used for calculating number of permitted events in data queue

Upper and lower bridge chips (32,30) have respective transceivers connected to a VLINK bus. Data relating to writing events, data length and data addresses are stored temporarily in data queue connected to one transceiver. A read/write recording circuit connected to other transceiver, stores data length to be used for calculating number of permitted events in data queue. Independent claims are also included for the following: (a) Signal transmission device; (b) Data transmission method ...

Prozessorbusanordnung

Die Erfindung betrifft eine Prozessorbusanordnung mit mehreren Daten-Prozeß-Einheiten, die jeweils mit einem als Bus vereinbarten Leistungssystem verbunden sind. Die erfindungsgemäße Lösung der Aufgabenstellung besteht darin, daß der Bus Verbindungseinheiten und Bussegmente aufweist, wobei die Bussegmente über die Verbindungseinheiten zu dem Bus auftrennbar verbunden ist. Bei dieser erfindungsgemäßen Lösung ist gewährleistet, daß die Funktionseinheiten, die an den Bus angeordnet sind und ihren Informationsaustausch über den Bus betreiben, diesen Austausch unabhängig von anderen Funktionseinheiten tätigen können. Vielnehr können auch andere Funktionseinheiten in weiteren Gruppierungen einen eigenen Informationsaustausch über diesen Bus ebenfalls zeitgleich ausführen. Während die Verbindungseinheiten die Funktion der definierten kombinatorischen Zusammenschaltung der Signalleitungen bewirken, stellen die Bussegmente die leitungsmäßigen Verbindungen zwischen den Verbindungseinheiten her. Hierbei ...

Processor architecture

METHOD AND APPARATUS FOR REGULATING INPUT/OUTPUT TRAFFIC OF A DATA PROCESSING SYSTEM

... 1412051 Data processing systems BURROUGHS CORP 19 June 1973 [3 July 1972] 29094/73 Heading G4A The system has a processor which can communicate with a number of peripherals. Data transfer is prevented if a traffic loading value indicative of the number and type of concurrent data transfer exceeds a certain threshold value. If the system uses several input/output control units the threshold values of the units are adjusted to ensure balanced use of the units. In the embodiment disclosed the processor comprises a number of modules (11, 13, 15, 17, Fig. 2, not shown) connectable to peripheral units (31, 37, &c.) via data buses (25, 27). Each bus is associated with an input/output multiplexing control unit (19, 21), and each control unit with a traffic regulator. Each I/O control unit (e.g. 19, Fig. 3, not shown) comprises a decoder (59) which, on receipt of an interrogating signal from a module, provides an input to an AND gate (61) within the unit. When a fresh peripheral is to communicate ...

MICROPROCESSOR BUS INTERFACE UNIT

A microprocessor which has an internal data bus width of n bytes where n is greater than 2 (in the currently preferred embodiment, 32-bit bus) provides address signals for an n byte transfer (read or write) of data. An input receives at least one "size" signal 34, 35 which indicates the number of bytes that an external memory will transfer on the next ready signal. The microprocessor includes logic means and an output 29 for providing a "last" signal indicating that a data transfer request by the microprocessor will be satisfied with the data transfer occurring at the next ready signal. This logic means keeps track of the number of bytes that have been transferred, periodically senses the byte sizing signal, and is able to change the status of the "last" signal "on the fly". Therefore, by way of example, the external memory can provide a particular byte size signal as a default condition, and then change the signal when the memory determines the number of bytes that the memory is actually ...

Disc autochanger interface system

A system for interfacing an optical disk autochanger 302 having a robot 314 and a plurality of disk drives 308 to a 102 host includes a master SCSI bus 104, a subordinate SCSI bus 306, a SCSI multiplexer 304 and a move controller 305. The master SCSI bus 104 is connected to the host. The subordinate SCSI 306 bus is connected to the plurality of disk drives 308. The multiplexer 304 is connected between the master SCSI bus and the subordinate SCSI bus. The multiplexer transfers communications between the host and a selected disk drive. The move controller 305 receives jukebox control commands from the host and selects the disk drive based on the jukebox control commands.

IBM PC Compatible multi-chip module

Processor architecture

Lookup Engine

A look up engine 200 comprising a storage means 212a, 212b for storing a plurality of entries, each entry comprising a value and an associated key value, such that, in operation, a look up is carried out by outputing a value which is associated with the stored key value which matches an input key value. The look up engine 200 comprises a plurality of look up state machines 206a, 206b, 206c, 206d connected in parallel to enable multiple look ups to be carried out concurrently. Each entry comprises an associated skip value, if the skipped bits of the input key value and the associated skip value mismatches, an error message is output to indicate lookup failure. The entries may be stored in a trie format which is constructed by identifying overlapping ranges between the plurality of entries; splitting the identified overlapping ranges; storing the plurality of entries within a trie structure.

DATA TRANSFER BUS WITH VIRTUAL MEMORY.

An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

APPARATUS FOR QUEUING REQUESTS AND REPLIES ON A PIPELINED PACKET BUS

Dynamically allocating space in RAM shared between multiple USB endpoints and USB host

Encryption processor with shared memory interconnect

An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories, A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.

Computer system having direct media access mode

DATA TRANSFER FOR TYPEWRITER TELEPRINTER OR DATA PRINTER

Bus arbitration system

System for detecting and resetting a device coupled to an inter-integrated circuit router

Embodiments of the present invention provide a system and method for detecting if a device is coupled to an inter-integrated circuit (I2C) router and/or for resetting the device. The I2C router (1605) comprises a first I2C bus port (1620) having a presence line (1660) and/or a reset line (1665). The I2C router (1605) further comprises a control logic (164) coupled to and/or distributed within the first I2C bus port (1620). The control logic (1640) may determine if a device is coupled to the I2C router as a function of a state of the presence line (1660). The control logic (1640) may also determine if a reset condition exists. If a reset condition exists, the control logic (1640) changes the state of the reset line (1665), thereby causing the device to reset itself.

Mixed-media telecommunication call set-up

Data processing apparatus with encoded system bus

A data processing apparatus includes a processor unit 34, one or more storage units 35, and input/output controller units 36 connected by a common system bus 37 which includes a system information field and an associated system operation code field encoded to designate the function and nature of the information in the information field. Synchronous clocking is typically employed on the system bus to ensure time synchronization throughout the data processing apparatus. The system operation code represents many different types of information. For example, when the system bus is connected for transfers between the storage unit and other parts of the system, the system operation code is encoded to specify that the associated system information field contains either a storage unit address or storage unit data. Priority access control apparatus is provided for allocating access to the system bus among the various units connected to the system bus. ...

Procedure and apparatus for inter processor data transfer in a multi processor system.

Procedure and apparatus for transferring data between central units or processors in a multi-processor system, said system comprising one or several central units (3) with memories (4). The data to be transferred between central units (3) or processors are separated from their internal bus (6) by means of joint memories (2) and the data transfer between the joint memories (2) is effected by a separate copying means (1). ...

Receiving buffer credits by a plurality of channels of one or more host computational devices for transmitting data to a control unit

A channel of a host computational device sends a command to transfer data to a control unit included in a storage controller. The channel of the host computational device receives a number of buffer credits from the control unit for communication with the control unit, where the number of buffer credits that is received is based on the control unit monitoring a number of transfer ready operations and a number of retry operations during a monitoring period while communicating with a plurality of channels that includes the channel.

A method and apparatus for isochronous data transport over an asynchronous bus

Processor system

Data bus system and method for performing cross-access between buses

Computer arrangements

... 1,042,973. Electronic digital computers. GENERAL ELECTRIC CO. April 23, 1963 [May 1. 1962 (2)], No. 16054/63. Heading G4A. Connection between a computer and one of its peripheral units is established with the use of a switching unit which on receipt of signals from a plurality of peripheral units calling for connection selects that unit having the highest priority from a predetermined order of priorities. The logical circuitry for such selection is illustrated schematically (Fig. 1, not shown), and includes a bi-stable unit for each peripheral device which when enabled controls the routing of data to and from that device.

MASTERLESS AND CONTENTIONLESS COMPUTER NETWORK

COMPUTER BUS APPARATUS

Memory system

... 1,069,480. Digital computers; memory systems. HUGHES AIRCRAFT CO. July 5, 1965 [Oct. 27, 1964], No. 28344/65. Heading G4A. In a memory system having a plurality of memory banks and a plurality of memory access sources, different sources may access different banks simultaneously but different sources may access a single bank only according to a predetermined priority. Each bank includes an address register and selection means including a priority network responsive to said register and also to memory access request signals from said sources. Said plurality of sources may include an arithmetic unit and one or more inputoutput devices, these devices taking priority over said arithmetic unit. The memory banks may comprise arrays of magnetic cores, films or wires. The input-output devices may include magnetic tape or discs, punched tape, radar or communication systems. The addresses provided by the various sources have a portion which is common to all memory banks and a bank selector portion ...

NET INTERFACE

TWO-DIRECTION INTERMEDIATE AMPLIFIER WITH HIGH/CLOW THRESHOLD DETECTION CIRCUIT

MULTI-GATE MEMORY UTILIZATION INTELLIGENT ONE DATA BUS INTERFACE

INTERRUPTION COMPLETION IN A SYNCHRONOUS ENVIRONMENT

PROCEDURE FOR THE ENTERPRISE OF A PROCESSOR BUS

Communication circuit of inter-integrated circuit device

A communication circuit of an Inter-Integrated Circuit (I2C) includes a master device, a switch circuit, first and second groups of slave devices. Each slave device includes a data signal pin and a clock signal pin, which are connected to the switch circuit. The master device includes a data signal pin, a clock signal pin, and a general purpose input output (GPIO) pin, which are connected to the switch circuit. The GPIO pin of the master device outputs a control signal to the switch circuit, to allow communication between the first group of slave devices and the master device or communication between the second group of slave devices and the master device.

Transmitting Retry Request Associated With Non-Posted Command Via Response Credit Channel

In a particular embodiment, a method is disclosed that includes, at a first computing device coupled to a second computing device via a bus, receiving a request from the second computing device to complete a non-posted command, where the request is received via a request credit channel of the bus, and where the first computing device is configured to receive requests to complete non-posted commands and requests to complete posted commands via the request credit channel. The method also includes removing the request to complete the non-posted command from the request credit channel. The method further includes transmitting a retry request associated with the non-posted command to the second computing device via a response credit channel of the bus.

Apparatus and method for controlling issuing of transaction requests

Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value.

Data transfer circuit and data transfer method

A port A request queue is configured with a port AQ 0 to a port AQn for each of request types Q 0 to Qn connected with a requester resource busy flag controller Q 0 to a requester resource busy flag controller Qn, respectively. A port A resource checking unit of a port X arbiter unit gives instructions to the requester resource busy flag controller of the port AQ 0 to turn a busy flag on when it is determined that a data request from the port AQ 0 has difficulty in being output to a port X inter-port arbiter unit due to resources being busy as a result of referring to a resource information unit of a port X resource managing unit. The port AQ 0 inhibits output of a data request as long as the busy flag is on.

Verifying access-control policies with arithmetic quantifier-free form constraints

A system and method is provided for verifying an access-control policy against a particular constraint for a multi-step operation. In disclosed embodiments, the method includes expressing the access-control policy as a first quantifier-free form (QFF) constraint and identifying the particular constraint as a second QFF constraint. The method also includes identifying an operation vector and providing copies of the operation vector associated with steps in the multi-step operation. The method also includes determining a third QFF constraint using the first QFF constraint, the second QFF constraint, and the copies of the operation vector. The method also includes solving the third QFF constraint to determine a solution and outputting a result of the solving.

Method for Assigning Addresses to Nodes of a Bus System, and Installation

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

Non-invasive direct-mapping usb switching device

A non-invasive direct-mapping USB switching device includes a main-controlled microprocessing module connected to a high-impedance module, and the high-impedance module is provided for detecting and monitoring a functional instruction code of a USB device transmitted from a data transmission module, such that a USB connecting module can be used for transmitting the USB data and functional instruction code to detect and monitor the data transmission module when the USB device is connected to the USB switching device. If the data transmitted from the data transmission module is not the required functional code, the non-required functional code (such as the USB data) will be passed, so that the USB device can be connected and communicated with a plurality of computer devices through another USB connecting module and a switching module to achieve a plug-and-play function.

Use of pci express for cpu-to-cpu communication

CPUs that generate PCIe auxiliary signals and changing clock signals nevertheless communicate with each other using PCIe owing to PCIe switch assemblies that are disposed in the communication paths to isolate and terminate the auxiliary signals from reaching other CPUs and to isolate changing clock signals, communicating with each other using a fixed clock derived from one of the changing clock signals. Also, the CPUs directly access the memories of CPUs to which they wish to write data so that data is directly written from one CPU memory to another without store-and-forward operations being needed in the network.

Communication system, master device and slave device, and communication method

A communication system includes a master device and slave devices. Each slave device includes a request signal generation part configured to, when data to transmit is generated, generate a request signal indicating a transmission request to a master device; and a transmission part configured to transmit the request signal to the master device. The master device includes a request signal reception part configured to receive the request signals from the slave devices; a selection part acting configured to select one of the slave devices according to the request signals received by the reception part; a transmission part configured to transmit a signal indicating to allow data transmission to the slave device selected by the selection part; and a data reception part configured to receive data from the selected slave device.

Cache with Multiple Access Pipelines

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

Method of adjusting transfer speed after initialization of SATA interface

In a method of adjusting transfer speed after initialization of a SATA interface, a SATA link device transmits a first predetermined primitive to a SATA link partner for requesting to change a first transfer speed of the SATA link device from a first speed to a second speed, the SATA link partner replies to the SATA link device with a second predetermined primitive according to the first predetermined primitive, and the SATA link device and the SATA link partner respectively adjust the first transfer speed of the SATA link device and a second transfer speed of the SATA link partner according to the second predetermined primitive.

Formal Verification of Random Priority-Based Arbiters Using Property Strengthening and Underapproximations

A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a set of input ports. Responsive to the first predetermined time period expiring before the processor determines whether the random priority-based arbiter is blocking, a determination is made as to whether the random priority-based arbiter is blocking one of the set of output ports or the set of input ports within a second predetermined time period using the random seed and at least one of property strengthening or underapproximation. Responsive to the processor determining that the random priority-based arbiter satisfies a non-blocking specification such that not one of the set of output ports or the set of input ports is blocked within the second predetermined time period, the random priority-based arbiter is validated as satisfying the non-blocking specification.

Determining addresses of electrical components arranged in a daisy chain

In one aspect, a system includes electrical components arranged in a daisy chain that include a first electrical component disposed at a first end of the daisy chain and a second electrical component disposed at an opposite end of the daisy chain than the first end. Each of the first and second electrical components includes an input port, an output port and a common port. The input port of the first electrical component is coupled to one of a supply voltage port or ground and the common ports of the first and second electrical components are coupled to the other one of the supply voltage or the ground. An address of the second electrical component is determined before addresses of the other of the electrical components are determined, and the addresses determine a position of an electrical component with respect to the other of the electrical components.

Communication system, master node, and slave node

In a node communicably coupled to alternative nodes through a bus, a transmitting unit receives first designation information from an alternative node. When the first designation information designates the node, the transmitting unit successively transmits, on the bus, the first designation information and data. When a request of an active communication occurs in the node, a request unit determines whether to receive a former part of the first identification information indicative of start timing of an active communication mode on the bus. When determining to receive the former part of the first identification information, the request unit transmits, on the bus, collision information at a timing that allows the collision information to collide with a latter part of the first identification information, resulting in rewrite of the first identification information based on bus arbitration, and transmits second designation information meeting the request of the active communication.

Baseboard management controller and method for sharing serial port

A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized, the COM serial port is used by the BIOS. When a processor of the BMC sends a control command to a sharing system of the BMC, the input queue and the output queue are converted to time division multiplex (TDM) queues. The COM serial port may be used by the BIOS or by the BMC according to an ID flag of each element of the TDM queues.

Multi-root sharing of single-root input/output virtualization

In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

Bus-handling

A processor, comprising a processing unit having an active state and a sleep state in which at least one of its sub-sections is inactive and a communication port adapted to receive signals from external units over a bus, which is configured to be not fully operative when the processor is in the sleep state. The processor additionally includes a bus monitoring unit configured to stall the bus responsive to identifying transmissions on the bus directed to the communication port, while the processing unit is in the sleep state and to indicate to the communication port that a transmission started while it was in the sleep state.

Electrical Circuit For Transmitting Signals Between Two Masters And One Or More Slaves

An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch.

Apparatus and methods for serial interfaces

Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers.

Operation method for a computer system

A device receives a standard command. The device judges whether an address field and/or a data length field and/or a data field of the standard command includes at least one of a vendor command, a vendor data and a checkword. The device judges whether the address field and/or a data length field and/or the data field of the standard command matches a vendor predetermined pattern. If matched, the device performs a vendor operation based on the vendor command and/or the vendor data of the standard command.

Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

Livelock prevention mechanism in a ring shaped interconnect utilizing round robin sampling

A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N 2 ).

Memory System with Calibrated Data Communication

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Zone group manager virtual phy

A switch is provided. The switch includes an expander configured to couple a server to a set of storage drive bays. The switch also includes a zone manager coupled to the expander and configured to maintain a zoning configuration corresponding to the set of storage drive bays. The zone manager is coupled to the expander through a virtual PHY.

Constituting a control system with virtual and physical backplanes and modules as building blocks

A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation.

Data transfer apparatus and data transfer method

A packet accompanying data valid information is transferred at high efficiency within an integrated circuit or between integrated circuits. A character indicating data enable information is provided and an identifier indicating a data enable character is assigned onto the packet. When the data enable information is valid in series, the data enable characters are eliminated from the packet to be transferred.

Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration

Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

Motherboard of computing device

A motherboard of a computing device includes a dual inline memory module (DIMM), a processor socket, a platform controller hub (PCH), a switch, and a switch controller. The DIMM is connected to the processor socket or the PCH through the switch controller. The switch is connected to the switch controller, and generates a signal when the switch is operated. The switch controller controls the DIMM to connect either to the processor socket or to the PCH according to the signal, so that a solid state disk (SSD) or a memory that is connected to the DIMM can be supported appropriately by the motherboard.

Avoiding non-posted request deadlocks in devices

Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Avoiding non-posted request deadlocks in devices

Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Implementing device physical location identification in serial attached scsi (sas) fabric using resource path groups

A method and controller for implementing device physical location identification in a Serial Attached SCSI (SAS) fabric using resource path groups, and a design structure on which the subject controller circuit resides are provided. The device physical location identification includes a Resource Path Group (RPG). Each RPG provides a unique persistent physical locator of a storage device in the system. Each RPG including at least two Resource Paths (RPs) and each RP has a fixed size identifying a type and a series of egress ports. A persistent RPG is stored within the device metadata on the storage device.

System and method for improving ecc enabled memory timing

A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

Requests and data handling in a bus architecture

Aspects relate to methods and systems for processing requests and sending data in a bus architecture. At least one master device is connected to at least two slave devices via a bus. An allocator allocates incoming requests from the master device to a target slave device. Incoming requests are buffered for the respective slave device. The master device sends a read request for a first slave device to the bus; the allocator generates a current-state indicator associated with the read request. The allocator generates a priority indicator associated with the read request. If the initial value of the current-state indicator equals the value of the priority indicator, the read request is processed; or if the initial value of the current-state indicator does not equal the value of priority indicator, the read request is deferred until a later time.

Bus monitoring device, bus monitoring method, and program

A bus monitoring device may include a measurement unit configured to measure a bandwidth of data on a common bus for a unit time, which is constant and predetermined, based on transfer information indicating a state of exchange of the data when a plurality of processing blocks connected to the common bus exchange the data via the common bus with a memory including an address space having a plurality of banks.

Multicore processor system, computer product, and control method

A multicore processor system includes a core configured to detect a change in a state of assignment of a multicore processor; obtain, upon detecting the change in the state of assignment, number of accesses of a common resource shared by the multicore processor by each of process that are assigned to cores of the multicore processor; calculate an access ratio based on the obtained number of accesses; and notify an arbitration circuit of the calculated access ratio, the arbitration circuit arbitrating accesses of the common resource by the multicore processor.

Integrating Intellectual Property (IP) Blocks Into A Processor

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

High Priority Command Queue for Peripheral Component

In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.

Methods and devices for universal serial bus port event extension

Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.

Low latency, high bandwidth data communications between compute nodes in a parallel computer

Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.

NOVEL CIRCUIT AND METHOD FOR COMMUNICATING VIA A SINGLE LINE

A method for transmitting logical information from a transmitter to a receiver via a single line, the receiver being connected to the transmitter by the line, the receiver placing a first signal on the line and the first signal being made up of alternating recessive and dominant levels, the transmitter placing a second signal on the line and the second signal being superposed on the line by the transmitter at least in the segments in which the first signal has a recessive level, the second signal being made up of a sequence of recessive and dominant levels, and the receiver determining from the second signal the logical information that is to be received. 113-. (canceled)14. A method for transmitting logical information from a transmitter to a receiver via a single line , the receiver being connected to the transmitter by the line , the method comprising:placing, using the receiver, a first signal on the line, the first signal being made up of alternating recessive and dominant levels;placing, using the transmitter, a second signal on the line, the second signal being superposed on the line by the transmitter at least in the segments in which the first signal has a recessive level, the second signal being made up of a sequence of recessive and dominant levels; anddetermining, using the receiver, from the second signal, the logical information that is to be received.15. The method of claim 14 , wherein the transmitted logical information is configuration information for initializing one of a control device claim 14 , a component claim 14 , and a bus connection unit.16. The method of claim 14 , wherein the first signal is made up of a sequence having a prespecified or prespecifiable number of rectangular pulses claim 14 , at least one of the duration of the recessive line level and the duration of the dominant line level within the sequence being approximately constant.17. The method of claim 14 , wherein the transmitter begins the superposition of the second signal ...

AS-I COMMUNICATION COMPONENT

A communication component is disclosed for communication via an AS-i line. In order to provide an improved AS-i communication component for communication via an AS-i line, it is proposed in at least one embodiment that a standard AS-i signal and an extended AS-i communication signal are sent and/or received via an AS-i line using a shared communication component. 1. A communication component for communication by way of an AS-i line , wherein a standard AS-i communication signal and an extended AS-i communication signal are at least one of sendable and receiveable by way of the AS-i line by way of the common communication component , wherein a frequency spectrum of the extended AS-i communication signal , used for at least one of sending and receiving , lies in the range of 1 MHz to 10 MHz.2. The communication component of claim 1 , wherein the communication component is an ASIC or an FPGA chip.3. The communication component of claim 1 , wherein the frequency spectrum of the standard AS-i communication signal used for at least one of sending and receiving lies in the range of 50 kHz to 500 kHz and the frequency spectrum of the extended AS-i communication signal used for at least one of sending and receiving lies in the range of 1 MHz to 10 MHz.4. The communication component of claim 1 , wherein the communication component uses the Orthogonal Frequency Division Multiplex method for at least one of sending and receiving the extended AS-i communication signal.5. The communication component of claim 1 , further comprising:a first analog to digital converter unit for receiving the standard AS-i communication signal; anda second analog to digital converter unit for receiving the extended AS-i communication signal.6. The communication component of claim 1 , further comprising:a shared analog to digital converter unit for receiving the standard AS-i communication signal and the extended AS-i communication signal.7. The communication component of claim 5 , further comprising: ...

ASYNCHRONOUS PROTOCOL CONVERTER

An asynchronous protocol converter, which is capable of flexibly carrying out communications between tens of IP cores in an asynchronous protocol Network-on-Chip system, and which is multiple input multiple output is provided. In an LSI (), which comprises a plurality of IP cores (), and routers () positioned adjacent to the plurality of IP cores (), an asynchronous protocol converter () is positioned between adjacent routers (). The asynchronous protocol converter () is configured to comprise: a two-to-four-phase converter () that is connected to an adjacent router () within the LSI (); a four-phase pipelined router () that is connected on the output side of the two-to-four-phase converter (); a four-to-two-phase converter () that is connected to the outputs of the four-phase pipelined router (); an input controller () that controls the two-to-four-phase converter (); and an output controller () that controls the four-to-two-phase converter (). 1. An asynchronous protocol converter provided between neighboring routers in an LSI including a plurality of IP cores and a router provided adjacent to the plurality of IP cores , comprising:a two-to-four-phase converter connected to the neighboring router in the LSI;a four-phase pipelined router connected to the output side of the two-to-four-phase converter;a four-to-two-phase converter connected to an output of the four-phase pipelined router;an input controller for controlling the two-to-four-phase converter; andan output controller for controlling the four-to-two-phase converter.2. An asynchronous protocol converter provided between neighboring routers in an LSI including a plurality of IP cores and a router provided adjacent to the plurality of IP cores , comprising:a two-to-four-phase converter connected to the neighboring router in the LSI;a four-phase pipelined router connected to the output side of the two-to-four-phase converter;a four-to-two-phase converter connected to an output of the four-phase pipelined ...

SYSTEMS AND METHODS FOR IMAGE STREAM PROCESSING

Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may provide vision systems and methods suitable for use in vehicles, particularly windowless vehicles, such as armored ground vehicles, submerged watercraft, and spacecraft. Some embodiments may enable sharing of image streams (e.g., with one or more other vehicles), generation of panoramic views (e.g., from various camera feeds), intelligent encoding of image streams, and implementation of security features based on image streams. 1. A system for image stream processing , comprising:an image stream input interface;an image stream output interface;a first image processing module configured to accept a plurality of image streams, stitch at least two image streams from the plurality of image streams into a contiguous image stream, and output the contiguous image stream, wherein the plurality of image streams comprises an image stream from the image stream input interface or from another image processing module;a second image processing module; and selectively map the image stream from the image stream input interface or from the second image processing module, to the first image processing module, and', 'selectively map the contiguous image stream from the first image processing module to the image stream output interface or to the second image processing module., 'a switching matrix in communication with the image stream input interface, the image stream output interface, the first image processing module, and the second image processing module, wherein the switching matrix is configured to2. The system of claim 1 , further comprising a plurality of image stream input interfaces claim 1 , the plurality of image stream input interfaces being in communication with the switching matrix and including the image stream input interface claim 1 , wherein at least two ...

Dynamically Determining A Primary Or Slave Assignment Based On An Order Of Cable Connection Between Two Devices

Methods, apparatuses, and computer program products for dynamically determining a primary or slave assignment based on an order of cable connection between two devices are provided. Embodiments include detecting, by a first device, insertion of one end of a cable into a port of the first device; determining, by the first device, whether a power signal is received from the cable at the port of the first device; if the power signal is received, performing, by the first device, a data transfer operation over the cable as a slave device to a second device that is coupled to the other end of the cable; and if the power signal is not received, performing, by the first device, a data transfer operation over the cable as a primary device to the second device that is coupled to the other end of the cable.

Supporting Multiple Channels Of A Single Interface

In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed.

COMMUNICATION CONTROL SYSTEM, SWITCHING NODE, COMMUNICATION CONTROL METHOD AND COMMUNICATION CONTROL PROGRAM

In a switching node, high-speed and advanced service protocol processing function is achieved by utilizing an external control server without affecting performance of conventional service protocol processing. Specifically, a forwarding engine has PCI express and an LAN interface. Depending on a type of an input packet, destination of the packet is switched to the PCI express side for conventional network service and to the LAN interface side for extended network service that cooperates with the external control server. A CPU having the PCI express and the LAN interface is provided ahead of the LAN interface. The CPU performs communication of service inquiry with the external control server at high speed via the LAN interface. After response from the control server is obtained, setting of the forwarding engine is performed through the PCI express. 1. A communication control system comprising:a switching node configured to execute conventional network service; anda control server configured to execute extended network service,wherein said switching node comprises:a first internal bus used for forwarding a frame for internal processing;a second internal bus for forwarding a frame for external transmission; anda forwarding engine configured to operate depending on a type of an input frame, to forward a frame regarding said conventional network service to said first internal bus for internal processing in said switching node, and to forward a frame regarding said extended network service to said second internal bus for utilizing said control server.2. The communication control system according to claim 1 ,wherein said switching node further comprises:a first processor configured to receive a frame from said forwarding engine through said first internal bus and to execute said conventional network service; anda second processor configured to receive a frame from said forwarding engine through said second internal bus, to perform processing related to said extended network ...

SYSTEM AND METHOD OF TRANSMITTING DATA BETWEEN DEVICES CONNECTED VIA A BUS DEFINING A TIME SLOT DURING TRANSMISSION FOR RESPONSIVE OUTPUT INFORMATION FROM BUS DEVICES

Techniques and devices for transmitting data and information via a bus are provided. According to these techniques, data is transmitted in units or frames together with information that is required or useful for one or more of the transmission and the use of the data. If desired, at least some of the units or frames include a time slot within which freely selectable devices can output onto the bus data representing freely selectable information at freely selectable points in time. 120-. (canceled)21. A first device adapted to transmit data to at least a second and third device interconnected via a bus , wherein the first device is adapted to:transmit, in units, data and information concerning at least one of a transmission of the data and a use of the data to one or more second devices to which the data does not concern, and one or more third devices to which the data does concern;form the units with at least one region defining a given time slot within which the second and third devices output onto the bus specific information and/or data; and a setting to determine whether and under which conditions the acknowledgement data are to be output within the given time slot;', 'a setting to determine which acknowledgement data is to be output within the given time slot; and', 'a setting to determine at which points in time within the given time slot the acknowledgement data is to be output., 'define, in the second and third devices that are configured to output acknowledgement data that acknowledges whether or not the data and information have been received by the second and third devices in a fault-free condition within the given time slot, at least one setting selected from the group consisting of22. The device of claim 21 , wherein the first device is adapted to determine the at least one setting before beginning transmission of the unit containing the given time slot.23. The device of claim 21 , wherein the first device is adapted to define the at least one setting ...

METHOD AND SYSTEM FOR COMMUNICATING WITH AND PROGRAMMING A SECURE ELEMENT

A method, device, and system are disclosed that enable the in-situ programming of an on-board secure element. A communication bus normally used to facilitate communications between the secure element and a microprocessor is borrowed to facilitate the in-situ programming with an off-board secure element. The microprocessor is disclosed to include the functionality to switch the configuration of the communication bus to enable the in-situ programming. 1. A method , comprising:determining, at a processor, that an off-board device is to become a master of an on-board secure element, the processor and on-board secure element being in communication with one another via a communication bus; andcontrolling one or more switches on the communication bus to replace the processor with the off-board device as a master to the on-board secure element.2. The method of claim 1 , further comprising:while the off-board device is the master to the on-board secure element, allowing the off-board device to program the on-board secure element;determining that the off-board device is done programming the on-board secure element; andcontrolling the one or more switches on the communication bus to replace the off-board device with the processor as the master to the on-board secure element.3. The method of claim 3 , wherein the off-board device is a removable secure element and the on-board secure element is an embedded secure element.4. The method of claim 1 , further comprising:shorting a clock of the off-board device with a clock of the on-board secure element.5. The method of claim 4 , further comprising:enabling the off-board device and the on-board secure element to have access to a data line on the communication bus; andexcluding the processor from using the data line while the off-board device and on-board secure element have access to the data line.6. The method of claim 5 , further comprising:monitoring, by the processor, a first reset value controlled by the off-board device; ...

System and Method for Providing PCIE over Displayport

An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed 120-. (canceled)21. An information handling system comprising:a processor configured to generate information;a video display subsystem interfaced with the processor and configured to process the information into video information for communication to a display;a host main link interfaced with video display subsystem and configured to couple to a display cable;a display configured to present the video information as visual images;a display main link interfaced with the display and configured to couple to the display cable;a display cable coupled at a first end to the host main link and at a second end to the display main link, the display cable configured to communicate the video information from the video display subsystem to the display across four serial links; anda peripheral coupled to the display and having associated peripheral information;wherein the display main link is further configured to communicate the peripheral information through the display cable to the host main link, the display main link and host main link cooperating to selectively assign some of the four serial links to communicate the peripheral information while the remaining of the four serial links communicate the video information.22. The information handling system of further comprising:a display receiver interfaced with the display main link and configured to receive the video information from the display cable;a peripheral transceiver interfaced with the display main link and configured to communicate peripheral information with the display cable; anda multiplexor disposed between the main link and the display receiver and the peripheral transceiver, the ...

APPARATUS AND METHODS TO COMMUNICATIVELY COUPLE FIELD DEVICES TO CONTROLLERS IN A PROCESS CONTROL SYSTEM

A disclosed example system includes a termination panel, and a shared bus on the termination panel. The shared bus is to removably receive a plurality of bases that removably receive modules to communicate with field devices, and communicatively couple the modules to an input/output card to exchange communications between the modules and a controller that is in communication with the input/output card via a second bus. 1. A system , comprising:a termination panel; and removably receive a plurality of bases that removably receive modules to communicate with field devices, and', 'communicatively couple the modules to an input/output card to exchange communications between the modules and a controller that is in communication with the input/output card via a second bus., 'a shared bus on the termination panel, the shared bus to2. The system of claim 1 , further comprising a socket rail having a plurality of termination module sockets at different locations of the socket rail claim 1 , the termination module sockets to removably receive the plurality of bases to communicatively couple the modules to the shared bus.3. The system of claim 2 , wherein the termination module sockets are assignable to any of the different types of field devices based on placements of the different modules at the different locations of the socket rail.4. The system of claim 1 , wherein at least a first one of the modules has an analog channel to communicate with a first one of the field devices claim 1 , and at least a second one of the modules having a digital channel to communicate with a second one of the field devices.5. The system of claim 4 , wherein any of the bases on the shared bus can receive either of the first or second one of the modules during an installation process.6. The system of claim 1 , wherein the shared bus is an Ethernet bus.7. The system of claim 1 , wherein the shared bus and the second bus use different communication protocols.8. The system of claim 1 , wherein the ...

Multi-Processor Architecture Implementing A Serial Switch And Method Of Operating Same

A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards. 1. A multi-processor architecture comprising:a plurality of blades, each including: a plurality of processors, a switch fabric that implements connections using point-to-point serial links, wherein the switch fabric is coupled to each of the plurality of processors, and packet processing logic coupled to the switch fabric; anda first external switch fabric that implements connections using point-to-point serial links, wherein the first external switch fabric is coupled to each switch fabric of the plurality of blades.2. The multi-processor architecture of claim 1 , further comprising a management processor coupled to the first external switch fabric.3. The multi-processor architecture of claim 2 , further comprising a processor accelerator coupled to the first external switch fabric.4. The multi-processor architecture of claim 1 , further comprising:one or more line cards that receive and transmit data packets; anda second external switch fabric coupling each of the one or more line cards to the packet processing logic of each of the plurality of blades.5. The multi-processor architecture of claim 4 , further comprising a third external switch fabric coupled to the first external switch fabric claim 4 , the one or more line cards and the second external switch fabric ...

METHOD AND A SYSTEM FOR POLLING AND PROCESSING DATA

The embodiments herein provide a method and system for polling and processing data. The method comprises computing a maximum time from a source after a last update time, waiting for a preset time to ensure that all transactions with respect to a change in a data is completed, querying for a plurality of changes after an elapse of the preset waiting time since the last update time and up to the maximum time, generating a time window, collecting a list of changes occurred within the generated time window, sending the collected list of changes for processing; and updating the processed data at the destination. The time window comprises a time interval between the last update time and the maximum time. 1. A method for polling and processing data from a source to a destination comprises:computing a maximum time from a source after a last update time;waiting for a preset time to ensure that all transactions with respect to a change in a data is completed , and wherein the preset time is set such that all transactions that are in flight at a time of lust query are completed;querying for a plurality of changes after an elapse of the preset waiting time since the last update time and up to the maximum time;generating a time window and wherein the time window comprises a time interval between the last update time and the maximum time collecting a list of changes occurred within the generated time window;sending the collected list of changes for processing; andupdating the processed data at the destination.2. A system for polling and processing a data from a source to a destination comprises:a connector framework and wherein the connector framework comprises two connector modules, a polling module and an adopter module;a processing manager and wherein the processing manager processes a poll event using a processing engine;a mapping manager and wherein the mapping manager maps a plurality of fields of the source to a corresponding fields of a destination;a recovery manager and ...

TIME AND EVENT BASED MESSAGE TRANSMISSION

A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus and to confirm a trigger condition. A module is configured to send a message over the communication bus when the trigger condition is confirmed. 1. A system , comprising:a module connected to a communication bus, the module comprising: receive a virtual schedule that provides a slot for sending a message over the communication bus, and', 'determine an actual time for sending the message in relation to the virtual schedule; and, 'a scheduler configured to send the message according to the actual time, and', 'determine whether to resend the message in accordance with a priority of the message and in response to a colliding message., 'wherein the module is configured to2. The system of claim 1 , wherein the scheduler is coupled to a virtual clock.3. The system of claim 1 , further comprising an actual clock claim 1 , wherein the actual time is further determined in accordance with the actual clock.4. The system of claim 1 , wherein the communication bus is configured to operate according to a controller area network (CAN) protocol.5. The system of claim 1 , further comprising a monitoring node connected to the communication bus claim 1 , wherein the monitoring node is configured to issue synchronization messages.6. An apparatus claim 1 , comprising: receive a virtual schedule, and', 'determine an actual time for sending a message in relation to the virtual schedule, wherein the virtual schedule includes a slot for sending the message over a communication bus; and, 'a scheduler configured to send the message according to the actual time, and', 'determine whether to resend the message in accordance with a priority of the message and in response to a colliding message., 'a transmitter configured to7. The ...

COMMUNICATING A MESSAGE REQUEST TRANSACTION TO A LOGICAL DEVICE

A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. 1. An apparatus comprising: assemble a completion header of a packet of a completion of a request, wherein the completion header is to include a routing identifier field to identify a device associated with the request; and', 'send the packet over an interconnect comprising one or more serial point-to-point links, wherein routing of the packet is based at least in part on values of the routing identifier field., 'an I/O module to2. The apparatus of claim 1 , wherein the header further is to include a completer identifier identifying a device that attempted to complete a request of the transaction.3. The apparatus of claim 2 , wherein the completer identifier is to include identification of a bus number claim 2 , a device number claim 2 , and a function number of the device.4. The apparatus of claim 1 , wherein the completer identifier comprises a field of at least sixteen ...

Graphics processing

In one embodiment, a computer system comprises two or more graphics cards, each graphics card comprising: a graphics processing unit and an interface. An interface of the first graphics card is coupled to an interface of the second graphics card for enabling communication between the first and second graphics cards. A cable couples the interface of the first graphics card with the interface of the second graphics card. The transmitting speed of data exchanging between graphics cards of the computer system is increased, and the arrangement of the PCB (printed circuit board) of the graphics card is simple and the cost thereof is low.

USB CLASS PROTOCOL MODULES

A computer system includes USB class protocol-aware modules for USB devices as part of a xHCI host controller. The protocol-aware modules serve as accelerators by implementing critical portions of the device class protocols, which includes fetching higher level protocol data directly from client buffers for transmission and delivering decoded data to client buffers on receipt; and emulating a register-based interface for the benefit of system software on the host computer. 1. A USB class aware protocol module operating with an xHCI controller to transfer data to a device attached to a Superspeed Universal Serial Bus 3.0 (USB) , the protocol module comprising:a set of registers and buffers including one or more registers and one or more buffers, the set modeling an interface for data transfer over a register oriented bus to the device, the set of registers and buffers receiving commands associated with data transfers to the device and the data for transfer to the device; process the data contained in the set of registers and buffers in accordance with the commands contained in the set of registers and buffers and a USB class protocol corresponding to the device and produce processed data, and', 'optimize the processed data for transfer over the USB to the attached device by the xHCI controller; and, 'one or more processors configured to'}transfer rings for directing the optimized and processed data over the USB to the is device under the control of the xHCI controller.2. The protocol module of wherein the one or more processors optimize the processed data by formatting the data as messages for transfer over the USB in accordance with an xHC protocol.3. The protocol module of wherein the one or more processors operate with an xHC driver to format the data.4. The protocol module of whereinthe device is a video device, andthe one or more processors process the data and commands contained in the set of registers and buffers by emulating a video device controller ...

Microcontroller resource sharing

A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

CONTROL OF DEVICE FEATURES BASED ON VEHICLE STATE

Methods and systems for a controlling device features based on vehicle state and device location are provided. Specifically, the device may be any type of electrical device capable of transmitting and/or receiving a signal (such as a phone, tablet, computer, music player, and/or other entertainment device). In some instances, the device may be associated with one or more vehicles. Although the device may be configured to run one or more applications, the functionality of the one or more applications may be controlled by a system associated with the vehicle. In some cases, this control may depend on the device application type, device location (either inside or outside of a vehicle), law, operator state, and/or vehicle state. 1. A method of controlling access to one or more features of a communication device associated with a vehicle , comprising:establishing, by a microprocessor executable feature control module, a connection with the communication device, wherein the feature control module is configured to receive input from at least one sensor;determining, by the feature control module, a location of the communication device relative to the vehicle; andcontrolling, via the feature control module and based at least partially on the location of the communication device, user access to one or more features of the communication device.2. The method of claim 1 , wherein the connection between the communication device and feature control module is established via manually registering the communication device with the feature control module.3. The method of claim 1 , wherein the connection between the communication device and feature control module is established via automatically registering the communication device with the feature control module.4. The method of claim 3 , wherein automatically registering the communication device further comprises storing in a memory an identifier associated with the communication device.5. The method of claim 1 , wherein the location ...

HARDWARE CONTROL INTERFACE FOR IEEE STANDARD 802.11

A standardized 802.11 hardware control interface may be provided such that a driver may communicate with any one or more of a variety of network adapters. 1. A method performed on a computing device , the method comprising exchanging information via a hardware control interface (“HCI”) between a network adapter and a driver of the network adapter , where the hardware control interface is configured for operating with a variety of different network adapters of different types , including the network adapter.2. The method of where the hardware control interface is configured for supporting at least a portion of a wireless communication standard.3. The method of where the hardware control interface comprises:a transmission control interface;a transmission status surface;a reception control interface; anda channel switching interface.4. The method of where the driver comprises the hardware control interface.5. The method of where the driver controls the network adapter according to at least a portion of a wireless communication standard.6. The method of where the wireless communication standard comprises at least one 802.11 standard.7. The method of where the hardware control interface is implemented as software.8. At least one computer storage media storing computer-executable instructions that claim 1 , when executed by a computing device claim 1 , cause the computing device to perform a method comprising method comprising exchanging information via a hardware control interface (“HCI”) between a network adapter and a driver of the network adapter claim 1 , where the hardware control interface is configured for operating with a variety of different network adapters of different types claim 1 , including the network adapter.9. The at least one computer storage media of where the hardware control interface is configured for supporting at least a portion of a wireless communication standard.10. The at least one computer storage media of where the hardware control ...

Method of debugging control flow in a stream processor

Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.

High availability and I/O aggregation for server environments

Methods and apparatus are provided for virtualizing port adapter resources such as network interface cards (NICs) used to connect servers to packet based networks. Resources are offloaded from individual servers onto a resource virtualization switch. Servers connected to the resource virtualization switch using an I/O bus connection share access to NICs. Redundancy can be provided using multipathing mechanisms implemented at individual servers or high availability mechanisms implemented at the resource virtualization switch. Switchover can occur between ports on the same port adapter, between ports on separate adapters, or between ports on separate resource virtualization switches. 135-. (canceled)36. A resource virtualization switch , comprising:an I/O bus switch connected to a plurality of external servers through a plurality of I/O bus ports, each of the plurality of external servers comprising a separate memory address space, the plurality of external servers including a first server running a first application and a second server running a second application;a plurality of network interface cards (NICs) connected to the PCI-Express bus switch, wherein the plurality of NICs are accessible to the plurality of servers as virtual NICs (VNICs), wherein a plurality of VNICs are assigned to the first application to allow for path redundancy in the event a particular NIC fails;a processor subsystem configured to initialize an internet protocol (IP) network connection through a first NIC regardless of whether any of the plurality of external servers are connected to the resource virtualization switch.37. The resource virtualization switch of claim 36 , wherein the first application accesses a particular VNIC as though it is accessing a particular NIC included in the first server.38. The resource virtualization switch of claim 36 , wherein the first application is operable to access the plurality of VNICs for load sharing.39. The resource virtualization switch of claim ...

I/O VIRTUALIZATION AND SWITCHING SYSTEM

Described herein is a system () having a virtualization and switching system configured to virtualize I/O devices () and perform switching of the I/O devices () and I/O requests. The virtualization and switching system () includes a peripheral virtualization controller (PVC) (), at least one device control module () connected to the PVC (), and at least one command parser (). The PVC () is configured to manage I/O virtualization and I/O command access of different I/O devices (). The device control module () is configured to store configuration and I/O device registers, implemented by the PVC () to enable virtualization of I/O devices (). The device control module () also implements the I/O command and switching logic to perform graceful handling of the I/O commands and virtualized I/O devices between multiple host processors (). 1. A method comprising:initializing one or more of least one configuration register set, and at least one device register set for a I/O device, wherein each of the at least one configuration register set and the at least one device register set correspond to a host processor from amongst a plurality of host processors; andproviding the initialized configuration registers and the device registers to the plurality of host processors for virtualization of the I/O device.2. The method as claimed in claim 1 , wherein the method further comprises:parsing requests from the plurality of host processors for the I/O device to identify command boundaries; andarbitrating between the requests from the plurality of host processors based at least on the identified command boundaries.3. The method as claimed in claim 2 , wherein the arbitrating further comprises virtually disconnecting the I/O device from a host processor based on the identified command boundaries.4. The method as claimed in claim 1 , wherein the method further comprises:assigning the I/O device to a first host processor from amongst the plurality of host processors to process a request ...

APPARATUS FOR COUPLING TO A USB DEVICE AND A HOST AND METHOD THEREOF

An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result. 1. An apparatus for coupling to a Universal Serial Bus (USB) device and a USB host , the apparatus comprising:a memory, storing one or more descriptor entries, said one or more descriptor entries; anda controller, coupled to said memory, configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result,wherein the controller enables or disables a link path between the USB host and the USB device according the comparing result.2. The apparatus as recited in claim 1 , wherein the controller enables the link path when the comparing result indicates that the descriptor matches to the specific descriptor entry.3. The apparatus as recited in claim 1 , wherein claim 1 , when the link path is enabled and the comparing result indicates that the USB device has remote wakeup capability claim 1 , the controller maintains the link path when the USB host is operated in a power saving mode.4. The apparatus as recited in claim 1 , wherein the controller further issues a reset command to be transmitted to the USB device after obtaining the descriptor claim 1 , thereby allowing for normal enumeration procedures by the said USB host.5. The apparatus as recited in claim 1 , wherein said controller disables the link path when the comparing result indicates that the descriptor does not match to any one of said one or more descriptor entries.6. The ...

MULTI-ROOT INPUT OUTPUT VIRTUALIZATION AWARE SWITCH

A system having a multi protocol multi-root aware (MP-MRA) switch () configured to route data between multiple host processors () and multiple I/O devices () is described herein. In said embodiment, the MP-MRIOV aware switch includes a switch routing module (), at least one upstream adaptive module (), and at least one downstream adaptive module (). The upstream adaptive module () is configured to map information in a primary communication protocol to a intermediate communication protocol at which the switch routing module operates. Further, the downstream adaptive module () maps the intermediate communication protocol to a secondary communication protocol at which the I/O device () operates. 1. A method for translating information in a multi-host computing system comprising:receiving information, from a host processor, from amongst a plurality of host processors, in a primary protocol; wherein at least two host processors from amongst the plurality of host processors form different root complexes, and wherein the primary protocol for at least one host processor from amongst the plurality of host processors is non Peripheral Component Interconnect express (PCIe);translating the information from the primary protocol to an intermediate protocol, wherein the intermediate protocol is implemented by a multi-root aware switch; andtranslating further, the information from the intermediate protocol to a secondary protocol, wherein the secondary protocol is associated with an I/O device coupled to at least one of the plurality of host processors.2. The method as claimed in claim 1 , wherein the translation comprises mapping one or more of address spaces claim 1 , completion status claim 1 , traffic classes claim 1 , atomic operations claim 1 , and split completions from the primary protocol to the secondary protocol claim 1 , and wherein the secondary protocol is associated with the I/O device coupled to at least one of the plurality of host processors.3. The method as ...

MULTI-PROCESSOR ELECTRONIC SYSTEMS

Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral. 2. The system as claimed in claim 1 , wherein the plurality of processors comprises at least one of homogeneous and heterogeneous processors.3. The system as claimed in claim 1 , wherein each of the plurality of processors is configured to run a operating system claim 1 , such that a plurality of operating systems of the system are at least one of homogeneous and heterogeneous operating systems.4. The system as claimed in claim 3 , wherein the system further facilitates selection of one of the plurality of operating systems as a primary operating system.5. The system as claimed in claim 3 , wherein the system further facilitates seamless switching from a first operating system of the plurality of operating systems to a second operating system of the plurality of operating systems.6. (canceled)7. The system as claimed in claim 3 , wherein the system further facilitates concurrent operation of the plurality of operating systems.811-. (canceled)12. The system as claimed in claim 1 , wherein the system is further configured to facilitate at least one of a serial sharing and a ...

DATA TRANSFERRING APPARATUS AND DATA TRANSFERRING METHOD

A data transferring apparatus includes a receiving unit configured to receive a transfer request containing attribute information that indicates a type of data transfer, a buffer configured to store the transfer requests received by the receiving unit, a storing unit configured to associate the attribute information with a first identifier and store the attribute information, and a sending unit configured to preferentially transmit, out of the plurality of transfer requests stored in the buffer, a transfer request containing attribute information that corresponds to the attribute information stored in the storing unit, wherein the sending unit is configured to transmit the first identifier associated with the attribute information that corresponds to the attribute information contained in the transfer request in place of the attribute information of the transfer request. 1. A data transferring apparatus comprising:a receiving unit configured to receive a transfer request containing attribute information that indicates a type of data transfer;a buffer configured to store a plurality of transfer requests received by the receiving unit;a storing unit configured to associate the attribute information with a first identifier and store the attribute information; anda sending unit configured to preferentially transmit, out of the plurality of transfer requests stored in the buffer, a transfer request containing attribute information that corresponds to the attribute information stored in the storing unit,wherein the sending unit is configured to transmit the first identifier associated with the attribute information that corresponds to the attribute information contained in the transfer request in place of the attribute information of the transfer request.2. The data transferring apparatus according to claim 1 , wherein the sending unit is configured to add claim 1 , to the transfer request claim 1 , a second identifier indicating whether the first identifier is included ...

LOW LATENCY, HIGH BANDWIDTH DATA COMMUNICATIONS BETWEEN COMPUTE NODES IN A PARALLEL COMPUTER

Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core. 1. A method for low latency , high bandwidth data transfers between compute nodes in a parallel computer , the method comprising:receiving, by an origin direct memory access (‘DMA’) engine, an acknowledgement of an request to send (‘RTS’) message from a target compute node; andtransferring, by the origin DMA engine in response to receiving the acknowledgement of the RTS message, any remaining portion of data in a buffer for transfer to the target compute node, to the target compute node using a direct put operation, including initiating the direct put operation without invoking an origin processing core on the origin compute node, the direct put operation specifying the other end of the buffer from which to begin transferring the remaining portion of the data.2. The method of wherein initiating the direct put operation without invoking a processing core further comprises:receiving a direct put data descriptor for a remote get operation from the target compute node; andinjecting the direct put data descriptor for the remote get operation into a high priority injection FIFO buffer ...

Negotiation Between Multiple Processing Units for Switch Mitigation

A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus. 124.-. (canceled)25. A system , comprising:a graphical processing unit (GPU); anda microcontroller coupled to the GPU through a bus; receive a bus request from the GPU;', 'grant the bus request to the GPU;', 'receive a request for a switch from the GPU;', 'grant the request for the switch to the GPU., 'wherein the microcontroller is configured to26. The system of claim 25 , wherein the microcontroller includes a register.27. The system of claim 26 , wherein receive a bus request from the GPU comprises the GPU writing a value into a first bit of the register.28. The system of claim 25 , wherein grant the bus request to the GPU comprises completing any current transactions on the bus.29. The system of claim 26 , wherein grant the bus request to the GPU comprises the microcontroller writing a value into a second bit of the software register.30. A system claim 26 , comprising:a display device;a graphical processing unit (GPU);a switch coupled between the display device and the GPU, through a bus; and send data through the bus to the display device;', 'receive a request from the GPU for access to the bus;', 'complete pending transactions on the bus; and', 'closing the switch responsive to completing the pending transactions., 'a microcontroller coupled to the display device through the bus, wherein the microcontroller is configured to31. The system of claim 30 , wherein the bus comprises a clock line and a data line.32. The system of claim 30 , wherein send data through the bus comprises activating one or more field-effect transistors (FETs) coupled to the bus.33. The ...

Serial Interface for FPGA Prototyping

In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component.

Method and device for transmitting data having a variable bit length

A method for serially transmitting data in a bus system having at least two bus users, which exchange data frames over the bus, the bus users deciding which data frames they receive, as a function of an identifier, the data frames having a logic structure according to the CAN standard, ISO 11898-1, the temporal bit length (L L) inside of a data frame being able to assume at least two different values, the temporal bit length (L) for at least one first, specified or specifiable region within the data frame meeting the requirements of the CAN standard, ISO 11898-1, the temporal bit length (L) in at least one second, specified or specifiable region being reduced in comparison with the first region, and a change in the temporal bit length being signaled by the sender, using an identification () contained in the same or one of the preceding data frames. 118-. (canceled)19. A method for serially transmitting data in a bus system having at least two bus users , which exchange data frames over the bus , the bus users deciding which data frames they receive , as a function of an identifier , the method comprising:reducing the temporal bit length in at least one second, specified or specifiable region in comparison with the first region; andsignaling a change in the temporal bit length by the sender, using an identification contained in the same or one of the preceding data frames;wherein the data frames have a logic structure according to the CAN standard, ISO 11898-1, wherein the temporal bit length inside of a data frame may assume at least two different values, the temporal bit length for at least one first, specified or specifiable region within the data frame meeting the requirements of the CAN standard, ISO 11898-1.20. The method of claim 19 , wherein the identification is situated inside the first specified or specifiable region of the indicated data frame.21. The method of claim 19 , wherein the first region includes at least the SOF bit and the arbitration field.22. ...

TRANSPONDER, METHOD AND RECORDING MEDIUM CONTAINING INSTRUCTIONS FOR CONTROLLING THE SAME

A transponder connected to a master, a transmission module and a reception module, the transponder including: a memory which stores a table indicating whether or not a command from the master is executable, wherein the table including: type information indicating a type of the command; and first status information including at least one of: a transmission status indicating a communication status of the transmission module; and a reception status indicating a communication status of the reception module; an acquiring unit that acquires second status information including at least one of: a current transmission status indicating a current communication status of the transmission module; and a current reception status indicating a current communication status of the reception module; a judging unit that judges, in response to a received command received from the master, whether or not the received command is executable using the table and the second status information. 1. A transponder connected to a master , a transmission module and a reception module , the transponder comprising: type information indicating a type of the command; and', a transmission status indicating a communication status of the transmission module; and', 'a reception status indicating a communication status of the reception module;, 'first status information comprising at least one of], 'wherein the table comprises, 'a memory which stores a table indicating whether or not a command from the master is executable,'} a current transmission status indicating a current communication status of the transmission module; and', 'a current reception status indicating a current communication status of the reception module; and, 'an acquiring unit that acquires second status information comprising at least one ofa judging unit that judges, in response to a received command received from the master, whether or not the received command is executable using the table and the second status information.2. The ...

SWITCH APPARATUS SWITCHING BETWEEN BASIC INPUT OUTPUT SYSTEM CHIP AND DIAGNOSTIC CARD

A switch apparatus which can switch between two different booting chips includes a first connector, a platform controller hub (PCH) chip, a first basic input output system (BIOS) chip, a switch circuit, and a diagnostic card. The diagnostic card includes a second connector operable to be plugged into the first connector, and a second BIOS chip. When the switch circuit receives a high level control signal from the second BIOS chip, the switch circuit outputs a high level switch signal to first and second trapping pins of the PCH chip, to select the second BIOS chip to bootstrap the motherboard. When the switch circuit does not receive a high level control signal, the switch circuit outputs a low level signal to the first and second trapping pins of the PCH chip, to select the first BIOS chip to bootstrap the motherboard. 1. A switch apparatus , comprising:a first connector arranged on a motherboard;a platform controller hub (PCH) chip arranged on the motherboard and coupled to the first connector through a low pin count (LPC) bus, the PCH chip comprising a first trapping pin and a second trapping pin;a first basic input output system (BIOS) chip arranged on the motherboard, and coupled to the PCH chip through a serial peripheral interface (SPI) bus;a switch circuit arranged on the motherboard; and a second connector being detachably plugged into the first connector; and', 'a second BIOS chip coupled to the second connector, to output a high level control signal through the second connector;, 'a diagnostic card, comprisingwherein the switch circuit receives the high level control signal from the second BIOS chip through the first connector in response to the second connector being plugged into the first connector, the switch circuit outputs high level switch signals to the first and second trapping pins of the PCH chip, to select the second BIOS chip to bootstrap the motherboard; wherein the switch circuit does not receive the high level control signal in response to ...

USB KEY DEVICE AND METHOD FOR REALIZING INTELLIGENT CARD COMMUNICATION USING USB INTERFACE

A USB key device and method for realizing the intelligent card communication using the USB interface are provided. The USB key device includes: a USB interface (), which is electrically connected with a safety chip () via a USB interface circuit () and an IO interface circuit () respectively; a clock () and a clock frequency setting unit (), which are electrically connected with the security chip (); in which the pin D+ of the USB interface () is electrically connected with the pin D+ of the USB interface circuit (), the pin D− of the USB interface () is electrically connected with the pin D− of the USB interface circuit (); the IO interface circuit () comprising a bilateral interface and an input interface; in which the pin D+ of the USB interface () is electrically connected with one of the interfaces of the IO interface circuit (), and the pin D− of the USB interface () is electrically connected with another interface of the IO interface circuit () except the connected pin; an interface processing unit (), which is used for setting the bilateral interface of the IO interface circuit () on input mode, judging the level of the bilateral interface, and turning on or off the USB interface circuit () according to the level of the bilateral interface. 1. A USB key device , comprising:a security chip;a clock and a clock frequency setting unit connected with the security chip;a USB interface circuit with a first D+ pin and a first D− pin, connected with the security chip;an IO interface circuit with a bidirectional interface and a first input interface, connected with the security chip;a USB interface with a second D+ pin and a second D− pin, in which the second D+ pin is connected with the first D+ pin of the USB interface circuit, the second D− pin is connected with the first D− pin of the USB interface circuit, the second D+ pin is connected with one of the bidirectional interface and the first input interface, and the second D− pin of the USB interface is connected ...

NETWORK ON CHIP (NOC) WITH QOS FEATURES

Quality-of-Service (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC). 1. A system for transmitting priority information in an on-chip-interconnect , the system comprising:a plurality of signal carriers for carrying an in-band priority signal an out-of-band priority signal and a third priority signal;an arbitration point comprising a first input and a second input; andwherein the arbitration point selects the first input over the second input when a priority indicated by the in-band priority signal or a priority indicated by the out-of-band priority signal is greater than a priority indicated by the third priority signal.2. The system of claim 1 , wherein the priorities of at least two of the in-band priority signal claim 1 , the out-of-band priority signal and the third priority signal are bar-graph encoded.3. A method of transmitting priority information at a transport layer interface of an on-chip-interconnect comprising:receiving an in-band signal;receiving an out-of-band signal; andprocessing a downstream signal that is assigned a priority that is the greater of a priority indicated by the in-band signal and a priority indicated by the out-of-band signal.4. The method of claim 3 , wherein processing the downstream signal comprises:arbitrating the downstream signal based at least in part on the assigned priority that is the greater of the priority indicated by the in-band signal and the priority indicated by the out-of-band signal.5. An on-chip- ...

Administering Connection Identifiers For Collective Operations In A Parallel Computer

Administering connection identifiers for collective operations in a parallel computer, including prior to calling a collective operation, determining, by a first compute node of a communicator to receive an instruction to execute the collective operation, whether a value stored in a global connection identifier utilization buffer exceeds a predetermined threshold; if the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold: calling the collective operation with a next available ConnID including retrieving, from an element of a ConnID buffer, the next available ConnID and locking the element of the ConnID buffer from access by other compute nodes; and if the value stored in the global ConnID utilization buffer exceeds the predetermined threshold: repeatedly determining whether the value stored in the global ConnID utilization buffer exceeds the predetermined threshold until the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold. 1. A method of administering connection identifiers for collective operations in a parallel computer , the method comprising:prior to calling a collective operation, if a value representing a number of connection identifiers in use and stored in a global connection identifier (‘ConnID’) utilization buffer does not exceed a predetermined threshold, calling the collective operation with a next available ConnID including, atomically: retrieving, from an element of a ConnID buffer, the next available ConnID and locking the element of the ConnID buffer from access by other compute nodes; andif the value stored in the global ConnID utilization buffer exceeds the predetermined threshold: repeatedly determining whether the value stored in the global ConnID utilization buffer exceeds the predetermined threshold until the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold.2. The method of wherein determining whether ...

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a first module that issues a first transaction from a first interface unit to be a bus master, a second module that includes a second interface unit to be a bus slave and a third interface unit to be a bus master, and issues a second transaction in response to the first transaction, a third module that receives the second transaction by a fourth interface unit to be a bus slave, a bus master stop request control unit that asserts a bus master stop request and completes an assertion process in response to assertion of a bus master stop acknowledgement, and a code addition unit that adds to the first transaction a compulsory process request code for forcing issuance of the second transaction regardless of the bus master stop request. 1. A semiconductor device including a plurality of interface units that are connected via a bus and assigned with either one of a bus master that issues a transaction and stops issuing the transaction in response to a bus master stop request and a bus slave that receives the transaction , the semiconductor device comprising:a first module that includes a first interface unit functioning as the bus master and issues a first transaction;a second module that includes a second interface unit functioning as the bus slave and a third interface unit functioning as the bus master, and issues a second transaction in response to the first transaction;a third module that includes a fourth interface unit functioning as the bus slave and receives the second transaction;a bus master stop request control unit that asserts the bus master stop request and, in response to assertion of a bus master stop acknowledgement corresponding to the bus master stop request, completes an assertion process of the bus master stop request; anda code addition unit that adds a compulsory process request code to the first transaction, whereinthe second module issues the second transaction while asserting the ...

Interface for Bridging Out-of-Band Information from a Downstream Communication Link to an Upstream Communication Link

A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

HETEROGENEOUS PARALLEL SYSTEMS FOR ACCELERATING SIMULATIONS BASED ON DISCRETE GRID NUMERICAL METHODS

A system for executing a given scientific code using a suitable finite-volume or finite-element solver for a large dataset represented as a grid, comprising a plurality of equal computing nodes interconnected by node communication means and a parallel computing software package for distributing and controlling the execution in sub-grids among said computing nodes; each computing node comprising at least a CPU-based first processing means and a FPGA-based second processing means interconnected by a bus; said package being configured for the simultaneous execution of at least one first solver process (which is fully executed in a first processing means) and one second solver process (which is fully executed in a second processing means) in each computing node for one sub-grid of said grid and for managing the exchange of boundary data with the solver processes that solve neighbour sub-grids. 1. A system for executing a given scientific code using a suitable finite-volume or finite-element solver for a large dataset represented as a grid , comprising a plurality of equal computing nodes and a front-end node , all of them interconnected by node communication , and a parallel computing software package for distributing the execution of said scientific code in sub-grids of said grid among said computing nodes , wherein:each computing node comprises at least a first processor and a second processor, which are interconnected by a bus, said first processor being a CPU-based processor and said second processor being a FPGA-based processor;said parallel computing software package being configured for simultaneous execution of at least one first solver process and one second solver process of said scientific code in each computing node, where each solver process solves at least one sub-grid of said grid, and for managing the exchange of boundary data between the first and second solver processes that compute neighbour sub-grids after each step of the solver;wherein said first ...

Bus Arbitration for a Real-Time Computer System

In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

MOTHERBOARD COMPRISING EXPANSION CONNECTOR

A motherboard includes a CPU, an expansion connector detachably connected to an expansion card, a controller, and a switch. The switch is electronically connected to the CPU, the expansion connector and the controller, the switch may be made to switch connections between the expansion connector and one of the CPU and the controller, according to a type of the expansion card which is installed. 1. A motherboard , comprising:a central processing unit (CPU);an expansion connector detachably connected to an expansion card;a controller; anda switch electronically connected to the CPU, the expansion connector and the controller, the switch receiving a first bus signal and a second bus signal from the CPU and the controller respectively, and selectively transmitting one of the first and second bus signals to the expansion card, according to a type of the expansion card.2. The motherboard of claim 1 , wherein the expansion connector is a PCIE connector that selectively connects to an expansion card of the PCIE type or the SAS type.3. The motherboard of claim 1 , further comprising a switching control unit claim 1 , wherein the switching control unit comprises a jumper and a jumper block electronically connected to the switch claim 1 , the jumper block comprises a plurality of jumper pins claim 1 , the jumper selectively constructs an electronic connection between different two jumper pins according to the type of the expansion card claim 1 , to control the switch to switch signal paths of the bus signals.4. The motherboard of claim 1 , wherein the first bus signal is a peripheral component interconnect-express (PCIE) signal claim 1 , and the second bus signal is a serial attached SCSI (SAS) signal.5. The motherboard of claim 4 , wherein the CPU transmits direct media interface (DMI) signal to the controller.6. The motherboard of claim 1 , wherein the controller is a platform controller hub (PCH).7. A motherboard claim 1 , comprising:a CPU;an expansion connector detachably ...

Memory mapped input/output bus address range translation

In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

INTERFACE FOR MODULAR INPUT/OUTPUT AND DATA ACQUISITION SYSTEMS

A modular I/O and data acquisition system includes a plurality of connection ports for receiving mating connectors of an interconnecting I/O module, the mating connectors configured to mate with a plurality of contacts in an associated connection port. The plurality of ports is mounted in an equipment rack. The equipment rack includes wiring interconnections, power buses and data buses for communication with automation devices. Connection ports include an interface circuit. The interface circuit includes a power source, a pair of USB data signal lines transmitting a USB data signal, and an optional video channel independent from the USB data signal. 1. An interface circuit for a modular input/output (I/O) human-machine interface (HMI) and data acquisition system , the interface circuit comprising:a connection port having a power source, a pair of USB data signal lines transmitting a USB data signal.2. The circuit of claim 1 , wherein the connection port is an I/O port claim 1 , the I/O port comprising a plurality of terminals connectable to a computer or automation system.3. The circuit of claim 1 , further comprising a first pair of terminals in electrical communication with a voltage source at a predetermined voltage level.4. The circuit of claim 3 , wherein the predetermined voltage level is 24 volts.5. The circuit of claim 3 , wherein the voltage source is the HMI or data acquisition system.6. The circuit of claim 3 , wherein the first pair of terminals is connectable to a connector of an external device.7. The circuit of claim 6 , wherein the external device comprises at least one of an input/output (I/O) claim 6 , a control device claim 6 , or a communications device.8. The circuit of claim 3 , further comprising a second pair of terminals in electrical communication with a common terminal of the voltage source.9. The circuit of claim 8 , further comprising a third set of terminals in electrical communication with a USB common signal bus of the computer or ...

Inter-component communication including slave component initiated transaction

Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed. A component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. Other embodiments may be disclosed or claimed.

CIRCUIT AND METHOD FOR PIPE ARBITRATION USING AVAILABLE STATE INFORMATION AND ARBITRATION

Provided is an arbitration circuit included in a host controller that can be connected to a plurality of external devices via a plurality of pipe control circuits. The arbitration circuit includes an available state information storage unit that stores available state information. The available state information indicates an available state of the plurality of pipe control circuits and is updated by the pipe control circuit by a unit of data transfer of a predetermined communication size. The arbitration circuit further includes an arbitration unit that refers to the available state information storage unit, selects the arbitrary pipe control circuit from the available pipe control circuit, and allocates the selected pipe control circuit to the external device, while updating the available state information storage unit. 1. A host controller comprising:a first port through which data communication is performed, wherein a first device is connected to the first port;a plurality of control circuits;a schedule control unit configured to output endpoint information of an external device to be connected;an arbitration circuit configured to, when an endpoint to which data is to be transmitted is included in the endpoint information, inform one of the plurality of control circuits of device information included in the endpoint information; andan informed control circuit configured to perform data communication with the first device through the first port based on the device information.2. The host controller according to claim 1 ,wherein the informed control circuit is further configured to inform the arbitration circuit that a data transfer of a predetermined size has been finished by using a data transfer end notification in data communication with the first device,wherein the arbitration circuit is further configured to obtain the endpoint information again and inform one of the plurality of control circuits of device information included in the endpoint information.3. ...

REMOTE ACCESS APPLIANCE WITH COMMUNICATION PROTOCOL AUTOSENSING FEATURE

A remote access appliance (“appliance”)is disclosed which includes an autosensing subsystem that automatically senses when an Ethernet device or a serial device has been connected to it. The appliance then automatically configures one or more internal components to operate with the sensed/connected Ethernet device or serial device. When a serial device connection is detected, the appliance is further able to automatically detect which one of two different, predetermined pinout configurations is being used by the serial device, and to automatically configure one or more internal components to accommodate the detected pinout configuration. 1. A remote access appliance adapted to sense a communications protocol of a device coupled to the remote access appliance via a cable , the appliance comprising:a jack forming a port to which either an Ethernet device or a serial device may be coupled, the jack including a plurality of pins;an autosensing subsystem in communication with selected ones of the pins of the jack and configured to detect when signals on specific ones of said pins are present when either an Ethernet device or a serial device is coupled to the jack via the cable, to thus indicate the presence of either the Ethernet device or the serial device; anda control logic subsystem responsive to the autosensing subsystem that controls at least one component of the autosensing subsystem so that the signals at the jack are handled as either Ethernet protocol signals or as serial protocol signals.2. The appliance of claim 1 , wherein the autosensing subsystem further includes a first switching component and a second switching component controlled by the control logic subsystem claim 1 , the first and second switching components selectively coupling signals at the pins of the jack to one of an Ethernet transformer or a serial transceiver.3. The appliance of claim 1 , further comprising a plurality of power switches claim 1 , responsive to the control logic subsystem ...

Transaction routing device and method for routing transactions in an integrated circuit

A transaction routing device (e.g. an interconnect) for routing transactions in an integrated circuit includes arbitration circuitry for performing arbitration between a plurality of candidate transactions using attribute values associated with the candidate transactions. Candidate transactions are selected for routing to a destination device in dependence on the arbitration. In a cycle in which a new candidate transaction is received, the arbitration is performed using a default attribute value as the attribute value for the new transaction. Meanwhile, the actual attribute value is stored to an attribute storage unit. In a following processing cycle, if the new candidate transaction has not yet been selected for muting, then the arbitration is performed using the actual attribute value stored in the storage unit.

STORAGE MEDIUM STORING INPUT/OUTPUT SETTING PROGRAM, STORAGE MEDIUM STORING OUTPUT SETTING PROGRAM, AND DATA PROCESSING APPARATUS

A non-transitory computer readable medium stores instructions that, when executed, cause a data processing apparatus, which includes a first input/output section and which is driven by a battery, to: judge whether the first input/output section is set as the input/output section; judge whether the remaining battery level of the battery is not less than a first reference remaining level; judge whether the data processing apparatus includes a second input/output section requiring a power consumption lower than that of the first input/output section; and switch or output a notification to switch the input/output section from the first input/output section to the second input/output section, in a case that the first input/output section is set as the input/output section; that the remaining battery level is less than the first reference remaining level; and that the data processing apparatus includes the second input/output section. 1. A non-transitory computer readable medium storing instructions that , when executed , cause a data processing apparatus , which includes a first input/output section for performing input/output of a data and which is driven by a battery , to:judge whether the first input/output section is set as the input/output section used for the input/output of the data;judge whether a remaining battery level of the battery is not less than a first reference remaining level;judge whether the data processing apparatus includes a second input/output section requiring a power consumption which is used for the input/output of the data and which is lower than that of the first input/output section, in a case that the data processing apparatus judges that the first input/output section is set as the input/output section used for the input/output of the data and that the remaining battery level is less than the first reference remaining level; andswitch the input/output section from the first input/output section to the second input/output section or output ...

OUTPUT INPUT CONTROL APPARATUS AND CONTROL METHOD THEREOF

An output input (I/O) control apparatus and a control method thereof are provided. The I/O control apparatus includes an interface control unit, a read-only memory, a random access memory, a multiplexer and a micro-process unit. The interface control unit is coupled to a memory apparatus through a bus, and the memory apparatus is external to the I/O control apparatus. The read-only memory stores judgment codes. The multiplexer is controlled by the micro-process unit to switch to the interface control unit, the read-only memory or the random access memory. When the bus is not busy, the micro-process unit can read data from the memory apparatus. When the bus is occupied and busy, the micro-process unit can read and execute codes from the read-only memory or the random access memory so as to avoid computer system instability or thermal damage. 1. An output input (I/O) control apparatus , comprising:an interface control unit, externally coupled to a memory apparatus through a bus;a read-only memory, storing judgment codes;a random access memory;a multiplexer, configured to switch to the interface control unit, the read-only memory or the random access memory; anda micro-process unit, coupled to the interface control unit and the multiplexer, and the micro-process unit controlling where the multiplexer is switched to.2. The I/O control apparatus according to claim 1 , wherein when the I/O control apparatus is powered on claim 1 , the multiplexer is switched to the read-only memory by default claim 1 , the micro-process unit reads and executes the judgment codes so that the multiplexer is switched to the memory apparatus by the micro-process unit through the interface control unit claim 1 , and the micro-process unit reads a data stored in the memory apparatus.3. The I/O control apparatus according to claim 2 , wherein when the interface control unit is aware that an electronic apparatus from the external is about to occupy the bus claim 2 , the interface control unit ...

Signal amplifier circuit for usb port

A signal amplifier circuit for USB port includes a USB controller, an amplifier circuit, a USB port and a signal regulator circuit. The USB controller includes a super speed transmitter differential pair and a super speed receiver differential pair. The amplifier circuit includes two first input terminals, two second input terminals, two first output terminals, and two second output terminals. The USB port includes two first differential signal receiving terminals and two first differential signal transmitting terminals. The super speed transmitter differential pair and the super speed receiver differential pair are electrically connected to the first input terminals and the second output terminals. The first output terminals and the second input terminals are electrically connected to the first differential signal receiving terminals and the first differential signal transmitting terminals. The signal regulator circuit regulates amplitude and jitter of differential signals amplified by the amplifier circuit.

Integer and Half Clock Step Division Digital Variable Clock Divider

A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

INFORMATION PROCESSING SYSTEM

An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device. 1. An information processing system comprising:a CPU that is connected to a bus;a device that is connected to the bus;a memory that is accessed by the CPU or the device; anda power mode control circuit that sets a power consumption mode, whereinthe power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device.2. The information processing system according to claim 1 , whereinthe power mode control circuit sets a low power consumption mode when the first information indicates a cache hit of the cache memory and the second information indicates the non-activated state.3. The information processing system according to claim 1 , whereinthe power mode control circuit sets a normal mode when the first information indicates a cache hit of the cache memory and the second information indicates the activated state.4. The information processing system according to claim 1 , whereinthe power mode control circuit sets the normal mode when the first information indicates a cache miss of the cache memory and the second information indicates the non-activated state.5. The information processing system according to claim 1 , whereinthe power mode control circuit, when the first information indicates a cache miss of the cache memory and the second information indicates the activated state, sets the power ...

Master-slave interface

A bus interface couples a master device and one or more slave devices. Upon detecting a condition on the bus, one or more of the slave devices may force an extension of the bus condition for a predetermined time period. The forced extension may comprise forcing a voltage level, causing other devices on the bus to change modes. A master on the bus may detect an out-of-variance bus condition and, in response, take action to change the bus state to a stable condition. The bus interface may include power contacts and a single-wire bus for communicating between a host device and one or more battery packs.

OPERATION ANALYSIS APPARATUS, OPERATION ANALYSIS METHOD, AND COMPUTER PROGRAM PRODUCT

An image forming apparatus includes a storage unit, an arbitration unit that controls access to the storage unit, and a plurality of image processing units that are connected to the arbitration unit and access the storage unit via the arbitration unit. And, an operation analysis apparatus includes: an access monitoring unit monitoring which of the image processing units the arbitration unit permits access to the storage unit; a log generation unit generating, in response to the fact that the access monitoring unit detects that the image processing unit with access permitted has been switched, information on the image processing unit with access permitted as a log; a log storage unit storing therein the generated log; and a remaining capacity determination unit determining whether the storage capacity of the log storage unit after storing the log has become equal to or smaller than a particular capacity. 1. An operation analysis apparatus for analyzing operation of an arbitration unit included in an image forming apparatus comprising a storage unit , the arbitration unit configured to control access to the storage unit , and a plurality of image processing units configured to be connected to the arbitration unit , access the storage unit via the arbitration unit , and perform respective different pieces of image processing on image data , the operation analysis apparatus comprising:an access monitoring unit configured to monitor which of the image processing units the arbitration unit permits access to the storage unit;a log generation unit configured to, in response to the fact that the access monitoring unit detects that the arbitration unit has switched the image processing unit with access to the storage unit permitted, generate information on the image processing unit with access permitted as a log;a log storage unit configured to store therein the generated log; anda remaining capacity determination unit configured to determine whether the storage capacity of ...

Sas fabric discovery

An example method of the present disclosure includes (i) creating, by a first serial attached SCSI (SAS) switch, a first topology map describing a portion of a SAS fabric associated with the first SAS switch; (ii) receiving, at the first SAS switch and from a second SAS switch, a second topology map describing a portion of the SAS fabric associated with the second SAS switch; and (iii) merging, by the first SAS switch, the first topology map and the second topology map to produce a consolidated topology map of the SAS fabric.

IMAGE PROCESSING APPARATUS

An image processing apparatus capable of controlling data transmission between a plurality of bus masters and a memory, includes a bandwidth-limitation storing unit which calculates a memory bandwidth-limitation setting value for each of the bus masters corresponding to the combination of the operating statuses of the bus masters based on a bandwidth-limitation table which stores memory bandwidth-limitation setting values of the bus masters, respectively, for each of the combinations of the operating statuses of the bus masters; a bus adjustment unit connected between the plurality of bus masters and the memory, which limits the data transmission for a bus master whose memory bandwidth occupancy ratio obtained by monitoring the operating statuses of the bus masters, reaches a respective set memory bandwidth-limitation setting value; and a control unit which dynamically sets the calculated memory bandwidth-limitation setting value for each of the bus masters in the bus adjustment unit. 1. An image processing apparatus capable of controlling data transmission including image data between a plurality of bus masters and a memory , comprising:a bandwidth-limitation storing unit which calculates a memory bandwidth-limitation setting value for each of the bus masters corresponding to the combination of the operating statuses of the bus masters obtained as a result of monitoring the operating statuses of the bus masters based on a bandwidth-limitation table which stores memory bandwidth-limitation setting values of the bus masters, respectively, for each of the combinations of the operating statuses of the bus masters;a bus adjustment unit connected between the plurality of bus masters and the memory, which limits the data transmission for a bus master whose memory bandwidth occupancy ratio obtained as a result of monitoring the operating statuses of the bus masters, reaches a respective set memory bandwidth-limitation setting value; anda control unit which dynamically sets ...

GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL

An enhanced general input/output communication architecture, protocol and related methods are presented. 1. An apparatus comprising: identify an allocated amount of bandwidth for an isochronous transaction; and', 'send a packet associated with the isochronous transaction to a device over a virtual channel of a differential, point-to-point serial data link based on the allocated amount of bandwidth., 'logic to2. The apparatus of claim 1 , wherein the link comprises at least one of a physical layer to support a Peripheral Component Interconnect Express (PCIe) protocol layer and a physical layer including one or more other protocols.3. The apparatus of claim 1 , wherein the link comprises a PCIe-compliant data link.4. The apparatus of claim 1 , wherein identifying the allocated amount of bandwidth includes identifying a virtual timeslot corresponding to the amount of bandwidth.5. The apparatus of claim 4 , wherein the virtual timeslot has a set duration of time and one isochronous request is permitted per virtual timeslot.6. The apparatus of claim 4 , wherein a number of virtual timeslots are to be identified for the transaction.7. The apparatus of claim 1 , wherein identifying the allocated amount of bandwidth includes identifying a maximum payload size for the transaction.8. The apparatus of claim 1 , wherein the amount of bandwidth allows for an amount of non-isochronous bandwidth on the link.9. The apparatus of claim 1 , wherein the virtual channel is one of a plurality of virtual channels and at least one other virtual channel in the plurality is a virtual channel for non-isochronous traffic.10. The apparatus of claim 9 , wherein the virtual channel is dedicated for isochronous traffic.11. The apparatus of claim 1 , wherein the logic is to configure the virtual channel to support servicing of the isochronous transaction according to the amount of bandwidth and a latency requirement.12. The apparatus of claim 1 , wherein the packet corresponds to a request.13. The ...

COMPUTER SYSTEM, AND SWITCH AND PACKET TRANSFER CONTROL METHOD USED THEREIN

A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O devices to a computer via a PCIe switch. A switch with which a computer and I/O devices are connected includes: a first PCI-PCI bridge which is positioned on the computer side; a second PCI-PCI bridge which is positioned on the I/O device side; trapper units which trap packet data which is inputted into the switch; a packet routing unit which transfers packet data to the I/O devices; and a management processor which is connected to the trapper units and provides the computer a virtual PCI-PCI bridge and a virtual link by execution of a program. The trapper units adjudicate the destination of the packet data which is transferred from the computer. 1. A computer system that transfers packet data via switches connected to a computer and an I/O device ,wherein the switch is provided with a first PCI-PCI bridge arranged on the side of the computer, a second PCI-PCI bridge arranged on the side of the I/O device, a trapper unit that traps packet data input to the switch and a packet routing unit that transfers the packet data to the I/O device;the switch is further provided with a management processor which is connected to the trapper unit and which provides a virtual PCI-PCI bridge and a virtual link to the computer by the execution of a program;the PCI-PCI bridge included in the physical configuration of the computer system is distinguished as a physical PCI-PCI bridge;address space of such a PCI-PCI bridge that its virtual PCI-PCI bridge and its physical PCI-PCI bridge can be correlated by one to one is realized in that of the physical PCI-PCI bridge;address space of a virtual PCI-PCI bridge that cannot be correlated with the corresponding physical PCI-PCI bridge by one to one is secured in a memory;the trapper unit determines a destination of the packet data transferred from the computer;when the destination is the ...

INFORMATION PROCESSING APPARATUS AND CONTROL METHOD

An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute a process including acquiring control information of a first application program of which execution result is displayed, extracting a dependency relationship between the first application program and a second application program on a basis of the control information, and determining whether an access request for a device from the second application program is granted on a basis of the dependency relationship. 1. An information processing apparatus comprising:a memory; anda processor coupled to the memory, configured to execute a process including:acquiring control information of a first application program of which execution result is displayed,extracting a dependency relationship between the first application program and a second application program on a basis of the control information, anddetermining whether an access request for a device from the second application program is granted on a basis of the dependency relationship.2. The information processing apparatus according to claim 1 , wherein the process further includes:acquiring a remaining capacity of a power source;acquiring device information corresponding to the remaining capacity of the power source; anddetermining whether an access request for a device corresponding to the device information from the second application program is granted.3. The information processing apparatus according to claim 1 , wherein the process further includes:granting an access request for the device from the second application program having dependency relationship with the first application program .4. The information processing apparatus according to claim 1 , wherein the process further includes:denying an access request for the device from a third application program other than the first application program and the second application program.5. The information processing apparatus according ...

Bus Subscriber Device For Connection To A Line-Redundant Serial Data Bus, And Method For Controlling The Communication Of A Bus Subscriber With A Line-Redundant Serial Data Bus

Bus subscriber device for connection to a line-redundant, serial data bus, over which data are exchanged according to a predefined protocol, having the following features: a data transmission unit, at least two data receiving units that are connected in parallel, a line selection logic and at least two bus communication interfaces for connecting to a corresponding number of lines of the data bus, wherein each of the data receiving units is connectable via an associated bus communication interface to an assigned line of the data bus and has means for receiving a data block from the associated line of the data bus and means for forwarding the received data block to the line selection logic, and wherein the line selection logic has means for selecting a line of the data bus as a receiving line and forwarding the data block received over the selected receiving line. 1. A bus subscriber device for connection to a line-redundant serial data bus , over which data are exchanged according to a predefined protocol , having the following features:a data transmission unit,at least two data receiving units that are connected in parallel,a line selection logic, andat least two bus communication interfaces for connecting to a corresponding number of lines of the data bus,wherein each of the data receiving units is connectable via an associated bus communication interface to an assigned line of the data bus and has a receiver for receiving a data block from the associated line of the data bus and a forwarding unit for forwarding the received data block to the line selection logic, and wherein the line selection logic has means for selecting one line of the data bus as a receiving line and forwarding the data block received over the selected receiving line, wherein each of the at least two data receiving units is associated with a dedicated timer device.2. Bus subscriber device according to claim 1 , additionally having a data processor for controlling the bus access claim 1 , ...

Method and Circuit Arrangement for Transmitting Data Between Processor Modules

The invention relates to a circuit arrangement for forming a digital interface comprising a digital data bus, which exchanges data when microprocessor systems are connected. The data exchange can be effected bidirectionally. On transmission of data the circuit arrangement generates as bus master a bus clock speed and operates on receipt of data as a bus slave in accordance with the received clock signal. The circuit arrangement comprises at least one FIFO memory for receiving data. 1102121122123123101104. A circuit arrangement (IPL) for forming a digital interface ( , , , ) comprising a digital data bus () which interchanges data when at least two microprocessor systems are connected to provide data interchange , wherein the data interchange can take place bidirectionally between the microprocessor systems and the circuit arrangement produces a bus clock when sending data as a bus master and operates on the basis of a received clock signal when receiving data as a bus slave , and at least one of a FIFO memory () for sending data and a FIFO memory () for receiving data.21234101104. The circuit arrangement as claimed in claim 1 , further comprising in that it the circuit arrangement is integrated in a microprocessor module ( claim 1 , ) having a microprocessor () which integrates the microprocessor systems and at least one DMA module () claim 1 , wherein the DMA module can read and write to the FIFO memory ( claim 1 , ) independently of read or write operations of one of the microprocessor systems.33. The circuit arrangement as claimed in claim 2 , further comprising in that the microprocessor is a multicore processor () which is designed to have a plurality of cores which operate in clock sync.4. The circuit arrangement as claimed in claim 2 , further comprising a read only memory of semiredundant design and the FIFO memory is of essentially fully redundant design.5105101104. The circuit arrangement as claimed in in that the interface further comprises a shift ...