Circuit Configuration And Method For Distributing Pulses Within A Time Interval

A circuit configuration for generating pulses within a time interval on the basis of an input signal includes a counting unit, a comparator unit and a first adder circuit; the time interval being predicted on the basis of at least two defined changes in input signals; the circuit configuration being configured for triggering at the beginning of the time interval by the first adder circuit on the basis of clock pulses, for generating and outputting pulses; for counting a number of generated and output pulses using the counting unit; for comparing the counted number to a setpoint value using the comparator unit; and for ending the generation and outputting of the pulses in response to the reaching of the setpoint value or the ending of the time interval.

NUMERICAL CONTROL DEVICE

A numerical control device that controls a machine in which a main set including an X1 axis, a Z1 axis and a first turret axis and a sub-set including an X2 axis, a Z2 axis and a second turret axis are arranged to be point-symmetric with respect to a C axis, wherein each of the turret axis of the main set and the turret axis of the sub-set are selectively designated as a reference side and a synchronized side and a simultaneous D-cut control mode command for selecting a mode in which both turret axes are simultaneously actuated in synchronization using the output of the turret axis of one of the sets is set; wherein the numerical control device comprises, simultaneous D-cut command processing means, X1/Y1/C axis interpolation processing means, X2/Y2 axis interpolation processing means, and H axis command selecting means. 1. A numerical control device that controls a machine in which a main set including an X1 axis , a Z1 axis and a first turret axis and a sub-set including an X2 axis , a Z2 axis and a second turret axis are arranged to be point-symmetric with respect to a C axis ,wherein each of the turret axis of the main set and the turret axis of the sub-set are selectively designated as a reference side and a synchronized side and a simultaneous D-cut control mode command for selecting a mode in which both turret axes are simultaneously actuated in synchronization using the output of the turret axis of one of the sets is set; simultaneous D-cut command processing means for analyzing and executing the simultaneous D-cut control mode command,', 'X1/Y1/C axis interpolation processing means for performing an interpolation process on the main set,', 'X2/Y2 axis interpolation processing means for performing an interpolation process on the sub-set, and', 'H axis command selecting means for selecting from which of the main set and the sub-set to acquire rotational angle control data of the turret axes and the C axis; and, 'wherein the numerical control device comprises ...

Passive Offset and Overshoot Cancellation for Sampled-Data Circuits

A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

NUMERICAL CONTROLLER HAVING A TOOL POSTURE CONTROL FUNCTION FOR MULTI-AXIS MACHINING MACHINES

A numerical controller controls a multi-axis machining machine having three linear axes and three rotation axes that include one rotation axis for tool phase control. The numerical controller interpolates smoothly a tool center point position and a tool posture (tool direction and tool phase direction) on the basis of a tool center point position instruction and a tool posture instruction; works out an interpolated tool center point position and an interpolated tool posture (interpolated tool direction and interpolated tool phase direction), and, on the basis of the interpolated tool center point position and the interpolated tool posture that have been worked out, calculates each position of the three linear axes and three rotation axes of the multi-axis machining machine, such that the respective axes are driven to the calculated position. 1. A numerical controller having a tool posture control function for multi-axis machining machine , which controls a multi-axis machining machine having at least three linear axes and at least three rotation axes including one rotation axis for tool phase control ,the numerical controller comprising:a tool position and posture instruction reading unit that reads a machining program that includes a tool center point position instruction and a tool posture instruction for a tool posture formed on the basis of a tool direction and a tool phase direction;a tool position and posture interpolation unit that interpolates smoothly a tool center point position and a tool posture on the basis of the tool center point position instruction and the tool posture instruction, and works out an interpolated tool center point position and an interpolated tool posture formed on the basis of an interpolated tool direction and an interpolated tool phase direction; anda respective axis positions arithmetic unit that calculates respective axis positions of the at least three linear axes and the at least three rotation axes, on the basis of the ...

Performing a division operation using a split division circuit

The disclosed embodiments disclose techniques for using a split division circuit that includes a first divider that is optimized for a first range of divisor values and a second divider that is optimized for a second range of divisor values; the first range is distinct from the second range. During operation, the circuit receives a divisor for the division operation. The circuit: determines whether the divisor is in the first range or the second range to determine whether the first divider or the second divider should perform the division operation; performs the division operation in the selected host divider; and then outputs the result that was generated by the selected host divider.

PERFORMING QUOTIENT SELECTION FOR A CARRY-SAVE DIVISION OPERATION

The disclosed embodiments disclose techniques for performing quotient selection in an iterative carry-save division operation that divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D. During a divide operation, a divider approximates Q by iteratively selecting an operation to perform for each iteration of the carry-save division operation and then performing the selected operation. The operation for each iteration is selected based on the current partial sum bits of a partial remainder in carry-save form (rs) and the current partial carry bits of a partial remainder in carry-save form (rc). More specifically, the operation is selected from a set of operations that includes: (1) a 2X* operation; (2) an S1 & 2X* operation; (3) an S2 & 2X* operation; (4) an A1 & 2X* operation; and (5) an A2 & 2X* operation. 1. A computer-implemented method for performing quotient selection for a carry-save division operation , wherein the carry-save division operation divides a dividend , R , by a divisor , D , to produce an approximation of a quotient , Q=R/D , the method comprising:approximating Q by iteratively selecting and performing an operation for each iteration of the carry-save division operation, wherein the operation for a given iteration is selected based on a set of partial sum bits of a partial remainder in carry-save form (rs) and a set of partial carry bits of a partial remainder in carry-save form (rc); a “2X* operation” that performs a left shift of rs and rc, inverts the most-significant bit of rs and rc, and then retires a quotient digit 0;', 'an “S1 & 2X* operation” that subtracts the divisor from rs and rc, performs a left shift of rs and rc, inverts the most-significant bit of rs and rc, and then retires a quotient digit 1;', 'an “S2 & 2X* operation” that subtracts twice the divisor from rs and rc, performs a left shift of rs and rc, inverts the most-significant bit of rs and rc, and then retires a quotient digit 2;', 'an “A1 ...

METHODS AND SYSTEMS FOR OPTIMAL GUIDANCE BASED ON ENERGY STATE APPROXIMATION

A system, computer-readable medium, and a method to operate a vehicle in a manner that minimizes a cost to travel from an origin to a destination that includes finding the input to a flight control system that minimizes direct operating cost. The approach described herein employs an energy state approximation (ESA). 1. A method for optimizing vehicle guidance to minimize direct operating cost of a prescribed mission , the method comprising:obtaining a mathematical model of a vehicle motion;eliminating fast dynamic state variables in the mathematical model;deriving a reduced-order mathematical model of the vehicle motion as a set of Differential Algebraic Equations that represent the slow dynamic states and includes mass as a slow state variable;determining quasi steady-state operating points within a flight envelope for the prescribed mission by solving the reduced-order model for thrust, drag, and fuel flow at uniform intervals of energy;generating a record of the quasi steady-state operating points with energy as an independent input variable and thrust, drag and fuel flow as dependent output variables;selecting speed as a control variable and using methods of optimal control to define a Hamiltonian function as direct operating cost per energy unit;at uniform intervals of energy, using a numerical method to determine the speed that minimizes the Hamiltonian function for a fixed energy per interval;constructing an optimal quasi-steady speed-energy trajectory based on the minimized Hamiltonian function and a corresponding velocity-altitude state trajectory derived therefrom using the reduced-order equations of motion;determining an optimal flight path angle to depart from the velocity-altitude state trajectory and terminate at a prescribed target cruise state;integrating backward from the target cruise state using an approximate weight and the previously-determined optimal flight path angle to define a departure point where the state trajectory intersects the ...

Non-volatile counter system, counter circuit and power management circuit with isolated dynamic boosted supply

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

FREQUENCY DOUBLER USING RECIRCULATING DELAY CIRCUIT AND METHOD THEREOF

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock. 1. A frequency doubler comprising:a multiplexer configured to receive a first clock and output a second clock in accordance with a third clock, wherein the first clock has a fifty percent duty cycle and is a two-phase clock comprising a first phase and a second phase;a recirculating delay circuit configured to receive the second clock and output a fourth clock and a fifth clock; anda divide-by-two circuit configured to receive the fourth clock and output the third clock, wherein the recirculating delay circuit comprises a logic gate and a delay chain comprising a plurality of clock buffers including an intermediate clock buffer and a last clock buffer, said logic gate being configured to receive the second clock and the fifth clock and output a sixth clock, said plurality of clock buffers being cascaded and configured to receive the sixth clock and output the fourth clock from the intermediate clock buffer and output the fifth clock from the last clock buffer.2. The frequency doubler of claim 1 , further including a control signal configured to control a delay of the delay chain.3. The frequency doubler of further comprising: a duty cycle detector configured to receive the second clock and output a duty cycle error signal claim 2 , a controller configured to receive the duty cycle error signal claim 2 , and a power supply circuit configured to establish a voltage level of a power supply node of the delay chain.4. The frequency doubler of claim 3 , wherein the controller is ...

NON-VOLATILE COUNTER SYSTEM, COUNTER CIRCUIT AND POWER MANAGEMENT CIRCUIT WITH ISOLATED DYNAMIC BOOSTED SUPPLY

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse. 1. An integrated circuit , comprising:a first power domain circuit;a second power domain circuit;a supply circuit having a supply input and a supply output;{'claim-text': ['the first power domain circuit;', 'the second power domain circuit; and', 'the supply circuit;'], '#text': 'a power management circuit coupled to:'}{'claim-text': ['a regulator circuit, having a regulator input coupled to the supply output and a regulator output coupled to the first power domain circuit;', 'a switch coupled between the first power domain circuit and the second power domain circuit, the switch having a switch control input; and', 'a control circuit having a control output coupled to the switch control input.'], '#text': 'the power management circuit including:'}2. The integrated circuit of claim 1 , wherein:the second power domain circuit requires a higher voltage than the first power domain circuit.3. The integrated circuit of claim 1 , wherein the power management circuit includes:a boost circuit having a boost output coupled to the second power domain circuit.4. The integrated circuit of claim 3 , wherein:the boost circuit is coupled to a sensor pulse signal; andthe boost circuit is ...

COMBINED CHEMICAL AND VELOCITY SENSORS FOR FLUID CONTAMINATION ANALYSIS

Methods and systems for locating a chemical source include cross-correlating chemical concentration data from pairs of positions using a processor to determine an average velocity vector for a group of positions that averages away turbulence contributions. A convergence region is determined based on multiple average velocity vectors to determine a chemical source location. 1. A computer-implemented method for locating a chemical source , comprising:cross-correlating chemical concentration data from pairs of positions using a processor to determine an average velocity vector for a group of positions that averages away turbulence contributions; anddetermining a convergence region based on a plurality of average velocity vectors to determine a chemical source location.2. The method of claim 1 , wherein determining the convergence region comprises reversing a direction of each of average velocity vector.3. The method of claim 1 , wherein cross-correlating chemical concentration data comprises integrating over a product of concentration values measured at a pair of positions at times separated by a time lag to produce a cross-correlation product C.4. The method of claim 3 , wherein cross-correlating chemical concentration data further comprises determining a time lag that produces a maximum cross-correlation product.6. The method of claim 4 , further comprising determining the average velocity vector based on a normalized sum of distances between each pair of positions divided by a respective determined time lag for each pair of positions.7. The method of claim 1 , wherein each group of positions comprises at least four chemical concentration sensors at respective positions.8. The method of claim 7 , wherein cross-correlating chemical concentration data from pairs of positions comprises determining respective average velocity vectors for a plurality of groups of positions.9. A combined chemical and velocity sensor system claim 7 , comprising:a sensor control module ...

DEDICATED HARDWARE SYSTEM FOR SOLVING PARTIAL DIFFERENTIAL EQUATIONS

Embodiments relate to a computing system for solving differential equations. The system is configured to receive problem packages corresponding to problems to be solved, each comprising at least a differential equation and a domain, and to select a solver of a plurality of solvers, based upon availability of each of the plurality of solvers. Each solver comprises a coordinator that partitions the domain of the problem into a plurality of sub-domains, and assigns each of the plurality of sub-domains to a differential equation accelerator (DEA) of a plurality of DEAs. Each DEA comprises at least two memory units, and processes the sub-domain data over a plurality of time-steps by passing the sub-domain data through a selected systolic array from one memory unit, and storing the processed sub-domain data in the other memory unit, and vice versa. 1. A system comprising:an interface computer configured to receive a problem to be solved, the problem comprising a differential equation and a domain, and to store the received problem in a problem queue;a dispatch computer configured to receive the problem from the problem queue, and to select a solver of a plurality of solvers, based upon availability of each of the plurality of solvers; a coordinator;', 'a plurality of differential equation accelerator (DEA) units, wherein each DEA unit comprises a plurality of systolic arrays, each systolic array having a hardware configuration for solving a corresponding type of differential equation;', 'wherein the coordinator, in response to receiving the problem from the dispatch computer, partitions the domain into a plurality of sub-domains, and assigns each of the plurality of sub-domains to a DEA unit of the plurality of DEA units; and', 'wherein each of the plurality of DEA units having an assigned sub-domain is configured to process sub-domain data of its assigned sub-domain over a plurality of time-steps., 'wherein each solver comprises2. The system of claim 1 , wherein a DEA ...

CONTROL DEVICE, CONTROL METHOD, AND PROGRAM

A control device provided with an interpolated attitude deriving section for deriving an interpolated attitude at a via-point of a machine element that moves in a trajectory reaching an end point from a starting point via the via-point, an optimum attitude deriving section for deriving an optimum attitude at the via-point of the machine element, and an attitude deriving section that derives an attitude that the machine element is controlled to have at the via-point on the basis of the interpolated attitude and the optimum attitude.

NUMERICAL CONTROLLER THAT SHORTENS CYCLE TIME OF MACHINING PROGRAM

A numerical controller decodes a block read out from a machining program, calculates execution data to be used for control over a machine tool, and determines whether a travel amount resulting from travel instructions for control axes of the machine tool is existent or not based on the calculated execution data. If the travel amount resulting from the travel instructions for the control axes is not existent as a result of such determination, processes for the present block are omitted and cycle time is thereby shortened. 1. A numerical controller that controls a machine tool including control axes based on a machining program , the numerical controller comprising:an execution data calculation unit that decodes a block read out from the machining program and that calculates execution data to be used for control over the machine tool; anda travel amount determination unit that determines whether a travel amount resulting from travel instructions for the control axes of the machine tool is existent or not based on the execution data calculated by the execution data calculation unit, whereinprocesses for the block are omitted if it is determined that the travel amount resulting from the travel instructions for the control axes of the machine tool is not existent.2. The numerical controller according to claim 1 , wherein the travel amount determination unit is configured so as to cause a shift to processes for a block next to the block of the machining program if it is determined that the travel amount resulting from the travel instructions for the control axes of the machine tool is not existent. 1. Field of the InventionThe present invention relates to a numerical controller that shortens cycle time of a machining program.2. Description of the Related ArtA numerical controller controls a machine tool by reading out blocks in a machining program, stored in a memory such as SRAM, one by one and operating servomotors and spindles based on instructions of the blocks that ...

SYSTOLIC ARRAY DESIGN FOR SOLVING PARTIAL DIFFERENTIAL EQUATIONS

Embodiments relate to a system for solving differential equations. The system is configured to receive problem packages corresponding to problems to be solved, each comprising at least a differential equation and a domain. A solver stores a plurality of nodes of the domain corresponding to a first time-step, and processes the nodes over a plurality of time-steps using a systolic array comprising hardware for solving the particular type of the differential equation. The systolic array processes each node to generate a node for a subsequent time-step using a sub-array comprising a plurality of branches, each branch comprising a respective set of arithmetic units arranged in accordance with a corresponding term of the discretized form of the differential equation, and an aggregator configured to aggregate the corresponding terms from each branch to generate node data for the subsequent time-step. 1. A system configured for discretized solving of differential equations , comprising:a first memory configured to store a plurality of nodes of a domain corresponding to a first time-step, the nodes associated with a differential equation having a discretized form having a plurality of terms;a plurality of systolic arrays, each corresponding to a respective differential equation type; and a plurality of branches, each branch comprising a respective set of arithmetic units arranged in accordance with a corresponding term of the discretized form of the differential equation, and configured to process the node to generate the corresponding term;', 'an aggregator configured to receive the corresponding terms from each of the plurality of branches, and to aggregate the received terms to generate a node corresponding to a second time-step;, 'a controller configured to select a systolic array of the plurality of systolic arrays, based upon a type of the differential equation, the systolic array configured to receive at least a portion of the plurality of nodes from the first memory, ...

FLOATING POINT MULTIPLY-ADD UNIT WITH DENORMAL NUMBER SUPPORT

The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum. 1. A floating point multiply-add unit (FMAC) configurable to add a product of first and second operands to a third operand , wherein the FMAC is configurable to:determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product; andcause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.2. The FMAC of claim 1 , comprising a leading zero anticipator configurable to generate the predicted left shift for the sum.3. The FMAC of claim 2 , wherein the FMAC is configurable to cause the bits representing the sum to be left shifted by the predicted left shift if the third operand is smaller than or equal to the product.4. The FMAC of claim 3 , wherein the FMAC is configurable to cause the bits representing the sum to be left shifted by an alignment shift if the addend is larger than the product claim 3 , wherein the alignment shift is used to right shift the third operand to line up with the product prior to adding the product to ...

METHOD AND COMPUTING DEVICE FOR OPTICALLY RECOGNIZING MATHEMATICAL EXPRESSIONS

Image data corresponding to an image depicting an equation is received. The image data is processed to identify a plurality of morphological components corresponding to the equation depicted in the image. A computer readable data object is generated using the plurality of morphological components, wherein the computer readable data object is in a defined syntax computable by a computational application. 1. A method of generating a computer readable data object corresponding to an equation depicted in an image , the method comprising:receiving, at one or more processors, image data corresponding to an image depicting an equation;processing, at one or more processors, the image data to identify a plurality of morphological components corresponding to the equation depicted in the image; andgenerating, at one or more processors, the computer readable data object using the plurality of morphological components, wherein the computer readable data object is in a defined syntax computable by a computational application.2. The method of claim 1 , further comprising:generating, at one or more processors, a plurality of bounding boxes corresponding to the plurality of morphological components;wherein generating the computer readable data object further includes using the plurality of bounding boxes.3. The method of claim 2 , wherein generating the computer readable data object includes using heuristics.4. The method of claim 1 , wherein processing the image data to identify the plurality of morphological components comprises:using a neural network to process the image data to identify alphanumeric characters and mathematical or scientific symbols.5. The method of claim 4 , wherein:the neural network is a first neural network; andgenerating the computer readable data object includes using a second neural network to process identified alphanumeric characters and mathematical or scientific symbols.6. The method of claim 5 , wherein:using the first neural network to process the ...

Physical Quantity Measurement Device, Electronic Apparatus, And Vehicle

A physical quantity measurement device includes a sensor element having a coupling capacitance formed between a drive electrode and a detection electrode, and a circuit device having a drive circuit adapted to supply a drive signal to the drive electrode, a detection circuit adapted to detect physical quantity information corresponding to a physical quantity based on a detection signal from the detection electrode, and a fault diagnosis circuit, and the fault diagnosis circuit has an electrostatic leakage component extraction circuit adapted to extract an electrostatic leakage component due to the coupling capacitance from one of the detection signal and an amplified signal of the detection signal, and performs a fault diagnosis based on the electrostatic leakage component extracted. 1. A physical quantity measurement device comprising:a sensor having a drive electrode and a detection electrode, and provided with a coupling capacitance formed between the drive electrode and the detection electrode; anda circuit device having a drive circuit adapted to supply a drive signal to the drive electrode, a detection circuit adapted to detect physical quantity information corresponding to a physical quantity based on a detection signal from the detection electrode, and a fault diagnosis circuit,wherein the fault diagnosis circuit has an electrostatic leakage component extraction circuit adapted to extract an electrostatic leakage component due to the coupling capacitance from one of the detection signal and an amplified signal of the detection signal, and performs a fault diagnosis based on the electrostatic leakage component extracted.2. The physical quantity measurement device according to claim 1 , whereinthe drive circuit outputs the drive signal as a rectangular wave, andthe electrostatic leakage component extraction circuit extracts a change of one of the detection signal and the amplified signal due to one of a rising edge and a falling edge of the drive signal as the ...

Apparatus and methods for low power frequency clock generation and distribution

Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (F S )(F S /N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential F S /N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.

RANDOM NUMBER GENERATING SYSTEM AND RANDOM NUMBER GENERATING METHOD THEREOF

A random number generation system and a random number generation method thereof are provided. The random number generation system includes a random number generator, a random number selection circuit, and a random number logic circuit. The random number generator receives the random number request signal to provide a first random number sequence with n bits, where n is a positive integer. The random number selection circuit receives the random number request signal to provide a bit selection signal with n bits, wherein the bit selection signal is a time varying signal and is determined by the received random number request signal. The random number logic circuit receives the random number request signal, the first random number sequence and the bit selection signal, and in response to the random number request signal to adjust the first random number sequence using the bit selection signal to provide the second random number sequence. 1. A random number generating system , comprising:a random number generator, receiving a random number request signal, and providing a first random number sequence with n bits in response to the random number request signal, wherein n is a positive integer;a random number selection circuit, receiving the random number request signal, and providing a bit selection signal with n bits in response to the random number request signal, wherein the bit selection signal is a time varying signal and determined by the received random number request signal; anda random number logic circuit, coupled to the random number generator and the random number selection circuit, and receiving the random number request signal, the first random number sequence and the bit selection signal, and in response to the random number request signal to adjust the first random number sequence using the bit selection signal to provide a second random number sequence.2. The random number generating system according to claim 1 , wherein when a logic level of a kbit of ...

NON-VOLATILE COUNTER SYSTEM, COUNTER CIRCUIT AND POWER MANAGEMENT CIRCUIT WITH ISOLATED DYNAMIC BOOSTED SUPPLY

Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse. 1. An integrated circuit , comprising:a first power domain circuit comprising a logic circuit, the first power domain circuit having a first power domain supply node;a second power domain circuit comprising a non-volatile memory circuit, the second power domain circuit having a second power domain supply node;a supply circuit having a sensor pulse input and a supply output; a regulator circuit, having an input coupled to the supply output and a regulator output coupled to the first power domain supply node;', 'a switch coupled between the first power domain supply node and the second power domain supply node, the switch having a control node;', 'a boost circuit having a boost output coupled to the second power domain supply node; and', 'a control circuit having a control output coupled to the control node of the switch., 'a power management circuit coupled to the first power domain circuit, to the second power domain circuit and to the supply circuit, the power management circuit comprising2. The integrated circuit of claim 1 ,wherein the logic circuit includes a first interface to send and receive first data signals representing a counter value, the logic circuit ...

PHASE RETRIEVAL USING COORDINATE DESCENT TECHNIQUES

Coordinate descent is applied to recover a signal-of-interest from only magnitude information. In doing so, a single unknown value is solved at each iteration, while all other variables are held constant. As a result, only minimization of a univariate quartic polynomial is required, which is efficiently achieved by finding the closed-form roots of a cubic polynomial. Cyclic, randomized, and/or a greedy coordinate descent technique can be used. Each coordinate descent technique globally converges to a stationary point of the nonconvex problem, and specifically, the randomized coordinate descent technique locally converges to the global minimum and attains exact recovery of the signal-of-interest at a geometric rate with high probability when the sample size is sufficiently large. The cyclic and randomized coordinate descent techniques can also be modified via minimization of the l-regularized quartic polynomial for phase retrieval of sparse signals-of-interest, i.e., those signals with only a few nonzero elements. 1. A method for obtaining phase information for a signal-of-interest from only magnitude information for the signal-of-interest , the method comprising:{'o': {'@ostyle': 'single', 'x'}, 'expressing the magnitude information as an objective function, f() the objective function being in the form of a multivariate quartic polynomial;'}{'sub': 'k', 'selecting a coordinate index, i, according to one or more predefined coordinate descent rules; and'}iteratively minimizing, according to the selected coordinate index, only one variable component of the multivariate quartic polynomial while maintaining every other variable component of the multivariate quartic polynomial at a constant value.2. The method of where selecting the coordinate index claim 1 , i claim 1 , comprises:{'sub': 'k', 'cyclically assigning isequential values from 1 to 2N for each of the variable components of the multivariate quartic polynomial.'}3. The method of where selecting the coordinate ...

Method and system for generating high-order pseudo-random electromagnetic exploration signal

A method and system for generating a high-order pseudo-random electromagnetic exploration signal. The method includes: constructing two or more basic unit signals according to an exploration requirement, where the basic unit signals are stairstep signals obtained by superposing a plurality of in-phase periodic square wave signals, and a frequency ratio between adjacent ones of the plurality of periodic square wave signals is 2; and superposing the two or more basic unit signals to obtain superposed stairstep signals, and correcting amplitudes to be consistent with amplitudes of the periodic square wave signals, to obtain high-order 2n sequence pseudo-random signals. The 2n sequence stairstep signals of different orders can be constructed within a limited frequency interval, improving the resolution during electromagnetic exploration.

HIGH VOLTAGE GAIN SWITCHED CAPACITOR FILTER INTEGRATION

A method of operating switched capacitor filter integration circuits by pre-charging a final filter capacitor thereof with the final full voltage gain value during a first subframe to obtain an enhanced signal to noise ratio without changes to the circuit or components thereof. 1. A method of operating a switched capacitor filter subframe integration circuit comprising: 'a split switch, a sum switch, an integration capacitor, a split capacitor, and a sum capacitor:', 'on a switched capacitor filter subframe integration circuit comprising'}closing all switches, thereby resetting all capacitors;integrating a first subframe across all capacitors simultaneously;resetting the integration capacitor and split capacitor;integrating a second subframe on the integration capacitor and split capacitor;opening the split switch;closing the sum switch, thereby allowing the charge on the split capacitor to flow into the sum capacitor;repeating the above steps pertaining to integrating the second subframe as many times as desired to complete subframe integration with desired levels of voltage gain and noise.2. The method of wherein the sum capacitor is larger than the other capacitors.4. The method of wherein the combined capacitance of all capacitors is double that of the integration and split capacitors.5. The method of wherein integration time is scaled based on the size of the sum capacitor relative to the integration and split capacitors to maintain a desired gain.6. The method of wherein the integration time is increased proportionately to the increase in capacitance to the switched capacitor filter subframe integration circuit.7. A method of operating a switched capacitor filter subframe integration circuit comprising:during a first integration interval, setting the voltage of a sum capacitor equal to what is seen on an integration capacitor.8. The method of wherein the sum capacitor is larger than other capacitors included on the integration circuit.10. The method of wherein ...

INITIALIZATION OF HYBRID EQUATION-BASED DYNAMICAL SYSTEM MODELS USING SMT METHODS

A SMT method for initialization of a hybrid equation-based dynamic system representing a dynamic behavior of a physical device, said method comprising: preparing a SMT problem, solving the SMT problem using a SMT solver, extracting a plurality of unfixed start value premises from UNSAT cores, creating a relaxed SMT problem by removing the plurality of unfixed start value premises, solving the relaxed SMT problem using the SMT solver, extracting the solution from the SMT solver and considering further algorithms to solve the relaxed SMT problem. 1. A SMT method for initialization of a hybrid equation-based dynamic system representing a dynamic behavior of a physical device , the SMT method comprising:preparing a SMT problem;solving the SMT problem using a SMT solver;extracting a plurality of unfixed start value premises from UNSAT cores;creating a relaxed SMT problem by removing the plurality of unfixed start value premises;solving the relaxed SMT problem using the SMT solver;extracting a solution from the SMT solver; andexecuting an advanced algorithm to solve the relaxed SMT problem.2. The SMT method of claim 1 , wherein the advanced algorithm further comprises:determining if a fixed start value premise exist in UNSAT cores of the relaxed SMT problem;creating a relaxed SMT problem by removing the fixed start value premise from the relaxed SMT problem;solving the relaxed SMT problem using a SMT solver;extracting a solution from the SMT solver;determining if a constraint equation exist in UNSAT cores of the relaxed SMT problem;creating a relaxed SMT problem by removing the constraint equation from the relaxed SMT problem;solving the relaxed SMT problem using the SMT solver; andextracting the solution from the SMT solver.3. The SMT method of claim 1 , wherein the advanced algorithm further comprises:determining if a fixed start value premise exist in UNSAT cores of the relaxed SMT problem;extracting a plurality of fixed start value premises;presenting the plurality of ...

METHOD FOR IDENTIFYING CARRIER MOTION MODE BASED ON TIME-DOMAIN DIFFERENTIAL CHARACTERISTIC

The present disclosure provides a method for identifying a carrier motion mode based on a time-domain differential characteristic. Firstly, a difference operation is performed on data to obtain a difference sequence, and then sign, progressive multiplication, and accumulation operations are performed on the difference sequence, and finally thresholds are set to determine an accumulation sequence, so as to obtain a carrier motion mode. All operations involved in this method are performed in time domain, and the method has the advantages of simple algorithm, good real-time performance, accurate determination, and strong robustness. 16-. (canceled)7. A method for identifying a carrier motion mode based on a time-domain differential characteristic , said method comprising:(a) assuming that a data sequence collected in a period of time is xi (i=1, . . . , k), performing a difference operation on the sequence xi to obtain a difference sequence di (i=1, . . . , k);(b) performing a sign obtaining algorithm on the difference sequence di to obtain a sign sequence si (i=1, . . . , k) and performing a progressive multiplication algorithm on the sign sequence to obtain a sequence gi (i=1, . . . , k);(c) defining a positive integer N and performing an accumulation algorithm on the sequence gi with length N to obtain a sequence zi (i=1, . . . , k); and(d) setting thresholds T1 and T2 based on a value of N and performing motion mode identification. The present disclosure relates to the field of intelligent sensing, and in particular, to a method for identifying a carrier motion mode based on a time-domain differential characteristic.With the rapid development of the electronic information technology, photoelectric detection technology, and artificial intelligence technology, the smart industry represented by wearable devices, smart homes, smart manufacturing, mobile robots, and unmanned driving has developed vigorously. Intelligent instruments and modern sensors are the hardware ...

Fast digital multiply-accumulate (mac) by fast digital multiplication circuit

Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals.

NEUROMORPHIC ARITHMETIC DEVICE

The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator. 1. A neuromorphic arithmetic device comprising:a first synapse circuit configured to generate a first current by performing a first multiplication operation on a first pulse width modulation (PWM) signal and a first weight;a second synapse circuit configured to generate a second current by performing a second multiplication operation on a second PWM signal and a second weight;a charging/discharging circuit configured to store charges induced by the first current and the second current in a charging period, and discharge the charges in a discharging period;a comparator configured to compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage; anda counter configured to count output pulses of an oscillator on the basis of a result of the comparison by the comparator.2. The neuromorphic arithmetic device of claim 1 , further comprising:a first PWM converter configured to convert a first input into the first PWM signal; anda second PWM converter configured to convert a second input into the second PWM ...

OPEN/CLOSE COUNTING DEVICE

An open/close counting device to be attached to one of a first die and a second die which constitute a die, the die being opened by relatively moving the first die and the second die, the open/close counting device counting the number of open/close times of the die. The open/close counting device includes an open/close detecting section provided so as to face a target face of the other of the first die and the second die and to detect relative displacement of the target face along a die moving direction in non-contact condition, and includes an output section to output the open/close times counted based on detection of open/close by the open/close detecting section. 1. An open/close counting device to be attached to one of a first die and a second die which constitute a die , the die being opened by relatively moving the first die and the second die , the open/close counting device counting open/close times of the die , the open/close counting device comprising:an open/close detecting section provided so as to face a target face of the other of the first die and the second die and to detect relative displacement of the target face along a die moving direction in non-contact condition; andan output section to output the open/close times counted based on detection of open/close by the open/close detecting section.2. The open/close counting device according to claim 1 , wherein the open/close detecting section comprises an emission portion to emit laser light toward the target face along a die moving direction and comprises a light receiving portion to receive reflected light.3. The open/close counting device according to claim 1 , wherein the output section comprises a display to display the open/close times.4. The open/close counting device according to claim 1 , wherein the open/close counting device comprises an identification information display section capable of identifying the die.5. The open/close counting device according to claim 1 , wherein a driving power ...

Method for Controlling Redundantly Actuated Machines for Cutting a Pattern of Disconnected Contours

A method controls a machine with redundant actuators according to pattern of disconnected contours, wherein the machine includes redundant actuators by first generating a set of initial trajectories from the pattern. Each initial trajectory corresponds to one of the disconnected contours, or a path from an exit point of one contour and an entry point of a next contour. A set of costs for the set of initial trajectories is determined. A sequence of final trajectories is determined based on the set of costs. Then, a set of commands is generated for controlling the machine according to the sequence of final trajectories. 1. A method for controlling a machine according to pattern of disconnected contours , wherein the machine includes redundant actuators , comprising:generating a set of initial trajectories from the pattern, wherein each initial trajectory corresponds to one of the disconnected contours, or a path from an exit point of one contour and an entry point of a next contour;determining a set of costs for the set of initial trajectories;determining a sequence of final trajectories based on the set of costs;determining a set of commands for controlling the machine according to the sequence of final trajectories, wherein the steps are performed in a processor.2. The method of claim 1 , wherein a particular trajectory represents an operation of the machine proceeding from the exit point with an exit velocity to an entry point with an entry velocity according to a shape of the contour to he cut claim 1 , and dynamics of the machine.3. The method of claim 1 , wherein the set of initial trajectories includes at least one trajectory representing; an operation of the machine along the contour with non-zero velocities at corresponding exit and entry points claim 1 , and at least one trajectory representing the operation between different contours with non-zero velocities at the corresponding exit and/or entry points.4. The method of claim 1 , wherein the costs minimize ...

Temporal computing

A system for evaluating a multiply and add expression. The system comprises an encoder for encoding variables of the multiply and add expression on a time domain signal divided into a plurality of time slots and comprising a first and second impulse on a first and second time slot. The system further comprises an integrator unit operable to receive the time domain signal on a time slot by time slot basis. The integrator unit is operable, to accumulate, on a time-slot-by-time-slot basis, an amplitude value corresponding to a running total of the sum of the amplitude of the impulse signals received, and accumulate, on a time-slot-by-time-slot basis, the accumulated amplitude value. The integrator unit is thereby operable to generate, after receipt of the time domain signal, a value which corresponds to the result of the multiply and add expression.

Frequency Multiplying Transceiver

Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).

PULSED BASED ARITHMETIC UNITS

Various examples of devices, methods and systems related to pulse based arithmetic units. In one example, a pulse domain device includes an augend area calculator to provide an augend area output for an augend pulse train; an addend area calculator to provide an addend area output for an addend pulse train; a resultant sum area (RSA) decoder to provide a RSA output using the augend and addend area outputs; and a pulse timing calculator to provide RSA output pulse timing. In another example, a pulse domain device includes a multiplicand area calculator to provide an multiplicand area output for a multiplicand pulse train; a multiplier area calculator to provide a multiplier area output for a multiplier pulse train; a resultant product area (RPA) decoder to provide a RPA output using the multiplicand and multiplier area outputs; and a pulse timing calculator to provide RPA output pulse timing. 1. A pulse domain device , comprising:an augend area calculator configured to provide an augend area output corresponding to an area of an augend pulse train input;an addend area calculator configured to provide an addend area output corresponding to an area of an addend pulse train input;a resultant sum area (RSA) decoder configured to provide a RSA output based upon the augend area output and the addend area output; anda pulse timing calculator configured to provide RSA output pulse timing corresponding to the RSA output.2. The pulse domain device of claim 1 , comprising a time-to-counts converter (TCC) configured to convert IF pulse timing of the augend pulse train input and the addend pulse train input into corresponding digital counts provided to the augend area calculator and the addend area calculator.3. The pulse domain device of claim 2 , wherein the corresponding digital counts comprise a high speed digital count and a low speed digital count.4. The pulse domain device of claim 3 , wherein the high speed digital count is based upon IF pulses of both the augend pulse ...

PERFORMING PROCESSING USING HARDWARE COUNTERS IN A COMPUTER SYSTEM

Performing processing using hardware counters in a computer system includes storing, in association with greatest common divisor (GCD) processing of the system, a first variable in a first redundant binary representation and a second variable in a second redundant binary representation. Each such redundant binary representation includes a respective sum term and a respective carry term, and a numerical value being represented by a redundant binary representation is equal to a sum of the sum and carry terms of the redundant binary representation. The process performs redundant arithmetic operations of the GCD processing on the first variable and second variables using hardware counter(s), of the computer system, that take input values in redundant binary representation form and provide output values in redundant binary representation form. The process uses output of the redundant arithmetic operations of the GCD processing to obtain an output GCD of integer inputs to the GCD processing. 1. A computer-implemented method to facilitate processing of a computer system , the method comprising:storing, in association with greatest common divisor (GCD) processing of the computer system, a first variable of the GCD processing in a first redundant binary representation and a second variable of the GCD processing in a second redundant binary representation, each of the first and second redundant binary representations comprising a respective sum term and a respective carry term, wherein a numerical value being represented by a redundant binary representation is equal to a sum of the sum term and the carry term of the redundant binary representation;performing redundant arithmetic operations of the GCD processing on the first variable and the second variable using one or more hardware counters, of the computer system, that take input values in redundant binary representation form and provide output values in redundant binary representation form; andusing output of the redundant ...

METHODS AND SYSTEMS FOR OPTIMAL GUIDANCE BASED ON ENERGY STATE APPROXIMATION

A system, computer-readable medium, and a method to operate a vehicle in a manner that minimizes a cost to travel from an origin to a destination that includes finding the input to a flight control system that minimizes direct operating cost. The approach described herein employs an energy state approximation (ESA). 1. A method for optimizing vehicle guidance to minimize direct operating cost of a prescribed mission , the method comprising:obtaining a mathematical model of a vehicle's motion, the model representative of at least one of a climbing flight motion and a descending flight motion;eliminating fast dynamic state variables in the mathematical model to create a reduced-order mathematical model;generating an optimal state trajectory based on the reduced-order mathematical model, the optimal state trajectory parameterized by a variable monotonically increasing or decreasing with altitude;controlling the vehicle to operate in accordance with the generated optimal state trajectory, including a determined optimal flight path for the at least one of the climbing flight motion and the descending flight motion.2. The method of claim 1 , wherein the mathematical model includes mass as a state variable.3. The method of claim 1 , wherein the generating of the optimal state trajectory further comprises a parameterization of energy intervals for the mathematical model.4. The method of claim 1 , wherein the generating of the optimal state trajectory further comprises a parameterization of altitude intervals for the mathematical model.5. The method of claim 1 , wherein the generating of the optimal state trajectory further comprises calculating a velocity along the optimal state trajectory for the mathematical model as a control variable.6. The method of claim 1 , wherein the generating of the optimal state trajectory further comprises a thrust command along the optimal state trajectory for the mathematical model as a control variable.7. The method of claim 1 , wherein the ...

Multi-bit full adder based on resistive-switching devices and operation methods thereof

The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.

COMBINED CHEMICAL AND VELOCITY SENSORS FOR FLUID CONTAMINATION ANALYSIS

Methods and systems for locating a chemical source include measuring chemical concentration with sensors at a plurality of different positions. Measurements from pairs of positions are cross-correlated to determine an average velocity vector for a group of positions. A convergence region is determined based on a plurality of average velocity vectors to determine a chemical source location. 1. A computer-implemented method for locating a chemical source , comprising:measuring chemical concentration with sensors at a plurality of different positions;cross-correlating measurements from pairs of positions using a processor to determine an average velocity vector for a group of positions; anddetermining a convergence region based on a plurality of average velocity vectors to determine a chemical source location.2. The method of claim 1 , wherein determining the convergence region comprises reversing a direction of each of average velocity vector.3. The method of claim 1 , wherein cross-correlating measurements comprises integrating over a product of concentration values measured at a pair of positions at times separated by a time lag to produce a cross-correlation product C.4. The method of claim 3 , wherein cross-correlating measurements further comprises determining a time lag that produces a maximum cross-correlation product.5. The method of claim 4 , wherein the cross-correlation product is calculated as:{'br': None, 'i': C', 'S', 't', 'S', 't', 'dt, 'sub': t', {'sub2': 'a'}, ',t', {'sub2': 'b'}, 't', {'sub2': 'a'}, '1', '2, 'sup': t', {'sub2': 'b'}], '(τ)=∫()(−τ)'}{'sub': a', 'b', '1', '2, 'where tand tare time limits, S(t) and S(t) are measurements from a first sensor and a second sensor at a time t, and τ is a time lag.'}6. The method of claim 4 , further comprising determining the average velocity vector based on a normalized sum of distances between each pair of positions divided by a respective determined time lag for each pair of positions.7. The method of ...

Method for on-board prime number generation

The present invention relates to a method to generate prime numbers on board a portable device, said method comprising the steps of, each time at least one prime number is requested: when available, retrieve results from previously performed derivation calculation or, if not, select a start point for derivation; process derivation calculation to converge towards a prime number; if a prime number is found, store it and restart derivation calculation from a new start point; stop the derivation calculation after a predetermined amount of time; store intermediate results to be used a next time a prime number will be requested; output a stored prime number.

ANALYSIS METHOD, ANALYSIS APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM FOR STORING PROGRAM

An analysis method includes: executing first accumulation processing for accumulating analysis reports including an analysis item regarding an analysis target and analysis results with respect to the analysis item; executing first extraction processing for extracting the analysis item and texts representing the analysis results from each of the analysis reports accumulated; executing first identification processing for identifying analysis techniques corresponding to the texts extracted; executing generation processing for generating analysis patterns; executing second identification processing for identifying first analysis patterns; executing third identification processing for identifying other analysis patterns; executing second accumulation processing for accumulating pattern information; executing second extraction processing for extracting the analysis item and the texts from a new analysis report; and executing output processing for identifying an analysis technique.

1-16 & 1.5-7.5 Frequency Divider For Clock Synthesizer In Digital Systems

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot. 1. A frequency doubler having inputs comprising a first clock and a second clock , and having an output , the frequency doubler comprising:a first flipflop having a data input coupled to receive the first clock input and configured to trigger on a rising edge of the second clock input;a second flipflop having a data input coupled to receive the first clock input and configured to trigger on a falling edge of the second clock; andan exclusive-or gate coupled to receive an output from the first flipflop and an output from the second flipflop.2. A divide-by-one-and-a-half divider comprising:a divide-by-three circuit having a square-wave output; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the frequency doubler of .'}3. For N an integer between 1 and 7 , a divide-by-N-and-a-half divider having an output comprising a divide-by-2N-plus-1 digital divider; coupled to drive a frequency doubler coupled to drive the output with pulses having width determined from edges of a digital clock.4. The divider of wherein the frequency doubler comprises:a first flipflop having a data input coupled ...

Methods and Systems for Constructing and Analyzing Component-Based Models of Engineering Systems Having Linear and Nonlinear Regions

In one aspect, a method for modeling and analyzing a physical system comprising a plurality of components includes constructing, by a computing device, a model of the plurality of components. The computing device determines that the at least one component in the plurality of components represents a region for which at least a first portion of an associated partial differential equation is linear. The computing device accesses one of a plurality of datasets, the accessed dataset comprising a representation of the first portion of the partial differential equation. The computing device determines that a subset of the plurality of components encapsulates a region for which a second portion of the associated partial differential equation is non-linear. The computing device generates a combined output based on the partial differential equation combining the first portion and the second portion. 1. A computer-implemented method for modeling and analyzing a physical system comprising a plurality of components , the method comprising:constructing, by a computing device, a model of the plurality of components, wherein the model is based at least in part on at least one parameter relating to a physical characteristic of at least one component;determining, by the computing device, that the at least one component in the plurality of components represents a region for which at least a first portion of an associated partial differential equation is linear; the component is an N-dimensional component, N being at least 2,', 'the component comprises an N-dimensional interior region and an (N−1)-dimensional port,', 'the dataset comprises a plurality of basis functions for a reduced basis space associated with an interface function for the (N−1)-dimensional port, and', 'a solution of the first portion of the partial differential equation represented by the accessed dataset depends on at least two independent spatial variables;, 'accessing, by the computing device, based at least in ...

Frequency multiplier

The frequency multiplier consists of a binary counter which counts fixed-frequency pulses for the duration of the period of an input signal. A second binary counter continuously counts pulses of a second frequency which is a multiple of the fixed frequency. When the count of the first binary counter has been reached, the second binary counter is cleared by a comparator and starts to count again from the beginning. Each clearing produces an output pulse. The ratio between input frequency and output frequency is equal to the ratio between the frequency of the pulses counted by the first binary counter and the frequency of the pulses counted by the second binary counter. To multiply the frequency of square wave signals whilst retaining the ratio between the duration of the positive part and the negative part of the input amplitude, pulses of a fixed frequency can be counted into a binary counter in each case for the duration of a positive or negative input amplitude part. To generate an output amplitude part, a chip used for switching the inputs of a comparator can connect the comparator outputs to the outputs of the binary counter used for measuring the amplitude part corresponding to the amplitude part to be generated, or to memories following this counter. The inputs of the comparator to be compared therewith are connected to the outputs of a secondary binary counter which counts pulses of a frequency which is different from the frequency used for measuring the amplitude parts. The output pulses of the comparator or of an AND gate, the inputs of which are preceded by invertors which, in turn, are connected to the outputs of the second binary counter, are divided by two in order to obtain the output signal of the frequency multiplier.

METHOD AND DEVICE FOR EVALUATING AN ANGLE ON AN EXTENDED RANGE

SYSTOLIC ARRAY DESIGN FOR SOLVING PARTIAL DIFFERENTIAL EQUATIONS

Embodiments relate to a system for solving differential equations. The system is configured to receive problem packages corresponding to problems to be solved, each comprising at least a differential equation and a domain. A solver stores a plurality of nodes of the domain corresponding to a first time-step, and processes the nodes over a plurality of time-steps using a systolic array comprising hardware for solving the particular type of the differential equation. The systolic array processes each node to generate a node for a subsequent time-step using a sub-array comprising a plurality of branches, each branch comprising a respective set of arithmetic units arranged in accordance with a corresponding term of the discretized form of the differential equation, and an aggregator configured to aggregate the corresponding terms from each branch to generate node data for the subsequent time-step. 1. A systolic array configured for discretized solving of a partial differential equation associated with a domain comprising a plurality of nodes , comprising: a plurality of branches, each comprising a respective set of circuit elements connected in series and selected based upon a respective term of a discretized form of the partial differential equation, and configured to receive, at a first circuit element of the respective set of circuit elements, the value of the respective node, and to output, at a last circuit element of the respective set of circuit elements, a value of the respective term generated by processing the value of the respective node through each circuit element of the respective set of circuit elements; and', 'an aggregator configured to aggregate the generated values of the respective terms from each of the plurality of branches to generate the value of the respective node for the next discrete step,', 'wherein the respective sets of circuit elements of the plurality of branches are arranged in a plurality of layers, wherein during each of a plurality ...

A parametrizable control module comprising first and second loadables counters, an electronic circuit comprising a plurality of such parametrized control modules, and a method for synthesizing such circuit

Frequency multiply circuit using smd, with arbitrary multiplication factor

개시한 체배회로는, 입력신호의 주파수를 가변으로 체배한 출력신호를 출력하고 입력신호의 주기를 측정하는 주기측정용 지연회로, 주기측정용 지연회로에서 측정된 주기에 기초하여 지연시간이 가변으로 설정되고 지연시간을 재현하는 지연재현용 지연회로를 구비한 동기지연회로, 동기지연회로로부터 출력되는 위상이 다른 복수의 신호를 받아 다중화하는 다중회로, 및 설정체배값에 따라 주기측정용 지연회로의 지연단수, 지연재현용 복수의 지연회로의 단수의 설정을 가변으로 설정하는 제어회로를 구비하고, 다중회로로부터 입력신호에 동기하여 그 주파수를 체배한 출력신호가 출력된다. 체배회로 The disclosed multiplication circuit outputs an output signal obtained by multiplying the frequency of the input signal by a variable, and the delay time is variable based on the period measured by the period measuring delay circuit and the period measuring delay circuit. A synchronous delay circuit having a delay reproducing delay circuit configured to reproduce the delay time, a multiple circuit for receiving and multiplexing a plurality of signals having different phases output from the synchronous delay circuit, and a delay circuit for periodic measurement according to a set multiplication value And a control circuit for setting the number of delay stages of the delay stage and the plurality of delay circuits for delay reproduction to be variable, and output signals obtained by multiplying their frequencies in synchronization with the input signals from the multiple circuits. Multiplication circuit

Device for moving object control

A numerical control device for such as machine tool operation, in which position and speed of movement of the tool or the workpiece is automatically effected in accordance with a preset program and certain recorded preselected information. The control provides for movement along a segment of the desired path generally in three phases: 1) acceleration to a predetermined maximum speed; 2) constant speed, and, 3) deceleration to zero speed. However, provision is also made for continuous movement along adjacent path segments through elimination of the third phase of the first segment.

Digital-to-analog converter

1444216 Digital - to - analogue conversion STANDARD TELEPHONES & CABLES Ltd 20 Feb 1975 7157/75 Heading H3H An analogue output is derived from a P.C.M. signal by increasing its sampling rate in interpolator 1, converting only the most significant bits to a pulse density signal in a rate-multiplier 3, and low-pass filtering 4 to give the analogue output. Noise is reduced by feeding back the least significant bits through a filter 12. The filter may comprise one or more delays whose outputs are combined with different weighting factors: several examples are described, Figs. 4, 8, 10, 11, not shown. The interpolator may be simply a recirculating register, Fig. 6, not shown, for merely repeating each P.C.M. word, e.g. 32 times or may be a linear interpolator, Fig. 7, not shown. D-to-A converter 3 comprises a synchronous binary counter 5, Fig. 2, fed with fast clock pulses fc, binarily weighted frequencies being obtained at its outputs A, B, C, D which are gated by the 4 most significant bits of the interpolated P.C.M. signal to produce a pulse train E of mean density corresponding to these 4 bits.

Coincidence circuit for time sharing type counter

Pulse capture unit and apparatus for controlling the blending of two flowable substances

A device is described which will accept trains of pulse signals on inputs thereof and will provide corresponding trains of pulse signals on corresponding outputs such that the number of pulse signals in the train at any of these outputs is equal to the number of pulse signals on the train at the corresponding input and such that there is never coincidence of pulse signals on these outputs regardless of whether or not there is coincidence of pulse signals on the inputs. In application of the device to a blending system two pipe lines for fluids to be blended have respective pulse transducers connected to respective inputs of such a device. The transducer for the minor component of the blend provides its pulses via said device to a counter which on reaching a predetermined count corresponding to the volume of the minor component in a standard quantity of the desired blend produces a signal to close a valve in the minor component flow line. The pulses at both outputs of said device are counted together by a further counter which on reaching a count corresponding to said standard quantity re-sets the first mentioned counter causing said valve in the minor component flow line to open again.

Information counter

Full Adder

본 발명은 전가산기에 관한 것으로, 낸드게이트와 노아게이트, 인버터, PMOS트랜지스터, NMOS트랜지스터 및 전송게이트로 구성된 전가신기를 개시한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder, and discloses a full transfer device consisting of a NAND gate, a noah gate, an inverter, a PMOS transistor, an NMOS transistor, and a transfer gate. 본 발명에 따른 전가산기는 종래의 전가산기에 비하여 처리속도가 향상된 특성을 갖는다. The full adder according to the present invention has an improved processing speed compared to the conventional full adder. 전가산기, 낸드게이트, 노아게이트, 인버터, 전송게이트 Full adder, NAND gate, Noah gate, Inverter, Transmission gate

Device for measuring ratio of pulse numbers of pulse trains

Arrangement for measuring the ratio between a number of sequential events occurring in a first series of events and a number of events in a second series of events, each series activating a pulse generator (P1, P2) included in the arrangement. The arrangement further comprises a counter (C) which is stepped forward by the pulses generated by the pulse generator (P1) controlled by the first series of events. A multiplying arrangement (D1) receives the counter value of the counter (C) and multiplies this value by a factor m where m indicates a selected part of the received counter content. The multiplying arrangement (D1) receives on a control input, a pulse from the pulse generator (P2) controlled by the second series of events. When the arrangement (D1) receives that pulse it feeds a signal to a subtracting input of the counter (C), which signal reduces the counter content by a number of steps corresponding to the multiplication result, so that the counter content varies between two limit values. An indicating unit (I) is arranged for indicating the difference between this two limits thus showing the quotient between the number of events of the two series of events.

Motor controlling method & device on numeric controlling system

본 발명은 프로그램 내장방식의 전용컴퓨터를 사용하는 수치제어시스템의 모터제어 방법 및 그 장치에 관한 것으로, 메인중앙처리장치에서 각 축의 모터가 구동하여야 할 변위량에 해당하는 초기값을 산출하고 슬레이브 중앙처리장치에서는 상기 메인중앙처리장치에서 산출한 초기값에 해당하는 모터의 변위량에 의거하여 모터의 구동을 제어하도록 함으로써 중앙처리장치별로 수치제어기능을 분담하여 수행할 수 있으며, 이에 따라 수치제어에 소요되는 실행속도를 단축할 수 있고 또한 순간적으로 변동하는 상황에 신속히 적응제어할 수 있는 효과가 있게 된다. The present invention relates to a motor control method and apparatus for a numerical control system using a dedicated computer with a built-in program. The main central processing unit calculates an initial value corresponding to an amount of displacement to be driven by a motor of each axis and performs slave central processing. In the apparatus, by controlling the driving of the motor based on the displacement of the motor corresponding to the initial value calculated by the main central processing unit, the numerical control function can be shared for each central processing unit. The speed of execution can be shortened and the effect can be quickly adapted to the situation that changes momentarily.

Up-down counter of digital integrator

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Clock control method and circuit

Device for industrial process automatic control

"PROCESS CONTROL APPARATUS" includes two transducers for measuring two parameters of the process, and a memory unit to which the outputs from the transducers are fed. The memory unit produces an output dependent on the values of the two parameters, this output being binary, and being coupled to a counter which also receives clock pulses. The counter samples the memory unit output, and produces an output pulse when the clock pulse reading is equal to the sample reading. The output pulses are then used to control the process.

A frequency multiplier

本发明公开了一种用于倍增信号、也即脉冲序列的脉冲频率的设备，所述设备包括用于所述信号的输入装置以及用于在多个点上访问所述信号的装置，所述信号在所述点之间具有预定的相位差。所述设备另外包括在第一级上的用于组合被访问的信号对的装置，在所有被组合的对内具有同一相位距离，来自每第一级组合装置的输出是脉冲序列。所述设备另外包括在第二级上的用于组合来自第一级的脉冲序列的组合装置，并且所述在第一级上的组合装置是这样的以致于在它们输出脉冲序列中的脉冲具有通常与被组合的访问信号对中的第一信号的上升沿重合的上升沿，以及具有通常与所述对中的第二信号的下降沿重合的下降沿。

Signal processing circuit, instrument for testing electric power consumption

FIELD: instruments. SUBSTANCE: signal processing circuit has modulation stages and demodulation stages for specific frequency ratio. EFFECT: increased precision. 14 cl, 4 dwg 65 9э99бгс пы сэ РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (19) ВИ “” 2 156 539 ' (51) МПК? 13) С2 Н 03 М 3/00, С 01 В 11/47, 11/48 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 94001560/09, 19.01.1994 (24) Дата начала действия патента: 19.01.1994 (30) Приоритет: 20.01.1993 ЕР 93400131.4 (46) Дата публикации: 20.09.2000 (56) Ссылки: ЕК 2570854 АЛ, 28.03.1986. ЦЗ 3659288 А, 25.04.1972. 4$ 400941ТЪ А, 22.02.1977. Ц 1444832 АЛ, 15.12.1988. $0 1539800 АД, 30.01.1990. 4$ 4622640 А, 11.11.1986. (98) Адрес для переписки: 129010, Москва, ул. Большая Спасская 25, стр.3, ООО "Городисский и Партнеры", Емельянову Е.И. (71) (72) (73) Заявитель: ШЛЮМБЕРЖЕ ЭНДЮСТРИ С.А. (ЕК) Изобретатель: Мишель ЖЕРВЭ (ЕК), Ален БАЗЭН (ЕК), Дениз ШАНГ (ЕК) Патентообладатель: ШЛЮМБЕРЖЕ ЭНДЮСТРИ С.А. (ЕВ) (54) СХЕМА ОБРАБОТКИ СИГНАЛА, ИЗМЕРИТЕЛЬНЫЙ ПРИБОР ДЛЯ КОНТРОЛЯ ПОТРЕБЛЕНИЯ ЭЛЕКТРИЧЕСТВА (57) Изобретение относится к измерительной технике и может быть использовано в каскадах модуляции в схемах обработки сигналов. Техническим результатом является повышение точности. Схема обработки сигнала содержит каскады модуляции и демодуляции сигналов при определенном отношении частот. Сущность изобретения заключается В использовании схемы обработки сигналов. 3 с. и 11 з. п. ф-лы, 4 ил. Тен = А/ЕСА 1 {Монзер 2 3 и“ @ РеЗРСВ Фиг.1 2156539 С2 КО 65 9э99бгс пы сэ (19) КУЗЗАМ АСЕМСУ ГОК РАТЕМТ$ АМО ТКАОЕМАКК$ 12) АВЗТКАСТ ОЕ 1МУЕМТОМ ВОИ "” 2 156 539 ^^ С2 51)" 17 Ц 03 М 3/00, С 01 В 11/17, 11/48 (21), (22) АррИсаНоп: 94001560/09, 19.01.1994 (24) ЕНесНуе дае Гог ргорейу па: 19.01.1994 (30) Рпогйу: 20.01.1993 ЕР 93400131.4 (46) Рае оГ рибИсаНоп: 20.09.2000 (98) Май адагез$: 129010, МозКкуа, ш. Во!эпа]а Зраззка]а 25, зг.3, ООО "Согоа!$ ки 1 Райпегу", Ете!апоми Е.1|. (71) АррИсапе: ЗЕ иМВЕК7ВЕ ЕВМОи ТЕ $.А ...

Frequency multiplier and method capable of adjusting clock duty cycle

Digital differential analyzer

Frequency synthesizer

Pulse generator

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Numerically controlled oscillator in particular for a radiofrequency signal receiver

특히 고주파 신호 수신기에 수치제어 발진기(8)가 장착되며, 고주파 신호의 수신 및 정형을 위한 수단(3), 상관 스테이지(4), 클럭 신호 발생기를 추가로 포함한다. 발진기는 발진기 동작을 클럭하는 제 1 주파수(CLK)를 가지는 클럭 신호와, 여러 비트의 이진워드(Nb)를 한 입력에서 수신하여, 상기 이진워드와 클럭 신호의 함수로 결정되는 주파수를 가지는 한 개 이상의 출력 신호(Mb)를 한 출력에서 제공한다. 발진기는 이진워드의 상위 비트 숫자 Ob에 대한 제 1 누산 스테이지(12)와, 상기 이진워드의 하위 비트 숫자(Pb)에 대한 제 2 누산 스테이지(11)를 포함한다. 제 1 누산 스테이지는 지정 주파수 출력 신호(Mb) 공급을 위해 제 1 클럭 주파수(CLK)로 클럭되고 제 2 스테이지는 상기 제 1 클럭 주파수보다 N배 작은 제 2 클럭 주파수(CLK/N)로 클럭된다. 제 2 스테이지로부터의 출력 비트(Qb)나 이진 신호는 N과 곱하여져서, 제 1 주파수(CLK)에서 클럭 신호의 매 N주기마다 제 1 스테이지의 입력에 공급된다. In particular, the high frequency signal receiver is equipped with a numerically controlled oscillator 8, and further includes means 3 for receiving and shaping the high frequency signal, a correlation stage 4, and a clock signal generator. An oscillator receives a clock signal having a first frequency CLK for clocking an oscillator operation and a binary word Nb of several bits at one input, and has a frequency determined as a function of the binary word and a clock signal. The above output signal Mb is provided at one output. The oscillator comprises a first accumulating stage 12 for the upper bit number Ob of the binary word and a second accumulating stage 11 for the lower bit number Pb of the binary word. The first accumulation stage is clocked at a first clock frequency CLK to supply a specified frequency output signal Mb and the second stage is clocked at a second clock frequency CLK / N which is N times less than the first clock frequency. . The output bit Qb or binary signal from the second stage is multiplied by N and supplied to the input of the first stage every N periods of the clock signal at the first frequency CLK.

Numerical controlling method for high dynamic processor

내용 없음. No content.

Programable counter

Programmable subframe typed pwm circuit

내용 없음.

Counter for inputting simultaneously plural inputs

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Programmable frequency divider

Frequency setting equipment generating various frequencies

Digital phase shift control for phased array antenna

Signal processing system

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Periodic interval integration circuit for digital signal

A circuit is for integrating the signal for the fixed interval with using a digital counter. The circuit comprises a first means for producing the up/down control signal and the enable signal by using the input digital signal, a second means for integrating the signal according to the up/down control signal and the enable signal, and a third means for converting the digital signal from the second means into the analog signal.

Clock control method and clock control circuit

귀환 구성을 취하지 않고, 외부 클럭에 위상 동기가 가능하도록 한 완전 신규한 클럭 제어 회로 및 방법을 제공한다. 제1 지연 회로(10)와, 제1 지연 회로의 출력을 지연 시간 t2 지연시키는 제1 내분 회로(11)로 구성되는 유닛을 N단 구비한 지연 회로 열과, 입력 클럭 IN과 지연 회로 열로부터 출력되는 클럭 END로부터 클럭 주기와 지연 회로 열의 지연 시간 차를 두 개의 신호의 위상 차 T로서 검출하는 위상 차 검지 회로(14)와, 제1 지연 회로의 출력을 입력하는 복수의 제2 내분 회로 (12)는, 위상 차 T에 기초하여 제1 지연 회로의 출력의 천이 엣지를 t2-n×T/N 지연시켜서 출력하고, 제2 내분 회로는 클럭 사이클의 개시 시점으로부터, n×tCK/N 지연된 타이밍으로 천이하는 신호를 각각 출력하고, 입력 클럭 IN과, 1 내지 N-1번째 제3 지연 회로의 출력으로부터, 상기 입력 클럭의 클럭 주기 tCK를 등분하여 구성되는 체배 클럭을 생성하는 합성 회로(13)를 포함한다.

A method and fast multiplier using crt

PURPOSE: A method of high speed multiplication using a CRT(Cathode Ray Tube) and an apparatus thereof are provided to increase calculation speed by reducing a CSA(Carry Save Adder) step and carry delay with a look up table. CONSTITUTION: A plurality of I modules(10) decodes an input signal using numbers. A plurality of calculator(20) multiplies outputs from the I modules. A plurality of reciprocal number calculators(30) calculates a reciprocal number of the outputs from the plurality of calculators. A CSA tree(40) changes the outputs of the plurality of reciprocal number calculators into a binary number. A moduli calculation part(50) calculates the outputs of the CSA tree with moduli. A 2's complement part(70) classifies the outputs of the moduli calculation part into a positive number or a negative number. The 2's complement part outputs a multiplication result of 16 bits by adding the output of an XOR gate(60).

Despiking method of abnormal signal data acquired with using three-dimensional doppler velocimetry in open channel flow and system for the same

Disclosed are a method for smoothing an abnormal signal of flow speed data acquired by a three-dimensional Doppler flow meter in an open channel flow, and a system for the same. The method for smoothing an abnormal signal of flow speed data acquired by a three-dimensional Doppler flow meter in an open channel flow according to an embodiment of the present invention can provide a clear standard of determination for an abnormal signal which used to be hard to be distinguished from components of turbulence by determining whether the abnormal signal exists or not by using an elliptic equation from a second derivative derived from instant flow speed data, can produce a result including an aspect of change of the instant flow speed data since the components of turbulence can be considered in a smoothing step, and can calculate flow speed data with minimized error for a general river which contains a large amount of foreign materials or in which sediment is actively transported.

Frequency multiplying transceiver

本发明描述一种使能无线通信的超低功率发射和接收的无线收发器及相关方法。在无线收发器的示例性实施例中，无线收发器接收具有第一参考频率的第一参考信号。然后无线收发器使用第一参考信号来注入锁定本地振荡器，该本地振荡器提供一组振荡信号，每个振荡信号具有等于第一参考频率的振荡频率，并且每个振荡信号具有相等地间隔的相位。然后无线收发器将振荡信号集组合成具有输出频率的输出信号，该输出频率是以下两项之一：（i）第一参考频率的倍数（根据发射器实施方式），或（ii）（a）第二参考信号的第二参考频率与（b）第一参考频率的倍数之间的差值（根据接收器实施方式）。

Multiplying circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Operation processing method of central processing unit

본 발명은 CPU(Central Processing Unit)의 연산 처리 방법에 관한 것으로, 초기 시동 후에 초기 위상차를 설정한 다음 기준 위상차를 연산하고, 각 카운터 값에 대한 위상차를 연산하여 저장하는 제1 단계와; 상기 제1 단계의 수행이 완료되고 카운터를 구동하여 카운터 값에 대한 계산 결과 값을 읽어들인 후에 해당 값에 의한 디지털/아날로그 변환 제어를 수행하는 제2 단계와; 상기 제2 단계의 수행 후에 클럭원의 안정도가 기준에 만족하는가를 판단하여 이에 따라 상기 제2 단계를 반복하여 수행하거나, 이전 출력을 그대로 유지하도록 하는 홀드 오버 모드(Hold over Mode)를 동작하고 종료하는 제3 단계로 이루어진 방법을 제공하는데, 복잡한 상수 계산을 위한 프로그램 작성 시, 연산에 대한 로드(load)가 많이 발생하는 CPU의 수행 능력 저하를 미연에 방지하여 다른 서브루틴의 수행이나 인터럽트 제어 시에 딜레이의 발생을 억제함으로써, 시스템 제어나 계측 분석 시에 많은 오차가 발생되는 것을 방지하는 등의 효과가 있다. The present invention relates to a computational processing method of a central processing unit (CPU), comprising: a first step of setting an initial phase difference after initial startup, calculating a reference phase difference, and calculating and storing a phase difference for each counter value; A second step of performing the digital / analog conversion control based on the value after the completion of the first step and driving the counter to read the calculation result value for the counter value; After the execution of the second step, it is determined whether the stability of the clock source satisfies the criterion, and accordingly, the second step is repeated or the hold over mode for maintaining the previous output is performed. It provides a method consisting of a third step, which is used to write a program for calculating a complicated constant, and prevents the CPU's ability to perform a large load of operations in advance, when performing another subroutine or interrupt control. By suppressing the occurrence of delay, it is possible to prevent a large number of errors from occurring during system control and measurement analysis.

All-Optical Full Adder by Using Semiconductor Optical Amplifiers

본 발명은 반도체 광증폭기 (SOA)의 이득포화 특성을 이용하여 전광 가산기를 구현할 수 있는 기술로서, 전광 가산기의 SUM과 CARRY의 동작에는 각각 2개의 전광 XOR 논리소자와 4개의 전광 NOR 논리소자가 이용되었으며, 두 연산이 동시에 구현되었다. The present invention is a technology capable of realizing an all-optical adder using gain saturation characteristics of a semiconductor optical amplifier (SOA), and two all-optical XOR logic elements and four all-optical NOR logic elements are used for the operation of SUM and CARRY of the all-optical adder. Both operations were implemented simultaneously. 전광 가산기, XOR 논리소자, NOR 논리소자, 반도체 광증폭기, SUM, CARRY All-optical adder, XOR logic element, NOR logic element, semiconductor optical amplifier, SUM, CARRY

Counting device

Position determining apparatus and transducer therefor

An apparatus for determining the position of a movable element or stylus which is movable in a data space. In accordance with the invention there are provided first and second spaced receivers, each receiver comprising a hollow shell of piezoelectric material, which may be cylindrical or spherical in shape, and resilient conductive means coupled across the inner and outer surfaces of the shell. Means are provided for periodically generating a source of sound waves for travel between the stylus and the first and second receivers. Timing means are coupled to the receivers and synchronized with the generation of the sound waves for measuring transit time of the sound waves between the source and receivers. Computing means are employed to determine the positional coordinates of the stylus in a desired coordinate system, such as rectangular coordinates. In an embodiment of the invention the first and second receivers have conductive mesh loaded within the shell and in contact with the inner surface of the shell. In this embodiment a spring contact is coupled to the outer surface of the shell. In an embodiment of the invention the movable element or stylus is passive and means are provided for periodically generating sound waves at a source position spaced from the movable element. This eliminates the need for an "active" stylus and the problems associated therewith.

Digital switch

Data transfer device of semiconductor memory including a divider device of clock frequency

본 발명은 반도체 메모리에서 클럭에 동기하여 동작하는 디램에 관한 것으로, 특히 디램의 내부 회로내에 클럭을 데이터의 최상 경로와 그외 경로로 구분하여 클럭 주파수를 체배함으로써, 발신 클럭을 최상 경로에 사용하고 체배된 클럭은 그외 경로에 사용하여, 내부의 데이터 전달 비율을 향상시켜서 빠른 데이터 전달을 구현할 수 있도록, 클럭을 발생시키는 클럭 제너레이터(10)와, 상기 클럭 제너레이터(10)로부터 발생된 발신 클럭에 동기되어 데이터, 어드레스, 명령어 등을 직렬로 수신하는 데이터 입력 버퍼(20); 상기 데이터 입력 버퍼(20)를 통하여 수신된 데이터를 데이터 패킷으로 합쳐서 메모리(50)에 병렬로 전달하는 데이터 시프트 레지스터(30) 및; 상기 클럭 제너레이터(10)에서 발생된 발신 클럭 주파수를 체배하여 데이터 시프트 레지스터(30)에서 발생된 발신 클럭 주파수를 체배하여 데이터 시프트 레지스터(30)로 입력하는 클럭 주파수 체배기(40)로 구비한, 클럭 주파수 체배 장치를 포함하는 반도체 메모리 장치의 데이터 전송 장치에 관한 것이다.

Function generator by data selector

Device for obtaining given variation of ignition lead angle

1479205 Ignition systems; timing ignition G HARTIG 7 June 1974 [26 July 1973] 25310/74 Heading F1B Apparatus for varying the ignition timing in an internal combustion engine comprises pulse generation means for deriving from a rotating part of the engine a sequence of pulses all of which are of substantially equal length, counting means 8 for performing a succession of counting operations during each of which the number of pulses occurring during a time t is counted, a control device for performing an arithmetical operation on the number of pulses counted during each time t or for altering the time t of the next count in dependence on the number of pulses counted during the preceding counting operation, the result of each arithmetical operation or the number of pulses counted during the altered time t being a reference count representing the angle of spark advance α relative to the top dead centre, counting means, which are the same as or different from the firstmentioned counting means for counting, starting from each reference count, from an arbitrary phase position which is advanced from the top dead centre by an angle # until a predetermined total number of pulses has been counted which represent the angle # and means for causing an ignition spark to be produced each time the predetermined total number of pulses has been counted whereby each spark occurs advanced by the angle α relative to the top dead centre. Fig. 4 shows how the circuit of Fig. 3 can be modified to be in accordance with the invention. The reference numeral 50 indicates a coding matrix which has a series of first inputs 51 and a second series of inputs 52a, 52b, 52c and so on. The inputs 51 are shown as connected to the outputs 10 to 13 of the counter 8. Values of operating parameters of the engine are fed through the inputs 52a, 52b and 52c. These values may represent engine temperature intake manifold vacuum, throttle valve position and so on. The pulses from the transmitter 2 are fed to the ...

Poly-phase frequency synthesis oscillator

A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.

Programmable counter

Two-threshold comparator of the binary bit range

FIELD: computer technology. SUBSTANCE: two-threshold comparator of the binary bit range is disclosed, containing an N-bit input bus D, an input bus of a lower threshold (of boundary) GL and an input bus of an upper threshold (of boundary) GM containing M bits, where M=]log 2 (N+1)[ (a larger integer), an output bus QL of the number of single bits up to a lower boundary, an output bus QC of the number of single bits inside the range and an output bus QM of the number of single bits above an upper boundary, also containing M bits, flag FL of single bits up to the lower boundary, flag FC of single bits inside the range, flag FM of single bits above the upper boundary, and an internal bus UL of junior ordered units, an internal bus UC of ordered units within the range, an internal bus UM of senior ordered units containing M bits, a decoder of the lower boundary 1, a decoder of the upper boundary 2, the first group 3 1 , 3 2 , …, 3 N-1 , and the second group 4 1 , 4 2 , …, 4 N-1 , each of which contains (N-1) elements OR, the group 5 1 , 5 2 , …, 5 N of N elements OR-NOT, the first group 6 1 , 6 2 , …, 6 N , the second group 7 1 , 7 2 , …, 7 N , and the third group 8 1 , 8 2 , …, 8 N , each of which contains N elements AND, the first 9 1 , the second 9 2 and the third 9 3 blocks of counting units, as well as the first 10 1 , the second 10 2 and the third 10 3 elements OR. EFFECT: technical result of the invention is providing the possibility of determining the number of single bits in the given range between lower and upper boundaries and the number of single bits outside the range. 1 cl, 1 dwg, 1 tbl РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 758 205 C1 (51) МПК G06F 7/60 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК G06F 7/60 (2021.05); G06F 7/607 (2021.05) (21)(22) Заявка: 2020143833, 29.12.2020 (24) Дата начала отсчета срока действия патента: 26.10.2021 Приоритет(ы): (22) Дата подачи заявки: 29.12.2020 (45) ...

Duty correction based frequency multiplier

위상동기 루프나 지연동기 루프를 이용하는 주파수 체배기의 단점을 제거하고 또한 집적회로로 구현될 경우 칩 면적이 작고 전력소모가 적은 주파수 체배기 및 주파수 체배방법이 개시된다. 제1듀티 정정회로는 제1신호를 수신하여 주파수는 상기 제1신호와 동일하고 듀티가 50:50인 제2신호를 발생한다. 에지 검출기는 상기 제2신호의 에지들을 검출하여 검출된 에지들에 대응하는 펄스들을 갖는 제3신호를 발생한다. 제2듀티 정정회로는 상기 제3신호를 수신하여 주파수는 상기 제3신호와 동일하고 듀티가 50:50인 제4신호를 발생한다. 따라서 상기 주파수 체배기 및 주파수 체배방법은 위상동기 루프나 지연동기 루프를 이용하지 않고 간단한 회로들로 구성되므로 위상동기 루프나 지연동기 루프를 이용하는 경우에 발생되던 지터 문제나 부정확한 락 문제를 원천적으로 제거할 수 있으며 또한 집적회로로 구현될 경우 위상동기 루프나 지연동기 루프를 이용하는 경우에 비해 칩 면적이 작고 전력소모가 적은 장점이 있다. Disclosed are a frequency multiplier and a frequency multiplication method that eliminate the disadvantages of a frequency multiplier using a phase-locked loop or a delayed-locked loop and are implemented as an integrated circuit and have a small chip area and low power consumption. The first duty correction circuit receives the first signal and generates a second signal having a frequency equal to the first signal and having a duty of 50:50. An edge detector detects the edges of the second signal and generates a third signal having pulses corresponding to the detected edges. The second duty correction circuit receives the third signal and generates a fourth signal having a frequency equal to the third signal and having a duty of 50:50. Therefore, the frequency multiplier and the frequency multiplying method are composed of simple circuits without using a phase lock loop or a delay lock loop, thereby eliminating jitter or inaccurate lock problems caused by using a phase lock loop or a delay lock loop. In addition, when implemented as an integrated circuit, there is an advantage in that the chip area is smaller and the power consumption is lower than in the case of using a phase locked loop or a delay locked loop.

Numerically controlled oscillator, especially for radio frequency signal receivers

Frequency divider with fractional division ratio to generate a symmetrical output signal

Timer device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Counting circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Well logging tool scale selection circuit

1362898 Scale selection TEXACO DEVELOPMENT CORP 4 Sept 1972 41005/72 Heading G4H The division factor of a divider comprising a chain of bi-stables is set remotely by changing the count in a counter, the output of which enables one of a set of gates connected one to each bi-stable. The system may be used for altering the output count of an oil well radioactivity logging tool. As shown, pulses proportional to radiation are generated in " logging tool electronics " 10 and fed via line 11 to bistables 12-17 which act as divide by two circuits. The output of each bi-stable is also connected to the input of an AND gate 44-49 and the outputs of these gates are connected via OR gate 52 to " logging tool electronics ". One gate at a time can be enabled and the output pulses are either logged in 10 or passed to the surface via cable 30. The gate that is enabled is determined by the state of the binary counter comprising bi-stables 55, 56, 57 which are connected to the gates 44-49 so that six of the eight possible slots of the counter enable gates, the other two being used for reference, A.C. pulses are transmitted from the surface to step the counter. These pulses pass low-pass filter 36 and resonant circuit 36 and are converted to D.C. pulses in differential amplifier 40 and trigger 41.

Frequency dividing circuit

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Hearing aid

ABSTRACT OF THE DISCLOSURE In a hearing aid comprising an input transducer, processing circuits for useful signals including an output stage and an output transducer, the useful signals are sampled with a sampling frequency before the output stage, are converted into data words, and are also processed in discrete-time fashion. The digital data words are capable of being converted into pulse-duration-modulated signals without being re-converted into analog signals. For this purpose, the processed data words can be read into a counting circuit via at least one input which can be placed into an initial condition with counting pulses after every read-in data word. The output stage is designed as a switching amplifier and is driven with an output signal of the counting circuit.

Variable frequency divider

Digital frequency multiplying circuit

Patent FR2198190A1