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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 4618. Отображено 100.
09-02-2012 дата публикации

Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device

Номер: US20120033516A1
Автор: Chang-Ho Do
Принадлежит: Individual

A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal.

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Номер записи: 1
16-02-2012 дата публикации

Method and apparatus for word line driver with decreased gate resistance

Номер: US20120037997A1
Автор: Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, You-Cheng Xiao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.

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Номер записи: 2
23-02-2012 дата публикации

Sub word line driver and apparatuses having the same

Номер: US20120043616A1
Автор: Hyang Ja Yang, Jae Young Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A sub word line driver is provided. The sub word line driver includes a first layer including a plurality of first pads disposed in a first line of a first direction, a plurality of second pads arranged in a second line of the first direction, and two first word lines arranged twisted twice in the first direction between the plurality of first pads and the plurality of second pads, each of the two first word lines being connected to a corresponding pad among the plurality of second pads; and a second layer, which is formed at a lower part of the first layer, and includes the second layer including a plurality of third pads, each the plurality of third pads each being embodied disposed at each corresponding a position corresponding to a pad from among one of the plurality of first pads and the plurality of second pads.

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Номер записи: 3
05-07-2012 дата публикации

Semiconductor device and method of generating voltages using the same

Номер: US20120170367A1
Автор: Bon Kwang Koo
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address; a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where the received control bits are generated in response to the command signal and a control signal; and a voltage generation circuit for outputting voltages distributed in response to the enable signals.

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Номер записи: 4
28-02-2013 дата публикации

High voltage generation circuit and semiconductor device including the same

Номер: US20130051159A1
Автор: Je Il RYU
Принадлежит: SK hynix Inc

A high voltage generation circuit includes a plurality of pumps configured to generate a final pump voltage, a plurality of switches configured to couple the pumps to various nodes, a voltage division circuit configured to divide the final pump voltage from the pumps interconnected by the switches, and outputting a divided voltage, a section signal generation circuit configured to generate a plurality of section signals by comparing the divided voltage with each of different reference voltages, and a section signal combination circuit configured to generate enable signals for controlling the switches by combining the section signals.

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Номер записи: 5
04-04-2013 дата публикации

Voltage supply circuit, semiconductor memory device, and operating method thereof

Номер: US20130083614A1
Автор: Duck Ju Kim, Je Il RYU, Pil Seon YOO
Принадлежит: SK hynix Inc

A voltage supply circuit includes a high voltage generator configured to generate an operating voltage, a global word line switch configured to transfer the operating voltage to global word lines, a plurality of local line switches coupled to the global word lines and configured to transfer the operating voltage to corresponding local word lines, a precharge unit configured to supply a precharge voltage to an unselect local line switch adjacent to a select local line switch to which the operating voltage will be supplied, from among the plurality of local line switches, in a preparation section before an operation is started, and a coupling unit configured to couple the unselect local line switch and the global word line switch when the operation is started.

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Номер записи: 6
25-04-2013 дата публикации

Method and apparatus for word line suppression

Номер: US20130100730A1
Автор: Chien-Kuo SU, Chiting Cheng, Chung-Cheng Chou, Jack Liu, Jonathan Tsung-Yung Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.

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Номер записи: 7
25-04-2013 дата публикации

LOCAL WORD LINE DRIVER

Номер: US20130100758A1
Автор: Chen Chung-Kuang, Chen Han-Sung, Hung Chun-Hsiung
Принадлежит:

A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver. 1. A memory circuit , comprising:a word line driver receiving a first voltage reference signal, a second voltage reference signal, and an input signal, the word line driver having an output coupled to a word line; andcontrol circuitry configured to deselect the word line by applying the input signal to the input of the word line driver, wherein during an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.2. The memory circuit of claim 1 , wherein claim 1 , during the program operation in which the word line is deselected and another word line is selected claim 1 , the control circuitry prevents discharge of the word line via only a p-type transistor of the word line driver.3. The memory circuit of claim 1 , wherein the input signal having one of at least a select value and a deselect value claim 1 , the select value and the deselect value having a same voltage polarity during an operation.4. The memory circuit of claim 1 , wherein the first voltage reference signal is received from a global word line claim 1 , the global word line selecting or deselecting a plurality ...

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Номер записи: 8
06-06-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20130141999A1
Автор: NATSUME Hidetaka, Takahashi Hiroyuki
Принадлежит: RENESAS ELECTRONICS CORPORATION

A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits. 1. A semiconductor integrated circuit , comprising:a memory cell that includes a gate transistor;a word line that is connected to a gate of the gate transistor;a bit line that is connected to the memory cell; anda driving circuit that drives the word line, and includes a transistor that has a gate oxide film thicker than a gate oxide film of the gate transistor,wherein a range of voltage between the gate and back-gate of the gate transistor is larger than a voltage range of the bit line.2. The semiconductor integrated circuit according to claim 1 , wherein a voltage difference between the gate and back-gate of the gate transistor in read mode is larger than the voltage range of the bit line.3. The semiconductor integrated circuit according to claim 1 , further comprises:a control circuit that controls writing data to the memory cell or reading data from the memory cell,wherein the range of voltage between the gate and back-gate of the gate transistor is larger than a range of voltage between a power supply voltage and a ground voltage supplied to the control circuit.4. The semiconductor integrated circuit according to claim 3 , wherein a gate oxide film of a transistor constituting the ...

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Номер записи: 9
13-06-2013 дата публикации

MEMORY DEVICE

Номер: US20130148411A1
Автор: Atsumi Tomoaki, Okuda Takashi
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays. 1. A memory device comprising:a driver circuit including a first bit line driver circuit, a second bit line driver circuit, a first word line driver circuit, and a second word line driver circuit;a first memory cell array including a first bit line and a first word line;a second memory cell array including a second bit line and a second word line;a third memory cell array including a third bit line and the second word line; anda fourth memory cell array including a fourth bit line and the first word line with the first memory cell array,wherein:each of the first to fourth memory cell arrays overlaps with the driver circuit,the first bit line driver circuit and the second bit line driver circuit are diagonally opposite to each other in the driver circuit,the first word line driver circuit and the second word line driver circuit are diagonally opposite to each other in driver circuit,the first and second bit line driver circuits and the first and second word line driver circuits are arranged so that in data writing, a signal is transmitted across the first bit line driver circuit toward a boundary between the first word line driver circuit and the first bit line driver ...

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Номер записи: 10
20-06-2013 дата публикации

Memory access control system and method

Номер: US20130155793A1
Автор: Russell Schreiber, Vikram Suresh
Принадлежит: ATI TECHNOLOGIES ULC

The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.

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Номер записи: 11
25-07-2013 дата публикации

Discrete Three-Dimensional Memory Comprising Off-Die Read/Write-Voltage Generator

Номер: US20130188415A1
Автор: Guobiao Zhang
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (V R /V W -generator) is located on a separate peripheral-circuit die. The V R /V W -generator generates at least a read and/or write voltage to the 3D-array die. A single V R /V W -generator die can support multiple 3D-array dies.

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Номер записи: 12
22-08-2013 дата публикации

Circuit for driving word line

Номер: US20130215697A1
Автор: Byeong Chan CHOI, Gyung Tae Kim
Принадлежит: SK hynix Inc

A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.

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Номер записи: 13
19-09-2013 дата публикации

SYSTEM AND METHOD FOR PROCESSING SIGNALS IN HIGH SPEED DRAM

Номер: US20130242685A1
Автор: Ba Ben, Wong Victor
Принадлежит: MICRON TECHNOLOGY, INC.

The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle. 1. A memory device , comprising:bank control logic configured to generate a modified bank address signal by passing a bank address and a delayed bank address signal through an OR gate, wherein the delayed bank address signal is a time delayed version of the bank address signal; and provide a bank activate signal;', 'receive an activate command signal and execute an activate command of the activate command signal at each one of a group of clock cycles, wherein each one of the group of clock cycles is greater than one clock cycle; and', 'receive the modified bank address signal, wherein the modified bank address signal is high for at least a portion of each one of the group of clock cycles, and wherein the at least a portion of each one of the group of clock cycles is greater than one clock cycle., 'an active driver configured to2. The memory of claim 1 , wherein the modified bank address signal transitions to a high state at a first time and transitions to a low state at a second time claim 1 , and the activate command transitions to a high state at a third time and transitions to a low state at a fourth time;wherein the third time is after the first time, and wherein the second time is after the fourth time.3. The memory of claim 2 , wherein a difference between ...

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Номер записи: 14
03-10-2013 дата публикации

Encoding program bits to decouple adjacent wordlines in a memory device

Номер: US20130262743A1
Автор: Ferdinando Bedeschi
Принадлежит: Micron Technology Inc

Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array.

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Номер записи: 15
24-10-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130279285A1
Автор: Lee Bum Jae, Yoo Han Sik
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor memory device includes a memory cell array region and a column decoder. The memory cell array region includes a plurality of memory cell arrays that are arranged in row and column directions. The column decoder includes a first column select line (CSL) driver and a second CSL driver that are disposed adjacent to a first edge of the memory cell array region extending in the row direction and that have different physical layouts. 1. A semiconductor memory device comprising:a memory cell array region comprising a plurality of memory cell arrays each array including memory cells that are arranged in row and column directions, sub-wordline drivers that are disposed between memory cell arrays in the row direction, and conjunction regions that are disposed between sub-wordline drivers in the column direction;protrusion conjunction regions that are disposed adjacent to a first group of the sub-wordline drivers positioned at a first edge of the memory cell array region extending in the row direction and that protrude from the first edge in the column direction; anda column decoder comprising first column select line (CSL) drivers each having a first physical layout and second CSL drivers each having a second physical layout different from the first physical layout, the first and second CSL drivers being disposed adjacent to the first edge of the memory cell array region,wherein the number of the first CSL drivers is greater than the number of the second CSL drivers.2. The semiconductor memory device of claim 1 , wherein the protrusion conjunction regions protrude from the first edge of the memory cell array region by a first distance claim 1 ,wherein each of the first CSL drivers is disposed apart from the first edge by a second distance less than the first distance, andwherein each of the second CSL drivers is disposed apart from the first edge by a third distance greater than the first distance.3. The semiconductor memory device of claim 1 , wherein the ...

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Номер записи: 16
07-11-2013 дата публикации

Memory Arrays

Номер: US20130294132A1
Автор: Zengtao T. Liu
Принадлежит: Micron Technology Inc

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

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Номер записи: 17
21-11-2013 дата публикации

HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

Номер: US20130308410A1
Автор: Chevallier Christophe, Siau Chang Hua
Принадлежит: UNITY SEMICONDUCTOR CORPORATION

Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example. 1. An integrated circuit , comprising:a substrate;a base layer formed on the substrate and including discrete devices configured to operate within a first voltage range; a plurality of X-line conductive array lines,', 'a plurality of Y-line conductive array lines, and', 're-writable two-terminal memory cells configured to operate within a second voltage range that is greater than the first voltage range, each memory cell having one terminal electrically coupled with one of the plurality of X-line conductive array lines and another terminal electrically coupled with one of the plurality of Y-line conductive array lines;, 'at least one cross-point memory array formed above the base layer and electrically coupled with the devices in the base layer, each cross-point memory array including'}an X-line decoder including a first subset of the discrete devices that operate in the first voltage range; anda Y-line decoder including a second subset of the discrete devices that operate in the first voltage range,wherein ...

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Номер записи: 18
05-12-2013 дата публикации

Semiconductor memory device

Номер: US20130322163A1
Автор: Yoshihiro Ueda
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor memory device includes a first cell array includes memory cells and reference cells, a second cell array located adjacent to the first cell array in a first direction, a third cell array located adjacent to the first cell array in a second direction crossing the first direction, a fourth cell array located adjacent to the second cell array in the second direction, and a sense amplifier connected to the first to fourth cell array and configured to compare a current through a memory cell with a current through a reference cell to determine the data of the memory cell. A reference cell is selected from a cell array which is diagonally opposite to a cell array as a read target.

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Номер записи: 19
16-01-2014 дата публикации

Word line driver circuits and methods for sram bit cell with reduced bit line pre-charge voltage

Номер: US20140016400A1
Автор: James D. Burnett, Perry H. Pelley
Принадлежит: Individual

A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN).

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Номер записи: 20
16-01-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE HAVING SELECTIVE ACTIVATION CIRCUIT FOR SELECTIVELY ACTIVATING CIRCUIT AREAS

Номер: US20140016427A1
Автор: KITAYAMA Makoto
Принадлежит: ELPIDA MEMORY, INC.

A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command. 1. A method comprising:producing one or more bank selective signals and one or more area selective signals in response to one or more bank address signals and one or more area address signals, respectively;providing each of the bank selective signals to a corresponding one of a plurality of memory banks;providing the area selective signals in common to the memory banks;supplying a voltage to one of logic circuits of one of memory banks; andpreventing from supplying the voltage to another of logic circuits of the one of the memory banks;the one of the memory banks being selected in response to the bank selective signals, the one of the logic circuits being selected in response to the area selective signals and another of the logic circuits being unselected in response to the area selective signals.2. The method as claimed in claim 1 , wherein the memory banks respectively include main power source lines each supplied with the voltage claim 1 , each of the logic circuits including a sub power source line and a gate transistor coupled between a corresponding one of the main power source lines and the sub power source line thereof claim 1 , the supplying the voltage to the one of the logic circuits of the one of the memory banks being performed through ...

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Номер записи: 21
13-02-2014 дата публикации

ADDRESS DECODER, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, METHOD OF OPERATING THE SAME

Номер: US20140043929A1
Автор: JANG Chae Kyu
Принадлежит: SK HYNIX INC.

A semiconductor memory device and method of operating the same is disclosed. The semiconductor memory device includes an address decoder including pass transistor groups, a memory block selector coupled in common to the pass transistor groups, and a block decoding section configured to deliver an enable signal through the block word line based on a block group address. The memory block selector is configured to deliver the enable signal to a first pass transistor group selected from the the pass transistor groups in response to a block select signal to activate the first pass transistor group. 1. An address decoder comprising:pass transistor groups;a memory block selector coupled in common to the pass transistor groups; anda block decoding section coupled to the memory block selector through a block word line, and configured to deliver an enable signal through the block word line based on a block group address;wherein the memory block selector is configured to deliver the enable signal to a first pass transistor group selected from the pass transistor groups according to a block select signal to activate the first pass transistor group.2. The address decoder of wherein the block group address and the block select signal are included in a block address received from an external circuit for accessing a memory block.3. The address decoder of wherein:each of the pass transistor groups is coupled between local word lines and global word lines; andthe first pass transistor group electrically connects the local word lines to the global word lines.4. The address decoder of claim 3 , further comprising a row decoder configured to control the global word lines according to a row address.5. The address decoder of claim 1 , wherein:the pass transistor groups further include a second pass transistor group;the block select signal is defined by one data bit; andthe memory block selector delivers the enable signal to one of the first pass transistor group and the second pass ...

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Номер записи: 22
06-03-2014 дата публикации

Memory and memory system including the same

Номер: US20140063994A1
Автор: Choung-Ki Song
Принадлежит: SK hynix Inc

A memory includes first to N th word lines, first to M th redundancy word lines configured to replace M number of word lines among the first to N th word lines, and a control circuit configured to activate at least one adjacent word line adjacent to a K th redundancy word line (1≦K≦M) in response to an active signal, in the case where a word line corresponding to an inputted address among the first to N th word lines is replaced with the K th redundancy word line among the first to M th redundancy word lines in a first mode.

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Номер записи: 23
06-03-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20140064012A1
Автор: SHIN Wan Cheul
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes a block decoder configured to output block selection signals for selecting memory blocks in response to a row address signal, a first memory block including a first drain select line, a first source select line, and a first word line group including a plurality of first word lines disposed between the first drain select line and the first source select line, the first memory block disposed between the block decoder and a first switching group, the first switching group configured to transmit first operating voltages to the first memory block in response to a first block selection signal among the block selection signals, and a first block word line configured to transmit the first block selection signal to the first switching group and disposed over the first memory block to avoid overlapping with the first word line group. 1. A semiconductor memory device comprising:a block decoder configured to output block selection signals for selecting memory blocks in response to a row address signal;a first memory block including a first drain select line, a first source select line, and a first word line group including a plurality of first word lines disposed between the first drain select line and the first source select line, the first memory block disposed between the block decoder and a first switching group;the first switching group configured to trans first operating voltages to the first memory block in response to a first block selection signal among the block selection signals; anda first block word line configured to transmit the first block selection signal to the first switching group and disposed over the first memory block to avoid overlapping with the first word line group.2. The device of claim wherein the first block word line is disposed on an edge region of the first memory block.3. The device of claim 1 , wherein the first block word line is disposed between the first drain select line and the first cord line group. ...

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Номер записи: 24
06-03-2014 дата публикации

Data storage device and operating method thereof

Номер: US20140068150A1
Автор: Ho Jung YUN, Young Soo Park
Принадлежит: SK hynix Inc

A data storage device includes: a first memory device. a second memory device configured to share a write control signal and a read control signal which are provided to the first memory device. and a controller configured to control the first and second memory devices, wherein the controller provides the write control signal and the read control signal to the first and second memory devices at the same time, the first memory device receives only the read control signal according to a first mask signal, and the second memory device receives only the write control signal according to a second mask signal.

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Номер записи: 25
06-01-2022 дата публикации

Two-Bit Memory Cell and Circuit Structure Calculated in Memory Thereof

Номер: US20220005525A1
Автор: CONG Wei, Lim Seow Fong
Принадлежит:

The invention relates to a two-bit memory cell structure, and an array architecture and a circuit structure thereof in an in-memory computing chip. The double-bit storage unit comprises three transistors which are connected in series, a selection transistor in the middle is used as a switch, and two charge storage transistors are symmetrically arranged on the two sides of the double-bit storage unit. A storage array formed by the double-bit storage unit is used for storing the weight of the neural network, and multiplication and accumulation operation of the neural network is carried out in a two-step current detection mode. According to the invention, leakage current can be effectively controlled, higher weight storage density and higher reliability are realized, and neural network operation with more practical significance is further realized. 1. A circuit structure of a two-bit memory cell for in-memory computing , comprising:a memory cell array consisting of two-bit memory cell structures and used for storing a weight matrix of a neural network, and the two-bit memory cell comprises: three transistors connected in series, in which the middle transistor is a select transistor used as a switch, and a first charge storage transistor and a second charge storage transistor are symmetrically placed on two sides of the select transistor; the gate electrode of the select transistor is connected to a word line, the gate electrodes of the first charge storage transistor and the second charge storage transistor are connected to respective word lines, and the drain side of the first charge storage transistor and the source side of the second charge storage transistor are respectively connected to the cell bit line and the cell source line while the source side of the first charge storage transistor and the drain side of the second charge storage transistor are respectively connected to the drain side and the source side of the select transistor; wherein the first charge ...

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Номер записи: 26
01-01-2015 дата публикации

Three-Dimensional Memory Comprising Discrete Read/Write-Voltage Generator Die

Номер: US20150003160A1
Автор: Guobiao Zhang
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (V R /V W -generator) is located on a separate peripheral-circuit die. The V R /V W -generator generates at least a read and/or write voltage to the 3D-array die. A single V R /V W -generator die can support multiple 3D-array dies.

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Номер записи: 27
02-01-2020 дата публикации

High-Speed Memory Architecture

Номер: US20200005836A1
Автор: Bohra Fakhruddin Ali, Dasani Jitendra, Dwivedi Shri Sagar, Gupta Lalit, Nautiyal Vivek, Singla Gaurav Rattan
Принадлежит:

Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal. 1. An integrated circuit , comprising:memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays, wherein the first pair of bank arrays have a first number of rows, and wherein the second pair of bank arrays have a second number of rows that is different than the first number of rows; andbank multiplexer circuitry coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel, wherein the bank multiplexer circuitry provides an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.2. The integrated circuit of claim 1 , wherein the second number of rows has a sum of rows that is asymmetrically balanced with a sum of rows of the first number of rows.3. The integrated circuit of claim 2 , wherein the asymmetrical balancing of the second number of rows with respect to the first number of rows provides a resistive-capacitive (RC) balancing between the multiple banks of bitcell arrays.4. The integrated circuit of claim 1 , wherein the second number of rows is less than the first number of rows.5. ...

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Номер записи: 28
07-01-2021 дата публикации

NONVOLATILE MEMORY DEVICE

Номер: US20210005622A1
Автор: CHO Min Kuck, LEE SEUNG HOON
Принадлежит: KEY FOUNDRY CO., LTD.

A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer. 1. A nonvolatile memory device , comprising:a cell array formed on a substrate; anda control gate pickup structure, floating gates, and', 'a control gate surrounding the floating gates,, 'wherein the cell array comprises'} a floating gate polysilicon layer,', 'a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and', 'at least one contact plug formed on the control gate polysilicon layer., 'wherein the control gate pickup structure comprises'}2. The nonvolatile memory device of claim 1 , wherein the control gate pickup structure further comprises a dielectric film formed between the floating gate polysilicon layer and the control gate polysilicon layer.3. The nonvolatile memory device of claim 1 , wherein the floating gates each has a long axis and a short axis claim 1 , and a direction of the long axis has a shape tilted with respect to an X-axial direction.4. The nonvolatile memory device of claim 1 , wherein the cell array further comprises:a bit line;a word line;a source line;a bit line contact formed in a first active region of the substrate; anda source line contact formed in a second active region of the substrate, whereinthe word line is connected to the at least one contact plug formed on the control gate polysilicon layer.5. The nonvolatile memory device of claim 1 , wherein the cell array comprises odd rows and even rows claim 1 , and the floating gates in the odd rows and the floating gates in the even rows have ...

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Номер записи: 29
07-01-2021 дата публикации

Three-dimensional semiconductor memory device

Номер: US20210005629A1
Автор: Bongsoon LIM, Hongsoo Jeon, Sang-Wan Nam, Sang-Won Park, Sang-Won Shim, Yonghyuk Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

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Номер записи: 30
03-01-2019 дата публикации

NONVOLATILE MEMORY DEVICE PERFORMING PROGRAM OPERATION AND OPERATION METHOD THEREOF

Номер: US20190005995A1
Автор: Oh Jin Yong
Принадлежит:

A nonvolatile memory device includes: a plurality of word lines that are stacked; a vertical channel region suitable for forming a cell string along with the word lines; and a voltage supplier suitable for supplying a plurality of biases required for a program operation on the word lines, where a negative bias is applied to neighboring word lines disposed adjacent to a selected word line at an end of a pulsing section of a program voltage which is applied to the selected word line. 1. A nonvolatile memory device , comprising:a plurality of word lines that are stacked;a vertical channel region suitable for forming a cell string along with the word lines; anda voltage supplier suitable for supplying a plurality of biases required for a program operation on the word lines,wherein a negative bias is applied to neighboring word lines disposed adjacent to a selected word line at an end of a pulsing section of a program voltage which is applied to the selected word line.2. The nonvolatile memory device of claim 1 , wherein the negative bias is applied to a word line which is to be programmed subsequent to the selected word line among the neighboring word lines disposed adjacent to the selected word line.3. The nonvolatile memory device of claim 1 , wherein the negative bias is applied to a word line among the neighboring word lines disposed adjacent to the selected word line.4. The nonvolatile memory device of claim 2 , wherein all unselected word lines in the cell string are biased with a pass voltage claim 2 , before the negative bias is applied to the word line which is to be programmed subsequent to the selected word line.5. The nonvolatile memory device of claim 2 , wherein the selected word line is discharged after the negative bias is applied.6. The nonvolatile memory device of claim 5 , wherein the selected word line is discharged with a ground voltage level.7. The nonvolatile memory device of claim 4 , wherein all the word lines in the cell string including the ...

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Номер записи: 31
02-01-2020 дата публикации

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ALUMINUM-SILICON WORD LINES AND METHODS OF MANUFACTURING THE SAME

Номер: US20200006374A1
Автор: Higashitani Masaaki, PACHAMUTHU Jayavel, Rabkin Peter
Принадлежит:

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; andmemory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, and extends through each of the electrically conductive layers and is laterally surrounded by each of the electrically conductive layers,wherein each of the electrically conductive layers includes a respective metallic alloy material portion including aluminum and silicon, wherein at least 40% of all atoms within the metallic alloy material portion are aluminum atoms and at least 1% of all atoms within the metallic alloy material portions are silicon atoms.2. The three-dimensional memory device of claim 1 , wherein each of electrically conductive layers comprises a metallic barrier layer embedding a respective metallic alloy material portion and providing spatial separation of the metallic alloy material portion from the insulating layers and from the memory stack structures.3. The three-dimensional memory device of claim 2 , further comprising a backside blocking dielectric layer located between each neighboring ...

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Номер записи: 32
02-01-2020 дата публикации

WORD LINE WITH AIR-GAP FOR NON-VOLATILE MEMORIES

Номер: US20200006433A1
Автор: Doyle Brian, Karpov Elijah V., Majhi Prashant, Pillarisetty Ravi, Sharma Abhishek
Принадлежит: Intel Corporation

Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical. 1. An integrated circuit , comprising:a plurality of word lines (WLs), wherein said WLs are arranged in a stacked configuration with respect to one another;one or more air-gaps arranged between at least some of said WLs;a plurality of bit lines (BLs), wherein one or more said BLs intersects one or more said WLs; andan array of memory cells, at least some of the memory cells being addressable by corresponding ones of said WLs and BLs.2. The integrated circuit according to claim 1 , wherein the array of memory cells includes an RRAM (“Resistance Random Access Memory) memory configuration.3. The integrated circuit according to claim 1 , wherein the array of memory cells includes a FeFET (“Ferroelectric Field Effect Transistor”) memory configuration.4. The integrated circuit according to claim 1 , wherein said WLs are arranged parallel to an underlying wafer surface or substrate surface.5. The integrated circuit according to claim 1 , wherein said WLs are arranged perpendicular to an underlying wafer surface or substrate surface.6. The integrated circuit according to claim 1 , wherein each memory cell comprises a selector claim 1 , a metal electrode claim 1 , and an RRAM switching layer.7. The integrated circuit according to claim 6 , wherein said RRAM switching layer comprises oxygen and one or more of hafnium claim 6 , tantalum claim 6 , silicon claim 6 , and tungsten.8. The integrated circuit according to claim 1 , wherein said integrated circuit is a processor or a communication chip.9. The integrated circuit according to claim 1 , wherein said integrated circuit is part of a mobile computing device.10. An integrated circuit claim 1 , comprising:a first word line (WL) and a second WL;an air-gap between the first WL and second WL; a switching layer including an oxide material,', 'a selector layer, for ...

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Номер записи: 33
03-01-2019 дата публикации

Circuit with Impedance Elements Connected to Sources and Drains of PMOSFET Headers

Номер: US20190007043A1
Автор: Chen Andy Wangkun, Chen Hsin-Yu, Chong Yew Keong, Li Yicong, Thyagarajan Sriram
Принадлежит:

A method to generate a circuit instance to include a plurality of pMOSFET instances, where each pMOSFET instance has a source terminal instance connected to one or more supply rail instances. The circuit instance includes impedance element instances, where each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance. Depending upon a set of requirements, one or more of the impedance element instances are in a high impedance state or a low impedance state. 1. A method comprising:generating a circuit instance to include a plurality of pMOSFET instances, wherein each pMOSFET instance has a source terminal instance connected to one or more supply rail instances;generating the circuit instance to include impedance element instances, wherein each impedance element instance is connected to a source terminal instance and a drain terminal instance of a corresponding pMOSFET instance;depending upon a set of requirements, generating the circuit instance to indicate that one or more of the impedance element instances are in a high impedance state or a low impedance state; andfabricating one or more masks according to the generated circuit instance.2. The method as set forth in claim 1 , further comprising:generating the circuit instance to include a controller instance coupled to gate terminals of those pMOSFET instances for which their corresponding impedance element instances are in a high impedance state; andgenerating the circuit instance to indicate a LOW voltage on gate terminals of those pMOSFET instances for which their corresponding impedance element instances are in a low impedance state.3. The method as set forth in claim 2 , wherein the circuit instance includes a memory instance.4. The method as set forth in claim 3 , wherein the memory instance includes a word driver instance claim 3 , wherein connected to the word driver instance is at least one of the pMOSFET instances.5. The method ...

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Номер записи: 34
08-01-2015 дата публикации

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

Номер: US20150009774A1
Автор: KO Bok Rim
Принадлежит: SK HYNIX INC.

The semiconductor device includes an internal command generator and an internal address generator. The internal command generator generates first and second command latch signals from first and second internal clock signals in response to an external control signal and latches a command signal in response to the first and second command latch signals to generate a synthesized internal command signal. The internal address generator generates first and second address latch signals from the first and second internal clock signals in response to the external control signal and latches an address signal in response to the first and second address latch signals to generate a synthesized internal address signal. 1. A semiconductor device comprising:an internal command generator suitable for generating first and second command latch signals from first and second internal clock signals in response to an external control signal and suitable for latching a command signal in response to the first and second command latch signals to generate a synthesized internal command signal; andan internal address generator suitable for generating first and second address latch signals from the first and second internal clock signals in response to the external control signal and suitable for latching an address signal in response to the first and second address latch signals to generate a synthesized internal address signal.2. The semiconductor device of claim 1 , wherein the external control signal is a chip selection signal for selecting a chip including the semiconductor device.3. The semiconductor device of claim 1 , wherein the first command latch signal includes a pulse generated from the first internal clock signal in synchronization with a pulse of the external control signal.4. The semiconductor device of claim 3 , wherein the first address latch signal includes a pulse generated after the pulse of the first command latch signal is generated.5. The semiconductor device of claim 4 ...

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Номер записи: 35
27-01-2022 дата публикации

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

Номер: US20220028439A1
Автор: HUANG Chia-En, Liu Yi-Ching, Wang Yih
Принадлежит:

A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, a first bit line, a second bit line and a first source line. The first bit lines extends in a first direction, and is coupled to the first memory cell, the second memory cell and the first select transistor. The second bit line extends in the first direction, and is coupled to the first select transistor. The first source line extends in the first direction, is coupled to the first memory cell and the second memory cell, and is separated from the first bit line in a second direction different from the first direction. 1. A memory circuit , comprising:a first memory cell on a first layer;a second memory cell on a second layer different from the first layer;a first select transistor on a third layer different from the first layer and the second layer;a first bit line extending in a first direction, and being coupled to the first memory cell, the second memory cell and the first select transistor;a second bit line extending in the first direction, and being coupled to the first select transistor; anda first source line extending in the first direction, being coupled to the first memory cell and the second memory cell, and being separated from the first bit line in a second direction different from the first direction.2. The memory circuit of claim 1 , further comprising:a first select line extending in the second direction, and being coupled to the first select transistor;a first word line extending in the second direction, being separated from the first select line in the first direction, and being coupled to the first memory cell; anda second word line extending in the second direction, being separated from the first word line in the first direction, and being coupled to the first memory cell.3. The memory circuit of claim 2 , wherein the ...

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Номер записи: 36
14-01-2021 дата публикации

APPARATUSES AND METHODS FOR CONTROLLING WORD LINE DISCHARGE

Номер: US20210012819A1
Автор: Suzuki Takamasa
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for driving word driver lines in a gradual manner are disclosed herein. Word driver lines may be driven to intermediate potentials between high and low potentials. In some examples, the word driver lines may be driven in a step-wise manner. In some examples, the intermediate potential may be a bias voltage. The bias voltage may be provided by a bias voltage generator. One or more enable signals may be used to control the driving of the word driver line. In some examples, an address signal may be used to control the driving of the word driver line. Driving the word driver line in a gradual manner may cause a word line to discharge in a gradual manner in some examples. 1. An apparatus comprising:a subword driver configured to drive a subword line; anda word driver configured to provide a first driving signal and a second driving signal to the subword driver, wherein:the subword line is driven to a high potential responsive to an activation of the first driving signal and the second driving signal; andthe subword line is discharged to an intermediate subword line voltage responsive to deactivating the first driving signal.2. The apparatus of claim 1 , wherein a rate of discharge is based claim 1 , at least in part claim 1 , on a time difference between deactivating the first driving signal and driving the second driving signal to an intermediate potential.3. The apparatus of claim 1 , wherein the intermediate subword line voltage is based claim 1 , at least in part claim 1 , on a threshold voltage of a transistor of the subword line driver.4. The apparatus of claim 1 , wherein:the subword line is further discharged responsive to deactivating the first driving signal and driving the second driving signal to an intermediate potential; andthe subword line is fully discharged responsive to deactivating the first driving signal and the second driving signal.5. The apparatus of claim 4 , further comprising a bias voltage generator configured to ...

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Номер записи: 37
10-01-2019 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20190013357A1
Автор: Jeong Hee Park, Jong Uk Kim, Jung Moo Lee, Seong Geon PARK, Soon Oh PARK
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.

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Номер записи: 38
14-01-2021 дата публикации

METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME

Номер: US20210012840A1
Автор: CHO Ji-ho, NAM Sang-Wan, SHIM Won-bo
Принадлежит:

A nonvolatile memory device includes a memory cell region, a peripheral circuit region, a memory block in the memory cell region, a row decoder in the peripheral circuit region, and a control circuit in the peripheral circuit region. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes memory cells stacked in a direction intersecting a substrate, and is divided into a plurality of sub-blocks configured to be erased independently. The row decoder selects the memory block by units of a sub-block. The control circuit receives a data erase command for a selected sub-block among the plurality of sub-blocks, performs a data read operation on at least one victim sub-block among the plurality of sub-blocks in response to the data erase command, selectively performs a soft program operation on the at least one victim sub-block based on a result of the data read operation, and performs a data erase operation on the selected sub-block after the data read operation is performed and the soft program operation is selectively performed. 1. A nonvolatile memory device comprising:a memory cell region including a first metal pad;a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;a memory block in the memory cell region including memory cells stacked in a direction intersecting a substrate, the memory block being divided into a plurality of sub-blocks configured to be erased independently;a row decoder in the peripheral circuit region configured to select the memory block by units of a sub-block; anda control circuit in the peripheral circuit region configured to receive a data erase command for a selected sub-block among the plurality of sub-blocks, to perform a data read operation on at least one ...

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Номер записи: 39
14-01-2021 дата публикации

LAYOUT STRUCTURE OF MEMORY ARRAY

Номер: US20210012846A1
Автор: Chang Meng-Sheng, CHOU Shao-Yu, Wang Yih, YANG Yao-Jen
Принадлежит:

A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line. 1. A layout method , comprising:forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells;disposing a word line between the first row and the second row;disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively;disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes located on a first side of the word line; anddisposing a second cut layer on a second portion of a second control electrode of the plurality of control electrodes located on a second side of the word line;wherein the first side of the word line is opposite to the second side of the word line.2. The layout method of claim 1 , wherein the first cut layer is located between a first storage cell of the first row and the first side of the word line claim 1 , the first control electrode is coupled to the first storage cell claim 1 , the second cut layer is located between a second storage cell of ...

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Номер записи: 40
15-01-2015 дата публикации

Memory architectures having dense layouts

Номер: US20150016180A1
Автор: Chun-Yao Ko, Felix Ying-Kit Tsui, Hau-yan Lu, Shih-Hsien Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate.

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Номер записи: 41
21-01-2016 дата публикации

MEMORY DEVICE

Номер: US20160019940A1
Автор: JANG Soo-Young, Lee Hyun-woo
Принадлежит:

A memory device includes a plurality of normal word lines arranged at a first distance from each other, a redundant word line arranged at a second distance, which is greater than the first distance from a normal word line adjacent to the redundant word line, among the normal word lines, and a word line control unit suitable for selectively activating the normal word lines, and replacing a frequently activated word line with the redundant word line when the frequently activated word line is detected.

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Номер записи: 42
03-02-2022 дата публикации

Memory Array Staircase Structure

Номер: US20220036931A1
Автор: Chia Han-Jong, LIN Chung-Te, Lin Meng-Han, Lin Yu-Ming, Wang Sheng-Chen, Yang Feng-Cheng
Принадлежит:

Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length second edge of the memory array; a memory film contacting a first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line. 1. A memory array comprising:a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array, the second edge of the memory array being perpendicular to the first edge of the memory array;a second word line extending from a third edge of the memory array, the third edge of the memory array being opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length second edge of the memory array;a memory film contacting a first word line; andan oxide semiconductor (OS) layer contacting a first source line and a first bit line, wherein the memory film is disposed between the OS layer and the first word line.2. The memory array of claim 1 , wherein the memory film comprises a ferroelectric (FE) material.3. The memory array of claim 1 , further comprising:an inter-metal dielectric (IMD) over the first word line;a first contact extending through the IMD to the first word line, wherein the first contact is electrically coupled to the first word line;a dielectric material ...

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Номер записи: 43
03-02-2022 дата публикации

THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME

Номер: US20220037354A1
Автор: SUN Zhongwang, XIA Zhiliang, Zhang Zhi, Zhang Zhong, ZHOU Wenxi
Принадлежит: Yangtze Memory Technologies Co., Ltd.

In a method for fabricating a semiconductor device, an initial stack of alternatingly sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. A connection region, a first staircase region, and a second staircase region are patterned in the initial stack. The first staircase region is shaped in the initial stack to form a first staircase, and the second staircase region is shaped in the initial stack to form a second staircase. The first staircase is formed in a first block of the initial stack and extends between first array regions of the first block. The second staircase is formed in a second block of the initial stack and extends between second array regions of the second block. The connection region is formed in the initial stack between the first staircase and the second staircase. 1. A method for fabricating a semiconductor device , comprising:forming an initial stack of sacrificial word line layers and insulating layers that are alternatingly disposed over a substrate of the semiconductor device;patterning a connection region, a first staircase region, and a second staircase region in the initial stack;shaping the first staircase region in the initial stack to form a first staircase; and the first staircase is formed in a first block of the initial stack and extends between first array regions of the first block,', 'the second staircase is formed in a second block of the initial stack and extends between second array regions of the second block, and', 'the connection region is formed in the initial stack between the first staircase and the second staircase., 'shaping the second staircase region in the initial stack to form a second staircase, wherein'}2. The method of claim 1 , wherein the shaping the first staircase region and the second staircase region further comprises:shaping the sacrificial word line layers and the insulating layers in the first staircase region to form a first stair extending in a ...

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Номер записи: 44
21-01-2021 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20210020655A1
Автор: NAKATSUKA Keisuke, YOSHIMURA Naoya
Принадлежит: Kioxia Corporation

A semiconductor memory device according to an embodiment includes a substrate, first to eleventh conductive layers, first and second pillars, and first to fourth insulating regions. The first insulating regions are provided between the third and fifth conductive layers and between the fourth and sixth conductive layers. The second insulating regions are provided between the eighth and tenth conductive layers and between the ninth and eleventh conductive layers. The third insulating region is provided between the third to sixth conductive layers and the eighth to eleventh conductive layers. The fourth insulating region is provided between the second and seventh conductive layers. The fourth insulating region is separated from the third insulating region in a planar view. 1. A semiconductor memory device comprising:a substrate;a first conductive layer provided above the substrate;a second conductive layer provided above the first conductive layer;a third conductive layer and a fourth conductive layer provided above the second conductive layer, the third conductive layer and the fourth conductive layer being separated from each other in a first direction;a fifth conductive layer provided in the same level of a layered structure as the third conductive layer above the second conductive layer, the fifth conductive layer being separated from the third conductive layer;a sixth conductive layer provided in the same level of the layered structure as the fourth conductive layer above the second conductive layer, the sixth conductive layer being separated from the fourth conductive layer;a plurality of first insulating regions provided between the third conductive layer and the fifth conductive layer and between the fourth conductive layer and the sixth conductive layer, along a second direction intersecting the first direction;a first pillar provided between the first insulating regions and penetrating the second conductive layer along the first direction, the first pillar ...

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Номер записи: 45
26-01-2017 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

Номер: US20170025162A1
Автор: JUNG Hun-Sam, Kim Chang-Hyun, Kim Min-Chang, LEE Do-Yun, Lee Jae-Jin
Принадлежит:

A semiconductor memory device includes a plurality of memory cells coupled to multiple word lines a word line deactivation voltage generation block suitable for generating word line deactivation voltages having different voltage levels corresponding to temperature ranges, and a word line driving block suitable for driving a word line to be deactivated with the word line deactivation voltages selected from the word line deactivation voltages. 1. A semiconductor memory device , comprising:a plurality of memory cells coupled to multiple word lines;an off voltage generation block suitable for generating word line deactivation voltages having different voltage levels corresponding to a plurality of temperatures;a word line driving block suitable for driving a word line to be deactivated with a word line deactivation voltage selected from the word line deactivation voltages; anda temperature detection block suitable for generating a plurality of detection signals corresponding to the plurality of temperatures and supplying the detection signals to the off voltage generation block, a plurality of voltage generation units suitable for generating a plurality of internal voltages; and', 'a multiplexing unit suitable for outputting one of the internal voltages as the word line deactivation voltage in response to the detection signal., 'wherein the off voltage generation block includes2. (canceled)3. The semiconductor memory device of claim 1 , wherein the word line deactivation voltages correspond to the plurality of the detection signals.4. The semiconductor memory device of claim 1 , further comprising:an active voltage generation block suitable for generating an active voltage for activating a word line and supplying the active voltage to the word line driving block.5. The semiconductor memory device of claim 1 , wherein the voltage level of the word line deactivation voltage gets lower as a temperature gets higher.610-. (canceled)11. The semiconductor memory device of ...

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Номер записи: 46
25-01-2018 дата публикации

SEMICONDUCTOR DEVICE INCLUDING A COLUMN DECODER

Номер: US20180025762A1
Автор: CHUN Duk Su
Принадлежит: SK HYNIX INC.

A semiconductor device may be provided. The semiconductor device may include a first power line located in a memory cell array region. The semiconductor device may include a second power line located in a column decoder region. The semiconductor device may include a third power line formed in a layer different from the first power line and the second power line, configured to couple the first power line to the second power line. The semiconductor device may include a metal-oxide-semiconductor (MOS) capacitor located below the third power line. 1. A semiconductor device comprising:a first power line located in a memory cell array region, and extended in a first direction;a second power line located in a column decoder region, and extended in a second direction crossing the first direction;a third power line formed in a layer different from the first power line and the second power line, configured to couple the first power line to the second power line; anda metal-oxide-semiconductor (MOS) capacitor located below the third power line.2. The semiconductor device according to claim 1 , wherein the third power line is located below the first power line and the second power line.3. The semiconductor device according to claim 1 , further comprising:a plurality of signal lines located in the memory cell array region, and arranged in an array in conjunction with the first power line.4. The semiconductor device according to claim 3 , wherein each of the plurality of signal lines extend in the first direction.5. The semiconductor device according to claim 3 , wherein two or more signal lines are located between each of the first power lines.6. The semiconductor device according to claim 3 , wherein the plurality of signal lines are located a layer formed over the memory cell array region claim 3 , and the first power line are located at the same layer as the plurality of signal lines.7. The semiconductor device according to claim 3 , wherein the plurality of signal lines ...

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Номер записи: 47
10-02-2022 дата публикации

READ BROADCAST OPERATIONS ASSOCIATED WITH A MEMORY DEVICE

Номер: US20220044713A1
Автор: Jain Shanky Kumar, Yudanov Dmitri A.
Принадлежит:

Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable read broadcast operations. A read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers. 1. A method , comprising:identifying a pattern of logic states stored in a second component of a memory device;coupling a plurality of access lines with a selection component, wherein the plurality of access lines are coupled with the second component;capturing the pattern of logic states at the selection component based at least in part on coupling the plurality of access lines with the selection component;coupling the selection component with a plurality of locations of a first component of the memory device based at least in part on capturing the pattern of logic states; andstoring, at the plurality of locations of the first component and based at least in part on coupling the selection component with the plurality of locations of the first component, a pattern of signal states associated with the pattern of logic states.2. The method of claim 1 , further comprising:activating a first set of word lines associated with the first component;applying a first signal to a set of signal lines coupled with the first component after activating the first set of word lines, wherein the first signal corresponds to a first logic state;activating a second set of word lines associated with the first component based at least in part on applying the first signal;applying a second signal to the set of ...

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Номер записи: 48
10-02-2022 дата публикации

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A COMPOSITE SEMICONDUCTOR CHANNEL AND A HORIZONTAL SOURCE CONTACT LAYER AND METHOD OF MAKING THE SAME

Номер: US20220045090A1
Автор: CUI Zhixin, SHIMIZU Satoshi, Zhang Yanli
Принадлежит:

A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;a source contact layer located between the substrate and the alternating stack;a memory opening vertically extending through the alternating stack and the source contact layer; anda memory opening fill structure located within the memory opening and comprising a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel, wherein the composite semiconductor channel comprises:a pedestal channel portion having a cylindrical sidewall segment that contacts the source contact layer and including at least one of carbon or arsenic dopant atoms at a first average dopant concentration; anda vertical semiconductor channel contacting a top surface of the pedestal channel portion, wherein the vertical semiconductor channel includes the at least one of carbon or arsenic ...

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Номер записи: 49
10-02-2022 дата публикации

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A COMPOSITE SEMICONDUCTOR CHANNEL AND A HORIZONTAL SOURCE CONTACT LAYER AND METHOD OF MAKING THE SAME

Номер: US20220045092A1
Автор: CUI Zhixin, SHIMIZU Satoshi, Zhang Yanli
Принадлежит:

A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers comprise source-select-level electrically conductive layers and word-line-level electrically conductive layers overlying the source-select-level electrically conductive layers;a source contact layer located between the substrate and the alternating stack;a memory opening vertically extending through the alternating stack and the source contact layer with a width-modulated vertical cross-sectional profile that has a first width at and below levels of the source-select-level electrically conductive layers, and has a second width that is greater than the first width at levels of a first subset of the word-line-level electrically conductive layers; anda memory opening fill structure located within the memory opening and comprising a composite semiconductor channel and ...

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Номер записи: 50
10-02-2022 дата публикации

SEMICONDUCTOR MEMORY DEVICES

Номер: US20220045094A1
Автор: HONG Jaeho, KIM Hyuncheol, Kim Yongseok, LEE Kyunghwan, SEO Hyeoungwon, YOO Sungwon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor memory device includes a word line extending in a vertical direction on a substrate, a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width, a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction, and a cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer. 1. A semiconductor memory device comprising:a word line extending in a vertical direction on a substrate;a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width;a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction; anda cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer.2. The semiconductor memory device of claim 1 , wherein an inner surface of the lower electrode layer comprises an electrode hole extending along a perimeter of the upper electrode layer and having a concave shape.3. The semiconductor memory device of claim 1 , wherein the lower electrode layer comprises a vertical cross-sectional surface having a U-shape rotated by 90 degrees.4. The semiconductor memory device of claim ...

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Номер записи: 51
29-01-2015 дата публикации

APPARATUSES AND METHODS FOR ADJUSTING DEACTIVATION VOLTAGES

Номер: US20150029804A1
Автор: Bollu Vikram K., Gossi Jonathan L., Kirsch Howard C., Merritt Todd A., Xia Zhong-yi
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for adjusting deactivation voltages are described herein. An example apparatus may include a voltage control circuit. The voltage control circuit may be configured to receive an address and to adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address. In some examples, the first voltage may be lower than the second voltage. 1. An apparatus , comprising:a voltage control circuit configured to receive an address and adjust a deactivation voltage of an access line associated with a target group of memory cells from a first voltage to a second voltage based, at least in part, on the address,wherein the first voltage is a lower voltage than the second voltage.2. The apparatus of claim 1 , wherein the voltage control circuit is further configured to provide a deactivation voltage to an access line physically adjacent the access line associated with the target group of memory cells at the second voltage for at least a portion of an access of the target group of memory cells.3. The apparatus of claim 1 , wherein the voltage control circuit is further configured to adjust the deactivation voltage of the access line associated with the target group of memory cells from the second voltage to the first voltage a period of time after adjusting the deactivation voltage of the access line associated with the target group of memory cells from the first voltage to the second voltage.4. The apparatus of claim 1 , wherein the voltage control circuit is further configured to provide the second voltage to a bus while the access line associated with the target group of memory cells is activated.5. The apparatus of claim 1 , wherein the access line associated with the target group of memory cells claim 1 , a first access line physically adjacent the access line associated with the target group of memory cells claim 1 , and a second access line ...

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Номер записи: 52
23-01-2020 дата публикации

NON-VOLATILE MEMORY CELL, ARRAY AND FABRICATION METHOD

Номер: US20200027492A1
Автор: CHERN GEENG-CHUAN
Принадлежит: NEXCHIP SEMICONDUCTOR CO., LTD

The present invention provides a non-volatile memory cell, array and fabrication method. The memory cell comprises a substrate, a gate structure, a source region and a drain region, wherein the gate structure is formed on the substrate, the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top, the source region is formed in the substrate, the source region comprises an N-type heavily doped source region, the drain region is formed in the substrate, the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region. The non-volatile memory cell and array provided by the present invention have a band-to-band tunneling programming ability and reserve the advantage of high reading current of an N-channel at the same time. 1. A non-volatile memory cell , characterized in that the non-volatile memory cell comprises:a substrate;a gate structure formed on the substrate, wherein the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top;a source region formed in the substrate, wherein the source region comprises an N-type heavily doped source region; anda drain region formed in the substrate, wherein the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region, wherein the source region and the drain region are respectively located at two ends of the gate structure, and the N-type doped drain region and the P-type heavily doped drain region both horizontally extend to positions below the gate structure and partially overlap with the gate structure.2. The non-volatile memory cell according to claim 1 , characterized in that the source region further comprises an N-type lightly doped source region ...

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Номер записи: 53
23-01-2020 дата публикации

STACKED MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF OPERATING STACKED MEMORY DEVICES

Номер: US20200027521A1
Автор: Choi Ahn
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A stacked memory device includes a buffer die, a plurality of memory dies stacked on the buffer die and a plurality of through silicon vias (TSVs). The buffer die communicates with an external device. The TSVs extend through the plurality of memory dies to connect to the buffer die. Each of memory dies includes a memory cell array which includes a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The buffer die includes a test circuit, and the test circuit, in a test mode, performs a test on the dynamic memory cells of a target memory die corresponding to one of the memory dies and store, an address of a memory cell row including at least one defective cell, in at least one column decoder of other memory dies of except the target memory die. 1. A stacked memory device comprising:a buffer die configured to communicate with at least one external device, the buffer die including a test circuit;a plurality of memory dies stacked on the buffer die, each of the plurality of memory dies including a memory cell array, the memory cell array including a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines;a plurality of through silicon vias (TSVs) extending through the plurality of memory dies and connected to the buffer die; and perform a test on the dynamic memory cells of a target memory die corresponding to at least one of the plurality of memory dies, the test to detect at least one defective cell of the target memory die, and', 'store, as fail address information, an address of a memory cell row including the at least one defective cell detected through the test, in at least one column decoder of another memory die of the plurality of memory dies, the another memory die not being the target memory die., 'the test circuit, during a test mode of the stacked memory device, is configured to,'}2. The stacked memory device of claim 1 , wherein each of the plurality of memory dies ...

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Номер записи: 54
28-01-2021 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20210028109A1
Автор: Cho Uk Rae, Choi Kyu Won, Jung Woo Jin, Lee Chan Ho, Youn Suk
Принадлежит:

A semiconductor device includes a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent the first and second cell regions in a second direction, a bit line in a first metal level on the substrate and extending in the first direction, and a first ground rail in a second metal level different from the first metal level. The first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region, a second sub-ground rail extending in the second direction on the second cell region, a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, and a fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction. 1. A semiconductor device comprising:a substrate comprising a first cell region, a second cell region that is adjacent the first cell region in a first direction, and a comparison region that is adjacent the first and second cell regions in a second direction different from the first direction;a bit line in a first metal level on the substrate, the bit line extending in the first direction; anda first ground rail in a second metal level different from the first metal level,wherein the first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region,a second sub-ground rail extending in the second direction on the second cell region,a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, anda fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction.2. The semiconductor device of claim 1 , wherein the third sub-ground rail extends in the first direction.3. The semiconductor device of claim 1 , wherein the third sub-ground rail comprises:a first portion ...

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Номер записи: 55
04-02-2016 дата публикации

Discrete Three-Dimensional Memory

Номер: US20160035394A1
Автор: Guobiao Zhang
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

The present invention discloses a discrete three-dimensional memory (3D-M). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an off-die peripheral-circuit component of the 3D-M arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

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Номер записи: 56
04-02-2016 дата публикации

Discrete Three-Dimensional Vertical Memory

Номер: US20160035395A1
Автор: Guobiao Zhang
Принадлежит: CHENGDU HAICUN IP TECHNOLOGY LLC

The present invention discloses a discrete three-dimensional vertical memory (3D-M V ). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. At least an off-die peripheral-circuit component of the 3D-M V arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

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Номер записи: 57
01-02-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180033473A1
Автор: CHI Sung Soo, LEE Sung Yub
Принадлежит: SK HYNIX INC.

A semiconductor device may be provided. The semiconductor device may include a driving voltage supply unit configured to supply a voltage such that a main word line signal has the voltage. The semiconductor device may include a current path control unit configured to increase the speed at which the voltage of the main word line signal decreases. 1. A semiconductor device comprising:a driving voltage supply unit configured to selectively supply a first or second voltage based on a driving voltage select signal, such that a main word line signal has the voltage level of the first voltage or the second voltage lower than the first voltage; anda current path control unit configured to provide a path of a current for increasing the speed at which the voltage level of the main word line signal decreases from the level of the first voltage to the level of the second voltage, based on a current path control signal.2. The semiconductor device of claim 1 , further comprising a main word line signal generation unit configured to selectively drive the main word line signal based on a main word line driving signal claim 1 ,wherein the driving voltage supply unit supplies the first or second voltage as a driving voltage of the main word line signal generation unit.3. The semiconductor device of claim 1 , wherein the current path control signal is activated for a predetermined time from a point of time that the driving voltage select signal is activated.4. The semiconductor device of claim 1 , wherein the current path control unit comprises a MOS transistor which is controlled according to the current path control signal.5. The semiconductor device of claim 4 ,wherein the MOS transistor comprises an NMOS transistor,wherein the current path control signal is generated by performing an XOR operation on the driving voltage select signal and a signal obtained by delaying the driving voltage select signal by a predetermined time.6. The semiconductor device of claim 5 , wherein the ...

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Номер записи: 58
17-02-2022 дата публикации

Three-Dimensional Memory Device and Method

Номер: US20220052060A1
Автор: Chia Han-Jong, Lin Yu-Ming, Wang Sheng-Chen, Yeong Sai-Hooi, Young Bo-Feng
Принадлежит:

In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer. 1. A device comprising:a first dielectric layer having a first sidewall;a second dielectric layer having a second sidewall;a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall;a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; anda semiconductor layer extending along the memory layer.2. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall claim 1 , the connecting surface and the inner sidewall forming a right angle.3. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall claim 1 , the connecting surface and the inner sidewall forming an obtuse angle.4. The device of claim 1 , wherein the word line has a connecting surface extending between the outer sidewall and the inner sidewall claim 1 , the connecting surface and the inner sidewall forming a sharp corner.5. The device of claim 1 , wherein the word line has a connecting surface ...

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Номер записи: 59
31-01-2019 дата публикации

METHOD FOR ACCESSING HETEROGENEOUS MEMORIES AND MEMORY MODULE INCLUDING HETEROGENEOUS MEMORIES

Номер: US20190034344A1
Автор: Lim Sun-Young
Принадлежит:

A method of accessing volatile memory devices, nonvolatile memory devices, and a controller controlling the volatile memory devices and the nonvolatile memory devices is provided. The method includes receiving, by the controller, a row address associated with the volatile memory devices and the nonvolatile memory devices through first lines at a first timing, receiving, by the controller, an extended address associated with the nonvolatile memory devices through second lines at a second timing, and receiving, by the controller, a column address associated with the nonvolatile memory devices and the volatile memory devices through third lines at a third timing. 1. An apparatus comprising:a memory device; anda controller connected to the memory device,wherein the controller is configured to perform operations on the memory device based on commands received from a host according to a protocol,wherein the protocol includes timings of the operations which is not deterministic,wherein the controller sends a ready signal in response to receiving a first command from the host, andwherein the controller receives a signal requesting data output from the host after sending the ready message.2. The apparatus of claim 1 , wherein the controller receives a second command before sending the ready signal and sends the ready signal when data associated with the second command is ready in response to the second command claim 1 , andwherein the controller sends the data to the host in response to the signal.3. The apparatus of claim 2 , wherein the second command includes a read command and an extended address command.4. The apparatus of claim 1 , wherein the memory device and the controller configure a non-volatile dual in-line memory module (NVDIMM) device.5. The apparatus of claim 1 , wherein the protocol provides the host direct access to the memory device.6. A method comprising:receiving, by a memory device, a first command from a host;sending, by the memory device, a ready ...

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Номер записи: 60
30-01-2020 дата публикации

Word-Line Driver and Method of Operating a Word-Line Driver

Номер: US20200035288A1
Автор: Ali Taghvaei, Atul Katoch
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.

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Номер записи: 61
04-02-2021 дата публикации

SEMICONDUCTOR DEVICES AND METHODS OF OPERATING THE SAME

Номер: US20210036011A1
Автор: HAN Jeehoon, KANG SEOGOO, SON YOUNGHWAN
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure. 1. A semiconductor device comprising: a body gate layer extending in the first direction;', 'a charge storage structure surrounding a sidewall of the body gate layer; and', 'a channel layer surrounding a sidewall of the charge storage structure;', 'a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and', 'a gate insulating layer between each of the plurality of gate electrodes and the channel structure., 'a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure comprising'}2. The semiconductor device of claim 1 , whereinthe charge storage structure is between the body gate layer and the channel layer, andthe charge storage structure is in contact with an inner wall of the channel layer.3. The semiconductor device of claim 1 , whereinthe channel layer is on an inner wall of a channel hole penetrating the plurality of gate electrodes and extending in the first direction,the charge storage structure is conformally along the inner wall of the channel hole on the channel layer, andthe body gate layer fills in the channel hole on the charge storage structure.4. The semiconductor device of claim 1 , wherein the charge storage ...

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Номер записи: 62
24-02-2022 дата публикации

Memory controller and method of operating the same

Номер: US20220057953A1
Автор: Ji Hoon Lee
Принадлежит: SK hynix Inc

A memory controller includes a meta data memory configured to store mapping information of data stored in a plurality of memory blocks included in a memory device and valid data information indicating whether the data stored in the plurality of memory blocks is valid data, and a migration controller configured to control the memory device to perform a migration operation of moving a plurality of valid data stored in a source memory block among the plurality of memory blocks from the source memory block to a target memory block based on the mapping information and the valid data information.

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Номер записи: 63
24-02-2022 дата публикации

Adaptive buffer partitioning

Номер: US20220057958A1
Автор: Federica Cresci, Massimiliano Patriarca, Massimiliano Turconi, Nicola Del Gatto
Принадлежит: Micron Technology Inc

Methods, systems, and devices for adaptive buffer partitioning are described. A memory system may include a buffer for storing data (e.g., associated with a read command or a write command received from a host system). For example, the buffer may buffer data associated with a write command prior to storing the data at a memory device of the memory system. In another example, the buffer may buffer data associated with a read command prior to transmitting the data to the host system. In some cases, the buffer may include a first portion configured to store data associated with one or more read commands, a second portion configured to store data associated with one or more write commands, and a third portion configured to store data associated with one or more read commands or one or more write commands.

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Номер записи: 64
24-02-2022 дата публикации

SELECTION GATE SEPARATION FOR 3D NAND

Номер: US20220059555A1
Автор: KANG Chang Seok, Kitajima Tomohiko
Принадлежит: APPLIED MATERIAL, INC.

Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating non-replacement word lines and replacement insulators. A filled slit extends through the memory stack, and there are at least two select gate for drain (SGD) isolation regions in the memory stack adjacent the filled slit. A select-gate-for-drain (SGD) cut is patterned into the top few pairs of alternating layers in the memory stacks. Through the cut opening, the sacrificial layer of the memory stacks is removed, and an insulator layer is used to fill the opening. 1. A semiconductor memory device comprising:a memory string including at least one select-gate-for-drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate, the memory stack comprising alternating non-replacement word line and replacement insulator;a filled slit extending through the memory stack; andat least two select gate for drain (SGD) isolation regions in the memory stack adjacent the filled slit.2. The semiconductor memory device of claim 1 , wherein the non-replacement word line comprises one or more of tungsten (W) claim 1 , molybdenum (Mo) claim 1 , tantalum (Ta) claim 1 , ruthenium (Ru) claim 1 , niobium (Nb) claim 1 , osmium (Os) claim 1 , zirconium (Zr) claim 1 , iridium (Ir) claim 1 , rhenium (Re) claim 1 , titanium (Ti) claim 1 , silicon (Si) claim 1 , silicon germanium (SiGe) claim 1 , and germanium (Ge).3. The semiconductor memory device of claim 1 , wherein the non-replacement word line comprises one or more of a metal claim 1 , a metal nitride claim 1 , a conductive metal compound claim 1 , and a semiconductor material.4. The semiconductor memory device of claim 3 , wherein the metal is selected from one or more of tungsten (W) claim 3 , molybdenum (Mo) claim 3 , tantalum (Ta) claim 3 , ...

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Номер записи: 65
24-02-2022 дата публикации

Semiconductor storage device

Номер: US20220059617A1
Автор: Yusuke NIKI
Принадлежит: Kioxia Corp

A memory includes first signal-lines divided into groups. Global signal lines correspond to the first signal-lines. The global signal-lines include a selected global signal-line and a non-selected global signal-line. First transistors correspond to the first signal-lines. The first transistors are connected between a corresponding first signal-line and any of the global signal-lines. Selection signal-lines correspond to the groups. The selection signal-lines are connected to gate electrodes of the first transistors included in a corresponding group. Second transistors are connected between the first signal-lines that belong to adjacent two of the groups. When one of the first signal-lines which is electrically connected to the selected global signal-line is a selected first signal-line, the first transistors corresponding to one of the groups which includes the selected first signal-line is in a conducting state. One of the second transistors which is connected to the selected first signal-line is in a non-conducting state.

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Номер записи: 66
07-02-2019 дата публикации

METAL-NITRIDE-FREE VIA IN STACKED MEMORY

Номер: US20190043807A1
Автор: Bohra Mihir, ECONOMY D. Ross, Redaelli Andrea
Принадлежит:

A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via. 1. An apparatus comprising:a memory stack structure including multiple memory cells, the memory stack structure including a crosspoint architecture;a via in parallel with the memory stack structure to provide a current path to select at least one of the memory cells;a metal layer to couple to the via and to a top electrode of the memory stack structure; anda metal silicon nitride layer to couple the metal layer to the top electrode, wherein the metal silicon nitride layer to be part of the memory stack structure, to be between individual pillars of the crosspoint architecture and the metal layer, and not be between the metal layer and the via.2. The apparatus of claim 1 , wherein the via is to provide a current path to a bitline.3. The apparatus of claim 1 , wherein the via is to provide a current path to a wordline.4. The apparatus of claim 1 , wherein the metal layer comprises tungsten (W) and the metal silicon nitride layer comprises tungsten silicon nitride (WSiN).5. The apparatus of claim 4 , further comprising a layer of tungsten silicide (WSix) as a seed layer for the tungsten metal layer.6. The apparatus of claim 1 , wherein the memory stack structure further comprises a layer of carbon as the top electrode.7. The apparatus of claim 1 , wherein the crosspoint architecture comprises a three dimensional (3D) crosspoint (3DXP) nonvolatile memory architecture.8. A system comprising:a ...

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Номер записи: 67
07-02-2019 дата публикации

Wordline bridge in a 3d memory array

Номер: US20190043874A1
Автор: David S. Meyaard, Deepak Thimmegowda, Khaled Hasnat, Owen W. Jungroth
Принадлежит: Intel Corp

The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.

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Номер записи: 68
19-02-2015 дата публикации

MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, OPERATING METHOD THEREOF

Номер: US20150049570A1
Автор: CHOI Hyo-Jin, KANG Dong-Soo, KIM Sua, LEE Sung-Hyun, YOO Jun-Hee, YOUN Jae-youn, YU Hak-soo
Принадлежит:

In one embodiment, the memory device includes at least one memory bank including first and second subbanks, and control logic configured to control storing data into the memory bank. The control logic is configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank. 1. A memory device , comprising:at least one memory bank including first and second subbanks; anda control logic configured to control storing data into the memory bank, the control logic configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank.2. The memory device of claim 1 , wherein the control logic is configured to active the first subbank and not precharge the second subbank in response to a second activate command for the first subbank.3. The memory device of claim 1 , wherein the control logic is configured to control a sense amplifier to precharge the second subbank.4. The memory deivce of claim 3 , wherein the sense amplifier is configured to precharge the second subbank in response to a PRE command.5. The memory device of claim 4 , wherein the sense amplifier is configured to precharge the second subbank in response to an ACT command for activating the first subbank.6. The memory device of claim 5 , wherein the ACT command is one of a first ACT command and a second ACT command claim 5 , and the sense amplifier precharges the second subbank in response to the first ACT command and does not precharge the second subbank in response to the second ACT command.7. The memory device of claim 5 , wherein when the second subbank is in the active status claim 5 , the sense amplifier is configured to precharge the second subbank in response to the ACT command for activating the first subbank; andwhen the second subbank is in a deactive status, the sense amplifier is configured to not precharge the second subbank in response to the ACT command for ...

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Номер записи: 69
18-02-2021 дата публикации

Semiconductor memory apparatus for preventing disturbance

Номер: US20210050058A1
Автор: Jin Su Park
Принадлежит: SK hynix Inc

A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.

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Номер записи: 70
26-02-2015 дата публикации

Semiconductor Device

Номер: US20150055394A1
Автор: Migaku Kobayashi, Shinya Iwasa
Принадлежит: Micron Technology Inc

A semiconductor device comprises a semiconductor substrate including first and second regions that have different conductivity types from each other; an isolation region extending continuously over the first and second regions and having a shallow trench covered by a field insulator; first and second active regions placed in respective first and second regions and being each surrounded by the isolation region; a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate groove being shallower than the shallow trench; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series.

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Номер записи: 71
26-02-2015 дата публикации

NONVOLATILE MEMORY DEVICE AND RELATED WORDLINE DRIVING METHOD

Номер: US20150055430A1
Автор: JINYUB LEE, KIM SU-YONG, SEUNGJAE LEE
Принадлежит:

A nonvolatile memory device comprises multiple memory blocks each comprising multiple memory cells arranged at intersections of wordlines and bitlines, an address decoder configured to electrically connect first lines to wordlines of one of the memory blocks in response to an address, a line selection switch circuit configured to electrically connect the first lines to second lines in different configurations according to the address, a first line decoder configured to provide the second lines with wordline voltages needed for driving, and a voltage generator configured to generate the wordline voltages. 1. A nonvolatile memory device , comprising:multiple memory blocks each comprising multiple memory cells arranged at intersections of wordlines and bitlines;an address decoder configured to electrically connect first lines to wordlines of one of the memory blocks in response to an address;a line selection switch circuit configured to electrically connect the first lines to second lines in different configurations according to the address;a first line decoder configured to provide the second lines with wordline voltages needed for driving; anda voltage generator configured to generate the wordline voltages.2. The nonvolatile memory device of claim 1 , wherein the memory blocks share the bitlines and at least two of the memory blocks share a common source line.3. The nonvolatile memory device of claim 1 , wherein the address decoder comprises multiple block selection transistors for connecting one of the first lines and one of the wordlines claim 1 , and at least two of the block selection transistors share a source region connected to one of the first lines.4. The nonvolatile memory device of claim 3 , wherein the at least two block selection transistors comprise a first block selection transistor and a second block selection transistor claim 3 ,wherein the first block selection transistor has a gate region connected to a first block selection wordline, a drain ...

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Номер записи: 72
03-03-2022 дата публикации

Channel formation for vertical three dimensional (3d) memory

Номер: US20220068927A1
Автор: Haitao Liu, Kamal M. Karda
Принадлежит: Micron Technology Inc

Systems, methods and apparatus are provided for depositing alternating layers of dielectric material and sacrificial material in repeating iterations to form a vertical stack, forming a plurality of vertical openings through the vertical stack to form elongated vertical, pillar columns with sidewalls in the vertical stack, patterning the pillar columns to expose a location to form a channel region, selectively removing a portion of the sacrificial material to form first horizontal openings in the first horizontal direction in the sidewalls of the elongated vertical, pillar columns, and depositing a channel material in the first horizontal openings to form the channel region within the sidewalls for the horizontally oriented access devices.

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Номер записи: 73
03-03-2022 дата публикации

Gate dielectric repair on three-node access device formation for vertical three-dimensional (3d) memory

Номер: US20220068933A1
Автор: Armin Saeedi Vahdat, Gurtej S. Sandhu, John A. Smythe Iii, Scott E. Sills, Si-Woo Lee
Принадлежит: Micron Technology Inc

Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material. Selectively removing the sacrificial material in the first region to form first horizontal openings. Repairing a second side of the gate dielectric exposed where the sacrificial material was removed in the first region. Depositing a first source/drain region, a channel region, and a second source/drain region in the first horizontal openings.

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Номер записи: 74
03-03-2022 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE

Номер: US20220068963A1
Автор: LEE Nam Jae
Принадлежит: SK HYNIX INC.

A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes: a bit line overlapping with a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit line; vertical channels connected to the bit line, the vertical channels penetrating the interlayer insulating layers and the conductive patterns, the vertical channels protruding farther in the first direction than the stacked interlayer insulating layers and the conductive patterns; a connection pattern in contact with a portion of each of the vertical channels that protrudes farther in the first direction than the stacked interlayer insulating layers and the conductive patterns, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source select line surrounding the source channel.

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Номер записи: 75
14-02-2019 дата публикации

SYSTEMS AND METHODS FOR REFRESHING A MEMORY BANK WHILE ACCESSING ANOTHER MEMORY BANK USING A SHARED ADDRESS PATH

Номер: US20190051347A1
Автор: Lee Joosang
Принадлежит:

A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path that refreshes a first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activates a row of a second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path. 1. A system comprising:a plurality of memory banks configured to store data, wherein the plurality of memory banks comprises a first set of memory banks and a second set of memory banks;an address path coupled to the plurality of memory banks, wherein the address path is configured to provide a row address to the plurality of memory banks; anda command address input circuit coupled to the address path, wherein the command address input circuit is configured to refresh the first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activate a row of the second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path.2. The system of claim 1 , wherein the command address input circuit is configured to refresh the second set of memory banks via the address path and claim 1 , when the command address input circuit refreshes the second set of memory banks claim 1 , activate a second row of the first set of memory banks to store the data or read the data from the row of the first set of memory banks via the address path.3. The system of claim 1 , wherein the command address input circuit is configured to refresh the plurality of memory banks of the semiconductor device by outputting a first row address of the first set of memory banks to be refreshed or a second row address of the ...

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Номер записи: 76
25-02-2021 дата публикации

WORD LINE DRIVERS SHARING A TRANSISTOR, AND RELATED MEMORY DEVICES AND SYSTEMS

Номер: US20210057008A1
Автор: Kim Tae H
Принадлежит:

Systems and memory devices that include a transistor shared by word line drivers are described. A memory device includes a first word line driver coupled to a first word line, and a second word line driver coupled to a second word line. The memory device also includes a transistor comprising a first terminal coupled to an output of the first word line driver, and a second terminal coupled to an output of the second word line driver. 1. A memory device , comprising:a first word line driver coupled to a first word line and configured to receive a first pre-decoding signal;a second word line driver coupled to a second word line and configured to receive a second pre-decoding signal different than the first pre-decoding signal; a first terminal coupled to a first output terminal of the first word line driver; and', 'a second terminal coupled to a second output terminal of the second word line driver; and, 'a first PMOS transistor comprisinga third word line driver coupled to a third word line and configured to receive the first pre-decoding signal;a fourth word line driver coupled to a fourth word line and configured to receive the second pre-decoding signal; and a third terminal coupled to a third output terminal of the third word line driver; and', 'a fourth terminal coupled to a fourth output terminal of the fourth word line driver., 'a second PMOS transistor comprising2. (canceled)3. The memory device of claim 1 , wherein the first PMOS transistor further comprises a third terminal configured to receive a memory address signal.4. The memory device of claim 1 , wherein the first word line driver comprises:a third PMOS transistor configured to receive the first pre-decoding signal at a first gate thereof; anda first NMOS transistor configured to receive the first pre-decoding signal at a second gate thereof and configured to receive a third pre-decoding signal at a first input terminal thereof.5. The memory device of claim 4 , wherein the third PMOS transistor further ...

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Номер записи: 77
25-02-2021 дата публикации

WORD LINE DRIVER CIRCUITRY, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS

Номер: US20210057009A1
Автор: KIM Tae H.
Принадлежит:

A word line driver circuit is disclosed. A word line driver circuit may include a circuit configured to generate a clamped voltage based on a first fixed supply voltage and in response to receipt of a first control signal triggering an active mode. The circuitry may further be configured to generate an internal global word line voltage based on the clamped voltage during the active mode. Further, the word line driver circuit may include at least one main word line driver configured to receive the internal global word line voltage and generate a global word line voltage. Additionally, the word line driver circuit may include at least one sub word line driver configured to receive the global word line voltage and generate a word line voltage. 1. A word line driver circuit , comprising: generate a clamped voltage based on a first fixed supply voltage and in response to receipt of a control signal triggering an active mode; and', 'generate an internal global word line voltage based on the clamped voltage during the active mode;, 'a circuit configured toat least one main word line driver configured to receive the internal global word line voltage and generate a global word line voltage; andat least one sub word line driver configured to receive the global word line voltage and generate a word line voltage.2. The word line driver circuit of claim 1 , wherein energy leakage in one or more of the circuit claim 1 , the at least one main word line driver claim 1 , and the at least one sub word line driver decreases the clamped voltage during the active mode.3. The word line driver circuit of claim 1 , wherein the circuit is further configured to:generate a second fixed supply voltage substantially equal to the first fixed supply voltage in response to receipt of a second, different control signal including a pre-charge commandtriggering a pre-charge mode; andgenerate the internal global word line voltage based on the second fixed supply voltage during the pre-charge mode.4. ...

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Номер записи: 78
13-02-2020 дата публикации

Sub word line driver of semiconductor memory device

Номер: US20200051611A1
Автор: Jae Hong Jeong
Принадлежит: SK hynix Inc

A layout structure of a sub word line driver for use in a semiconductor memory device may be disclosed. The sub word line driver may include a first active region through which first and second main word lines pass. The sub word line driver may include first gates arranged in the first active region, and configured to receive word line selection signals.

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Номер записи: 79
10-03-2022 дата публикации

Vertical 3d memory device and method for manufacturing the same

Номер: US20220077236A1
Автор: Corrado Villa, Paolo Fantini, Paolo Tessariol
Принадлежит: Micron Technology Inc

A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.

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Номер записи: 80
10-03-2022 дата публикации

THREE-DIMENSIONAL MEMORY DEVICES HAVING ISOLATION STRUCTURE FOR SOURCE SELECT GATE LINE AND METHODS FOR FORMING THE SAME

Номер: US20220077283A1
Автор: Geng Jingjing, Guo Zhen, Wu Jiajia, Xiao Meng, ZHANG Hui, Zhou Yang
Принадлежит:

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, and one or more isolation structures. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). Each isolation structure surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. 1. A three-dimensional (3D) memory device , comprising:a substrate;a memory stack on the substrate comprising a plurality of interleaved conductive layers and dielectric layers, an outmost one of the conductive layers toward the substrate being a source select gate line (SSG);a plurality of channel structures each extending vertically through the memory stack; andone or more isolation structures each surrounding at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure.2. The 3D memory device of claim 1 , wherein the plurality of channel structures are disposed in a core array region and an edge region in the plan view claim 1 , and the at least one channel structure is disposed in the edge region.3. The 3D memory device of claim 2 , wherein the memory stack comprises a staircase structure claim 2 , the edge region is laterally between the staircase structure and the core array region claim 2 , and the at least one channel structure is disposed in an outmost column adjacent to the staircase structure in the plan view.4. The 3D memory device of claim 2 , wherein a lateral dimension of the at least one channel structure is greater than a lateral dimension of the channel structures disposed in the core array region.5. The 3D memory device of claim 1 , wherein a lateral ...

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Номер записи: 81
20-02-2020 дата публикации

MEMORY CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Номер: US20200058328A1
Автор: Chang Meng-Sheng, WU Min-Shin, YANG Yao-Jen
Принадлежит:

A memory circuit array includes a first read device and a first program device. The first read device is coupled to a first bit line. The first read device includes a first transistor coupled to a first word line, and a second transistor coupled to the first word line. The first program device is coupled to the first read device. The first program device includes a third transistor coupled to a second word line, and a fourth transistor coupled to the second word line. 1. A memory circuit comprising: a first transistor coupled to a first word line; and', 'a second transistor coupled to the first word line; and, 'a first read device coupled to a first bit line, the first read device comprising a third transistor coupled to a second word line; and', 'a fourth transistor coupled to the second word line., 'a first program device coupled to the first read device, the first program device comprising2. The memory circuit of claim 1 , wherein the second transistor is coupled in parallel with the first transistor claim 1 , and the fourth transistor is coupled in parallel with the third transistor.3. (canceled)3. The memory circuit of claim 1 , whereinthe first transistor comprises a first terminal, a second terminal and a third terminal; and the first terminal of the first transistor, the first terminal of the second transistor and the first word line are coupled to each other,', 'the second terminal of the first transistor is coupled to the second terminal of the second transistor, and', 'the third terminal of the first transistor is coupled to at least the third terminal of the second transistor., 'the second transistor comprises a first terminal, a second terminal and a third terminal,'}4. The memory circuit of claim 3 , whereinthe third transistor comprises a first terminal, a second terminal and a third terminal; and the first terminal of the third transistor, the first terminal of the fourth transistor and the second word line are coupled to each other,', 'the second ...

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Номер записи: 82
04-03-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FORMATION

Номер: US20210066492A1
Автор: Huang Chin-Yi, SHIH Wade
Принадлежит:

A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate. 1. A semiconductor device , comprising: a first source/drain region;', 'a second source/drain region;', 'a channel region between the first source/drain region and the second source/drain region; and', 'a gate electrode over the channel region;, 'a transistor, comprisinga dielectric layer over the gate electrode;a capacitive field plate over the dielectric layer; anda word line electrically coupled to the capacitive field plate.2. The semiconductor device of claim 1 , comprising:a first ion implant region disposed between the first source/drain region and the channel region; anda second ion implant region disposed between the second source/drain region and the channel region.3. The semiconductor device of claim 1 , comprising:a spacer disposed between the gate electrode and the dielectric layer.4. The semiconductor device of claim 1 , comprising:an isolation region adjacent to the first source/drain region; anda doped region adjacent to the isolation region.5. The semiconductor device of claim 4 , comprising:a vertical interconnect access (VIA) electrically coupled to the doped region; anda body contact electrically coupled to the VIA.6. The semiconductor device of claim 1 , wherein:the gate electrode has a first length, andthe capacitive field plate has a second length different than the first length.7. The semiconductor device of claim 6 , wherein the second length is greater than the first length.8. The semiconductor device of claim 1 , wherein the capacitive field plate overlies the gate electrode.9. The semiconductor device of claim 1 , wherein the dielectric layer comprises a resist protective oxide (RPO) film.10. The semiconductor device of claim 9 , wherein the RPO film comprises an ...

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Номер записи: 83
12-03-2015 дата публикации

INTERCONNECTION FOR MEMORY ELECTRODES

Номер: US20150070960A1
Автор: Castro Hernan A., Flores Everardo Torres, Tang Stephen H.S.
Принадлежит:

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. 1. An integrated circuit comprising a vertical interconnection region for connecting multiple levels of conductive lines , the integrated circuit comprising:a first bundle of terminating adjacent conductive lines extending in a first direction and a second bundle of terminating adjacent conductive lines extending in the first direction, the first bundle and the second bundle being separated by a gap in the first direction, wherein the first bundle includes inner conductive lines that co-terminate in the first direction and a pair of outer conductive lines that extend farther than the inner conductive lines in the first direction;a plurality of non-terminating conductive lines adjacent the first bundle that pass through the gap in the first direction; anda plurality of vertical connectors formed in the gap.2. The integrated circuit of claim 1 , wherein some of the non-terminating conductive lines include a jog segment within the gap which extends in a second direction crossing the first direction.3. The integrated circuit of claim 2 , wherein the vertical connectors are connected to the jog segments of the non-terminating conductive lines.4. The integrated circuit of claim 2 , wherein the non-terminating conductive lines are formed at a same vertical level as the first and second bundles claim 2 , and wherein the vertical connectors are pass-through vertical connectors that electrically connect structures at vertical levels above and below the same vertical level.5. The integrated circuit of claim 2 , wherein the conductive lines of one of the first and second bundles and the non-terminating lines have a periodic line-to- ...

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Номер записи: 84
12-03-2015 дата публикации

MEMORY SYSTEM

Номер: US20150071019A1
Автор: Toda Haruki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different physical states; and an access circuit operative to make access to the memory cell via the first line and the second line, wherein the access circuit, on writing data in the access cell, uses a non-access-side first line driver to electrically connect a non-access first line adjacent to an access first line to a first potential power supply via a diode-connected transistor. 1. A memory system , comprising:a cell array including a unit cell array, said unit cell array containing plural first lines, plural second lines intersecting said plural first lines, and plural memory cells provided at the intersections of said plural first lines and said plural second lines and operative to store data in accordance with different physical states; andan access circuit operative to make access to said memory cell via said first line and said second line,wherein an access-targeted memory cell of said plural memory cells is defined as an access cell, a first line connected to said access cell of said plural first lines is defined as an access first line and other first lines as non-access first lines,said access circuit includes two first line drivers each operative to alternately control said first lines on alternate lines,one for controlling said access first line of said two first line drivers is defined as an access-side first line driver and the other as a non-access-side first line driver, andsaid access circuit, on writing data in said access cell, uses said non-access-side first line driver to electrically connect said non-access first line adjacent to said access first line to a first potential power supply via ...

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Номер записи: 85
29-05-2014 дата публикации

Vccmin for a dual port synchronous random access memory (dpsram) cell utilized as a single port synchronous random access memory (spsram) cell

Номер: US20140146631A1
Автор: Cheng Hung Lee, Chia-Cheng Chen, Ching-Wei Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

One or more techniques for improving Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell are provided herein. In some embodiments, a second word line signal is sent to a second word line of the DPSRAM cell. For example, the second word line signal is sent in response to a logical low at a first bit line or a logical low at a second bit line. In this way, Vccmin is improved for the DPSRAM cell.

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Номер записи: 86
17-03-2022 дата публикации

Backside Power Rail Architecture

Номер: US20220084561A1
Автор: Amirante Ettore, Chen Andy Wangkun, Chong Yew Keong, Kulshrestha Ayush, N/A Sony, Thyagarajan Sriram
Принадлежит:

Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic. 1. A device , comprising:first backside power rails that supply a core voltage to memory logic; andsecond backside power rails that supply a periphery voltage to control logic,wherein at least one first backside power rail has a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.2. The device of claim 1 , wherein the first backside power rails provide a first net that supplies the core voltage to the memory logic claim 1 , and wherein the second backside power rails provide a second net that supplies the periphery voltage to the control logic.3. The device of claim 1 , wherein the rail break provides a spatial opening in the at least one first backside power rail to allow coupling of the at least one second backside power rail to the control logic.4. The device of claim 1 , wherein the core voltage refers to an internal core voltage (VDDC) claim 1 , and wherein the periphery voltage refers to an internal periphery voltage (VDDP).5. The device of claim 1 , wherein the memory logic has wordline headers and wordline drivers claim 1 , and wherein the control logic has a wordline controller.6. The device of claim 5 , wherein:the wordline drivers include an upper wordline driver for an upper core array and a lower wordline driver for a lower core array, andthe wordline headers include an upper wordline header that operates as an upper power-gating header for the upper wordline driver and a lower wordline header that ...

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Номер записи: 87
17-03-2022 дата публикации

METHOD OF REDUCING PROGRAM DISTURBANCE IN MEMORY DEVICE AND MEMORY DEVICE UTILIZING SAME

Номер: US20220084573A1
Автор: CUI YING, Jia Jianquan, Li Kaiwei, Li Shan, You Kaikai, Zhang An
Принадлежит:

A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level. The controller is further configured to, after the voltage on the select line reaches the second level, drive a voltage on a selected word line of the word lines from the second level to a third level higher than the first level to program the memory cells coupled to the selected word line. 1. A memory device , comprising:bit lines;a cell array comprising strings, each of the strings comprising memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells;a select line coupled to the select cells;a dummy word line coupled to the dummy cells;word lines each coupled to a respective row of the memory cells; and drive a voltage on the dummy word line from a first level to a second level lower than the first level;', 'drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level; and', 'after the voltage on the select line reaches the second level, drive a voltage on a selected word line of the word lines from the second ...

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Номер записи: 88
17-03-2022 дата публикации

Semiconductor device

Номер: US20220084859A1
Автор: Bong Soon LIM, Dae Seok Byeon, Jae Ick Son
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.

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Номер записи: 89
17-03-2022 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20220085052A1
Автор: HIROTSU Yu, Iwasaki Taichi, Matsumoto Sota, MATSUURA Osamu, WATARAI Ayumi
Принадлежит: Kioxia Corporation

A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer. 1. A semiconductor memory device comprising:a substrate including a core region and a first region, the first region being provided to surround an outer periphery of the core region;a source line provided above the substrate in the core region;a plurality of word lines provided above the source line in the core region, the word lines being provided apart from each other in a first direction intersecting a surface of the substrate;a pillar provided to extend in the first direction in the core region, a bottom of the pillar reaching the source line, and an intersecting portion of the pillar and one of the word lines functioning as a memory cell;an outer peripheral conductive layer provided to surround the core region in the first region, the outer peripheral conductive layer being included in a first layer including the source line;a lower layer conductive layer provided in the first region, the lower layer conductive layer being included in a second layer between the first layer and the substrate; anda first contact provided on the lower layer conductive layer to surround the core region in the first region, an upper end of the first contact being included in the first layer, and the first contact being electrically ...

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Номер записи: 90
28-02-2019 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20190066744A1
Автор: NIKI Yusuke
Принадлежит: Toshiba Memory Corporation

A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL to the sense amplifier. The decoder includes first and second multiplexers. The first multiplexer includes a first n-type transistor and a first p-type transistor. The first n-type transistor is connected to the first BL and capable of applying a first voltage for writing a first logic or a non-select voltage for not writing data to the first BL. The first p-type transistor is connected to the first BL and capable of applying a second voltage for writing a second logic or the non-select voltage to the first BL. The second multiplexer is connected between the first multiplexer and the sense amplifier and transmits the first voltage or the non-select voltage to the first n-type transistor and transmits the second voltage or the non-select voltage to the first p-type transistor. 1. A semiconductor storage device comprising:a memory cell array;a plurality of bit lines connected to the memory cell array;a plurality of word lines connected to the memory cell array;a sense amplifier configured to read data from memory cells in the memory cell array or write data to the memory cells via the bit lines; anda decoder configured to connect a first bit line selected from the bit lines to the sense amplifier, wherein the decoder includesa first multiplexer comprising a first n-type transistor connected to the first bit line among the bit lines and configured to apply a first voltage for writing a first logic or a non-select voltage for not writing data to the first bit line, and a first p-type transistor connected to the first bit line and configured to apply a second voltage for writing a second logic or the non-select voltage to the first bit line, anda second multiplexer connected between the first multiplexer and the sense amplifier and configured to transmit the first voltage or the non-select voltage to the first n-type transistor and transmit the second voltage or the non-select ...

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Номер записи: 91
08-03-2018 дата публикации

Devices, systems, and methods for increasing the usable life of a storage system by optimizing the energy of stored data

Номер: US20180068701A1
Автор: "DABREU MANUEL ANTONIO", Das Ashutosh Kumar
Принадлежит: SMART IOPS, INC.

In certain aspects, a device may include a memory and a controller coupled to the memory. The controller may be configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory. The controller may encode and tag the incoming data (from the host) to minimize the charge that is required to be stored in the non-volatile memory. 1. A data storage device , comprising:a memory device comprising memory; and assemble a plurality of equalized data packets such that each of the equalized data packets is for a different page in a plurality of pages of a memory;', 'shuffle one or more bits in the assembled plurality of equalized data packets to form an optimized data packet, wherein the shuffling of the one or more bits reduces an amount of energy to be stored in the memory while maintaining equalization; and', 'store the optimized data packet in the memory., 'a controller communicatively coupled to the memory device and comprising logic to2. The data storage device of claim 1 , wherein each of the equalized data packets is for a different page in a plurality of pages of a wordline claim 1 , block of wordlines claim 1 , or cluster of blocks of wordlines in the memory; and wherein the shuffling of the one or more bits reduces the amount of energy to be stored in the wordline claim 1 , block of wordlines claim 1 , or cluster of blocks of wordlines while maintaining equalization.3. The data storage device of claim 1 , wherein the controller further comprises logic to:generate one or more tags, wherein the one or more tags comprise decoding instructions based on the optimized data packet; andstore the one or more tags in the optimized data packet.4. The data storage device of claim 3 , wherein the controller further comprises logic to:receive a plurality of data packets; andequalize each data packet of the plurality of data packets to form the plurality of equalized data packets.5. The data storage device of claim 4 , ...

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Номер записи: 92
28-02-2019 дата публикации

THREE-DIMENSIONAL MEMORY DEVICE WITH STRADDLING DRAIN SELECT ELECTRODE LINES AND METHOD OF MAKING THEREOF

Номер: US20190067025A1
Автор: SAI Akihisa, SAKAKIBARA Kiyohiko, YADA Shinsuke
Принадлежит:

An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are replaced with, electrically conductive layers. An insulating cap layer is formed over the alternating stack. After formation of memory stack structures through each layer of the alternating stack and the insulating cap layer, a line trench straddling a neighboring pair of rows of the memory stack is formed. Sidewalls of the line trench include a sidewall of each memory stack structure within the neighboring pair of rows of the memory stack structures. A drain select gate dielectric and a drain select electrode line are formed within the line trench. The drain select electrode line controls flow of electrical current through an upper portion of a vertical semiconductor channel within each memory stack structure below the drain regions to activate or deactivate the neighboring rows. 2. The three-dimensional memory device of claim 1 , wherein:each vertical semiconductor channel contacts a bottom surface of a respective drain region; andeach drain region contacts a respective memory film.3. The three-dimensional memory device of claim 2 , further comprising a drain select gate dielectric contacting at least one of the sidewalls of the line trench and a bottom surface of the line trench claim 2 , wherein the drain select electrode line contacts the drain select gate dielectric.4. The three-dimensional memory device of claim 3 , wherein the vertical semiconductor channel comprises an L-shaped doped region having a doping of an opposite conductivity type from a conductivity type of the drain regions and contacting a sidewall and a bottom surface of the drain select gate dielectric.5. The three-dimensional memory device of claim 4 , wherein the L-shaped doped region has a greater concentration of electrical dopants than portions of the vertical semiconductor channels that extend through the alternating stack and having a same ...

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Номер записи: 93
08-03-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

Номер: US20180068706A1
Автор: YOO Deung Kak
Принадлежит: SK HYNIX INC.

Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array to which a plurality of word lines are coupled, a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation, and a control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation, wherein the control logic controls the voltage generation circuit such that, during the discharge operation, a potential level of a selected word line among the plurality of word lines is discharged, and then potential levels of the other unselected word lines are discharged. 1. A semiconductor memory device comprising:a memory cell array to which a plurality of word lines are coupled;a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation; anda control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation,wherein the control logic controls the voltage generation circuit such that, during the discharge operation, a potential level of a selected word line among the plurality of word lines is discharged, and then potential levels of the other unselected word lines are discharged.2. The semiconductor memory device according to claim 1 , wherein the voltage generation circuit applies a program voltage to the selected word line and applies a pass voltage to the unselected word lines claim 1 , during the program operation.3. The semiconductor memory device according to claim 1 , wherein the voltage generation circuit comprises:a high voltage pump configured to generate a high voltage in response to an enable signal;a regulator ...

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Номер записи: 94
08-03-2018 дата публикации

Semiconductor device

Номер: US20180068708A1
Автор: Koji Nii
Принадлежит: Renesas Electronics Corp

A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.

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Номер записи: 95
08-03-2018 дата публикации

SRAM CELL WITH DYNAMIC SPLIT GROUND AND SPLIT WORDLINE

Номер: US20180068716A1
Автор: Wong Robert C.
Принадлежит:

An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters. 1. A memory cell , comprising:cross coupled inverters comprising PFETs and NFETs;a bitline left (BL) which accesses a first inverter of the cross coupled inverters by enabling a first access transistor;a bitline right (BR) which accesses a second inverter of the cross coupled inverters by enabling a second access transistor; anda split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters,wherein the GNDR and GNDL allow for differential signaling.2. The memory cell of claim 1 , further comprising:a wordline left (WL) which enables the first access transistor; anda wordline right (WR) which enables the second access transistor.3. The memory cell of claim 1 , wherein during global reset of memory array to zero state claim 1 , the GNDL is raised to Vdd to pull down CR and push up CL.4. The memory cell of claim 1 , wherein during global set of memory array to one state claim 1 , the GNDR is raised to Vdd to pull down the CL and push up the CR.5. The memory cell of claim 1 , wherein during global set/reset of specific columns of ...

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Номер записи: 96
08-03-2018 дата публикации

SRAM CELL WITH DYNAMIC SPLIT GROUND AND SPLIT WORDLINE

Номер: US20180068718A1
Автор: Wong Robert C.
Принадлежит:

An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters. 1. A memory cell , comprising:a first ground line (GNDL) separated from a second ground line (GNDR), the GNDL being connected to a first inverter of cross coupled inverters and the GNDR being connected to a second inverter of the cross coupled inverters,wherein during read access on bitline right (BR), the GNDL is raised by a predetermined amount of Vdd above a common ground GND and/or the GNDR is lowered by a predetermined amount of Vdd below the common ground GND.2. The memory cell of claim 1 , wherein the predetermined amount of Vdd above the common ground GND is about 10% of Vdd.3. The memory cell of claim 1 , wherein the predetermined amount of Vdd below the common ground GND is about 10% of Vdd.4. The memory cell of claim 1 , further comprising:a first access transistor that controls access to the cross coupled inverters by a first bitline; anda second access transistor that controls access to the cross coupled inverters by a second bitline.5. The memory cell of claim 1 , wherein GNDL and GNDR are kept common.6. The memory cell of claim 1 , wherein the GNDR and the GNDL are not strapped together.7. The memory cell of claim 1 , wherein the GNDR and GNDL allow for differential signaling.8. The memory cell of claim 1 , wherein each of the first ...

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Номер записи: 97
12-03-2015 дата публикации

MEMORY CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM

Номер: US20150074346A1
Автор: Chang Sheng-Ming, CHEN Shang-Pin, Hsieh Bo-Wei, Hung Chih-Chien, Liou Ming-Shi, Luo Yan-Bin
Принадлежит:

A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed. 2. The memory controller of claim 1 , wherein the chip-select transmitter generates the first signal and the second signal synchronously.3. The memory controller of claim 1 , wherein when a notification is acquired to be performed by the first signal and the second signal claim 1 , the first signal is asserted to a first voltage level for a specific time interval claim 1 , and the second signal is asserted to a second voltage level different from the first voltage level for the specific time interval.4. The memory controller of claim 3 , wherein the memory controller further provides a clock output claim 3 , and the specific time interval equals to a period of the clock output.5. The memory controller of claim 1 , wherein the memory controller is a DDR3 memory controller for controlling a DDR3 memory module.7. The memory module of claim 6 , wherein the first signal and the second signal reach the predetermined resistor substantially at the same time via the first conducting path and the second conducting path respectively.8. The memory module of claim 6 , wherein a first impedance obtained by looking into the second end of the first conducting path substantially equals a second impedance obtained by looking into the first terminal of the ...

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Номер записи: 98
27-02-2020 дата публикации

Sram cell with dynamic split ground and split wordline

Номер: US20200066334A1
Автор: Robert C. Wong
Принадлежит: International Business Machines Corp

An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.

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Номер записи: 99
27-02-2020 дата публикации

SYMMETRIC BIPOLAR SWITCHING IN MEMRISTORS FOR ARTIFICIAL INTELLIGENCE HARDWARE

Номер: US20200066340A1
Автор: Kumar Suhas, Sharma Amit S., Sheng Xia
Принадлежит:

A memristor device includes a first electrode, a second electrode, and a memristor layer disposed between the first electrode and the second electrode. The memristor layer is formed of a metal oxide. The memristor layer includes a plurality of regions that extend between the first electrode and the second electrode. The plurality of regions of the memristor layer are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions. The controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage. 1. A memristor device comprising:a first electrode;a second electrode; anda memristor layer formed of a metal oxide and disposed between the first electrode and the second electrode, the memristor layer including a plurality of regions that extend between the first electrode and the second electrode and are created with different concentrations of oxygen before electrical operation, and, during electrical operation, a voltage-conductance characteristic of the memristor device is controlled based on the different concentrations of oxygen of the plurality of regions, the controlling of the voltage-conductance characteristic including increasing or decreasing the conductance of the memristor device toward a target conductance at a specific voltage.2. The memristor device of claim 1 , wherein the controlling of the voltage-conductance characteristic includes increasing or decreasing the conductance of the memristor device toward a plurality of target conductances in a voltage range.3. The memristor device of claim 2 ,wherein the voltage-conductance characteristic indicates a voltage-conductance relationship between the voltage and the conductance of the memristor device ...

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Номер записи: 100