УСТРОЙСТВО ПРЕДОТВРАЩЕНИЯ НЕСАНКЦИОНИРОВАННОГО ДОСТУПА ПРИ ЗАПУСКЕ, ЗАВЕРШЕНИИ СЕАНСА, ПЕРЕУСТАНОВКЕ ГЕОГРАФИЧЕСКИХ ИНФОРМАЦИОННЫХ СИСТЕМ

Устройство предотвращения несанкционированного доступа при запуске и завершении сеанса программы на постоянном запоминающем устройстве компьютера путем проверки некоторых регистров центрального вычислительного устройства правомерности выполняемых операций при инициализации в режиме отладки под управлением утилиты отладчика, отличающиеся тем, что для расширения функциональных возможностей устройства за счет предотвращения несанкционированного доступа при запуске и завершении сеанса, при переустановке географических информационных систем и цифровой топографической основы электронной базы данных выполняется разделение всех оперируемых данных на три класса необходимого, спонтанного и комбинированного необходимо-спонтанного типа данных, интеграция модуля матрицы контроля доступа и модуля утилиты безопасности.

Halbleiterbauelement mit nichtflüchtigem Speicher

DATENSPEICHER UND VERFAHREN ZUM BEREITSTELLEN DESSELBEN

Ein Datenspeicher umfasst eine Speicherzellenanordnung mit einer Mehrzahl von flächig angeordneten Speicherzellen und eine mehrlagige Anordnung von Verbindungselementen, die eine Verbindung zwischen der Mehrzahl von Speicherzellen bereitstellt und die mit der Speicherzellenanordnung zumindest teilweise überlappt. Die mehrlagige Anordnung von Verbindungselementen ist ausgebildet, dass bei einer Entfernung einer ersten Lage von Verbindungselementen unter Verbleib einer zwischen der ersten Lage und der Speicherzellenanordnung angeordneten zweiten Lage von Verbindungselementen eine Unterbrechung zumindest einer Verbindung eintritt.

BETRUGSSICHERE VERPACKUNG

Verhinderung der Veränderung von Daten, die in einer sicheren integrierten Speicherschaltung gespeichert sind.

ELEKTRONISCHE UND/ODER ELEKTRISCHE INTEGRIERTE SCHALTUNG MIT ISOLATIONSMITTELN ENES FUNKTIONELLEN MODULS , ISOLATIONSANORDNUNG UND -VERFAHREN SOWIE IHRE VERWENDUNG

ELECTRONIC AND/OR ELECTRICAL INTEGRATED CIRCUIT WITH ISOLATION MEANS ENES OF FUNCTIONAL MODULE, ISOLATION ARRANGEMENT AND - PROCEDURES AS WELL AS YOUR USE

Single chip microprocessor, math co-processor, random number generator, real-time clock and ram having a one-wire interface

Policy engine and methods and systems for protecting data

PREVENTION OF ALTERATION OF DATA STORED IN SECURE INTEGRATED CIRCUIT CHIP MEMORY

PROGRAMMABLE ACCESS PROTECTION IN A FLASH MEMORY DEVICE

A memory device (100) comprises a memory array (102) having corresponding first access control bits (202, 204) to control access thereto. A second set of access control bits (104) is provided to control write access to the first access control bits. The memory array is divided into memory blocks, each block having a corresponding access control bit. At least one such block (BLK0) is further subdivided into pages, each page having a corresponding control bit.

ELECTRIC SYSTEM AND/OR JUST ELECTRONICS HAVE MEANS Of INSULATION Of FUNCTIONAL UNMODULE, DEVICE AND PROCESS Of INSULATION AND UTILISATIONCORRESPONDANTS

METHOD OF ALLOCATING MEMORY SPACE

SECURE ELEMENT AND METHOD IN SUCH A SECURE ELEMENT SOCIETY

L'invention concerne un élément sécurisé, tel qu'une carte à microcircuit, comprenant une mémoire non-volatile réinscriptible et une interface de communication avec un lecteur externe, ainsi qu'un procédé mis en œuvre dans un tel élément sécurisé. Ce procédé comprend les étapes suivantes : - réception d'une commande à travers l'interface de communication ; - à réception de ladite commande, copie d'une image mémoire mémorisée dans une zone (ISD, D1, D2 ; ISD', D1', D2') de la mémoire non-volatile vers une partie (ISD', D1', D2' ; ISD, D1, D2) de la mémoire non-volatile distincte de ladite image mémoire.

CIRCUIT FOR CONSERVING MEMORY DATA UPON POWER FAILURE OF A KEY SWITCHING SYSTEM

PURPOSE: A circuit for conserving memory data is provided to prevent the damage to memory data by connecting the high enable terminal of a decoder to an output terminal of a voltage sensor. CONSTITUTION: A memory unit(2) receives plural control signals from a processor and stores the received data. A decoder(12) is connected to a chip enable terminal of the memory unit(2), receives the plural control signal from the processor, outputs the control signals in a normal operation voltage range of the processor, and converts the write pin of the memory unit(2) in an abnormal operation voltage range of the processor into an inactive state or converts the chip enable terminal into a disable state. A voltage sensor(14) outputs a voltage of a low level in the abnormal operation voltage range. COPYRIGHT 2000 KIPO ...

MEMORY CIRCUIT COMPRISING MEANS FOR DETECTING AN ERROR INJECTION

The invention relates to a memory circuit (MEM1) comprising a memory plane (MA) comprising memory cells (MC), and an address decoder (RDEC) configured to apply to the memory plane signals (V0-VI-1, Vsel) for selecting a group of memory cells as a function of an address (AD1). According to the invention, the memory circuit comprises means (LCT) for capturing signals (Vsel) for selecting memory cells appearing in the memory plane, and means (RCOD), for reconstructing, on the basis of the selection signals captured, an address (AD2) of a selected group of memory cells.

SOLID-STATE MEMORY DEVICE

The invention relates to a solid-state memory device with a plurality of memory cells (3) arranged on a semiconductor substrate at crossing points of bit lines and word lines and controllable for programming with data contents using a word line control circuit (4) and a bit line control circuit (5). Enabling memory cells (12, 14) are arranged along an enabling bit line (9, 10, 13), can be controlled by a controllable enabling bit line control circuit (11) arranged to be separate and independent of the bit line control circuit (5) and are associated with the memory cells (3). Said enabling memory cells can be actuated by an enabling value to enable the memory cells (3) of a predetermined word line.

Information storage apparatus and information processing apparatus using the same

In a small and thin memory module for sharing data among electronic devices such as information processing apparatuses, a write prohibit state can be visually recognized. A conductive seal is attached to a predetermined position on a support member, thereby setting the memory module in the write prohibit state. The conductive seal visually indicates the write prohibit state. When the memory module is mounted in a connector section of a card-shaped holder, connector pins are electrically connected to each other via the conductive seal. Thus, a write prohibit mechanism is realized at low cost.

Fusing and detection circuit

A fusing and detection circuit includes a diode fusing element which is coupled to a fuse input terminal of an integrated circuit. Upon the application of the proper voltage at the fuse input terminal, the fuse element is blown, causing the diode to become a low impedance resistor. The detection circuitry senses whether the fuse has been blown or not and provides a lock or unlock indication at an output terminal. The fusing and detection circuit is designed to thwart attempts to change the lock status to an unlock status after the fuse has been blown.

Secure module with microprocessor and co-processor

An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.

Semiconductor memory device

A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.

Method and arrangement for the verification of NV fuses as well as a corresponding computer program product and a corresponding computer-readable storage medium

The invention relates to a method and an arrangement for the verification of NV fuses as well as to a corresponding computer program product and to a corresponding computer-readable storage medium which can be used notably for the detection of attacks on the smart card security which modify EEPROM contents and hence also the contents of EEPROM fuses. During the reset phase the fuses are read from the EEPROM. The fuse values successively read out are then automatically verified. One possible implementation is, for example, to load the fuse values read out into a signature register, followed by comparison with a reference value. Appropriate security measures can be activated should the automatic verification indicate an error, for example, due to unauthorized modification of a fuse or attack on the boot operation.

An apparatus and a method for erasing data stored in a memory device

The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal. Such an approach enables the security of a memory device to be improved, and in particular prevents hackers from taking advantage ...

SECURE MEMORY HAVING ANTI-WIRE TAPPING

According to a first aspect of the present invention, cryptography without a dedicated microprocessor on the smart card is employed to provide authentication of both the smart card and the smart card reader, and wherein the cryptography provides only a preselected number of attempts at authentication, if not reset, before access to the smart card is denied permanently. According to a second aspect of the present invention, access to each of the memory zones of the smart card may be individually provided by cryptography, passwords or both.

SOLID-STATE MEMORY DEVICE

Устройство для контроля оперативной памяти

Ein Verfahren und Einrichtungen zum Steuern der Kernlogiktemperatur

ELECTRONIC MEMORY AND ELECTRONIC ARRANGEMENT WITH SUCH MEMORY

PREVENTION OF ALTERATION OF DATA STORED IN SECURE INTEGRATED CIRCUIT CHIP MEMORY

Secure memory having anti-wire tapping

SECURE MEMORY HAVING ANTI-WIRE TAPPING

According to a first aspect of the present invention, cryptography without a dedicated microprocessor on the smart card is employed to provide authentication of both the smart card and the smart card reader, and wherein the cryptography provides only a preselected number of attempts at authentication, if not reset, before access to the smart card is denied permanently. According to a second aspect of the present invention, access to each of the memory zones of the smart card may be individually provided by cryptography, passwords or both.

Semiconductor storage device having effective and reliable redundancy process

Device of read-only memory in semiconductors

Dispositif de mémoire morte à semiconducteurs comportant des lignes de transmission de mots (WL), des lignes de transmission de bits (BL), des lignes de lecture (SL), des cellules de mémoire morte (CE), des transistors de sélection de colonne (CT), des moyens formant mémoire-tampon de page (38), des lignes de transmission de données (DLo à DLn), un circuit de commande d'entrée/amplificateur de lecture (34), des moyens formant mémoire-tampon d'entrée (30), un registre d'entrée/sortie (32) et un comparateur (36). Un premier code d'accès secret est verrouillé dans les moyens formant mémoire-tampon de page (38), un second code d'accès secret entré par les moyens formant mémoire-tampon d'entrée (30) est comparé au premier code 1u par le registre d'entrée/sortie (32) par octets dans le comparateur (36), et si les premier et second code concordent, le premier code est écrit dans des cellules de la ligne de rangée désignée par avance parmi les cellules de mémoire morte (CE).

Electrically erasable programmable read only memory

L'invention concerne une mémoire non volatile électriquement programmable et effaçable, comportant des registres mémoire adressables individuellement ou par bloc, et comportant également un registre de protection dans lequel un mot de protection peut être écrit, ce mot de protection comprenant un nombre donné de bits pour coder l'adresse d'un registre mémoire quelconque ou d'un bloc de registres mémoire, dite adresse limite, qui partage l'espace mémoire en une zone inférieure et une zone supérieure, et un bit de zone dont la valeur détermine celle des deux dites zones de la mémoire qui peut être protégée en écriture.

Safeguarding data in EEPROM microprocessor circuit in motor vehicle

L'invention concerne un dispositif de sauvegarde de données dans un ensemble à microprocesseur, notamment de véhicule automobile, dans lequel l'ensemble à microprocesseur comporte un microprocesseur associé à des moyens de mémorisation programmables électriquement. Ce dispositif est caractérisé en ce que les moyens de mémorisation comprennent des zones de stockage de données (E1,...) destinées à être utilisées successivement en boucle par le microprocesseur.

SAFETY DEVICE Of an ERASABLE AND REPROGRAMMABLE READ-ONLY MEMORY

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

The device for reducing the chip size replaces the function of the memory cell for writing the security call code to a dummy cell row (42) of a memory cell array (40) as well as removing one out of two I/O registers. The function of the removed register is replaced by a page buffer (38). A first security call code latched by the page buffer is read byte by byte with an I/O register (32). It is compared to a second security call code input through an I/O buffer (30). If both of them is equal, the first one is written to a dummy cell row (42). If not, an error signal is provided. Copyright 1997 KIPO ...

메모리 장치 및 그 동작 방법

... 본 기술은 전자 장치에 관한 것으로, 본 기술에 따른 비정상적인 컬럼 어드레스 생성을 방지하는 메모리 장치는, 복수의 메모리 셀들을 포함하는 메모리 셀 어레이, 외부로부터 입력되는 어드레스 신호 중 상기 복수의 메모리 셀들 중 선택된 메모리 셀들의 열 방향으로의 위치를 나타내는 컬럼 어드레스에 대응되는 컬럼 어드레스 신호가 입력될 때 인에이블 되는 컬럼 어드레스 제어 신호에 따라 상기 컬럼 어드레스를 생성하는 컬럼 어드레스 제어부를 포함한다.

TAMPER-RESISTING PACKAGING

A tamper-resistant packaging approach protects non-volatile memory. According to an example embodiment of the present invention, an array of magnetic memory elements (130-132) in an integrated circuit (100) are protected from magnetic flux (122) by a package (106) including a magnet (120). Flux from the magnet is directed away from the magnetic memory elements by the package. When tampered with, such as by removal of a portion of the package for accessing the magnetic memory elements, the package allows the flux to reach some or all of the magnetic memory elements, which causes a change in a logic state thereof. With this approach, the magnetic memory elements are protected from tampering.

METHOD AND APPARATUS FOR CONTROLLING WRITING TO MEMORY

The invention relates to a method and apparatus for controlling writing to a memory. The apparatus comprises control means (1-8) for the formation of a memory activation signal (C(Boolean not)E(Boolean not)) in response to the applying of a predetermined key code to the control means, the control means comprising timer means (2) which are started by applying the key code and which prevent the formation of the memory activation signal (C(Boolean not)E(Boolean not)) when a predetermined time has elapsed from the applying of the key code. In order to speed up the writing of long data blocks into a memory, the invention is characterized in that the control means further comprise means (3, 5, 6) for restarting the time means (2) within a predetermined time interval from the applying of the key code or the previous memory write operation as a result of a performed memory write operation.

A METHOD AND APPARATUS TO CONTROL CORE LOGIC TEMPERATURE

A method for controlling core logic temperature. The core logic having a memory controller (208) and memory components (207) coupled to system memory (102). The method having the step of determining the access rate to the system memory (102) through the core logic and controlling the temperature of the core logic by adjusting the access rate.

A METHOD AND APPARATUS FOR INVALIDATING MEMORY ARRAY WRITE OPERATIONS

An electronic device that invalidates a memory write operation before a memory address predecode occurs. The electronic device uses several dynamic latches (16, 17, 25, 26) to assert complementary clock like memory address data to drive the associated predecode circuitry (8). A stack of serially connected transistors (18, 20, 22, 24 ...) is coupled to the input node of each dynamic latch to provide input node state control. By managing the operation of each stack of serially connected transistors, the dynamic latches may be prevented from asserting their complementary clock like memory address data to the associated predecode circuitry in order to invalidate a memory write operation.

Time-key integrated circuit

A secure electronic circuit which (in its early life) can be electronically calibrated and written to, but thereafter holds its data securely.

Semiconductor memory for logic-hybrid memory

This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

Serial port interface to low-voltage low-power data module

A signal interface to a low-cost portable electronic token data module, which can be used with a wide variety of computers, including a tremendous variety of personal and other computers, as long as the computer includes an interface to RS232 (or some comparable stardard). The token has a one-wire-bus interface, implemented in a battery-backed open-collector architecture, which provides a read/wire interface. The communication protocol expected by the token has been specified so that the token never sources current to the data line, but only sinks current. The communication protocol also includes time-domain relations which are referenced to a very crude time base in the token, and the system must preserve timing relations which will be satisfied by tokens in which the time base takes on any of the wide range of forseeable speeds. To interface to this protocol, the programmable capabilities of the standard UART chip in the computer's RS232 interface are exploited to provide adaptation to ...

METHOD AND APPARATUS FOR CONTROLLING WRITING TO MEMORY

The invention relates to a method and apparatus for controlling writing to a memory. The apparatus comprises control means (1-8) for the formation of a memory activation signal (C(Boolean not)E(Boolean not)) in response to the applying of a predetermined key code to the control means, the control means comprising timer means (2) which are started by applying the key code and which prevent the formation of the memory activation signal (C(Boolean not)E(Boolean not)) when a predetermined time has elapsed from the applying of the key code. In order to speed up the writing of long data blocks into a memory, the invention is characterized in that the control means further comprise means (3, 5, 6) for restarting the time means (2) within a predetermined time interval from the applying of the key code or the previous memory write operation as a result of a performed memory write operation.

ЗАЩИЩЕННОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО, ИМЕЮЩЕЕ ЗАЩИТУ ОТ ПЕРЕХВАТА

Изобретение относится к защищенным запоминающим устройствам и может быть использовано, в частности, для обеспечения протокола аутентификации для защиты от перехвата и набора паролей для считывания и записи в области памяти защищенного запоминающего устройства пользователем. Его использование позволяет получить технический результат в виде обеспечения аутентификации интеллектуальной карточки и устройства считывания карточек друг с другом с помощью криптографии и/или паролей без использования микропроцессора в интеллектуальной карточке для предотвращения перехвата. Технический результат достигается за счет того, что обеспечивается аутентификация как интеллектуальной карточки, так и устройства считывания карточек, причем криптография обеспечивает только определенное число попыток аутентификации, при этом только предварительно выбранное число попыток при аутентификации, если не произошло обнуление перед тем, как окончательно запретить доступ в интеллектуальную карточку. 2 с. и 12 з.п.ф-лы, ...

УСТРОЙСТВО ПРЕДОТВРАЩЕНИЯ НЕСАНКЦИОНИРОВАННОГО ДОСТУПА, АУДИТ БЕЗОПАСНОСТИ ПРИ ЛИКВИДАЦИИ ЗАЩИТЫ ПРОГРАММЫ КОМПЬЮТЕРА

Устройство предотвращения несанкционированного доступа при ликвидации защиты программы компьютера путем проверки некоторых регистров центрального вычислительного устройства правомерности выполняемых операций при инициализации в режиме отладки под управлением утилиты отладчика, в режиме работы, отличающееся тем, что для расширения функциональных возможностей за счет предотвращения несанкционированного доступа при ликвидации защиты программы, отдельных ее модулей дополнительно вводится модуль прерывания доступа к программе, модуль разделения процедур по проверке целостности данных, модуль процедур изменения данных, модуль аудита безопасности событий и выполняется интеграция данных модулей.

СПОСОБ ПРЕДОТВРАЩЕНИЯ НЕСАНКЦИОНИРОВАННОГО ДОСТУПА К ПРЕОБРАЗОВАТЕЛЯМ, СИСТЕМЕ УПРАВЛЕНИЯ МОБИЛЬНЫХ УСТРОЙСТВ

Способ предотвращения несанкционированного доступа при возможном считывании информации на этапе получения контрольных значений от первичных, вторичных преобразователей и системы управления мобильным устройством, при инициализации в режиме отладки под управлением утилиты отладчика, в режиме работы, отличающийся тем, что для расширения функциональных возможностей за счет предотвращения несанкционированного доступа на этапе формирования базы данных значений с преобразователей и системы управления мобильным устройством дополнительно вводятся модули контроля транзакций, проверки целостности доменов и промежуточного контроля исполнительных процессов.

Устройство для защиты памяти

Halbleitervorrichtung und Verfahren für die Ablaufverfolgung elnes Speichers einer Halbleitervorrichtung

Verfahren zum Nachverfolgen eines Speichers einer Halbleitervorrichtung (6), wobei der Speicher eine Mehrzahl von Speicherbereichen (2) aufweist, die jeweils eine Mehrzahl von Bit umfassen, wobei die Halbleitervorrichtung (6) ferner einen Etikettspeicher umfasst, der eine Mehrzahl von Nachverfolgungsetiketten (4) umfasst, wobei jedes Nachverfolgungsetikett (4) wenigstens ein Bit umfasst, wobei das Verfahren die folgenden Schritte umfasst: a) Abbilden jedes Speicherbereichs (2) des Speichers auf ein Nachverfolgungsetikett (4), das angibt, ob der jeweilige Speicherbereich (2) für die Nachverfolgung ausgewählt ist oder nicht, b) Zugreifen auf jeden Speicherbereich (2) des Speichers und Lesen des zugewiesenen Nachverfolgungsetiketts (4), und c) Erfassen von Daten der Speicherbereiche, falls das zugewiesene Nachverfolgungsetikett (4) angibt, dass der Speicherbereich (2) für die Nachverfolgung ausgewählt ist, und d) Verwerfen von Daten der Speicherbereiche (2), falls das zugewiesene Nachverfolgungsetikett ...

Access control in a non-volatile semi-conductor memory

In a nonvolatile semiconductor memory device comprising word lines WL bit lines BL, sense lines SL, memory cells CE, column selecting transistors CT, a page buffer 38, data lines DL0 to DLn, an input driver/sense amplifier 34, an input buffer 30, an input/output register 32 and a comparator 36, a secret access code is stored by first latching it in the page buffer 38, comparing in comparator 36 a second secret access code input by way of the input buffer 30 with the first secret access code read byte-wise from the page buffer by the input/output register 32, and if the first and second access codes match, writing the first secret access code in a predetermined row 42 of the memory cells. ...

PREVENTION OF INSPECTION OF SECRET DATA STORED IN ENCAPSULATED INTEGRATED CIRCUIT CHIP

MEMORY DEVICE, MEMORY ADDRESS DECODER, SYSTEM AND RELATED METHOD FOR MEMORY ATTACK DETECTION

A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding pathconfigured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from themultiple stages indicative of a fault along the decoding path ...

PROCESS OF PROTECTION OF NONVOLATILE STORAGE AREAS

DISPOSITIF DE PROTECTION D'UNE MEMOIRE MORTE EFFACABLE ET REPROGRAMMABLE

L'INVENTION CONCERNE UN DISPOSITIF DE PROTECTION D'UNE MEMOIRE 1 MORTE EFFACABLE ET REPROGRAMMABLE, QUI COMPORTE UNE CELLULE MEMOIRE 6 ET DES MOYENS D'ECRITURE ET DE LECTURE DE LA CELLULE 6 PERMETTANT DE PROGRAMMER CETTE CELLULE A UN ETAT DETERMINE, LA PROGRAMMATION DE CETTE CELLULE PERMETTANT D'EMPECHER TOUTE REPROGRAMMATION DE LA MEMOIRE SANS EFFACEMENT PREALABLE DE LA CELLULE. APPLICATION AUX MEMOIRES MORTES EFFACABLES ET REPROGRAMMABLES.

SEMICONDUCTOR MEMORY DEVICE HAVING DELAY PULSE GENERATION CIRCUIT

PURPOSE: A semiconductor memory device having a delay pulse generation circuit is provided, which can operate a memory core block with the same condition without a delay time difference between internal clock signals during a high speed operation and a direct accessing operation. CONSTITUTION: The semiconductor memory device(300) comprises a logic circuit part(310), a DA(Direct Accessing) part(320), a memory core block(330) and a delay pulse generation circuit(340). The logic circuit part operates by external clock signals and controls a high speed operation of the memory device. The DA part operates the memory core block at a low speed. The memory core block reads or program data of a memory cell by internal clock signals generated by the logic circuit part or the DA part. The delay pulse generation circuit part generates a delay time difference of the internal clock signals as a pulse signal(PUL). The pulse signal is transmitted to a pad and an interval of the pulse signal can be measured ...

Semiconductor memory device

The semiconductor memory device is provided with an address buffer. The address buffer includes address input circuits provided for respective bits of an address signal. Each address input circuit includes an address signal transmission circuit that is activated by an activation signal, a plurality of delay circuits provided in parallel, each delaying and outputting the output of the address signal transmission circuit, and a delay time select circuit that selects an output signal from one of the plurality of delay circuits according to the type of access and transmits the selected signal to an address decoder. Each of the plurality of delay circuits has a delay time different from each other. If an access is started with activation of the address buffer, a delay time that is shorter than a conventional case is set.

SYSTEMS WITH DATA-TOKEN/ONE-WIRE-BUS

A low-power CMOS memory (0130) is packaged in a very compact and economical electronic data module (0100) (a ''data token''), which includes battery backed memory. The module (0100) is preferably coin-shaped, with two faces of the module being isolated from each other. Preferably a two-part metal container (0100) is used, which has two shallow concave pieces (0100A and 0100B) which fit together. An integrated circuit (0130) is mounted on a very small flexible printed circuit board (0100), which fits inside the container (0100). Conductive elastic material (0140) (such as plastic foam) is used to mount the board (0120) inside the container. The memory (0130) itself preferably uses a low-voltage low-power CMOS architecture without sense amplifiers, in which the selected cell drives full logic levels onto its bitline pair, and only one line of the bitline pair is connected to the following logic stage. Preferably bitline precharge transistors are connected to always pull up any unselected ...

Secure memory having anti-wire tapping

According to a first aspect of the present invention, cryptography without a dedicated microprocessor on the smart card is employed to provide authentication of both the smart card and the smart card reader, and wherein the cryptography provides only a preselected number of attempts at authentication, if not reset, before access to the smart card is denied permanently. According to a second aspect of the present invention, access to each the memory zones of the smart card may be individually provided by cryptography, passwords or both.

Architecture modification for improved ROM security

A technique of modifying a ROM mask to prevent external access of internal memory of an integrated circuit device. Patterns in the ROM mask are altered to permit implantation of components of a driver circuit such that these driver circuits are disabled. Disabling of the driver circuit prevents control signals from permitting external access of internal memory, therein allowing copy protection of the contents of the internal memory.

One-wire bus architecture

A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to a data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from the host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read. Thus, the ...

Electrostatic discharge protection systems and methods for electronic tokens

A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to the data line, of the one-wire bus but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from the host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read. Thus, ...

Programmable memory and cell

An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.

Nanoscale interconnection interface

One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2^k or fewer nanowires, employing supplemental, internal address lines to map 2^k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2^k nanowires, with n>k, using 2^k, well-distributed, n-bit external addresses to access the 2^k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, ...

INTEGRATED CIRCUIT DEVICE AND OPERATING METHOD OF INTEGRATED CIRCUIT DEVICE

Described herein is an integrated circuit device includes a shuffler, a logic unit and registers each including two or more bit storages. The shuffler receives an address indicating one of the registers and data bits, selects target bit storages at which the data bits are to be stored from among bit storages of the registers depending on a shuffle configuration and the address, stores the data bits into the target bit storages, and transfers the data bits from the target bit storages depending on the shuffle configuration. The logic unit receives the data bits transferred from the shuffler and operates using the received data bits. The shuffle configuration is adjusted when a reset operation is performed.

SECURE MODULE WITH MICROPROCESSOR AND CO-PROCESSOR

The present invention relates to an electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. More specifically, the present invention relates to an electronic module which includes an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token-sized metallic container. The present invention will preferably communicate via a single wire data bus which uses a one-wire protocol.

INTEGRATED CIRCUIT USING PROGRAMMABLE FUSE ARRAY

PROBLEM TO BE SOLVED: To disclose an integrated circuit IC to make an objective circuit by using the array of an electrically programmable fuse. SOLUTION: The IC includes the array 14 of data cells arranged to a plurality of rows and a plurality of columns. Each data cell includes the electrically programmable fuse 40. When a current route is not physically changed, each fuse 40 includes the current route to impart a first digital state. When it is destroyed, each fuse 40 includes the current route to impart a second digital state. Each row in a plurality of the rows includes at least one cell in order to give a row protection designator selected from a group constituted of reading protection and writing protection. The IC includes a control circuit 12 to selectively destroy the fuse 40 in the cell selected from the data cells in a programming control mode and to read out the cell selected from the data cells in a reading mode. COPYRIGHT: (C)2004,JPO&NCIPI ...

DATA SECURITY DEVICE AND METHOD

PROBLEM TO BE SOLVED: To provide a data security device for achieving the facilitation of the check of write contents while maintaining the security of the write contents. SOLUTION: After write to a P-ROM(programable ROM) 4, a switching circuit 14 is opened and an internal bus 16 and an external bus are cut off. That is, the contents of the P-ROM 4 can not be read. In order to read the contents of the P-ROM 4, a protection cancellation terminal 24 is turned to 'H'. Thus, the switching circuit 14 is conducted and read is made possible. However, simultaneously, signals are supplied to an elimination signal generation circuit 8 as well and the contents of a selected part are eliminated by an elimination selection switch 6. Since all the programs of the P-ROM 4 are not read, practical secrecy is maintained. Also, for the part other than the eliminated part, the accuracy of the write can be checked. COPYRIGHT: (C)1997,JPO ...

МЕХАНИЗМ ОСУЩЕСТВЛЕНИЯ ПОЛИТИКИ И СПОСОБЫ И СИСТЕМЫ ДЛЯ ЗАЩИТЫ ДАННЫХ

... 1. Способ, содержащий этапы, на которых устанавливают действие, предназначенное для выполнения над данными, полученными из источника данных; извлекают политики контента, связанные с данным действием; ранжируют политики в ранжированном порядке; осуществляют запрос, поддерживаются ли отдельные политики потребителем данных; и управляют потребителем данных для реализации одной из ранжированных политик, поддерживаемых потребителем данных. 2. Способ по п.1, дополнительно содержащий применение отдельной политики. 3. Способ по п.1, дополнительно содержащий установление доверительных отношений между источником данных и компонентом, который выполняет указанный этап управления. 4. Способ по п.1, дополнительно содержащий подтверждение того, что потребитель данных реализовал указанную одну политику, и затем разрешение потребителю данных получить доступ к данным для выполнения указанного действия. 5. Способ по п.1, в котором указанный этап установления содержит установление действия, предназначенного ...

СИСТЕМА ДОСТУПА К ИНФОРМАЦИИ

Изобретение относится к железнодорожной автоматике и используется в управлении транспортными средствами. Технический результат - повышение эффективности системы защиты информации, хранящейся в ЭВМ. За счет введения новых блоков, а также новых связей между функциональными узлами обеспечивается возможность введения многоуровневой проверки санкционированного доступа к информации, регистрация обращения пользователей к тем или иным зонам памяти, многоуровневый доступ к информации в зависимости от кода пароля пользователей, обеспечивается возможность стирания информации в оперативном запоминающем устройстве после завершения работы пользователя с информацией с тем, чтобы последующий пользователь не смог бы воспользоваться информацией в оперативном запоминающем устройстве, оставшейся от работы предыдущего пользователя, имеющего более высокий уровень доступа к информации. Обеспечивается возможность самотестирования устройства съема информации с электронного ключа. 2 з.п.ф-лы, 1 ил.

Устройство для защиты памяти

УСТРОЙСТВО ДЛЯ ЗАЩИТЫ ИНФОРМАЦИИ В БЛОКЕ ОПЕРАТИВНОЙ ПАМЯТИ

Halbleiterspeicheranordnung, Steuerungsanordnung und elektronisches Gerät

FRAUD-SAFE PACKING

MEMORY CARD FILE SYSTEM INTEROPERABILITY SUPPORTS

PREVENTION OF THE INSPECTION INTO SECRET DATA, WHICH ARE STORED IN AN INTEGRATED CIRCUIT CHIP

SEMICONDUCTOR MEMORY DEVICE

MEMORY CARD WITH SUPPORTED FILE SYSTEM INTEROPERABILITY

A METHOD AND APPARATUS FOR INVALIDATING MEMORY ARRAY WRITE OPERATIONS

PREVENTION OF ALTERATION OF DATA STORED IN SECURE INTEGRATED CIRCUIT CHIP MEMORY

MEANS AND METHOD FOR DISABLING ACCESS TO A MEMORY

ACCESS CONTROL TO A MEMORY DEVICE USING ALIAS ADDRESS

STORAGE Of an IMMUTABLE BINARY CODE IN an INTEGRATED CIRCUIT

L'invention concerne un circuit (1) de stockage d'un code binaire (B1 , B2 ,..., B i-1 , B i ,..., Bn-1 , Bn) dans une puce de circuit intégré, comportant une borne (2) d'entrée d'application d'un signal (E) de déclenchement d'une lecture du code, des bornes (31 , 32 , 3 i-1 , 3 i ,... 3n-1 , 3n) de sortie propres à délivrer ledit code binaire, des premiers chemins électriques (P1 , P2 ,..., P i ,..., Pn) reliant individuellement ladite borne d'entrée à chaque borne de sortie, chaque chemin apportant un retard fixé à la fabrication du circuit intégré, et des moyens (4, 51 , 52 ,... 5 i, 5n) de prise en compte simultanée des états binaires présents en sortie des chemins électriques.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH COPY PREVENTION FUNCTION

Method for preventing non-volatile memory of System-on-Chip from being copied

A method for preventing non-volatile memory of System-on-Chip from being copied comprises (a) inputting a write address signal into a write address logic; (b) determining the write address signal as a relative low value or a relative high value of specific address range, to generate a selection code signal; (c) inputting the selection code signal into a multiplexer; (d) inputting random number signal created by a random number generator into the multiplexer; and (f) inputting the random number signal into the non-volatile memory to write into the specific address range of the nonvolatile memory.

TAMPER-RESISTANT PACKAGING AND APPROACH

A tamper-resistant packaging approach protects non-volatile memory (108). According to an example embodiment of the present invention, a package (106) having a plurality of magnetic particles (120-125) therein is arranged with an integrated circuit device (100) to cause a plurality of magnetically-responsive circuit nodes (130-134) to take on magnetic states. Each magnetic state is detected as a logic state, and then compared with a real-time logic state of the magnetically-responsive circuit nodes and, in response to a stored logic state being different from a real-time logic state, package tampering is detected. In one instance, tampering is detected when the magnetic state of one of the magnetically-responsive circuit nodes is altered as a portion of the package is removed. The detected tampering may alter a characteristic of the integrated circuit, such as by altering stored data or setting a tamper flag that indicates the package has been tampered with.

Memory data protection circuit

A memory data protection circuit is provided on a one-chip microcomputer having a CPU, ROM, volatile memory, and nonvolatile memory which together with an input/output control circuit are connected to each other via a first bus line. A security flag storage circuit receives a security flag consisting of a plurality of bits. In one state the security flag cannot be rewritten once it has been written. A security flag monitor circuit reads the security flag and when receiving the power-on reset signal recognizes the flag contents. A bus line control circuit controls the connections of the first bus line, a second bus line connected to the ROM, and a third bus line connected to a test-only memory in response to the security flag monitor circuit When the security flag indicates test mode before shipment, the bus line control circuit controls connections so a shift to the test mode may be possible; when it indicates normal operation mode after shipment, a shift to the test mode may be impossible ...

Secure circuit structure

Parasitically powered microprocessor capable of transmitting data over a single data line and ground

An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.

TAMPER RESISTANT FUSE DESIGN

IDENTIFICATION OF AN INTEGRATED CIRCUIT FROM ITS PHYSICAL MANUFACTURE PARAMETERS

УСТРОЙСТВО ДЛЯ ДОСТУПА К КОНФИДЕНЦИАЛЬНОЙ ИНФОРМАЦИИ

Устройство для доступа к конфиденциальной информации, содержащее разъем повышенной долговечности, микроконтроллер с модулем светодиодной индикации подключения к электронному порту и блок памяти, контакты разъема повышенной долговечности подключены через микроконтроллер к блоку памяти, отличающееся тем, что содержит модуль светодиодной индикации факта автоматического удаления использованного случайного шифрующего ключа, подключенного входами и выходами к микроконтроллеру, при этом гнездо разъема повышенной долговечности выполнено по индивидуальной схеме расположения выступов.

Verfahren zum Schützen nichtflüchtiger Speicherbereiche

Integrated circuit

METHOD AND APPARATUS FOR CONTROLLING WRITING TO MEMORY

PREVENTION OF INSPECTION OF SECRET DATA STORED IN ENCAPSULATED INTEGRATED CIRCUIT CHIP

PREVENTION OF INSPECTION OF SECRET DATA STORED IN ENCAPSULATED INTEGRATED CIRCUIT CHIP

PREVENTION OF INSPECTION OF SECRET DATA STORED IN ENCAPSULATED INTEGRATED CIRCUIT CHIP

An integrated circuit chip includes a secure memory element that stores secret data, an opaque layer of material encapsulating the chip, and means for eliminating the secret data from the secure memory element in the event that the encapsulation material is removed from the chip. The eliminating means comprise a protective circuit encapsulated by the encapsulation material and coupled to the secure memory element. The protective circuit includes a light sensitive element having a current characteristic that has a detectable change upon exposure to light; means for detecting said current change when the light sensitive element is exposed to light; and switching means coupled to the secure memory element and the detecting means forcausing the secret data to be removed from the secure memory element in response to said current change produced by the light sensitive element when the light sensitive element is exposed to light, such that should the encapsulation material be removed from the ...

PREVENTION OF ALTERATION OF DATA STORED IN SECURE INTEGRATED CIRCUIT CHIP MEMORY

PREVENTION OF ALTERATION OF DATA STORED IN SECURE INTEGRATED CIRCUIT CHIP MEMORY An integrated circuit chip in which alteration of secure data stored in a predetermined location of a memory on the chip may be prevented. In one embodiment, the chip includes a memory having a plurality of memory locations, with a predetermined location being for the storage or unalterable secure data; a memory control logic circuit coupled to the memory by an address bus for causing data to be stored in locations of the memory indicated by address signals provided on the address bus; a fuse element having an initial state and an irreversibly altered state; means coupled to the fuse element for irreversibly altering the state of the fuse element in response to a predetermined control signal; and a decoder coupled to the fuse element, the memory control circuit and the address bus for monitoring the state of the fuse element and said address signals, and for preventing the memory control circuit from causing ...

Mobile terminal, memory card socket and method of writing protection for memory card in the mobile terminal

The present invention provides a mobile terminal, a memory card socket and a method of writing protection for a memory card in the mobile terminal. The mobile terminal comprising a memory card socket accommodating a pluggable memory card, the memory card socket externally provided with a metal shielding structure; the mobile terminal further comprising: a touch capacitance sensor connected to the metal shielding structure of the memory card socket and configured to sense a capacitance via the metal shielding structure; and a write control unit configured to determine whether the metal shielding structure is touched by a finger based on the capacitance sensed by the touch capacitance sensor, and prohibit data being written into the memory card when it is determined that the metal shielding structure is touched by a finger. The present invention ensures that the data can be safely written into the memory card.

Method for discharging a voltage from a capacitance in a memory device

In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by an architecture of the discharge circuit.

Nonvolatile Memory And Writing Method Thereof, And Semiconductor Device

A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit. 1. A memory device comprising: a plurality of first memory cells; and', 'at least one second memory cell; and, 'a memory cell array comprisinga circuit for writing data to the plurality of first memory cells and the second memory cell,wherein, when the writing of the data to one of the plurality of first memory cells fails, the circuit is arranged to assign an address of the one of the plurality of first memory cells to the second memory cell and write the data to the second memory cell.2. The memory device according to claim 1 , further comprising an antenna which is capable of receiving an electric wave.3. The memory device according to claim 1 , wherein the plurality of first memory cells and the second memory cell are arranged to irreversibly change an electrical resistance thereof when the data is stored therein.4. The memory device according to claim 1 , further comprising a second circuit for confirming whether the data is normally stored in the plurality of first memory cells.5. The memory device according to claim 4 , further comprising a third circuit coupled with and arranged to ...

DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP

A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. 1. A method for clearing a dynamic random access memory (DRAM) at power up , the method comprising the steps of:providing memory cells with a transistor body and a reference voltage connection to the transistor body;generating a boosted voltage during a period after the power up of the DRAM;removing the reference voltage connection to the transistor body;applying the boosted voltage to the transistor body of the memory cells in the DRAM; andallowing capacitors of the memory cells to equalize in voltage to clear data contents of the DRAM.2. The method of further comprising the step of:generating a power on reset (POR) signal on a chip containing the DRAM to generate the period for the boosted voltage.3. The method of further comprising an on chip circuit to provide the POR signal.4. The method of wherein the step of removing a reference voltage connection to the transistor body utilizes a body tie transistor that responds to a boost signal to remove the reference voltage connection between the body of the transistor and a reference voltage to allow the charge pump to provide the boosted voltage to the body of the transistor.5. The method of wherein the boosted voltage is provided by a charge pump.6. The method of wherein the DRAM comprises NFET transistors. ...

Nonvolatile memory device and operating method thereof

Disclosed is a memory system which includes a nonvolatile memory device configured to store data information; and a memory controller configured to control the nonvolatile memory device. The memory controller provides the nonvolatile memory device with a program command sequence including program speed information according to an urgency level of an internally requested program operation.

Repair method and device for abnormal-erase memory block of non-volatile flash memory

A repair method for an abnormal-erase memory block of a non-volatile flash memory is provided. The method includes steps of: sequentially scanning bit data in a page of a block when reading data in a NAND flash; determining whether the page is an abnormal-erase page; setting logic “0” bit data in the page to logic “1” when the page is an abnormal-erase page; and re-erasing the block.

PHYSICAL UNCLONABLE FUNCTION WITH IMPROVED START-UP BEHAVIOR

An electric physical unclonable function (PUF) () is provided comprising a semiconductor memory element () connectable to a PUF control means for reading content from the memory element and for deriving at least in part from said content a digital identifier, such as a secret key. Upon powering the memory element it settles into one of at least two different stable states. The particular stable state into which the memory element settles is dependent at least in part upon random physical characteristics of the memory element introduced during manufacture of the memory element. Settling of the memory element is further dependent upon a control input () of the memory element. The electric physical unclonable function comprises shielding means () for shielding, during a time period including the power-up of the memory element and lasting at least until the settling of the memory element, the control input from receiving control signals upon which the particular stable state into which the memory element settles is dependent. In this way, the dependency of the memory element on its physical characteristics is improved, and dependency on possibly irreproducible control signals is reduced. 119.-. (canceled)22. An electric physical unclonable function as in claim 21 , wherein the interconnected semiconductor gates comprises at least two gates connected in a cross-coupled loop.23. An electric physical unclonable function as in claim 22 , wherein at least one of the two gates connected in the cross-coupled loop is a multiple input gate.24. An electric physical unclonable function as in claim 23 , wherein the memory element is a latch claim 23 , a flip-flop or a register.25. An electric physical unclonable function (PUF) as in claim 20 , wherein the time period lasts at least until the reading of the content of the memory element by the PUF control means.26122. An electric physical unclonable function as in claim 20 , wherein the deriving of the digital identifier depends on ...

Nonvolatile memory device and program method thereof

Disclosed is a nonvolatile memory device which includes a nonvolatile memory including a plurality of LSB and MSB pages at a plurality of wordlines; and a controller controlling the nonvolatile memory. The controller controls the nonvolatile memory such that an LSB program operation on a first wordline (first LSB page) of the plurality of wordlines is programmed and then an LSB program operation on a second wordline of the plurality of wordlines (second LSB page) is programmed. When the LSB program operation on the second wordline (second LSB page) is performed, the nonvolatile memory stores information about LSB data programmed at the first wordline (first LSB page) at a spare area of the second wordline (second LSB page).

Integrated circuit chip and memory device

A memory device includes a pad that provides an interface with an exterior, a first setting unit that generates a termination setting signal for setting the pad for a purpose of termination data strobe using a first specific code of a mode register set operation, a second setting unit that generates a mask setting signal for setting the pad for a purpose of data mask using a second specific code of the mode register set operation, and a third setting unit that generates a write inversion setting signal for setting the pad for a purpose of write data bus inversion using third specific code of the mode register set operation. When a setting signal with a higher priority is activated, a setting signal with a lower priority is deactivated regardless of a value of the corresponding code.

Nonvolatile memory system and related method of preserving stored data during power interruption

A nonvolatile memory system comprises a temporary power supply that supplies power in the event of an unexpected power interruption. The temporary power supply provides power while metadata stored in one or more buffers is compressed and transferred to a nonvolatile memory device.

Memory system generating random number and method generating random number

In a memory of non-volatile memory cells, a random number is generated by programming non-volatile memory cells, reading the programmed non-volatile memory cells using a random number read voltage selected in accordance with a characteristic of the non-volatile memory cells to generate random read data, and generating the random number from the random read data.

Method for dodging bad page and bad block caused by suddenly power off

A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off during NAND flash erasing or programming.

System and Method for Employing Secure Non-Volatile Storage Devices in Gaming Machines

A write-protection system and method for use with a gaming machine. The system having a non-volatile data storage device, an interface device and an electrically conductive connector. The storage device having electronic data storage and a write-protection controller providing a write-protected state and a write-permitting state, the electronic data storage being blocked from receiving electronic write commands in the write-protected state and being able to receive write commands in the write-permitting state. The interface device electrically connecting the data storage device to a power supply and control circuitry of the gaming machine. The interface device connected to the electronic data storage through the controller and the connector. 1. A write-protection system for use with a gaming machine , comprising:a non-volatile data storage device having electronic data storage operatively connected to a write-protection controller, the controller having a control element, associated circuitry and control logic stored on a computer-readable medium for activating a write-protected state and a write-permitting state, in the write-protected state electronic write commands being blocked from being received by the electronic data storage by the controller and in the write-permitting state electronic write commands being able to be received by the electronic data storage;an interface device electrically connecting the data storage device to a power supply and control circuitry of the gaming machine, the interface device connected to the electronic data storage through the controller, andan electrically conductive connector connecting the controller and the interface device, the connector carrying a voltage generated by the power supply.2. The system of where the interface is a serial advanced technology attachment interface.3. The system of where the interface device and storage device have separate connections for the transmission of data and power supplied to the storage ...

STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY

A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information. 1. A stacked memory chip device , comprising:a plurality of stacked memory chips;read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips;data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive data of a particular one of the cache lines is not stored in a same memory chip with the respective substantive data, the information to protect the substantive data of the cache lines being one of mirroring information and ECC information.2. The stacked memory chip device of where the information is to be stored at row/column granularity.3. The stacked memory chip device of where the information is to be stored at bank granularity4. The stacked memory chip device of wherein the information is to be stored in a region of the plurality of memory chips that is reserved for storage of respective information to protect respective substantive data of multiple cache lines.5. The stacked memory chip device of wherein the information is ...

MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE DEVICE AND CONTROL METHOD THEREOF

A control method of a memory storage device is provided and includes: detecting a first signal stream controlled by a host system; executing a boot code according to the first signal stream and entering a boot code mode; and receiving a command from the host system in the boot code mode and not executing a firmware code stored in a rewritable non-volatile memory module in the memory storage device. According, operational flexibility of the memory storage device may be enhanced. 1. A memory control circuit unit configured to control a memory storage device , the memory control circuit unit comprising:a host interface, configured to be coupled to a host system;a memory interface, configured to be coupled to a rewritable non-volatile memory module of the memory storage device;a signal detection circuit; anda memory management circuit, coupled to the host interface, the memory interface, and the signal detection circuit,wherein the signal detection circuit is configured to detect a first signal stream controlled by the host system,wherein the memory management circuit is configured to execute a boot code according to the first signal stream and enter a boot code mode,wherein the memory management circuit is further configured to receive a command from the host system in the boot code mode and not to execute a firmware code stored in the rewritable non-volatile memory module after entering the boot code mode.2. The memory control circuit unit as claimed in claim 1 , wherein the memory management circuit is further configured to establish a connection with the host system in the boot code mode after entering the boot code mode.3. The memory control circuit unit as claimed in claim 1 , wherein the memory management circuit is further configured to load the firmware code from the rewritable non-volatile memory module and attempt to establish a connection with the host system based on an execution of the firmware code before the signal detection circuit detects the first ...

SECURITY DEVICE FOR PREVENTING LEAKAGE OF DATA INFORMATION IN SOLID-STATE DRIVE

Disclosed is a security device for preventing leakage of data information in solid-state drive. The present invention provides the security device for preventing leakage of data information in solid-state drive (SSD), the device enabling a user to electrically destroy flash memory personally to prevent leakage of data stored in the SSD, which is used and is to be waste-processed. 1. A security device for preventing leakage of data information in solid-state drive including: a flash memory for storing data; an data interface for data communication with a host; a device controller controlling data exchange operation between the flash memory and the host via the data interface; and a buffer memory temporarily storing data read out from the flash memory by the device controller and data to be recorded in the flash memory ,wherein the solid-state drive is provided with a high-voltage pulse generator generating and outputting a control gate breakdown voltage (a high-voltage pulse ranging DC 60 V to 240 V) capable of destroying a dielectric layer of a control gate of a flash memory cell when a user operates a switch separately from the device controller;a memory controller of the flash memory provides a voltage selector capable of selecting and inputting the high-voltage pulse from the high-voltage pulse generator to a word line of a flash memory cell array; andwhen the user turns on the switch, the memory controller executes addressing on all word lines and bit lines in sequence and applies the control gate breakdown voltage to the word line of the flash memory cell array.2. The data information leakage prevention security device of claim 1 , wherein the high-voltage pulse generator includes:a DC-DC converter electrically connected to an output side of a power supply of a computer to increase a voltage by receiving a DC power from the power supply;a resistor electrically connected to an output side of the DC-DC converter to adjust an output current from the DC-DC ...

Control circuit of semiconductor device and semiconductor memory device

A control circuit includes a ROM suitable for generating ROM data based on a ROM address corresponding to a predetermined operation, a command analyzing unit suitable for outputting the ROM address corresponding to the predetermined operation, generating an address storing signal in response to an operation suspension command for suspending the predetermined operation, and generating an address output signal in response to an operation resumption command for resuming the predetermined operation, an address storing unit suitable for storing a ROM address, which corresponds to the ROM address at a time point where the predetermined operation is suspended, in response to the address storing signal, and an address output unit suitable for outputting the ROM address corresponding to said time point in response to the address output signal, wherein the ROM generates ROM data for resuming the predetermined operation based on the ROM address corresponding to said time point.

Write protection circuit for memory and display apparatus

A write protection circuit for memory and a display apparatus are provided. The write protection circuit includes an interference signal absorbing circuit connected with a data writing triggering terminal to absorb a first level signal when the receiving of the first level signal by the data writing triggering terminal is detected.

PROTECTION CIRCUIT OF MEMORY IN DISPLAY PANEL AND DISPLAY APPARATUS

Disclosed is a protection circuit of a memory in a display panel. The circuit includes: a timing controller (), for outputting a first control signal; a memory (), for storing software data of the timing controller (); a power supply circuit (), for outputting a power signal; and a monitor circuit (), having three input ends and a signal output end, two input ends being respectively connected to the power supply circuit () and a control signal output end, and the other one input end being input with a write control signal; the monitor circuit () controls the memory () to be in a write protection state when in a normal state, and controls the memory () to be in a write enable state when a level state collection of the power signal, the first control signal, and the write control signal satisfies a preset level state collection. 1. A protection circuit of a memory in a display panel , comprising:a timing controller, having a signal transmission end and a control signal output end, the timing controller being configured to output a first control signal of high/low level;a memory, having a signal transmission end and a write protection control end, the signal transmission end of the memory being connected to the signal transmission end of the timing controller; the memory being configured to store software data of the timing controller;a power supply circuit, being configured to output a power signal; anda monitor circuit, having a first input end, a second input end, a third input end, and a signal output end, the first input end being connected to the power supply circuit, the second input end being connected to the control signal output end, the third input end being configured to be input with a write control signal, and the signal output end being connected to the write protection control end;wherein the monitor circuit is configured to:output a write protection signal when in a normal state, to control the memory to be in a write protection state; andoutput a ...

PHYSICAL UNCLONABLE FUNCTION FOR NON-VOLATILE MEMORY

A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port. 1. A method for generating a data set for storage on a memory , comprising:generating, by a first circuit, first level security information having N bits of data, N being an integer greater than 1;generating, by a second circuit, second level security information having M bits of data, the second level security information being generated as a function of the N bits of data of the first level security information, M being an integer that is less than N; andstoring the second level security information in the memory as the data set.2. The method of claim 1 , wherein the first circuit is a random number generator and the N bits of data of the first level security information are obtained from a randomly generated number.3. The method of claim 2 , wherein the random number generator is a physical unclonable function (PUF) circuit and the N bits of data of the first level security information are obtained using the randomly generated number and programmable memory cells of the PUF circuit.4. The method of claim 1 , wherein the function used to generate the second level security information is a hash function.5. The method of claim 4 , wherein the second circuit applies the hash function to the first level ...

PHYSICAL UNCLONABLE FUNCTION USING DIVIDED THRESHOLD DISTRIBUTIONS IN NON-VOLATILE MEMORY

A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port. 1. A method for generating a data set on an integrated circuit including a set of programmable memory cells , comprising:exposing the set of programmable memory cells having addresses on the integrated circuit to a process inducing variant thresholds in members of the set within a starting distribution of thresholds;finding a first dividing line and a second dividing line different than the first dividing line, in the starting distribution;identifying a first subset of the set of programmable memory cells having thresholds below the first dividing line in a first part of the starting distribution, and a second subset of the set of programmable memory cells having thresholds above the second dividing line in a second part of the starting distribution; andgenerating the data set using addresses of at least one of the first and second subsets.2. The method of claim 1 , wherein said generating the data set includes using the addresses to select memory cells in said at least one of the first and second subsets; andreading the programmable memory cells in the set using a read voltage between the first and second dividing lines.3. The method of claim 1 , wherein said generating the data set includes ...

NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING

A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block. 1. A method of operating a non-volatile memory device , the method comprising:upon initiating operation of the non-volatile memory device, reading control information from an information block in the non-volatile memory device, and reading lock information from an additional information block in the non-volatile memory device;determining whether a secure block of the non-volatile memory device will be locked in response to the lock information;upon determining that the secure block will be locked, generating a lock enable signal associated with the secure block that inhibits access to data stored in the secure block, and also activating a read-only enable signal associated with the additional information block that prevents change in the data stored in the additional information block.2. The method according to claim 1 , further comprising:upon determining that the secure block will not be locked, performing at least one of a read operation, a program operation, and an erase operation on the secure block.3. The method according to claim 1 , wherein the information block and the additional information block are separate and distinctly addressable regions within a memory cell array of the non-volatile memory device.4. The method of claim 1 , wherein the non-volatile memory comprises a row decoder that receives an address claim 1 , and the method further comprises:applying the lock enable signal to the row decoder to prevent selection of any word line in the secure block during any data access operation.5. The method of claim 4 , further ...

Memory Controllers and User Systems Including the Same

A user system is provided including a plurality of flash memory devices and a memory controller connected to the flash memory devices through a plurality of channels. The memory controller includes a voltage regulator configured to supply a power of the flash memory devices and a compensation unit configured to supply an additional power to the flash memory devices when a power required by the flash memory devices exceeds a predetermined level. The compensation unit includes a resistor unit connected to an output terminal of the voltage regulator and input terminals of the flash memory devices and a charging unit connected to input terminals of the flash memory devices. The charging unit is configured to supply an additional power to the flash memory devices according to voltages of input terminals of the flash memory devices.

AUTHENTICATION LOGGING USING CIRCUITRY DEGRADATION

Apparatuses and methods related to logging failed authentication attempts. Failed authentication attempts can be logged in the circuitry by degrading the circuitry. The degradation can signal a fail authentication attempt while an amount of the degradation can represent a timing of the error. 1. An apparatus , comprising:a memory array;peripheral circuitry coupled to the memory array and comprising a command decoder configured to receive a trigger to perform an authentication sequence;a first portion of the peripheral circuitry coupled to the memory array and configured to, responsive to receipt of the trigger, perform the authentication sequence; anda second portion of the peripheral circuitry coupled to the memory array and configured to, responsive to an error of the authentication sequence, log the error of the authentication sequence in circuitry by degrading one or more components in the second portion of the circuitry.2. The apparatus of claim 1 , wherein the second portion of the peripheral circuitry comprises one or more components configured to degrade based at least in part on the error of the authentication sequence and a time associated with the error.3. The apparatus of claim 2 , wherein the second portion of the peripheral circuitry comprises a voltage regulator configured to shift a threshold voltage of the circuitry.4. The apparatus of claim 2 , wherein a shift in the threshold voltage identifies the error and the shift identifies a particular authentication sequence that experienced the error.5. The apparatus of claim 1 , wherein the first portion of the peripheral circuitry comprises logic configured to perform the authentication sequence to authenticate a process executed by a processing resource.6. The apparatus of claim 1 , wherein the first portion of the peripheral circuitry comprises logic is configured to perform the authentication sequence to unlock the apparatus.7. The apparatus of claim 1 , further comprising at least one of a ...

SEMICONDUCTOR MEMORY DEVICE FOR PSEUDO-RANDOM NUMBER GENERATION

According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value. 1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells;a random number generation circuit configured to generate a random number; anda controller configured to control the memory cell array and the random number generation circuit,wherein the random number generation circuit includes:a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter; anda pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.2. The device of claim 1 , wherein the random number control circuit includes:a control parameter generation circuit configured to generate the control parameter; andan accumulation circuit configured to generate the seed value by executing an accumulation process on read-out data of the memory cell, which is input.3. The device of claim 2 , wherein the control parameter generation circuit includes:an address setting circuit configured to receive a random number generation trigger signal from the controller, and to generate a control parameter of an address at a time of reading out data from the memory cell array, by using an output value of the pseudo-random number generation circuit; anda ...

Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains

Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected. 1. A computer system , comprising:a memory configured to at least store instructions of routines of a predefined set of domains;a processor coupled with the memory; anda memory management unit coupled between the processor and the memory, wherein the memory management unit is configured to manage a page table containing a page table entry that includes a permission bit for a type of memory access for each of the domains in the predefined set;wherein the memory management unit is configured to map a virtual memory address to a physical memory address using the page table entry during an execution of a routine that is in a first domain;wherein the memory management unit is further configured to control, in accordance with a respective permission bit for the first domain, a memory access of the type in response to an instruction of the routine causing the processor to use the virtual memory address to access the physical memory address.2. The computer system of claim 1 , wherein the page table entry includes a base for a page of physical addresses.3. The computer system of claim 2 , wherein the memory management unit is configured to combine the base and an offset specified in the virtual memory address to generate the physical address.4. The computer system of claim 3 , wherein the predefined set of domains comprises at least one of a domain for hypervisor claim 3 , a domain for operating ...

SEMICONDUCTOR DEVICE AND SECURITY SYSTEM

A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion. 1. A semiconductor device comprising:a unique-information generation portion operating in a plurality of operation environments to generate unique information, wherein the unique information comprises stable information and unstable information, the stable information is the constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments;a detection portion detecting the unstable information;a memory portion storing the unique information and identification information for identifying the unstable information; anda readout portion reading out the unique information and the identification information and outputting the unique information and the identification information to an external portion.2. The semiconductor device according to claim 1 , further comprising:an erasing portion deleting the unique information and the identification information which are stored in the memory portion.3. The semiconductor device according to claim 2 , wherein the erasing portion deletes the unique ...

PUF APPLICATIONS IN MEMORIES

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

SHUT-OFF MECHANISM IN AN INTEGRATED CIRCUIT DEVICE

Described herein are technologies related to self-disabling feature of a integrated circuit device to avoid unauthorized access to stored data information 1. An integrated circuit (IC) device comprising:a sensor configured to measure a signal;a control unit configured to process the measured signal and provide a triggering signal based upon the measured signal;a high-surge voltage component coupled to the control unit, the high-surge voltage component configured to provide a voltage based upon the triggering signal, wherein the provide voltage is greater than a voltage threshold of a storage component in the IC device, the voltage threshold includes a maximum voltage of operation of the storage component;2. The IC device as recited in claim 1 , wherein the sensor is a dosimeter that is configured to measure amount of radiation exposure of the IC device.3. The IC device as recited in claim 1 , wherein the sensor is an ohm meter that is configured to measure total resistance in a circuitry of the IC device.4. The IC device as recited in claim 1 , wherein the measured signal includes measured biometric identification signals.5. The IC device as recited in claim 1 , wherein the control unit is configured to generate one or more of a remote triggering signal claim 1 , a local software triggering signal claim 1 , or a local hardware triggering signal.6. The IC device as recited in claim 1 , wherein the high-surge voltage component includes one or more of a charged capacitor or a voltage supply that is configured to generate the supplied voltage that is above the threshold voltage of the storage component.7. The IC device as recited in claim 1 , wherein the high-surge voltage component includes a charged capacitor that is configured to generate the supplied voltage when a wireless device is powered OFF.8. A wireless device comprising: The IC device as recited in .9. The IC device as recited in further comprising a micro electro mechanical system (MEMS) coupled to the ...

Protection against side-channel attacks on non-volatile memory

A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.

Latch control signal generation circuit and semiconductor devices

A semiconductor device may be provided. The semiconductor device may include a latch control signal generation circuit configured to compare a count signal counted according to the number of times that a command is inputted to the latch control signal generation circuit with a random signal having a random combination to generate a latch control signal which is enabled, based on an update signal. The semiconductor device may include a storage circuit configured to latch an address to generate a latched address, based on the latch control signal. The semiconductor device may include an internal circuit configured to receive the latched address to execute an internal operation.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to the embodiment includes a memory cell array including memory cells; and a data write unit, the memory cells including a first selected memory cell defined for a memory cell targeted to data write, a second selected memory cell defined for a memory cell targeted to the data write next to the first selected memory cell, and non-selected memory cells defined for other memory cells, and the data write unit, at the time of write operation to the first selected memory cell, providing the second selected memory cell with a first non-selection electric pulse having electric energy within a range causing no change in the physical state of a memory element, and providing the non-selected memory cells with a second non-selection electric pulse having smaller electric energy than the first non-selection electric pulse.

POWER DELIVERY CIRCUITRY

A memory device may include one or more circuit boards. Additionally, memory circuitry and an energy storage device may be disposed on the one or more circuit boards. The energy storage device may supplant or supplement an external power source, for example, when power of the external power source is eliminated or insufficient. 1. A memory device comprising:one or more circuit boards;memory circuitry disposed on the one or more circuit boards; andan energy storage device disposed on the one or more circuit boards, wherein the energy storage device is configured to supplant or supplement an external power source configured to provide power to the memory circuitry.2. The memory device of claim 1 , comprising power delivery circuitry configured to regulate power from the external power source to the memory circuitry and to regulate power from the energy storage device to the memory circuitry.3. The memory device of claim 2 , wherein a first electrical connection of the energy storage device is configured to be switched between a reference voltage and an output voltage of the power delivery circuitry.4. The memory device of claim 2 , wherein the power delivery circuitry comprises a buck mode DC to DC converter.5. The memory device of claim 1 , wherein the energy storage device is configured to supplement the external power source in response to an increased power demand of the memory circuitry.6. The memory device of claim 5 , wherein the increased power demand is associated with an increased performance of the memory circuitry.7. The memory device of claim 6 , wherein the increased performance comprises a reduction in latency.8. The memory device of claim 5 , where in the energy storage device is configured to supplement at least 25 milliwatts (mW) of power.9. The memory device of claim 1 , comprising a serial advanced technology attachment (SATA) interface configured to transmit memory data between an external system and the memory circuitry.10. The memory device of ...

NONVOLATILE MEMORY DEVICES AND SOLID STATE DRIVES INCLUDING THE SAME

A nonvolatile memory device includes a memory cell array, a voltage generator, and a control circuit. The voltage generator generates word-line voltages to be applied to the memory cell array. The control circuit generates control signals that control the voltage generator in response to a command and an address. The control circuit includes a hacking detection circuit. The hacking detection circuit disables an operation of the nonvolatile memory device when a hacking is detected, wherein the hacking is detected when an access sequence of the command and the address does not match a standard sequence of the nonvolatile memory device a consecutive number of times. 1. A nonvolatile memory device , comprising:a memory cell array;a voltage generator configured to generate word-line voltages to be applied to the memory cell array; anda control circuit configured to generate control signals that control the voltage generator in response to a command and an address,wherein the control circuit includes a hacking detection circuit configured to disable an operation of the nonvolatile memory device when a hacking is detected, wherein the hacking is detected when an access sequence of the command and the address does not match a standard sequence of the nonvolatile memory device a consecutive number of times.2. The nonvolatile memory device of claim 1 , wherein the hacking detection circuit comprises:an access sequence analyzer configured to analyze the access sequence and to output a decision signal that is enabled when the access sequence does not match the standard sequence;a counter configured to count the decision signal that is enabled and to output a counting signal; anda hacking detection signal generator configured to receive the counting signal and to output a hacking detection signal that is enabled when the counting signal exceeds a reference value.3. The nonvolatile memory device of claim 2 , wherein the access sequence analyzer is configured to output the ...

INTEGRATED CIRCUIT HAVING AN ELECTROSTATIC DISCHARGE PROTECTION FUNCTION AND AN ELECTRONIC SYSTEM INCLUDING THE SAME

An integrated circuit includes a data processing circuit, an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail and protects the data processing circuit from an ESD event on the voltage rail, and a switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal. 1. An integrated circuit , comprising:a data processing circuit;an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail, and protects the data processing circuit from an ESD event on the voltage rail; anda switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal.2. The integrated circuit of claim 1 , further comprising a controller which determines whether the data processing circuit performs a data processing operation claim 1 , and generates the control signal for controlling the connection between the voltage rail and the data processing circuit according to a result of the determination.3. The integrated circuit of claim 2 , wherein the controller generates the control signal for connecting the voltage rail and the data processing circuit when the data processing circuit performs the data processing operation claim 2 , and generates the control signal for blocking the connection between the voltage rail and the data processing circuit when the data processing circuit does not perform the data processing operation.4. The integrated circuit of claim 3 , wherein the data processing operation is a write operation or a read operation.5. The integrated circuit of claim 1 , wherein the switch circuit includes:a first switch which is connected between the voltage rail and the data processing circuit and includes a first control terminal; anda second switch which is connected between the first control terminal and the ground rail, includes a second control ...

Semiconductor integrated circuit

A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

READ CIRCUITRY FOR ELECTROSTATIC DISCHARGE SWITCHING MEMRISTIVE ELEMENT

In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor. 1. An apparatus comprising:a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin; andread circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor,wherein the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor,2. The apparatus of claim 1 , wherein the coupling between the read circuitry and the memristive element includes a direct path for current from the ESD event to a dopant diffusion region of the first transistor.3. The apparatus of claim 1 , wherein the read circuitry comprises:a current source to provide a reference current;a current mirror to replicate the reference current to be passed through the memristive element; anda voltage comparator to compare a voltage drop across the ...

Semiconductor device with secure access key and associated methods and systems

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

APPARATUSES AND METHODS FOR ADJUSTING WRITE PARAMETERS BASED ON A WRITE COUNT

According to one embodiment of the present invention, an apparatus disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters. 1. An apparatus comprising:a memory array having a plurality of memory cells;memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals;control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.2. The apparatus of claim 1 , further comprising:a parameter table defining a plurality of write cycle bins, wherein the control logic configured to compare the number of write operations performed by the memory access circuits to the plurality of write cycle bins to select the set of write parameters.3. The apparatus of claim 2 , wherein the parameter table is to ed in the memory array.4. The apparatus of claim 2 , wherein the parameter table includes a minimum number of write operations and a maximum number of write operations for each of the plurality of write cycle bins.5. The apparatus of claim 1 , wherein the plurality of memory cells includes one or more phase change memory cells.6 ...

Integrated Circuit Copy Prevention Device Powered By A Photoelectric Cell

An integrated circuit includes a substrate, a first circuit disposed on the substrate, a photoelectric cell disposed on the substrate and coupled to the first circuit, the photoelectric cell to provide power to the first circuit when the photoelectric cell is exposed to light, and the first circuit to allow disabling at least a portion of the integrated circuit when powered by the photoelectric cell. 1. An integrated circuit comprising:a substrate;a first circuit disposed on the substrate;a photoelectric cell disposed on the substrate and coupled to the first circuit, the photoelectric cell to provide power to the first circuit when the photoelectric cell is exposed to light;the first circuit to allow disabling at least a portion of the integrated circuit when powered by the photoelectric cell; anda silicon controlled rectifier circuit to damage the integrated circuit after power is supplied to the integrated circuit.2. The integrated circuit of claim 1 , further comprising:a fuse array coupled to the first circuit, the fuse array when blown after power is supplied to the integrated circuit, to disable one or more portions of the integrated circuit.3. The integrated circuit of claim 1 , further comprising:a programmable memory coupled to the first circuit, the first circuit to disable the at least a portion of the integrated circuit via a change in a portion of the programmable memory after power is supplied to the integrated circuit.4. The integrated circuit of claim 3 , wherein the change in a portion of the programmable memory is to erase the portion of the programmable memory.5. The integrated circuit of claim 3 , wherein the change in a portion of the programmable memory is to re-program the portion of the programmable memory.6. (canceled)7. The integrated circuit of claim 1 , further comprising:a disable circuit to disable the first circuit.8. A computing device comprising: a substrate;', 'a first circuit disposed on the substrate;', 'a photoelectric cell ...

ADAPTIVE READ THRESHOLD VOLTAGE TRACKING WITH CHARGE LEAKAGE MITIGATION USING CHARGE LEAKAGE SETTLING TIME

Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells. 1. A device for use with multi-level memory cells , comprising:a controller configured to perform the following steps:after a predefined time interval that is based on a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determining a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; andemploying the plurality of read reference voltages to read data from the multi-level memory cells.2. The device of claim 1 , further comprising the step of employing the plurality of read reference voltages shifted by at least one reference voltage offset to read data from the multi-level memory cells during the predefined time interval.3. The device of claim 2 , wherein the shifting is performed until the charge leakage of the multi-level memory cells has settled.4. The device of claim 2 , wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages after the predefined time interval since the programming of the multi-level memory ...

UNCHANGEABLE PHYSICAL UNCLONABLE FUNCTION IN NON-VOLATILE MEMORY

A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set. 1. A circuit configured for maintaining PUF keys in unchangeable form when needed , comprising:a plurality of non-volatile memory cells, wherein the plurality of non-volatile memory cells includes an array of memory cells with peripheral circuits for access to the array;logic to use a physical unclonable function to produce a key, and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells; andlogic to disable changes to data in the set of non-volatile memory cells after the key is stored in the set, wherein the peripheral circuits have a first state in which access to the set of non-volatile memory cells to write the key is enabled, and a second state in which access to the set of non-volatile memory cells to write is disabled while access to other non-volatile memory cells in the array to write is enabled, and wherein the logic to disable changes to data in the set of non-volatile memory cells includes an indicator to set the first state or the second state.2. The circuit of claim 1 , wherein the physical unclonable function utilizes entropy generated using non-volatile memory cells in the plurality of non-volatile memory cells to produce the key.3. The circuit of claim 1 , wherein the logic to disable changes to data in the set of non-volatile memory cells further includes logic that disables use of the physical ...

TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE

A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation. 1. A device comprising:a plurality of detection memory cells, each detection memory cell of the plurality of detection memory cells configured to be pre-programmed to a respective initial predetermined state, the initial predetermined state of each of the plurality of detection memory cells configured to be unmodifiable by subsequent commands directed to the memory device;a plurality of reference bits, each reference bit of the plurality of reference bits corresponding to a respective one of the plurality of detection memory cells, wherein the initial predetermined state of each detection memory cell is represented by a corresponding reference bit of the plurality of reference bits; andcomparator circuitry coupled to the plurality of detection memory cells and the plurality of reference bits, the comparator circuitry configured to compare a current state of each detection memory cell of the plurality of ...

METHOD OF CONTROLLING ON-DIE TERMINATION AND SYSTEM PERFORMING THE SAME

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation. 1. A method of operating a low power double data rate 5 (LPDDR5) dynamic random access memory (DRAM) in a multi-rank memory system including a plurality of memory ranks , the method comprising:receiving a CAS command and a write command, wherein the CAS command and the write command conform to an LPDDR5 standard, the write command is dedicated to a first memory rank among the plurality of memory ranks and the write command is not dedicated to a second memory rank among the plurality of memory ranks;enabling a reception buffer in the first memory rank;disabling a transmission driver in the first memory rank;disabling a reception buffer and a transmission driver in the second memory rank;receiving a data strobe signal pair;enabling on-die terminal (ODT) circuits of the first memory rank and the second memory rank in response to the write command;receiving write data signals while the data strobe signal pair is toggled during the enabling of the ODT circuits of the first memory rank and the second memory rank;receiving the CAS command and a read command, wherein the read command conforms to the LPDDR5 standard, the read command is dedicated to the first memory rank and the read command is not dedicated to the second memory rank;enabling the transmission driver in the first memory rank;disabling the reception buffer in the first memory rank;disabling the ...

Device, system and method for providing information security

A cryptography system comprising a first node having a unique identifier generator configured to generate at least one physical unclonable function (PUF); and a second node configured to remotely send an attestation request to the first node is disclosed. In some embodiments, the cryptography system may form at least part of a distributed ledger and the PUF is configured to respond to the attestation request.

PROTECTION CIRCUIT FOR MEMORY IN DISPLAY PANEL AND DISPLAY PANEL

The present application discloses a protection circuit for a memory in a display panel and a display panel. The circuit comprises a timing controller, a memory, a power circuit, and a switching circuit. By removing the write protection signal originally provided by the computer, the power circuit outputs a stable and reliable write protection signal to the memory to limit the memory data from being overwritten, and then the timing controller controls the switching circuit to be turned on for grounding the control terminal of the write protection signal of the memory only when receiving an instruction to write data to the memory. 1. A protection circuit for a memory in display panel , wherein the protection circuit for a memory in display panel comprises:a timing controller having a signal transmission end and a write control signal output end;a memory having a signal transmission end and a write protection signal control end, the signal transmission end of the memory being connected to the signal transmission end of the timing controller; the memory is configured to store software data of the timing controller;a power circuit, an output end of which being connected to the write protection signal control end, the power circuit being configured to output a write protection signal to the memory to limit data of the memory from being overwritten; anda switching circuit, an input end of which is interconnected with the output end of the power circuit and the write protection signal control end, an output end of the switching circuit being grounded, a controlled end of the switching circuit being connected to the write control signal output end;the timing controller is configured to control the switching circuit to be in a normally turn-off state, and control the switching circuit to be turned on when receiving a data write instruction to the memory.2. The protection circuit for a memory in display panel according to claim 1 , wherein the switching circuit includes a ...

PUF APPLICATIONS IN MEMORIES

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit. 1. A memory device , comprising:an array of memory cells;a physically unclonable function (PUF) circuit in the memory device to generate PUF codes;a deterministic random bit generator (DRBG) to generate a sequence of at least pseudo random numbers based upon personalization strings;a data path including a first path connecting a first circuit comprising one of (i) the PUF circuit and (ii) a first set of memory cells at a first location in the array of memory cells storing a PUF code, to the DRBG in the memory device and a second path connecting the DRBG to a second set of memory cells at a second location in the array of memory cells for storing keys; andsecurity logic circuitry to apply PUF code output, received from the first circuit via the first path to the DRBG, and to apply pseudorandom number sequences generated by the DRBG, to the second set of memory cells via the second path.2. The memory device of claim 1 , wherein the pseudorandom number sequences generated by the DRBG are used for initializing encryption operations on data to be provided.3. The memory device of claim 1 , wherein the applying of the pseudorandom number sequences generated by the DRBG to the second set of memory cells via the second path claim 1 , further includes:storing a sequence of numbers generated by the DRBG as a key in the second set of memory cells in the array of memory cells.4. The memory device of claim 1 , wherein PUF codes are applied by the security logic circuitry for initializing the DRBG.5. The memory device of claim 4 , wherein a ...

Using dark bits to reduce physical unclonable function (puf) error rate without storing dark bits location

Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.

MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME

Provided herein may be a memory system and a method of operating the same. A semiconductor memory device may include a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin and a control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device. 1. A semiconductor memory device comprising:a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin; anda control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device.2. The semiconductor memory device according to claim 1 , wherein the control logic comprises an internal state detection unit configured to provide the external device with a detection signal representing an unstable operation condition of the semiconductor memory device through the write protect pin.3. The semiconductor memory device according to wherein the internal state detection unit generates the detection signal when an external or internal voltage of the semiconductor memory device is a threshold voltage or less.4. The semiconductor memory device according to wherein the internal state detection unit generates the detection signal when an internal temperature of the semiconductor memory device is a preset low temperature or less or is a preset high temperature or greater.5. The semiconductor memory device according to claim 2 , further comprising an output buffer configured to provide the detection signal to the external device through the write protect pin.6. The semiconductor memory device according to claim 1 , wherein the write protect pin ...

Unchangeable physical unclonable function in non-volatile memory

A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

ELECTROSTATIC DISCHARGE PROTECTION STRUCTURES FOR EFUSES

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source. 1. A structure comprising an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse , the ESD protection structure being structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.2. The structure of claim 1 , wherein the ESD protection structure is a diode formed in parallel with the eFuse claim 1 , wherein both terminals of the eFuse and the diode are each shared terminals.3. The structure of claim 2 , wherein one of the terminals of the diode are directly coupled to the source.4. The structure of claim 2 , wherein the diode is forward biased during the ESD event and reverse biased during normal operation.5. The structure of claim 4 , wherein the diode is clamped during a negative pulse such that parasitic current from a FET network will not unintentionally program the eFuse.6. The structure of claim 1 , wherein the ESD protection structure is a diode formed in series with the eFuse.7. The structure of claim 6 , wherein the diode is reverse biased during the ESD event and forward biased during normal operations.8. The structure of claim 7 , wherein the diode prevents a voltage from forming across the eFuse above its threshold.9. The structure of claim 6 , wherein the diode is coupled in series to a bank of eFuses.10. The structure of claim 6 , wherein the diode is between the eFuse and a FET network.11. The structure of claim 1 , wherein the ESD protection structure is a FET in parallel with the eFuse.12. The structure of claim 1 , wherein the ESD protection structure is a FET in series with the eFuse claim 1 , where a ...

MEMORY PROTECTION CIRCUIT AND LIQUID CRYSTAL DISPLAY INCLUDING SAME

Provided is a liquid crystal display device, including: a liquid crystal display panel; a memory for storing driving information and image data modulation information, and supplying the stored driving information and image data modulation information to a timing controller; a memory protection circuit for enhancing a write protection function of the memory, the memory protection circuit including a pull-up resistor for pulling up a write protection terminal of the memory to a power voltage, and a pad connected to the write protecting terminal and applying a low voltage to the write protection terminal; and a timing controller for reading the data stored in the memory to output various control signals for driving the liquid crystal display panel. 1. A memory protection circuit , comprising:a pull-up resistance having one end connected to a write protection terminal of a writable and readable memory and the other end connected to a power voltage; anda pad connected to the write protection terminal,wherein the pad is connected to a low-voltage source of a ROM-writer which writes data on the memory.2. The memory protection circuit of claim 1 , wherein the memory is an electrically erasable programmable read only memory (EEPROM) connected to a timing controller of a display device.3. The memory protection circuit of claim 2 , wherein the pull-up resistor is connected to the write protection terminal and a VCC terminal of the memory.4. A liquid crystal display device claim 2 , comprising:a liquid crystal display panel;a memory for storing driving information and image data modulation information, and supplying the stored driving information and image data modulation information to a timing controller;a memory protection circuit for enhancing a write protection function of the memory, the memory protection circuit including a pull-up resistor for pulling up a write protection terminal of the memory to a power voltage, and a pad connected to the write protecting terminal ...

Puf with dissolvable conductive paths

The generation of “fingerprints”, also called challenge-response pairs (CRPs) of Physically Unclonable Functions (PUFs), can often stress electronic components, leaving behind traces that can be exploited by crypto-analysts. A non-intrusive method to generate CRPs based on Resistive RAMs may instead be used, which does not disturb the memory cells. The injection of small electric currents (magnitude of nanoAmperes) in each cell causes the resistance of each cell to drop abruptly by several orders of magnitudes through the formation of temporary conductive paths in each cell. A repeated injection of currents into the same cell, results in an almost identical effect in resistance drop for a single cell. However, due to the small physical variations which occur during manufacturing, the cells are significantly different from each other, in such a way that a group of cells can be used as a basis for PUF authentication.

REGISTER FILE DEVICE

A register file device includes: a multi-port latch; and a write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, wherein the write circuit includes: a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, and a changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal. 1. A register file device comprising:a multi-port latch; anda write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, whereinthe write circuit includes:a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, anda changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal.2. The register file device according to claim 1 , whereinthe detection circuit outputs an address match signal when detecting a simultaneous writing to at least two ports of a multi-port latch.3. The register file device according to claim 2 , whereinthe detection circuit outputs an alarm in response to the address match signal.4. A register file device comprising:a multi-port latch; anda write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write address, and write data,wherein the write circuit includes:a detection circuit that outputs an address match signal when a first write address of one ...

Physical Identifiers for Authenticating an Identity of a Semiconductor Component

This document describes techniques for authenticating an identity of a semiconductor component using a physical identifier. In some aspects, a physical identifier comprised of a region of features located indiscriminately within a surface of an encapsulated semiconductor component is fabricated. The physical identifier is then mapped. The map is then stored for use when authenticating the identity of the semiconductor component. 1. A method for enabling authentication of an identity of a semiconductor component , the method comprising:fabricating, as part of an encapsulation process defining a surface of the semiconductor component, a physical identifier, the physical identifier a region of features located indiscriminately within the surface;mapping the physical identifier, the map representing the region;reading, electrically from integrated circuitry of the semiconductor component, a binary identifier; andstoring the map and the binary identifier to enable authentication of the identity of the semiconductor component.2. The method of claim 1 , wherein fabricating the region having features located indiscriminately within the surface fabricates a microridge region claim 1 , the microridge region comprising a plurality of microridges located indiscriminately within the surface of the semiconductor component.3. The method of claim 2 , wherein mapping the physical identifier includes measuring the microridge region via a pressure-indicating sensor film claim 2 , a high-resolution camera claim 2 , or an interferometer.4. The method of claim 1 , wherein fabricating the region having features located indiscriminately with the surface fabricates a magnetic field region claim 1 , the magnetic field region comprising a plurality of magnetic nanoparticles located indiscriminately within the surface of the semiconductor component.5. The method of claim 4 , wherein mapping the physical identifier includes reading the magnetic field region via an induction mechanism claim 4 , ...

STROBE SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

A strobe signal generation circuit includes a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal; a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; and a second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal from among the at least one pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal. 1. A strobe signal generation circuit comprising:a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal;a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; anda second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal.2. The strobe signal generation circuit according to claim 1 , wherein the trigger circuit comprises:a serializer configured to generate a pre-pull-up signal and a pre-pull-down signal by serializing signals inputted through a first data input terminal and a second data input terminal, according to the clock signal;a first pre-driver configured to generate the pull-up signal by driving the pre-pull-up signal; anda second pre-driver configured to generate the pull-down signal by driving the pre-pull-down signal.3. The strobe signal generation circuit according to claim 2 , wherein the serializer is configured to receive a power supply voltage through the first data input terminal and receive a ground voltage through the second data input terminal.4. The strobe signal generation circuit according to claim 1 , ...

METHOD OF CONTROLLING ON-DIE TERMINATION AND SYSTEM PERFORMING THE SAME

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation. 1. A memory system operating in synchronization with an operation clock signal pair , the memory system comprising:a plurality of memory ranks, each memory rank including a plurality of memory devices, and each memory device including first and second mode registers for storing a target on-die termination (ODT) resistance value and a non-target on-die termination (ODT) resistance value respectively;a memory controller configured to set the first and second mode registers in each memory device and to perform a write operation on one of the plurality of memory ranks, the memory controller including a third mode register for storing a memory controller on-die termination (ODT) resistance value;a control bus shared by the plurality of memory ranks and coupled to the memory controller, and through the control bus, the memory controller transmitting a first CAS command and a write command to the plurality of memory ranks for a write operation;a data bus shared by the plurality of memory ranks and coupled to the memory controller, and through the data bus, the memory controller transmitting write data to the plurality of memory ranks;a plurality of rank selection signals, each of which connecting the memory controller to corresponding memory rank, wherein, when a first rank selection signal connected to a first memory rank among the plurality of memory ranks is ...

PROTECTION OF A MICROCONTROLLER

In an embodiment, a method for protecting an electronic circuit includes: detecting a malfunction of the electronic circuit; executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit; and triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures. An interval between two waves of countermeasures of the plurality of waves of countermeasures is variable. 1. A method for protecting an electronic circuit , the method comprising:detecting a malfunction of the electronic circuit;executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit, wherein an interval between two waves of countermeasures of the plurality of waves of countermeasures is variable; andtriggering a reset of the electronic circuit after executing the plurality of waves of countermeasures.2. The method of claim 1 , wherein a first group of waves of countermeasures of the plurality of waves of countermeasures does not comprise a non-maskable interrupt.3. The method of claim 2 , wherein the first group of waves of countermeasures comprises:blocking writing in a memory;blocking all or a part of an output of the electronic circuit; orregenerating cryptographic keys.4. The method of claim 2 , wherein a second group of waves of countermeasures of the plurality of waves of countermeasures comprises a non-maskable interrupts.5. The method of claim 1 , wherein the variable interval is random.6. The method of claim 5 , wherein the variable interval is longer than a predetermined minimum time and shorter than a predetermined maximum time.7. The method of claim 1 , wherein a number of countermeasures waves of the plurality of waves of countermeasures varies from one execution to another.8. The method of claim 1 , wherein a number of countermeasures per wave of countermeasures of the plurality of waves of countermeasures varies from one execution to another.9. The method of ...

Semiconductor Device

A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.

RANDOM CODE GENERATOR

A random code generator includes a control circuit, a high voltage power supply, a memory module and a counter. The control circuit generates a control signal and an enabling signal. During a program cycle, the enabling signal is activated. The high voltage power supply receives the enabling signal. A charge pump of the high voltage power supply generates a program voltage according to an oscillation signal. When the enabling signal is activated, the high voltage power supply outputs the program voltage. The memory module determines a selected memory cell of the memory module according to the control signal. During the program cycle, the selected memory cell receives the program voltage. During the program cycle, the counter counts a pulse number of the oscillation signal to acquire a counting value, and the control circuit determines a random code according to the counting value. 1. A random code generator , comprising:a control circuit generating a control signal and an enabling signal, wherein during a program cycle, the enabling signal is activated;a high voltage power supply receiving the enabling signal, wherein the high voltage power supply generates a program voltage according to an oscillation signal, wherein when the enabling signal is activated, the high voltage power supply outputs the program voltage, wherein when the enabling signal is inactivated, the high voltage power supply stops outputting the program voltage;a memory module receiving the control signal, and determining a selected memory cell of the memory module according to the control signal, wherein during the program cycle, the selected memory cell receives the program voltage; anda counter receiving the oscillation signal and the enabling signal, wherein during the program cycle, the counter counts a pulse number of the oscillation signal to acquire a counting value, and the control circuit determines a random code according to the counting value.2. The random code generating method as ...

METHOD OF MANAGING SEMICONDUCTOR MEMORIES, CORRESPONDING INTERFACE, MEMORY AND DEVICE

A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved. 1. A method of providing non-volatile data memory space for a range of user addresses , the method comprising:providing a range of non-volatile flash memory locations for writing data, wherein the range of flash memory locations for writing data is larger than the range of user addresses; andwriting data for the same user address in a plurality of different flash memory locations in the range of flash memory locations.2. The method of claim 1 , further comprising:receiving flash memory user access requests;checking if a certain request in the flash memory user access requests is a data access request; andin response to the certain request being a data access request, mapping the range of user addresses into the range of flash memory locations.3. The method of claim 1 , further comprising configuring the flash memory locations for writing data to include a first field to contain data written in the location claim 1 , and a second field to contain a tag indicative of a logic address coupled to the data written in the location.4. The method of claim 3 , wherein configuring the flash memory locations for writing data further comprises configuring the flash memory locations for writing data to include a third field to contain a flag indicative of whether the location is empty or not.5. The method of claim 1 , further comprising writing data in the range of flash memory locations in a bottom-up direction claim 1 , with data written in a first empty location each time a new data write is issued.6. The method of claim 1 , further ...

METHOD FOR DETECTING A THINNING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE AND CORRESPONDING INTEGRATED CIRCUIT

The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region. 1. A method for detecting a thinning of the semiconductor substrate of an integrated circuit from its back face , comprising:measuring a physical quantity representative of a resistance between first and second ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region;wherein the two electrically-conducting contacts extend, at least partially, into the insulating region.2. An integrated circuit , comprising:a semiconductor substrate,at least one insulating region formed within the substrate,an underlying substrate region below the at least one insulating region, anda detector comprising first and second electrically-conducting contacts extending, at least partially, into the insulating region, each having a first end situated at an interface between the insulating region and the underlying substrate region and having a second end,wherein the second ends are connected to an electrical circuit configured to generate an electrical signal representative of a value of a resistance of the underlying substrate region between the first ends.3. The integrated circuit according to claim 2 , further comprising:a dielectric layer situated on top of the semiconductor substrate, andat least a first metallization level situated on top of the dielectric layer,wherein the first and second electrically-conducting contacts also extending into the dielectric layer, andwherein the second ends open onto the first metallization level.4. The integrated circuit according to claim 3 , ...

MEMORY CARD

According to one embodiment, a memory card includes a housing and a switch. The housing includes a first surface and a second surface. The second surface is opposite to the first surface. The switch includes a first part, a second part, and a third part. The first part is disposed outside from the housing. The third part is disposed in the housing. The second part is connected to both the first part and the third part. The third part is in contact with both the first surface and the second surface. 1. A memory card comprising:a housing including a first surface and a second surface, the second surface being opposite to the first surface; anda switch including a first part, a second part, and a third part, the first part being disposed outside from the housing, the third part being disposed in the housing, the second part being connected to both the first part and the third part, the third part being in contact with both the first surface and the second surface.2. The memory card according to claim 1 , whereinthe third part includes symmetrical structure to a line passing through a center of the second part.3. The memory card according to claim 1 , whereinthe first surface includes a first side surface, and the second surface includes a second side surface.4. The memory card according to claim 3 , whereinthe third part includes a first portion being in contact with the first side surface and a second portion being in contact with the second side surface.5. The memory card according to claim 3 , whereinthe third part includes a convex portion on an opposite side of a side where the second part is connected.6. The memory card according to claim 3 , whereinthe third part includes asymmetrical structure to a line passing through a center of the second part.7. The memory card according to claim 6 , whereina thickness of the first side surface is thicker than that of the second side surface.8. The memory card according to claim 7 , whereinthe thickness of the first side ...

SEMICONDUCTOR DEVICE, PRE-WRITE PROGRAM, AND RESTORATION PROGRAM

When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device and a second storage device to have threshold voltages, respectively, both increased, and the control circuit thereafter controls performing an erase process to allow the first storage device and the second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit has received a second erase command, the control circuit controls performing a second pre-write process to allow one of the first storage device and the second storage device to have its threshold voltage increased, and control circuit subsequently controls performing the erase process.

APPARATUS AND A METHOD FOR ERASING DATA STORED IN A MEMORY DEVICE

The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal. Such an approach enables the security of a memory device to be improved, and in particular prevents hackers from taking advantage of data remanence effects, by ensuring that stored data is overwritten in an efficient, and clock independent, manner, triggered by assertion of an erase signal generated if a pulse-based control signal does not take it is expected form. 1. An apparatus comprising:a memory device comprising an array of memory cells, and configured to operate from a clock signal;erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array; anderase signal generation circuitry configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses;the erase signal generation circuitry being configured to issue said erase signal in said asserted state if the control signal does ...

POWER DELIVERY CIRCUITRY

A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient. 1. A method comprising:charging an energy storage device via a first power from a power supply, wherein the energy storage device is coupled between an input of power delivery circuitry of a memory device and an output of the power delivery circuitry;receiving, in the power delivery circuitry, the first power from the power supply, a second power from the energy storage device, or both; anddelivering a third power, via the power delivery circuitry, to a memory system of the memory device.2. The method of claim 1 , wherein the energy storage device is directly coupled to the input of the power delivery circuitry.3. The method of claim 1 , wherein charging comprises charging the energy storage device through a resistor configured to regulate the charging.4. The method of claim 1 , comprising directly coupling the energy storage device to the input of the power delivery circuitry via a switch configured to bypass a resistor.5. The method of claim 1 , wherein the third power comprises a combination of the first power and the second power.6. The method of claim 1 , wherein the memory system comprises a solid state memory system.7. The method of claim 1 , wherein the power delivery circuitry comprises a direct current (DC) to DC voltage converter.8. The method of claim 7 , wherein the DC to DC voltage converter comprises a buck mode DC to DC converter.9. The method of claim 1 , comprising supplementing the first power to the power delivery circuitry with the second power.10. A method of manufacturing a memory device comprising:coupling power delivery circuitry to a memory system; andcoupling an energy storage device between an input of the power delivery circuitry and an output of the power delivery circuitry, wherein the energy storage device ...

ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND APPLICATIONS THEREOF

An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well. 1. An electrostatic discharge (ESD) protection apparatus , comprising:a semiconductor substrate, having a doping well with a first conductivity, wherein one end of the doping well is grounded;a first gate structure, disposed on the doping well;a first doping region, having a second conductivity, disposed in the doping well and adjacent to the first gate structure, and electrically connected to a pad;a second doping region, having the second conductivity, disposed in the doping well and adjacent to the first gate structure; anda third doping region, having the first conductivity, disposed in the doping well, and forming a P/N junction interface with the second doping region;wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.2. The ESD protection apparatus according to claim 1 , further comprising:a second gate structure, disposed on the doping well and adjacent to the first doping region;a fourth doping region, having the second conductivity, disposed in the ...

SECURELY SHARING A MEMORY BETWEEN AN EMBEDDED CONTROLLER (EC) AND A PLATFORM CONTROLLER HUB (PCH)

Systems and methods for securely sharing a memory between an Embedded Controller (EC) and a Platform Controller Hub (PCH). In some embodiments, an IHS may include: a chipset; a flash device coupled to the chipset; and an EC coupled to the flash device via a first bus and to the chipset via a second bus, wherein the EC comprises a Read-Only Memory (ROM) portion and a Random Access Memory (RAM) portion, the EC configured to: retrieve EC firmware from the flash device via the first bus; store the retrieved EC firmware in the RAM portion; and prior to the execution of any instruction stored in the RAM portion, relinquish access to the flash device via the first bus. 1. An Information Handling System (IHS) , comprising:a chipset;a flash device coupled to the chipset; and retrieve EC firmware from the flash device via the first bus;', 'store the retrieved EC firmware in the RAM portion; and', 'prior to the execution of any instruction stored in the RAM portion, relinquish access to the flash device via the first bus., 'an Embedded Controller (EC) coupled to the flash device via a first bus and to the chipset via a second bus, wherein the EC comprises a Read-Only Memory (ROM) portion and a Random Access Memory (RAM) portion, the EC configured to2. The IHS of claim 1 , wherein the chipset is a Platform Controller Hub (PCH).3. The IHS of claim 1 , wherein the first bus is a Serial Peripheral Interface (SPI) bus claim 1 , and wherein the second bus is an Enhanced SPI bus (eSPI).4. The IHS of claim 1 , wherein the EC firmware comprises: (i) trusted EC code; and(ii) untrusted processor code.5. The IHS of claim 1 , further comprising multiplexing circuitry configured to control access by the EC to the flash device over the first bus.6. The IHS of claim 1 , further comprising counter circuitry coupled to the EC claim 1 , the counter circuitry configured to end EC access to the flash device via the first bus.7. The IHS of claim 6 , wherein the counter circuitry is configured to ...

Power delivery circuitry

A memory device may include a memory system and an energy storage device. Additionally, the energy storage device may supply a first power to the memory system when a second power from a power supply is eliminated or insufficient.

DELAY CIRCUITRY TO HOLD UP POWER TO A MASS STORAGE DEVICE AND METHOD THEREFOR

A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media. 1. A computer device , comprising:an enclosure having one or more host computers powered by a power supply;a plurality of non-volatile memory mass storage devices having a volatile memory cache and a non-volatile memory data carrier;a plurality of interposer boards, the one or more host computers communicatively coupled to the plurality of non-volatile memory mass storage devices by the plurality of interposer boards;where at least one of the host computers in the one or more host devices is configured to exchange data and control signals with selected non-volatile memory devices in the plurality of non-volatile memory mass storage devices; and a first e-fuse to gate power to a logic circuit on the at least one interposer board along a data path to a first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices;', 'a second e-fuse to gate power to the first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices, wherein the first and the second e-fuses are logically connected to fault the second e-fuse when a fault condition occurs on the first e-fuse; and', 'a delay circuit, coupled between the first e-fuse and the second e-fuse, configured to delay the fault of the second e-fuse after the fault of the first e-fuse., 'where each of the interposer boards in the plurality of interposer boards comprises2. The computer device of claim 1 , further comprising a midplane coupled between the one or more host devices and the plurality of interposer boards.3. The computer device of claim 1 , wherein the fault of ...

SYSTEM AND METHOD FOR PROBABILISTIC DEFENSE AGAINST REMOTE EXPLOITATION OF MEMORY

A system and method is provided for probabilistic defense against remote exploitation of memory. In certain embodiments, the system comprises one or more processors, read and execute (RX) portions of memory, read and write (RW) portions of memory, execute only (XOM) portions of memory, and one or more programs stored in the memory. The one or more programs include instructions for maintaining all pointers to RX memory instructions in XOM memory. In addition, the one or more programs include instructions for preventing all direct references to RX memory in RW memory by forcing pointers in RW memory to reference XOM memory first, which then references RX memory instructions. 1. A system for probabilistic defense against remote exploitation of memory , comprising:one or more processors;read and execute (RX) portions of memory;read and write (RW) portions of memory;execute only (XOM) portions of memory; and maintaining all pointers to RX memory instructions in XOM memory; and', 'preventing all direct references to RX memory in RW memory by forcing pointers in RW memory to reference XOM memory first, which then references RX memory instructions., 'one or more programs stored in the memory, the one or more programs comprising instructions for2. The system of claim 1 , wherein all pointers to RX memory instructions in XOM memory are maintained in an opaque trampoline table (OTT).3. The system of claim 2 , wherein the OTT is a contiguous region of XOM memory.4. The system of claim 3 , wherein the OTT comprises JMPs and CALLs.5. The system of claim 1 , wherein ASLR is implemented on the system.6. The system of claim 1 , wherein if an attacker can leak a pointer to a code segment claim 1 , the attacker is still forced to guess because the attacker cannot find out through the leak where code segments exist in target address space.7. The system of claim 1 , wherein an attacker is able to conduct arbitrary read and writes over the address space.8. A method for probabilistic ...

NOISE SHIELDING CIRCUIT AND CHIP

A chip includes a processor, a memory, and a storage controller of the memory. There is an access path between the processor and the storage controller, and the processor reads data from or writes data into the memory by using the storage controller through the access path. The chip further includes a shielding circuit. The shielding circuit is configured to shield a signal on the access path when the processor is powered off. 110.-. (canceled)11. A chip , comprising:a processor;a memory;a storage controller configured to control the memory, wherein there is an access path between the processor and the storage controller, and the processor is configured to read data from or write data into the memory using the storage controller through the access path; anda shielding circuit, wherein the shielding circuit is configured to shield a signal on the access path when the processor is powered off.12. The chip according to claim 11 , wherein the chip comprises at least two power domains claim 11 , the processor is located in a first power domain claim 11 , and the memory and the storage controller are located in a second power domain;wherein the chip is configured in a manner that, when the first power domain is powered off, the processor is powered off, and the second power domain is maintained with a power supply; andwherein the memory is configured to store state data when the first power domain is powered off, wherein the state data is useable to, when the first power domain is powered on, recover a system to a state before the system is powered off.13. The chip according to claim 12 , wherein the shielding circuit comprises:a power-off confirming circuit; anda shielding circuit, wherein the power-off confirming circuit is configured to confirm whether the processor or the first power domain is powered off, and the shielding circuit is configured to shield the signal on the access path when the first power domain is powered off.14. The chip according to claim 13 , ...

ELECTROSTATIC DISCHARGE CIRCUIT

An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path. 1. An electrostatic discharge (ESD) circuit connected to a power pad and a first node , the ESD circuit comprising:a RC circuit connected between the power pad and the first node, wherein the RC circuit is capable of providing a first control voltage and a second control voltage; anda first ESD current path connected between the power pad and the first node, wherein when the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.2. The ESD circuit as claimed in claim 1 , further comprising:a first P-type transistor, wherein a first drain/source terminal and a body terminal of the first P-type transistor are connected to the power pad, a gate terminal of the first P-type transistor receives the first control voltage, and a second drain/source terminal of the first P-type transistor is connected to a second node; anda first N-type transistor, wherein a first drain/source terminal of the first N-type transistor is connected to the second node, a gate terminal of the first N-type transistor receives the second control voltage, and a second drain/source terminal and a body terminal of the first N- ...

POWER DELIVERY CIRCUITRY

Embodiments of the present disclosure are directed to a system that includes a memory device. The memory device includes a memory system and an energy storage device including a capacitor. Additionally, the memory storage device includes power delivery circuitry that delivers to the memory system a first power from the energy storage device and a second power from an external power supply coupled to the memory device. 1. A system , comprising: 'a memory system;', 'a memory device, comprising 'power delivery circuitry configured to deliver to the memory system a first power from the energy storage device and a second power from an external power supply coupled to the memory device, wherein the memory system has a power demand limit that exceeds the maximum power that may be delivered by the external power supply.', 'an energy storage device; and'}2. The system of claim 1 , wherein the power delivery circuitry maintains a constant output voltage to the memory system.3. The system of claim 2 , wherein the constant output of the power delivery circuitry is maintained and/or smoothed by the energy storage device.4. The system of claim 1 , wherein the energy storage device is configured to provide the first power in combination with the second power to meet a power demand of the memory system.5. The system of claim 4 , wherein the power demand of the memory system is greater than 200 mW and a maximum power providable by the external power supply is 200 mV.6. The system of claim 4 , wherein the use of the energy storage device allows for a maintained or a decreased latency of the memory system.7. The system of claim 4 , wherein the power demand of the memory system is the power demand associated with the memory system being idle.8. The system of claim 1 , wherein the second power is 0 W.9. The system of claim 1 , wherein when the power demand of the memory system is less than the maximum power of the external power supply claim 1 , and the energy storage device is charged ...

SEMICONDUCTOR SYSTEM, SEMICONDUCTOR CHIP, AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR SYSTEM

A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

FAILURE DETECTION CIRCUITRY FOR ADDRESS DECODER FOR A DATA STORAGE DEVICE

A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.

METHOD OF CONTROLLING ON-DIE TERMINATION AND SYSTEM PERFORMING THE SAME

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation. 1. A method of controlling on-die termination (ODT) in a multi-rank memory system including a plurality of memory ranks , the method comprising:enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank memory system is powered on;enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; anddisabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.2. The method of claim 1 , wherein each of the ODT circuits of the plurality of memory ranks has a first resistance value in the initial state.3. The method of claim 2 , wherein enabling the ODT circuits during the write operation comprises:maintaining the ODT circuits of the plurality of memory ranks in the initial state to have the first resistance value during the write operation.4. The method of claim 2 , wherein enabling the ODT circuits during the write operation further comprises:changing a resistance value of the ODT circuit of the write target memory rank from the first resistance value to a second resistance value different from the first resistance value during the write operation.5. The method of claim 2 , wherein enabling the ...

Encrypted memory access using page table attributes

Encrypted memory access using page table attributes is disclosed. One example is a memory system including a memory controller at a memory interface. The memory controller includes an encryptor to control a plurality of memory access keys respectively associated with memory regions, where each memory region is allocated to a respective client, and an access manager to receive an access request from a client, the access request including a client access key to access a memory element. The access manager looks up a memory access key from a page table attribute associated with a physical address of the memory element, and determines if the access request is valid by comparing the client access key with the memory access key associated with the memory region that includes the memory element. Based on the determination and a mode of operation, the access manager provides a response to the access request.

Memory module, operation method of memory module, memory system, and operation method of memory system

A memory module includes: a plurality of memories, wherein each of the memories comprises: an encryption key storage circuit suitable for storing an encryption key; an address encryption circuit suitable for generating an encrypted address by encrypting an address transferred from a memory controller by using the encryption key stored in the encryption key storage circuit; and a cell array accessed by the encrypted address, wherein the encryption key storage circuits of the memories store different encryption keys.

MEMORY ARRAY HAVING DISTURB DETECTOR AND WRITE ASSISTOR

A memory array having a first port and a second port is disclosed. The memory array includes: a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line; a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; and a disturb detector, used to generate a disturb detected signal for indicating whether the first memory cell and the second memory cell are accessed at a same time. A memory array having a write assistor is also disclosed. 1. A memory array having a first port and a second port , the memory array comprising:a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line;a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; anda disturb detector, configured to generate a disturb detected signal according to an internal clock of the first port and an internal clock of the second port for indicating whether the first memory cell and the second memory cell are accessed at a same time;wherein the disturb detector includes a signal keeper to allow a logical value of the disturb detected signal to be remained when the internal clock of the first port is activated and the internal clock of the second port is deactivated.2. The memory array of claim 1 , wherein the disturb detector generates the disturb detected signal according to a received decoded row address of the first port and a received decoded row address of the second ...

OFF-CHIP MEMORY ADDRESS SCRAMBLING APPARATUS AND METHOD FOR SYSTEM ON CHIP

The present disclosure provides an off-chip memory address scrambling apparatus and method for a system on chip. The apparatus includes a true random number generator, a key memory and an on-chip security controller. The on-chip security controller is connected to the true random number generator, the key memory and an off-chip memory respectively and is configured to read or write data in the off-chip memory and perform address scrambling processing on the data. The on-chip security controller includes: a memory interface module, and an address scrambling module configured to read a random key stored in the key memory, to select according to a valid/invalid state of the random key to directly invoke the read random key or read again a random key that is generated by the true random number generator and stored into the key memory, and then to perform according to the random key scrambling algorithm processing on an unscrambled address inputted by the memory interface module to form a scrambled address, and output the scrambled address to an address scrambling module of the off-chip memory. The present disclosure can improve the security while high efficiency. 1. A memory address scrambling apparatus disposed on a system on. a chip (SoC) that is coupled to an off-chip memory , comprising:a true random number generator configured to generate random keys;a key memory configured to store the random keys; and a memory interface module configured to output an address for data to be read from or written to the off-chip memory, and', 'an address scrambling module configured to acquire a valid random key stored in. key memory, to scramble the address received from the memory interface module using the valid random key, and to output the scrambled address to the off-chip memory., 'an on-chip security controller communicatively coupled to the true random number generator, the key memory, and the off-chip memory, the on-chip security controller comprising2. The apparatus of ...

METHOD AND APPARATUS FOR PUF GENERATOR CHARACTERIZATION

Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a testing method for physical unclonable function (PUF) generator includes: verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array; determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states; if the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, wherein the first map comprises at least one stable bit cells and at least one unstable bit cell; generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, wherein the second map comprises at least one stable bit cells and at least one unstable bit cell; determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map using a Built-in Self Test (BIST) engine; if the second number of second bit cells is determined to be zero, determining a third number of third bit cells using the BIST engine, wherein the third bit cells are stable in the first map and stable in the second map; and if the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator. 1. A testing method for physical unclonable function (PUF) generator comprising:verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array,determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the ...

Memory device

A memory device includes a non-volatile memory block, a protection unit arranged for connecting to a communication bus, and a sequencer arranged to receive commands from the protection unit. A logic circuit is arranged to output an enabling signal, and includes first and second logic subcircuits, and a combiner logic circuit.

METHOD AND APPARATUS FOR PUF GENERATOR CHARACTERIZATION

Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a testing method for physical unclonable function (PUF) generator includes: verifying a functionality of a PUF generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array; determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states; when the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, generating a second map under a second set of operation conditions using the PUF generator and the masking circuit, determining a second number of second bit cells, wherein the second bit cells are stable in the first map and unstable in the second map; when the second number of second bit cells is determined to be zero, determining a third number of third bit cells, wherein the third bit cells are stable in the first map and stable in the second map; and when the third number of third bit cells are greater than a second preconfigured number, the PUF generator is determined as a qualified PUF generator. 1. A method comprising:verifying a functionality of a physical unclonable function (PUF) generator by writing preconfigured logical states to and reading output logical states from a plurality of bit cells in a PUF cell array;determining a first number of first bit cells in the PUF cell array, wherein the output logical states of the first bit cells are different from the preconfigured logical states;when the first number of first bit cells is less than a first predetermined number, generating a first map under a first set of operation conditions using the PUF generator and a masking circuit, wherein the first set of operation conditions comprises a first ...

Electronic control system

An engine control system stores data indicating a monitor frequency ratio for each failure diagnosis target item in EEPROM and standby RAM being backed up by a battery. The failure diagnosis target items are designated based on Rate Base Monitor Method. A data item of the data indicating a monitor frequency is incremented by one, at one time at the maximum, for one operation period of the system. When the system starts its operation, whether a value S [i] in standby RAM is greater by one than a value E [i] in EEPROM is determined for each data item. When the determination is affirmed for a given data item, it is determined that storing of the given data item is not completed in EEPROM for the preceding operation period. The value S [i] is thereby written in EEPROM.

Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains

Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected. 1. A device , comprising: a base to map a virtual memory address region to a physical memory address region; and', 'a list of permissions for a plurality of domains of routines respectively; and, 'a page table having a plurality of page table entries, including a first page table entry configured to specify determine, based on the list of permissions, a permission to access, by execution of the instruction in a routine having a first domain among the plurality of domains, the physical memory address region; and', 'control, based on the permission, the execution of the instruction in accessing, via the virtual memory address, the physical memory address region., 'a logic circuit configured to, in response to an instruction of a routine executed in a processor to access a virtual memory address in the virtual memory address region2. The device of claim 1 , further comprising:a memory having the physical memory address region; andthe processor coupled with the memory.3. The device of claim 2 , wherein the logic circuit includes a memory management unit.4. The device of claim 2 , wherein a plurality of routines stored in the memory are classified in the plurality of domains.5. The device of claim 2 , wherein the first page table entry includes data representative of the physical memory address region.6. The device of claim 5 , wherein the logic circuit is configured to use an offset specified in ...

ワンチツプ・マイクロコンピユ−タ

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Semiconductor memory for logic-hybrid memory

본 발명의 목적은 논리 블럭으로부터 이상 신호를 차단하는 것이 가능한 반도체 메모리를 제공하는 것이다. It is an object of the present invention to provide a semiconductor memory capable of blocking an abnormal signal from a logic block. 상기 목적을 달성하기 위해, 본 발명은 로우 어드레스로부터의 선택을 제어하는 제1 제어 신호 라인, 칼럼 어드레스로부터의 선택을 제어하는 제2 제어 신호 라인, 소정 수의 제어 신호들이 이상 신호인 경우 제1 제어 신호 라인을 차단하는 제1 전압 제어 수단, 및 소정 수의 제어 신호들이 이상 신호인 경우 제2 제어 신호 라인을 차단하는 제2 전압 제어 수단을 포함하는 반도체 메모리를 제공한다. In order to achieve the above object, the present invention provides a first control signal line for controlling selection from a row address, a second control signal line for controlling selection from a column address, and a first control signal when a predetermined number of control signals are abnormal signals. A semiconductor memory includes a first voltage control means for blocking a control signal line and a second voltage control means for blocking a second control signal line when a predetermined number of control signals are abnormal signals.

Non-volatile memory, memory card and information processing device using same, and software write protect control method of non-volatile memory

라이트 프로텍트 기능이 없는 불휘발성 메모리를 사용한 메모리카드 및 정보처리장치에 있어서 불휘발성의 소프트 웨어 라이트 프로텍트가 가능한 불휘발성 메모리 및 그것을 이용한 시스템 기술을 제공한다. 불휘발성 소프트 웨어 라이트 프로텍트 기능이 없는 개서 가능한 불휘발성 메모리를 이용한 플래시 메모리 카드로서 일괄전기적 소거 및 기록 가능한 플래시 메모리와 전원투입시의 파워 온 리셋 신호를 발생하는 리셋 IC와 이들이 디바이스간의 컨트롤러와 메모리카드 인터페이스와의 사이의 제어를 행하는 카드 컨트롤러를 포함하여 플랫 메모리에는 라이트 프로텍트를 행하고 싶은 에어리어의 어드레스를 라이트 하는 프로텍트 보존 레지스터가 어트리뷰영역에서 설정되며 시스템에서 프로텍트 범위가 설정된다.

Method and apparatus for protecting flash memory

프로세서(102), 시스템 메모리, 플래시 메모리, 및 메모리 제어기(104)를 갖는 컴퓨터 시스템에서, 시스템 메모리(106)의 일부로 이미지 및 디지털 서명하는 방법이 설명된다. 즉, 프로세서가 플래시 메모리(108)와 시스템 메모리(106)의 일부로만 액세스하도록 제한하는 메모리 제어기를 구성하는 단계; 디지털 서명을 사용하여 플래시 메모리 갱신 프로그램을 검증하는 단계; 및 플래시 메모리 갱신 프로그램이 인증된 것이라면 플래시 메모리를 갱신하는 단계를 포함한다. In a computer system having a processor 102, system memory, flash memory, and memory controller 104, a method of image and digitally signing as part of system memory 106 is described. That is, configuring the memory controller to restrict the processor to access only part of the flash memory 108 and the system memory 106; Verifying the flash memory update program using the digital signature; And updating the flash memory if the flash memory update program is authenticated.

Write-in method for from

Semiconductor device

Ic memory unit

Nonvolatile memory having attribute data area and data storage area for storing attribute data of data storage area

메모리는 다수의 워드 라인(WL1-8), 다수의 비트 라인(BL1-512, BLa1-32), 다수의 메모리 셀(C1-512, Ca1-32)을 갖고, 메모리 셀(C1-512, Ca1-32)의 각각은 워드 라인(WL1-8)의 선택된 하나와 비트 라인(BL1-512, BLa1-32)의 선택된 하나 사이에 접속되며, 워드 라인(WL1-8)의 선택된 하나에 접속된 다수의 메모리 셀(C1-512, Ca1-32)은 제1그룹 메모리 셀(C1-512)과 제2그룹 메모리 셀(Ca1-32)로 분할되며, 제1그룹 메모리 셀(C1-512)은 데이터 기억을 위해 제공되며 제2그룹 메모리 셀(Ca1-32)은 제1그룹 메모리 셀(C1-512)의 속성 데이터를 기억하도록 제공된다. The memory has a plurality of word lines WL1-8, a plurality of bit lines BL1-512 and BLa1-32, and a plurality of memory cells C1-512 and Ca1-32, and memory cells C1-512 and Ca1. Each of -32 is connected between the selected one of the word lines WL1-8 and the selected one of the bit lines BL1-512 and BLa1-32, and a plurality of connected to the selected one of the word lines WL1-8. The memory cells C1-512 and Ca1-32 are divided into a first group memory cell C1-512 and a second group memory cell Ca1-32, and the first group memory cells C1-512 are data. The second group memory cells Ca1-32 are provided for storage and are provided to store attribute data of the first group memory cells C1-512.

Erase lock of page unit

청구범위에 기재된 발명이 속하는 기술분야; 불휘발성 반도체 메모리 장치의 소거락 및 소거언락방법에 관한 것이다. The technical field to which the invention described in the claims belongs; An erase lock and an unlock method of a nonvolatile semiconductor memory device. 발명이 해결하려고 하는 기술적 과제; 워드라인 단위, 즉 페이지 단위의 소거방지를 구현할 수 있는 불휘발성 반도체 메모리 장치 및 소거락방법을 제공함에 있다. Technical problem to be solved by the invention; Disclosed is a nonvolatile semiconductor memory device and an erase lock method capable of implementing erasure prevention on a word line basis, that is, on a page basis. 발명의 해결방법의 요지; 불휘발성 반도체 메모리 장치에 있어서 : 상기 메모리 쎌 어레이내의 메모리 트랜지스터들과 접속된 락쎌들과; 락명령에 응답하여 선택된 워드라인에 접속된 다수개의 메모리 트랜지스터들을 소거함에 따라 상기 락쎌의 상태가 온 쎌상태가 되고, 상기 락쎌들과 접속된 비트라인에 외부신호가 인가되는 것을 방지하는 소거락 동작을 수행하며, 언락명령에 응답하여 상기 선택된 다수개의 메모리 트랜지스터들을 소거함에 따라 상기 락쎌을 온시키고 블록 프로그램할 데이터를 인가받아 상기 락쎌을 오프 쎌로 유지하는 언락동작을 수행하는 제어부를 가짐을 요지로 한다. The gist of the inventive solution; A nonvolatile semiconductor memory device, comprising: locks coupled to memory transistors in the memory array; The erase lock operation is performed to erase the plurality of memory transistors connected to the selected word line in response to the lock command, thereby to turn on the lock pin and to prevent an external signal from being applied to the bit line connected to the lock pins. And a control unit for performing an unlock operation to turn on the lock and to receive the data to block program in response to an unlock command and to erase the selected plurality of memory transistors in response to an unlock command. . 발명의 중요한 용도; 불휘발성 반도체 메모리 장치에 적합하게 사용된다. Important uses of the invention; It is suitably used for a nonvolatile semiconductor memory device.

Address decoder circuit

Semiconductor device

An electrically erasable programmble rom

PURPOSE: An EEPROM(Electrically Erasable and Programmable Read Only Memory) is provided to be programmable without additional program power supply part comprised in the external. CONSTITUTION: The EEPROM(30) is programmable when a normal operation is performed by receiving a power supply voltage(Vcc) and a program voltage(Vpp) for programming and a write enable signal are inputted, and includes: a register(37) which is located in a region of a memory region and stores data(D0) to set a program enable/disable state by being selected when a corresponding address signal is inputted; and a program state set part(39) setting the program enable/disable state by receiving an output of the register and the write enable signal. The register receives the data(D0) and is a flip flop for 1 bit latch with the write enable signal as a clock signal, and the program state set part comprises an OR gate receiving an output signal of the flip flop and receives the write enable signal. The program voltage is the same voltage(5V) as the power supply voltage or is a voltage(12V) higher than the power supply voltage.

Nonvolatile memory device and program method thereof

본 발명은 불휘발성 메모리 장치에 관한 것으로, 좀더 자세하게는 멀티 레벨 셀 방식을 지원하는 불휘발성 메모리 장치 및 그것의 프로그램 방법에 관한 것이다. 본 발명의 실시 예에 따른 불휘발성 메모리 장치는 복수의 페이지들을 포함하는 불휘발성 메모리 및 상기 불휘발성 메모리를 제어하는 컨트롤러를 포함하며, 상기 컨트롤러는 상기 복수의 페이지들 중 제 1 페이지에 대한 LSB 프로그램 동작이 수행된 후에 상기 복수의 페이지들 중 제 2 페이지에 대한 LSB 프로그램 동작이 수행되도록 상기 불휘발성 메모리를 제어하며, 상기 불휘발성 메모리는 상기 제 2 페이지에 대한 LSB 프로그램 동작이 수행될 때 상기 제 1 페이지에 프로그램된 데이터에 대한 정보를 상기 제 2 페이지의 스페어 영역에 저장한다. 본 발명의 실시 예에 따른 불휘발성 메모리 장치는 서든 파워 오프 후 복구 동작이 수행되는 경우에 빠른 속도로 복구 동작을 수행할 수 있다. The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device supporting a multi-level cell method and a programming method thereof. A non-volatile memory device according to an embodiment of the present invention includes a non-volatile memory including a plurality of pages and a controller for controlling the non-volatile memory, The non-volatile memory controls the non-volatile memory such that an LSB program operation for a second page of the plurality of pages is performed after the operation is performed, and the non-volatile memory controls the non-volatile memory such that when the LSB program operation for the second page is performed, And stores information about data programmed in one page in the spare area of the second page. The nonvolatile memory device according to the embodiment of the present invention can perform the recovery operation at a high speed when the recovery operation is performed after the power is turned off.

Semiconductor device

반도체 장치는 제 1 및 제 2 소자와, 차광 소자 및 비교기를 포함한다. 제 1 및 제 2 소자는 동일한 기판위에 형성되고, 자외선의 조사시 전기적 특성이 변화하며, 변화된 상태를 유지한다. 제 1 소자는 제 2 소자의 배열과 동일한 배열을 갖는다. 차광 소자는 자외선을 차폐시키기 위하여 제 1 소자위에 형성된다. 비교기는 제 1 및 제 2 소자의 전기적 특성들을 비교하여 비교 결과에 근거하여 이상 검출 신호를 출력한다.