Low thermal expansion filler, method for preparing the same and glass composition

An object of the present invention is to provide a low thermal expansion filler for low thermal expansion glasses which has a low coefficient of thermal expansion and exhibits superior flowability in a molten state, and a glass composition containing the same. It has been found that a low thermal expansion filler composed of a hexagonal zirconium phosphate powder where a specific particle size of 0.8 μm to 50 μm is 95% or more on a volume basis has excellent low thermal expansion property and excellent flowability, and a glass composition containing the filler has been accomplished.

Lead-Free Low Melting Point Glass Composition

Disclosed is a lead-free, low melting point glass composition, which is characterized by being substantially free from a lead component and comprising 0-8 mass % of SiO 2 , 2-12 mass % of B 2 O 3 , 2-7 mass % of ZnO, 0.5-3 mass % of RO (MgO+CaO+SrO+BaO), 0.5-5 mass % of CuO, 80-90 mass % of Bi 2 O 3 , 0.1-3 mass % of Fe 2 O 3 , and 0.1-3 mass % of Al 2 O 3 . This glass composition is not easily crystallized at high temperatures and is stable. Therefore, it is useful as an insulating coating material and a sealing material for electronic material substrates.

HIGH PRESSURE DISCHARGE LAMP

A high pressure discharge lamp of the present invention is provided with a light-emitting bulb comprising a light-emitting part and sealing sections; metal foils embedded within the sealing sections; and a pair of electrodes having one end protruding into the light-emitting part and having the other end embedded in the corresponding sealing section and joined to the corresponding metal foil. An embedded length L (mm) of the electrodes that is defined by the length between a light-emitting part side end of the metal foil and the border section between the protruding section and the embedded section of the electrode, and the temperature T (° C.) at the joint region of the electrode and the metal foil are set to satisfy 1.8≦2.8 and T≦970. 1. A high pressure discharge lamp comprising:a light-emitting bulb including a light-emitting part, and first and second sealing sections interposing the light-emitting part;first and second metal foils embedded in the first and second sealing sections, respectively;first and second electrodes each having one end protruding into the light-emitting part and having the other end embedded in the corresponding one of the first and second sealing sections and joined to the corresponding one of the first and second metal foils; anda sub-mirror covering at least a portion on a second electrode side of the light-emitting bulb without covering the first electrode side of the light-emitting bulb, whereinthe light-emitting bulb comprises quartz glass, and an embedded length L (mm) of the second electrode that is defined as a distance from a border section between a protruding section and an embedded section of the second electrode to a light-emitting part side end of the second metal foil, and a temperature T (° C.) at a joint region of the second electrode and the second metal foil during a discharging of the lamp satisfy 1.8≦L≦2.8 and T≦970 so that the quartz glass and the second metal foil do not detach by the discharging of the lamp.2. The ...

FASTENING DEVICE

A fastening device is provided that includes a semiconductor body with an integrated circuit, and a dielectric passivation layer formed on the surface of the semiconductor body, and a trace formed underneath the passivation layer, and an oxide layer formed beneath the trace, and a connecting component that forms a frictional connection between a component formed above the passivation layer and the semiconductor body, wherein a formation passing through the passivation layer and the oxide layer and having a bottom surface is formed, and a conductive layer is formed on the bottom surface and the connecting component forms an electrical connection between the conductive layer and the component. 1. A fastening device comprising:a semiconductor body with an integrated circuit;a dielectric passivation layer provided on the surface of the semiconductor body;a trace provided underneath the passivation layer;an oxide layer provided beneath the trace;a connecting component that forms a frictional connection between a component arranged above the passivation layer and the semiconductor body;a formation passing through the passivation layer and the oxide layer, the formation having a bottom surface; anda conductive layer provided on the bottom surface and/or on a lateral surface of the formation, the connecting component having an organic polymer and forms an electrical connection between the conductive layer and the component,wherein the component is provided as a first part and the connecting component is provided as a second part of an integrated component formed underneath the passivation layer.2. The fastening device according to claim 1 , wherein one elevation is formed on the bottom surface.3. The fastening device according to claim 2 , wherein a plurality of elevations are formed on the bottom surface.4. The fastening device according to claim 2 , wherein the elevation is implemented as a tungsten plug.5. The fastening device according to claim 2 , wherein the elevation ...

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

Provided is a resin sealed semiconductor device with improved reliability. After positioning a cap (lid) so as to cover semiconductor chips and wires, resin is supplied into a space formed by the cap, so that a sealing body is formed to cover the semiconductor chips and the wires. In the step of forming the sealing body, the resin is supplied from an opening formed at a corner of the cap in the planar view. The sealing body is exposed at the corner of the cap, so that the exposed part of the sealing body can be kept away from the wires. 1. A manufacturing method of a semiconductor device , comprising the steps of:(a) providing a lead frame having a chip mounting portion and a plurality of leads arranged around the chip mounting portion;(b) after the step (a), mounting a semiconductor chip over the chip mounting portion, said semiconductor chip having a front surface, a plurality of electrodes formed over the front surface, and a back surface opposite to the front surface;(c) after the step (b), electrically connecting the leads with the electrodes of the semiconductor chip via a plurality of wires;(d) after the step (c), arranging a lid so as to cover the semiconductor chip and the wires, and bonding the lid to the leads by a sealant; and(e) after the step (d), supplying resin into a space inside the lid with the semiconductor chip arranged therein, thereby sealing the wires and the semiconductor chip with the resin,wherein a shape in a plan view of the lid is comprised of a quadrangle having a first corner,wherein in the step (d), a gap between adjacent ones of the leads is filled with a part of the sealant, andwherein in the step (e), the resin is supplied into the space from the first corner not filled with the sealant.2. The manufacturing method of a semiconductor device according to claim 1 , wherein the lid is made of metal claim 1 , andwherein in the step (d), the lid and the leads are bonded together via the sealant made of insulating material such that the ...

APPARATUS AND METHODS FOR RESIZING ELECTRONIC DISPLAYS

Apparatus and methods are provided for resizing an electronic display that includes front and back plates, a perimeter seal spacing apart the plates and defining an enclosed cell area between the plates that includes an original display image area, image-generating medium sealed in the enclosed cell area, and electrical circuits on inner surfaces of the plates extending throughout the original display image area. For example, a cut line may be identified that intersects across the original display image area of the display. A laser may be directed adjacent the cut line to heat and/or separate leads of the electrical circuits adjacent the cut line. The display may be cut adjacent the cut line, e.g., before or after separating leads along the cut line, resulting in a target display portion with an exposed edge, and an excess display portion, and then the exposed edge may be sealed. 1. A method for resizing an electronic display , wherein the display comprises front and back plates , a perimeter seal spacing apart the plates and at least partially defining an enclosed cell area between the plates that comprises an original display image area , image-generating medium sealed in the enclosed cell area , and electrical circuits on inner surfaces of the plates extending throughout the original display image area , the method comprising:identifying a cut line that intersects across the original display image area of the display;directing a laser adjacent the cut line to sever the electrical circuits adjacent the cut line;cutting the display adjacent the cut line resulting in a target display portion with an exposed edge, and an excess display portion; andsealing the exposed edge.2. The method of claim 1 , wherein the laser is directed substantially parallel to the cut line such that the laser severs the electrical circuits along a line offset from the cut line by a predetermined distance.3. The method of claim 2 , wherein the laser severs the electrical circuits along a ...

FLAT PANEL DISPLAY AND METHOD OF MANUFACTURING THE SAME

Flat panel displays and methods of manufacturing the displays are disclosed. In one embodiment, the flat panel display includes: i) a substrate, ii) a display unit formed over the substrate, iii) an encapsulation substrate formed so as to face the display unit and iv) a sealing member formed between the substrate and the encapsulation substrate so as to substantially surround the display unit. The display may further include i) a wiring unit formed between the substrate and the encapsulation substrate so as to substantially overlap with the sealing member, wherein the wiring unit includes at least one via hole and ii) an inlet unit connected to the wiring unit and connectable to an external power source. 1. A flat panel display comprising:a substrate;a display unit formed over the substrate;an encapsulation substrate formed so as to face the display unit;a sealing member formed between the substrate and the encapsulation substrate so as to substantially surround the display unit;a single wiring unit formed between the substrate and the encapsulation substrate so as to substantially overlap with the sealing member, wherein the wiring unit includes at least one via hole, wherein the at least one via hole passes through the single wiring unit, and wherein the wiring unit surrounds the four sides of the display unit; andan inlet unit connected to the wiring unit and connectable to an external power source.2. The flat panel display of claim 1 , wherein the sealing member contacts the substrate through the via hole.3. The flat panel display of claim 1 , wherein the wiring unit is formed on the substrate claim 1 , and wherein the sealing member is formed between the wiring unit and the encapsulation substrate.4. The flat panel display of claim 1 , wherein the sealing member substantially fills the via hole.5. The flat panel display of claim 1 , wherein the sealing member contacts the encapsulation substrate.6. The flat panel display of claim 1 , wherein the sealing member ...

FEED-THROUGH AND METHOD FOR INTEGRATING THE FEED-THROUGH IN A HOUSING BY ULTRASONIC WELDING

A feed-through, in particular a feed-through which passes through a housing component of a housing, for example a battery housing, such as a battery cell housing. The housing component includes at least one opening through which at least one conductor, for example an essentially pin-shaped conductor, is guided. The pin-shaped conductor is at least partially surrounded by an insulator, for example made of a glass or a glass ceramic material. The at least one conductor connection, for example of the essentially pin-shaped conductor and/or of the housing component with the insulator, which is a glass or a glass ceramic material, is formed, the connection being an ultrasonic welding. 1. A feed-through , comprising:a housing component of a housing, said housing component having at least one opening;an insulator;at least one conductor which is at least partially surrounded by said insulator, said at least one conductor being guided through said at least one opening of said housing component; andan ultrasonic welding connection between said at least one conductor and at least one of said housing component and said insulator.2. The feed-through according to claim 1 , wherein said housing is a battery cell housing.3. The feed-through according to claim 1 , wherein said at least one conductor is an essentially pin-shaped conductor.4. The feed-through according to claim 1 , wherein said insulator is a material which is one of a glass material and a glass ceramic material.5. The feed-through according to claim 3 , wherein said conductor includes a head part and said insulator is positioned between said head part and said housing component.6. The feed-through according to claim 3 , wherein said conductor includes a metal.7. The feed-through according to claim 6 , wherein said metal is one of copper claim 6 , copper silicon carbide (CuSiC) claim 6 , a copper alloy claim 6 , aluminum claim 6 , aluminum silicon carbide (AlSiC) claim 6 , an aluminum alloy claim 6 , nickel-iron (NiFe ...

SEALING APPARATUS AND METHOD OF MANUFACTURING FLAT DISPLAY DEVICE USING THE SAME

A sealing apparatus and a method of manufacturing a flat display device using the sealing apparatus. The sealing apparatus to attach a first substrate and a second substrate to each other using an attachment member disposed between the first and second substrates, the sealing apparatus comprises a stage on which the first substrate is seated, a halogen lamp irradiating light, and a reflector reflecting light irradiated from the halogen lamp to the attachment member. 136-. (canceled)37. A method of sealing a first substrate and a second substrate , the method comprising:converging irradiated light onto an attachment member disposed between a first substrate and second substrate so as to define cells; andsimultaneously melting the attachment member for multiple cells while irradiating the light onto the attachment member to seal the first substrate and the second substrate.38. The method of claim 37 , further comprising hardening the attachment member melted by the irradiated light to attach the first substrate and the second substrate to each other.39. The method of claim 37 , wherein the converged irradiated light is irradiated across a first direction that is a whole section area of the first substrate covering multiple cells.40. The method of claim 39 , further comprising irradiating light in a second direction that is not parallel to the first direction while simultaneously irradiating light across the first direction by moving the light irradiated across the first direction in the second direction.41. The method of claim 37 , wherein the attachment member is a frit material. This application claims the benefit of Korean Application No. 10-2009-0033189, filed Apr. 16, 2009 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.1. Field of the InventionAspects of the present invention relate to a sealing apparatus and a method of manufacturing a flat display device using the sealing apparatus.2. Description of the ...

SURFACE MOUNT CHIP

A surface mount chip including, on the side of a surface, first and second pads of connection to an external device, wherein, in top view, the first pad has an elongated general shape, and the second pad is a point-shaped pad which is not aligned with the first pad. 1. A surface mount chip comprising , on the side of a surface , only two pads , a first pad having an elongated shape , and a second point-shaped pad.2. The chip of claim 1 , wherein claim 1 , in top view claim 1 , the largest dimension of the first pad is greater by at least a factor 2 than that of the second pad.3. The chip of having claim 1 , in top view claim 1 , a rectangular general shape.4. The chip of claim 3 , wherein the first pad is substantially parallel to the two shortest chip edges.5. The chip of claim 3 , wherein the second pad is approximately equidistant from the two longest chip edges.6. The chip of claim 1 , wherein claim 1 , in top view claim 1 , the largest dimension of the first pad is at least equal to half the smallest width of the chip.7. The chip of claim 1 , wherein claim 1 , in top view claim 1 , the largest dimension of the second pad is smaller than 10 percent of the smallest width of the chip.8. The chip of claim 1 , wherein claim 1 , in top view claim 1 , the smallest width of the rectangle circumscribed in the first pad is substantially equal to the largest dimension of the second pad.9. The chip of claim 1 , wherein the first pad comprises two conductive bumps or drops interconnected by a conductive strip.10. The chip of claim 1 , wherein the second pad comprises a conductive bump or drop. This application claims the priority benefit of French patent application serial number 12/57536, filed on Aug. 2, 2012, which is hereby incorporated by reference to the maximum extent allowable by law.1. Technical FieldThe present disclosure relates to the field of electronic chips. It more specifically aims at surface mount (or flip-chip) chips, that is, chips comprising, on the ...

Die Attach Methods and Semiconductor Devices Manufactured based on Such Methods

A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers. 1. A semiconductor device , comprising:a carrier;a power semiconductor die that comprises first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively;a die attach material arranged between the carrier and the first electrode,wherein the die attach material forms a fillet at the side surface of the power semiconductor die,wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die,wherein the height of the power semiconductor die is a length of the side surface, andwherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.2. The semiconductor device of claim 1 , wherein the height of the power semiconductor die is less than about 400 micrometers.3. The semiconductor device of claim 2 , wherein the height of the power semiconductor die is less than about 150 micrometers.4. The semiconductor device of claim ...

Semiconductor Package

A semiconductor package includes a semiconductor chip including a body, a connection pad, a passivation film, a first connection bump disposed, and a first coating layer; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer, a redistribution layer, and a connection via. The first connection bump includes a low melting point metal, the redistribution layer and the connection via include a conductive material, and the low melting point metal has a melting point lower than a melting point of the conductive material. 1. A semiconductor package , comprising:a semiconductor chip including a body having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a passivation film disposed on the active surface of the body and covering at least a portion of the connection pad, a first connection bump disposed on the passivation film and electrically connected to the connection pad, and a first coating layer disposed on the passivation film and covering at least a portion of a side surface of the first connection bump;an encapsulant covering at least a portion of the semiconductor chip; anda connection structure including an insulating layer disposed on the first coating layer of the semiconductor chip, a redistribution layer disposed on the insulating layer, and a connection via passing through the insulating layer and electrically connecting the first connection bump to the redistribution layer,wherein the first connection bump includes a low melting point metal,the redistribution layer and the connection via include a conductive material, andthe low melting point metal has a melting point lower than a melting point of the conductive material.2. The semiconductor package of claim 1 , wherein the low melting point metal includes a solder claim 1 , andthe conductive material includes copper (Cu).3. The semiconductor package of claim 1 , wherein a ...

METHOD OF MANUFACTURING FLAT PANEL DISPLAY

A method of manufacturing a flat panel display is disclosed. In one aspect, the method includes forming a plurality of display elements over a first substrate and forming over the first substrate or a second substrate a plurality of sealing units respectively surrounding the display elements. The method further c includes arranging the first and second substrates to face each other and emitting a laser beam to the sealing units so as to bond the first and second substrates. The emitting includes (a) emitting a first laser beam, from a first laser source, clockwise or counterclockwise along perimeters of the sealing units and (b) substantially simultaneously emitting a second laser beam, from a second laser source, to facing sides of adjacent ones of the sealing units.

Manufacturing Method for Glass Panel with Glazing Gasket and Glazing Gasket Molding Apparatus

In a manufacturing method for a glass panel with a gasket, an elastic member is placed on a table, and a multilayer glass panel is placed thereupon. A die is pressed against a top surface of the multilayer glass panel, thereby compressing the elastic member and glazing gasket molding material together with adhesive ejected from the application nozzle and applied to the top surface of the multilayer glass panel. 1. A manufacturing method for a glass panel with a glazing gasket for ejecting glazing gasket molding material together with adhesive from an application nozzle onto a periphery of a top surface of the glass panel that is facing upwards and placed on a table , the glass panel and the application nozzle being moved relative to one another to apply the glazing gasket molding material , the method comprising:placing an elastic member on the table, the elastic member being made from an elastically deformable material;placing the glass panel on the elastic member; andapplying the glazing gasket molding material to the top surface of the glass panel by ejecting the glazing gasket together with the adhesive slanting downward from an outlet to the rear in a direction of movement of the application nozzle, while a portion of the application nozzle in which the outlet is formed is pressed against the top surface of the glass panel to compress the elastic member.2. The manufacturing method for a glass panel with a glazing gasket according to claim 1 , wherein the glazing gasket molding material is applied by starting at an application starting point located on the fixture plate and by finishing at an application finishing point located on the fixture s late the method further comprising:detachably attaching a fixture plate to a portion of the periphery of the top surface of the glass panel so that the fixture plate is immoveable,applying the glazing gasket molding material together with the adhesive to the periphery of the top surface of the glass panel,cutting portions ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

In a method for manufacturing a semiconductor device according to the present invention, as shown in FIG. (A), a case () including a first terminal () is placed on a working table () with an opening () formed at the bottom of the case (). Subsequently, as shown in FIG. (B), a plurality of packages () including second terminals () are placed on the working table () through the opening () of the case (), forming a clearance () between the first terminal () and the second terminal (). As shown in FIG. (C), a bonding material () is disposed in the clearance () so as to electrically connect the first terminal () and the second terminal (). Thus, the exposed surfaces of the packages () in the opening () of the case () are aligned at the same height, thereby reducing variations in thermal resistance among the packages (). 1. A method for manufacturing a semiconductor device including a plurality of packages disposed in a resin-molded case , the package containing a power semiconductor element ,the method comprising:placing the case on a working table with an opening formed at a bottom of the case, the case including a first terminal with one end internally drawn along the bottom of the case and connected to the power semiconductor element;placing the package on the working table through the opening of the case, the package including a second terminal connected to the power semiconductor element, and forming a clearance between the first terminal of the case and the second terminal of the package; andelectrically connecting the first terminal and the second terminal with a bonding material disposed in the clearance.2. A method for manufacturing a semiconductor device including a plurality of packages disposed in a resin-molded case , the package containing a power semiconductor element ,the method comprising:placing the package on a working table, the package including a second terminal connected to the power semiconductor element, the second terminal being extended along ...

TIM STRAIN MITIGATION IN ELECTRONIC MODULES

A heat spreading lid, including a lid body, a wing portion, where the wing portion flexibly moves independently from the lid body. 1. A heat spreading lid , comprising:a lid body; anda wing portion;wherein the wing portion flexibly moves independently from the lid body.2. The lid according to claim 1 , wherein a gap is formed between the wing portion and a portion of the lid body above the wing portion such that the gap separates the wing portion and the portion of the lid body in a vertical direction.3. The lid according to claim 1 , wherein the wing portion has a thickness less than a thickness of a center portion of the lid body.4. The lid according to claim 1 , wherein the lid body comprises a lid insert and a lid frame in which the lid insert is disposed claim 1 , andwherein the wing portion comprises an edge portion of the lid insert.5. The lid according to claim 4 , wherein the wing portion comprises a corner of the lid insert.6. The lid according to claim 1 , wherein the wing portion is adapted to overlap a corner of a die.7. The lid according to claim 1 , wherein the wing portion is flexible independently from a portion of the lid body above the wing portion.8. The lid according to claim 1 , wherein the lid includes a plurality of ones of the wing portion claim 1 , andfurther comprising a trench extending between two adjacent wing portions.9. A device comprising:a die;a thermal interface material disposed on the die; a lid body; and', 'a wing portion;, 'a heat spreading lid disposed on the thermal interface material opposite the die, the lid comprisingwherein the wing portion flexibly moves independently from the lid body.10. The device according to claim 9 , wherein a gap is formed between the wing portion and a portion of the lid body above the lid portion.11. The device according to claim 9 , wherein the wing portion is connected to a wing pedestal claim 9 , the wing pedestal being disposed between the lid body and the die.12. The device according to ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening. 1. A semiconductor package comprising:a support frame having a first surface and a second surface opposing each other, and including a cavity connecting the first and second surfaces;a semiconductor chip disposed in the cavity, and having an active surface on which contact pads are arranged; anda connection member disposed on the second surface of the support frame and on the active surface of the semiconductor chip,wherein the semiconductor chip includes:a first insulating film disposed on the active surface and exposing the contact pads; a RDL pattern connected to the contact pads and extending onto the first insulating film; a second insulating film disposed on the active surface and including a first opening exposing a connection region of the RDL pattern; and a conductive crack preventing layer disposed on the connection region and having an outer peripheral region extending to a portion of the second insulating film around the first opening, andthe connection member includes:an insulating layer disposed on the second surface of the support frame and ...

INTEGRATED DECOUPLING CAPACITORS

Embodiments herein describe providing a decoupling capacitor on a first wafer (or substrate) that is then bonded to a second wafer to form an integrated decoupling capacitor. Using wafer bonding means that the decoupling capacitor can be added to the second wafer without having to take up space in the second wafer. In one embodiment, after bonding the first and second wafers, one or more vias are formed through the second wafer to establish an electrical connection between the decoupling capacitor and bond pads on a first surface of the second wafer. An electrical IC can then be flip chipped bonded to the first surface. As part of coupling the decoupling capacitor to the electrical IC, the decoupling capacitor is connected between the rails of a power source (e.g., VDD and VSS) that provides power to the electrical IC. 1. A combination wafer , comprising:a first wafer comprising an electrically driven component; anda second wafer comprising a decoupling capacitor, wherein the first wafer and the second wafer are directly bonded along a wafer bond line,wherein the first wafer comprises a plurality of vias that electrically connect the decoupling capacitor in the second wafer to bond pads disposed on a first side of the first wafer that is opposite the wafer bond line.2. The combination wafer of claim 1 , wherein an insulator of the first wafer is directly bonded to an insulator of the second wafer at the wafer bond line.3. The combination wafer of claim 2 , wherein the plurality of vias extend through the insulator of the first wafer and the insulator of the second wafer.4. The combination wafer of claim 2 , wherein a first plurality of metallic connections in the insulator of the first wafer are directly bonded to a second plurality of metallic connections in the insulator of the second wafer at the wafer bond line claim 2 , wherein first vias of the plurality of vias are coupled to the first plurality of metallic connections and second vias of the plurality of vias ...

METHOD FOR MANUFACTURING ALL-GLASS SOLAR COLLECTOR TUBE WITHOUT EXHAUST TAIL TUBE

A method for manufacturing an all-glass solar heat collecting tube without a tail pipe. The bottom of one end of an inner glass tube plated by a selective absorbing coating layer is rounded, the other end is connected to a first glass outer tube. The bottom of one end of a second glass outer tube is rounded and the other end is flared. The connected inner glass tube/first glass outer tube is inserted into the second glass outer tube. A gap is formed between the first glass outer tube and the second glass outer tube to serve as an air exhausting channel. The first glass outer tube is inserted into the flared opening of the second glass outer tube. The contact point between the first glass outer tube and the second glass outer tube is heated to frit seal and butt joint. 1. A method for manufacturing an all-glass solar collector tube without an exhaust tail tube , comprising the steps of:rounding a bottom of one end of an inner glass tube plated with a selective absorption coating, and sealing a first outer glass tube on the other end thereof, wherein a length of the first outer glass tube is not larger than a length of the inner glass tube;rounding a bottom of end of a second outer glass tube, and flaring the other end thereof;inserting the inner glass tube sealed with the first outer glass tube into the second outer glass tube;abutting joint, sealing and vacuumizing an exhaust groove of an exhaust platform and a flaring site of the second outer glass tube, to form a gap between the first outer glass tube and the second outer glass tube to serve as an exhaust passage;after vacuumizing and exhausting, propelling the first outer glass tube using a mechanical device in the exhaust groove to insert the first outer glass tube into a flared opening of the second outer glass tube, wherein the first outer glass tube is in contact with the second outer glass tube;heating a contact point of the first outer glass tube and the second outer glass tube to achieve a frit seal and ...

LENS CAP FOR OPTICAL MODULE, OPTICAL MODULE, AND METHOD FOR MANUFACTURING LENS CAP FOR OPTICAL MODULE

A lens cap for an optical module includes: a barrel of a metal material; and a press lens of glass and held in the barrel. The coefficient of linear expansion of the glass is 6 to 8 ppm/K, and the coefficient of linear expansion of the metal material is at least 10 ppm/K at 150° C. to 800° C. and no more than 8 ppm/K at up to 100° C. or below. 1. A lens cap for an optical module comprising:a barrel of a metal material; and coefficient of linear expansion of the glass is 6 to 8 ppm/K, and', 'coefficient of linear expansion of the metal material is at least 10 ppm/K at 150° C. to 800° C. and no larger than 8 ppm/K at up to 100° C., 'a press lens of glass and held in the barrel, wherein'}2. The lens cap for an optical module according to claim 1 , wherein the metal material is selected from the group consisting of invar claim 1 , super invar claim 1 , and stainless steel invar.3. An optical module comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the lens cap for an optical module according to ; and'}an optical semiconductor element located at a position where the press lens in the barrel converges light.4. The optical module according to claim 3 , further comprising helium filling the barrel claim 3 , wherein leakage rate of the helium from the barrel is no more than 1×10Pa·m/s.5. A method for manufacturing a lens cap for an optical module comprising:forming a barrel of a metal material; and coefficient of linear expansion of the glass is 6 to 8 ppm/K, and', 'coefficient of linear expansion of the metal material is at least 10 ppm/K at 150° C. to 800° C. and 8 ppm/K at up to 100° C., 'molding glass into the barrel, by pressurization to form a press lens held in the barrel, wherein'}6. The method for manufacturing a lens cap for an optical module according to claim 5 , wherein claim 5 , during the pressurization claim 5 , the temperature is in a range from 600° C. to 800° C. 1. Field of the InventionThe present invention relates to a lens cap for an optical ...

SEMICONDUCTOR DEVICE COMPONENT AND SEMICONDUCTOR DEVICE

A semiconductor device component includes a first portion having a first hole usable as a nut insertion hole, and a second portion having a second hole adjacent to the first hole with a wall interposed therebetween. The first hole includes a first surface facing the wall, a second surface adjacent to the first surface, a third surface adjacent to the second surface, a fourth surface adjacent to the third surface and facing the first surface, a fifth surface adjacent to the fourth surface and facing the second surface, and a sixth surface adjacent to the fifth surface and the first surface and facing the third surface. A distance between the first and fourth surfaces is greater than a distance between the second and fifth surfaces, and greater than a distance between the third and sixth surfaces. 1. A case for mounting a semiconductor device , comprising a recess and a terminal access opening separated by a dividing wall , a plurality of walls within the recess in mirror symmetry about a center of the recess , one of the walls defining a dividing wall that separates the recess from the terminal access opening ,wherein a first width of the recess measured between the dividing wall and another one of the walls through the center of the recess, is larger than a second width of the recess measured between two other walls of the recess and through the center of the recess.2. The case of claim 1 , wherein the recess is generally hexagonal in profile.3. The case of claim 2 , wherein the recess includes a plurality of notches claim 2 , each extending outwardly with respect to the center of the recess at an intersection between two of the walls.4. The case of claim 2 , wherein the notches include a first notch at a first intersection between the dividing wall and a first wall claim 2 , which is one of the walls adjacent to the dividing wall and a second notch at a second intersection between the dividing wall and a second wall claim 2 , which is another one of the walls ...

GLASS SYSTEM FOR HERMETICALLY JOINING CU COMPONENTS, AND HOUSING FOR ELECTRONIC COMPONENTS

An housing for electronic components, such as LEDs and/or FETs, is provided. The housing has a base body having an upper surface that at least partially defines a mounting area for an electronic functional element, such that the base body provides a heat sink for the electronic functional element. The base body has a lower surface and a lateral surface and includes a connecting body for the electronic functional element, which is joined to the base body a glass layer formed by an alkali titanium silicate glass. 128-. (canceled)29. An housing for accommodating an electronic functional element , comprising:a base body made of metal and having an upper surface that at least partially defines a mounting area for the electronic functional element so that said base body forms a heat sink for the electronic functional element, the base body having a lower surface and a lateral surface; andat least one connecting body made of metal that is joined to the base body at least by one glass layer, wherein the at least one glass layer is formed by an alkali titanium silicate glass.35. The housing as claimed in claim 29 , wherein the at least one glass layer has a thickness of more than 30 μm.36. The housing as claimed in claim 29 , wherein the at least one glass layer has a thickness a range from 30 μm to 2000 μm.37. The housing as claimed in claim 29 , wherein the at least one glass layer is disposed in a location selected from the group consisting of between the lateral surface of the base body and the at least one connecting body claim 29 , between the upper surface of the base body and the at least one connecting body claim 29 , between the lower surface of the base body and the at least one connecting body claim 29 , and combinations thereof.38. The housing as claimed in claim 29 , wherein at least portions of the at least one connecting body are arranged at a location selected from the group consisting of the upper surface of the base body claim 29 , at the lower surface of ...

METHOD AND APPARATUS FOR APPLYING SOLDER TO A WORK PIECE

The invention concerns a method and an apparatus for the application of solder onto a work piece, wherein the solder is soldered on at a soldering temperature Tand subject to the influence of ultrasound. In order to be able to solder without difficulties the solder onto work pieces that exhibit sensitivity to breakage it is proposed that the solder is heated, is applied to the work piece that is supported in particular in a spring-mounted manner, and is soldered-on subject to the influence of ultrasound. 115-. (canceled)1. An apparatus for the application and soldering-on of a solder in a soldering zone onto a work piece , in particular onto a semiconductor component such as a solar cell , encompassing a soldering supply device , a heating device for the solder , an ultrasound sonotrode as well as a transport installation for the transport of the work piece relative to the heating device as well as also the ultrasound sonotrode , whereinthe transport installation transports the work piece through the soldering zone in a spring-mounted manner by means of the pressing-on of the same in the direction of the ultrasound sonotrode.216. An apparatus according to claim , wherein the transport installation features a first and second transport element between which the work piece is fixed in a clamped manner , whereby the first transport element is actively driven and the second transport element is driven by means of frictional engagement with the first transport element or the work piece or by means of its own additional drive.317. An apparatus according to claim , wherein the first and the second transport elements are endless flat elements or endless round elements such as flat belts or round sections.417. An apparatus according to claim , wherein the first and/or the second transport element features two endless flat elements or endless round elements that are spaced apart to each other and that are guided respectively by guide rollers that originate from a common axis. ...

LAMP COMPRISING MULTIPLE COMPONENT DESIGNS AND CONSTRUCTIONS

The present invention provides a bulb (′) an excitation chamber (′) a ferrite core (′), a spool (); an assembly or subassembly of such components, and a lamp () for producing electromagnetic radiation, such as in the light spectrum, UV or IR. 154-. (canceled)55. An excitation chamber assembly for an electrodeless electromagnetic radiation source or lamp , said excitation chamber assembly including an excitation chamber which is formed from a generally U-shaped tube which has ends which are adapted to be joined to ends of a tubular lamp bulb;a flange which connects to said generally U-shaped tube or said tubular lamp bulb when joined to said generally U-shaped tube;said excitation chamber assembly including an amalgam housing which is connected to said generally U-shaped tube;said excitation chamber assembly including or adapted to include an electromagnetic circuit which when activated will create an inductively coupled plasma in said excitation chamber and said tubular lamp bulb when joined; andsaid flange adapted to provide thermal isolation of said electromagnetic circuit when present and the amalgam housing from electromagnetic radiation which will be generated from the tubular lamp bulb.56. An excitation chamber assembly as claimed in claim 55 , wherein there is also included one or a combination of two or more of the following features: an electromagnetic core which is part of said electromagnetic circuit when assembled; a field coil which is part of said electromagnetic circuit when assembled; a thermal barrier coating; a graphene coating on the outside of said excitation chamber; the outside of the U-shaped tube is coated with graphene.57. An excitation chamber assembly as claimed in claim 55 , wherein said electromagnetic circuit when present and activated is a toroidal dipole magnetic circuit with a centrally located field coil or coils.58. An excitation chamber assembly as claimed in claim 55 , wherein said electromagnetic circuit when present utilises a ...

Packaging of Semiconductor Devices

A packaged semiconductor device comprising a stack including a die comprising a functional circuit, and a cap which is wafer bonded to the die for protecting the functional circuit as well as a mold component for packaging the stack. At least the cap and/or the die comprises at least one groove at least partially in contact with the mold component, for increasing adhesion of the mold component to the stack. A corresponding method for manufacturing such a packaged device also is described. 110-. (canceled)11. A packaged semiconductor device comprising a die comprising a functional circuit,', 'a cap having a top surface and a bottom surface, the cap being attached with its bottom surface to the die for protecting the functional circuit, and', 'a mold component for overmolding the stack except for an access window, wherein at least the cap and/or the die comprises at least one groove in an upstanding wall remote from the top surface of the cap, the at least one groove having slanted surfaces and being at least partially in contact with the mold component, for increasing adhesion of the mold component to the stack., 'a stack comprising'}12. The packaged semiconductor device of claim 11 , wherein both the cap and the die comprise at least one groove.13. The packaged semiconductor device according to claim 11 , wherein at least one dimension of the at least one groove is between 50 μm and 150 μm.14. The packaged semiconductor device according to claim 11 , wherein the cap comprises at least one cavity arranged to face the die.15. The packaged semiconductor device according to claim 11 , wherein the functional circuit is a sensor circuit.16. The packaged semiconductor device according to claim 11 , wherein the cap is a semiconductor cap.17. A method for obtaining a packaged semiconductor device claim 11 , the method comprisingobtaining a die comprising a functional circuit and a cap having a top surface and a bottom surface, at least one of the die and/or the cap having at ...

THERMAL MATCHED COMPOSITE DIE

A thermal matched composite material, suitable for use as a die is described. In one example, the material includes a metal plate and a substrate having a coefficient of thermal expansion (CTE) lower than the metal plate to carry microelectronic circuits. An adhesive layer between the substrate and the metal plate physically attaches the metal plate to the substrate so that the combined metal plate and substrate have a higher CTE than the substrate alone. 1. An apparatus comprising:a metal plate;a substrate having a coefficient of thermal expansion (CTE) lower than the metal plate to carry microelectronic circuits; andan adhesive layer between the substrate and the metal plate to physically attach the metal plate to the substrate so that the combined metal plate and substrate have a higher CTE than the substrate alone.2. The apparatus of claim 1 , wherein the substrate is formed of at least one of silicon claim 1 , glass claim 1 , germium claim 1 , III-IV claim 1 , silicon-on-insulator claim 1 , and ceramic.3. The apparatus of claim 1 , wherein the substrate is to carry solder and wherein the adhesive layer is bonded to metal and the substrate at a temperature lower than the melting temperature of the solder.4. The apparatus of claim 1 , wherein the adhesive layer has a silicon preferential portion to bond to the silicon and a metal preferential portion to bond to the metal claim 1 , the two portions being bonded to each other.5. The apparatus of claim 4 , wherein the silicon preferential portion comprises a first layer applied to the substrate and the metal preferential portion comprises a second layer applied to the metal plate and wherein the two layers are pressed together to bond the silicon substrate to the metal plate.6. The apparatus of claim 5 , wherein the first layer comprises epoxy.7. The apparatus of claim 6 , wherein the first layer comprises a zirconium alkoxide with epoxy functionalize silane to for a sol-gel network.8. The apparatus of claim 4 , ...

DIE CRACK DETECTION

Systems and methods for die crack detection are disclosed. In one exemplary embodiment, a die includes a first conductive segment, an intermediate conductive segment, and a second conductive segment. The crack detection ring substantially surrounds the die according to a serpentine path having a plurality of legs, wherein each leg intersects the first conductive segment at a first intersection, an intermediate conductive segment at an intermediate intersection and a second conductive segment at a second intersection, wherein the intermediate intersection is horizontally offset from at least the first intersection and the second intersection. 1. A die with an integrated circuit formed thereon , the die comprising:a first conductive segment that defines part of a crack detection ring;a second conductive segment that defines part of the crack detection ring; andan intermediate conductive segment, between the first conductive segment and the second conductive segment, that defines part of the crack detection ring; intersects the first conductive segment at a first intersection;', 'intersects the second conductive segment a second intersection; and', 'intersects the intermediate conductive segment at an intermediate intersection horizontally offset from at least one of the first intersection and the second intersection., 'wherein the crack detection ring substantially surrounds the integrated circuit according to a serpentine path having a plurality of legs, each of which2. The die of claim 1 , wherein at least one of the plurality of legs comprises a horizontal portion extending along a portion of the intermediate conductive segment claim 1 , wherein the first intersection is vertically aligned with a first end of the portion and the second intersection is vertically aligned with a second end of the portion.3. The die of claim 1 , wherein in each of the plurality of legs claim 1 , the first conductive segment intersects claim 1 , at the first intersection claim 1 , with ...

FIXTURE TO CONSTRAIN LAMINATE AND METHOD OF ASSEMBLY

A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions. 1. A method of joining a chip on a laminate , comprising:positioning a laminate having a top surface, a bottom surface and sides on a surface of a first plate of a fixture and directly abutting against a stepped feature;positioning a second plate of the fixture on the top surface of the laminate;mating the first plate and the second plate together;placing a chip on the laminate; andreflowing solder to connect the chip on the laminate.2. The method of claim 1 , wherein when the first plate and the second plate are mated and the laminate is directly abutting the stepped feature claim 1 , the laminate is constrained in X claim 1 , Y and Z directions during assembly processes.3. The method of claim 1 , wherein the first plate and the second plate are mated by one or more mechanical fasteners.4. The method of claim 1 , wherein the placing a chip on the laminate comprising placing the chip on the laminate through an opening in the first plate.5. The method of claim 1 , wherein the first plate and the second plate apply pressure to the top surface claim 1 , the bottom surface and all sides of the laminate to prevent expansion within the fixture.6. The method of claim 1 , wherein a chip is bonded to ...

INTEGRATED DEVICE HAVING GDT AND MOV FUNCTIONALITIES

Integrated device having GDT and MOV functionalities. In some embodiments, an electrical device can include a first layer and a second layer joined with an interface, with each having an outer surface and an inner surface, such that the inner surfaces of the first and second layers define a sealed chamber therebetween. The electrical device can further include an outer electrode implemented on the outer surface of each of the first and second layers, and an inner electrode implemented on the inner surface of each of the first and second layers. The first layer can include a metal oxide material such that the first outer electrode, the first layer, and the first inner electrode provide a metal oxide varistor (MOV) functionality, and the first inner electrode, the second inner electrode, and the sealed chamber provide a gas discharge tube (GDT) functionality. 1. An electrical device comprising:a first layer and a second layer joined with an interface that includes a glass seal, each layer having an outer surface and an inner surface, such that the inner surfaces of the first and second layers and the interface define a sealed chamber enclosing a gas therein;an outer electrode implemented on the outer surface of each of the first and second layers;an inner electrode implemented on the inner surface of each of the first and second layers; andwherein the first layer includes a metal oxide material such that the first outer electrode, the first layer and the first inner electrode form a first metal oxide varistor (MOV), and the first inner electrode, the second inner electrode and the sealed chamber with the gas form a gas discharge tube (GDT).2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. The electrical device of claim 1 , wherein the second layer includes a metal oxide material such that the second inner electrode claim 1 , the second layer and the second outer electrode form a second MOV claim 1 , such that the electrical device ...

RADIATION GENERATING TUBE, RADIATION GENERATING APPARATUS, RADIOGRAPHY SYSTEM AND MANUFACTURING METHOD THEREOF

The present invention relates to a radiation generating tube. The radiation generating tube includes an envelope including an insulating tubular member having at least two openings, a cathode connected to one of the openings of the insulating tubular member, and an anode connected to the other of the openings of the insulating tubular member. At least one of the cathode and the anode and the insulating tubular member are bonded at a bonded portion with an electrically conductive bonding member; and the bonded portion bonded with the electrically conductive bonding member is coated with a dielectric layer. 1. A radiation generating apparatus comprising: an envelope including an insulating tube having a pair of tube ends, a cathode connected to one of the pair of tube ends, and an anode connected to the other of the pair of tube end;', 'an electron emitting source connected to the cathode;', 'a target connected to the anode; and', 'a conductive bonding member bonded between the insulating tube and at least any one of the cathode and the anode;, 'a radiation generating tube includinga conductive container grounded and accommodating the radiation generating tube;insulating liquid filled in a rest space between the conductive container and the radiation generating tube; anda dielectric member located outside of the insulating tube in the conductive container,wherein the dielectric member and the insulating liquid are located between the conductive bonding member and the conductive container.2. The radiation generating apparatus according to claim 1 , wherein the dielectric member relaxes electric field concentration at a bonded region bonded between the insulting tube and at least any one of the cathode and the anode via the conductive bonding member.3. The radiation generating apparatus according to claim 1 , wherein the conductive bonding member is shaped annularly and the dielectric member is shaped annularly.4. The radiation generating apparatus according to claim 1 ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHODS OF MANUFACTURING THE SAME

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component. 1. A semiconductor package structure , comprising:a substrate;a first electronic component disposed on the substrate, wherein the first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface;an interlayer on the upper surface of the first electronic component;a third electronic component attached to the upper surface of the first electronic component via the interlayer; andan encapsulant encapsulating the first electronic component and the interlayer;wherein the interlayer does not contact the lateral surface of the first electronic component.2. The semiconductor package structure of claim 1 , wherein the first edge of the first electronic component is a first recessed edge.3. The semiconductor package structure of claim 2 , wherein the first recessed edge comprises a first sub-edge connected to the upper surface and a second sub-edge connected to the lateral surface claim 2 , and wherein the interlayer does not contact the second sub-edge of the first recessed edge.4. The semiconductor package structure of claim 3 , wherein the interlayer does not contact the first sub-edge of the first ...

SYSTEM, A TANGENT PROBE CARD AND A PROBE HEAD ASSEMBLY FOR TESTING SEMICONDUCTOR WAFTER

A system for semiconductor wafer testing, a tangent probe card and a probe head assembly thereof. The system has a tangent probe card and a tester. Testing ends of the probe card are flat, hence the allowable alignment budget will always be more generous for the tangent probe card. The probes are held on the probe head assembly, and once the alignment is achieved accurately during manufacture, the alignment will remain stable throughout the whole life cycle. The probe has a greater CCC due to its larger cross section. The throughput of the tangent probes is higher than that of the conventional probe card since there is no need to move the pointed pin/structure. No pointed pin/structure needs to be repaired, and the flat bottom surface of the probe head assembly is easier to clean and maintain. 1. A probe head assembly for a tangent probe card , wherein the probe head assembly comprises:a plurality of probes, one end of each of which is a testing end, the other end of each of which is a connecting end, with the testing ends being flat;a probe holding portion, which holds the plurality of probes at the prescribed locations and makes the testing ends of the plurality of probes be flush with the bottom surface of the probe holding portion.2. The probe head assembly according to claim 1 , wherein the said probe holding portion comprises:a main body part, which is provided with a cavity for the plurality of probes to run through.3. The probe head assembly according to claim 2 , wherein the said probe holding portion further comprises:a peripheral part, which is located at the top edge of the main body part and is connected to the main body part.4. The probe head assembly according to claim 2 , wherein the main body part is provided with a plurality of through-holes on the bottom thereof;wherein the testing ends of the plurality of probes extend into the plurality of through-holes, and the said testing ends are flush with the bottom surface of the main body part.5. The ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder. 1. A semiconductor device comprising:a semiconductor element;a surface electrode formed on a surface of the semiconductor element;a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, the joining portion includes a first joining film;solder joined to the joining portion while avoiding the stress relieving portion;an external electrode joined to the joining portion through the solder; anda coating film covering the stress relieving portion so that the solder does not contact the stress relieving portion, the coating film is thinner than the solder,wherein the thickness of the first joining film is equal to or larger than 0.5 μm.2. The semiconductor device according to claim 1 , wherein the first joining film is formed of Ni.3. The semiconductor device according to claim 2 , wherein the joining portion includes an alloy portion formed of solder and Ni on the first joining film claim 2 , and a first intimate-contact film formed of Ti or Mo on the surface electrode.4. The semiconductor device according to claim 1 , wherein the surface electrode has an aluminum content of 95% or more.5. The semiconductor device according to claim 1 , wherein the stress relieving portion is formed so that a length from a portion bordering on the joining portion to an outermost peripheral portion is equal to or larger than 10 μm.6. A semiconductor device comprising:a semiconductor element;a surface electrode ...

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SAME

In a semiconductor apparatus, the apparatus is so arranged as to comprise: a semiconductor device having electrodes and wiring-interconnects on a main surface of a semiconductor chip; a first resin structure member, being placed on a side of the main surface of the semiconductor chip, constituting, in lateral and upward directions of a specific electrode of the semiconductor device, a hollow-body structure between the specific electrode and the first resin structure member; a second resin structure member covering an outer lateral side of the first resin structure member, and having the permittivity smaller than or equal to the permittivity of the first resin structure member; and an insulation film covering an outer lateral side of the second resin structure member, and having moisture permeability lower than that of the second resin structure member. 1. A semiconductor apparatus , comprising:a semiconductor device having electrodes and wiring-interconnects on a main surface of a semiconductor chip;a first resin structure member, being placed on a side of the main surface of the semiconductor chip, covering laterally and upwardly a specific electrode of the semiconductor device while separating apart from the specific electrode with a space;a second resin structure member, having permittivity smaller than or equal to permittivity of the first resin structure member, covering an outer lateral side of the first resin structure member while laterally and upwardly making contact with the first resin structure member; andan insulation film, having moisture permeability lower than that of the second resin structure member, covering an outer lateral side of the second resin structure member.2. The semiconductor apparatus as set forth in claim 1 , wherein wiring-interconnects being multilayered are placed above on the second resin structure member.3. A semiconductor apparatus claim 1 , comprising:a semiconductor device having electrodes and wiring-interconnects on a main ...

INTERLAYER FOR LAMINATED GLASS, AND LAMINATED GLASS

An interlayer film for laminated glass includes a first layer containing a polyvinyl acetal resin, a plasticizer, and silica particles; and a second layer containing a polyvinyl acetal resin and a plasticizer, wherein the second layer is disposed on a first surface side of the first layer and wherein a concentration of hydroxyl groups of the polyvinyl acetal resin in the second layer is higher than a concentration of hydroxyl groups of the polyvinyl acetal resin in the first layer. 1. An interlayer film for laminated glass , comprising:a first layer containing a polyvinyl acetal resin, a plasticizer, and silica particles; anda second layer containing a polyvinyl acetal resin and a plasticizer,wherein the second layer is disposed on a first surface side of the first layer andwherein a concentration of hydroxyl groups of the polyvinyl acetal resin in the second layer is higher than a concentration of hydroxyl croups of the polyvinyl acetal resin in the first layer.2. The interlayer film for laminated glass according to claim 1 ,wherein an absolute value of a difference between the concentration of hydroxyl groups of the polyvinyl acetal resin in the first layer and the concentration of hydroxyl groups of the polyvinyl acetal resin in the second layer is 5 mol % or greater.3. The interlayer film for laminated glass according to claim 2 ,wherein an absolute value of a difference between acetal resin. in the first layer and the concentration of hydroxyl groups of the polyvinyl acetal resin in the second layer is 10 mol % or greater.4. The interlayer film for laminated class according to claim 1 ,wherein the concentration of hydroxyl groups of the polyvinyl acetal resin in the second layer is 30 mol % or greater.5. The interlayer film for laminated glass according to claim 4 ,wherein the concentration of hydroxyl groups of the polyvinyl acetal in tile second layer is 32 mol % or greater.6. The interlayer film for laminated glass according to claim 1 ,wherein a content of ...

Sintering apparatus, packaging system for organic light emitting diode device and sintering method

The application provides a sintering apparatus, a packaging system for an organic light emitting diode device and a sintering method, belongs to the technical field of organic light emitting diode device and can solve problems of long process time and high cost existed in the existing high temperature sintering process of organic light emitting diode device. The sintering apparatus comprises two sintering chambers capable of being communicated with each other, during operation, the substrate coated with glass cement is first placed into a sealed first sintering chamber to complete a first sintering process; then the substrate is placed into the second sintering chamber to complete a second sintering process. Thus, a time interval between the first sintering process and the second sintering process can be reduced, and no more nitrogen is wasted in transition from the first sintering process to the second sintering process.

ELECTRON TUBE

In an electron tube, an atomic layer deposition method is used to form an electrical resistance film having a stacked structure of electrically insulating layers and electrically conductive layers or a mixed structure of an electrically insulating material and an electrically conductive material, so as to cover the whole of an inner wall surface and an outer wall surface of a second envelope. By use of the atomic layer deposition method, the firm and fine electrical resistance film with a desired resistance can be formed on an insulation surface, without containing a material such as a binder. When the electrical resistance film is provided with slight electrical conductivity, it can suppress occurrence of withstand voltage failure due to electrification of the insulation surface or the like and realize stability of withstand voltage characteristics. 1. An electron tube comprising:a cylindrical housing in which an insulation surface with an electrical insulation property is located on the inside; andan electrical resistance film covering the insulation surface,wherein the electrical resistance film has a stacked structure of an electrically insulating layer and an electrically conductive layer formed by an atomic layer deposition method.2. An electron tube comprising:a cylindrical housing in which an insulation surface with an electrical insulation property is located on the inside; andan electrical resistance film covering the insulation surface,wherein the electrical resistance film has a mixed structure of an electrically insulating material and an electrically conductive material formed by an atomic layer deposition method.3. The electron tube according to claim 1 , wherein the electrical resistance film is formed across a substantially entire area of the insulation surface.4. The electron tube according to claim 1 , wherein on the inside of the housing claim 1 , an electrical conduction surface with an electrical conduction property is located so as to be ...

TIM STRAIN MITIGATION IN ELECTRONIC MODULES

A lid including a lid body, and a wing portion, the wing portion being disposed on a die side of the lid body such that an edge of the wing portion is flexible independent from a portion of the lid body adjacent to the edge of the wing portion. 1. A lid comprising:a lid body; anda wing portion, the wing portion being disposed on a die side of the lid body such that an edge of the wing portion is flexible independent from a portion of the lid body adjacent to the edge of the wing portion.2. The lid according to claim 1 , wherein a gap is formed between the wing portion and a portion of the lid body above the wing portion.3. The lid according to claim 1 , wherein the wing portion has a thickness less than a thickness of a center portion of the lid body.4. The lid according to claim 1 , wherein the lid body comprises a lid insert and a lid frame in which the lid insert is disposed claim 1 , andwherein the wing portion comprises, an edge portion of the lid insert.5. The lid according to claim 4 , wherein the wing portion comprises a corner of the lid insert.6. The lid according to claim 1 , wherein the wing portion is adapted to overlap a corner of the die.7. The lid according to claim 1 , wherein the wing portion is flexible independent from a portion of the lid body above the wing portion.8. The lid according to claim 1 , wherein the lid includes a plurality of one of the wing portion claim 1 , andfurther comprising a trench extending between two wing portions.9. A device comprising:a die;a thermal interface material disposed on the die;a lid disposed on the thermal interface material opposite the die, the lid comprising a lid body; anda wing portion, the wing portion being disposed on a die side of the lid body such that an edge of the wing portion is flexible independent from a portion of the lid body adjacent to the edge of the wing portion.10. The device according to claim 9 , wherein a gap is formed between the wing portion and a portion of the lid body above the ...

FINGERPRINT MODULE AND MANUFACTURING METHOD FOR SAME

A fingerprint module of fingerprint identification chip is provided. The fingerprint module includes a substrate, a fingerprint identification chip, a molding layer, a color layer, and a protecting layer. The substrate includes a pair of surfaces and a plurality of pads. The surfaces are on the opposite sides of the substrate. The pads are exposed on one of the surfaces. The fingerprint identification chip electrically connects with the substrate according to at least a wire. The molding layer disposes on the substrate and covers the fingerprint identification chip and the wire. The color layer disposes on the molding layer. The protecting layer disposes on the color layer. 1. A fingerprint module comprising:a substrate comprising a pair of surfaces and a plurality of pads, the surfaces formed on two sides of the substrate, the pads exposed on one of the surfaces;a fingerprint identification chip electrically connected with the substrate by at least a wire;a molding layer disposed on the substrate and covering the fingerprint identification chip and the wire;a color layer disposed on the molding layer; anda protecting layer disposed on the color layer.2. The fingerprint module of claim 1 , wherein the fingerprint module further comprises a protecting frame disposed on the substrate; the protecting frame comprising an opening claim 1 , the fingerprint identification chip are disposed inside the opening.3. The fingerprint module of claim 1 , wherein the materials of the molding layer claim 1 , the color layer claim 1 , and the protecting layer are selected form the group consisting of: aluminum oxide claim 1 , titanium dioxide claim 1 , titanium carbide claim 1 , chromium oxide claim 1 , chromium carbide claim 1 , zirconium oxide claim 1 , and zirconium carbide.4. The fingerprint module of claim 3 , wherein the dielectric constants of the molding layer claim 3 , the color layer claim 3 , and the protecting layer are in the range of 15 to 50.5. The fingerprint module ...

SEMICONDUCTOR PACKAGES WITH SUB-TERMINALS AND RELATED METHODS

A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate. A mold compound encapsulates the die and a majority of the sub-terminal. In implementations a first surface of the mold compound is coupled to the second surface of the substrate and a second surface of the mold compound opposing the first surface of the mold compound is flush with a second surface of the sub-terminal opposing the first surface of the sub-terminal. In implementations the sub-terminal includes a pillar having a longest length perpendicular to a longest length of the substrate. In implementations an electrically conductive pin couples to the second surface of the sub-terminal. 1. A semiconductor device package , comprising:a substrate having a first surface and a second surface on an opposing side of the substrate from the first surface;a die coupled to the second surface of the substrate at a first surface of the die;an electrically conductive sub-terminal electrically coupled with an electrical contact of the die and physically coupled to the second surface of the substrate at a first surface of the sub-terminal, the sub-terminal having a second surface on an opposing side of the sub-terminal from the first surface of the sub-terminal, the second surface of the sub-terminal exposed at an outer surface of the semiconductor device package; anda mold compound that encapsulates the die and a majority of the sub-terminal.2. The semiconductor package of claim 1 , wherein the mold compound is coupled to the second surface of the substrate at a first surface of the mold compound claim 1 , and wherein a second surface of the mold compound opposing the first surface of the mold compound is flush with the second ...

SEMICONDUCTOR DEVICE

A semiconductor device including: an insulating substrate; a semiconductor element mounted on the insulating substrate; an internal printed circuit board disposed on the semiconductor element; and a sealing member that seals the semiconductor element, the internal printed circuit board, and at least a portion of the insulating substrate. The sealing member is made of a sealant that includes a resin and a pigment, and that initially has a chromatic, white, or gray color, and the sealing member degrades, thereby causing color of a front surface thereof to change to a degree recognizable by a user after the semiconductor device has been in use under a prescribed condition for a prescribed duration. 16-. (canceled)7. A method of estimating remaining life of a semiconductor device that includes a sealing member made of a sealant , the method comprising:heating a test sealant that has a same composition as a composition of the sealant in the semiconductor device at prescribed heating temperatures for prescribed durations;acquiring a relationship among the heating temperatures, heating durations, and resulting changes in color of the test sealant, by observing the color of the test sealant while the test sealant is being heated; andestimating the remaining life of the semiconductor device that has been operated, by evaluating color of a front surface of the sealing member in accordance with the relationship acquired in the step of acquiring said relationship.8. The method of estimating remaining life of a semiconductor device according to claim 7 , wherein the color of the test sealant is quantified using a L*a*b* color space in the step of acquiring said relationship.9. The method of estimating remaining life of a semiconductor device according to claim 7 , wherein the step of heating includes:preparing a test semiconductor device having same structure and composition as structure and composition of the semiconductor device of which the remaining life is to be estimated; ...

ELECTRONIC DEVICE, ALTIMETER, ELECTRONIC APPARATUS, AND MOVING OBJECT

An electronic device includes a package including an opening, and a cavity communicating with the opening, a pressure sensor element disposed in the cavity, and a waterproof unit is disposed in the package so as to cover the opening, in which the waterproof unit includes a through hole that is a separate body from the package, blocks passing of liquid, and permits passing of gas from an outside of the package into an inside of the cavity. 1. An electronic device comprising: an opening, and', 'an accommodation space communicating with the opening;, 'a package that includes'}an electronic component that is disposed in the accommodation space; anda waterproof unit that is disposed in the package so as to cover the opening,wherein the waterproof unit is a separate body from the package, blocks passing of liquid, and permits passing of gas from an outside of the package into an inside of the accommodation space.2. The electronic device according to claim 1 ,wherein the waterproof unit includes a through hole that blocks the passing of liquid and permits the passing of gas from the outside of the package into the inside of the accommodation space.3. The electronic device according to claim 2 ,wherein a plurality of through holes are disposed in the waterproof unit, andwherein disposition density of the through holes positioned on an edge portion of the opening is higher than that of the through holes positioned on a center portion of the opening of the waterproof unit, in a plan view of the opening.4. The electronic device according to claim 1 ,wherein a minimum width of the through hole is equal to or greater than 0.1 μm, and equal to or less than 10 μm.5. The electronic device according to claim 1 ,wherein a center of the electronic component is positioned by being deviated from a center of the opening, in a plan view of the opening.6. The electronic device according to claim 1 , a first member, and', 'a second member fixed to the first member, and, 'wherein the package ...

WAFER-BASED ELECTRONIC COMPONENT PACKAGING

A surface mount device includes at least one semiconductor device including an exposed top metal, an encapsulation layer partially encapsulating the at least one semiconductor device, and at least one end-termination cap on the surface mount device resulting in an electrical connection from a first side of the surface mount device to a second side of the surface mount device. In implementations, one process for fabricating the surface mount device includes dicing a finished device wafer in a scribe-line region, applying tape to a first side of the finished device wafer, backgrinding a second side of the finished device wafer, encapsulating the second side of the finished device wafer with an encapsulation layer, singulating the finished device wafer, and forming at least one wrap-around connection from a first side of the surface mount device to a second side of the surface mount device. 1. A surface mount device , comprising:at least one semiconductor device including an exposed top metal;an encapsulation layer partially encapsulating the at least one semiconductor device; andat least one end-termination cap on the surface mount device, the at least one end-termination cap resulting in an electrical connection from a first side of the surface mount device to a second side of the surface mount device.2. The surface mount device in claim 1 , where the at least one semiconductor device includes at least one of a capacitor claim 1 , an inductor claim 1 , a resistor claim 1 , or a diode.3. The surface mount device in claim 1 , where the top metal includes at least one contact pad.4. The surface mount device in claim 1 , where the encapsulation layer encapsulates all but one side of the semiconductor device.5. The surface mount device in claim 1 , where the encapsulation layer includes an epoxy-based material.6. The surface mount device in claim 1 , where the at least one end-termination cap includes two end-termination caps.7. The surface mount device in claim 1 , where ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a plurality of semiconductor modules, each of which includes a semiconductor circuit having a circuit board on which at least one or more semiconductor chips are mounted; and a module storage case that accommodates the plurality of semiconductor modules which are arranged in parallel. In the module storage case, a plurality of pairs of positioning guide members, which position and guide the semiconductor modules, are formed on opposite surfaces forming a module storage region for accommodating the semiconductor modules so as to protrude inward and to face each other, so that a distance between the plurality of semiconductor modules in a longitudinal direction can be selected. A pair of fitting concave portions, which are fitted to the pair of positioning guide members, are formed at both ends of each semiconductor module in the longitudinal direction. 1. A semiconductor device comprising:a semiconductor module comprising a fitting portion; anda module storage case configured to accommodate a plurality of the semiconductor modules and comprising a plurality of positioning guide members configured to position the semiconductor modules at selectable distances between the plurality of semiconductor modules,wherein the fitting portion is fitted to a positioning guide member of the plurality of positioning guide members.2. The semiconductor device according to claim 1 , wherein:the semiconductor module comprises a semiconductor circuit having a circuit board on which at least one semiconductor chip is mounted,the module storage case is configured to accommodate the plurality of semiconductor modules arranged in parallel,a plurality of pairs of the positioning guide members are disposed on opposite sides of the module storage case so as to protrude inward and face each other, to provide the selectable distances between the plurality of semiconductor modules in a longitudinal direction, andfitting concave portions, which are fitted to a pair ...

Radiation generating tube and radiation generating apparatus

The present invention relates to a radiation generating tube. The radiation generating tube includes an envelope including an insulating tubular member having at least two openings, a cathode connected to one of the openings of the insulating tubular member, and an anode connected to the other of the openings of the insulating tubular member. At least one of the cathode and the anode and the insulating tubular member are bonded at a bonded portion with an electrically conductive bonding member; and the bonded portion bonded with the electrically conductive bonding member is coated with a dielectric layer.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a base plate to which a stacked substrate is bonded, the stacked substrate being mounted on a semiconductor chip. The semiconductor device further includes a heat sink mounted to the base plate, via thermal paste and a metal ring. A center hole of the metal ring is provided to face the semiconductor chip and the thermal paste fills the center hole. Further, the metal ring is formed using a material having about a same hardness as the heat sink, or a material having a lower hardness than the hardness of the heat sink. 1. A semiconductor device , comprising:a stacked substrate having opposing first and second sides;a semiconductor chip mounted on the first side of the stacked substrate;a base plate having opposing first and second sides and being mounted on the second side of the stacked substrate;a metal ring having opposing first and second sides, the first side of the metal ring being mounted on the second side of the base plate; anda heat sink mounted to the second side of the base plate, via a thermal paste, with the metal ring therebetween.2. The semiconductor device according to claim 1 , whereinthe metal ring has an opening provided at a position corresponding to an area in which the semiconductor chip is disposed in the plan view, and the thermal paste is disposed between the heat sink and the base plate at at least an area corresponding to the opening of the metal ring.3. The semiconductor device according to claim 1 , wherein the metal ring is comprised of a material having a hardness equal to or lower than a hardness of a material of the heat sink.4. The semiconductor device according to claim 1 , wherein the metal ring is comprised of a material containing one of copper claim 1 , aluminum claim 1 , and an alloy containing at least one of copper and aluminum.5. The semiconductor device according to claim 1 , wherein the base plate is comprised of a material containing silicon carbide and at least one of magnesium and a ...

ELEMENT-ACCOMMODATING PACKAGE AND MOUNTING STRUCTURE

An element-accommodating package which can improve frequency characteristics of an element-accommodating package having a coaxial connector, and a mounting structure are provided. An element-accommodating package includes a metallic substrate, a frame, a first coaxial connector, a second coaxial connector, and a circuit board. A groove is provided between one side of the frame and a side surface of the circuit board and between a first signal line and a second signal line. 1. A package for accommodating an element , the package comprising: [ first and second signal lines; and', 'a first conductor layer between the first signal line and a second signal line with a distance;, 'an upper face comprising, 'a lower face comprising a second layer overlapping with the first and second lines in a transparent plan view; and', 'a mounting region on the upper face;, 'a substrate comprisinga frame disposed on upper face, comprising an inner wall surrounding the mounting region with a distance and an outer wall;a first connector on the inner wall, connected to the first signal line;a second connector on the inner wall, connected to the second signal line; and surrounded by the frame', 'being in contact with the inner wall; and, 'a circuit board'}a recess on a side of the circuit board, the recess facing the inner wall and disposed between the first signal line and the second signal line.2. (canceled)3. The package according to claim 1 , whereinthe groove is apart in a distance from the first conductor layer in the plan view.4. The package according to claim 1 , wherein the circuit board:has a rectangular shape comprising two corners opposed to an inner face of the frame; andcomprises a cutout at each of the two corners.5. A mounting structure claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the package according to ; and'}an element disposed on the mounting region of the package.6. The package according to claim 1 , whereinthe frame further comprises a ...

SEMICONDUCTOR PACKAGE WITH ELASTIC COUPLER AND RELATED METHODS

A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die. The pin includes a reversibly elastically deformable lower portion, which in implementations includes a spring, configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate. The pin is fixedly coupled in a top of the housing and is configured to be coupled with the substrate by lowering the housing towards the substrate. In implementations the pin includes two rigid portions coupled together only with a coil spring, the spring biasing the rigid portions away from one another when the housing is lowered towards the substrate. 1. A semiconductor package , comprising:a die coupled to a substrate;a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and;a pin fixedly coupled to the housing and electrically coupled with the die, the pin comprising a reversibly elastically deformable lower portion coupled with a lower end of the pin comprising a flat plate;wherein the reversibly elastically deformable lower portion is located in the pin between the housing and the substrate; andwherein the reversibly elastically deformable lower portion is configured to compress to prevent the lower end of the pin from lowering beyond a predetermined point relative to the flat plate and the lower end of the pin when the housing is lowered to be coupled to the substrate.2. The semiconductor package of claim 1 , wherein a base of the pin is coupled to the substrate with a spring.3. The semiconductor package of claim 1 , wherein the pin is fixedly coupled in a top of the housing and is configured to be coupled with the substrate by lowering the housing towards the ...

COMPACT MODULAR CATHODE

Example compact modular electron beam units are provided that can be used to generate electron beams using field emitter elements. A modular electron beam unit may comprise an electron beam source including a base portion, at least one field emitter element coupled to the base portion, the field emitter element including a field emitter tip, at least one gate electrode and a membrane window disposed over the at least one gate electrode. 1. A modular electron beam unit comprising: a base portion;', a first end that is proximate to the base portion;', 'a field emitter tip disposed proximate to a second end that is opposite to the first end;', 'a transistor channel formed between the first and the second end of the at least one emitter element; and, 'at least one field emitter element coupled to the base portion, comprising, 'at least one gate electrode disposed proximate to the second end of the at least one field emitter element, to apply a potential difference proximate to the field emitter tip of the at least one field emitter elements, thereby extracting electrons from the at least one field emitter tip to form an electron beam; and, 'an electron beam source comprisinga membrane window disposed over the at least one gate electrode, the membrane window being formed of a material that is selectively transmissive to electrons but impermeable to gas molecules, and the membrane window being coupled to the at least one gate electrode such that the modular electron beam unit has low permeability to oxidizing gaseous molecules.2. The modular electron beam unit of claim 1 , wherein at least a portion of the membrane window is in physical communication with the at least one gate electrode.3. The modular electron beam unit of claim 1 , further comprising an electrically insulating or poorly conductive stand-off enclosure disposed between and spacing apart at least a portion of the membrane window from the at least one gate electrode.4. The modular electron beam unit of claim ...

SYSTEM, A TANGENT PROBE CARD AND A PROBE HEAD ASSEMBLY FOR TESTING SEMICONDUCTOR WAFER

A system for semiconductor wafer testing, a tangent probe card and a probe head assembly thereof. The system has a tangent probe card and a tester. Testing ends of the probe card are flat, hence the allowable alignment budget will always be more generous for the tangent probe card. The probes are held on the probe head assembly, and once the alignment is achieved accurately during manufacture, the alignment will remain stable throughout the whole life cycle. The probe has a greater CCC due to its larger cross section. The throughput of the tangent probes is higher than that of the conventional probe card since there is no need to move the pointed pin/structure. No pointed pin/structure needs to be repaired, and the flat bottom surface of the probe head assembly is easier to clean and maintain. 1. A probe head assembly for a tangent probe card , wherein the probe head assembly comprises:a plurality of probes, a first end of each of which is a testing end and a second end of each of which is a connecting end, with the testing ends being flat, the connecting end of each of the plurality of probes being configured to electrically connect to a tester by a conductive wire such that the probe head assembly will hang from and be suspended by the conductive wires; anda probe holding portion, which holds the plurality of probes at prescribed locations and makes the testing ends of the plurality of probes be flush with a bottom surface of the probe holding portion, the plurality of probes being permanently connected to the probe holding portion,wherein the probe head assembly is carried by a holder, the holder being mounted in a fixed position such that the holder does not interact directly with a test target,wherein a buffer part is located between the probe head assembly and a top of the holder to adjust a contact force between the testing ends and the test target during testing, andwherein the probe head assembly is configured to move upward and downward when the test ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening. 1. A semiconductor package comprising:a semiconductor chip having an active surface on which contact pads are arranged;a first insulating film disposed on the active surface and exposing the contact pads;a RDL pattern electrically connected to the contact pads and extending onto the first insulating film;a second insulating film disposed on the first insulating film and the RDL pattern, and including a first opening exposing a connection region of the RDL pattern;an insulating layer disposed on the second insulating film and including a second opening exposing the connection region;a redistribution layer electrically connected to the connection region through the second opening; anda conductive crack preventing layer disposed above the redistribution layer;wherein a first region of the conductive crack preventing layer is disposed directly on the redistribution layer; andwherein a second region of the conductive crack preventing layer extends to a portion of the insulating layer so that a portion of the insulating layer is disposed between the second ...

SEMICONDUCTOR POWER MODULE AND POWER CONVERSION DEVICE

A semiconductor power module includes a base plate, an insulating substrate, a power semiconductor element, an external terminal, a main terminal, a connected body, a case, a highly-insulating voltage-resisting resin material, a sealing resin, and a cover. The main terminal is connected to the connected body. The connected body is directly joined to the metal plate. The connected body is provided with a receiving section in which the main terminal is received. The receiving section is provided with a slit portion. The slit portion extends from a lower end side of the receiving section toward an upper end side thereof. The lower end side is located on a side close to the insulating substrate. The upper end side is located opposite to the side close to the insulating substrate. 1. A semiconductor power module comprising:a base plate;an insulating substrate mounted on the base plate and including a conductive pattern;a power semiconductor element mounted on the conductive pattern;a case member mounted on the base plate so as to surround the insulating substrate;a main terminal attached to the case member and electrically connecting to an outside;a connected body to which the main terminal is connected, the connected body being connected to the conductive pattern; anda sealing material introduced into the case member to seal the insulating substrate, the main terminal and the connected body, wherein a receiving section provided in one of the main terminal and the connected body and receiving the other of the main terminal and the connected body, and', 'a slit portion formed in the receiving section so as to extend from a first end portion of the receiving section toward a second end portion of the receiving section, wherein the first end portion is located on a side close to the insulating substrate, and the second end portion is located opposite to the side close to the insulating substrate., 'the main terminal and the connected body include'}2. The semiconductor power ...

평판형 형광램프 제조장치

본 발명은 평판형 형광램프 제조장치에 관한 것으로, 본 발명의 평판형 형광램프 제조장치는 형광램프 기판을 소정 형태로 성형하는 금형을 구비한 성형부와; 상기 성형부 내부를 소정 온도로 가열하는 제 1온도조절장치와; 상기 성형부의 외측에 설치되어 성형부와 금형을 주고 받는 적어도 1개 이상의 임시예열부와; 상기 금형을 성형부와 임시예열부 간에 반송하여 주는 반송장치와; 상기 임시예열부 내에서 금형을 소정 온도로 가열 및 냉각하는 제 2온도조절장치를 포함하여 구성된 평판형 형광램프 제조장치를 제공한다. 따라서, 본 발명에 의하면, 형광램프의 기판을 성형하는 금형의 유지 관리(maintenance) 및 교체(changeover)가 용이하고 신속하게 이루어지고, 금형의 유지 관리 및 교체 작업이 수행되는 도중에도 기판의 성형 작업이 중지되지 않고 연속적으로 성형 작업이 수행될 수 있다. 평판형, 형광램프, 제조장치, 성형장치, 금형, 임시예열부

Semiconductor device

Patent JPS6055990B2

ブラウン管のファンネルとネックとの溶着部の除歪方法

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Manufacture of projection type cathode ray tube

Slug lead

Reducing video display radiation

A video display has a flat panel display, and to reduce electric field radiation, includes a conducting shield having a transparent conducting surface overlying the display. The terminal is also shielded and wired to reduce magnetic field radiation.

Chip size package

본 발명은 칩 사이즈 패키지에 관한 것으로, 종래 반도체 패키지는 아웃리드가 외부로 돌출되어 있어서 패키지를 경박단소화 시키는데 한계가 있는 문제점이 있었다. 본 발명 칩 사이즈 패키지는 외부단자가 되는 리드(14)들이 외부로 돌출되지 않게 되어 경박단소화가 가능한 효과가 있고, 칩(11)의 하면에 열방출판(13)이 설치되어 있어서 칩(11)의 동작시 주로 열방출판(13)을 통하여 충분한 열방출이 이루어지게 되어 패키지의 오동작이 발생되는 것을 방지하는 효과가 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package, and the conventional semiconductor package has a problem in that the outlead protrudes to the outside, thereby limiting the size of the package. In the chip size package of the present invention, the leads 14, which are external terminals, do not protrude to the outside, thereby making it possible to reduce the thickness of the chip 11, and the heat radiating plate 13 is provided on the bottom surface of the chip 11, In operation, sufficient heat dissipation is made mainly through the heat dissipation plate 13, thereby preventing the malfunction of the package.

Method for manufacturing tight metal-glass electrical connectors

FIELD: physics; glass. SUBSTANCE: invention relates to a method for manufacturing sealed multi-lead electric connectors with eye junctions of glass with metal and can be used in radio engineering, electronic and electrical industries, where high requirements to electric strength and tightness at high pressures are made to products. Method of making sealed metal-glass electrical connectors involves assembling glass pads, a metal body with a baffle and holes, and kovar inputs in a mandrel. Mandrel is made in the form of matrix of the same metal or alloy as body with partition. In the matrix holes are made, which are coaxial to the holes in the casing partition, the diameter of which is not less than the diameter of the corresponding opening in the partition. Graphite bushings with inlet bores are pressed into matrix holes. On ends of bushings on side of glass tablets installation outer and inner chamfers are made, ensuring protrusion of bushings by end face of matrix on (0.1÷0.2) mm. Further, in argon medium, assembly is heated to temperature (1000–1020) °C, holding at this temperature for (30–60) min and cooling to 200 °C with speed of (2–3) °C/min. EFFECT: technical result is improved quality (tightness and electric strength) and reliability of multi-terminal electric connectors. 1 cl, 2 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 738 636 C1 (51) МПК C03C 27/02 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК C03C 27/02 (2020.08) (21)(22) Заявка: 2020111981, 23.03.2020 (24) Дата начала отсчета срока действия патента: Дата регистрации: 15.12.2020 (45) Опубликовано: 15.12.2020 Бюл. № 35 2 7 3 8 6 3 6 R U (56) Список документов, цитированных в отчете о поиске: SU 1044610 A1, 30.09.1983. SU 169220 A1, 11.03.1965. SU 706349 A1, 30.12.1979. SU 1661158 A1, 07.07.1991. EP 3053887 A1, 10.08.2016. (54) СПОСОБ ИЗГОТОВЛЕНИЯ ГЕРМЕТИЧНЫХ МЕТАЛЛОСТЕКЛЯННЫХ ЭЛЕКТРОСОЕДИНИТЕЛЕЙ (57) Реферат: Изобретение относится к способу ...

Semiconductor device

음극선관용 패널

본 발명은 평면형 칼라 음극선관에 관한 것으로서, 보다 상세하게는 평면 패널의 구조를 개선하여 AK재 새도우 마스크를 사용하면서 도밍(Doming)품질을 확보할 수 있는 평면형 칼라 음극선관에 관한 것이다. 본 발명은 외면은 평탄하고 내면이 소정의 곡률을 가지는 패널과 AK재 새도우 마스크가 사용되는 칼라 음극선관에 있어서, 상기 패널의 중심부 대비 유효면 끝단부의 투과율의 비가 40~60%이고, 패널 내면의 대각곡률반경(Rd)이 1.29R~4.35R인 것을 특징으로 한다. 본 발명에 따른 음극선관은 가격이 절반이상 저렴하며 인바 재질의 새도우 마스크의 도밍품질과 대등한 품질이 확보될 수 있는 AK 재질의 새도우 마스크가 사용될 수 있는 패널이 제공될 수 있는 장점이 있다.

Color cathode ray tube

본 발명은 평면감이 양호하고, 섀도우 마스크의 낙하 강도가 향상된 평면 패널형 칼라 음극선관을 제공하기 위해서, The present invention is to provide a flat panel-type color cathode ray tube with a good flatness and improved drop strength of the shadow mask, 패널(1)의 외면의 대각 방향의 곡률을 평탄에 가깝게 하고, 패널(1)의 외면의 X축을 따른 등가 곡률 반경(Rox)을 Y축을 따른 등가 곡률 반경(Roy)보다 작게 하고, 패널(1)의 내면의 X축을 따른 등가 곡률 반경(Rix)을 Y축을 따른 등가 곡률 반경(Riy)보다 크게 했다. 또한, 패널(1)의 내면의 Y축을 따른 등가 곡률 반경과 X축을 따른 등가 곡률 반경의 비의 최적치를 0.7 < (Riy / Rix) < 1.0의 범위로 했다. The diagonal curvature of the outer surface of the panel 1 is made close to flat, the equivalent radius of curvature Rox along the X axis of the outer surface of the panel 1 is smaller than the equivalent radius of curvature Roy along the Y axis, and the panel 1 The equivalent radius of curvature Rix along the X axis of the inner surface of the X is larger than the equivalent radius of curvature Riy along the Y axis. In addition, the optimum value of the ratio of the equivalent curvature radius along the Y-axis and the equivalent curvature radius along the X-axis of the inner surface of the panel 1 was made into the range of 0.7 <(Riy / Rix) <1.0.

합착 장치 및 이를 이용한 액정표시장치의 제조 방법

본 발명은 대면적의 액정표시소자에 유리한 합착 장치 및 이를 이용한 액정표시소자의 제조 방법에 관한 것으로, 합착기 챔버 내에 각각 대향되어 구비되고, 반입된 기판을 각각 흡착하여 각 기판간 합착을 수행하는 상부 스테이지 및 하부 스테이지와, 상기 합착기 챔버 내부에 설치되어 제 2 기판을 받아주는 받침 수단과, 상기 하부 스테이지에 제 1 기판이 로딩될 때와 합착된 제 1, 제 2 기판이 하부 스테이지로부터 언로딩 될 때 기판을 리프팅하는 리프팅 수단과, 상기 합착기 챔버 내에 승강 및 회전하게 구비되고, 합착 완료된 기판을 고정하거나 혹은, 상부 스테이지에 고정되는 기판을 받쳐주는 공정 보조 수단을 구비한 합착 장치를 이용하여, 제 1 기판과 제 2 기판을 상기 각 스테이지에 로딩하는 공정과, 상기 받침수단을 구동하여 상부 스테이지에 로딩된 기판을 상기 받침 수단에 올려 놓고 상기 합착기 챔버를 진공시키는 공정과, 상기 받침 수단의 기판을 상부 스테이지가 흡착하여 상기 제 1, 제 2 기판을 합착하는 공정과, 상기 합착된 제 1, 제 2 기판을 상기 리프팅 수단을 이용하여 상기 하부 스테이지로부터 탈거시켜 언로딩하는 공정을 구비한 것이다. 액정표시장치 제조 방법, 액정표시장치 합착 방법, 액정표시장치용 합착 장치

Semiconductor device

본 발명은 복수의 배선 기판과 전기 접속부를 포함하는 다층 배선 기판에 관한 것이다. 여기서, 각각 배선 기판은 각각 표면들을 갖는 판 또는 시트 형상 절연 기판과, 상기 절연 기판의 표면들 중 하나에 형성된 배선 층을 포함하며, 상기 복수의 배선 기판은 상기 절연 기판과 상기 배선 층이 번갈아서 위치하도록 적층된다. 전기 접속부는 절연 기판 내에 구비된 비어 홀 등의 연결 수단(communication means)과, 상기 절연 기판 상의 배선 층의 일부가 상기 연결 수단을 통하여 상기 하나의 절연 기판의 반대쪽 표면을 향하여 구부러져서 형성한 굴곡 신장부와, 상기 굴곡 신장부를 상기 하나의 절연 기판에 인접한 상기 절연 기판 상의 상기 배선 층에 전기적으로 접속하기 위한 솔더 또는 도전 페이스트 등의 제 1 도체를 포함한다. The present invention relates to a multilayer wiring board comprising a plurality of wiring boards and an electrical connection portion. Here, each wiring board includes a plate or sheet-shaped insulating substrate each having surfaces, and a wiring layer formed on one of the surfaces of the insulating substrate, wherein the plurality of wiring substrates are alternately positioned with the insulating substrate and the wiring layers. To be laminated. The electrical connection portion is formed by bending means such as via holes provided in the insulating substrate and a part of the wiring layer on the insulating substrate bent toward the opposite surface of the one insulating substrate through the connecting means. And a first conductor, such as solder or conductive paste, for electrically connecting the flexural extension to the wiring layer on the insulating substrate adjacent to the one insulating substrate. 다층 배선 기판, 절연 기판, 배선 층 Multilayer Wiring Board, Insulation Board, Wiring Layer

Press-in type semiconductor rectifying device

Packaging method of power semiconductor device

(57)【要約】 【課題】 製品特性に障害となる“ウエルドスプラッシ ュのキャビテイ内部への侵入”を防止する電力用半導体 装置のパッケ−ジング方法を提供すること。 【解決手段】 ＤＯスタッド１(又はＴＯヘッダ−)の外 周部の溶接メタル部１１内側の所定位置にウエルドスプ ラッシュストッパ−(凸状の突起)３を形成したＤＯスタ ッド１(又はＴＯヘッダ−)を用い、前記溶接メタル部１ １と金属キャップ７のフランジ部(リングプロジェクシ ョン)９とを加圧し、電気抵抗溶接により金属ハ−メチ ックシ−ルを行う。このストッパ−３を設けることで、 製品特性に障害となる“ウエルドスプラッシュのキャビ テイ内部への侵入”が設計構造上完全に阻止されるた め、従来技術におけるＰＩＮＤ試験及び樹脂キャップ被 着が不要となる。

Process for production of semiconductor device

Patent JPS5912016B2

A vacuum attachment to the substrate touch pannel

PURPOSE: A vacuum attaching device for a touch panel substrate is provided to prevent the generation of bubbles by adhering a liquid crystal glass substrate attached to the top of a portable electronic device in a vacuum. CONSTITUTION: A top substrate(110) is a liquid crystal glass substrate and a bottom substrate(120) is supplied with resin(102) on an upper side. A transfer unit(130) simultaneously grips the top substrate and the bottom substrate and includes a top fixing bar(132) for the top substrate, a bottom fixing bar(134) for the bottom substrate, and a transfer robot. The transfer robot combines the top fixing bar with the bottom fixing bar to simultaneously transfer the top substrate and the bottom substrate to a vacuum chamber of each process. The vacuum chamber includes vacuum spaces for simultaneously accepting the top substrate and the bottom substrate.

Dumet wire made of composite wire and manufacture thereof

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Glass Cement

Semiconductor device

Cementing composition

Electronic parts device

Glass for soldering with covar

Color picture tube

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Cathode ray tube

Vacuum entry mechanism

Semiconductor module

PURPOSE:To provide a semiconductor module which is provided with a plurality of semiconductor chips and can mount the semiconductor chips at a high density. CONSTITUTION:This semiconductor module is constituted by constituting each vertically mounting type semiconductor chip 1 by arranging semiconductor chip lead patterns 3 for input-output on one edge section of a chip main body section 2 in a limited state and, at the same time, input-output terminals 4 provided in corresponding to the lead patterns 3 in the extent of the thickness T of the chip main body section 2 and mounting a printed board 15 constituted by arranging the semiconductor chips 1 in parallel on a base substrate 20 in an overlapping state.

Semiconductor device

Composition for soldering glasses

Manufacturing method of semi-conductor device

Cathode-ray tube

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method of soldered joint manufacturing

FIELD: manufacturing technology. SUBSTANCE: invention relates to production of metal-glass articles, mainly for electrotechnical industry, intended for operation under conditions of increased electrical and mechanical loads, such as connectors, sealed leads, etc. Method of brazed joint manufacturing includes assembly of sealed lead from at least one current lead assembly and glass and metal parts covering it with subsequent soldering in argon medium, holding at soldering temperature 20–30 minutes and further cooling. Before soldering, the current lead and the glass part are fixed in the cylindrical hole of the metal part. Soldering is carried out simultaneously with pressing of glass part by puncheons, one of which is movable, isolated from glass part by graphite washers made with high class of surface cleanliness. Pressing is carried out on the condition to ensure the specific pressure on glass piece (0.045–0.055) kg/cm 2 at temperature (860±10) °C. After holding, the assembly is cooled at rate of (5±1) °C/min to temperature (400±10) °C, and then with the furnace switched off. EFFECT: improvement of quality of the junction at provision of high tightness of the soldered connection. 1 cl, 1 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 730 959 C1 (51) МПК C03C 27/02 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК C03C 27/02 (2020.02) (21)(22) Заявка: 2019141172, 11.12.2019 (24) Дата начала отсчета срока действия патента: Дата регистрации: 26.08.2020 (45) Опубликовано: 26.08.2020 Бюл. № 24 R U 2 7 3 0 9 5 9 C 1 Адрес для переписки: 119017, Москва, ул. Б. Ордынка, 24, Госкорпорация "Росатом", Департамент правовой и корпоративной работы (56) Список документов, цитированных в отчете о поиске: SU 1661158 A1, 07.07.1991. SU 290000 A1, 22.12.1970. SU 1370104 A1, 30.01.1988. US 5227250 A1, 13.07.1993. DE 3880776 D1, 09.06.1993. (54) СПОСОБ ПОЛУЧЕНИЯ ПАЯНОГО СОЕДИНЕНИЯ (57) Реферат: Изобретение относится к технологии ...

Manufacture of semiconductor device

Low-melting glass cement

Panel glass for color cathode ray tube

Image forming device

FED의 전방면 기판(11)의 주연부에는, 측벽을 밀봉 부착하기 위한 직사각형 프레임형의 밀봉 부착면(11a)이 형성되어 있다. 밀봉 부착면(11a)에는, 하지층(31)을 거쳐서 인듐층(32)이 형성된다. 인듐층(32)의 4개의 코너부에는, 각각 통전을 위한 전극(34)이 접속되어 있다. 인듐층(32)은, 밀봉 부착면(11a)의 각 변부의 대략 중앙으로부터 인접하는 코너부를 향해 폭이 서서히 좁아지도록 형성되어 있다. 전방면 기판, 주연부, ㅂ측벽, 밀봉 부착면, 하지층, 전극, 인듐층, 코너부

Package for upper/lower electrode type light emitting diode, and its manufacturing method

【課題】量産性に優れ、強度の高い上下電極型発光ダイオード用パッケージを提供する。 【解決手段】本発明の発光ダイオード用パッケージは、上下電極型発光ダイオード１１を取り付ける金属基板１２、１４と、前記金属基板１２、１４に設けられたスリット１３と、前記スリット１３を挟んで前記金属基板１２、１４の上に形成されている一対のパッケージ電極１１１（上部電極）、１１２（下部電極）と、前記スリット１３に対応して取り付けられた反射体１６とから少なくとも構成されている。前記スリット１３は、金属基板１２、１４の上に一列または複数列に多数開口されている。前記反射体１６は、底部が狭く先端部に進む従い広くなる傾斜面を備えた筒状体であり、前記底部が前記金属基板１２、１４に取り付けられているとともに、少なくとも一方の幅が前記スリット１３の長さより短く形成されている。 【選択図】図１

Magnetic shield

Method for adhering mortar to crystallized glass plate

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Process for producing laminate of light-transmitting rigid plates and device for laminating light-transmitting rigid plates

생산효율을 높이면서 위치 정밀도의 향상을 꾀할 수 있는 투광성 경질 기판 적층체의 제조방법을 제공한다. 또 판형 제품의 생산효율을 높이면서 위치 정밀도의 향상에 기여하는 투광성 경질 기판 라미네이팅 장치를 제공한다. 본 발명에 관한 투광성 경질 기판 적층체의 제조방법 및 투광성 경질 기판 라미네이팅 장치에서는 광경화성 고착제를 개재시켜 투광성 경질 기판끼리를 정해진 위치 관계로 라미네이팅할 때 양 투광성 경질 기판 외주 부분에 존재하는 고착제만 임시 고정시키기 위해 경화시킨다. Provided is a method of manufacturing a light transmitting rigid substrate laminate capable of improving positional accuracy while increasing production efficiency. The present invention also provides a translucent rigid substrate laminating apparatus which improves production efficiency of a plate-shaped product and contributes to improvement of positional accuracy. In the method of manufacturing a light transmissive hard substrate laminate according to the present invention and the light transmissive hard substrate laminating apparatus, when laminating transparent translucent hard substrates with each other in a predetermined positional relationship via a photocurable fixative, only the fixative existing in the periphery of the translucent hard substrate is temporarily fixed .

Semiconductor device molded with resin and its manufacture

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Flat panel display

間隙をあけて対向配置されかつ成分としてシリコンを含む１対のガラス基板と、この１対のガラス基板の周辺部に配置した封止部材とを有し、封止部材は成分としてビスマスを含む材料により構成され、かつガラス基板と封止部材との接合面にガラス基板よりシリコンの含有量が少ない材料からなる中間層である保護層、絶縁体層を設けた。これにより、封止部分の強度が強く、信頼性に優れた平面型表示装置を提供できる。

Cathode ray tube

本发明涉及一种平面彩色阴极射线管，特别是一种通过改进平面板的结构和使用由铝镇静材料制成的荫罩板的具有良好的穹顶质量的平面彩色阴极射线管。对于所述的阴极射线管，用于此阴极射线管的面板的外表面非常平，而其内表面具有一定的曲率，面板的有效的表面的末端部位与面板的中心部位的透射比的比率是在0.4到0.6的范围之内，面板内表面的对角线曲率(RD)的半径是在1.29R到4.35R的范围之内(其中，1R＝1.767×有效表面的对角线长度)，荫罩板由铝镇静材料制成。体现本发明的原理的阴极射线管在价格方面具有非常大的优势，低于常规阴极射线管的价格的一半，它的面板使用由铝镇静材料制成的荫罩板，能够确保与由不变钢制成的荫罩板相同的穹顶质量。

Semiconductor device

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Process for fabricating a hermetic glass-to-metal seal

A process for forming a hermetic glass-to-metal seal between a conductive pin and an outer body, wherein a corrosion-resistant noble metal (e.g., gold) coating is applied to the conductive pin before the hermetic seal is formed. The process generally includes providing a noble metal-coated conductive pin, placing glass having a softening point less than about 650° C. into a cavity of the outer body, inserting the coated conductive pin into a bore in the glass preform, heating the assembly to a temperature in excess of the softening point of the glass but less than about 700° C., and cooling the assembly. The coefficients of thermal expansion of the components of the assembly are preferably selected such that the resulting assembly is a hermetic compression seal.

Hermetic glass-to-metal seal useful in headers for airbags

A hermetic glass-to-metal seal between a conductive pin and an outer body, wherein a corrosion-resistant noble metal (e.g., gold) coating is applied to the conductive pin before the hermetic seal is formed. The noble metal-coated conductive pin is located in glass having a softening point less than about 650° C. and disposed in a cavity of the outer body. This is accomplished by inserting the coated conductive pin into a bore in a glass preform, heating the assembly to a temperature in excess of the softening point of the glass but less than about 700° C., and cooling the assembly. The coefficients of thermal expansion of the components of the assembly are preferably selected such that the resulting assembly is a hermetic compression seal.