ПЕЧАТНАЯ ПЛАТА, В ЧАСТНОСТИ, ДЛЯ СИЛЬНОТОЧНОГО ЭЛЕКТРОННОГО МОДУЛЯ, СОДЕРЖАЩЕГО ЭЛЕКТРОПРОВОДЯЩУЮ ПОДЛОЖКУ

Изобретение относится к печатной плате, в частности, для сильноточного электронного модуля. Технический результат - достижение непосредственного электрического контакта проводящих поверхностей или соответственно токопроводящих дорожек с самой подложкой и использование подложки в качестве электрического проводника. Достигается тем, что в печатной плате, в частности, для сильноточного электронного модуля, содержащего электропроводную подложку, подложка, по меньшей мере, частично, предпочтительно, полностью, выполнена из алюминия или из алюминиевого сплава. Причем, по меньшей мере, на одной поверхности электропроводной подложки расположена, по меньшей мере, одна проводящая поверхность в виде электропроводящего слоя, нанесенного, предпочтительно, методом печати, особенно предпочтительно, методом трафаретной печати. Причем проводящая поверхность непосредственно контактирует с электропроводной подложкой. 2 н. и 13 з.п. ф-лы, 11 ил.

ВЫВОДНАЯ РАМКА КОРПУСА ИНТЕГРАЛЬНОЙ МИКРОСХЕМЫ

Полезная модель относится к области электронной техники, а именно к конструкции выводных рамок интегральных схем, герметизируемых пластмассой. Техническим результатом данной полезной модели является повышение надежности и выхода годных изделий интегральных микросхем за счет улучшения удержания выводов в пластмассовом корпусе при воздействии сил, направленных как вдоль оси выводов, так и поперек им. Указанный технический результат достигается тем, что в предлагаемой выводной рамке корпуса интегральной микросхемы, состоящей из проводящей пластины, в которой сформированы площадки под посадку полупроводниковых кристаллов, внешние выводы с участками для разварки внутренних гибких выводов от контактных площадок полупроводниковых кристаллов и технологические связи площадок под посадку и выводов с материалом пластины, причем размер площадок под посадку и участков выводов под разварку со стороны присоединения полупроводниковых кристаллов больше, чем их размер с обратной стороны, выводы за пределами ...

СОЕДИНИТЕЛЬНЫЕ ВЫВОДЫ ЭЛЕКТРОННОГО КОМПОНЕНТА (ВАРИАНТЫ), ЭЛЕКТРОННЫЙ КОМПОНЕНТ (ВАРИАНТЫ) И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ (ВАРИАНТЫ)

Использование: микроэлектроника. Сущность изобретения: соединительные выводы электронного компонента предложено выполнять из дисперсионно твердеющего сплава мартенситного или аустенитного типа определенных составов. Предложен электронный компонент с соединительными выводами из указанных сплавов и способы его изготовления. Техническим результатом изобретения является создание соединительных выводов толщиной менее 0,1 мм для электронного компонента, имеющих механическую прочность, достаточную для осуществления различных операций, обеспечение удобства обращения с электронным компонентом и его монтажа на печатной схеме. 7 с. и 10 з.п.ф-лы.

Halbleiteranordnung mit Metallplatte

Halbleiterbauelement mit wenigstens zwei in einem Gehäuse integrierten und durch einen gemeinsamen Kontaktbügel kontaktierten Chips

Halbleiterbauelement, das folgende Merkmale aufweist: - ein Gehäuse (90), - wenigstens zwei in dem Gehäuse (90) angeordnete Halbleiterchips (1-5), die jeweils eine Vorderseite (12, 22, 32, 42, 52) und eine Rückseite (11, 21, 31, 41, 51) und jeweils wenigstens eine Kontaktfläche (43, 33, 34) an der Vorder- und/oder Rückseite aufweisen, - wenigstens einen Kontaktbügel (61-63, 71-73, 81-83) der wenigstens ein Anschlussbein, das aus dem Gehäuse (90) herausragt, und der innerhalb des Gehäuses (90) einen plattenförmigen Abschnitt (631, 721, 821) mit einer ersten und einer zweiten Anschlussfläche, die sich gegenüberliegen, aufweist und der wenigstens zwei der Chips (1-5) kontaktiert, wobei dessen erste Anschlussfläche auf die Kontaktfläche (43) wenigstens eines der Chips (1-5) und dessen zweite Anschlussfläche auf die Kontaktfläche wenigstens eines anderen der Chips (1-5) aufgebracht ist, - wobei das Gehäuse (90) eine Oberseite (92) und eine Unterseite (91) aufweist, deren Flächen größer als übrige ...

Optische oder optoelektronische Anordnung mit mindestens einem auf einem Metallträger angeordneten optoelektronischen Bauelement

Optische oder optoelektronische Anordnung mit mindestens einem auf einem Metallträger angeordneten optoelektronischen Bauelement, wobei der Metallträger aufweist: - mindestens einen planen Aufnahmebereich zur Aufnahme und Befestigung des Bauelements sowie - randseitige Kontaktbeine, die über elektrische Mittel mit dem Bauelement elektrisch verbunden sind, - im planen Aufnahmebereich mindestens einen Bereich reduzierter Dicke (11), worin das Bauelement befestigt ist, wobei - der Aufnahmebereich im Bereich reduzierter Dicke mindestens eine Öffnung (13) aufweist, durch die von dem in dem Bereich reduzierter Dicke angeordneten optoelektronischen Bauelement (2) ausgesandtes oder empfangenes Licht durch den Metallträger tritt.

Einkapselungsverfahren

Verfahren zum Einkapseln eines Halbleiterbauelements, mit den folgenden Schritten: Bereitstellen eines Systemträgers (12), der eine erste Chippadzone und eine zweite Chippadzone aufweist, wobei jede Chippadzone eine erste Seite (60, 62) und eine zweite Seite (70, 72) aufweist, wobei die erste Chippadzone relativ zu der zweiten Chippadzone in der Höhe versetzt ist und wobei die erste Chippadzone und die zweite Chippadzone zusammenhängend sind; Befestigen eines ersten Chips (16) an der ersten Seite (62) der ersten Chippadzone; Befestigen eines zweiten Chips (14) an der ersten Seite (60) der zweiten Chippadzone; Drahtbonden von Drähten an den ersten und zweiten Chip (16, 14); Anordnen eines Gussrahmens gegenüber dem Systemträger (12), um eine Lücke zwischen den zweiten Seiten (72, 70) der ersten und der zweiten Chippadzonen und einer Oberfläche des Gussrahmens zu bilden; und Einkapseln mit einem den ersten Chip (16) und den zweiten Chip (14) überdeckenden Einkapselungsmaterial, das in die ...

ELEKTRONIKGEHÄUSE MIT LEITERRAHMEN MIT VERBESSERTER ADHAESION

Gestapelte Mehrchip-Module und Verfahren zur Herstellung

TAB Band und sein Herstellungsverfahren

Leiterrahmen-Kondensator

Halbleiteranordnung mit Versorgungsbusleitungen

Verfahren zur Herstellung einer harzversiegelten Halbleitervorrichtung, bei diesem Verfahren verwendeter Leiterrahmen zur Montage vieler Halbleiterelemente und harzversiegelte Halbleitervorrichtung

Leiterrahmen für integrierte Schaltungsanordnungen

VERFAHREN ZUR HERSTELLUNG EINER HALBLEITER-BAUGRUPPE MIT EINEM AUSSENANSCHLUSSTEIL

Packung für elektronische Schaltung

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

INTEGRATED CIRCUIT LEAD FRAME

Elektronisches Bauteil und Leadframe

In einer Ausführungsform weist ein elektronisches Bauteil einen Halbleiterchip mit einer ersten Oberfläche auf, wobei die erste Oberfläche eine erste Lastelektrode und eine Steuerelektrode aufweist. Das elektronische Bauteil weist ferner ein Chipinsel mit einer ersten Oberfläche, eine Vielzahl von Anschlüssen und ein knickflügelförmiges leitfähiges Element auf, das mit einem ersten Anschluss der Vielzahl von Anschlüssen gekoppelt ist. Die erste Lastelektrode ist auf der Chipinsel montiert, und das knickflügelförmige leitfähige Element ist zwischen der Steuerelektrode und dem ersten Anschluss gekoppelt.

Elektronikbauelement und Verfahren zum Herstellen eines Elektronikbauelements

Ein Halbleiterbauelement enthält einen elektrisch leitenden Träger und einen über dem Träger angeordneten Halbleiterchip. Das Halbleiterbauelement enthält auch eine zwischen dem Träger und dem Halbleiterchip bereitgestellte poröse Diffusionslotschicht.

Semiconductor component with chip fastened or bond island

The component has rows of inner terminals (150,152) coupled to numerous outer terminals (160), with the inner terminals electrically coupled to the chip (110) on the bond island (130) with anchoring members (140), from which the terminals are spaced. The chip, inner terminals, and bond island are embedded in a casting substance. At least on one side in the casting substance are located encapsulated blind terminals (154), set in front of the inner terminals. Preferably, the rows of inner terminals are formed at all sides of the bond island at a preset distance to the latter.

Metall-Basisplatte wie Wärmesenke für eine Plastikumhüllte Halbleiteranordnung mit erhöhten Teilen zum Löten von Erdschluss-Verbindungsdrähten

Metallträger für ein Mehrschicht-Leitergitter und Verfahren zum Herstellen desselben

Innere Leiterstruktur einer Halbleiteranordnung

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Gehäuse und Leitungsrahmen für ein Halbleiterbauelement hoher Stromleitfähigkeit, mit großflächigen Verbindungsschlüssen und veränderter Form

Vergossenes Leiterrahmengehäuse und Verfahren zu dessen Herstellung

Ein Halbleitervorrichtungsgehäuse beinhaltet einen Leiterrahmen und einen an dem Leiterrahmen montierten Halbleiterchip. Das Halbleitervorrichtungsgehäuse beinhaltet ferner einen Vergussverkapselungsstoff, der ausgelegt ist, den Leiterrahmen in Position zu vergießen. Ein Oberflächenbereich des Leiterrahmens verbleibt von dem Verkapselungsstoff freiliegend. Eine elektrisch isolierende Deckschicht erstreckt sich über einem Teil des Oberflächenbereichs und ist ausgelegt, den Oberflächenbereich in wenigstens zwei Zonen zu unterteilen.

HALBLEITERANORDNUNG UND VERFAHREN ZU IHRER HERSTELLUNG

Connecting wires for semiconductor device - using wires of copper and tin or similar alloy and connecting to aluminium electrodes

The method of forming a connection between conductor strips (2,3) and a semiconductor device (5) such as a transistor, uses thin conductor wires (8) between the strips and the aluminium zones (6,7) forming the base and emitter electrodes. Instead of using gold conductors, a copper-tin, or a copper-tin-lead or a copper-tin-indium alloy is used. The first alloy has a 20 to 60 percent by weight of copper. The second alloy has a 50/40/10 mixture by weight, and the third alloy also has a 50/40/10 mixture.

Anschlussrahmen für ein Halbleiterbauelement

Anschlussrahmen für ein Halbleiterbauelement mit: einem Anschlussrahmenkörper; und mehreren Metallbeschichtungen, die eine Silber- oder Silberlegierungsbeschichtung aufweisen und die auf den Anschlussrahmenkörper aufgebracht sind, wobei die Silber- oder Silberlegierungsbeschichtung eine äußerste Metallbeschichtung eines vorbestimmten Teiles des Anschlussrahmens ist, und wobei der vorbestimmte Teil von einem Gehäuse des Halbleiterbauelements zu umschließen ist.

Mehrzweck-Kupferlegierungen mittelhoher Leitfähigkeit und hoher Festigkeit und Verfahren zu ihrer Herstellung.

Anschlussrahmen für Harz-Halbleiterverpackungen

Verbindungsleiter bestehend aus einem spiralförmigen Leiterentwurf.

Halbleiteranordnung mit Leiterrahmen

STRUKTUR UND FERTIGUNGSVERFAHREN EINES DREIDIMENSIONALEN SYSTEMS EINER METALL-LEITERPLATTE, DIE VOR DEM HORIZONTALEN BESTÜCKEN GEÄTZT WIRD

Gegenstand ist eine horizontal bestückte, dreidimensionale, vor dem Bestücken geätzte System-Level-Metall-Leiterplatte, charakterisiert durch einen Metallsubstrat-Rahmen (1). Dieser Metallsubstrat-Rahmen (1) weist Basisbereiche (2) und Stifte (3) auf. Die Frontseiten der Basisbereiche (2) werden mit Chips (5) bestückt, die Frontseiten der Chips (5) sind über Metalldrähte (6) mit den Frontseiten der Stifte (3) verbunden. Auf den Front- oder den Rückseiten der Stifte (3) befinden sich Leitungspunkte (7). Die peripheren Bereiche der Basisbereiche (2), die Bereiche zwischen den Basisbereichen (2) und den Stiften (3), die Bereiche zwischen den Stiften (3), über den Basisbereichen (2) und den Stiften (3) und den Außenbereichen der Chips (5), die Metalldrähte (6) und die Leitungspunkte (7) sind mit Formmasse (8) vergossen und die Oberflächen des Rahmens aus Metall-Substrat (1), der Stifte (3) und der Leitungspunkte (7), die aus der Formmasse (8) herausragen, sind mit einer oxidationsbeständigen ...

Verfahren zum Herstellen von Leitungsverbindungen an elektronischen schaltelementen

Elektronische Schaltung in einer Package-in-Package-Konfiguration und Herstellungsverfahren für eine solche Schaltung

Elektronische Schaltung in einer Package-in-Package-Konfiguration, umfassend eine von einer Verkapselung (10) umhüllte Anordnung aus einem Halbleiterelement (20) auf einem Elementeträger (40), einem Leadframe (50) mit einer inneren Kontaktierung (55), einem innerhalb der Verkapselung verlaufenden Innenleiter (60) und einer aus der Verkapselung hinaus geführten äußeren Kontaktierung (70), wobei der Innenleiter (60) mindestens einen von der Außenseite der Package-in-Package-Konfiguration aus kontaktierbaren freiliegenden Innenleiter-Abschnitt (80) aufweist und der freiliegende Innenleiter-Abschnitt (80) in Form eines aus dem Verlauf des Innenleiters herausgebogenen und/oder abgekanteten Abschnittes (85) mit einem aus der Verkapselung (10) hervortretenden kontaktierbaren Kontaktstück (90) ausgebildet ist, wobei auf dem freiliegenden Innenleiter-Abschnitt eine abziehbare Schutzfolie vorgesehen ist.

Plastics encapsulated semiconductor with surface terminals - on side edges and opposite sides of plastics encapsulation

The areal surface terminals cover each a side edge and contact surfaces of two opposite sides of the plastics encapsulation. The surface contacts are planar relative to these sides, or may possibly protrude over these sides in a slight manner. Preferably the terminals are in the form of U-shaped stirrups of flat strips, fitting into depressions in the plastics encapsulation. Originally straight strips may be used and subsequently bent from one side to the other. A two-layer metal band is stamped to obtain the metal strips which are connected each to one electrode of the semiconductor. This is followed by encapsulation of the assembly in plastics, preferably by injection moulding. Finally the individual strips are bent round the two sides.

Solderable electric contact element - has silver@-tin@ alloy layer below gold@-tin@ solder alloy layer

A solderable electric contact element consists of an Fe-Ni alloy backing bearing a layer system of a metallic layer and, on part of the metallic layer surface, a 60-90 wt.% Au/10-40 wt.% Sn solder alloy layer, the novelty being that the metallic layer (3) consists of a 50-90 wt.% Ag/10-50 wt.% Sn alloy. ADVANTAGE - The Ag-Sn alloy layer is less expensive than prior art Au layers but has similar electrical and physico-chemical properties and prevents uncontrolled flow of the Au-Sn solder alloy on the contact element surface.

Verfahren zur Herstellung von Klebebändern für elektronische Bauelemente

Gehäuse für ein oberflächenmontierbares elektronisches Bauelement

Trägeranordnung zur Aufnahme eines Halbleiterbauelements

Mikrosensor mit Steckeranschluss

VERKAPSELTES, ANSCHLUSSLEITERLOSES PACKAGE MIT ZUMINDEST TEILWEISE FREILIEGENDER INNENSEITENWAND EINES CHIPTRÄGERS, ELEKTRONISCHE VORRICHTUNG, VERFAHREN ZUM HERSTELLEN EINES ANSCHLUSSLEITERLOSEN PACKAGES UND VERFAHREN ZUM HERSTELLEN EINER ELEKTRONISCHEN VORRICHTUNG

Anschlussleiterloses Package (100) mit:- einem zumindest teilweise elektrisch leitenden Träger (102), der einen Aufbaubereich (104) und einen Anschlussleiterbereich (106) aufweist;- einem elektronischen Chip (108), der an dem Aufbaubereich (104) angebracht ist,- einer Verkapselung (110), die zumindest teilweise den elektronischen Chip (108) verkapselt und teilweise den Träger (102) verkapselt, so dass zumindest ein Teil einer Innenseitenwand (112, 130, 132) des Anschlussleiterbereichs (106) freiliegt, die nicht einen Teil einer Außenseitenwand (115) des Packages (100) bildet, wobeider Anschlussleiterbereich (106) eine Mehrzahl von beabstandeten Anschlussleiterkörpern (118) aufweist, von denen zumindest einer eine zumindest teilweise freiliegende Innenseitenwand (112, 130, 132) hat, die nicht einen Teil der Außenseitenwand (115) des Packages (100) bildet, undeine Bodenfläche (116') der Verkapselung (110) zumindest eine Ausnehmung (198) hat, die zumindest teilweise zumindest eine der Innenseitenwände ...

Semiconductor component especially for low voltage power components has chip with contact bumps surrounded by conductive adhesive and electrodes shorted to a metal contact layer

A semiconductor component comprises housing (2) and chip (3) with a large surface contact between contact metal (5) on the chip and external contacts (6). Many small chip electrodes (7) are shorted to the contact metal and a transition layer (9) has contact bumps (11) surrounded by electrically conductive adhesive (12) on the contact metal.

Semiconductor device package forming process

The process involves using a first connecting wire frame (1) to support a carrier plate (10) by a number of support wires (11). A second connecting wire frame (2) overlaps the first, and is connected by support wires (21,25). The first and second wire frames (1, 2) are arranged in an injection mould within a cage, together with the inner connecting wire sections (22, 26) of the inner connecting wires (21, 25). Offset sections (12) lay outside the cage. A second mould is clamped to the first, and a resin case is formed around the device.

Wärmeabführende Halbleitervorrichtung

Substrat mit metallischer Beschichtung und seine Verwendung

KUPFERLEGIERUNGEN MIT VERBESSERTER LOETFAEHIGKEITS-HALTBARKEIT

BAUTEIL FÜR EIN DISPLAY UND VERFAHREN ZUR HERSTELLUNG EINES BAUTEILS

Es wird ein Bauteil (100) mit einem Träger (10) und einer Mehrzahl von Halbleiterchips (2) angegeben, bei dem der Träger eine einlagig ausgeführte und elektrisch leitfähige Trägerschicht (1) aufweist, wobei die Trägerschicht (1) strukturiert ausgebildet ist und eine Mehrzahl von Teilschichten (1A, 1B) aufweist. Die Trägerschicht weist eine Montagefläche (1M) auf, auf der die Halbleiterchips (2) angeordnet sind, wobei die Halbleiterchips (2) von der Trägerschicht (1) mechanisch getragen und mit den Teilschichten (1A, 1B) elektrisch leitend verbunden sind. Der Träger (10) weist eine gemeinsame Elektrode für Halbleiterchips (2) einer Gruppe aus mehreren Halbleiterchips (2) auf, wobei die gemeinsame Elektrode durch eine der Teilschichten (1A, 1B) oder durch mehrere miteinander im elektrischen Kontakt stehende Teilschichten (1A, 1B) der Trägerschicht (1) gebildet ist.Des Weiteren wird ein Verfahren zur Herstellung eines solchen Bauteils (100) angegeben.

Leistungshalbleiterbaugruppe und Verfahren zum Herstellen eines Leistungsmoduls und der Leistungshalbleiterbaugruppe

Die vorliegende Erfindung offenbart eine Leistungsbaugruppe, aufweisend ein Leistungsmodul, das einen kupferbasierten Leiterrahmen, mindestens einen Halbleiter, der auf einer ersten Seite des kupferbasierten Leiterrahmens bereitgestellt ist, eine Metallgrundplatte, die auf einer zweiten Seite des kupferbasierten Leiterrahmens bereitgestellt ist, und eine organische Isolierungsschicht, die zwischen dem kupferbasierten Leiterrahmen und der Metallgrundplatte bereitgestellt ist, aufweist. Mindestens ein Mittenloch ist in der Mitte des Leistungsmoduls gebildet. Ein Herstellungsverfahren für das Leistungsmodul und die Leistungshalbleiterbaugruppe sind ebenfalls offenbart.

Leiterrahmen für integrierte Schaltungen

Protective coating for electronic device contg. fluorinated acrylate] - and/or fluorinated polyurethane and opt. acrylic] resin, applied as organic soln.

Protective surface coating material for electronic devices consists of (a) 0.01-2 (wt.)% fluorinated acrylate (IA) and/or fluorinated polyurethane ((B) and 99.99-98% completely or partly fluorinated hydrocarbon cpd. (II); or (b) 0.01-2% (I), 1.5-35% acrylic resin (III) and 98.49-63% organic solvent (IV). Pref. (IA) is an N-lower alkyl-perfluoroalkylsulphonamido-acrylic acid, -acrylamide, -acrylonitrile or -alkyl (meth)acrylate; ((B) a reaction prod. of an N-lower alkyl-perfluoroalkylsulphonamidoalkanol and isocyanate; (III) a resin from acrylic acid, alkyl acrylate, methacrylate, acrylonitrile, N-vinylpyrrolidone, styrene or 2-chloro-styrene; and (IV) a mixt. of MEK and butyl acetate. USE/ADVANTAGE - The compsn. is claimed for coating circuit boards and laminated substrates. Good protection is obtd. and selective coating is unnecessary, which improves the efficiency and quality.

VERFAHREN ZUR SERIENFERTIGUNG VON HALBLEITERBAUELEMENTEN

VERFAHREN ZUM ABDICHTEN VON UMHUELLUNGEN FUER ELEKTRISCHE TEILE

Elektrische Baugruppe mit Abstandshaltern zwischen mehreren Schaltungsträgern

Elektrische Baugruppe (1), aufweisend einen Schaltungsträger (2, 23) mit mindestens einem elektrischen Stromkreis (21), der mindestens ein auf einem Oberflächenabschnitt (237) des Schaltungsträgers (2, 23) angeordnetes elektrischen Bauelement (22, 221) aufweist, und mindestens einen weiteren Schaltungsträger (3, 33) mit mindestens einem weiteren elektrischen Stromkreis (31), wobei der Schaltungsträger (2, 23) und der weitere Schaltungsträger (3, 33) derart aneinander angeordnet sind, dass ein Zwischenraum (6) zwischen dem Schaltungsträger (2) und dem weiteren Schaltungsträger (3) vorhanden ist und sich das Leistungshalbleiterbauelement (221) in dem Zwischenraum (6) befindet, der Stromkreis (21) und der weitere Stromkreis (31) über mindestens eine elektrische Verbindungsleitung (5) elektrisch leitend miteinander verbunden sind, das auf dem Oberflächenabschnitt (237) des Schaltungsträgers (2, 21) angeordnete Bauelement (22, 21) dem weiteren Schaltungsträger (3, 33) gegenüberliegend angeordnet ...

HALBLEITERBAUTEIL

Semiconductor chip arrangement for flip chip; has base plate metallized rear surface and source and gate contacts connected to contacts of connection frame and has casing with window near rear surface

The arrangement (10) has a connection frame with a number of contacts (20). A base plate with a metallized rear surface (14) and source and gate connectors is connected to the connection frame, so that the contacts are connected directly to the connectors. A casing with windows surrounds at least part of the connection frame and the base plate. The base plate is positioned with respect to the casing, so that the rear surface is near a window. An Independent claim is included for a method for manufacturing the arrangement.

SEMICONDUCTOR DEVICE

MOUNTING OF ELECTRONIC DEVICES

A SEMICONDUCTOR DEVICE AND THE ASSEMBLY LEAD FRAME THEREOF

SEMICONDUCTOR PACKAGE

LAMINATED LEAD FRAME

... 1398578 Semi-conductor devices PLESSEY MICRO SCIENCE Inc 6 Oct 1972 [8 Oct 1971] 46205/72 Heading H1K A lead frame is formed from two preformed sheets laminated together, the lower sheet having inner lead tips to which a semi-conductor device may be bonded, the upper sheet being similar to the lower but lacking the lead tips. Both sheets may be of the same thickness; or a very thin lower sheet may be used, allowing very fine inter lead tip spacing; the upper sheet may be correspondingly thicker, to provide a frame suitable for handling. A recess is formed in the top sheet by the absence of lead tips, which recess is suitable for at least partially containing the semi-conductor device, e.g. an integrated circuit. The lower sheet may be formed by photo-etching, the upper sheet by stamping. The preformed sheets may be of copper or aluminium, or an alloy of iron, nickel and cobalt. The sheets may be bonded by soldering or by plating the upper sheet with copper and silver and heating the sheets ...

CIRCUIT BLOCK

Method of preventing deformation of lead frames

Resin-sealed semiconductor device

A resin-sealed semiconductor device which has a insulation substrate 1 on which a chip-mounting portion 2 is provided with leads 3 radially disposed around the chip-mounting portion 2, an IC chip 5 mounted on the chip-mounting portion 2 and connected electrically with the leads 3, and a resin 7 which seals up an area including the IC chip and inner portions 3a of the leads and does not include an outer portion of the insulation substrate and does not include outer portions 3b of the leads. The semiconductor device also includes outer terminals 8 electrically connected with the outer portions 3b of the leads, outside of the resin. ...

Tape-fixed leadframe

The leadframe is comprised of electrically-conductive lead fingers 16a and an electrically-insulating tape 1 for fixing the, lead fingers. The tape includes an electrically-insulating base film 1a and an electrically-insulating adhesive layer 2 formed on a surface of the base film. The adhesive layer of the tape is adhered to the lead fingers thereby fixing the lead fingers at their original positions. The adhesive layer has thickened portions 2a located at respective sides of each of the lead fingers, intervening portions 2b between adjacent thickened portions, and thinned portions 2c below the lead fingers. Ionized atoms of a metal such as copper contained in the lead fingers are trapped by the thickened portions 2a and as a result, ion migration of the metal towards an adjacent lead finger is prevented from occurring.

Electrically isolated power semiconductor package

Electronic device package

COPPER ALLOYS

MULTI-LAYER MOULDED PLASTIC IC PACKAGE

COPPER ALLOY LEAD MATERIAL FOR LEADS OF A SEMICONDUCTOR DEVICE

LEADED CHIP CARRIER

Semiconductor device which dissipates heat

The semiconductor device includes a package (10) accommodating a semiconductor chip (20), and a plurality of connecting leads (30). One end portion of each connecting lead (30) is attached to the semiconductor chip (20) by an adhesive member (40) and the other end portion thereof is external to the package (10) and is connected to a circuit substrate (15). The semiconductor device further includes at least one heat-dissipating lead (60), whose one end portion is attached to the semiconductor chip (20) by the adhesive member (40) and whose other end portion is external to the package (10) and is separated from the circuit substrate (15). The semiconductor device also includes a heat-dissipating body (50) inserted into the adhesive member (40): one portion thereof is connected to the heat-dissipating lead (60).

Leadframes

A lead frame for use in the manufacture of electronic components of the Quad Flat Pack - No Lead Package (QFN) type comprises an array of sites 11 for receiving respective electronic component devices, a plurality of rails 12 arranged in a grid with each site 11 being disposed in respective spaces formed within the grid. Each rail 12 within the grid carries oppositely-directed lead fingers 14 for respective adjacent sites. A further rail extends around the periphery of the array 15 and carries inwardly directed lead fingers 14 for the peripheral sites 11 as well as outwardly directed dummy lead fingers 16. The symmetrical shape and configuration of the terminals 14 and dummy terminals 16 on the peripheral rails 15 is identical to the shape and configuration of the terminals 14 on parallel rails 12 within the array and thus any wire-bonding problems associated with a difference between the resilience and thermal/electrical characteristics of the supporting structure of terminals along the ...

BONDING SEMICONDUCTOR CHIPS TO A LEAD FRAME

Copper alloy and method of manufacturing the same

A copper alloy is disclosed which comprises 0.01 to 1.0 wt. % of Cr, 0.01 to 8 wt. % of Sn, 0.001 to 5 wt. % of at least one of 0.001 to 5 wt. % of Zn, 0.001 to 0.5 wt. % of Mn and 0.001 to 0.2 wt. % of Mg and the remainder of Cu, the content of O2 therein being not more than 0.005 wt. %. A method of manufacturing therefor is described wherein, after the hot processing or the heat treatment at 800 DEG to 950 DEG C., the alloy is cooled by passage through a region of 800 DEG to 400 DEG C. within 20 minutes, then following cold processing, heating treatment is carried out for at least 1 minute at 400 DEG to 650 DEG C. The alloy with the composition aforementioned is used as an alloy material for electric or electronic instruments.

Electrode configuration in surface-mounted devices

Method of and apparatus for packaging multi-terminal modules

... 961,756. Circuit assemblies. TEXAS INSTRUMENTS Inc. Aug. 13, 1962 [Aug. 14, 1961], No. 31014/62. Heading H1R. Multi-terminal modules are packaged in bays formed by shaping and interleaving conductive and insulating sheets. Fig. 1 shows a conductive sheet 110 of Au-coated Ni-Fe-Co alloy, having a rectangular rim portion and cross bars 117, 117a . . . 117d, defining bays 111 . . . 116. Uniformly spaced conductive strips 118 . . . 122 extending the length of the sheet are cut out or trimmed to leave tabs in register with the terminals of modules 151 . . . 156, Fig. 2; alternatively, the sheets may be machined or stamped with tabs in desired patterns. End arrays of tabs 130 . . . 139 are provided, of which 130 is shown as being retained. A plurality of such conductive sheets 110, 160 . . . 163, Fig. 4, are interleaved with insulating sheets 1101 . . . 1631, e.g. of plastic film adhesively or otherwise secured to the conductive sheets and preferably shaped to form bays of slightly ...

Packaging of electronics components

A thin strip of aluminium, copper or other conductive material is punched etched or otherwise formed so as to produce a series of sets of leads, with each set held together at the extremities by an outer and an inner frame. Each set can be of a specific pattern, or of a general pattern, such that successive fabrication removes undesired portions of leads, leaving the resulting complex and specific shaped for the leads, which, after bonding, form integral connectors. (The bond may be of any suitable means dependent on the needs of the component under assembly). The semi conductor die electronic component is placed in position and bonded immediately following the removal of the inner frame of the leads. Subsequently, encapsulation in ceramic or plastic casing completes the packaging. The more substantial ends of the leads can be bent to form the connectors if required. If desired, the tape may be converted from a mono-layer system to a testable system with ease.

Assemblies of an IC module and a carrier

A carrier element for an IC module (integrated circuit) comprising leads which are connected at one end with the corresponding terminals of the module and at the other end have a contact surface. The ends of the leads running into the contact surfaces extend unsupported beyond the edge of the carrier so that they can be bent into the desired position according to the intended purpose of the carrier element. When the leads are bent around the carrier plane towards the back surface of the module and united by using a castable material in a casting the result is a compact carrier element well adapted to the dimensions of the IC module. For the incorporation of the carrier element according to the invention into an identification card the free ends of the leads can be directed through corresponding recesses in the cover film of the card. During lamination of the layers of the identification card the ends of the leads are bent onto the cover film and thus pressed into the film material.

A QFN with wettable flank

Methods of fabricating a QFN with wettable flank are described. In an embodiment, a leadframe 506 is used which comprises regions of reduced thickness dam bar which extend across an edge of a kerf width 508 and the QFN are formed using film assisted molding with a shaped mold chase 504 that comprises raised portions which correspond in shape and position to the one or more regions of reduced thickness in the leadframe. The shaped mold chase prevents mold compound from filling recesses under the regions of reduced thickness of leadframe and once diced, each QFN has an edge structure which comprises a small step 510, 534, into which solder will wet where there are exposed plated leads. The steps or lips around the peripehery of the QFN allow the solder joints to be inspected.

Method of assembling a microcircuit with face-mounted leads and the resulting microcircuit

A method of assembling a packaged microcircuit with face-mounted leads includes forming a lead frame into a holder with opposed sets of leads turned upward and angular to spaced apart carrier strips, and securing a substrate having a microcircuit thereon within the holder with one set of leads securely held in contact with terminals on a face of the substrate, so that bonded electrical connections between the leads and the terminals can be readily made with conventional soldering techniques.

SEMI-CONDUCTOR ARRANGEMENT AND METHOD OF PRODUCTION

... 1300334 Semi-conductor devices SEMIKRON GES FUR GLEICHRICHTERBAU UND ELEKTRONIK mbH 31 March 1970 [1 April 1969] 15121/70 Heading H1K A semi-conductor arrangement, particularly for use in rectifier circuits, comprises a plurality of conductive members formed from a strip of conductive material, so that each member forms at least one conductor portion and contact portion, and a semi-conductor wafer contacted by a pair of the members. The contact portion 2a of one of the members, 2, is initially formed from a recess 1c of the contact part la of the co-operating member 1 by cutting or etching, and subsequently the intermediate port 2d of member 2 is bent at right angles to the plane of the strip so as to form a clamp between contacts parts 2a and la for the semi-conductor wafer 3 as shown. The wafer 3 may be soldered between the contact portions and subsequently encapsulated. By rearrangements of the members including members with a plurality of conductor and/or contact portions, bridge rectifiers ...

METHOD OF MANUFACTURING A METALLIC LEAD FRAME FOR A SEMICONDUCTOR DEVICE

... 1406207 Making lead frames MATSUSHITA ELECTRONICS CORP 11 Feb 1974 [16 Feb 1973] 06145/74 Heading B3A [Also in Division H1] A metallic lead frame for a semiconductor is made by plating a strip 10 of precious metal, e.g. gold on a metallic plate and punching out the frame from the plate such that the tips of leads 2, 3, 4 are positioned on the strip 10. The metallic plate may be plated with nickel or cobalt before plating the precious strip 10, which may be positioned in the middle of, as shown, or at the side edge of the plate. After a frame having sets of leads, 2, 3, 4 has been punched out, transistor bodies are mounted on the leads 3 and electrodes of the transistors are connected to the leads 2, 4. The transistors are encapsulated with plastics whereupon each set of leads 2, 3, 4 is separated from the remainder of the frame.

LEADED CHIP CARRIER

TAPE AUTOMATED BONDED MICROCHIPS

MICROELECTRONIC CIRCUITS

IMPROVEMENTS IN/RELATING TO DRINKING STRAWS

Improvements in or relating to processes for providing electrical components with connecting leads

... 1,148,352. Semi-conductor devices; capacitors. SIEMENS A.G. 13 Sept., 1967 [14 Sept., 1966], No. 41756/67. Headings H1K and H1M. Each of a plurality of electrical components 8-particularly semi-conductor components, though capacitors and resistors are also mentioned-is sandwiched between a portion 6 of a suitably cut-out metal sheet and a second portion 8 which is bent over from an initial position shown in section A of Fig. 1 to a final position shown in section B of Fig. 1. The components are thus held on the sheet and may be transported on it through processing stages, such as etching. Ultimately the sheet, which may be solder-coated for the purpose, is bonded to the components by soldering; alternatively, a thermo-compression bonding technique may be employed. Then each device is individually encapsulated by a moulding process and finally the portions of the sheet to which the components have been bonded are cut from the sheet and serve as the component terminals. For components required ...

CIRCUIT BLOCK

PLASTICS ENCAPSULATED PLANAR TRANSISTOR

... 1,207,230. Semi-conductor devices. ITT INDUSTRIES Inc. 23 Oct., 1968 [31 Oct., 1967], No. 50373/68. Addition to 1,137,619. Heading H1K. Those caplanar leads of the plastics encapsulated semi-conductor device of the parent specification which do not act as a shielding lead or the support for the device are hook-shaped at their ends 2b, 3b to key them into the plastics encapsulating material to provide firmer anchorage. The wires 11, 12 and 13 are prevented from touching one another by being fixed in position by plastics insulating material 14 prior to encapsulation. Further, where wires 11 and 12 pass over the shielding lead 4 they are similarly fixed and insulated by plastics material 15 prior to encapsulation. The leads are gold plated.

SEMICONDUCTOR WAFERS AND PLLETS

... 1314267 Semi-conductor devices GENERAL ELECTRIC CO 4 May 1970 [5 May 1969] 21373/70 Heading H1K Plural semi-conductive assemblies formed in a single crystal wafer of, e.g. silicon (Fig. 3) comprise element 51 with spaced parallel major surfaces 52, 54 separated by N-type central zone 56; a first P-type zone 58 being interposed between zone 56 and major surface 52 to form junction, having central parallel portion 60a and peripheral portion 60b angularly extending toward the second major surface 54. A second P-type zone 62 separates the central zone from the second major surface and a third N+ zone is interposed between the second major surface and a portion of the second zone to form junctions 66, 68. Grooves 70 inwardly spaced from the element edge extend inwardly from the second major surface to intersect the edges of junctions 60b, 66. A dielectric glass passivant 72 is inserted in the grooves to cover the exposed junction edges. An ohmic contact layer 74 is imposed on the first ...

Integrated circuit packaging

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

High-voltage packaged device

Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described.

Semiconductor device

A semiconductor device includes a first semiconductor chip 1 , a second semiconductor chip 4 , a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4 . A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

Integrated Power Converter Package With Die Stacking

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

Integrated circuit package system with encapsulation lock

An integrated circuit package system includes an external interconnect having a lead tip and a lead body, including a recess in the lead body including a first recess segment, having an orientation substantially parallel to the lengthwise dimension of the lead body, and a second recess segment intersecting and perpendicular to the first recess segment along a lead body top surface of the lead body, the first recess segment at a bottom portion of the second recess segment; an internal interconnect between an integrated circuit die and the external interconnect; and an encapsulation to cover the external interconnect with the recess filled.

Method for manufacturing semiconductor device

A method of manufacturing a semiconductor device comprises: preparing a lead frame including a package external region and a package internal region, a burred surface being provided at a top end of a side of the lead frame, and a fracture surface being provided in the vicinity of the top end of the side; chamfering the top end of the side in the package external region; mounting a semiconductor element on the lead frame and sealing the semiconductor element with mold resin in the package internal region; and removing resin burr provided on the side of the lead frame in the package external region after the chamfering and the sealing.

Power module

A reliable power module is realized, in which a good performance of radiating heat of the power semiconductor element is secured and it is hard for the heat of a power semiconductor element to be conducted to a driving element. A power module includes a power semiconductor element mounted on a lead frame, and a driving element mounted on the lead frame, and a heat radiating plate radiating heat which is generated by the power semiconductor element, and a resin holding the power semiconductor element, the driving element, and the heat radiating plate, wherein the heat radiating plate has a portion disposed at a side opposite to a surface of the lead frame where the power semiconductor element is mounted, a portion disposed between the power semiconductor element and the driving element, and a portion disposed below the power semiconductor element, as the portions being in a body.

Integrated circuit packaging system with leveling standoff and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit.

Semiconductor memory card

In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.

Wafer Level Chip Scale Package Method Using Clip Array

A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.

Electronic device and manufacturing thereof

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

Semiconductor device and driving apparatus including semiconductor device

A semiconductor device includes a semiconductor module and a pressing member configured to press the semiconductor module to a heat radiation member. The semiconductor module includes switching elements, conductors, and a molded member. Each of the switching elements is mounted on a corresponding one of the conductors. The molded member covers the switching elements and the conductors. More than three of the switching elements are disposed around the pressing member. The switching elements are disposed in a region in which a pressure generated between the semiconductor module and the heat radiation member by pressing with the pressing member is greater than or equal to a predetermined pressure with which heat generated from the switching elements is releasable from the semiconductor module to the heat radiation member.

Dc/dc convertor power module package incorporating a stacked controller and construction methodology

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Package structure of transient voltage suppressor

A package structure of transient voltage suppressor is disclosed. The package structure comprises a package housing with a bottom thereof having a first contact pin, a second contact pin, and a third contact pin, wherein the third contact pin is positioned between the first contact pin and the second contact pin. A first diode is positioned in the package housing, and an anode and a cathode of the first diode are respectively connected with the third contact pin and the first contact pin. A second diode is installed in the package housing, and an anode and a cathode of the second diode are respectively connected with the third contact pin and the second contact pin.

Power Semiconductor Package

The present invention provides a power semiconductor package. The power semiconductor package comprises a dual lead frame assembly comprising a bottom lead frame having a first heat sink pad at its bottom surface and a top lead frame having a second heat sink pad at its bottom surface. The top lead frame is coupled to the bottom lead frame by an isolation layer, wherein the isolation layer is a thermal conductive, but electrical isolative, material. The power semiconductor package further comprises a power semiconductor device coupled to the top lead frame of the dual lead frame assembly and an encapsulation member encapsulating the dual lead frame assembly and the power semiconductor device, while exposing the first heat sink pad at the bottom surface of the bottom lead frame.

Semiconductor device

According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface.

Bonded wire semiconductor device

A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

Protective sleeve for electrical components

A sleeve structure includes an electrically insulating protective sleeve having clips that retain and capture component pins and regulate a mounting distance of the electrical component from a wiring structure. A method of component wiring assembly is also included.

Integrated circuit packaging system with planarity control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.

Semiconductor package and method for manufacturing the same and semiconductor package module having the same

Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.

SEMICONDUCTOR DEVICE

A semiconductor device includes: a lead frame; a semiconductor element held by the lead frame; a frame body which is formed on the lead frame to surround the semiconductor element, cover a side surface of the lead frame, and expose a bottom surface of the lead frame; and a protective resin filling a region surrounded by the frame body. The lead frame includes an uneven part formed in a section which is part of an upper surface of the lead frame, and is covered with the frame body. 1. A semiconductor device comprising:a lead frame;a semiconductor element held by the lead frame;a frame body formed on the lead frame to surround the semiconductor element, cover a side surface of the lead frame, and expose a bottom surface of the lead frame; anda protective resin filling a region surrounded by the frame body, whereinthe lead frame includes an uneven part formed in a section which is part of an upper surface of the lead frame and is covered with the frame body.2. The semiconductor device of claim 1 , whereinthe uneven part is formed at an inner side of an outer circumference of the upper surface of the lead frame.3. The semiconductor device of claim 2 , wherein a plurality of first ridges linearly extending in a first direction, and', 'a plurality of second ridges linearly extending in a second direction which crosses the first direction., 'the uneven part includes'}4. The semiconductor device of claim 3 , whereinthe lead frame includes an external terminal protruding outside the frame body, andthe plurality of first ridges and the plurality of second ridges have a greater height, a larger width, or a narrower interval in a region of the lead frame under a position at which the frame body is in contact with the external terminal than in the other region of the lead frame.5. The semiconductor device of claim 3 , whereinthe lead frame includes a barrier portion which extends along an outer edge portion of the lead frame, and is raised from an upper surface of the lead frame ...

Method of forming a semiconductor device and leadframe therefor

In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.

SEMICONDUCTOR DEVICE

In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur. 1. A semiconductor device comprising:a die pad having an upper surface and a lower surface opposite to the upper surface;a plurality of leads arranged around the die pad;a first semiconductor chip having a first main surface, a first semiconductor element formed on the first main surface, a plurality of first electrode pads formed on the first main surface and electrically connected to the first semiconductor element, a first protective film formed on the first main surface such that the plurality of first electrode pads are exposed, and a first rear surface opposite to the first main surface, the first semiconductor chip being mounted on the die pad such that the first rear surface is opposed to the upper surface of the die pad;a second semiconductor chip having a second main surface, a second semiconductor element formed on the second main surface, a plurality of second electrode pads formed on the second main surface and electrically connected to the second semiconductor element, a second protective film formed on the second main surface such that the plurality of second electrode pads are exposed, and a second rear surface opposite to the second main surface, the second semiconductor chip being mounted on the first semiconductor chip such that the second rear surface is opposed to the first main surface of the first ...

INSERTS FOR DIRECTING MOLDING COMPOUND FLOW AND SEMICONDUCTOR DIE ASSEMBLIES

Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice. 1. A lead frame strip for use in encapsulating a plurality of electronic devices disposed in at least one mold cavity with a flowable molding compound , the lead frame strip comprising:a plurality of lead frames, wherein each lead frame of the plurality comprises:a plurality of lead fingers located in proximity to an intended location of at least one electronic device when secured to the lead frame;at least one member having an enlarged portion proximate the intended location of the at least one electronic device, the enlarged portion positioned and configured with respect to an intended direction of flow of a molding compound past the lead frame during encapsulation thereof to impede flow of the molding compound past at least one surface of the at least one electronic device.2. The lead frame strip of claim 1 , wherein the at least one member comprises At least one paddle for receiving the at least one electronic device thereon.3. The lead frame strip of claim 1 , wherein the at least one member is a tie bar securing each lead frame to a surrounding support structure of the lead frame strip.4. The lead frame strip of claim 1 , wherein the at least one electronic device comprises at least one semiconductor device.5. The lead frame strip of ...

Apparatus for integrated circuit packaging

Apparatuses are disclosed, such as those involving integrated circuit packaging. In one embodiment, a chip package includes: an encapsulation having a top surface and a bottom surface facing away from the top surface. The package further includes a leadframe including a plurality of leads. Each of the leads includes an exposed portion exposed through one of edges of the bottom surface of the encapsulation. The exposed portion has a length. At least one of exposed portions positioned along one of the edges of the bottom surface of the encapsulation has a length different from other exposed portions along the edge. The package can also include a dummy pad exposed through a corner of the bottom surface. The configuration can enhance solder joint reliability of the package when the package is attached to a printed circuit board.

CONNECTOR AND RESIN-SEALED SEMICONDUCTOR DEVICE

A connector for electrically connecting a chip electrode of a semiconductor element to a lead constituting an external leading terminal of the chip electrode, includes a first connecting part having an interface joined to the chip electrode; a second connecting part having an interface joined to a base end part of the lead; and a plate-shape coupling part for connecting the first connecting part and the second connecting part to each other, and having a step formed on the interface of the first connecting part in a direction away from the chip electrode by a half blanking process. 1. A connector for electrically connecting a chip electrode of a semiconductor element to a lead constituting an external leading terminal of the chip electrode , comprising:a first connecting part having an interface joined to the chip electrode;a second connecting part having an interface joined to a base end part of the lead; anda plate-shape coupling part connecting the first connecting part and the second connecting part to each other, and having a step formed on the first connecting part in a direction away from the chip electrode by a half blanking process.2. A connector according to claim 1 , wherein the coupling part has a plurality of steps formed by the half blanking process.3. A connector according to claim 1 , wherein the coupling part comprises a step formed on the second connecting part in a direction away from the base end part of the lead by the half blanking process.4. A connector according to claim 1 , wherein the step formed by the half blanking process has a thickness equal to or less than half a plate thickness of the coupling part.5. A resin-sealed semiconductor device claim 1 , comprising:a semiconductor element;a lead frame including a chip mounting part having the semiconductor element mounted thereon and a plurality of external leading terminals; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the connector according to for electrically connecting the chip ...

Method of forming an electronic package and structure

In one embodiment, an electronic package structure includes multiple rows of I/O pads and is formed without a flag portion. An electronic device may be attached to a pair of adjacent inner rows of I/O pads. The pair of adjacent inner rows of I/O pads is configured to support, at least in part, the electronic device, and to receive connective structures, such as wire bonds. Connective structures may electrically connect the electronic device to the multiple rows of I/O pads, and an encapsulating layer covers portions of the I/O pads, the electronic device and the connective structures.

DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

SEMICONDUCTOR PACKAGE

A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads. 1. A semiconductor device , comprising:a semiconductor chip having a first side and a second side opposite the first side;a plurality of electrode pads disposed on the semiconductor chip along the first side;a base member on which the semiconductor chip is mounted; and a first index lead, a second index lead and a plurality of inner leads disposed on the base member, the inner leads being arranged between the first index lead and the second index lead, and the first index lead, the second index lead and the inner leads being electrically connected with the electrode pads of the semiconductor chip across the first side of the semiconductor chip,wherein a first distance between ends of the first and second index leads and the first side is longer than a second distance between each of ends of the inner leads and the first side, andwherein all ends of the inner leads are coincident with a line which is in parallel to the first side.2. The semiconductor device according to the claim 1 , wherein the first and second index leads are longer than the inner leads.3. The semiconductor device according to the claim 1 , wherein the first index lead claim 1 , the second index lead and the inner leads are electrically connected with the electrode pads of the semiconductor chip via aurous bumps.4. The semiconductor device according to the claim 1 , wherein the first index lead claim 1 , the second index lead and the inner leads are made from copper.5. The semiconductor device according to the claim 4 , wherein the first index lead claim 4 , the second index lead and the inner leads are covered with tin.6. The semiconductor device according to the claim 1 , wherein a ...

PRINTED WIRING BOARD

A printed wiring board includes a substrate, a first buildup formed on a first surface of the substrate and including the outermost conductive layer, and a second buildup layer formed on a second surface of the substrate and including the outermost conductive layer. The outermost layer of the first buildup has pads positioned to connect a semiconductor component, the first buildup has a component mounting region directly under the component such that the outermost layer of the first buildup has a portion in the region, the outermost layer of the second buildup has a portion directly under the region, and the portions satisfy the ratio in the range of from 1.1 to 1.35, where the ratio is obtained by dividing a planar area of the portion of the second buildup by a planar area of the portion of the first buildup. 1. A printed wiring board , comprising:a substrate having a first surface and a second surface on an opposite side of the first surface;a first buildup layer formed on the first surface of the substrate and comprising a resin insulation layer and a plurality of conductive layers including an outermost conductive layer; anda second buildup layer formed on the second surface of the substrate and comprising a resin insulation layer and a plurality of conductive layers including an outermost conductive layer,wherein the outermost conductive layer of the first buildup layer has a plurality of pads positioned to connect a semiconductor element, the first buildup layer has a component mounting region directly under the semiconductor element such that the outermost conductive layer of the first buildup layer has a conductive portion in the component mounting region, the outermost conductive layer of the second buildup layer has a conductive portion directly under the component mounting region, and the conductive portion in the outermost conductive layer of the first buildup layer and the conductive portion in the outermost conductive layer of the second buildup layer ...

Stacked Half-Bridge Package with a Common Leadframe

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. 120-. (canceled)21. A stacked half-bridge package comprising:a control transistor having a control drain, a control source, and a control gate;a sync transistor having a sync drain, a sync source, and a sync gate;said control and sync transistors being stacked on opposite sides of a common leadframe, said common leadframe serving as an output terminal by coupling said control source with said sync drain.22. The stacked half-bridge package of claim 21 , wherein said common leadframe comprises a web portion and a leg portion.23. The stacked half-bridge package of claim 21 , wherein respective bottom surfaces of said sync transistor and a leg portion of said common leadframe are substantially flush with one another.24. The stacked half-bridge package of claim 21 , wherein a conductive clip provides connection between said control drain and a control drain leadframe.25. The stacked half-bridge package of claim 21 , comprising a conductive clip including a web portion that is coupled to said control drain and including a leg portion that is coupled to a control drain leadframe.26. The stacked half-bridge package of claim 21 , wherein a conductive clip is coupled to said control drain at a topside of said stacked half- ...

Packaged Semiconductor Device Having Multilevel Leadframes Configured as Modules

A semiconductor system () has a first planar leadframe () with first leads () and pads () having attached electronic components (), the first leadframe including a set of elongated leads () bent at an angle away from the plane of the first leadframe; a second planar leadframe () with second leads () and pads () having attached electronic components (); the bent leads of the first leadframe conductively connected to the second leadframe, forming a conductively linked 3-dimensional network between components and leads in two planes; and packaging material () encapsulating the 3-dimensional network. 1. A semiconductor device comprising:a first planar leadframe with first leads and pads having attached electronic components, the first leadframe including a first set of elongated leads bent in a first direction away from the plane of the first leadframe;a second planar leadframe with second leads and pads having attached electronic components;the bent leads of the first leadframe conductively connected to the second leadframe, forming a conductively linked 3-dimensional network between components and leads in two planes; andpackaging material encapsulating the 3-dimensional network.2. The device of wherein at least portions of the first and second leads are un-encapsulated by the packaging material claim 1 , the un-encapsulated lead portions operable as electrical device terminals.3. The device of wherein the terminals are located in more than one plane of the device encapsulation.4. The device of further including a second set of elongated leads of the first leadframe claim 1 , the second set leads bent in a second direction away from the plane of the first leadframe claim 1 , the second direction opposite to the first direction.5. The device of further including a third planar leadframe with pads having attached electronic components claim 2 , the third leadframe conductively connected to the second leadframe by bent elongated leads of a third set.6. The device of ...

Integrated Dual Power Converter Package Having Internal Driver IC

An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. 1. An integrated dual power converter package comprising:a leadframe comprising:a first control FET paddle configured to support a drain of a first control FET;a second control FET paddle configured to support a drain of a second control FET;a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET;a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of said first and second control FETs and each of said first and second sync FETs.2. The package of claim 1 , further comprising a first switched node configured for electrical connection to a source of said first control FET and a drain of said first sync FET via a first trace claim 1 , connector claim 1 , clip claim 1 , ribbon claim 1 , or wire.3. The package of claim 2 , further comprising a second switched node configured for electrical connection to a source of said second control FET and a drain of said second sync FET via a second trace claim 2 , connector claim 2 , clip claim 2 , ribbon claim 2 , or wire.4. The package of claim 1 , wherein said first control FET paddle and said second control FET paddle are disposed substantially ...

Dual Power Converter Package Using External Driver IC

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively.

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF

There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead. 1. A semiconductor device , comprising:(a) a semiconductor chip including a plurality of pads formed over the surface thereof;(b) a first member having a top surface including the semiconductor chip mounted thereover, and a bottom surface on the opposite side of the top surface;(c) a suspension lead fixed with the first member;(d) a plurality of leads disposed around the first member;(e) a plurality of wires each for electrically coupling each of the pads formed over the semiconductor chip with each of the leads; and(f) a sealing body for sealing the semiconductor chip, a part of the first member, a part of the suspension lead, a part of each of the leads, and, the wires,wherein in the first member, a first junction portion formed of a concave part is formed,wherein the suspension lead includes a second junction portion, andwherein fixing between the first member and the suspension lead is performed by fitting the second junction portion into the first junction portion.2. The semiconductor device according to claim 1 ,wherein fixing between the first member and the suspension lead is performed by inserting and compression-bonding the second junction portion into the first junction portion.3. The semiconductor device according to claim 2 ,wherein the depth of the concave part is larger than the thickness of the second junction portion.4. The ...

Support Device for a Semiconductor Chip and Optoelectronic Component with a Carrier Device and Electronic Component with a Carrier Device

A carrier device for a semiconductor chip includes a bondable and/or solderable metallic carrier having a mounting region for the semiconductor chip and a soldering region. The carrier is at least partly covered with a covering material. A solder barrier is arranged between the soldering region and the mounting region at an interface between the carrier and the covering material. An electronic component and an optoelectronic component are furthermore specified. 115-. (canceled)16. A carrier device for a semiconductor chip comprising:a bondable and/or solderable metallic carrier having a mounting region for the semiconductor chip and a soldering region;a covering material, wherein the carrier is at least partly covered with the covering material; anda solder barrier arranged between the soldering region and the mounting region at an interface between the carrier and the covering material.17. The carrier device according to claim 16 , wherein the solder barrier extends on a surface having the mounting region transversely with respect to an extension direction from the soldering region to the mounting region over the entire surface.18. The carrier device according to claim 16 , wherein the covering material encloses the carrier apart from the soldering region.19. The carrier device according to claim 16 , wherein the covering material encloses the carrier apart from the soldering region and the mounting region.20. The carrier device according to claim 16 , wherein the carrier device comprises a further bondable and/or solderable metallic carrier that is at least partly covered by the covering material claim 16 , wherein a further solder barrier is arranged at a further interface between the further carrier and the covering material.21. The carrier device according to claim 16 , wherein the carrier is a leadframe or a part of a leadframe.22. The carrier device according to claim 16 , wherein the carrier comprises copper or a copper alloy.23. The carrier device according ...

Semiconductor device

A semiconductor device according to an embodiment includes: first and second semiconductor chips, each including a first electrode and a second electrode opposite to each other in a predetermined direction; a chip-mount substrate on which the first and second semiconductor chips are mounted; and a first wiring terminal to which the second electrodes of the first and second semiconductor chips are connected. The second semiconductor chip lies over the first semiconductor chip in the predetermined direction such that the second electrode of the first semiconductor chip and the second electrode of the second semiconductor chip face each other across the first wiring terminal, and the chip-mount substrate is bent such that the first electrode of the first semiconductor chip is connected to the first electrode of the second semiconductor chip.

METHOD FOR MANUFACTURING ELECTRONIC DEVICES

A support structure includes a support cell with a support substrate, junction sacrificial portions surrounding the support substrate, and pin blocks extending from the junction sacrificial portion toward the support substrate. A semiconductor chip is mounted to the support substrate and electrically wire bonded to the pin blocks. An encapsulating body covers the chip, with the pin blocks extending from the body. A transversal groove is formed in each pin block. Surfaces of the pin block and groove are electroplated with solder material. Each pin block is sectioned at the groove to define a pin having a first end corresponding to a portion of the groove surface of the groove and a second end corresponding to the sectioned portion of the pin block that is not electroplated with solder material. Sectioning causes the separation of the chip-insulating body assembly from the junction sacrificial portions. 1. A method , comprising:forming a groove extending transversal to a leadframe pin block, said leadframe pin block extending away from a side of an encapsulated semiconductor device, said groove including a side wall;covering surfaces of the pin block including said side wall with a solder material layer;sectioning the pin block at the groove to define a pin for the encapsulated semiconductor device having an outer end formed in part by said solder material layer covered side wall and in part by a sectioned portion of the pin block not covered by said solder material layer.2. The method of claim 1 , further comprising:providing a leadframe support structure including a support cell having a support substrate, junction sacrificial portions surrounding the substrate support, and pin blocks which extend from the junction sacrificial portions towards the support substrate, each pin block having a first end connected to a junction sacrificial portion and a second end opposite to the first end.3. The method of claim 2 , further comprising: connecting a semiconductor material ...

SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE

A semiconductor device includes a lead frame, an oscillator, an integrated circuit and first bonding wires. The oscillator includes plural terminals separated from each other by a predetermined distance, and that is mounted to an oscillator mounting region formed on a first face of the lead frame. The oscillator mounting region has a narrower width than the distance between the plural terminals. The integrated circuit is mounted to a second face of the lead frame, which is on an opposite side to the first face. The first bonding wires connect the plural terminals of the oscillator to terminals of the integrated circuit. 1. A semiconductor device comprising:a lead frame;an oscillator that comprises a plurality of terminals separated from each other by a predetermined distance, and that is mounted to an oscillator mounting region formed on a first face of the lead frame, the oscillator mounting region having a narrower width than the distance between the plurality of terminals;an integrated circuit that is mounted to a second face of the lead frame, which is on an opposite side to the first face; andfirst bonding wires that connect the plurality of terminals of the oscillator to terminals of the integrated circuit.2. The semiconductor device of claim 1 , wherein:the lead frame further comprises an opening that faces the plurality of terminals of the oscillator; andthe plurality of terminals of the oscillator and the terminals of the integrated circuit are connected by the bonding wires through the opening.3. The semiconductor device of claim 1 , wherein:an opening area of the opening is larger than a terminal of the oscillator, and the terminal of the oscillator is larger than the terminal of the integrated circuit.4. The semiconductor device of claim 1 , wherein:the integrated circuit is mounted to a central portion of the lead frame, and the oscillator and the integrated circuit overlap each other in plan view projection such that the plurality of terminals of the ...

LEAD FRAME FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE USING THE LEAD FRAME

A lead frame for a semiconductor device and a semiconductor device package using the lead frame. The lead frame includes a package body having an internal space configured to mount a semiconductor device, and a lead unit disposed so as to apply voltages to the semiconductor device. The lead unit includes internal leads embedded in the package body and having an area in which the semiconductor device is to be mounted, and external leads each being connected to the internal leads, respectively . Each external lead protrudes from the package body and each has a contact portion that contacts a printed circuit board (PCB). The lead frame also includes and a support structure disposed on external sides of the package body and supporting the external leads. 1. A lead frame comprising:a package body having an internal space configured to mount a semiconductor device;a lead unit disposed so as to apply voltages to the semiconductor device and comprising internal leads embedded in the package body and having an area in which the semiconductor device is to be mounted, and external leads each being connected to the internal leads, respectively, each protruding from the package body and each having a contact portion that contacts a printed circuit board (PCB); anda support structure disposed on external sides of the package body and supporting the external leads.2. The lead frame of claim 1 , wherein the lead unit comprises a first lead unit and a second lead unit claim 1 , andthe first lead unit comprises a first internal lead and a first external lead,the second lead unit comprises a second internal lead and a second external lead, andthe first external lead and the second external lead are bent along the external sides of the package body.3. The lead frame of claim 2 , wherein the external sides of the package body comprise:a left side;a right side that faces the left side;a front side that connects the left side and the right side;a rear side that faces the front side; anda ...

MULTI-CHIP FLIP CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A multi-chip flip chip package includes multiple dies. Each die comprises several pads for coupling with pads of the other die and for coupling with pins of the multi-chip flip chip package through conducting elements. A dielectric element is positioned between the dies and the conducting elements, and positioned between the dies for providing the electrical insulation. The dies and the conducting elements between the dies are coated with a packaging element for preventing physical damage and corrosion. 1. A method for manufacturing a multi-chip flip chip package , comprising:attaching a second surface of a first die and a second surface of a second die to a second substrate;positioning a first dielectric element between the first die and the second die;coupling a plurality of conducting elements of a first conducting group with at least part of pads on a first surface of the first die, and with at least part of pads on a first surface of the second die;coupling at least part of the pads on the first surface of the first die with at least part of the pads on the first surface of the second die by utilizing a plurality of conducting elements of a second conducting group;coupling at least part of the conducting elements of the first conducting group with strips of a lead frame; andcoating the first die, the second die, and the conducting elements of the second conducting group with a packaging element.2. The method of claim 1 , further comprising:attaching the second surface of the first die and the second surface of the second die to the second substrate after the first surface of the first die and the first surface of the second die were attached to a first substrate; andremoving the first substrate after the first die and the second die were attached to the second substrate.3. The method of claim 1 , further comprising:coating the first die, the second die, and the conducting elements of the second conducting group with the packaging element after the second ...

INTEGRATED POWER CONVERTER PACKAGE WITH DIE STACKING

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry. 1. A semiconductor device comprising:a first semiconductor die comprising a first switching device;a second semiconductor die comprising a second switching device, the second semiconductor die having a top surface that is electrically connected to electrical ground;a lead frame structure comprising at least a first section supporting the first semiconductor die and a second section supporting the second semiconductor die, the first semiconductor die having a bottom surface that is on the first section of the lead frame structure, the second semiconductor die having a bottom surface that is on the second section of the lead frame structure; anda third semiconductor die that is vertically stacked on the second semiconductor die, the third semiconductor die comprising a control circuit and having a bottom surface that is attached to the top surface of the second semiconductor die.2. The semiconductor device of wherein the first and second sections of the lead frame are electrically isolated from each other.3. The semiconductor device of wherein the third semiconductor die is electrically connected to the first semiconductor die by a first bonding wire and to the second semiconductor die by a second bonding wire.4. The semiconductor device of wherein the first section of the lead frame structure comprises a first electrical lead that electrically couples the bottom surface of the first semiconductor die to a power supply voltage.5. The semiconductor device of ...

LEAD STRUCTURES WITH VERTICAL OFFSETS

A microelectronic structure includes a first row of contacts () and a second row of contacts () offset from the first row, so that the first and second rows cooperatively define pairs of contacts. These pairs of contacts include first pairs () and second pairs () arranged in alternating sequence in the row direction. The first pairs are provided with low connectors (), whereas the second pairs are provided with high connectors (). The high connectors and low connectors have sections vertically offset from one another to reduce mutual impedance between adjacent connectors. 1. A microelectronic structure comprising:(a) a first element having a first row of contacts extending in a row direction in a first plane;(b) a second element having a second row of contacts extending parallel to the first row of contacts, the second row of contacts being offset from the first row in a horizontal direction transverse to the row direction and offset upwardly in the vertical direction from the first row of contacts, the first-row and second row contacts defining single-connection pairs each including a first-row contact and a second-row contact, the single-connection pairs including mutually adjacent first and second pairs arranged in alternating sequence in the row direction; and(c) elongated connectors, one of connectors extending between the first-row contact and the second-row contact of each of the single-connection pairs, the connectors associated with the first pairs being low connectors, the connectors associated with the second pairs being high connectors, each high connector extending generally upwardly from a first-row contact at a horizontal location adjacent the first row, each low connector extending generally horizontally from a first-row contact and extending generally upwardly at a horizontal location remote from the first row so that sections of the high connectors are offset vertically from sections of the low connectors.2. A structure as claimed in wherein the ...

ELECTRONIC SYSTEM WITH A COMPOSITE SUBSTRATE

A composite substrate made of a conductive pattern structure mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the conductive pattern structure. Metal lines are used for electrical coupling between the circuitry of the IC chip and the conductive pattern structure. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the conductive pattern structure and good heat distribution from the lead frame. 1. An electronic system with a composite substrate , comprising:a lead frame having a chip mounting area and a plurality of metal leads arranged along a periphery of said chip mounting area, wherein each of plurality of metal leads is spaced from said chip mounting area by a gap;a circuit board disposed over the lead frame and having circuitry, said circuit board bridging the gap between each said metal lead and said chip mounting area; anda chip, mounted on said chip mounting area of said lead frame and electrically coupling to the circuitry of said circuit board.2. The electronic system according to claim 1 , wherein said circuit board comprises a through opening claim 1 , and said chip is disposed within the through opening of said circuit board claim 1 , wherein said chip comprises a plurality of pins claim 1 , wherein said pins are electrically coupling to the circuitry of circuit board through edges of the through opening.3. The electronic system according to claim 1 , wherein the through opening is a rectangular opening claim 1 , wherein said chip is disposed within the rectangular opening.4. The electronic system according to claim 1 , the through opening is a U-shape opening claim 1 , wherein said chip is disposed within the U-shape opening.5. The electronic system according to claim 1 , the through opening is a L-shape opening ...

PACKAGE STRUCTURE HAVING LATERAL CONNECTIONS

An embodiment of a packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor. Thus, well-established techniques for incorporating a lead frame or any other conductive system in a package may be applied in order to impart wireless lateral connectivity to packaged semiconductor devices in an electronic system. 120.-. (canceled)21. An article , comprising:a package having a side;an first integrated circuit disposed in the package; anda first communication pad disposed adjacent to the side of the package, coupled to the integrated circuit, and configured to allow the integrated circuit to communicate wirelessly outside of the package.22. The article of wherein the package includes a molded material.23. The article of wherein the integrated circuit includes a die.24. The article of wherein the integrated circuit includes a packaged integrated circuit.25. The article of wherein the communication pad is disposed fully within the package.26. The article of wherein:the side of the package includes a side surface; andthe communication pad is exposed through the side surface.27. The article of wherein:the side of the package includes a side surface; andthe communication pad includes a pad surface that is exposed through, and recessed relative to, the side surface.28. The article of wherein:the side of the package includes a side surface; andthe communication pad includes a pad surface that is exposed through, and is coplanar with, the side surface.29. The article of wherein:the side of the package includes a side surface; andthe communication pad includes a pad surface that is exposed through, and protrudes ...

Thermally Enhanced Semiconductor Package with Conductive Clip

One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.

Wiring substrate and semiconductor device

A wiring substrate includes an adhesive layer, a wiring layer, and a support substrate. The adhesive layer includes a first surface and a second surface that is opposite to the first surface. The wiring layer is formed on the first surface of the adhesive layer. The support substrate is formed on the second surface of the adhesive layer. The wiring layer is partially exposed in a through hole extending through the adhesive layer and the support substrate in a thicknesswise direction. The support substrate is adhered to the adhesive layer in a removable manner.

Sgs or gsgsg pattern for signal transmitting channel, and pcb assembly, chip package using such sgs or gsgsg pattern

A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.

LOWER SEMICONDUCTOR MOLDING DIE, SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package. 1. A semiconductor package molding die comprising:a mounting surface configured for receiving a plurality of circuit board chips, each having a through-hole; anda plurality of window patterns, each aligned with the through-hole of a circuit board chip, each window pattern extending in a first direction under a corresponding one of the circuit board chips,wherein each of the window patterns comprises a first passage pattern having a first width and a second passage pattern having a second width different from the first width.2. The molding die of claim 1 , further configured for receiving an encapsulant which fills the through-hole and the window patterns.3. The molding die of claim 1 , wherein the first passage pattern and the second passage pattern are connected alternately in the first direction.4. The molding die of claim 1 , wherein the second width is greater than the first width.5. The molding die of claim 4 , wherein the second passage pattern is deeper than the first passage pattern.6. The molding die of claim 4 , wherein the second passage pattern is longer than the first passage pattern.7. The molding die of claim 6 , wherein the first passage pattern is disposed adjacent to an end of each of the circuit board chips claim 6 , and the second passage pattern is disposed adjacent to the through-hole of each of the circuit board chips.8. The molding die of claim 4 , wherein each of the window patterns further comprises a third passage ...

SYSTEM AND METHOD TO MANUFACTURE AN IMPLANTABLE ELECTRODE

The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason. 1. An implantable electrode system , comprising:a) a wafer comprising a frame portion defining an open region;b) at least a first electrode structure comprising a first conductive lead and at least one of a first stimulation electrode site and a first recording electrode site; andc) at least a first and a second bridges, the first bridge extending from a first bridge frame end connected to the frame portion to a first bridge electrode end connected to the first electrode structure in the open region, and the second bridge extending from a second bridge frame end connected to the frame portion spaced from the first bridge frame end to a second bridge electrode end connected to the first electrode structure in the open region,d) wherein the first electrode structure is connected to the first and second bridges in the open region, spaced from the frame portion to be thereby suspended in the open region defined by the frame portion of the base by the first and second bridges.2. The implantable electrode system of further including:a) at least a second electrode structure comprising a second conductive lead and at least one of a second stimulation electrode site and a second recording electrode site ...

RESIN MOLDED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame. 13-. (canceled)4. A resin molded semiconductor device , comprising:a semiconductor die;a lead; anda resin package in which the semiconductor die and part of the lead are embedded,wherein the lead comprises a dent portion which extends from inside the resin package to outside the resin package and is formed on a top side of the lead, the top side being the same side as the side of the lead on which the semiconductor die is disposed.5. The resin molded semiconductor device of claim 4 , wherein a surface roughness of the dent portion is smaller than a surface roughness of the lead not having the dent portion.6. The resin molded semiconductor device of claim 4 , wherein burrs of the dent portion is smaller than burrs of the lead not having the dent portion.7. The resin molded semiconductor device of claim 4 , further comprising a wire that is bonded to the lead at a position of the lead that is closer to the semiconductor die than to the dent potion.8. The resin molded semiconductor device of claim 4 , wherein the device is part of a single in-line package.9. The resin molded semiconductor device of claim 4 , wherein the device is part of a quad flat package.10. The resin molded semiconductor device of claim 4 , wherein the semiconductor ...

Top Exposed Semiconductor Chip Package

A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls. 1. A semiconductor package comprising:a lead frame having a first die pad, a first source lead and first gate lead separated but near the first die pad, wherein the first source lead having substantially a V groove disposed on its top surface with two sidewalls of the V groove terminated substantially on a same plane coplanar to the top surface of the first source lead;a first semiconductor chip having a source electrode and a gate electrode on its top surface and a drain electrode on its bottom surface disposed on the first die pad with the bottom drain electrode electrically attached to a top surface of the first die pad through a conductive adhesive;a first metal plate with a first bent extension, wherein a bottom face of the first metal plate electrically attached to the source electrode of the first semiconductor chip and the first bent extension terminated in the V groove of the first source lead, the first bent extension being in contact with at least one of the V groove sidewalls;a first bond wire electrically connecting the gate electrode of the first semiconductor chip to the first gate lead of the lead frame; anda molding plastic encapsulating the first chip, the first metal plate, the first bond wire and the lead frame with a bottom face of the lead frame exposed on the bottom of the molding encapsulation.2. The semiconductor package of wherein the V groove has symmetric sidewalls.3. The semiconductor package of wherein an end face of a portion of an end of the first metal plate opposite to the bent extension exposed through a middle portion of a side surface of the ...

Thin Leadframe QFN Package Design of RF Front-Ends for Mobile Wireless Communication

Systems and methods are disclosed herein for a low cost, compact size, and thin half-etched leadframe quad-flat no-leads (QFN) package that integrates RF passive elements in the QFN leadframe for linearized PA design and RF FEMs. The integrated RF passive elements in the QFN leadframe may include RF inductors (e.g., meanders lines or spirals) for amplifier bias or RF matching, extension bar of the ground paddle for inter-stage matching or jumper pads for connection. The integrated RF passive elements may also include transmission lines for output power matching, coupled line structures such as RF couplers, RF divider or combiner realized using transmission lines with proper impedance and length, jumper pads for adjusting the bond wire length, etc. The RF parameters of the integrated passive elements are adjustable using different length and number of wire bond for fine tuning the performance of the PAM or the RF FEM.

Selective Leadframe Planishing

A metal leadframe strip () for semiconductor devices comprising a plurality of sites () for assembling semiconductor chips, the sites alternating with zones () for connecting the leadframe to molding compound runners; the sites () having mechanically rough and optically matte surfaces (); the zones () having at least portions with mechanically flattened and optically shiny metal surfaces (); and the flattened surface portions transitioning into the rough surface portions by a step. 1. A metal leadframe strip for semiconductor devices comprising:a plurality of sites for assembling semiconductor chips, the sites alternating with zones for connecting the leadframe to molding compound runners;the sites having a mechanically rough and optically matte surface; andthe zones having at least portions with a mechanically flattened and optically shiny metal surface, the flattened surface portions transitioning into the rough surface portions by a step.2. The leadframe strip of further including the mechanically rough and optically matte surface of the sites on both sides of the leadframe claim 1 , and the mechanically flattened and optically shiny surface of the zones on both sides of the leadframe.3. The leadframe strip of wherein the rough metal surfaces have an average roughness of 90±20 nm claim 1 , enhancing the adhesion of the leadframe metal to a molding compound.4. The leadframe strip of wherein the flattened metal surfaces have an average roughness of 35±20 nm claim 3 , reducing the adhesion of the leadframe metal to a molding compound.5. The leadframe strip of wherein the flattened metal surfaces have been created by selectively planishing portions of the rough surfaces of the leadframe strip claim 4 , wherein the planishing process causes a thickness reduction of the rough-surface leadframe metal by 10±5%.6. The leadframe strip of wherein the step spacing the smooth surface portions from the rough surface portions equals the thickness reduction of the rough-surface ...

STACKED DUAL CHIP PACKAGE HAVING LEVELING PROJECTIONS

The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication. 1. A semiconductor package comprising:a first semiconductor die;a dip structure attached to the first semiconductor die; anda plurality of leveling projections located between the clip structure and the first semiconductor die, such that the clip structure is parallel with the semiconductor die, wherein an adhesive material is located between at least some of the leveling projections, attaching the clip structure to the first semiconductor die.2. The package of wherein said leveling projections have a common height.3. The package of wherein said clip structure is in electrical communication with a package lead.4. The package of wherein the leveling projections are electrically non-conductive.5. The package of wherein at least some of said adhesive material is electrically conductive and located between at least some of the leveling projections claim 4 , electrically connecting at least a portion of the clip structure to the first semiconductor die.6. The package of wherein the clip structure further comprises a first conductive segment and a second conductive segment.7. The package of wherein the tops of the first and second conductive segments are co-planar.8. The package of wherein the first conductive segment is conductively attached to the first semiconductor die claim 7 , and the second conductive segment is superimposed with but electrically isolated from the first semiconductor die.9. The package of further comprising a second semiconductor chip stacked on the clip structure on a side opposite that of the first semiconductor die.10. A semiconductor package comprising:a first semiconductor die;a clip structure, having first and second conductive segments, attached to the first semiconductor die; anda plurality of ...

SEMICONDUCTOR UNIT AND SEMICONDUCTOR DEVICE USING THE SAME

In some aspects of the invention, semiconductor unit can produce chips performing uniform parallel operation and a low-thermal-resistance. Aspects of the invention can include a plurality of small semiconductor chips of one and the same kind formed by use of an SiC substrate, which is a wide gap substrate are sandwiched between two conductive plates. In this manner, there can be provided a high-reliability semiconductor unit in which parallel operation of the semiconductor chips is uniformized so that breakdown caused by current concentration can be prevented. 1. A semiconductor unit having a plurality of semiconductor chips formed by use of a wide gap semiconductor substrate , and connected in parallel , the semiconductor comprising:a plurality of semiconductor chips configured such that one principal surface of each of the semiconductor chips of the same type is joined onto a first principal surface of a first common conductive plate while each of a plurality of conductive blocks is joined to the other principal surface of each of the semiconductor chips;a first principal surface of a second common conductive plate joined onto the conductive blocks, and an insulating resin is packed in between the first principal surface of the first common conductive plate and the first principal surface of the second common conductive plate, while a second principal surface of the first common conductive plate and a second principal surface of the second common conductive plate are exposed.2. A semiconductor unit according to claim 1 , whereineach of the semiconductor chips is an SiC-diode chip in which a cathode electrode is formed on the one principal surface while an anode electrode is formed on the other principal surface;the cathode electrodes are joined to the first principal surface of the first common conductive plate; andthe anode electrodes are joined to the first principal surface of the second common conductive plate through the conductive blocks.3. A semiconductor ...

Stacked die power converter

A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Semiconductor Package with Interposer

The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. 120-. (canceled)21. A semiconductor package comprising:a substrate having a lower substrate segment including a first plurality of lower interconnect pads;said substrate including an upper substrate segment having an upper width and including a first plurality of upper interconnect pads;an interposer for electrically connecting at least some of said first plurality of lower interconnect pads to at least some of said first plurality of upper interconnect pads;said interposer having an interposer width that is different from said upper width of said upper substrate segment.22. The semiconductor package of claim 21 , wherein a second plurality of lower interconnect pads are configured for use as contact pads for receiving a lower semiconductor die.23. The semiconductor package of claim 22 , further comprising said lower semiconductor die.24. The semiconductor package of claim 21 , wherein said upper substrate segment includes upper contact pads for receiving an upper semiconductor die.25. The semiconductor package ...

WIRELESS MODULE WITH ACTIVE DEVICES

A wireless multichip module has a leadframe structure with potions for receiving flip-chip mounted dies, including an integrated circuit and high and low side mosfets to form a half-bridge circuit encapsulated in molding compound The module is assembled without any bond wires. The module may also carry passive components including an external input capacitor or an internal input capacitor 1. A wireless multichip module comprising:a plurality of active components including an integrated circuit having a plurality of terminals and one or more semiconductor devices including a first semiconductor device having two or more terminals;a leadframe structure for supporting and interconnecting the integrated circuit and the one or more semiconductor devices, said leadframe structure having:one or more semiconductor leadframe structure portions including a first semiconductor leadframe structure portion having one or more pads, said pads mechanically and electrically attached to separate terminals of the first semiconductor device, andan integrated circuit leadframe structure portion having a plurality of leads for connecting to an integrated circuit; andone or more traces, including a first trace for connecting one of the pads of the semiconductor leadframe structure to a lead of the integrated circuit leadframe structure portion;a clip coupled to another terminal of the semiconductor device for connecting said another terminal of the semiconductor device on to a terminal of another semiconductor device;said integrated circuit having a plurality of terminals including a first terminal, said integrated circuit flip-chip mounted onto said plurality of leads for connecting the terminals of the integrated circuit to the leads including connecting said first terminal of the integrated circuit to said first trace which is also connected to a pad of the semiconductor leadframe structure portion; andan insulating molding compound encapsulating the leadframe structure, the one or ...

SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME

A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. 19-. (canceled)10. A semiconductor memory device , comprising:an element-mounting region;a semiconductor memory element mounted on the element-mounting region;a rectangular region sealing the semiconductor memory element with resin;an element-supporting portion supporting the semiconductor memory element, the element-supporting portion having an opening;a plurality of first hanging elements provided at a first long edge side of the rectangular region, and extending from the element-supporting portion to the first long edge;an outer lead portion having a plurality of outer leads arranged at first and second short edge sides of the rectangular region; andan inner lead portion having a plurality of inner leads, at least a part of the inner leads being routed in the element-mounting region, and one end of at least one of the inner leads being arranged at a second long edge side of the rectangular region,wherein at least a part of the inner leads has a first portion extended to the one end of the inner leads, a second portion extended to the outer leads arranged at the first short edge side, and a third portion routed in the element-mounting region so as to extend in a direction which intersects the first and second portions,wherein at least another part of the inner leads has a fourth portion extended to the one end of the inner ...

Semiconductor Device Having a Clip Contact

A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

SEMICONDUCTOR DEVICE

A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN. 1. A semiconductor device , comprising:a die pad having an upper surface and a lower surface opposite to the upper surface, a shape in a plan view of the upper surface comprised of quadrangle;a plurality of suspension leads supporting corner parts of the die pad, respectively;a plurality of lead groups arranged along sides of the die pad, respectively, in the plan view;a first semiconductor chip having a first main surface, a plurality of first pad groups formed along sides of the first main surface, respectively, and a first back surface opposite to the first main surface, and arranged over the upper surface of the die pad, and arranged at the central part of the die pad in the plan view such that the first back surface faces to the upper surface of the die pad, and such that the sides of the first main surface are arranged in parallel with the sides of the upper surface of the die pad, respectively, in the plan view;a second semiconductor chip having a second main surface, a second pad group formed over the second main surface, and a second back surface opposite to the second main surface, and arranged over the upper surface of the die pad, and arranged next to the first semiconductor chip in the plan view; anda plurality of first down bonding wire groups electrically connecting the first pad groups of the ...

Semiconductor device including semiconductor chip mounted on lead frame

A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

A semiconductor device has a plurality of electronic components mounted on an insulating substrate formed with a metal layer, and electrically connected to each other or to the metal layer; a positioning wire member having a predetermined diameter and a predetermined length, and bonded to each of the plurality of electronic components or to the metal layer; a lead frame disposed to bridge and electrically connect the plurality of electronic components to each other or between the metal layer and the electronic components; and an opening having a size capable of inserting the wire member therethrough formed to penetrate through the lead frame, to join the lead frame to each of the electronic components or the metal layer at a predetermined position therein. The lead frame is positioned on the insulating substrate by inserting the wire member into the opening. 1. A semiconductor device , comprising:a plurality of electronic components mounted on an insulating substrate formed with a metal layer, and electrically connected to each other or to the metal layer;a positioning wire member having a predetermined diameter and a predetermined length, and bonded to each of the plurality of electronic components or to the metal layer;a lead frame disposed to bridge and electrically connect the plurality of electronic components to each other or between the metal layer and the electronic components; andan opening having a size capable of inserting the wire member therethrough and formed to penetrate through the lead frame, to join the lead frame to each of the electronic components or the metal layer at a predetermined position therein,wherein the lead frame is positioned on the insulating substrate by inserting the wire member into the opening.2. The semiconductor device according to claim 1 , wherein the lead frame comprises:at least a pair of joints contacting the electronic components or the metal layer,rising portions rising from each of the pair of joints, anda connector ...

SURFACE MOUNT PACKAGE FOR A SEMICONDUCTOR INTEGRATED DEVICE, RELATED ASSEMBLY AND MANUFACTURING PROCESS

A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package. 1. A surface mount package comprising:an encapsulation housing a die of semiconductor material, the encapsulation including a first surface having a coupling element configured to mechanically engage a corresponding coupling element of a first surface of a circuit board; andelectrical contact leads protruding from the encapsulation and configured to be coupled to contact pads of the first surface of the circuit board.2. The package according to claim 1 , wherein the coupling element of the encapsulation is a recess claim 1 , to wherein the engagement between the recess and the coupling element of the circuit board restricts movement of the encapsulation when the package is mounted onto the first surface of the circuit board.3. The package according to claim 2 , wherein the recess has a depth along a direction transverse to the first surface comprised between 50 μm and 150 μm.4. The package according to claim 3 , wherein the recess is a first recess claim 3 , the package further comprising a second recess claim 3 , the second recess being configured to receive a second coupling element of the first surface of the circuit board.5. The package according to claim 4 , wherein the encapsulation has a generically ...

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire. 1. A semiconductor device comprising:a first unit device including a semiconductor chip, a backside electrode in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode;a second unit device having a function different from that of the first unit device;a resin layer fixing the first and second unit devices to each other; anda first wiring formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.2. The device according to claim 1 , wherein the semiconductor chip includes a first pad electrode formed on a surface of the semiconductor chip claim 1 ,and the first wiring is electrically connected to the first pad electrode.3. The device according to claim 2 , wherein the first unit device includes a metallic ball unit and a wire unit connected to the ball unit on the first pad electrode claim 2 ,and the first wiring is in contact with the wire unit to be electrically connected to the first pad electrode.4. The device according to claim 1 , wherein the backside electrode is a ground potential.5. The device according to claim 1 , wherein the semiconductor chip includes a second pad electrode that is formed on a surface of the semiconductor chip claim 1 , the second unit device includes an I/O electrode claim 1 ,and the device comprises a ...

Power Quad Flat No-Lead (PQFN) Semiconductor Package with Leadframe Islands for Multi-Phase Power Inverter

According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a U-phase output node situated on a first leadframe island of a leadframe, a V-phase output node situated on a second leadframe island of said leadframe, and a W-phase output node situated on a W-phase die pad of said leadframe. The first leadframe island can be on a first leadframe strip of the leadframe, where the first leadframe strip is connected to a U-phase die pad of the leadframe. The second leadframe island can be on a second leadframe strip of the leadframe, where the second leadframe strip is connected to a V-phase die pad of the leadframe. A first W-phase power switch is situated on the W-phase die pad. Furthermore, at least one wirebond is connected to the W-phase die pad and to a source of a second W-phase power switch. The W-phase die pad can be a W-phase output terminal of the PQFN package. 1. A power quad flat no-lead (PQFN) package comprising:a U-phase output node situated on a first leadframe island of a leadframe;a V-phase output node situated on a second leadframe island of said leadframe;a W-phase output node situated on a W-phase die pad of said leadframe.2. The PQFN package of claim 1 , comprising a first W-phase power switch situated on said W-phase die pad.3. The PQFN package of claim 1 , comprising at least one wirebond connected to said W-phase die pad.4. The PQFN package of claim 1 , comprising at least one wirebond connecting a source of a second W-phase power switch to said W-phase die pad.5. The PQFN package of claim 1 , comprising at least one wirebond connected to said first leadframe island of said leadframe.6. The PQFN package of claim 1 , comprising at least one wirebond connected to said second leadframe island of said leadframe.7. The PQFN package of claim 1 , wherein said first leadframe island is exposed on a bottom-side of said PQFN package.8. The PQFN package of claim 1 , wherein said second leadframe island is exposed on a bottom- ...

LEADFRAME FOR SEMICONDUCTOR PACKAGES

A leadframe for semiconductor packages is provided. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. The leads includes a first lead and a second lead being at opposite locations of the leadframe relative to a center line through the die pad. The first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values. The plurality of leads are disconnected to each other. 1. A leadframe for semiconductor packages , comprising:a die pad;a side rail around the die pad;a tie bar connecting the die pad and the side rail; anda plurality of leads extending from the side rail in close proximity to the die pad, comprising a first lead and a second lead being at opposite locations of the leadframe relative to a center line through the die pad, wherein the first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values, wherein the plurality of leads are disconnected to each other.2. The leadframe as claimed in claim 1 , wherein the first and second leads comprise substantially different lead lengths.3. The leadframe as claimed in claim 1 , wherein the first and second leads comprise substantially different lead widths.4. The leadframe as claimed in claim 1 , wherein the first and second leads comprise substantially asymmetrical extending traces.5. The leadframe as claimed in claim 1 , wherein the plurality of leads further comprise a third lead adjacent to the first lead claim 1 , and a fourth lead adjacent to the second lead.6. The leadframe as claimed in claim 5 , wherein a space between the first and third leads is substantially different from that between the second and fourth leads.7. The leadframe as claimed in claim 5 , wherein a pitch between the ...

Open Source Power Quad Flat No-Lead (PQFN) Leadframe

According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase power switch is connected to a U-phase output strip of the PQFN leadframe. A source of the U-phase power switch is connected to a U-phase current sense terminal. The U-phase output strip can substantially traverse across the PQFN leadframe. Another U-phase power switch is situated on the PQFN leadframe with a source of the another U-phase power switch connected to the U-phase output strip of the PQFN leadframe. The PQFN leadframe can include a leadframe island within the U-phase output strip. At least one wirebond may be connected to the U-phase output strip. 1. A power quad flat no-lead (PQFN) leadframe comprising:U-phase, V-phase, and W-phase power switches situated on said PQFN leadframe;a drain of said U-phase power switch being connected to a U-phase output strip of said PQFN leadframe;a source of said U-phase power switch being connected to a U-phase current sense terminal.2. The PQFN leadframe of claim 1 , wherein said U-phase output strip substantially traverses across said PQFN leadframe.3. The PQFN leadframe of comprising a first leadframe island within said U-phase output strip.4. The PQFN leadframe of comprising at least one wirebond connected to said U-phase output strip.5. The PQFN leadframe of comprising another U-phase power switch situated on said PQFN leadframe claim 1 , a source of said another U-phase power switch connected to said U-phase output strip of said PQFN leadframe.6. The PQFN leadframe of claim 1 , comprising at least one wirebond connecting said source of said U-phase power switch to said U-phase current sense terminal.7. The PQFN leadframe of claim 1 , wherein said U-phase power switch is situated on a U-phase output pad of said PQFN leadframe.8. The PQFN leadframe of comprising a driver integrated circuit (IC) situated on said PQFN leadframe ...

Power Quad Flat No-Lead (PQFN) Package in a Single Shunt Inverter Circuit

According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC. 1. A power quad flat no-lead (PQFN) package comprising:a driver integrated circuit (IC) situated on a leadframe;U-phase, V-phase, and W-phase power switches situated on said leadframe;a logic ground of said leadframe coupled to a support logic circuit of said driver IC;a power stage ground of said leadframe coupled to sources of said U-phase, V-phase, and W-phase power switches.2. The PQFN package of claim 1 , wherein said power stage ground is further coupled to gate drivers of said driver IC.3. The PQFN package of claim 1 , comprising at least one wirebond connecting said power stage ground of said leadframe to said source of said W-phase power switch.4. The PQFN package of claim 1 , comprising at least one wirebond connecting said source of said W-phase power switch to said source of said V-phase power switch.5. The PQFN package of claim 1 , comprising at least one wirebond connecting said source of said V-phase power switch to said source of said U-phase power switch.6. The PQFN package of claim 1 , comprising at least one wirebond connecting a power stage ground terminal of said PQFN package to said source of said W-phase power switch.7. The PQFN package of claim 1 , comprising at least one wirebond connecting a logic ground terminal of said PQFN package to said support logic circuit of said driver IC.8. The PQFN package of claim 1 , comprising at least one wirebond connecting said ...

Power Semiconductor Package with Non-Contiguous, Multi-Section Conductive Carrier

In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed. The power semiconductor package according to the present disclosure results in effective thermal protection, current carrying capability, and a relatively small size.

WAFER LEVEL CHIP SCALE PACKAGE WITH EXPOSED THICK BOTTOM METAL

A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices. 1. A wafer level chip scale (WLCS) package device with a thick bottom metal comprising:a semiconductor chip including a plurality of bonding pads formed on a front surface each having a plurality of metal interconnecting structures formed thereon;a bottom metal layer covering at a back surface opposite the front surface of the semiconductor chip;a thick bottom metal different from the bottom metal layer attached on the bottom metal layer through a conductive bonding layer, said thick bottom metal having a thick central portion extending within an area of the semiconductor chip and a thin portion extending substantially to a sidewall of the semiconductor chip;a top package layer covering the front surface of the chip and surrounding a sidewall of each metal interconnecting structure; anda package body surrounding at least a bottom portion of the semiconductor chip sidewall adjacent to the back surface and a sidewall of the thick bottom metal.2. The WLCS package device of claim 1 , wherein the package body further surrounds the entire sidewall of the semiconductor chip and a sidewall of the top package layer.3. The WLCS package device of claim 1 , wherein the bonding pads comprise a first bonding pad and a second bonding pad and the semiconductor chip further comprises a through via aligning with the second bonding pad and penetrating through the ...

Semiconductor package

Provided are a semiconductor die and a semiconductor package. The semiconductor package includes: a monolithic die; a driving circuit, a low-side output power device, and a high-side output power device disposed in the monolithic die; and an upper electrode and a lower electrode disposed above and below the monolithic die.

SELECTIVE TREATMENT OF LEADFRAME WITH ANTI-WETTING AGENT

Embodiments of the present disclosure are directed to a leadframe packages that include a leadframe having a surface that is selectively treated with chemicals that reduce the wettability of the surface and thereby reduce adhesive flow on the surface and methods of forming a packing comprising same. In one embodiment there is provided a leadframe having an upper surface that includes a first portion that is treated with an anti-epoxy bleed out chemical and a second portion that was not treated with the anti-epoxy bleed out chemical. A semiconductor die is attached to the upper surface of the leadframe at the second portion via an epoxy adhesive. 1. A leadframe package comprising:a die pad having an upper surface that is treated at a first location with an anti-wetting agent, the anti-wetting agent configured to reduce adhesive bleed out on the treated upper surface of the die pad at the first location;at least one lead located proximate to the die pad;a die secured to the upper surface of the die pad at a second location via an adhesive, the second location being untreated with the anti-wetting agent; andencapsulation material located over the die and the upper surface of the die pad.2. The leadframe package of wherein first location is located outwardly of the second location.3. The leadframe package of wherein the first location has a rectangular or square shape and the second location being located in the center of the rectangular or square shape of the first location.4. The leadframe package of wherein the first location is outwardly bound a distance from a perimeter of the die pad.5. The leadframe package of wherein the first location has an edge that is equal to or slightly larger than the perimeter of the die pad.6. The leadframe package of the adhesive abuts an edge of the first location.7. A method of forming a leadframe package claim 1 , the method comprising:treating a first portion of an upper surface of a die pad with an anti-wetting agent without ...

LEADLESS PACKAGES AND METHOD OF MANUFACTURING SAME

Embodiments of the present disclosure are directed to leadframe strips and methods of forming packages that include first separating adjacent leads of a leadframe strip and subsequently singulating components into individual packages. In one embodiment, the adjacent leads are separated by etching through the leads, thereby providing electrical isolation of the adjacent packages. In that regard, if desired, the individual adjacent packages may be electrically tested in leadframe strip form. Subsequently, the individual packages are formed by sawing through the encapsulation material. 1. A method comprising:coupling a first die to a first die pad;coupling a second die to a second die pad;coupling a first end of a first conductive wire to a pad of the first die and coupling a second end of the first conductive wire to a first lead;coupling a first end of a second conductive wire to a pad of the second die and coupling a second end of the second conductive wire to a second lead, the first and second leads being connected to each other by a connecting bar, the first lead, the second lead and the connecting bar each having a respective bottom surface;encapsulating the first and second dice, the first and second conductive wires, and portions of the first and second leads and the connecting bar with encapsulation material, a surface of the encapsulation material being coplanar with a surface of the first and second die pads and the first and second leads;removing the connecting bar by chemically etching the connecting bar and to expose a surface of the encapsulation material; andcutting through the encapsulation material at the exposed surface and forming individual packages.2. The method of further comprising plating the bottom surfaces of the first and second leads with Ni/Pd/Ag and leaving the bottom surface of the connecting bar un-plated claim 1 , wherein removing the connecting bar by chemically etching the connecting bar comprises using a single etch chemistry to ...

Semiconductor device

A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.

SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE USED THEREFOR

A semiconductor module includes a first heat sink member, a semiconductor device, a second heat sink member, a lead frame, a second sealing member. The semiconductor device includes a semiconductor element, a first sealing member for covering the semiconductor element, a first wiring and a second wiring electrically connected to the semiconductor element, and a rewiring layer on the semiconductor element and the sealing member. The second heat sink member is disposed on the semiconductor device. The lead frame is electrically connected to the semiconductor device through a bonding member. The second sealing member covers a portion of the first heat sink member, the semiconductor and a portion of the second heat sink member. A surface of the second heat sink member faces the semiconductor device. The semiconductor device has a portion protruded from an outline of the second surface sink member. 1. A semiconductor module comprising:a first heat sink member; a semiconductor element,', 'a first sealing member covering the semiconductor element,', 'a first wiring and a second wiring electrically connected to the semiconductor element, and', 'a rewiring layer disposed on the semiconductor element and the sealing member;, 'a semiconductor device including'}a second heat sink member disposed on the semiconductor device;a lead frame electrically connected to the semiconductor device through a bonding member; anda second sealing member covering a portion of the first heat sink member, the semiconductor and a portion of the second heat sink member,wherein the second heat sink member has a first surface and a second surface,wherein the second surface of the second heat sink member faces the semiconductor device,wherein the semiconductor device has a portion protruded from an outline of the second surface of the second heat sink member, andwherein the second wiring has an end extending to the portion of the semiconductor device protruded from the outline of the second surface of ...

Semiconductor device

Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

It is an object to provide a method for manufacturing a semiconductor device which can reduce degradation in package strength and a manufacturing cost, and promote miniaturization of a package. A method for manufacturing a semiconductor device includes steps of (a) preparing a lead frame having a die pad on which a semiconductor element is mounted, (b) placing a first resin which is granular in a mold, (c) placing the lead frame in the mold in such a manner that the first resin comes into contact with a lower side of the die pad, (d) filling the mold with a second resin on an upper side of the first resin in the mold, and (e) curing the first resin and the second resin, to mold the first resin and the second resin. 1. A method for manufacturing a semiconductor device , comprising the steps of:(a) preparing a lead frame having a die pad on which a semiconductor element is mounted;(b) placing a first resin which is granular in a mold;(c) placing said lead frame in said mold in such a manner that said first resin comes into contact with a lower side of said die pad;(d) filling said mold with a second resin on an upper side of said first resin in said mold; and(e) curing said first resin and said second resin, to mold said first resin and said second resin.2. The method for manufacturing a semiconductor device according to claim 1 , whereinsaid step (b) includes a step of placing said first resin which is powdery or fragmentary in the mold.3. The method for manufacturing a semiconductor device according to claim 1 , whereinsaid mold includes a side gate for injecting said second resin sideways relative to said semiconductor element,said step (d) includes a step of injecting said second resin from said side gate of said mold to fill said mold, andsaid step (e) includes a step of molding said first resin and said second resin with said first resin being compressed by said second resin.4. The method for manufacturing a semiconductor device according to claim 1 , ...

Electronic device and method of manufacturing the same

Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size. 1. An electronic device comprising:a mounting surface configured to mount the electronic device to an external structure and having a first size;a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode;wherein the first size is at least three times the second size.2. The electronic device according to claim 1 , wherein the first size is at least five times the second size.3. The electronic device according to claim 1 , further comprising an encapsulation encapsulating at least partially the electronic device.4. The electronic device according to claim 3 , wherein the encapsulation is formed by an encapsulation material at least partially forming the backside of the electronic device.5. The electronic device according to claim 3 , wherein the encapsulation comprises a plurality of encapsulation materials claim 3 , wherein a first encapsulation material covers the backside of the backside electrode and a second encapsulation material covers a frontside of the electronic device.6. The electronic device according to claim 5 , wherein the first encapsulation material has a different dielectric constant than the second encapsulation material.7. The electronic device according to claim 5 , wherein the first encapsulation material has a different specific heat conductivity than the second encapsulation material.8. The electronic device according to claim 1 , wherein the mounting surface and the backside surface partially overlap in area.9. An electronic module comprising{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'an ...

METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE HAVING A MULTI-LAYER ENCAPSULATED CONDUCTIVE SUBSTRATE AND STRUCTURE

In one embodiment, a semiconductor package includes a multi-layer encapsulated conductive substrate having a fine pitch. The multi-layer encapsulated conductive substrate includes a conductive leads spaced apart from each other, a first encapsulant disposed between the leads, a first conductive layer electrically connected to the plurality of leads, conductive pillars disposed on the first conductive layer, a second encapsulant encapsulating the first conductive layer and the conductive pillars, and a second conductive layer electrically connected to the conductive pillars and exposed in the second encapsulant. A semiconductor die is electrically connected to the second patterned conductive layer. A third encapsulant covers at least the semiconductor die. 1. A semiconductor package comprising: a plurality of leads spaced apart from each other;', 'a first encapsulant disposed between the plurality of leads;', 'a first conductive layer electrically connected to the plurality of leads;', 'conductive pillars disposed on the first conductive layer;', 'a second encapsulant encapsulating the first conductive layer and the conductive pillars; and', 'a second conductive layer electrically connected to the conductive pillars and disposed adjacent the second encapsulant;, 'a multi-layer encapsulated conductive substrate comprisinga semiconductor die electrically coupled to the second conductive layer; anda third encapsulant encapsulating at least the semiconductor die.2. The semiconductor package of claim 1 , wherein a bottom surface of the first encapsulant protrudes to a bottom portion of the multi-layer encapsulated conductive substrate more than bottom surfaces of the plurality of leads.3. The semiconductor package of further comprising:solder structures attached to the bottom surfaces of the plurality of leads.4. The semiconductor package of claim 1 , wherein bottom surfaces of the plurality of leads protrude to a bottom portion of the multi-layer encapsulated conductive ...

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE

A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer. 121-. (canceled)22. A semiconductor device manufacturing method , comprising:preparing a semiconductor chip, a heat radiation plate and a lead frame having a die pad section;joining the semiconductor chip to the die pad section;causing the heat radiation plate to directly face the die pad section; andforming an encapsulating resin portion that covers the semiconductor chip, the heat radiation plate and the die pad section,wherein the act of forming the encapsulating resin portion comprises joining the heat radiation plate and the die pad section by the encapsulating resin portion23. The method of claim 22 , wherein the die pad section has a die pad major surface and a die pad rear surface claim 22 , the act of joining the semiconductor chip comprises joining the semiconductor chip to the die pad major surface claim 22 , and causing the heat radiation plate to directly face the die pad section comprises causing the heat radiation plate to directly face the die pad rear surface.24. The method of claim 23 , wherein the heat radiation plate is exposed from the encapsulating resin portion in the act of forming the encapsulating resin portion.25. The method of claim 22 , further comprising preparing a first mold ...

ELECTRONIC DEVICE COMPRISING AN IMPROVED LEAD FRAME

An electronic device includes a chip and a support element which supports the chip. Leads are provided to be electrically coupled to at least one terminal of the chip. A coupling element is mounted to a free region of the support element that is not occupied by the chip. The coupling element includes a conductive portion electrically connected to at least one lead and to the at least one terminal of the chip to obtain an electrical coupling. 1. An electronic device , comprising:a chip of semiconductor material configured to implement functionalities of the electronic device,a support element for supporting the chip,a plurality of leads each one adapted to be electrically coupled to at least one terminal of the chip, anda coupling element on a free region of the support element that is not occupied by the chip, said coupling element comprising a conductive portion electrically connected to at least one lead and to the at least one terminal of the chip to obtain said electrical coupling.2. The electronic device according to claim 1 , wherein the conductive portion is electrically connected to the at least one lead by a wire connection between the at least one lead and a region of the conductive portion proximal to the at least one lead claim 1 , and wherein the conductive portion is electrically connected to the at least one terminal by a wire connection between the at least one terminal and a region of the conductive portion proximal to the at least one terminal.3. The electronic device according to claim 1 , further comprising an electronic component configured to be electrically coupled to the at least one lead claim 1 , said electronic component being mounted claim 1 , within the electronic device claim 1 , on the coupling element claim 1 , and being electrically connected claim 1 , within the electronic device claim 1 , to said at least one lead and to said at least one terminal of the chip.4. The electronic device according to claim 3 , wherein said conductive ...

Matrix Lid Heatspreader for Flip Chip Package

A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array () designed for direct attachment to an array of integrated circuit die () by including a thermal interface adhesion layer () to each die () and encapsulating the attached heat spreader lid array () and array of integrated circuit die () with mold compound () except for planar upper lid surfaces of the heat spreader lids (). 110-. (canceled)11. A semiconductor package , comprising:a substrate having first and second surfaces;a die having first and second surfaces, where the first surface of the die is flip-chip bonded to the first surface of the substrate;a compressed, laterally expansive, thermally conductive interface layer formed to cover the second surface of the die; anda heat spreader lid comprising an exposed heat dissipation surface layer and a plurality of connection spars extending laterally from the heat dissipation surface layer, where the heat dissipation surface layer contacts the compressed, laterally expansive, thermally conductive interface layer and is positioned apart from the substrate to define an encapsulation molding region in which encapsulation mold compound material is located to permanently attach the substrate, die, and heat spreader lid.12. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally to be co-planar with the exposed heat dissipation surface layer.13. The semiconductor package of claim 11 , where the plurality of connection spars extend laterally as downset connection spars that are not co-planar with the exposed heat dissipation surface layer.14. The semiconductor package of claim 11 , where the heat spreader lid is formed with a thermally conductive layer of copper claim 11 , nickel or an alloy thereof.15. The semiconductor package of claim 11 , where the exposed heat dissipation surface layer has a thermal contact surface that is at ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a circuit pattern, at least one or more wires joined thereto, an electrode terminal joining thereto, and a semiconductor element. The electrode terminal includes a horizontally extending portion extending along a main surface and connected to the wire, and a bent portion at which an extending direction of the electrode terminal is changed relative to the horizontally extending portion. Each of the wires has joint portions at which each of the wires and the circuit pattern are joined to each other. In a plan view, the joint portions are located on an outside of a portion where each of the wires and the electrode terminal overlap each other. 1. A semiconductor device comprising:a circuit pattern formed on one main surface of an insulating substrate and at least partially having conductivity;at least one or more wires joined to the circuit pattern and having conductivity,an electrode terminal joined to the wires, thereby being electrically connected to the circuit pattern; anda semiconductor element joined to the circuit pattern,the electrode terminal including a horizontally extending portion extending along the one main surface and connected to the wires, and a bent portion at which an extending direction of the electrode terminal is changed relative to the horizontally extending portion,each of the wires having a joint portion at which each of the wires and the circuit pattern are joined to each other,in a plan view, the joint portion being located on an outside of a portion where each of the wires and the electrode terminal overlap each other.2. The semiconductor device according to claim 1 , wherein the joint portions are provided at two or more positions so as to be spaced apart from each other.3. The semiconductor device according to claim 1 , wherein the joint portion is arranged in a region on a side of the horizontally extending portion with respect to the bent portion in a direction connecting the horizontally extending ...

SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode. 1. A semiconductor component having at least first and second terminals , comprising:a leadframe having first and second opposing sides, a device receiving area, and a first lead integrally formed with the leadframe;an insulated metal substrate having a first surface and a second surface, the second surface coupled to the leadframe;a first semiconductor chip mounted to the insulated metal substrate, the first semiconductor chip having first and second surfaces, a first gate bond pad, a first source bond pad, and a first drain bond pad, the first semiconductor chip configured from a III-N semiconductor material, wherein the second surface of the first semiconductor chip is coupled to the insulated metal substrate; anda second semiconductor chip mounted to the first semiconductor chip and having first and second surfaces, an anode formed from the first surface and a cathode formed from the second surface, wherein the cathode is coupled to the first source bond pad.2. The semiconductor component of claim 1 , further including a second lead that is electrically isolated from the leadframe and wherein the first gate bond pad is electrically coupled to ...

Printed circuit board element and method for producing a printed circuit board element

The invention relates to an electronic component, namely a printed circuit board element comprising a first semiconductor component () which is arranged on an upper side of an electrically conductive intermediate plate () such that a connector pad () of the semiconductor component () is electrically contacted with the intermediate plate () and comprising a second semiconductor component () which is arranged on a lower side of the intermediate plate (). The second semiconductor component () comprises a first connector pad () and a second connector pad (), wherein both connector pads () are aligned in the direction of the intermediate plate () and wherein the first connector pad () is contacted with the intermediate plate (), and wherein the second connector pad () is not contacted with the intermediate plate (). Moreover, the invention relates to a method for producing such a printed circuit board element. 1. A printed circuit board element comprising:a first semiconductor component which is arranged on an upper side of an electrically conductive intermediate plate such that a connector pad of the first semiconductor component has a whole-area electrical contact with the intermediate plate;a second semiconductor component which is arranged on a lower side of the intermediate plate;the second semiconductor component comprises a first connector pad and a second connector pad;both connector pads are aligned in the direction of the intermediate plate; andthe first connector pad is contacted with the intermediate plate, the second connector pad is not contacted with the intermediate plate, and the intermediate plate forms a phase tap of the printed circuit board element.2. The printed circuit board element as claimed in claim 1 , wherein the intermediate plate comprises a recess for avoiding electrical contact between the intermediate plate and the second connector pad of the second semiconductor component.3. The printed circuit board element as claimed in claim 2 , ...

Lead frame assembly for a semiconductor device

This disclosure relates to a lead frame assembly for a semiconductor device, a semiconductor device and an associated method of manufacture. The lead frame assembly includes a die attach structure and a clip frame structure. The clip frame structure includes a die connection portion configured to contact a contact terminal on a top side of the semiconductor die; and a continuous lead portion extending along the die connection portion. The continuous lead portion is integrally formed with the die connection portion.

Lead frames including lead posts in different planes

A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.

Semiconductor device and method of manufacturing the same

According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.

Enhanced Thermal Transfer in a Semiconductor Structure

A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment. 1. A method for fabricating a semiconductor device have enhanced thermal transfer , the method comprising:providing at least one die including a device layer formed on a front side of a semiconductor substrate, the device layer including one or more functional circuit elements formed therein;attaching the die to a support structure such that the front side of the die is disposed on at least a portion of the support structure; andtexturing a back side of the substrate so as to increase a surface area of the back side of the substrate thereby enhancing thermal transfer between the substrate and an external environment.2. The method of claim 1 , wherein the die is attached to the support structure using at least one connection structure coupled between the device layer and the support structure.3. The method of claim 1 , wherein texturing the back side of the substrate comprises at least one of forming periodic structures in or on the back side of the substrate and forming non-periodic structures in or on the back side of the substrate.4. The method of claim 1 , wherein texturing comprises forming a plurality of trenches in the back side of the substrate claim 1 , a portion of the substrate remaining between adjacent trenches forming periodic fingered structures claim 1 , a surface area of the back side of the substrate being controlled as a function of an aspect ratio of the fingered structures.5. The method of ...

MOLDED INTELLIGENT POWER MODULE FOR MOTORS

An intelligent power module (IPM) has a first, second, third and fourth die supporting elements, a first, second, third, fourth, fifth and sixth transistors, a connection member, a low voltage IC, a high voltage IC, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die supporting element. The second transistor is attached to the second die supporting element. The third transistor is attached to the third die supporting element. The fourth, fifth and sixth transistor s are attached to the fourth die supporting element. The low and high voltage ICs are attached to the connection member. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first, second, third, fourth, fifth and sixth transistors, the connection member and the low and high voltage ICs. The IPM has a reduced thermal resistance of junction-to-case (RJC) compared to a conventional IPM. 1. An intelligent power module (IPM) for driving a motor , the IPM comprising:a first, second, third and fourth die supporting elements;a first transistor attached to the first die supporting element;a second transistor attached to the second die supporting element;a third transistor attached to the third die supporting element;a fourth, fifth, and sixth transistors attached to the fourth die supporting element;a connection member;a low voltage integrated circuit (IC) attached to the connection member; the low voltage IC being electrically connected to the first, second and third transistors;a high voltage IC attached to the connection member, the high voltage IC being electrically connected to the fourth, fifth, and sixth transistors;a first plurality of leads;a second plurality of leads;a first dummy bar; anda molding encapsulation enclosing the first, second, third, and fourth die supporting elements, the first, second, third, fourth, fifth, and sixth transistors, the connection member, the low voltage IC, and the high voltage IC ...

3D-Stacked Module with Unlimited Scalable Memory Architecture for Very High Bandwidth and Very High Capacity Data Processing Devices

A 3-D memory module comprising a plurality of packaged integrated memory circuits or devices is mounted to a substrate with integrated pins that are edge-connected on two surfaces where the top surface provides an edge connection from the integrated memory circuits to an orthogonally-mounted memory controller circuit through a wide-word interface. Each integrated memory device can be accessed independently wherein the memory controller is configured to reduce the wide-word interface to a serial interface which is brought to the opposite surface of the memory module for electrical coupling to an external system or printed circuit assembly. 1. A device comprising a plurality of packaged memory integrated circuits mounted to a substrate with integrated pins that are edge connected on two surfaces where the top surface provides an edge connection from the integrated circuits to an orthogonally mounted memory controller through a wide-word interface and configured where each integrated circuit can be accessed independently and wherein the memory controller reduces the wide-word interface to a serial interface which is routed to an opposite face for attachment to a system substrate.2. A method of producing the device of wherein the package substrate uses a lead frame that is soldered or welded to the substrate and each finger of the lead frame is used for aligning the layers to the required pitch to mount the controller as well as providing a means for compliance and flexibility in achieving said pitch.3. A method using the lead frame of wherein after the plurality of packages are stacked and the lead frame fingers are bent in a J-lead fashion to provide a planar surface for mounting the controller circuit.4. A method of communication between cubes using the faces of the module in any direction independently to allow bypassing of routing signals out of the overall physical memory and back in.5. A method of using the enclosure to help channel communication via waveguide ( ...

Heterojunction Semiconductor Device for Reducing Parasitic Capacitance

A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer. 1. A semiconductor device , comprising:an active layer made of III-V group semiconductor materials;a source electrode disposed on the active layer;a drain electrode disposed on the active layer;a gate electrode disposed above the active layer and between the source electrode and the drain electrode;a gate field plate disposed above the active layer;an interlayer dielectric covering the source electrode, the drain electrode, the gate field plate, and the gate electrode, the interlayer dielectric having a plurality of inter-gate via holes;an inter-source layer disposed on the interlayer dielectric and electrically connected to the source electrode;an inter-drain layer disposed on the interlayer dielectric and electrically connected to the drain electrode;an inter-gate layer disposed on the interlayer dielectric, wherein the gate field plate is separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer; anda plurality of inter-gate plugs filled into the inter-gate via holes;wherein at least one of the inter-gate via holes positioned on the gate field ...

METHOD AND STRUCTURE OF PANELIZED PACKAGING OF SEMICONDUCTOR DEVICES

A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (); laminating low CTE insulating material to fill gaps between chips and grid (); turning over assembly to place carrier under backside of chips and lamination and to remove tape (); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (); optionally plating metal layer (); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (). 1. A method for fabricating packaged semiconductor devices in panel format , comprisingplacing a metallic grid onto an adhesive tape, the grid having a plurality of openings framed by metal rims with sidewalls, each opening sized to accommodate one or more discrete semiconductor chips;placing semiconductor chips inside each opening, the chips spaced by gaps between adjacent chips and sidewalls, and attaching the chips onto the adhesive tape with the metallized terminals facing the tape, the chips coated with a layer of insulating inert polymer, the layer having openings to expose chip terminals;laminating, under vacuum suction, a compliant insulating material to cohesively fill the gaps between adjacent chips and sidewalls, thereby forming an assembly with a planar surface, the material having a coefficient of thermal expansion approaching the coefficient of the semiconductor chips;placing a carrier sheet over the assembly and attaching the sheet to the planar surface;turning over the metallic grid with the assembly so that the adhesive tape is facing up for removing the tape and exposing the coats and terminals of the chip surfaces;plasma-cleaning, in an equipment for sputtering metals, the exposed chip and lamination surfaces;sputtering, at uniform energy and rate and while cooling the assembly, at least ...

Semiconductor device

Provided is a semiconductor device including a package having a hollow portion, which can meet the need of reduction in size and thickness. The semiconductor device includes: a resin molded member ( 1 ) including a hollow portion ( 10 ) having an inner bottom surface on which a semiconductor chip ( 6 ) is mounted, a surrounding portion ( 1 b ) that surrounds the hollow portion ( 10 ), and a bottom surface portion ( 1 a ); an inner lead ( 2 e, 2 f ); and an outer lead ( 2 a, 2 b ) exposed from the resin molded member ( 1 ). The inner lead buried in the molded member ( 1 ) includes an L-shaped lead extending portion having a through hole formed therethrough.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A semiconductor device includes a die pad, which includes an upper surface and a lower surface, the upper surface forming a rectangular shape in plan view; a plurality of support pins that support the die pad; a plurality of inner leads arranged around the die pad; a plurality of outer leads connected to each of the inner leads; a semiconductor chip which includes a main surface and a back surface and in which a plurality of electrode pads is formed in the main surface; a plurality of wires which electrically couple the electrode pads of the semiconductor chip to the inner leads respectively; and a sealing body that seals the support pins, the inner leads, the semiconductor chip, and the wires. A first support pin of the plurality of support pins is integrally formed together with the die pad. The first support pin is terminated inside the sealing body. 1. A semiconductor device comprising:a die pad, which includes an upper surface and a lower surface opposite to the upper surface, the upper surface forming a rectangular shape in plan view;a plurality of support pins that support the die pad;a plurality of inner leads arranged around the die pad;a plurality of outer leads connected to each of the inner leads;a semiconductor chip which includes a main surface and a back surface opposite to the main surface and in which a plurality of electrode pads is formed in the main surface, the semiconductor chip being mounted over the die pad so that the back surface faces the upper surface of the die pad;a plurality of wires which electrically couple the electrode pads of the semiconductor chip to the inner leads respectively; anda sealing body that seals the support pins, the inner leads, the semiconductor chip, and the wires,wherein a first support pin of the plurality of support pins is integrally formed together with the die pad,wherein the first support pin is terminated inside the sealing body.2. The semiconductor device according to claim 1 ,wherein a tip of the first ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces. 132-. (canceled)33. A semiconductor device comprising:a first lead frame formed integral with first two terminals respectively extending from the first lead frame, the first two terminals including respective curved portions curved so that edges of the first two terminals are placed in line with other lead terminals than the first two terminals in a plain view, each of the respective curved portions having two mutually opposing and continuously curved edges each having a center of curvature located on a same side of said each edge in plan view as proceeding along said each edge;a first elongated semiconductor chip mounted on the first lead frame and having a first edge and a second edge in plan view, the first edge being parallel to a longitudinal direction of the first elongated semiconductor chip and greater in length than the second edge, the second edge being perpendicular to the first edge;an isolator chip mounted on the first lead frame;a second lead frame formed with second two terminals respectively extending from the second lead frame, the second two terminals are curved so that edges of the second ...

SURFACE MOUNT PACKAGE FOR A SEMICONDUCTOR DEVICE

A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension. 1. A lead of a semiconductor package , comprising:a central segment having a first side and a second side;a first extension from a portion of the first side;a second extension from a portion of the second side; anda recess extending through a portion of the central segment, the first extension and the second extension.2. The lead as recited in claim 1 , wherein the first extension intersects a junction between the central segment and the recess on the first side of the central segment.3. The lead as recited in claim 1 , wherein the central segment has a thickness greater than a thickness of the first extension and the second extension.4. The lead as recited in claim 1 , wherein a thickness of the first extension is substantially equal to a thickness of the second extension.5. The lead as recited in claim 1 , wherein the recess comprises a concave shape.6. The lead as recited in claim 1 , wherein the recess comprises a step shape.7. The lead as recited in claim 1 , wherein the first extension of the lead includes an angular edge opposite the recess.8. A package claim 1 , comprising:a semiconductor die attached to a die attach pad; and a central segment having a first side and a second side;', 'a first extension from a portion of the first side;', 'a second extension from a portion of the second side; and', 'a recess extending through a portion of the central segment, the first extension and the second extension of the lead, a portion of the lead being exposed from a molding compound covering the semiconductor die., 'a lead coupled to ...

SEMICONDUCTOR DEVICE, POWER CONVERTER, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING POWER CONVERTER

There is provided a semiconductor device including an insulating substrate provided with a circuit surface, and an external terminal bonded to the circuit surface. The circuit surface has an upper surface that is in contact with and bonded to a part of a lower surface of the external terminal. In at least a part of a portion where the upper surface of the circuit surface and the lower surface of the external terminal are in contact with each other, a melted portion of the circuit surface and the external terminal is formed. A gap between the upper surface of the circuit surface and the lower surface of the external terminal has a size of 20 μm or less. The circuit surface and the external terminal are each made of copper or copper alloy. 1. A semiconductor device comprising:a metal plate;a semiconductor element disposed on an upper surface of the metal plate via a bonding material; andan external terminal bonded to the upper surface of the metal plate,whereinthe upper surface of the metal plate and a lower surface of the external terminal are in contact with each other via a conductive material,in at least a part of a portion where the upper surface of the metal plate and the lower surface of the external terminal are in contact with each other, a melted portion of the metal plate, the external terminal, and the conductive material is formed, andthe metal plate and the external terminal are each made of copper or copper alloy.2. The semiconductor device according to claim 1 , further comprising a sealing material formed covering the metal plate claim 1 , the semiconductor element claim 1 , and a part of the external terminal.3. The semiconductor device according to claim 1 , wherein the conductive material is formed beyond a range where the metal plate and the external terminal overlap with each other in plan view.4. The semiconductor device according to claim 1 , wherein a plurality of the melted portions is formed.5. A power converter comprising: a metal plate;', ...