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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 24101. Отображено 100.

05-01-2012 дата публикации

Double molded chip scale package

Номер: US20120001322A1

Автор: Luke England, Yong Liu

Принадлежит: Fairchild Semiconductor Corp

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

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Номер записи: 1

05-01-2012 дата публикации

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Номер: US20120003830A1

Автор: Haijing Cao, Qing Zhang, Yaojian Lin

Принадлежит: Individual

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

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Номер записи: 2

12-01-2012 дата публикации

Wiring board and method for manufacturing the same

Номер: US20120006592A1

Автор: Makoto Terui, Shigeru Yamada, Shinji OUCHI, Yoshinori Shizuno

Принадлежит: Ibiden Co Ltd

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

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Номер записи: 3

12-01-2012 дата публикации

Method of forming cu pillar capped by barrier layer

Номер: US20120007231A1

Автор: Wei Sen CHANG

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

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Номер записи: 4

12-01-2012 дата публикации

Microelectronic packages with dual or multiple-etched flip-chip connectors

Номер: US20120007232A1

Автор: Belgacem Haba

Принадлежит: TESSERA RESEARCH LLC

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

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Номер записи: 5

12-01-2012 дата публикации

Redistribution layers for microfeature workpieces, and associated systems and methods

Номер: US20120007256A1

Автор: David Pratt

Принадлежит: Micron Technology Inc

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

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Номер записи: 6

19-01-2012 дата публикации

Methods of forming semiconductor chip underfill anchors

Номер: US20120012987A1

Автор: Neil McLellan, Roden R. Topacio

Принадлежит: Individual

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

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Номер записи: 7

19-01-2012 дата публикации

Conductive Sidewall for Microbumps

Номер: US20120012998A1

Автор: Arvind Chandrasekaran, Christine S. Hay-Riege, Shiqun Gu

Принадлежит: Qualcomm Inc

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

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Номер записи: 8

26-01-2012 дата публикации

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

Номер: US20120018904A1

Автор: Jianmin Fang, KANG Chen, Xia Feng, Yaojian Lin

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

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Номер записи: 9

02-02-2012 дата публикации

Semiconductor device and method of designing a wiring of a semiconductor device

Номер: US20120025377A1

Автор: Hideaki Ikuma, Shoji Seta, Yukihito Oowaki

Принадлежит: Toshiba Corp

A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

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Номер записи: 10

09-02-2012 дата публикации

Metal semiconductor alloy structure for low contact resistance

Номер: US20120032275A1

Автор: Balasubramanian S. Haran, Sivananda K. Kanakasabapathy

Принадлежит: International Business Machines Corp

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

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Номер записи: 11

16-02-2012 дата публикации

High-frequency switch

Номер: US20120038411A1

Автор: Hirotsugu Wakimoto, Masanori Ochi, Masayuki Sugiura, Noriyasu Kurihara, Toshiki Seshita, Toshiyuki Shimizu, Yoshio Itagaki, Yoshitomo Sagae

Принадлежит: Toshiba Corp

According to one embodiment, a high-frequency switch includes a high-frequency switch IC chip. The high-frequency switch IC chip has a high-frequency switching circuit section including an input terminal, a plurality of switching elements, a plurality of high-frequency signal lines, and a plurality of output terminals. The input terminal is connected to each of the plurality of output terminals via each of the plurality of switching elements with the high-frequency signal lines having the same lengths. The plurality of output terminals are arranged on a surface at an outer periphery of the high-frequency switch IC chip. The input terminal is arranged on the surface of the high-frequency switch IC chip at the center of the high-frequency switch IC circuit section.

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Номер записи: 12

23-02-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120043592A1

Автор: Chao Zhao, Huilong Zhu, Wenwu Wang

Принадлежит: Institute of Microelectronics of CAS

The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

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Номер записи: 13

23-02-2012 дата публикации

Method of making interconnect structure

Номер: US20120045893A1

Автор: Heinrich Koerner

Принадлежит: Individual

One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.

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Номер записи: 14

01-03-2012 дата публикации

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

Номер: US20120049343A1

Автор: Frank Kuechenmeister, Lei Fu, Michael Su, Thomas Schulze

Принадлежит: Advanced Micro Devices Inc, Globalfoundries Inc

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

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Номер записи: 15

15-03-2012 дата публикации

Semiconductor chip with redundant thru-silicon-vias

Номер: US20120061821A1

Автор: Bryan Black, Gamal Refai-Ahmed, Joe Siegel, Michael Z. Su, Seth Prejean

Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

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Номер записи: 16

15-03-2012 дата публикации

Semiconductor device having pad structure with stress buffer layer

Номер: US20120061823A1

Автор: Chao-Wen Shih, Shang-Yun Hou, Shin-puu Jeng, Tzu-Wei Chiu, Tzuan-Horng LIU, Wei-Cheng Wu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

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Номер записи: 17

15-03-2012 дата публикации

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

Номер: US20120061834A1

Автор: Tae Min Kang

Принадлежит: Hynix Semiconductor Inc

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

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Номер записи: 18

22-03-2012 дата публикации

Anti-tamper microchip package based on thermal nanofluids or fluids

Номер: US20120068326A1

Автор: James J. McNamara, Jr., Mark D. Poliks, Rabindra N. Das, Voya R. Markovich

Принадлежит: Endicott Interconnect Technologies Inc

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

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Номер записи: 19

22-03-2012 дата публикации

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

Номер: US20120068331A1

Автор: Eric Peeters, Eugene M. Chow

Принадлежит: Palo Alto Research Center Inc

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

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Номер записи: 20

22-03-2012 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20120068334A1

Автор: Hirokazu Ezawa, Soichi Yamashita, Tatsuo Migita

Принадлежит: Toshiba Corp

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

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Номер записи: 21

22-03-2012 дата публикации

Semiconductor device having decreased contact resistance

Номер: US20120070987A1

Автор: David Wu, Donna Michael, MARK Michael, Zhonghai Shi

Принадлежит: Globalfoundries Inc

Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

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Номер записи: 22

12-04-2012 дата публикации

Chip stacked structure

Номер: US20120086119A1

Автор: Ming-Che Wu

Принадлежит: Universal Global Scientific Industrial Co Ltd, Universal Scientific Industrial Shanghai Co Ltd

A chip stacked structure is provided. The chip stacked structure includes a first die and a second die stacked on the first die. The first die has a plurality of connection structures each which has a through hole, a connection pad and a solder bump. The connection pad has a terminal connected to the through hole. The solder bump is disposed on the connection pad and located around the through hole. The second die has a plurality of through holes which are aligned and bonded to the solder bump respectively. The chip stacked structure may simplify the process and improve the process yield rate.

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Номер записи: 23

12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1

Автор: Jeong-Woo Park, Moon-Gi Cho, Sun-Hee Park, Ui-Hyoung Lee

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

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Номер записи: 24

19-04-2012 дата публикации

Non-volatile memory device and methods for manufacturing the same

Номер: US20120091424A1

Автор: Chrong-Jung Lin, Ya-Chin King

Принадлежит: Individual

A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification.

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Номер записи: 25

19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091520A1

Автор: Nobuyuki Nakamura

Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

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Номер записи: 26

19-04-2012 дата публикации

Microelectronic assemblies having compliancy and methods therefor

Номер: US20120091582A1

Автор: Belgacem Haba, David Ovrutsky, Guilian Gao, Vage Oganesian

Принадлежит: Tessera LLC

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

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Номер записи: 27

26-04-2012 дата публикации

Bond pad for wafer and package for cmos imager

Номер: US20120098105A1

Автор: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Richard L. Rassel

Принадлежит: International Business Machines Corp

An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

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Номер записи: 28

26-04-2012 дата публикации

Conductive feature for semiconductor substrate and method of manufacture

Номер: US20120098121A1

Автор: Hsien-Wei Chen, Ying-Ju Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

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Номер записи: 29

03-05-2012 дата публикации

Chip-on-chip structure and manufacturing method therof

Номер: US20120104597A1

Автор: Junji Yoshikawa, Tatsuji Ishiduka, Tsutomu Kojima

Принадлежит: Toshiba Corp

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

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Номер записи: 30

17-05-2012 дата публикации

Method For Segregating The Alloying Elements And Reducing The Residue Resistivity Of Copper Alloy Layers

Номер: US20120121799A1

Автор: Jick M. Yu, Xinyu Fu

Принадлежит: Applied Materials Inc

Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

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Номер записи: 31

24-05-2012 дата публикации

Package carrier

Номер: US20120125669A1

Автор: Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang, Tsung-Fu Tsai

Принадлежит: Industrial Technology Research Institute ITRI

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

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Номер записи: 32

24-05-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120129335A1

Автор: Hiroyuki Yoda, Masamitsu Ikumo, Yoshito Akutagawa

Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

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Номер записи: 33

24-05-2012 дата публикации

Structures and methods for improving solder bump connections in semiconductor devices

Номер: US20120129336A1

Автор: Anthony K. Stamper, Daniel C. Edelstein, Felix P. Anderson, Thomas L. McDevitt, William Cote

Принадлежит: International Business Machines Corp

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

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Номер записи: 34

31-05-2012 дата публикации

Semiconductor device

Номер: US20120133058A1

Автор: Kunihiro Komiya

Принадлежит: ROHM CO LTD

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

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Номер записи: 35

31-05-2012 дата публикации

Semiconductor Structures and Method for Fabricating the Same

Номер: US20120135201A1

Автор: Ching-Hung Ko, Mu-Jia Liu, Tsung-Chieh Chang

Принадлежит: Himax Technologies Ltd

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a second substrate opposite to the first substrate, a plurality of spacers disposed between the first substrate and the second substrate, and an adhesive material bonded with the first substrate and the second substrate within the two adjacent spacers. The invention also provides a method for fabricating the semiconductor structure.

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Номер записи: 36

14-06-2012 дата публикации

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

Номер: US20120146215A1

Автор: Chih-Hung Lu, Yu-Ju Yang

Принадлежит: ILI Techonology Corp

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

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Номер записи: 37

14-06-2012 дата публикации

Semiconductor Device and Method of Manufacture Thereof

Номер: US20120146231A1

Автор: Ludwig Heitzer, Thorsten Meyer

Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

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Номер записи: 38

14-06-2012 дата публикации

Semiconductor device and substrate

Номер: US20120146233A1

Автор: Akira Nakayama

Принадлежит: Oki Semiconductor Co Ltd

A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes.

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Номер записи: 39

14-06-2012 дата публикации

Method for Manufacturing Heat Dissipation Bulk of Semiconductor Device

Номер: US20120149138A1

Автор: Chun-Liang Lin, Kuan-Chun Chen, Yan-Kuin Su

Принадлежит: National Cheng Kung University NCKU

A method for manufacturing a heat dissipation bulk of a semiconductor device including the following steps is described. An electrically conductive layer is formed to cover a surface of a temporary substrate. At least one semiconductor chip is connected to the electrically conductive layer by at least one metal bump, wherein the at least one metal bump is located between the at least one semiconductor chip and the electrically conductive layer. A metal substrate is formed on the electrically conductive layer, wherein the metal substrate fills up a gap between the at least one semiconductor chip and the electrically conductive layer. The temporary substrate is removed.

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Номер записи: 40

21-06-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120153481A1

Автор: Sung Hwan Ahn

Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are disclosed, which can prevent a short-circuit between a bit line contact plug and a storage node contact plug, resulting in improved semiconductor device characteristics. A method for manufacturing a semiconductor device includes: forming a bit line contact hole from which an active region is protruded, by etching a semiconductor substrate; forming a conductive material over the semiconductor substrate including the bit line contact hole; etching the conductive material to form a bit line contact plug and a bit line, each of which has a smaller width than the bit line contact hole; and forming a spacer insulation film over the entire surface of the semiconductor substrate including the bit line contact hole, the bit line contact plug, and the bit line.

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Номер записи: 41

21-06-2012 дата публикации

Semiconductor chip assembly and method for making same

Номер: US20120155055A1

Автор: Belgacem Haba, Hiroaki Sato, Ilyas Mohammed, Kiyoaki Hashimoto, Norihito Masuda, Philip Damberg, Teck-Gyu Kang, Wei-Shun Wang, Yoshikuni Nakadaira

Принадлежит: Tessera LLC

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

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Номер записи: 42

21-06-2012 дата публикации

Method for fabricating semiconductor device with buried gate

Номер: US20120156869A1

Автор: Jong-Han Shin, Kyung-Bo Kim

Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming an isolation layer for defining an active region by using the hard mask pattern, forming a buried gate in and across the active region and the isolation layer over the substrate, forming an inter-layer dielectric layer over the substrate, forming a storage node contact hole that exposes the hard mask pattern by selectively etching the inter-layer dielectric layer, extending the storage node contact hole to expose the active region by removing the hard mask pattern exposed under the storage node contact hole, and forming a storage node contact plug that fills the extended storage node contact hole.

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Номер записи: 43

12-07-2012 дата публикации

Test Contact System For Testing Integrated Circuits With Packages Having An Array Of Signal and Power Contacts

Номер: US20120176151A1

Автор: Brian K. Warwick, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg

Принадлежит: Johnstech International Corp

A test fixture ( 120 ) is disclosed for electrically testing a device under test ( 130 ) by forming a plurality of temporary mechanical and electrical connections between terminals ( 131 ) on the device under test ( 130 ) and contact pads ( 161 ) on the load board ( 160 ). The test fixture ( 120 ) has a replaceable membrane ( 150 ) that includes vias ( 151 ), with each via ( 151 ) being associated with a terminal ( 131 ) on the device under test ( 130 ) and a contact pad ( 161 ) on the load board ( 160 ). In some cases, each via ( 151 ) has an electrically conducting wall for conducting current between the terminal ( 131 ) and the contact pad ( 161 ). In some cases, each via ( 151 ) includes a spring ( 152 ) that provides a mechanical resisting force to the terminal ( 131 ) when the device under test ( 130 ) is engaged with the test fixture ( 120 ).

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Номер записи: 44

12-07-2012 дата публикации

Increasing Dielectric Strength by Optimizing Dummy Metal Distribution

Номер: US20120180018A1

Автор: Hsien-Wei Chen, Tzuan-Horng LIU

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

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Номер записи: 45

19-07-2012 дата публикации

Packaging substrate with conductive structure

Номер: US20120181688A1

Автор: Shih-Ping Hsu

Принадлежит: Individual

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

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Номер записи: 46

19-07-2012 дата публикации

Distributed Metal Routing

Номер: US20120181707A1

Автор: Hung-jen Liao, Jung-Hsuan Chen, Li-Chun Tien, Shao-Yu Chou, Yen-Huei Chen, You-Cheng Xiao

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

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Номер записи: 47

26-07-2012 дата публикации

Integrated structures of high performance active devices and passive devices

Номер: US20120192139A1

Автор: Anthony K. Stamper, Daniel S. Vanslette, Robert M. Rassel

Принадлежит: International Business Machines Corp

Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

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Номер записи: 48

02-08-2012 дата публикации

Customized rf mems capacitor array using redistribution layer

Номер: US20120193781A1

Автор: Jonathan Hale Hammond, Julio Costa, Thomas Scott Morris

Принадлежит: RF Micro Devices Inc

Disclosed is a method for fabricating a customized micro-electromechanical systems (MEMS) integrated circuit using at least one redistribution layer. The method includes steps of providing a substrate on which MEMS components are fabricated and coupling predetermined ones of the MEMS components via the redistribution traces.

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Номер записи: 49

02-08-2012 дата публикации

Semiconductor Package with Embedded Die

Номер: US20120196406A1

Автор: Rajendra D. Pendse

Принадлежит: Stats Chippac Pte Ltd

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

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Номер записи: 50

16-08-2012 дата публикации

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

Номер: US20120208326A9

Автор: Rajendra D. Pendse

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

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Номер записи: 51

23-08-2012 дата публикации

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

Номер: US20120211269A1

Автор: Kouichi Saitou, Toshiya Shimizu

Принадлежит: Sanyo Electric Co Ltd

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

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Номер записи: 52

30-08-2012 дата публикации

Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections

Номер: US20120217610A1

Автор: Luu Nguyen, Peter J. Hopper, Peter Johnson, Peter Smeys

Принадлежит: National Semiconductor Corp

A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

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Номер записи: 53

30-08-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

Номер: US20120217643A1

Автор: Byung Tai Do, Dioscoro A. Merilo, Reza A. Pagaila

Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

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Номер записи: 54

27-09-2012 дата публикации

Apparatuses and methods to enhance passivation and ild reliability

Номер: US20120241952A1

Автор: Bob Sankman, Richard J. Harries, Sudarashan V. Rangaraj

Принадлежит: Individual

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

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Номер записи: 55

11-10-2012 дата публикации

Solder ball contact susceptible to lower stress

Номер: US20120256313A1

Автор: Luc Guerin, Mario J. Interrante, Michael J. Shapiro, Thuy Tran-Quinn, Van T. Truong

Принадлежит: International Business Machines Corp

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

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Номер записи: 56

01-11-2012 дата публикации

Spherical solder reflow method

Номер: US20120273155A1

Автор: Jae-Woong Nah, Peter A. Gruber

Принадлежит: International Business Machines Corp

The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.

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Номер записи: 57

01-11-2012 дата публикации

Semiconductor Device and Method of Making a Semiconductor Device

Номер: US20120273935A1

Автор: Beng Keh See, Chin Wei Ronnie Tan, Horst Theuss, Kathleen Ong, Kian Pin Queck, Stefan Martens, Tze Yang Hin, Ulrich Krumbein

Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

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Номер записи: 58

01-11-2012 дата публикации

Contact Metal for Hybridization and Related Methods

Номер: US20120273951A1

Автор: Aaron M. Ramirez, Andreas Hampp, Jonathan GETTY, Scott S. Miller

Принадлежит: Raytheon Co

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

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Номер записи: 59

01-11-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120276736A1

Автор: Naoki Idani

Принадлежит: Fujitsu Semiconductor Ltd

An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.

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Номер записи: 60

08-11-2012 дата публикации

Semiconductor device having groove-shaped via-hole

Номер: US20120280396A1

Автор: Kenichi Watanabe

Принадлежит: Fujitsu Semiconductor Ltd

The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66 a having a pattern bent at a right angle; and buried conductors 70, 72 a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66 a. A groove-shaped via-hole 66 a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

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Номер записи: 61

08-11-2012 дата публикации

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Номер: US20120282771A1

Автор: Heiko Wolf, Laurent Malaquin, Tobias Kraus

Принадлежит: International Business Machines Corp

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

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Номер записи: 62

15-11-2012 дата публикации

Semiconductor device

Номер: US20120286426A1

Автор: Ki Young Kim

Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a first structural body having first electrode pads; a second structural body disposed in a face-up type over the first structural body in such a way as to expose the first electrode pads, and having first connection members with at least two protrusions; and a third structural body disposed in a face-down type over the second structural body, and having second connection members with at least two protrusions, on a surface thereof facing the second structural body, wherein some of the protrusions of the second connection members are electrically connected with the exposed first electrode pads, and at least one of remaining protrusions of the second connection members is electrically connected with the first connection members.

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Номер записи: 63

29-11-2012 дата публикации

Power Semiconductor Module with Embedded Chip Package

Номер: US20120299150A1

Автор: Benjamin Tang, Frank Daeche, Kenneth Ostrom, Laura Carpenter

Принадлежит: INFINEON TECHNOLOGIES AG, Primarion Inc

A power semiconductor module includes a power semiconductor die, a metal substrate, a patterned metallization layer, a plurality of padless electrical connections, a plurality of vias and an inductor. The power semiconductor die has a top surface, an opposing bottom surface and a plurality of sides extending between the top and bottom surfaces. The metal substrate is attached to the bottom surface of the die. The patterned metallization layer is disposed above the top surface of the die. The plurality of padless electrical connections are at the top surface of the die and connect the patterned metallization layer to the die. The plurality of vias are disposed adjacent one or more of the sides of the die and electrically connected to the patterned metallization layer at a first end of the plurality of vias and to the metal substrate at a second end of the plurality of vias.

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Номер записи: 64

29-11-2012 дата публикации

Pad structure, circuit carrier and integrated circuit chip

Номер: US20120299192A1

Автор: Yeh-Chi Hsu, Yu-Kai Chen

Принадлежит: Via Technologies Inc

A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

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Номер записи: 65

29-11-2012 дата публикации

Method for manufacturing memory device

Номер: US20120302060A1

Автор: Hsien-Wen Liu, Ping Hsu, Yi-Nan Chen

Принадлежит: Nanya Technology Corp

The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.

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Номер записи: 66

06-12-2012 дата публикации

Estimation of presence of void in through silicon via (tsv) based on ultrasound scanning

Номер: US20120304773A1

Автор: Akihiro Horibe, Fumiaki Yamada

Принадлежит: International Business Machines Corp

A method and apparatus to detect a defect in a three-dimensional integrated structure by ultrasound scanning and to non-destructively detect the presence of a void that can occur in a process in a through silicon via (TSV) arranged in a board, such as a silicon wafer. To avoid measurement by ultrasound scanning over a board surface from being impeded by an object, such as a (solder) bump, scattering ultrasound, one or more TSVs belonging to a test element group (TEG) are selected from among a plurality of TSVs such that physical obstruction in the vicinity of the TEG.

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Номер записи: 67

20-12-2012 дата публикации

Enhanced Bump Pitch Scaling

Номер: US20120319269A1

Автор: Matthew Kaufmann, Mengzhi Pang

Принадлежит: Broadcom Corp

An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.

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Номер записи: 68

20-12-2012 дата публикации

Metal Bump Formation

Номер: US20120322255A1

Автор: Chih-Wei Lin, Chung-Shi Liu, Hsiu-Jen Lin, Ming-Da Cheng, Tzong-Hann Yang, Wen-Hsiung LU, Yi-Wen WU, Zheng-Yi Lim

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

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Номер записи: 69

27-12-2012 дата публикации

Low profile package and method

Номер: US20120326300A1

Автор: Anindya Poddar, Ashok S. Prabhu, Hau T. Nguyen, Tao Feng, Will K. Wong

Принадлежит: National Semiconductor Corp

In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

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Номер записи: 70

27-12-2012 дата публикации

Through wafer vias and method of making same

Номер: US20120329219A1

Автор: Alvin Jose Joseph, Anthony Kendall Stamper, Hanyi Ding

Принадлежит: International Business Machines Corp

A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

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Номер записи: 71

03-01-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130001274A1

Автор: Jumpei Konno, Kazunori Hasegawa, Michiaki Sugiyama, Nobuhiro Kinoshita, Takafumi Nishita

Принадлежит: Renesas Electronics Corp

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

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Номер записи: 72

03-01-2013 дата публикации

Bump-on-trace (bot) structures

Номер: US20130001778A1

Автор: Han-Ping Pu, Tin-Hao Kuo, Yu-feng Chen, Yuh Chern Shieh

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

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Номер записи: 73

03-01-2013 дата публикации

Semiconductor Constructions

Номер: US20130001788A1

Автор: Akram Ditali, Tianhong Zhang

Принадлежит: Micron Technology Inc

Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.

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Номер записи: 74

03-01-2013 дата публикации

Local interconnect having increased misalignment tolerance

Номер: US20130005138A1

Автор: Simon S. Chan

Принадлежит: SPANSION LLC

A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

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Номер записи: 75

10-01-2013 дата публикации

Semiconductor chip and flip-chip package comprising the same

Номер: US20130009286A1

Автор: Hwan-Sik Lim, Jong-ho Lee, Moon-Gi Cho, Sun-Hee Park, Young-Lyong KIM

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

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Номер записи: 76

17-01-2013 дата публикации

Semiconductor package including an external circuit element

Номер: US20130015557A1

Автор: Jie Xue, Jovica Savic, Li Li, Zhiping Yang

Принадлежит: Cisco Technology Inc

Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening.

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Номер записи: 77

17-01-2013 дата публикации

Solder Bump with Inner Core Pillar in Semiconductor Package

Номер: US20130015576A1

Автор: Yaojian Lin

Принадлежит: Stats Chippac Pte Ltd

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

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Номер записи: 78

24-01-2013 дата публикации

Method to form uniform silicide by selective implantation

Номер: US20130020705A1

Автор: Bin Yang, Cung D. Tran, Emre Alptekin, Viraj Y. Sardesai

Принадлежит: Globalfoundries Inc, International Business Machines Corp

Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

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Номер записи: 79

31-01-2013 дата публикации

TCE Compensation for Package Substrates for Reduced Die Warpage Assembly

Номер: US20130029457A1

Автор: Margaret Simmons-Matthews

Принадлежит: Texas Instruments Inc

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

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Номер записи: 80

31-01-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130029475A1

Автор: Takeo Tsukamoto

Принадлежит: Elpida Memory Inc

A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

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Номер записи: 81

07-02-2013 дата публикации

Integrated Inductor

Номер: US20130032923A1

Автор: Chen-Shien Chen, Ching-Wen Hsiao, Mirng-Ji Lii, Tsung-Ding Wang, Yen-Liang Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

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Номер записи: 82

14-02-2013 дата публикации

Through Silicon Via Layout

Номер: US20130040453A1

Автор: Chen-Shien Chen, Ming-Fa Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.

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Номер записи: 83

21-02-2013 дата публикации

Semiconductor Contact Barrier

Номер: US20130043546A1

Автор: Chen-Hua Yu, Chung-Shi Liu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

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Номер записи: 84

28-02-2013 дата публикации

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

Номер: US20130049205A1

Автор: David O'Sullivan, Klaus Reingruber, Thorsten Meyer

Принадлежит: Intel Mobile Communications GmbH

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

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Номер записи: 85

28-02-2013 дата публикации

Method for manufacturing a circuit device

Номер: US20130052796A1

Автор: Koichi Saito, Yasuyuki Yanase, Yoshio Okayama

Принадлежит: Sanyo Electric Co Ltd

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

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Номер записи: 86

07-03-2013 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20130056875A1

Автор: Hidetoshi Koyama, Yoshitsugu Yamamoto, Youichi Nogami

Принадлежит: Mitsubishi Electric Corp

A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.

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Номер записи: 87

14-03-2013 дата публикации

Semiconductor Devices and Methods of Manufacturing and Packaging Thereof

Номер: US20130062741A1

Автор: Chen-Shien Chen, Ming-Da Cheng, Sheng-Yu Wu, Tin-Hao Kuo

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

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Номер записи: 88

21-03-2013 дата публикации

Solder cap bump in semiconductor package and method of manufacturing the same

Номер: US20130069231A1

Автор: Geng-Shin Shen

Принадлежит: CHIPMOS TECHNOLOGIES INC

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

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Номер записи: 89

28-03-2013 дата публикации

Multi-Chip and Multi-Substrate Reconstitution Based Packaging

Номер: US20130075917A1

Автор: Edward Law, Kevin (Kunzhong) HU, Rezaur Rahman Khan

Принадлежит: Broadcom Corp

Embodiments for multi-chip and multi-substrate reconstitution based packaging are provided. Example packages are formed using substrates from a reconstitution. substrate panel or strip. The reconstitution substrate panel or strip may include known good substrates of same or different material types and/or same of different layer counts and sizes. As such, different combinations of reconstitution substrates and chips can be used within the same package, thereby allowing substrate customization according to semiconductor chip block(s) and types contained in the package.

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Номер записи: 90

28-03-2013 дата публикации

Integrated circuit packaging system with encapsulation and method of manufacture thereof

Номер: US20130075923A1

Автор: HeeJo Chi, Hyungmin Lee, YeongIm Park

Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.

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Номер записи: 91

28-03-2013 дата публикации

Integrated circuit and method of making

Номер: US20130075928A1

Автор: Abram Castro, Bernardo Gallegos

Принадлежит: Texas Instruments Inc

Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via.

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Номер записи: 92

28-03-2013 дата публикации

Method for improving the electromigration resistance in the copper interconnection process

Номер: US20130078798A1

Автор: Lin Chen, Pengfei Wang, Qingqing Sun, Wei Zhang, Wen Yang

Принадлежит: FUDAN UNIVERSITY

The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi 3 , CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.

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Номер записи: 93

04-04-2013 дата публикации

Zener Diode Structure and Process

Номер: US20130082330A1

Автор: WEI Xia, Xiangdong Chen

Принадлежит: Broadcom Corp

A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

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Номер записи: 94

11-04-2013 дата публикации

Power management applications of interconnect substrates

Номер: US20130087366A1

Автор: Anthony Stratakos, Chiteh Chiang, Ilija Jergovic, Kwang Hong Tan, Mihalis Michael

Принадлежит: Volterra Semiconductor LLC

Various applications of interconnect substrates in power management systems are described.

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Номер записи: 95

11-04-2013 дата публикации

Semiconductor device having multiple bump heights and multiple bump diameters

Номер: US20130087910A1

Автор: Ramlah Binte Abdul Razak

Принадлежит: Texas Instruments Inc

A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

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Номер записи: 96

11-04-2013 дата публикации

Semiconductor device, electronic device, and semiconductor device manufacturing method

Номер: US20130087912A1

Автор: Kozo Shimizu, Seiki Sakuyama, Toshiya Akamatsu

Принадлежит: Fujitsu Ltd

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

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Номер записи: 97

11-04-2013 дата публикации

FUSE STRUCTURE FOR HIGH INTEGRATED SEMICONDUCTOR DEVICE

Номер: US20130089976A1

Автор: KIM Hyung Kyu

Принадлежит: HYNIX SEMICONDUCTOR INC.

The present invention provides a technology capable of improving an operation reliability of a semiconductor device. Particularly, a fuse material which constitutes the copper can be prevented from migrating being locked in the recesses or the grooves after a blowing process. A semiconductor device includes an insulating layer including a concave-convex-shaped upper part; and a fuse formed on the insulating layer. 18-. (canceled)9. A method of manufacturing a semiconductor device , comprising:forming a plurality of trenches of a first type by etching a first insulating layer provided over a substrate;depositing a second insulating layer over the first insulating layer having the plurality of trenches of the first type;forming a trench of second type by etching the second insulating layer, the plurality of trenches of the first type being exposed; andforming a fuse by filling the trenches of the first type and the second type with conductive material.10. The method of manufacturing the semiconductor device according to claim 9 , further comprising depositing a third insulating layer on the inside of the recess and the first insulating layer before depositing the second insulating layer claim 9 , wherein an etching ratio of the third insulating layer is different from that of the first insulating layer.11. The method of manufacturing the semiconductor device according to claim 9 , wherein the plurality of recesses formed in parallel in a crossing-direction with a major axis of the trench.12. The method of manufacturing the semiconductor device according to claim 11 , wherein one recess near a blowing region of the fuse among the plurality of recesses has a wider width than the rest.13. The method of manufacturing the semiconductor device according to claim 11 , wherein a width of the plurality of recesses becomes wider as they close to a blowing region of the fuse.14. The method of manufacturing the semiconductor device according to claim 10 , wherein the plurality of ...

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Номер записи: 98

18-04-2013 дата публикации

Method for fabricating semiconductor device and semiconductor device

Номер: US20130093090A1

Автор: Atsuko Sakata, Hiroshi Toyoda, Kei Watanabe, Makoto Wada, Noriaki Matsunaga, Shinichi Nakao, Yumi Hayashi

Принадлежит: Atsuko Sakata, Hiroshi Toyoda, Kei Watanabe, Makoto Wada, Noriaki Matsunaga, Shinichi Nakao, Yumi Hayashi

A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

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Номер записи: 99

25-04-2013 дата публикации

Semiconductor package and stacked semiconductor package

Номер: US20130099359A1

Автор: Sung Min Kim

Принадлежит: SK hynix Inc

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

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Номер записи: 100