IMPATT-DIODE.

In an IMPATT diode consisting of a monocrystalline silicon substrate, on which is applied a heterostructure semiconductor layer sequence comprising an alternating arrangement of at least two different semiconductor layers forming one or more hetero-junctions, the novelty is that the generation zone contains at least one SiGe layer (2).

Silizium-Germanium-Heterobipolartransistor

SILIZIUMCARBID-HALBLEITERBAUELEMENT

Eine Mehrzahl von Graben-Gate-Elektroden ist von einer oberen Oberfläche ausgebildet, um eine Zwischentiefe eines SiC-Epitaxiesubstrats vom Typ n zu erreichen, das auf einer unteren Oberfläche ein Drain-Gebiet vom Typ n und auf einer oberen Oberfläche ein Source-Gebiet vom Typ n, die mit dem Source-Gebiet in Kontakt steht, enthält, um in einer Richtung entlang der oberen Oberfläche angeordnet zu werden. Hierbei stehen zumindest drei Seitenflächen von vier Seitenflächen einer jeden der Graben-Gate-Elektroden, die eine rechtwinkelige planare Form aufweisen, mit einer Body-Schicht vom Typ p unterhalb des Source-Gebiets in Kontakt. Außerdem erstrecken sich ein JFET-Gebiet in dem SiC-Epitaxiesubstrat und eine Source-Elektrode, die mit dem Source-Gebiet unmittelbar über dem JFET-Gebiet verbunden ist, entlang einer Richtung, in der die Mehrzahl der Graben-Gate-Elektroden angeordnet ist.

Bipolartransistor.

BIPOLARER HETEROUEBERGANGSTRANSISTOR MIT EINEM BASISBEREICH AUS GERMANIUM.

Heterojunction transistor comprises: a GaAs collector region (3) of first type; a Ge base layer (11) of second type; and an SiGe mixed crystal (I) emitter layer (12) of first type. Si content of (I) is pref. 10-40 mol. %; The Si content may be uniform, or graded from zero at the Ge layer interface. GaAs layer is formed on a high impurity concn. GaAs layer of first type (2) to which a collector electrode is contacted; a base electrode (a) contacts the Ge layer; and a high impurity concn. Ge layer of first type (13) is formed on the mixed crystal layer and an emitter contact attached.

Siliziumkarbid-Halbleitervorrichtung

Es wird eine Siliziumkarbid-Halbleitervorrichtung offenbart. Die Siliziumkarbid-Halbleitervorrichtung weist ein Substrat, eine Driftschicht, die einen ersten Leitfähigkeitstyp aufweist und sich auf einer ersten Oberfläche des Substrats befindet, und ein Halbleiterelement eines vertikalen Typs auf. Das Halbleiterelement des vertikalen Typs weist eine Störstellenschicht, die einen zweiten Leitfähigkeitstyp aufweist und sich in einem Oberflächenabschnitt der Driftschicht befindet, und einen Bereich eines ersten Leitfähigkeitstyps auf, der sich in der Driftschicht befindet, von der Störstellenschicht entfernt ist, näher als die Störstellenschicht an dem Substrat angeordnet ist und eine Störstellenkonzentration aufweist, die höher als die der Driftschicht ist.

Feldeffekttransistor und Verfahren zu dessen Herstellung

Verfahren zum Bilden von defektarmen gestreckt-relaxierten Schichten auf gitterfehlangepassten Substraten und entsprechende Halbleitervorrichtungsstrukturen und Vorrichtungen

Verfahren zum Bilden von gestreckt-relaxierten Halbleiterschichten werden gezeigt, in denen ein poröser Bereich in einer Oberfläche eines Halbleitersubstrats gebildet wird. Eine erste Halbleiterschicht, die mit dem Halbleitersubstrat gitterangepasst ist, wird auf dem porösen Bereich gebildet. Eine zweite Halbleiterschicht wird auf der ersten Halbleiterschicht gebildet, wobei die zweite Halbleiterschicht eine gestreckt gebildete Schicht ist. Die zweite Halbleiterschicht wird dann relaxiert.

Passivierung und Facettierung für FIN-Feldeffekttransistor

Es ist ein Fin-Feldeffekttransistor (FinFET) und ein Verfahren zum Ausbilden desselben vorgesehen. Der FinFET weist einen Grat auf, der eine oder mehrere Halbleiterschichten aufweist, die epitaktisch auf einem Substrat aufgezogen werden. Eine erste Passivierungsschicht wird über den Graten ausgebildet und Isolierbereiche werden zwischen den Graten ausgebildet. Ein oberer Abschnitt der Grate wird umgebildet und eine zweite Passivierungsschicht wird über dem umgebildeten Abschnitt ausgebildet. Dann kann eine Gatestruktur über den Graten ausgebildet werden und Source/Drain-Bereiche können ausgebildet werden.

SILICIUMCARBID-HALBLEITEREINHEIT, LEISTUNGSWANDLEREINHEIT UND HERSTELLUNGSVERFAHREN FÜR EINE SILICIUMCARBID-HALBLEITEREINHEIT

Eine Siliciumcarbid-Halbleitereinheit weist Folgendes auf: eine Drift-Schicht (20) vom n-Typ, die auf einem aus Siliciumcarbid bestehenden Halbleitersubstrat (10) ausgebildet ist, ein Muldenbereich (30) vom p-Typ, der in einem Oberflächenbereich der Drift-Schicht (20) ausgebildet ist, einen Source-Bereich (40) vom p-Typ, der in einem Oberflächenbereich des Muldenbereichs (30) ausgebildet ist, eine Gate-Isolierschicht (50), die in Kontakt mit dem Source-Bereich (40), dem Muldenbereich (30) und der Drift-Schicht (20) ausgebildet ist, sowie eine Gate-Elektrode (60), die auf der Gate-Isolierschicht (50) ausgebildet ist. In der Siliciumcarbid-Halbleitereinheit ist in einem Bereich, der von einer Grenzfläche zwischen dem Muldenbereich und der Gate-Isolierschicht aus in Richtung zu der Seite des Muldenbereichs hin eine vorgegebene Dicke aufweist, Sauerstoff enthalten.

SIC-Halbleiterbauelement

SiC-Halbleiterbauelement, aufweisend: ein SiC-Chip mit einer Hauptoberfläche, die eine erste Oberfläche, eine zweite Oberfläche, die in einer Dickenrichtung in einer ersten Tiefe außerhalb der ersten Oberfläche vertieft ist, und eine Verbindungsoberfläche, die die erste Oberfläche und die zweite Oberfläche verbindet, aufweist, und in der eine Mesa durch die erste Oberfläche, die zweite Oberfläche und die Verbindungsoberfläche definiert ist; eine Transistorstruktur, die an einem innenliegenden Abschnitt der ersten Oberfläche ausgebildet ist, wobei die Transistorstruktur eine Gate-Grabenstruktur, die eine zweite Tiefe aufweist, die geringer ist als die erste Tiefe, und eine Source-Grabenstruktur aufweist, die eine dritte Tiefe aufweist, die größer ist als die zweite Tiefe, und die in einer Richtung an die Gate-Grabenstruktur angrenzt; und eine Dummy-Struktur, die an einem Umfangsrandabschnitt der ersten Oberfläche ausgebildet ist, wobei die Dummy-Struktur eine Vielzahl von Dummy-Source-Grabenstrukturen ...

Verfahren zur Fertigung einer Siliciumcarbid-Halbleitervorrichtung

Verfahren zur Fertigung einer Siliciumcarbid-Halbleitervorrichtung, die folgenden Schritte aufweisend: Bilden einer Driftschicht (2) auf einem Substrat (1) eines ersten Leitfähigkeitstyps oder eines zweiten Leitfähigkeitstyps; Bilden einer Basisschicht (3) auf der Driftschicht (2) oder in einem Oberflächenabschnitt der Driftschicht (2); Bilden eines Grabens (6), um die Basisschicht (3) zu durchdringen und die Driftschicht (2) zu erreichen; Abrunden eines Teils eines Schulterecks und eines Teils eines Bodenecks des Grabens (6); Bedecken einer Innenwand des Grabens (6) mit einem organischen Film (21); Implantieren von Störstellen des ersten Leitfähigkeitstyps in einen Oberflächenabschnitt der Basisschicht (3); Bilden eines Source-Bereichs (4) durch eine Aktivierung der implantierten Störstellen im Oberflächenabschnitt der Basisschicht (3) nach dem Bilden des Grabens (6); Entfernen des organischen Films (21) nach dem Bilden des Source-Bereichs (4); Bilden eines Gate-Isolierfilms (7) auf der ...

SILIZIUMKARBIDHALBLEITERVORRICHTUNG UND HERSTELLUNGSVERFAHREN HIERFÜR

Eine SiC-Halbleitervorrichtung enthält ein Substrat (1), eine Drift-Schicht (2), einen Basisbereich (3), einen Source-Bereich (4), einen Graben (6), einen Gate-Oxidfilm (7), eine Gate-Elektrode (8), eine Source-Elektrode (9) und eine Drain-Elektrode (11). Das Substrat (1) hat als Hauptoberfläche eine Si-Fläche. Der Source-Bereich (4) hat die Si-Fläche. Der Graben (6) ist ausgehend von einer Oberfläche des Source-Bereichs (4) zu einem Abschnitt tiefer als der Basisbereich (3) ausgebildet, erstreckt sich längs in einer Richtung und hat einen Si-Flächen-Boden. Der Graben (6) hat eine umgekehrte sich verjüngende Form oder im Querschnitt eine Keilform mit einer kleineren Breite am Eintrittsabschnitt als am Boden zumindest in demjenigen Abschnitt, der in Kontakt mit dem Basisbereich (3) ist.

METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR-SIDEFLAT

HIGH IMPEDANCE SILICON CARBIDE AND PROCEDURE FOR ITS PRODUCTION

TRANSISTOR STRUCTURE.

SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS TEMPERATURE INSTABILITY (BTI) IN SILICON CARBIDE DEVICES

A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.

Semiconductor device.

Preparation method of silicon carbide wafers and silicon carbide wafers

REALIZATION Of a MICROELECTRONIC DEVICE INCLUDING/UNDERSTANDING OF the JUST GERMANIUM AND SILICON NANO-FILS ON a SAME SUBSTRATE

REALIZATION Of a MICROELECTRONIC DEVICE INCLUDING/UNDERSTANDING OF the JUST GERMANIUM AND SILICON NANO-FILS ON a SAME SUBSTRATE

L'invention concerne un procédé de réalisation d'un dispositif comprenant une structure avec des nano-fils à base d'un matériau semi-conducteur tel que du Si et une autre structure avec des nano-fils à base d'un autre matériau semi-conducteur tel que du SiGe et s'applique notamment à la réalisation de transistors.

위상 절연체의 임계 적층두께 도출방법

... 본 발명은 위상 절연체의 임계 적층두께 도출방법에 관한 것으로서, 더욱 상세하게는 V-VI족 위상 절연체의 열역학적 안정성과 전자 밀도 분포 그리고 전자 밴드 갭을 정량적으로 분석하고 이들을 이용하여 압력과 응력에 따른 위상 절연체의 적층두께를 도출하는 위상 절연체의 임계 적층두께 도출방법에 관한 것이다.이를 위해 본 발명은 (A) 위상 절연체들의 5배층 내부의 적층 구조에 따른 1차 모델들을 설정하는 단계: (B) 상기 (A) 단계에서 설정된 상기 1차 모델들을 콘-샴 방정식에 적용하여 열역학적 에너지를 계산하는 단계; (C) 상기 (B) 단계에서 계산된 열역학적 에너지를 기반으로 선정된 상기 1차 모델들을 활용하여 설정되며, 선정된 상기 1차 모델들에서 원자 층의 면간 미끄러짐을 통하여 설계가 가능한 전이 상태 모델들을 포함하는 2차 모델들을 설정하는 단계; 및 (D) 상기 (C) 단계에서 설정된 상기 2차 모델들의 열역학적 안정성 및 전자구조적 특성을 계산 및 비교 검증하여 위상 절연체 특성을 나타내기 위한 상기 2차 모델들의 임계 적층두께를 도출하는 단계; 를 포함한다.

NONVOLATILE MEMORY DEVICE CONTAINING A CARBON- OR NITROGEN-DOPED DIODE AND METHODS OF MAKING AND OPERATING THE SAME

A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration. COPYRIGHT KIPO & WIPO 2010 ...

Semiconductor device

Contact resistance between a SiC substrate and an electrode is decreased. When a silicide layer is analyzed by Auger Electron Spectroscopy (AES) sputter in a direction from a titanium layer side to a SiC substrate side, sputtering time corresponding to a depth profile of the silicide layer is defined as ts. In this case, a depth profile of the silicide layer from the titanium layer side in a range of sputtering time from 0.4ts to ts contains a region where titanium atoms determined by the AES sputter accounts for 5 at% or more of all atoms determined by the AES sputter.

INTEGRATED CIRCUIT HAVING DISLOCATION-FREE SUBSTRATE

An integrated circuit bulk substrate having a zinc blende or Wurtzite crystalline structre is alloyed with a material having atoms that replace atoms of the host semiconductor. The alloyed atoms have a bond length with the nearest neighboring host atoms that is less than the bond length of the host atoms. The number of bonded alloyed atoms is small compared to the number of host atoms so as not to substantially affect electronic conduction properties of the host material, but is large enough to virtually eliminate dislocations over a large surface area and volume of the host material on which active semiconductor devices are located.

Semiconductor Structure with Metal Gate and Method of Fabricating the Same

A metal gate process comprises the steps of providing a substrate, forming a dummy gate on said substrate, forming dummy spacers on at least one of the surrounding sidewalls of said dummy gate, forming a source and a drain respectively in said substrate at both sides of said dummy gate, performing a replacement metal gate process to replace said dummy gate with a metal gate, removing said dummy spacers, and forming low-K spacers to replace said dummy spacers.

Semiconductor device having asymmetric active region and method of forming the same

Provided are a semiconductor device and a method of forming the same. The semiconductor device includes an active region defined by an isolation layer. A source region portion, a drain region portion and a channel region are located in the active region. The channel region includes a first portion located close to the source region portion and a second portion having a higher threshold voltage than the first portion.

Method for reducing loss of silicon cap layer over SiGe source/drain in a CMOS device

A method for forming a semiconductor device includes providing a semiconductor substrate including a PMOS region and an NMOS region. A spacer material layer is deposited. Then, a first photo masking and etch process is used to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region. A sacrificial surface layer is formed. Next, a second photo masking and etch process is used to form second sidewall spacers on the sidewalls of the gate structures in the PMOS region. After the second photoresist layer is removed, with the sacrificial layer masking the NMOS region, stress layers are formed in source/drain regions in the PMOS region, and a cover layer is formed on the stress layers. The method further includes removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.

Transparent solid-state structure for diagnostics of fluorescently labeled biomolecules

Fluorescence modification, meaning either fluorescence enhancement or fluorescence diminishment, is obtained in a transparent layer structure comprised of a substrate, a dielectric layer and a fluorophore-labeled biomolecule layer. A metal particle layer is positioned in the layer structure a distance of 200-500 nm from the fluorophore-labeled biomolecule layer. Separation distances between 200 and 500 nanometers can be used to enhance or diminish fluorescence. All of the layers may be made transparent so that microscopic viewing of the fluorescence is possible from either side of the layer structure.

VERTICAL TRANSISTOR FLOATING BODY ONE TRANSISTOR DRAM MEMORY CELL

A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1T DRAM that has a substrate with a horizontal substrate surface, a source disposed on the horizontal substrate surface, a drain, and a channel. The channel has a channel top, a channel bottom, a first channel side, a second channel side, and two channel ends. The channel top is connected to the drain. The channel bottom is connected to the source. The channel is vertical and perpendicular to the substrate surface. A first gate stack interfaces with the first channel side and a second gate stack interfaces with the second channel side. A single external gate connection electrically connects the first gate stack and the second gate stack A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion. The first gate stack is made of a first high-k dielectric layer and a first gate metal layer. The ...

SELF-ALIGNED FINFET FORMATION

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

METHOD FOR DEPINNING THE FERMI LEVEL OF A SEMICONDUCTOR AT AN ELECTRICAL JUNCTION AND DEVICES INCORPORATING SUCH JUNCTIONS

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Semiconductor device and fabrication method

Semiconductor devices and fabrication methods are provided. A semiconductor substrate is provided having dummy gate structures formed thereon. A stress layer is formed in the semiconductor substrate between adjacent dummy gate structures. A first dielectric layer is formed on the semiconductor substrate, the stress layers, and the sidewall spacers of the dummy gate structures, exposing dummy gate electrode layers. Gate structures are formed in the dielectric layer to replace the dummy gate structures. The gate structures include functional gate structures and at least one non-functional gate structure. The at least one non-functional gate structure is removed to form at least one second opening in the first dielectric layer. At least one third opening is formed in the semiconductor substrate at a bottom of the at least one second opening. A second dielectric layer is formed in the at least one second opening and the at least one third opening.

Semiconductor structures including bodies of semiconductor material and methods of forming same

Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

SEMICONDUCTOR DEVICE AND ELECTRIC APPARATUS

The present invention provides a semiconductor device and an electric apparatus each of which can realize both high-speed switching operation and energy loss reduction and excels in resistance to current concentration based on a counter electromotive voltage generated by, for example, an inductance load of the electric apparatus. A semiconductor device (100) of the present invention includes: a semiconductor layer (3) made of a first conductivity type wide band-gap semiconductor; a transistor cell (101T) in which a vertical field effect transistor (102) is formed, the vertical field effect transistor (102) causing a charge carrier to move in a thickness direction of the semiconductor layer (3); and a diode cell (101S) in which a schottky diode (103) is formed, the schottky diode (103) being formed such that a schottky electrode (9) forms a schottky junction with the semiconductor layer (3), wherein the semiconductor layer 3 is divided into a plurality of square subregions (101T and 101S ...

Digital alloy FinFET co-integrated with passive resistor with good temperature coefficient

A method for integrating fin field effect transistors (FinFETs) and resistors on a common substrate is provided. By employing a digital alloy as a channel material for each FinFET and as a resistor body for each resistor, FinFETs with improved charge carrier mobility, and resistors with good temperature coefficient of resistance are obtained.

P-FET with graded silicon-germanium channel

A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile.

SUPERLATTICE MATERIALS AND APPLICATIONS

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF EVALUATING SEMICONDUCTOR DEVICE

A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

Silicon carbide semiconductor device and method of manufacturing the same

An SiC semiconductor device includes a substrate, a drift layer disposed on a first surface of the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a trench penetrating the source region and the base region to the drift layer, a gate insulating layer disposed on a surface of the trench, a gate electrode disposed on a surface of the gate insulating layer, a first electrode electrically coupled with the source region and the base region, a second electrode disposed on the second surface of the substrate, and a second conductivity-type layer disposed at a portion of the base region located under the source region. The second conductivity-type layer has the second conductivity type and has an impurity concentration higher than the base region.

Solder bump placement for thermal management in flip chip amplifiers

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.

Porous silicon relaxation medium for dislocation free CMOS devices

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

PERFORMANCE OPTIMIZED GATE STRUCTURES

A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.

Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same

A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer of metal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

STACKED SHORT AND LONG CHANNEL FINFETS

An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

SEMICONDUCTOR STRUCTURE HAVING FINFET ULTRA THIN BODY AND METHODS OF FABRICATION THEREOF

In one aspect there is set forth herein a semiconductor structure having fins extending upwardly from an ultrathin body (UTB). In one embodiment a multilayer structure can be disposed on a wafer and can be used to pattern voids extending from a UTB layer of the wafer. Selected material can be formed in the voids to define fins extending upward from the UTB layer. In one embodiment silicon (Si) can be grown within the voids to define the fins. In one embodiment, germanium based material can be grown within the voids to define the fins.

SEMICONDUCTOR DEVICE

A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.

FORMATION OF PURE SILICON OXIDE INTERFACIAL LAYER ON SILICON-GERMANIUM CHANNEL FIELD EFFECT TRANSISTOR DEVICE

Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate. A mask is formed on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer. The unmasked portion of the alloy semiconductor material layer not covered by the mask is irradiated with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer. The surface region surrounds the internal region.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.

Uniform height tall fins with varying silicon germanium concentrations

A method of making a semiconductor device includes forming a first fin in a first semiconducting material layer disposed over a substrate, the first semiconducting material layer comprising an element in a first concentration; and forming a second fin in a second semiconducting material layer disposed over the substrate and adjacent to the first semiconducting material layer, the second semiconducting material layer comprising the element in a second concentration; wherein the first concentration is different than the second concentration.

SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER

A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

SEMICONDUCTOR DEVICE HAVING FIN AND DUAL LINER

A semiconductor device is provided as follows. A first fin is formed on a first region of a substrate, extending in a first direction. A second fin is formed on a second region of the substrate, extending in a second direction. A first dual liner is formed on a lateral surface of the first fin. The first dual liner includes a first liner and a second liner. The first liner is interposed between the second liner and the lateral surface of the first fin. A second dual liner is formed on a lateral surface of the second fin. The second dual liner includes a third liner and a fourth liner. The third liner is interposed between the fourth liner and the lateral surface of the second fin. An epitaxial layer surrounds a top portion of the second fin. The first liner and the third liner have different thicknesses.

Dual Silicide Structure and Methods Thereof

A semiconductor structure is received that has a first and second fins. A first epitaxial feature is formed on the first fin and has a first type dopant. A first capping layer is formed over the first epitaxial feature. A second epitaxial feature is formed on the second fin and has a second type dopant different from the first type dopant. A first metal is deposited on the second epitaxial feature and on the first capping layer. A first silicide layer is formed from the first metal and the second epitaxial feature, and a second capping layer is formed from the first metal and the first capping layer. The second capping layer is selectively removed. A second metal is deposited on the first epitaxial feature and over the second epitaxial feature. A second silicide layer is formed from the second metal and the first epitaxial feature.

Method for improving transistor performance through reducing the salicide interface resistance

An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

MEMBRANE HAVING MEANS FOR STATE MONITORING

The invention relates to a membrane. Partly permeable membranes often have holes or perforations having a specific diameter to allow substances having a smaller particle diameter to pass through, but to hold back substances having a larger particle diameter. Such membranes are subject to wear primarily at the holes, i.e. cracks form which grow through the membrane proceeding from a hole. Particularly in the case of micromechanical membranes having holes having a small diameter in the range of 1 m or less, it is very difficult to detect the state of the membrane, in particular whether the latter has cracks. Membranes having cracks can then undesirably allow passage even of those particles which should actually be held back. In medical or hygienic applications, the function can then be impaired.

POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

Heterogeneously integrated semiconductor device and manufacturing method thereof

A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.

COMPLEMENTARILY STRAINED FINFET STRUCTURE

A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.

Semiconductor device and complementary semiconductor device

A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer. A channel direction connecting the p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.

Semiconductor device and inverter circuit

A semiconductor device according to embodiments includes a p-type SiC layer having a first plane, a gate electrode, and a gate insulating layer provided between the first plane of the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, and a first region. The second layer has a higher oxygen density than the first layer. The first region is provided between the first layer and the second layer and includes a first element, the first element being at least one element in the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth).

High dose implantation for ultrathin semiconductor-on-insulator substrates

Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

SEMICONDUCTOR DEVICE STRUCTURE WITH NANOSTRUCTURES

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The semiconductor device structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The semiconductor device structure further includes a metal gate stack over the nanostructures, and the nanostructures are separated from each other by portions of the metal gate stack. In addition, the semiconductor device structure includes a dielectric layer surrounding the metal gate stack, the nanostructures, and the fin structure.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

Power reduction in finFET structures

The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

Heterojunction bipolar transistor and method for fabricating the same

A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

Semiconductor device manufacturing method

Bipolar transistor

Device having strain induced region

METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a method for producing a semiconductor device, and the semiconductor device in which high strain relaxation rate is attained even in a strained SiGe film having thickness equal to or thinner than critical film thickness and high Ge concentration formed on a semiconductor substrate, through dislocation density is reduced, undulation of a second SiGe film surface formed on it is inhibited and smoothness can be enhanced. SOLUTION: The method for producing the semiconductor device includes following steps: (a) a step of forming a first SiGe film thickness in thickness equal to or thinner than the critical film thickness on the substrate whose surface is composed of silicon, (b) a step of forming a first cap semiconductor film on the first SiGe film, (c) a step of subjecting the obtained substrate to ion implantation, (d) a step of annealing the substrate having the first cap semiconductor film on it's surface, (e) a step of forming second SiGe film on the first ...

PROCESS FOR PRODUCING SEMICONDUCTOR SUBSTRATE

PROBLEM TO BE SOLVED: To provide a process for producing a semiconductor substrate in which a strained Si layer can be formed on a silicon substrate while suppressing threading dislocation as much as possible and eliminating an SiGe layer as much as possible and production efficiency can be enhanced. SOLUTION: The process for producing a semiconductor substrate comprises a step for preparing a first material, where a silicon-germanium porous layer formed by anodizing a silicon-germanium substrate and a strained silicon layer are formed sequentially, on the silicon-germanium substrate, a step for preparing a second material where a silicon oxide film layer is formed on a silicon-germanium substrate, a step for pasting the strained silicon layer side of the first material and the silicon oxide film layer side of the second material, and a step for obtaining a silicon substrate where the silicon oxide film layer and the strained silicon layer are formed sequentially by separating and removing ...

VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS

Verfahren zum Herstellen eines Halbleiterbauelements (100), umfassend: - Bilden einer Graphenschicht (30) an einer ersten Seite (11, 21) eines Siliciumcarbidsubstrats (10, 20), das zumindest in der Nähe der ersten Seite (11, 21) eine erste Defektdichte von höchstens 5*102/cm2 aufweist; - Anbringen einer Akzeptorschicht (40) an der Graphenschicht (30) zum Bilden eines Waferstapels (124), wobei die Akzeptorschicht (40) Siliciumcarbid mit einer zweiten Defektdichte aufweist, die höher ist als die erste Defektdichte; - Spalten des Waferstapels (124) entlang einer Spaltfläche (23) in dem Siliciumcarbidsubstrat (10, 20) zum Bilden eines Bauelementwafers (432), der die Graphenschicht (30) und eine an der Graphenschicht (30) angeordnete Siliciumcarbidspaltschicht (20') aufweist; - Bilden einer epitaktischen Siliziumcarbidschicht (50), die sich zu einer Oberseite (52) des Bauelementwafers (432) erstreckt, auf der Siliziumcarbidspaltschicht (20'); - Weiterbearbeiten des Bauelementwafers (124) an ...

EPITAXIALER SiC-WAFER

Epitaxialer SiC-Wafer (10), welcher Folgendes aufweist: ein einkristallines SiC-Substrat (1), dessen Hauptoberfläche einen Versatzwinkel von 0,4° bis 5° in Bezug auf die (0001)-Ebene aufweist, und eine Epitaxieschicht (2), die auf dem einkristallinen SiC-Substrat (1) vorgesehen ist, wobei die Epitaxieschicht (2) eine Basalebenenversetzungsdichte von 0,1 Teilen/cm2 oder weniger, wobei es sich um die Dichte der sich von dem einkristallinen SiC-Substrat (1) zu einer äußeren Oberfläche erstreckenden Basalebenenversetzungen handelt, und eine Dichte intrinsischer 3C-Dreiecksfehler von 0,1 Teilen/cm2 oder weniger aufweist, und wobei zur Bestimmung der Dichte intrinsischer 3C-Dreiecksfehler der epitaxiale SiC-Wafer (10) mit Ultraviolettlicht bestrahlt wird und emittiertes Licht mit einer Wellenlänge von 540 nm bis 640 nm als Photolumineszenzlicht erfasst wird.

Feldeffekttransistor und Verfahren zu dessen Herstellung

Halbleitergerät und Verfahren zu seiner Herstellung

Halbleitergerät (100, 200) mit: einem Siliziumcarbidsubstrat (10, 210) eines 4H oder 6H Polytyps; und einer Elektrode (6, 206), die auf einer Oberfläche des Siliziumcarbidsubstrats (10, 210) gebildet ist; wobei eine 3C Polytypschicht (12, 212) in dem Siliziumcarbidsubstrat (10, 210) so gebildet ist, dass sie sich schräg von der Oberfläche des Siliziumcarbidsubstrats (10, 210) in der Tiefenrichtung des Siliziumcarbidsubstrats (10, 210) erstreckt, und ein Endabschnitt der 3C Polytypschicht (12, 212) an der Oberflache des Siliziumcarbidsubstrats (10, 210) in Kontakt mit der Elektrode (6, 206) steht.

Methode zur Herstellung von vertikalen Transistoren

Passivierung und Facettierung für FIN-Feldeffekttransistor

Fin-Feldeffekttransistor (FinFET) (200), der Folgendes umfasst:ein Substrat (202);eine Gratstruktur (220), die sich von dem Substrat (202) erhebt, wobei die Gratstruktur (220) eine erste Halbleiterschicht (2201) mit einer ersten Gitterkonstante, eine zweite Halbleiterschicht (220m) mit einer zweiten Gitterkonstante auf der ersten Halbleiterschicht (220l) und eine dritte Halbleiterschicht (220u) mit einer dritten Gitterkonstante auf der zweiten Halbleiterschicht (220m) umfasst, wobei die dritte Gitterkonstante größer als die zweite Gitterkonstante ist, die zwischen der ersten und der dritten Gitterkonstante liegt;einen Isolierbereich (212), der angrenzend an gegenüberliegende Seitenwände der Gratstruktur (220) liegt, wobei die Gratstruktur (220) einen oberen Abschnitt aufweist,der sich über den Isolierbereich (212) erstreckt und wobei der obere Abschnitt geneigte Seitenwände aufweist;eine erste Passivierungsschicht (230), die zwischen der Gratstruktur (220) und dem Isolierbereich (212) liegt ...

SiC-HALBLEITERBAUTEIL

Ein SiC-Halbleiterbauteil weist einen SiC-Chip mit einer ersten Hauptfläche auf einer Seite und einer zweiten Hauptfläche auf einer anderen Seite auf, eine erste Hauptflächenelektrode, die eine erste Al-Schicht aufweist und die auf der ersten Hauptfläche gebildet ist, eine Pad-Elektrode, die auf der ersten Hauptflächenelektrode gebildet ist und mit einem Anschlussdraht zu verbinden ist, und eine zweite Hauptflächenelektrode, die eine zweite Al-Schicht enthält und die auf der zweiten Hauptfläche gebildet ist.

Siliciumcarbid-Halbleitervorrichtung

In einer Siliciumcarbid-Halbleitervorrichtung weisen mehrere Gräben (7) eine Längsrichtung in einer Richtung auf und sind die mehreren Gräben (7) in einem Streifenmuster angeordnet. Jeder der Gräben (, die sich in der Längsrichtung erstrecken. Die erste Seitenwand liegt in einem ersten spitzen Winkel zu einer von einer (11-20)-Ebene und einer (1-100)-Ebene, und die zweite Seitenwand liegt in einem zweiten spitzen Winkel zu der einen von der (11-20)-Ebene und der (1-100)-Ebene, wobei der erste spitze Winkel kleiner als der zweite spitze Winkel ist. Ein Bereich (5) ersten Leitfähigkeitstyps ist in Kontakt mit nur der ersten Seitenwand der ersten und der zweiten Seitenwand von jedem der Gräben (7), und ein Strompfad wird nur auf der ersten Seitenwand der ersten und der zweiten Seitenwand gebildet.

Siliciumcarbid-Halbleitervorrichtung

Siliciumcarbid-Halbleitervorrichtung mit einem vertikalen Halbleiterelement mit einer Trench-Gate-Struktur, aufweisend: – ein Siliciumcarbid-Halbleitersubstrat (1, 2) mit einer Schicht (1) ersten oder zweiten Leitfähigkeitstyps und einer Driftschicht (2) auf der Schicht (1) ersten oder zweiten Leitfähigkeitstyps, wobei die Driftschicht (2) den ersten Leitfähigkeitstyp aufweist und das Siliciumcarbid-Halbleitersubstrat (1, 2) eine Hauptoberfläche mit einer Offset-Richtung aufweist; – einen Graben (6), der auf einer Oberfläche der Driftschicht (2) angeordnet ist und eine Längsrichtung aufweist; und – eine Gate-Elektrode (9), die über einen Gate-Isolierfilm (8) in dem Graben (6) angeordnet ist, wobei – eine Seitenwand des Grabens (6) eine Kanalbildungsoberfläche bildet, – die vertikale Halbleitervorrichtung dazu ausgelegt ist, einen Strom in Übereinstimmung mit einer Gate-Spannung, die an die Gate-Elektrode (9) gelegt wird, entlang der Kanalbildungsoberfläche des Grabens (6) fließen zu lassen ...

Verfahren zum Herstellen einer Halbleitervorrichtung und für das Verfahren verwendete Halbleiterherstellungsvorrichtung

Verfahren zum Herstellen einer Halbleitervorrichtung, das Folgendes umfasst:thermisches Oxidieren einer Oberfläche einer zu verarbeitenden Basis (200) aus Siliziumcarbid als Körpermaterial, um einen Siliziumdioxidfilm zu bilden, durch Zuführen von Gas, das ein Oxidationsmittel enthält, zu der Oberfläche der zu verarbeitenden Basis (200); undnach dem Bilden des Siliziumdioxidfilms, Absenken einer Temperatur der zu verarbeitenden Basis (200), wobei der Siliziumdioxidfilm auf eine Größe von 0,1 nm oder weniger gezüchtet wird, während die Temperatur der zu verarbeitenden Basis (200) abgesenkt wird, wobei das Absenken der Temperatur das Abwerfen der zu verarbeitenden Basis (200) in ein Flüssigkeitsbad umfasst, in das Flüssigkeit gegossen wird, um die Temperatur der zu verarbeitenden Basis (200) zu senken.

Verfahren zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung

Verfahren zum Herstellen einer Siliziumkarbid-Halbleitervorrichtung, wobei das Verfahren folgende Schritte aufweist: – einen ersten Wachstumsschritt, in dem man eine erste Epitaxieschicht (2, 10, 12) auf einer Hauptfläche eines Siliziumkarbid-Halbleitersubstrats (1) aufwachsen lässt, welches einen Abweichungswinkel aufweist; und – einen zweiten Wachstumsschritt, in dem man eine zweite Epitaxieschicht (3, 11, 13) auf und in Kontakt mit einer oberen Oberfläche der ersten Epitaxieschicht (2, 10, 12) bei einer niedrigeren Wachstumstemperatur als einer Wachstumstemperatur für die erste Epitaxieschicht (2, 10, 12) aufwachsen lässt, wobei beide Wachstumsschritte mit einer Dampfphasenepitaxie-Methode durchgeführt werden, und wobei eine Differenz zwischen der Wachstumstemperatur für die erste Epitaxieschicht (2, 10, 12) und der Wachstumstemperatur für die zweite Epitaxieschicht (3, 11, 13) mindestens 50 K und höchstens 150 K beträgt.

P-FET mit einem verspannten Nanodraht-Kanal und eingebetteten SiGe-Source- und Drain-Stressoren und Verfahren

Verfahren zum Herstellen eines Feldeffekttransistors (FET), das die folgenden Schritte umfasst:Bereitstellen eines dotierten Substrates mit einem darauf befindlichen Dielektrikum, wobei das dotierte Substrat ein p++-dotiertes Siliciumsubstrat umfasst;Platzieren mindestens eines Silicium-Nanodrahtes auf dem Dielektrikum;Abdecken eines oder mehrerer Teile des Nanodrahtes mit einer Maske, wobei andere Teile des Nanodrahtes freiliegend bleiben;Aufwachsen epitaktischen Germaniums auf den freiliegenden Teilen des Nanodrahtes; undEindiffundieren des epitaktischen Germaniums in das Si im Nanodraht, um im Nanodraht eingebettete Silicium-Germanium-Zonen zu bilden, die Druckspannung in den Nanodraht einbringen,wobei das dotierte Substrat als Gate des FET dient, die durch Maske abgedeckten Teile des Nanodrahtes als Kanäle des FET dienen und die eingebetteten Silicium-Germanium-Zonen als Source- und Drain-Zonen des FET dienen.

Verfahren zum Herstellen eines FET mit verspanntem Kanal mit Source/Drain-Puffern und FET

Verfahren zum Bilden eines Feldeffekttransistors (FET) mit verspanntem Kanal mit Source/Drain-Puffern, wobei das Verfahren aufweist: Ätzen von Hohlräumen in einem Substrat auf beiden Seiten eines Gate-Stapels, der sich auf dem Substrat befindet; Abscheiden von Source/Drain-Puffermaterial in den Hohlräumen; Ätzen des Source/Drain-Puffermaterials, um vertikale Source/Drain-Puffer neben einem Kanalbereich des FET zu bilden; und Abscheiden von Source/Drain-Stressormaterial in den Hohlräumen neben und über den vertikalen Source/Drain-Puffern.

Semiconductor circuit structure having dislocation-free substrate

An integrated circuit bulk substrate having a zinc blende or Wurtzite crystalline structure is alloyed with a material having atoms that replace atoms of the host semiconductor. The alloyed atoms have a bond length with the nearest neighboring host atoms that is less than the bond length of the host atoms. The number of bonded alloyed atoms is small compared to the number of host atoms so as not to substantially affect electronic conduction properties of the host material, but is large enough to virtually eliminate dislocations over a large surface area and volume of the host material on which active semiconductor devices are located.

INTEGRATED CIRCUIT HAVING DISLOCATION-FREE SUBSTRATE

An integrated circuit bulk substrate having a zinc blende or Wurtzite crystalline structure is alloyed with a material having atoms that replace atoms of the host semiconductor. The alloyed atoms have a bond length with the nearest neighboring host atoms that is less than the bond length of the host atoms. The number of bonded alloyed atoms is small compared to the number of host atoms so as not to substantially affect electronic conduction properties of the host material, but is large enough to virtually eliminate dislocations over a large surface area and volume of the host material on which active semiconductor devices are located.

HALFISOLATING SILICON CARBIDE WITHOUT VANADIUM DOMINANCE

SILICON GERMANIUM HETERO BIPOLAR TRANSISTOR

GE CHANNEL HETEROSTRUCTURE WITH HIGH SPEED FOR FIELD EFFECT ARRANGEMENTS

DUENNSCHICHTTRANSISTOR.

MAKING AMORPHOUS SEMICONDUCTOR ALLOYS USING MICROWAVE ENERGY

High voltage, high temperature capacitor structures and methods of fabricating same

SILICON-GERMANIUM-CARBON COMPOSITIONS AND PROCESSES THEREOF

Thin film transistor and organic EL display apparatus using the same

A thin film transistor and an organic EL display device using the thin film transistor are provided. A semiconductor layer (4) comprising Si, Ge is applied in the thin film transistor, Ge concentration of the semiconductor layer (4) is high at the side of an insulating substrate (1), crystallization orientation of the semiconductor layer (4) is random at a region having a distance of 20 nm from the side of the insulating substrate (1) and is displayed (111), (110) or (100) preferably-oriented at the side of film surface of the semiconductor layer (4).

High-speed composite p channel si/siGe heterogeneous structure of field-effect devices

SEMICONDUCTOR DEVICE

semiconductor heterostructure, method for forming the semiconductor heterostructure and strained silicon on insulataor wafer(sSOI) comprising the semiconductor heterostructure

METHOD FOR IMPROVING INVERSION LAYER MOBILITY IN A SILICON CARBIDE MOSFET

A method of manufacturing a semiconductor device based on a SiC substrate (12), comprising the steps of forming (201) an oxide layer (14) on a Si-terminated face of the SiC substrate (12) at an oxidation rate sufficiently high to achieve a near interface trap density below 5 x 1011 cm-2; and annealing (202) the oxidized SiC substrate in a hydrogen- containing environment, in order to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET (10) having improved inversion layer mobility and reduced threshold voltage. It has been found by the present inventors that the density of DTs increases while the density of NITs decreases when the Si- face of the SiC substrate is subject to rapid oxidation. According to the present invention, the deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.