ЛОГИЧЕСКИЙ ВЕНТИЛЬ

Изобретение относится к электронике и предназначено для использования в интегральных логических устройствах на комплементарных униполярных полевых транзисторах структуры металл-окисел-полупроводник (МОП) с индуцированными каналами p и n типов проводимости и биполярных транзисторах n-p-n и p-n-p структур. Техническим результатом является повышение надежности за счет снижения паразитных емкостей базовых узлов. Логический вентиль содержит МОП-ключи p и n типов проводимости, истоковые выводы которых соответственно подключены к шинам положительного и отрицательного полюсов напряжения питания, эмиттерные повторители на биполярных транзисторах n-p-n и p-n-p структур, коллекторы которых соответственно подключены к шинам положительного и отрицательного полюсов напряжения питания, а эмиттеры соединены с выходом логического вентиля, МОП-ключи p и n типов проводимости составляют более двух комплементарных пар, в каждой из которых стоковые выводы МОП-ключей соединены и подключены к базе биполярного ...

Мультиплексор

Использование при создании автоматических линий, в станках с ЧПУ, а также для получения импульсов различной длительности в приборостроении и в лазерной технике . Сущность изобретения: мультиплексор содержит дешифратор, имеющий адресные входы S вход разрешения Е, схемы СОВПАДЕНИЯ с информационными входами J и комплементарными выходами Y и Y, а также блок управления, имеющий два управляющих входа и N рабочих входов и выходов, каждый рабочий вход блока управления подключен к соответствующему выходу дешифратора , а каждый рабочий выход подключен к соответствующему входу-схемы СОВПАДЕНИЯ, блок управления состоит из N каскадов, каждый из которых включает последовательно соединенные первый элемент ИЛИ, элемент И и второй элемент ИЛИ. причем первые входы первого и второго элементов ИЛИ каждого каскада соединены между собой и образуют N рабочих входов блока управления, второй вход первого элемента ИЛИ каждого каскада соединен с выходом первого элемента ИЛИ последующего каскада, второй вход первого ...

Logikschaltungen, die ausgelegt sind, um das Verhalten zu verbessern

Torschaltung mit Feldeffekt- und Bipolartransistoren.

Ratiod BiCMOS logic circuits

In a logic circuit 100, an optimum ratio is provided between the widths of the MOS pull-up 106 and pull-down 104 devices, with one or more bipolar devices 102 connected to the output 112. This optimum ratio substantially minimises the propagation delay of the circuit. An empirically derived ratio may be applied to circuits having different fanouts, different total MOS size, and different emitter lengths, but will remain substantially optimal. ...

Memory repair multiplexer with reduced propagation delay

The output 34 of a memory repair multiplexer 30 is fed directly to an output terminal 16a. After a short delay the output is buffered by enabling a non-inverting driver 36 coupled at its input and output to the multiplexer output node. The direct connection of the multiplexer output 34 to the output terminal 16a avoids the propagation delay of the driver 36. A data latch may be interposed between the multiplexer output 34 and the input of the driver 36 (figure 4), so that the circuit may be used in EDO mode SIMMs.

Logic circuits scaled to enhance performance

COMPLEMENTARY FIELD-EFFECT TRANSISTOR LOGIC WITH HIGH SPEED.

DYNAMIC ECL CIRCUIT TO SCOLDED FROM LOADS WITH IMPORTANT CAPACITY.

LEVEL SLIDEGATE VALVE FOR EXTREME LOW SUPPLY VOLTAGES

BUS DRIVER CIRCUIT FOR THE TEILENTLADUNG OF A BUS FOR THE DECREASE OF THE COUPLING BETWEEN LINES

DIGITAL INTEGRATED CIRCUIT COMPRISING COMPLEMENTARY FIELD EFFECT TRANSISTORS

... "Digital integrated circuit comprising complementary field effect transistors." Digital integrated C-MOS circuit in which two crosscoupled P-MOS transistors are connected via two separation transistors (N-MOS) to two complementary switching N-MOS transistor networks. The gate electrodes of the separation transistors are connected to a reference voltage source. The switching speed of the C-MOS circuit is increased in that a) the voltage sweep across the logic network is reduced; b) the P-MOS transistor, which is connected via a separation transistor to a junction of the logic network to be charged, is slightly conducting and so is "ready" to charge this junction, and c) the separation transistor forms between the fully conducting P-MOS transistor and the junction to be discharged of the second logic network a high impedance which prevents the (still conducting) P-MOS transistor from charging the junction.

ЛОГИЧЕСКИЙ ЭЛЕМЕНТ

Изобретение относится к импульсной технике. Логический элемент содержит первый p-n-p транзистор, первый и второй диоды, первый и второй резисторы, первую и вторую входные шины, выходную и общую шины, эмиттер первого транзистора, соединенной с общей шиной, а баз а с помощью первого резистора подключен а к первой входной шине.

Устройство для вычисления бисимметрических булевых функций

Устройство для вычисления бисимметрических булевых функций, содержащее два элемента сложения по модулю два, i-й вход первого из которых (i = 1,2) соединен с i-м информационным входом устройства первой группы, i-й вход второго элемента сложения по модулю два соединен с i-м информационным входом устройства второй группы, отличающееся тем, что содержит два элемента ИЛИ-НЕ и тринадцать элементов И-НЕ, первый вход j-го из которых (j = ) соединен с j-м настроечным входом устройства, выход k-го элемента И-НЕ (k = 1,2,3) соединен с k-м входом десятого элемента И-НЕ, четвертый вход которого соединен с выходом первого элемента ИЛИ-НЕ, выход (k + 3)-го элемента И-НЕ соединен с k-м входом одиннадцатого элемента И-НЕ, четвертый вход которого соединен с выходом первого элемента сложения по модулю два, выход (k + 6)-го элемента И-НЕ соединен с k-м входом двенадцатого элемента И-НЕ, (i + 3)-й вход которого соединен с i-м информационным входом устройства первой группы и i-м входом первого элемента ИЛИ-НЕ ...

Level shifting circuit

HIGH SPEED SATURATION MODE SWITCHING CIRCUIT FOR A CAPACITIVE LOAD

Logical circuit

COMPRISING DECODER OF TRANSISTORS MOS

Bipolar transistor integrated circuit with injection logic - contains FET normally non-conducting and junctions integrated with bipolars (CS 31.8.78)

ELECTRONIC ASSEMBLY Of EXCITATION HAS FIELD-EFFECT TRANSISTORS COMPLEMENTARY

LOGIC ELEMENT

CIRCUIT HAS FIELD-EFFECT TRANSISTORS USING a POTENTIAL OF SUBSTRATE TO PUT EXCEPT WORKING CIRCUIT OF the DEVICES IN MODE Of IMPOVERISHMENT

GENERATING CIRCUIT Of IMPULSES USING a MEMORIZING AND POWER SOURCE TOGETHER USING SUCH a CIRCUIT

LOGICAL CIRCUIT-PORTE Of INTEGRAL INJECTION

LOGICALLY CONTROLLED INVERTER

LOGIC INTERCONNECTIONS

Circuit of pulling towards a given state of an entry of integrated circuit

CIRCUIT OF PUMP OF LOAD TO ORDER TRANSISTORS MOS HAS CHANNEL NR

LOGIC ELEMENT

INTEGRATED CIRCUIT

MEMORY ADDRESS SELECTION CIRCUITRY

Full-swing BiCMOS driver

BiCMOS logic circuit having a rapid output voltage falling-down property

A BiCMOS logic circuit includes a MOS logic circuit connected between a high voltage supply line and a low voltage supply line and having an input connected to an input terminal, and an output circuit composed of first and second bipolar transistors connected in series between the high and low voltage supply lines. The first bipolar transistor has a base connected to an output of the MOS logic circuit, and a connection node of the first and second bipolar transistors is connected to an output terminal. In addition, a base current supplying circuit having first and second MOS transistors is connected in series between the first voltage supply line and a base of the second bipolar transistor. The first MOS transistor has a gate connected to the output of the MOS logic circuit, and the second MOS transistor has a gate connected to the input terminal.

Signal receiving and signal processing unit

A signal receiving and signal processing unit connected to one or several conductors is adapted to transmit information-carrying signals in the form of voltage pulses. A conductor is connected to a transistor belonging to a signal receiving circuit, to have an effect upon a current by using variations in the voltage pulses and the voltage value of a pulse. The current is in the form of pulses passing through the transistor. The current is generated by the voltage pulse variations and a voltage level, and the current is adapted to an information-carrying form in a signal processing circuit. The transistor belonging to the signal receiving circuit is coordinated with at least one other transistor to form a current mirror. The ability of the signal receiving circuit to receive, detect, and process the signals is adjustable through a current generating circuit such that an increasing current value provides detection of a voltage pulse at an increased transfer rate and vice versa.

Signal receiving and signal processing unit

A signal receiving and signal processing unit connected to one or several conductors is adapted to transmit information-carrying signals in the form of voltage pulses. A conductor is connected to a transistor belonging to a signal receiving circuit, to have an effect upon a current by using variations in the voltage pulses and the voltage value of a pulse. The current is in the form of pulses passing through the transistor. The current is generated by the voltage pulse variations and a voltage level, and the current is adapted to an information-carrying form in a signal processing circuit. The transistor belonging to the signal receiving circuit is coordinated with at least one other transistor to form a current mirror. The ability of the signal receiving circuit to receive, detect, and process the signals is adjustable through a current generating circuit such that an increasing current value provides detection of a voltage pulse at an increased transfer rate and vice versa.

TTL current sinking circuit with transient performance enhancement during output transition from high to low

Output stage for digital current switch

ТАКТИРУЕМЫЙ ЛОГИЧЕСКИЙ ЭЛЕМЕНТ И-ИЛИ НА КМДП ТРАНЗИСТОРАХ

Изобретение относится к области вычислительной техники и может быть использовано в КМДП интегральных схемах при реализации логических устройств. Техническим результатом изобретения является уменьшение потребляемой мощности устройства. Этот результат достигается тем, что тактируемый логический элемент И-ИЛИ на КМДП транзисторах содержит предзарядовые транзисторы (1) р-типа и (2) n-типа, тактовые транзисторы (3) р-типа и (4) n-типа, логический транзистор (5) р-типа и логический блок (6), содержащий ключевые цепи (7-8), выполненные на последовательно соединенных транзисторах n-типа, затворы которых подключены к логическим входам (9) устройства, и которые включены параллельно между выходом (12) логического блока (6) и тактовой шиной (13). Предзарядовый транзистор (2) n-типа и предзарядовый транзистор (1) р-типа, затвор которого подключен к выходу (10) устройства, включены между шиной питания (11) и выходом (12). Тактовый транзистор (4) n-типа включен между выходом (10) устройства и шиной земли ...

Схема сквозного переноса на КМОП-транзисторах

Изобретение относится к электронике и вычислительной технике. Цель изобретения - повышение надежности и быстродействия схемы сквозного переноса в сумматорах и арифметико-логических устройствах. Схема содержит элемент, обеспечивающий генерацию инверсии функции распространения переноса, выполненный на элементе И-НЕ, блок, обеспечивающий генерацию сквозного переноса и включающий инвертор и элемент ИЛИ-И-НЕ, и блок, обеспечивающий генерацию инверсии функции формирования сквозного переноса, реализованные на КМОП-транзисторах. Входами схемы служат прямые или инверсные значения входного переноса и поразрадных функций формирования и распространения переноса. 2 ил.

Combined bipolar transistor and MOSFET amplifier for ECL-CMOS level shifting circuit - uses two bipolar transistors with series MOSFETs between two opposing potentials providing amplifier inputs and outputs

The amplifier has two bipolar transistor (31-32) connected at their base and collector terminals to the amplifier inputs (33, 34) and a reference potential respectively. A respective MOSFET (35, 36) is coupled to the emitter of each bipolar transistor (31, 32) at its source, its drain coupled via an impedance (41, 42) to a second potential (VEE). The gate of each MOSFET is coupled to the drain of the other MOSFET, the amplifier outputs (39, 40) connected to the drain terminals. The impedance (41, 42) may be provided by a further pair of MOSFET's each cross-coupled at its gate to the emitter of the opposing bipolar transistor. ADVANTAGE - High operating rate and low current consumption.

Logic circuits scaled to enhance performance

CMOS CLAMPING CIRCUITS

LOW-VOLTAGE CONVERTER WITH DIFFERENTIAL INPUT AND ONLY ONE EXIT

Logic function

BIPOLAR LOGICAL HIGH-SPEED CIRCUITS.

TTL CIRCUIT WITH INCREASED SWITCHING ACHIEVEMENT.

LOGICAL CIRCUIT AND PROCEDURE FOR THE USE.

INTEGRATED BICMOS SWITCHING CONFIGURATION

General purpose divide by two logic circuit - has four similar gates and logic inverter composed of transistor stages

ELECTRONIC CIRCUIT HAS EVEN DIFFERENTIAL OF TRANSISTORS AND CARRIES LOGIQUECOMPRENANT SUCH A CIRCUIT.

SYSTEM HAS LOGICAL INJECTION INTEGREE

CONTROL DEVICE HAS FIELD-EFFECT TRANSISTORS WORKING IN MODE Of ENRICHISSEMENT/APPAUVRISSEMENT

FAST INSULATED GATE FIELD EFFECT TRANSISTOR CIRCUIT USING MULTIPLE THRESHOLD TECHNOLOGY

CIRCUIT Of ACCELERATION FEEDS BY the ALTERNATE COMPONENT OF the CURRENT

GENERATING CIRCUIT Of IMPULSES USING a MEMORIZING AND POWER SOURCE TOGETHER USING SUCH a CIRCUIT

LOGIC CIRCUIT SEMICONDUCTOR FET TRANSISTOR DIRECT COUPLING

FET ADDRESS DECODER

Circuits for electronic computers

Device for improving the operation at high frequencies of logic integrated circuits, in particular of the ECL family

CIRCUIT HAS SEMICONDUCTOR METALLIC OXIDES FOR the DETECTION Of an EDGE Of an IMPULSE

COMPRISING DECODER OF TRANSISTORS MOS

CIRCUIT OR LOGIC IMPROVES FOR LOGIC NETWORKS PROGRAMS

FIELD EFFECT TRANSISTOR PUSH?PULL DRIVER

JUST LOGICAL CIRCUIT HAS INJECTING CURRENTS

CONVERTER OF LEVEL.

BOOTSTRAPPING LEVEL ADJUSTING CIRCUIT

The bootstrapping level is adjusted according to the voltage of bootstrapping generating point of word line transmission path of DRAM. The circuit includes a MOSFET capacitor (CBOOT) and a capacitor (C4) connected to the bootstrapping point (pai1) in parallel, NOT gates (G1,G4) connected to the capacitors (C4,CBOOT) in series to delay the signal and to reverse the polarity of the signal, a NAND gate (G5) connected to the NOT gate (G1), NAND gates (G6,G8) connected to VCC level detectors; and VCC level detectors (2A,2B,2C) for detecting the Vcc level of bootstrapping point. A control signl is generated according to the VCC level and then supplied to the NAND gates (G6,-G8) to adjust the bootstrappng level. Copyright 1997 KIPO ...

OUTPUT BUFFER FOR NOISE REDUCTION

The output buffer is for controlling the on-timing of noise reduction circuit efficiently. The buffer includes a circuit(50) delaying input data for certain time, a NOR gate(10) receiving output of the circuit and enable signal of outside circuit, a pull-up/pull-down circuit(4) providing data to final output tap according the output of the NOR gate, a noise reduction control circuit(20) providing noise reduction signal when driving voltage(Vcc) greater than normal one is applied, and a circuit for reducing noise generation by forming current path between output and ground tap of the NOR gate. Copyright 1999 KIPO ...

LOW CONSUMPTION POWER TYPE WORD LINE DRIVING CIRCUIT FOR SRAM

The circuit for reducing the power consumption and preventing the lowering of driving capabilities compreses a push-pull driving circuit and a super buffer circuit, the push-pull circuit including a load FET having a depletion type FET (J5) and an enhancement type FET (J6) parallel-connected each other, and a driving FET having an enhancement type FET (J7). The super buffer circuit includes a load FET having depletion type FET's (J1,J3) and a driving FET having enhancement type FET's (J2,J4). The output of second stage of the super buffer is connected to the gate of the load FET (J5,J6). Copyright 1997 KIPO ...

INTEGRATED CIRCUIT FOR SIGNAL LEVEL CONVERTER

TRANSISTOR CIRCUIT WITH FASTER SPEED OF SWITCHING

PURPOSE: Voltage ringing can be reduced effectively without delay with a transistor off. A circuit with a better switching speed is provided in a transistor in which circuits after a speed-up condenser and a resistor for reducing ringing can be operated independently. CONSTITUTION: With the second transistor (Q2) off, the resistor for reducing ringing (RP) does not delay the second transistor going off, because the resistor for ringing (RP) is placed between the secondary winding of a transformer and a speed-up condenser (CS). With the second transistor (Q2) on, the whole electric current from the transformer to the speed-up condenser is supplied for the base terminal of the second transistor without being divided by the resistor for ringing (RP), because the resistor for ringing (RP) is placed between the transformer and the speed-up condenser (CS). This is the same as saying the current from the speed-up condenser (CS) to the base terminal does not subject itself to the resistor for ringing ...

Process monitoring by comparing delays proportional to test voltages and reference voltages

An evaluation circuit includes a test circuit configured to provide a test voltage indicative of a characteristic of a semiconductor device, a reference circuit configured to provide a first reference voltage, a first delay circuit configured to convert the test voltage into a first delay, a second delay circuit configured to convert the first reference voltage into a second delay, and a first latching circuit configured to determine a relationship between the first delay and the second delay.

Output buffer circuit having a level conversion function

Speed enhancement technique for CMOS circuits

ECL to CMOS level converter of BiCMOS type

BIPOLAR MOS LOGIC CIRCUIT

PURPOSE: To shorten the turned-on time of third and fifth transistors(TR), and to drastically change an output terminal condition by connecting first to sixth TRs in a prescribed way, turning on the sixth TR with turning off the first TR, and pulling out the base charge of the fifth TR. CONSTITUTION: When an 'H' is inputted to an npn TR Q110 with an SBD, which receives a signal to designate s logical output on a base, the same npn elements Q11 and Q14 are turned on, the collector potential of the Q11 drops, and Q12 and Q13 are turned off. A current is applied from a terminal 3 through the Q14, to a low potential connecting terminal 2, and the output terminal 3 becomes an 'L'. When the 'L' is inputted to the Q10, the Q10 and Q11 are turned off, the Q12 and Q13 are turned on, and the terminal 3 becomes the 'H' As soon as the signal is inputted to the base of the Q10, it is inputted to the gate of a pchMOSFET 15, and turns on the gate, and the base charge of the Q14 is extracted in a low resistance ...

МНОГОФУНКЦИОНАЛЬНЫЙ ЛОГИЧЕСКИЙ ЭЛЕМЕНТ НА КМДП ТРАНЗИСТОРАХ

Изобретение относится к вычислительной технике. Технический результат заключается в расширении функциональных возможностей. Устройство содержит элементы И-НЕ (1-3) с выходами (10-12), логические элементы первого типа (4) второго типа (5), тактовые транзисторы (Т) (6, 7), предзарядовый Т (8), шину питания (9), нулевую шину (13), тактовую шину (14), входы (15-17) сигналов переменных, выходы (21, 25, 26, 29, 32) устройства, а также Т (18-20, 22-24) p-типа и Т (27, 28, 30, 31, 33) n-типа. В результате устройство реализует пять логических функций от шести переменных, в том числе 2И-ИЛИ, 2ИЛИ-И, 2И, 4И, 6И. При подключении затворов Т p-типа логических элементов (4, 5) к выходам элементов И-НЕ (1-3) может быть реализован другой набор пяти логических функций на тех же выходах устройства. Элементы И-НЕ (1-3) могут содержать более двух входов и несколько ключевых цепей, включенных параллельно, что позволит реализовать многофункциональные логические устройства от большего числа входных переменных ...

DIGITAL INTEGRATED CIRCUIT COMPRISING COMPLEMENTARY FIELD EFFECT TRANSISTORS

Logische Bicmos-Schaltung

Noise attenuation output buffer

CMOS INPUT CIRCUIT.

DIFFERENCE OUTPUT STAGE FOR THREE CONDITIONS

INTEGRATED CIRCUIT

AUTOMATIC INPUT IMPEDANCE CONTROL

The present disclosure is directed to an input impedance control circuit. In one embodiment, the automatic input impedance control circuit includes a circuit controller that comprises a module for calculating an impedance and a control logic module, wherein the control logic module provides a current enable signal and a current control output signal, a driver in communication with the circuit controller for receiving the current enable signal and the current control output signal, an input voltage sensing circuit in communication with the module for calculating the impedance and the control logic module and an input current sensing circuit in communication with the module for calculating the impedance.

Burr-free double-clock switching device

Latch reverse circuit and trigger and double-latch data trigger using the same

ANTI-TORQUE DISCHARGE CIRCUIT BLOCK

DEVICE OF COMMUTATION IN TECHNOLOGY C-MOS

BINARY AMPLIFIER INTEGRATED AND INTEGRATED CIRCUIT INCORPORATING SAME

SENSE AMPLIFIER

LOGICAL ASSEMBLY HAS FIELD-EFFECT TRANSISTORS COMPLEMENTARY

CHARGE PUMP CIRCUIT FOR DRIVING N-CHANNEL MOS TRANSISTORS

Direct access semiconductor memory - has input and output registers and column and row address registers (SW 4.7.77)

EXCURSION LIMITER CIRCUIT LOGIC VOLTAGES, AND LOGIC CIRCUIT COMPRISING SUCH AN EXCURSION LIMITER

Генератор случайного полумарковского процесса с симметричными законами распределения

Полезная модель относится к области вычислительной техники и может быть использована при построении имитационных моделей систем, работающих в условиях случайных возмущений, настройке и эксплуатации различных устройств автоматики.Техническим результатом, получаемым в данном техническом решении, является упрощение генератора случайного полумарковского процесса путем уменьшения количества ячеек блока памяти, в котором задаются длительности моделируемого случайного процесса, в 2 раза и уменьшения их разрядности.Технический результат достигается тем, что в генератор случайного полумарковского процесса с симметричными законами распределения, содержащий блок синхронизации, первый выход которого подключен к входу синхронизации первого регистра памяти, выход которого является выходом генератора, выход первого регистра памяти соединен с информационным входом второго регистра памяти, выход которого подключен к первому адресному входу первого блока памяти, второй адресный вход которого соединен с выходом третьего регистра памяти, информационный вход которого соединен с выходом датчика равномерно распределенных случайных чисел, выход первого блока памяти соединен с информационным входом первого регистра памяти, три ключа, элемент ИЛИ-НЕ, второй блок памяти, счетчик, блок ключей, элемент ИЛИ, первый вход которого соединен с вторым выходом блока синхронизации, выход элемента ИЛИ соединен с входом "Опрос" датчика равномерно распределенных случайных чисел, выход которого соединен с информационным входом блока ключей, счетчик, счетный вход которого соединен с первым входом блока синхронизации, выход счетчика подключен к входу элемента ИЛИ-НЕ, выход которого соединен с управляющими входами первого, второго и третьего ключей, информационные входы первого и второго ключа объединены и подключены к третьему входу блока синхронизации, четвертый выход которого подключен к информационному входу третьего ключа, выход которого подключен к входу синхронизации третьего регистра памяти, ...

Semiconductor Device, and Display Device and Electronic Device Utilizing the Same

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.

Universal Digital Input Module in a Process Automation Controller

In a process automation controller, a universal digital input module is provided. The universal digital input module comprises a plurality of digital input channels, each channel to sink a first current at a first voltage level associated with an input having a digital high value and to sink a second current at a second voltage level associated with the input having a digital high value, wherein the first current is greater than the second current and wherein the first voltage is less than the second voltage.

Receiver circuit with high input voltage protection

An integrated circuit 2 includes a receiver circuit 4 for receiving an input signal PAD and converting this to an output signal OUT. Conduction path circuitry 14 couples an input 10 to a first node 16 . Buffer circuitry 18 is coupled between the first node 16 and an output 12 carrying the output signal Out. The conduction path circuitry comprises a first PMOS transistor 24 and a second PMOS transistor 26 connected between the input 10 and the first node 16 . A first NMOS transistor 28 is connected between the input 10 and the first node 16 . The gate of the second PMOS transistor 26 is coupled to the output 12 to directly receive the output signal and thereby achieve rapid cut off of the charging of the node 16 when the input voltage rises beyond a certain level which switches the buffer circuitry 18.

Vol up-shifting level shifters

A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

Semiconductor device and method of adjusting characteristic thereof

To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Switching circuits, latches and methods

Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.

Electronic device and method for buffering

A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Level shifter circuit, scanning line driver and display device

An object of the present invention is to achieve a scanning line drive device which allows further reduction of circuit scale and production costs. A gate driver ( 100 ) of the present invention includes: a shift register circuit ( 1 ) including g latch circuits ( 21 ) to ( 2 g ); g selection circuits ( 8 ); and g level shifter circuits ( 3 ). A level shifter circuit ( 3 ) of an output drive circuit (st 1 ) receives a pulse ( 61 ) from a NAND circuit ( 6 ) of a selection circuit ( 8 ) at its input terminal (N 1 ); a pulse ( 71 ) from a NAND circuit ( 7 ) of the selection circuit ( 8 ) at its input terminal (N 2 ); and a pulse (Q 1 ) from a latch circuit ( 21 ) at its input terminal (N 3 ). The level shifter circuit ( 3 ) of the output drive circuit (st 1 ) outputs a voltage signal obtained by converting the voltage level of the pulse ( 61 ) from its output terminal (O 1 ); and a voltage signal obtained by converting the voltage level of the pulse ( 71 ) from its output terminal (O 2 ).

Semiconductor device, circuit board device, and information processing device

In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Driver circuit and video system

In a driver circuit in a transmission system, an output circuit outputs a differential signal based on input data signals. A current source control circuit controls a constant current source so that a common-mode potential of the differential signal becomes equal to a predetermined reference potential. An overshoot reduction circuit is connected to an input line of the common-mode potential of the current source control circuit, and reduces an overshoot of the common-mode potential based on the control signal.

Buffer circuit having switch circuit capable of outputting two and more different high voltage potentials

A buffer circuit includes a first node receiving a first voltage, a second node receiving a second voltage lower than the first voltage, a third node, an output node driving the first voltage and the second voltage, a first transistor coupled between the first node and the output node, a second transistor coupled between the second node and the output node, one end of the second transistor being connected to the second node, another end of the second transistor being connected to the third node, and a switch circuit coupled between the output node and the third node. Both of the first transistor and the switch circuit include a transistor having a first breakdown voltage. The second transistor has a second breakdown voltage being different from the first breakdown voltage.

Differential output buffer

According to one embodiment, a main driver is configured to shift the level of a differential signal. A bypass circuit is configured to bypass current flowing through the main driver in such a manner as to contain the change amount of current running through the main driver flowing from a high power supply potential to a low power supply potential within a fixed range upon transition between an operating state and a standby state of the main driver.

Symmetrical, Direct Coupled Laser Drivers

Symmetrical, direct coupled laser drivers for high frequency applications. The laser drivers are in integrated circuit form and use a minimum of relatively small (low valued) external components for driving a laser diode coupled to the laser driver through transmission lines. An optional amplifier may be used to fix the voltage at an internal node at data frequency spectrum to improve circuit performance. Feedback to a bias input may also be used to fix the voltage at the internal node. Programmability and a burst mode capability may be included.

Low Voltage Differential Signal Driving Circuit and Digital Signal Transmitter

A low voltage differential signal (LVDS) driving circuit and a digital signal transmitter with the LVDS driving circuit are provided. The LVDS driving circuit includes a positive differential output terminal and a negative differential output terminal and a transition accelerator. A differential output signal is provided by the positive and negative differential output terminals. When the differential output signal transits from low to high, the transition accelerator couples the positive differential output terminal to a high voltage source and couples the negative differential output terminal to a low voltage source. When the differential output signal transits from high to low, the transition accelerator couples the positive differential output terminal to the low voltage source and couples the positive output terminal to the high voltage source.

Receiver circuit

A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.

Output circuit and output control system

An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Output stage circuit for outputting a driving current varying with a process

An output stage circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, and a current source. A voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor is a first voltage minus a voltage drop between a first terminal and a second terminal of the first P-type metal-oxide-semiconductor transistor. The N-type metal-oxide-semiconductor transistor is coupled between the third terminal of the first P-type metal-oxide-semiconductor transistor and the current source. A second terminal of the second P-type metal-oxide-semiconductor transistor is coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor. When a second terminal of the N-type metal-oxide-semiconductor transistor receives a kick signal, a driving current flowing through the second P-type metal-oxide-semiconductor transistor is relevant to the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor.

Coupling Circuit, Driver Circuit and Method for Controlling a Coupling Circuit

A coupling circuit has a first and a second transistor (P 1, P 2 ) of a p-channel field-effect transistor type. A drain terminal of the first transistor (P 1 ) is connected to a signal input ( 1 ), source terminals of the first and the second transistor (P 1, P 2 ) are commonly connected to a signal output ( 2 ), bulk terminals of the first and the second transistor (P 1, P 2 ) are commonly connected to a drain terminal of the second transistor (P 2 ), and a gate terminal of the first transistor (P 1 ) is connected to a gate terminal of the second transistor (P 2 ). The coupling circuit further comprises a gate control circuit ( 10 ) with a charge pump circuit ( 110 ) which is configured to generate a negative potential. The gate control circuit ( 10 ) is configured to control a gate voltage at the gate terminals of the first and the second transistor (P 1, P 2 ) based on a negative potential.

Differential output buffer having mixing and output stages

An exemplary differential output buffer includes a mixing stage and an output stage. The mixing stage includes a mixing circuit that mixes a differential data signal and an inverted delayed differential data signal to generate a mixed differential data signal. The output stage includes a first and a second output stage differential pair of transistors. Sources of the transistors in each of the output stage differential pairs are commonly coupled. Gates of the transistors in the first and second output stage differential pairs are supplied with the differential data signal and the mixed differential data signal, respectively. Drains of corresponding ones of the transistors in the first and second output stage differential pairs are commonly connected to form output nodes to output an emphasized differential data signal. The mixing stage includes a mixing ratio setting circuit that sets the mixing ratio to one of 1:0, 1:1, and 0:1.

Input circuit

The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.

High definition multimedia interface (hdmi) apparatus including termination circuit

A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.

Clamping circuit to a reference voltage for ultrasound applications

A clamping circuit includes a clamping core connected to an output terminal and having a central node connected to a voltage reference and at least one first and one second clamp transistor, connected to the central node and having respective control terminals, the clamping core being also connected at the input to a low voltage input driver block. The clamping core includes a first switching off transistor connected to the output terminal and to the first clamp transistor, as well as a second switching off transistor connected to the output terminal and to the second clamp transistor.

Level shift circuit

A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Semiconductor device

A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code, and an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code.

Device

A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

Cml to cmos conversion circuit

The present invention provides a CML to CMOS conversion circuit comprising a first differential unit, a second differential unit, and an output unit. The output unit comprises a series connection of a first inverter and a second inverter, wherein, a resistor is connected with the first inverter in parallel. The CML to CMOS conversion circuit of the present invention omits the amplifier in the conventional circuit and reduces the delay time to 34 ps, which is almost half of the delay time of 64 ps in the conventional circuit, and thus provides more clock delay redundancy for the high speed parallel-serial conversion circuit.

Output driver, devices having the same, and ground termination

An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.

Voltage switch circuit

A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.

Output buffer, operating method thereof and devices including the same

A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals.

DRIVING CIRCUIT WITH ZERO CURRENT SHUTDOWN AND A DRIVING METHOD THEREOF

Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current. 1. A driving circuit comprising:a) a linear regulating circuit configured to receive an input voltage source, and to provide an output voltage based on a first current;c) a first power switch configured to receive said output voltage of said linear regulating circuit and an external enable signal, and to generate an internal enable signal configured to drive a logic circuit; andd) a start-up circuit configured to receive said external enable signal at a gate of a second power switch, wherein when said external enable signal is lower than a threshold voltage that is related to said second power switch, said start-up circuit is configured to disable said first current and said driving circuit, and when said external enable signal is higher than said threshold voltage, said start-up circuit is configured to a generate said first current and enable said driving circuit.2. The driving circuit of claim 1 , further comprising a first current mirror coupled to said input voltage source claim 1 , said linear regulating circuit claim ...

Adaptive termination

A system for receiving data is provided the system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.

SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF

A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signals, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal. 1. A semiconductor device comprising:a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock;a driving signal generation unit configured to decide logic levels of a first driving signal and a second driving signal based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first driving signal and the second driving signal, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first driving signal and the second driving signal; andan output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal.2. The semiconductor device of claim 1 , wherein the driving signal generation unit comprises:a first driving signal output section configured to decide the logic level of the first driving signal in response to the input data, to determine transition to a second logic level based on the source ...

LEVEL SHIFT CIRCUIT AND DRIVE CIRCUIT OF DISPLAY DEVICE

In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage. 1. A level shift circuit comprising:a first MOS transistor of a first conductivity type, into a gate of which an input signal having an amplitude between a third supply voltage indicating a voltage between a first supply voltage and a second supply voltage and the first supply voltage is input;a second MOS transistor of the first conductivity type, into a gate of which an inverted input signal which is an inverted signal of the input signal, is input, sources of the first and the second MOS transistors being commonly coupled to the first supply voltage;a third MOS transistor of a second conductivity type complementary to the first conductivity type, whose gate is coupled to a drain of the second MOS transistor;a fourth MOS transistor of the second conductivity type, whose gate is coupled to a drain of the first MOS transistor, sources of the third and the fourth MOS transistors being commonly coupled to the second supply voltage;a first voltage generation circuit coupled between the drain of the first MOS transistor and a drain of the third MOS transistor;a second voltage generation circuit coupled between the drain of the second MOS transistor and a drain of the fourth MOS transistor;a fifth MOS transistor of the second conductivity type, whose gate is coupled to a ...

Switching circuit

A switching circuit suitable for a low power oscillator circuit includes control and output circuits, the control circuit arranged to control the output circuit, the control circuit having input and output terminals, the output circuit having input and output terminals and control terminals; wherein the input terminal of the control circuit is connected to the input terminal of the output circuit, and the control terminal of the output circuit is connected to the output terminal of the control circuit, the output circuit first switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time, and the control circuit has second switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time.

Output buffer circuit

There is provided an output buffer circuit which can reduce the time differences of the rise time and fall time of the output voltages of a differential output signal and, furthermore, can make the rise time and fall time match with a good precision. To the resistance elements R 1, R 2, PMOS transistors Tr 5, Tr 6 are connected in parallel. At this time, if designating the resistance components of the resistance elements R 1, R 2 as r 1 (Ω), r 2 (Ω), designating the resistance components of the PMOS transistors Tr 5, Tr 6 as rTr 5 (Ω) and rTr 6 (Ω), and designating the resistance component of the current source I 1 as rI 1 (Ω), the conditions of (r1//rTr5)=(r2//rI1) and (r2//rTr6)=(r1//rI1) are satisfied. Due to this, the time differences between the rise time and fall time of the output voltages can be reduced and, furthermore, the rise time and fall time can be made to precisely match.

Level shifters and integrated circuits thereof

An integrated circuit including a first level shifter configured to receive a first input signal and a first power supply signal, and to output a first output signal. The integrated circuit further includes a first inverter configured to receive the first output signal, and to output a first inverter signal. The integrated circuit further includes a second level shifter configured to receive a second input signal and a second power supply signal, and to output a second output signal, wherein a voltage level of the second power supply signal is different from a voltage level of the first power supply signal. The integrated circuit further includes a second inverter configure to receive the second output signal, and to output a second inverter signal. The integrated circuit further includes an output buffer configured to receive the first inverter signal and the second inverter signal, and to output a buffer output signal.

Slew-rate limited output driver with output-load sensing feedback loop

Output driver feedback circuitry is configured to sense an amount of output capacitance of an output pad and to adjust the strength of the output driver accordingly. The feedback circuitry adjusts the output driver within a single cycle. A chain of delay reference signals is generated by representative capacitive loads that replicate a range of actual output loads. Adjustments to the output driver are based on a comparison of the delay reference signals with output of the output driver.

3x input voltage tolerant device and circuit

A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

TECHNIQUES FOR SWITCHING BETWEEN AC-COUPLED CONNECTIVITY AND DC-COUPLED CONNECTIVITY

A circuit for switching between an AC-coupled connectivity and DC-coupled connectivity of a multimedia interface. The circuit comprises a current source connected in series to a wire of the multimedia interface and a coupling capacitor; and a termination resistor connected to the current source and to the coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, wherein the current source and the termination resistor allows the setting of voltage levels of signals received at the sink line receiver to voltage levels defined by the multimedia interface thereby to switch to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates. 1. A circuit for switching between an AC-coupled connectivity and a DC-coupled connectivity of a multimedia interface , comprising:a first current source connected in series to a first wire of the multimedia interface and a first tap of a first coupling capacitor; anda first termination resistor connected to the first current source and to the first tap of the first coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, thereby the circuit switches to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates, wherein the sink line receiver is connected to the first tap of the first coupling capacitor and the source line driver is connected to a ...

Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments

A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.

PROGRAMMABLE LOGIC SWITCH

One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory. 1. A programmable logic switch comprising: a first channel region provided between a first source and a first drain;', 'a first insulating film formed on the first channel region;', 'a first charge storage film formed on the first insulating film;', 'a second insulating film formed on the first charge storage film; and', 'a first gate electrode formed on the second insulating film;, 'a first nonvolatile memory having a second channel region provided between a second source and a second drain;', 'a third insulating film formed on the second channel region;', 'a second charge storage film formed on the third insulating film;', 'a fourth insulating film formed on the second charge storage film; and', 'a second gate electrode formed on the fourth insulating film;, 'a second nonvolatile memory havinga first line connected to the first gate electrode and to the second gate electrode;a second line connected to the first source;a third line connected to the first drain and to the second drain;a fourth line connected to the second source;a substrate electrode through which a substrate voltage is applied to a well, the first nonvolatile memory and the second nonvolatile memory being formed in the well;one or more first logic transistors connected to the third line, each first logic transistor being ...

Semiconductor integrated circuit

A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition.

INPUT BUFFER

An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal. 1. An input buffer comprising:a first amplification block configured to be driven by an external voltage and differentially amplify an input signal and a reference voltage in response to a bias voltage generated from the reference voltage, and generate first and second differential signals; anda second amplification block configured to be driven by an internal voltage and differentially amplify the first and second differential signals and generate an output signal.2. The input buffer of claim 1 , wherein the levels of the first and second differential signals are adjusted by the bias voltage.3. The input buffer of claim 1 , wherein the first amplification block comprises:a first switch unit configured to be turned on according to the bias voltage and control driving of a first node according to the external voltage; anda differential amplification unit coupled between the first node and a second node and configured to differentially amplify the input signal and the reference voltage and generate the first and second differential signals.4. The input buffer of claim 3 , wherein the differential amplification unit comprises:a load section coupled between the first node and a third node through which the first differential signal is outputted, and the load section coupled between the first node and a fourth ...

FLOATING GATE DRIVER WITH BETTER SAFE OPERATION AREA AND NOISE IMMUNITY, AND METHOD FOR LEVEL SHIFTING A SWITCH SIGNAL

A floating gate driver includes a level shifter to transmit a set signal and a reset signal to a first output terminal and a second output terminal, respectively. The level shifter includes a first high-voltage transistor, a first current limiter and a first input transistor connected in series between the first output terminal and a ground terminal, and a second high-voltage transistor, a second current limiter and a second input transistor connected in series between the second output terminal and the ground terminal, and the first and second high-voltage transistors are remained on. With this arrangement, the level shifter can transmit signals from low side to high side under better safe operating area and has better noise immunity. 1. A floating gate driver , comprising:an edge pulse generator detecting a rising edge and a falling edge of a switch signal to trigger a set signal and a reset signal, respectively;a level shifter having a first input transistor and a second input transistor connected to the edge pulse generator for transmitting the set signal and the reset signal to a first output terminal and a second output terminal to generate a first negative voltage pulse and a second negative voltage pulse, respectively; anda logic regeneration circuit connected to the first output terminal and the second output terminal, responsive to the first negative voltage pulse and the second negative voltage pulse to generate a signal as being level shifted from the switch signal; a first high-voltage transistor and a second high-voltage transistor connected to the first output terminal and the second output terminal, respectively, and remained on;', 'a first current limiter connected between the first high-voltage transistor and the first input transistor; and', 'a second current limiter connected between the second high-voltage transistor and the second input transistor., 'wherein the level shifter further comprises2. The floating gate driver of claim 1 , wherein ...

TRANSMISSION CIRCUIT

A transmission circuit includes a first drive part capable of switching to one of an on state that is driven by current and an off state, i.e., a high impedance state in accordance the value of a first input signal; and a first termination resistor part connected in series with the first drive part. The resistance values of the first drive part are switched in accordance with the state of the first drive part. 1. A transmission circuit comprising:a first drive part capable of switching to one of an on state that is driven by current and an off state, that is, a high impedance state in accordance the value of a first input signal; anda first termination resistor part connected in series with the first drive part and the resistance values of which are switched in accordance with the state of the first drive part.2. The transmission circuit according to the claim 1 , further comprising:a second drive part capable of switching to one of an on state that is driven by current and an off state, that is, a high impedance state in accordance the value of a second input signal and configured to enter the off state when the first drive part is in the on state and to enter the on state when the first drive part is in the off state; anda second termination resistor part connected in series with the second drive part and the resistance values of which are switched in accordance with the state of the second drive part.3. The transmission circuit according to claim 2 , whereinthe first termination resistor part has a first base resistor part and a first adjustment resistor part connected in parallel with the first base resistor part and the resistance values of which are switched in accordance with the state of the first drive part, andthe second termination resistor part has a second base resistor part and a second adjustment resistor part connected in parallel with the second base resistor part and the resistance values of which are switched in accordance with the state of the ...

Dual Path Level Shifter

Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters. 1. A dual path level shifter comprising:a dual path level shifter input terminal;a dual path level shifter output terminal;a first voltage-to-current converter;a second voltage-to-current converter;a third voltage-to-current converter;a first current-to-voltage converter; anda second current-to-voltage converter,wherein:in a first condition, during operation, an input signal having an input signal level swinging between an input signal low voltage level and an input signal high voltage level is routed from the dual path level shifter input terminal to an input of the first voltage-to-current-converter, from an output of the first voltage-to-current-converter to an input of the second current-to-voltage converter, from an output of the second current-to-voltage converter to an input of the third voltage-to-current converter, from an output of the third voltage-to-current converter to an input of the first current-to-voltage converter and from the output of the first current-to-voltage converter to the dual path level shifter output terminal;in a second condition, during operation, the input signal is routed from the dual path level shifter input terminal to an input of the second voltage-to-current converter, from an output of the second voltage-to-current converter to the input of the first current-to-voltage converter and from the output of first current-to-voltage converter to the dual path level shifter output terminal;during operation in the second condition, no current is flowing through an electrical path defined by the input signal routing of the first condition;the output signal is a replicate of the input signal swinging between an output signal low voltage level and an output signal high voltage level, so that the output signal low/high level is a shifted version of the input signal low/high level ...

INTERFACE CIRCUIT

According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor. 1. An interface circuit comprising:an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor; anda driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.2. The interface circuit according to claim 1 ,wherein the driver circuit is provided with a slew rate control unit which is capable of changing the turn-ON speed of the transistor, and a reset rate control unit which is capable of changing the turn-OFF speed of the transistor.3. The interface circuit according to claim 2 ,wherein the transistor is provided with a first P-channel field-effect transistor and a first N-channel field-effect transistor which is connected to the first P-channel field-effect transistor in series, andthe driver circuit is provided with a P-slew rate control unit which is capable of changing a turn-ON speed of the first P-channel field-effect transistor, a P-reset rate control unit which is capable of changing a turn-OFF speed of the first P-channel field-effect transistor, a N-slew rate control unit which is capable of changing a turn-ON speed of the first N-channel field-effect transistor, and a N-reset rate control unit which is capable of changing a turn-OFF speed of the first N-channel field-effect transistor.4. The interface circuit according to claim 3 , further comprising:a time lag generation circuit which adds a period of time in order to turn off both of the first P-channel field-effect transistor and the first N-channel field-effect transistor at the same time.5. The interface circuit according to claim 4 , further comprising:a level ...

SWITCHING ARRANGEMENT, INTEGRATED CIRCUIT COMPRISING SAME, METHOD OF CONTROLLING A SWITCHING ARRANGEMENT, AND RELATED COMPUTER PRORAM PRODUCT

There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant. 1. A switching arrangement , comprising:a switch comprising a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail, each of said elementary switches being in either one of a closed state and an open state independently of the others; and,a controller adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch, wherein the number of elementary switches in the closed state is variable and wherein the higher is the intensity of the current the higher the number of elementary switches in the closed state.2. The switching arrangement of claim 1 , wherein the controller is further adapted to receive claim 1 , from a load supplied by the second supply rail claim 1 , a current value indication representative of the intensity of the current flowing through the switch claim 1 , and to control the closing or opening of the elementary switches responsive to said current value indication.3. The switching arrangement of claim 1 , wherein the controller comprises a current-sense block adapted to ...

Output driver, electrical device having the output driver, and method of evaluating the output driver

An output driver includes a data processing unit configured to perform a data processing on an input signal to generate processing result data; a D/A (Digital-to-Analog) conversion unit configured to apply D/A conversion on the processing result data to generate an analog signal; an output amplifier configured to amplify the analog signal to obtain an amplified analog signal as an output signal; a comparing unit configured to compare the processing result data with expected value data to obtain and output comparison result data; and an output control unit configured to select the comparison result data as the output signal instead of the amplified analog signal according to a comparison output selection signal.

Buffering circuit, semiconductor device having the same, and methods thereof

A multipoint low-voltage differential signaling (mLVDS)receiver of a semiconductor device and a buffering circuit of a semiconductor device, includes: an even-number data buffering unit configured to: sample even-number data from input data, amplify and output the even-number data in a section in which a positive clock is activated, and latch the even-number data in a section in which the positive clock is inactivated, and an odd-number data buffering unit configured to: sample odd-number data from the input data, amplify and output the odd-number data in a section in which a negative clock is activated, and latch the odd-number data in a section in which the negative clock is inactivated.

ASYMMETRICAL BUS KEEPER

Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level. 2. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a single p-channel transistor wherein a gate of the p-channel transistor is connected to the input node of the asymmetrical inverter stage claim 1 , a source of the p-channel transistor is connected to a positive voltage supply level claim 1 , and a drain of the p-channel transistor is connected to the output node of the asymmetrical inverter stage.3. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a p-channel transistor having a first drive and an n-channel transistor having a second drive claim 1 , the p-channel and n-channel transistors being oriented in an inverter configuration claim 1 , wherein the first drive is at least one order of magnitude larger than the second drive.4. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level and the asymmetrical ...

POWER STAGE

A power stage has a differential output stage driven by one or more buffer stages The buffer stages are implemented as high and low side buffers each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS. 1. An apparatus , comprising:an input circuit configured and arranged to provide a drive signal in response to receiving an input voltage;a first set of isolation capacitive couplers provided with the drive signal from the input circuit;at least one differential buffer stage, having a high side buffer stage and a low side buffer stage, configured and arranged to receive the drive signal from the first set of isolation capacitive couplers; andan output stage, between a high voltage rail and a low voltage rail, configured and arranged to drive an isolation transformer through a second set of isolation capacitive couplers in response to the drive signal received from the at least one differential buffer stage.2. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a first buffer stage having an inverting output that drives an inverting input of a second buffer stage.3. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a self-biassing bias line connecting parallel ports of a first buffer stage and a second buffer stage and providing an intermediate voltage between the high side line and the low side line.4. The apparatus of claim 1 , wherein the input circuit is further configured and arranged between the low voltage rail and a digital power supply voltage.5. The apparatus of claim 1 , wherein the input circuit provides an input signal that includes a sinusoidal input voltage.6. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a plurality of transistors which are each implemented with an isolated well.7. The apparatus of claim 1 , wherein the at least one differential buffer stage ...

Sensor Connection Circuit

A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train. 1. A sensor connection circuit comprising:an input node;an output node, the output node being sampled by an acquisition circuit;a comparator connected between the input node and the output node; anda switching element connected between the input node and a ground node, the switching element being controlled by a control signal, wherein the sampling of the output node is synchronized with the control signal.2. The sensor connection circuit of further comprising a level adapter connected between comparator and the output node.3. The sensor connection circuit of claim 1 , wherein the control signal has a duty cycle greater than 10%.4. The sensor connection circuit of claim 1 , wherein the comparator comprises two inputs claim 1 , a first input connected to the input node claim 1 , and a second input connected to a reference voltage.5. The sensor connection circuit of further comprising a current-limiting element connected in series with the switching element.6. The sensor connection circuit of claim 1 , wherein the acquisition circuit comprises a microcontroller.7. The sensor connection circuit of further comprising: a visual indicator; and', 'a second switching element, the second switching element connected in parallel with the visual indicator, the second switching element being controlled by an output of the comparator., 'an indicator circuit connected in series with the switching element, the indicator circuit comprising8. An integrated circuit comprising: an ...

Voltage compensated level-shifter

Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.

Circuit Arrangements and Methods of Operating the Same

In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.

Bootstrap circuit

A bootstrap circuit includes an input terminal, an inverting input terminal, an output terminal, an inverting output terminal, a first sub-bootstrap circuit, a second sub-bootstrap circuit, and a charging path providing circuit. The first sub-bootstrap circuit includes a first bootstrap capacitor, a first charging path, a first discharging path, and a first high voltage providing path. The charging path providing circuit includes a third charging path. In response to a high voltage level inputted into the input terminal, the first charging path and the third charging path are turned on, the first bootstrap capacitor is charged to a capacitor voltage, and the first discharging path is turned on to discharge the output terminal. In response to a low voltage level inputted into the input terminal, a first superimposed voltage including the high voltage level and the capacitor voltage is provided to the output terminal.

Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method

An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

INTERFACE IC AND MEMORY CARD INCLUDING THE SAME

A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view. 1. A memory card comprising:a memory that stores data;a driver that transmits the data received from the memory; andat least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit,wherein the driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.2. The memory card according to claim 1 , wherein the at least one transmitter comprises a coil.3. The memory card according to claim 1 , wherein the at least one transmitter comprises a plurality of transmitters.4. The memory card according to claim 3 , wherein the plurality of transmitters transmit the data to the receiver alternately.5. The memory card according to claim 3 , wherein the plurality of transmitters transmit the data to the receiver randomly.6. The memory card according to claim 1 , further comprising a clock receiver that receives a clock signal from the external main unit.7. The memory card according to claim 6 , wherein a size of the at least one transmitter differs from a size of the clock receiver.8. The memory card according to claim 1 , further comprising an encrypting circuit that encrypts the data received from the memory and transmits the encrypted data to the driver.9. The memory card according to claim 8 , wherein the encrypting circuit is provided in the IC chip.10. The memory card according to claim 1 , wherein the memory is provided in the IC chip.11. The memory card according to claim 1 , wherein the data stored in the memory comprises a game software.12. An ...

SEMICONDUCTOR DEVICE BASED ON POWER GATING IN MULTILEVEL WIRING STRUCTURE

A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively. 1. A device comprising: a first circuit cell array extending in a first direction,', 'a second circuit cell array extending in the first direction substantially in parallel to the first circuit cell array,', 'first and second power lines each of which extends in the first direction and arranged over the first circuit cell array,', 'third and fourth power lines each of which extends in the first direction and arranged over the second circuit cell array,', 'a first transistor coupled between the second and third power supply lines,', 'a plurality of first logic circuits arranged in the first cell array, each of the first logic circuits includes first and second power nodes coupled respectively to the first and second power lines,', 'a plurality of second logic circuits arranged in the second cell array, each of the second logic circuits includes third and fourth power nodes coupled respectively to the third and fourth power lines,', 'a first interconnection connecting an output node of a first one of the first logic circuits to an input node of a first one of the second logic circuits, and', 'a second interconnection connecting an output node of the first one of the second logic circuits to an input node of a second one of the first logic circuits., 'a circuit unit ...

SEMICONDUCTOR DEVICE HAVING FLOATING BODY TYPE TRANSISTOR

A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level. 1. A semiconductor device comprising:a first circuit node supplied with a first signal changing between first and second logic levels;a second circuit node supplied with a second signal changing between the first and second logic levels;a third circuit node;a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level;a fourth circuit node supplied with a voltage level being close to or the same as the second logic level; anda second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level,the first transistor being configured as a floating body type in which a body between a source and a drain is in en electrically floating state.2. The semiconductor device as ...

INPUT CIRCUIT ARRANGEMENT, OUTPUT CIRCUIT ARRANGEMENT, AND SYSTEM HAVING AN INPUT CIRCUIT ARRANGEMENT AND AN OUTPUT CIRCUIT ARRANGEMENT

The invention relates to an input circuit arrangement (), which is designed for operation either in a first or a second operating mode (A, B) and comprises a connection () for supplying a connection signal (SWI) and a detection circuit (). The detection circuit () is coupled on the input side to the connection () and is designed to put the input circuit arrangement () into an operating mode from a group comprising the first and second operating modes (A, B) depending on the steepness of a change of the connection signal (SWI). 1. An input circuit arrangement , which is designed for operation either in a first or a second operating mode , the input circuit arrangement comprising:a connection for supplying a connection signal; anda detection circuit that is coupled on the input side to the connection and is designed to put the input circuit arrangement into an operating mode from a group comprising the first and second operating modes depending on a steepness of a change of the connection signal),wherein, in the first operating mode, via the connection, both data information and also clock information are supplied to the input circuit arrangement, and, in the second operating mode, the input circuit arrangement is designed to provide an input signal that corresponds to the connection signal.2. The input circuit arrangement according to claim 1 , wherein the detection circuit is designed to put the input circuit arrangement into a first operating mode if the steepness of the change of the connection signal is smaller than a predetermined value claim 1 , and to put the input circuit arrangement into the second operating mode if the steepness of the change of the connection signal is greater than the predetermined value.3. The input circuit arrangement according to or claim 1 , wherein the detection circuit is designed to put claim 1 , depending on the steepness of the falling edge of the connection signal claim 1 , the input circuit arrangement into an operating mode ...

APPARATUS FOR MIXED SIGNAL INTERFACE ACQUISITION CIRCUITRY AND ASSOCIATED METHODS

An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation. 1. An integrated circuit (IC) , comprising:a plurality of pads adapted to communicate signals with a circuit external to the IC;a first mixed signal interface block coupled to a first pad in the plurality of pads, the first mixed signal interface block adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal; anda second mixed signal interface block coupled to a second pad in the plurality of pads, the second mixed signal interface block adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC, and to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC,wherein a power consumption of the IC is lower in the first mode of operation than in the ...

Receiver circuit

A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a first intermediate output signal and a second intermediate output signal. The second amplification unit is configured to differentially amplify the first and second intermediate output signals and generate an output signal. The first equalizing unit is configured to control the level of the second intermediate output signal in response to the output signal. And the second equalizing unit is configured to control the level of the first intermediate output signal in response to the output signal.

Level shifting circuit for high voltage applications

A level shifting circuit includes a current mirror that generates a first bias current and a second bias current (proportional to the first bias current with a first ratio). A first level shifter is coupled between a first input node (receiving a first input signal) and a first output node coupled to an input of the current mirror. The first level shifter applies a first voltage variation to the first input signal in response to the first bias current. A second level is coupled between a second input node (receiving a second input signal) and a second output node coupled to an output of the current mirror. The second level shifter applies a second voltage variation (associated with the first voltage variation) to the second input signal in response to the second bias current.

LEVEL SHIFTER

A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal. 1. A level shifter , comprising: a first Type 1 transistor;', 'a second Type 1 transistor, wherein the gate of the first Type 1 transistor and the gate of the second Type 1 transistor are connected to a first input terminal and a second input terminal respectively, the sources of both the first Type 1 transistor and the second Type 1 transistor are connected to a first voltage terminal;', 'a third Type 1 transistor, wherein the gate and the drain of the third Type 1 transistor are interconnected, the source of the third Type 1 transistor is connected to the drain of the first Type 1 transistor; and', 'a fourth Type 1 transistor, wherein the gate and the drain of the fourth Type 1 transistor are interconnected, the source of the fourth Type 1 transistor is connected to the drain of the second Type 1 transistor; and, 'a plurality of Type 1 transistors, wherein each of the Type 1 transistors includes a source, a gate, and a drain, the Type 1 transistors include a first Type 2 transistor, wherein the drain and the gate of the first Type 2 transistor are interconnected and also connected to the drain of the third Type 1 transistor;', 'a second Type 2 transistor, wherein the drain and the gate of the second Type 2 transistor are interconnected and also connected to the drain of the fourth Type 1 transistor;', 'a third Type 2 transistor, wherein the drain of the third Type 2 transistor is connected to the source of the first Type 2 ...

Pre-Heating For Reduced Subthreshold Leakage

Certain semiconductor processes provide for the use of multiple different types of transistors with different threshold voltages in a single IC. It can be shown that in certain ones of these semiconductor processes, the speed at which high threshold transistors can operate at decreases with decreasing temperature. Thus, the overall processing speed of an IC that implements high, threshold transistors is often limited by the lowest temperature at which the IC is designed (or guaranteed) to properly function. Embodiments of a system and method that overcome this deficiency by “pre-heating” the IC (or at least portions of the IC that implement the high threshold transistors) such that the IC can operate at a frequency (once pre-heated) higher than what would otherwise be possible for a given minimum temperature at which the IC is designed or guaranteed) to properly function at are provided. 1. A system comprising:a variable frequency oscillator configured to generate a clock signal to clock a sequential logic block; anda pre-heating controller configured to reduce a frequency of the clock signal if a temperature associated with the sequential logic block is determined to be below a particular temperature.2. The system of claim 1 , wherein the sequential logic block comprises a first device that has an operating speed that decreases with decreasing temperature of the first device.3. The system of claim 2 , wherein the sequential logic block comprises a storage element configured to store a logic value produced at least in part by the first device.4. The system of claim 2 , wherein the first device is configured to form an inversion layer at a first threshold voltage and is implemented on an integrated circuit with a second device claim 2 , the second device configured to form an inversion layer at a second threshold voltage that is less than the first threshold voltage.5. The system of claim 4 , wherein the first device and the second device are transistors.6. The ...

DIFFERENTIAL OUTPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances. 1. A differential output circuit comprising:a current source;a voltage source;first paired transistors configured to, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and configured to be always turned off in a second operating mode;second paired transistors configured to, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode;third paired transistors configured to, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, depending on the logic levels of the differential input signals, and configured to be always turned on in the first operating mode, the third paired transistors being connected to output current paths of the second ...

Level Shifter Having Feedback Signal From High Voltage Circuit

According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit. The high voltage circuit is configured to receive the differential signal from the low voltage circuit so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The differential signal is provided by the low voltage circuit responsive to a feedback signal from the high voltage circuit. The feedback signal can indicate common mode noise in the level shifter. Furthermore, the low voltage circuit can be configured to refresh the differential signal responsive to the feedback signal.

Autonomous initialization method of facing port of semiconductor integrated circuit and semiconductor integrated circuit

On a transmission path connecting a first semiconductor integrated circuit that is started by a system management apparatus and a second semiconductor integrated circuit that is not started by the system management apparatus, when connection of the first semiconductor integrated circuit to the second semiconductor integrated circuit is detected, after being turned to a first signal state for detecting a valid lane, each lane on the transmission path is turned to a second signal state corresponding to each bit of initial setting code. In the second semiconductor integrated circuit, the first and second signal states are detected for each lane of the transmission path. Based on the detected signal state, after detecting the first signal state, the second signal state is detected and each bit value of the initial setting code is decoded. Based on the decoded initial setting code, an initialization process is executed.

Common mode termination with c-multiplier circuit

Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.

Output buffer and signal processing method

An output buffer comprises a series connection of a first field effect transistor and a second field effect transistor, wherein the first field effect transistor is connected to a first supply potential terminal and the second field effect transistor is connected to a second supply potential terminal. An output terminal is connected to a common connection of the first transistor and the second transistor. The output buffer has a series connection of a resistive element and a capacitive element, wherein the capacitive element is connected to the output terminal, and a control circuit, to which an input signal is provided. The control circuit controls the transistors in such a way that turning off of a transistor is performed immediately, while turning on of a transistor is performed depending on the charging or discharging of the capacitive element, thus achieving a defined slew rate of the output signal at the output terminal.

LOW VOLTAGE TRANSMITTER WITH VARIABLE OUTPUT SWING

Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source. 1. An apparatus comprising:a voltage mode driver coupled to an output node; anda switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver.2. The apparatus of further comprises:a bias generator to bias the switching current source.3. The apparatus of claim 1 , wherein the switching current source comprises:a first current source, coupled to the output node, to increase the voltage swing of the signal on the output node by raising a logical high level of the signal.4. The apparatus of claim 3 , wherein the switching current source comprises:a second current source, coupled to the output node, to increase the voltage swing of the signal by lowering a logical low level of the signal.5. The apparatus of claim 4 , wherein the voltage mode driver includes pull-up and pull-down devices.6. The apparatus of claim 3 , wherein the first current source is operable to inject current claim 3 , to raise the logical high level of the signal claim 3 , from a power supply node to the output node when a pull-up device is on.7. The apparatus of claim 4 , wherein the second current source is operable to sink current claim 4 , to lower the logical low level of the signal claim 4 , from the output node to a ground node when a pull-down device is on.8. The apparatus of claim 3 , wherein the first current source comprises:a first P-transistor, ...

Transmission channel for ultrasound applications

A transmission channel configured to transmit high-voltage pulses and to receive echos of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

Schmitt receiver systems and methods for high-voltage input signals

Presented systems and methods facilitate efficient switching operations for components operating at different voltage level than a received signal voltage level. In one embodiment, the components of a presented system are operable to perform switching operations for signals with a voltage level swing larger than the power rail of the circuit receiving the signals. In one embodiment a system includes an input component, a transition component, a transition point feedback component and an output component. The input component is operable to receive an input signal. The transition component is operable to transition the input signal. The transition point feedback component is operable to adjust a point at which a transition in the input signal occurs in the transition component. The output component is operable to forward an output signal from the transition point feedback component.

Apparatus and methods for digital configuration of integrated circuits

Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.

PREVENTING REVERSE CONDUCTION

In one embodiment, a circuit includes a resistance including first and second terminals. The first terminal of the resistance is coupled to ground. The circuit also includes a first switching element including first, second, and third terminals. The first terminal of the first switching element is coupled to an output of an integrated circuit and the second terminal of the first switching element is coupled to a voltage supply of the integrated circuit. Additionally, the circuit includes a second switching element including first, second, and third terminals. The first terminal of the second switching element is coupled to an enable input of the integrated circuit. Furthermore, the second terminal of the second switching element is coupled to the third terminal of the first switching element and to the second terminal of the resistance. Moreover, the third terminal of the second switching element is coupled to the ground.

Voltage level shift circuit for multiple voltage integrated circuits

A voltage level shift circuit comprises a first pair of transistors and a second pair of transistors. A first transistor of the second pair of transistors is coupled with an input signal terminal. A second transistor of the transistors of the second pair of transistors is coupled with an inverted input signal terminal. The transistors of the second pair of transistors are cross-coupled with the transistors of the first pair of transistors. The voltage level shift circuit also comprises a third pair of transistors. The transistors of the third pair of transistors are coupled with the transistors of the first pair of transistors and the transistors of the second pair of transistors. A first transistor of the third pair of transistors is directly coupled with an output signal terminal and second transistor of the third pair of transistors is directly coupled with an inverted output signal terminal.

Output buffer circuit controlling slew slope and source driver comprising the same and method of generating the source drive signal thereof

An output buffer circuit is provided. The output buffer circuit includes a fast slew rate (FSR) controller that detects a transition duration of an input voltage, to adjust a magnitude of a detection current generated in the detected transition duration based on information on a slew slope, and to generate a slew rate control signal as the adjustment result, and an output buffer that outputs the input voltage as a source drive signal having a slew rate or a slew slope, which is selected, in response to the slew rate control signal.

System and Method for a Pre-Driver Circuit

A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch. 1. A circuit comprising:a driver having an input terminal and an output terminal;a semiconductor switch having a first terminal and a second terminal, the first terminal of the semiconductor switch coupled to the output terminal of the driver; and the semiconductor switch and the capacitance element comprise a variable capacitance,', the variable capacitance provides a capacitance of substantially zero during a first portion of a data transition in the output terminal of the driver from a first state to a second state, and', 'the variable capacitance provides a non-zero capacitance during a second portion of a data transition in the output terminal of the driver from the first state to the second state., 'the variable capacitance is controlled such that'}], 'a capacitance element coupled between the second terminal of the semiconductor switch and a power supply terminal, wherein'}2. The circuit of claim 1 , wherein the semiconductor switch comprises a transistor and the capacitance element is a capacitor.3. The circuit of claim 1 , wherein the semiconductor switch comprises a p-type transistor and the driver is an inverting driver.4. The circuit of claim 1 , wherein the first state represents a 1 and the second state represents a 0. ...

HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array. 1. (canceled)2. An integrated circuit comprising:a substrate;a base layer formed on the substrate, the base layer comprising a decoder formed with a plurality of transistors configured to operate within a first voltage range; and a plurality of conductive array lines; and', 'a plurality of re-writable two-terminal memory cells formed at intersections of the plurality of conductive array lines, the plurality of re-writable two-terminal memory cells configured to operate within a second voltage range, wherein the first voltage range is smaller than the second voltage range., 'a cross-point memory array formed above the base layer, the cross-point memory array comprising3. The integrated circuit of claim 2 , wherein the plurality of conductive lines comprises a plurality of X-line conductive array lines and a plurality of Y-line conductive array lines.4. The integrated circuit of claim 3 , wherein each of the plurality of re-writable two-terminal memory cells comprises a first terminal electrically coupled with one of the plurality of X-line conductive array lines and second terminal electrically coupled with one of the plurality of Y-line conductive array lines.5. The integrated circuit of claim 4 , wherein the base layer further comprises:an X-line decoder including a first subset of the plurality of ...

APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error. 1. An apparatus , comprising: a delay generator circuit configured to provide a start signal and further configured to provide a stop signal following the start signal after one cycle of the input clock signal;', 'a first delay line coupled to the delay generator circuit and configured to delay the start signal through a plurality of first delay stages;', 'a delay control logic circuit coupled to the delay generator circuit and the first delay line, the delay control logic configured to activate the first delay line to delay the start signal, and the delay control logic further configured to determine a number of first delay stages of the plurality of first delay stages through which the start signal propagates responsive to the stop signal and to provide control signals representing the number of first delay stages of the plurality of delay stages;', 'a second delay line coupled to the delay control logic and configured to delay the input clock signal through a plurality of second delay stages to provide the second clock signal, a number of second delay stages of ...

HIGH SPEED VOLTAGE LEVEL SHIFTER

In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain. 1. A voltage level shifter , comprising:a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output; anda second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate;wherein the first and second NOR gates are powered by a supply voltage of the second power domain.2. The voltage level shifter of claim 1 , wherein each of the first and second input signals has a voltage range approximately equal to a first voltage range claim 1 , the enable signal has a voltage range approximately equal to a second voltage range claim 1 , and the second voltage range is greater than the first voltage range.3. The voltage level shifter of claim 2 , wherein the output of each of the first and second NOR gates has a voltage range approximately equal to the second voltage range.4. The voltage level shifter of claim 1 , wherein the first and second input signals are complementary.5. The ...

HIGH SPEED VOLTAGE LEVEL SHIFTER

In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground. 1. A voltage level shifter , comprising:a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain;a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node;an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor; anda first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.2. The voltage level shifter of claim 1 , wherein the inverter is powered by the supply voltage of the second power domain.3. The voltage level shifter of claim 1 , wherein the input signal has a voltage range that is at least 20 percent lower than the supply voltage of the second power domain.4. The voltage level shifter of claim 1 , further comprising an enable circuit configured to receive an enable signal in the second power domain claim 1 , to enable the voltage level shifter when the enable signal has a first logic state claim 1 , and to disable the voltage level shifter when the enable signal has a second ...

APPARATUS FOR PROVIDING A SHARED REFERENCE DEVICE

Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time. 1. A system comprising:a memory;a reference device;a processor coupled to the memory and the reference device, the processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.2. The system further comprising:a wireless interface for allowing the processor to communicatively couple to another device.3. The system of claim 1 , wherein the processor includes logic to provide a valid token to one of the circuit units of the plurality to cause that circuit unit to electronically couple with the reference device.4. The system of claim 3 , wherein the logic to provide an invalid token to other circuit units to cause the other circuit units to electronically uncouple with the reference device.5. The system of claim 1 , wherein the processor includes logic to issue tokens for the circuit units at a programmable rate to allow each circuit unit to update their calibration code in view of time varying effects.6. The system of claim 1 , wherein the processor includes logic to issue tokens after a preset change in temperature is detected.7. The system of claim 1 , wherein the reference device to calibrate any number of calibration devices in the circuit units such that the processor to use a single pin for calibration purposes.8. The system of ...

GATE STRUCTURE AND METHODS THEREOF

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided. 1. A method of fabricating a semiconductor device , comprising:forming a gate dielectric trench within a substrate;depositing a first dielectric layer within the gate dielectric trench, wherein a top surface of the first dielectric layer is co-planar with a top surface of the substrate;forming a second dielectric layer over the first dielectric layer; andforming a metal gate over the second dielectric layer.2. The method of claim 1 , wherein the forming the gate dielectric trench further includes etching the gate dielectric trench to a first depth claim 1 , and wherein the first depth is measured from a plane parallel to the top surface of the substrate to a bottom surface of the gate dielectric trench.3. The method of claim 1 , wherein the forming the gate dielectric trench further includes forming the gate dielectric trench having a first width along the plane parallel to the top surface of the substrate claim 1 , and forming the gate dielectric trench having a second width along a plane parallel to the bottom surface of the gate dielectric trench.4. The method of claim 3 , wherein the second width is less than the first width.5. The method of claim 1 , further ...

Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

BIAS CIRCUITRY AND BIASING METHOD

A bias circuitry includes a simulation circuit and a level shifter circuit. The simulation circuit is configured to simulate circuit architecture of a processing circuitry, in which the processing circuitry is biased by a bias signal, in order to generate output signals according to input signals. The level shifter circuit is configured to increase a voltage difference between a first node and a second node of the simulation circuit, in which the first node is for tracking an output common mode voltage of the output signals, and the second node is for outputting the bias signal. 1. A bias circuitry , comprising:a simulation circuit configured to simulate a circuit architecture of a processing circuitry, wherein the processing circuitry is biased by a bias signal, in order to generate a plurality of output signals according to a plurality of input signals; anda level shifter circuit configured to increase a voltage difference between a first node and a second node of the simulation circuit, wherein the first node is configured to track an output common mode voltage of the output signals, and the second node is configured to output the bias signal.2. The bias circuitry of claim 1 , wherein the processing circuitry comprises an input pair circuit and a first transistor claim 1 , the input pair circuit receives the input signals and generates the output signals claim 1 , the first transistor generates a first current according to the bias signal to bias the input pair circuit claim 1 , and the simulation circuit comprises:a second transistor coupled to the first node, and configured to simulate the input pair circuit, wherein a control terminal of the second transistor is configured to receive a common mode voltage related to the input signals; anda third transistor coupled between the second transistor and a ground, and configured to simulate the first transistor, wherein a control terminal of the third transistor is coupled to the second node.3. The bias circuitry of ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter. 1. A semiconductor device comprising:an input/output (IO) signal receiver circuit; anda latch circuit connected to the IO signal receiver circuit, a first inverter configured to output a first signal based on an input signal received from the IO signal receiver circuit,', 'a second inverter configured to output a first clock signal based on a first strobe signal,', 'a third inverter configured to output a second clock signal based on a second strobe signal which is an inversion signal of the first strobe signal,', 'a first clock generation circuit which is connected to an output terminal of the second inverter and is configured to generate a third clock signal from the first clock signal, wherein logical level transitions in the third clock signal are delayed with respect to the first clock signal and are completed in a shorter amount of time than the first clock signal,', 'a second clock generation circuit which is connected to an output terminal of the third inverter and is configured to generate a fourth clock signal from the second clock signal, wherein logical level transitions in the fourth clock signal are delayed with ...

GATE CONTROL FOR A TRISTATE OUTPUT BUFFER

A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal. 1. A gate control circuit for a tristate output buffer operating in a first voltage domain , the gate control circuit comprising:a pull-up circuit coupled between an upper rail and a first gate control signal;a pull-down circuit coupled between a lower rail and a second gate control signal; anda gate isolation switch coupled between the first gate control signal and the second gate control signal, the gate isolation switch comprising a first PMOS transistor coupled in parallel with a first NMOS transistor, the first NMOS transistor being controlled by a first enable signal and the first PMOS transistor being controlled by a second enable signal.2. The gate control circuit for a tristate output buffer as recited in wherein when the tristate output buffer is enabled claim 1 , the first enable signal is high and the second enable signal is low and when the tristate output buffer is in high impedance claim 1 , the first enable signal is low and the second enable signal is high.3. The gate control circuit for a tristate output buffer as recited in wherein the gate isolation switch further comprising a second PMOS transistor coupled in parallel with a second NMOS transistor claim 2 , the second NMOS transistor being controlled by the first enable signal and the second PMOS transistor being controlled by the second enable signal claim 2 , the first PMOS transistor and ...

Low Power Logic Circuit

The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT. 1. A logic circuit comprising:a first thin film transistor (TFT) having a first drain, a first gate, and a first source;a second TFT having a second drain, a second gate, and a second source;a third TFT having a third drain, a third gate, and a third source; anda fourth TFT having a fourth drain, a fourth gate, and a fourth source,wherein the second source, the fourth gate, the third source, and the first drain form a first node,wherein the fourth drain and the second drain form a second node,wherein the fourth source, the second gate, and the third drain form a third node, andwherein the third gate and the first gate form a fourth node.2. The logic circuit according to claim 1 , wherein the first source forms a fifth node with a first power supply.3. The logic circuit according to claim 2 , wherein a second power supply additionally forms the second node with the fourth drain and the second drain.4. The logic circuit according to claim 3 , wherein the first TFT is the only current path from the second power supply to the first power supply through the logic circuit.5. The logic circuit according to claim 3 , wherein the first power supply is ground and the second power supply is a positive supply voltage.6. The logic circuit according to claim ...

SEMICONDUCTOR DEVICE

Path transistor malfunction is reduced. A path gate circuit includes transistors MP, MW, and MC. The transistor MP functions as a path transistor that connects a signal line INL to a signal line OUTL. The transistor MW connects a signal line BL for inputting a signal for setting the on or off state of the transistor MP and a node SN (gate of the transistor MP). When a high-level potential is written to the node SN, the potential of BL is set higher than a normal high-level potential if the potential of INL is high. Thus, even when the potential of the node SN is dropped in accordance with transition of INL from a high level to a low level, the potential drop does not influence the operation of the transistor MP because a high potential is written in advance. 1. A semiconductor device comprising: a first transistor between an input signal line and an output signal line, one of a source and a drain of the first transistor being electrically connected to the input signal line; and', 'a second transistor between a bit line and a gate of the first transistor; and, 'a path gate circuit comprisinga circuit being electrically connected to the gate of the first transistor through the second transistor and the bit line,wherein the circuit is configured to supply a first signal at a first high level when a potential of the input signal line is at a low level, andwherein the circuit is configured to supply a second signal at a second high level when the potential of the input signal line is at a high level, the second high level being higher than the first high level.2. The semiconductor device according to claim 1 ,wherein the other of the source and the drain of the first transistor is electrically connected to the output signal line,wherein one of a source and a drain of the second transistor is electrically connected to the bit line,wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor, ...

Electrostatic Discharge Protection for Level-Shifter Circuit

In some embodiments, a method includes providing an input voltage to a level-shifting circuit, where the input voltage is in a first power domain, shifting the input voltage to an output voltage using the level-shifting circuit, where the output voltage is in a second power domain different from the first power domain, and where the level-shifting circuit is coupled to power supply voltages in the second power domain. The method further includes in response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain. 1. A method comprising:providing an input voltage to a level-shifting circuit, wherein the input voltage is in a first power domain;shifting the input voltage to an output voltage using the level-shifting circuit, wherein the output voltage is in a second power domain different from the first power domain, wherein the level-shifting circuit is coupled to power supply voltages in the second power domain; andin response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain.2. The method of claim 1 , wherein the first transistor is an N-type transistor claim 1 , wherein the turning off comprises supplying a reference low voltage level of the second power domain to a gate of the first transistor.3. The method of claim 2 , further comprising detecting the ESD event using a control circuit.4. The method of claim 3 , wherein the control circuit is coupled to the power supply voltages of the second power domain claim 3 , wherein an output of the control circuit is coupled to the gate of the first transistor claim 3 , and wherein the control circuit outputs a reference low voltage level of the second power domain during an ESD event.5. The method of claim 4 , wherein the control circuit ...

VOLTAGE LEVEL SHIFTER

A voltage level shifter includes: in stages a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit. 1. A voltage level shifter comprising:a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage;a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal;a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; anda bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull- ...

CONFIGURABLE POWER DOMAIN AND METHOD

Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication). 1. An apparatus comprising:a first circuit configured and arranged to operate under a first power domain having a first voltage range;a second circuit configured and arranged to operate under a second power domain having a second voltage range; and detect a voltage range of the first power domain,', 'detect a voltage range of the second power domain, and', convert a voltage level of each communication received from one of the first and second circuits to a voltage level of the other one of the first and second circuits in response to the detected voltage ranges being different, and thereafter providing the communication to the other one of the first and second circuits, and', 'pass each communication directly between the first and second circuits in response to the detected voltage ranges being the same., 'for communications between the first and second circuits,'}], 'a level shifter circuit connected to the first circuit and to the second circuit, the level shifter circuit being configured and arranged to2. The apparatus of claim 1 , wherein the level shifter circuit is configured and arranged to:in a first ...

I/o cell

An I/O cell includes a reference output circuit that has a reference output transistor, connected to an output terminal, and has a reference pre-buffer, the reference pre-buffer driving the reference output transistor according to an input signal of the input terminal; adjustment output circuits that have an adjustment output transistor, connected to the output terminal and connected in parallel with the reference output transistor, and have an adjustment pre-buffer, the adjustment pre-buffer driving the adjustment output transistor according to the input signal; and a gate voltage detection control circuit that monitors all of gate voltages applied to the output transistors included in the reference output circuit and the adjustment output circuit. The gate voltage detection control circuit generates a timing when all of the output transistors are turned OFF when switching the H/L level of the output current to the load according to the change of the input signal.

APPARATUSES AND METHODS FOR PARTIAL BIT DE-EMPHASIS

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion. 1. An apparatus comprising:an external terminal; and receive a first signal having a first logical value,', 'receive a second signal following the first signal, the second signal having a second logical value different from the first logical value, and', 'drive, in response to receiving the second signal, the external terminal from a first voltage to a second voltage by way of a third voltage, wherein the third voltage is a de-emphasized first voltage based at least in part on a de-emphasis time., 'an output driver coupled to the external terminal, the output driver configured to2. The apparatus of claim 1 , wherein the output driver de-emphasizes the first voltage for two bit periods.3. The apparatus of claim 1 , further comprising a variable delay circuit to introduce a delay interval claim 1 , wherein the delay interval determines the de-emphasis time.4. The apparatus of claim 3 , wherein the delay interval comprises a half bit period to produce a half bit period de-emphasis.5. The apparatus of claim 3 , wherein the variable delay circuit is configured to receive an input signal having first and second logic values claim 3 , and generate a delayed signal that is delayed relative to ...

COMPENSATION CIRCUIT FOR USE WITH INPUT BUFFER AND METHOD OF OPERATING THE SAME

A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal. 1. A compensation circuit for use with an input buffer , the compensation circuit comprising:an input buffer configured to amplify an input signal and output a compensated signal; anda process detector including a replica of the input buffer, the process detector configured to output at least one comparison signal indicating a variation in the input buffer,wherein the input buffer is configured to control an output signal based on the at least one comparison signal.2. The compensation circuit of claim 1 , wherein the input buffer is configured to control a bias voltage of an output terminal according to the at least one comparison signal.3. The compensation circuit of claim 1 , wherein the input buffer comprises an input buffer differential amplifier configured to receive and differentially amplify a reference voltage and the input signal claim 1 , and the replica comprises a replica buffer differential amplifier including two input terminals to which the reference voltage is applied claim 1 , the replica buffer differential amplifier configured to output a replica voltage.4. The compensation circuit of claim 3 , wherein the input buffer further comprises an output adjust unit configured to decrease a bias voltage of an output terminal when the variation is slow-fast (SF) and to increase the bias voltage of the output terminal when the variation is fast-slow (FS).5. The compensation circuit of claim 3 , further comprising:a first comparator configured to compare the replica voltage with a first reference voltage and output a first comparison signal according ...

BUFFER CIRCUIT BETWEEN DIFFERENT VOLTAGE DOMAINS

A circuit includes a first inverter and a second inverter. The first inverter is coupled to an input terminal. The input terminal receives an input signal varying in a first voltage domain. The second inverter is coupled between the first inverter and an output terminal. The second inverter generating an output signal varying in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in the second voltage domain. 1. A circuit , comprising:a first inverter, coupled to an input terminal, the input terminal receiving an input signal varying in a first voltage domain from a negative supply level to a first positive supply level; anda second inverter, coupled between the first inverter and an output terminal, the second inverter generating an output signal varying in a second voltage domain from the negative supply level to a second positive supply level, a first PMOS transistor biased by a first input tracking signal generated from the input signal, the first input tracking signal varies in a third voltage domain from a reference level to the first positive supply level, the reference level is higher than the negative supply level; and', 'a first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varies in the second voltage domain., 'wherein the first inverter comprising2. The circuit of claim 1 , wherein a first voltage difference window of the first voltage domain is larger than a second voltage difference window of the second voltage domain claim 1 , and the first voltage difference window is larger than a third voltage difference window of ...

DIFFERENTIAL SIGNAL TRANSMISSION CIRCUIT

There is provided a differential signal transmission circuit that includes a first output terminal, a second output terminal connected to the first output terminal via a load resistor, a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal, a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal, a high-side pre-driver configured to drive the high-side transistor, a low-side pre-driver configured to drive the low-side transistor, a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor, and a second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor. 1. A differential signal transmission circuit , comprising:a first output terminal;a second output terminal connected to the first output terminal via a load resistor;a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal;a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal;a high-side pre-driver configured to drive the high-side transistor;a low-side pre-driver configured to drive the low-side transistor;a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor; anda second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor.2. The differential signal transmission circuit of claim 1 , wherein the first resistance part and the second resistance part are devices having a same composition.3. The differential signal transmission circuit of claim 2 , wherein the first resistance part and the ...