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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка

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Применить Всего найдено 4126. Отображено 100.

29-03-2012 дата публикации

Level shifter circuit, scanning line driver and display device

Номер: US20120075279A1

Автор: Tatsuya Ishida

Принадлежит: Individual

An object of the present invention is to achieve a scanning line drive device which allows further reduction of circuit scale and production costs. A gate driver ( 100 ) of the present invention includes: a shift register circuit ( 1 ) including g latch circuits ( 21 ) to ( 2 g ); g selection circuits ( 8 ); and g level shifter circuits ( 3 ). A level shifter circuit ( 3 ) of an output drive circuit (st 1 ) receives a pulse ( 61 ) from a NAND circuit ( 6 ) of a selection circuit ( 8 ) at its input terminal (N 1 ); a pulse ( 71 ) from a NAND circuit ( 7 ) of the selection circuit ( 8 ) at its input terminal (N 2 ); and a pulse (Q 1 ) from a latch circuit ( 21 ) at its input terminal (N 3 ). The level shifter circuit ( 3 ) of the output drive circuit (st 1 ) outputs a voltage signal obtained by converting the voltage level of the pulse ( 61 ) from its output terminal (O 1 ); and a voltage signal obtained by converting the voltage level of the pulse ( 71 ) from its output terminal (O 2 ).

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Номер записи: 1

26-07-2012 дата публикации

Buffer circuit having switch circuit capable of outputting two and more different high voltage potentials

Номер: US20120187982A1

Автор: Tatsufumi Kurokawa

Принадлежит: Renesas Electronics Corp

A buffer circuit includes a first node receiving a first voltage, a second node receiving a second voltage lower than the first voltage, a third node, an output node driving the first voltage and the second voltage, a first transistor coupled between the first node and the output node, a second transistor coupled between the second node and the output node, one end of the second transistor being connected to the second node, another end of the second transistor being connected to the third node, and a switch circuit coupled between the output node and the third node. Both of the first transistor and the switch circuit include a transistor having a first breakdown voltage. The second transistor has a second breakdown voltage being different from the first breakdown voltage.

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Номер записи: 2

06-09-2012 дата публикации

Receiver circuit

Номер: US20120223759A1

Автор: Chao-Yen Huang, Sheng-Tsai Huang, Wen-Tai Wang

Принадлежит: Global Unichip Corp, Taiwan Semiconductor Manufacturing Co TSMC Ltd

A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.

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Номер записи: 3

13-09-2012 дата публикации

Output circuit and output control system

Номер: US20120229164A1

Автор: Hiroyuki Ideno, Takashi Taguchi

Принадлежит: Toshiba Corp

An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

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Номер записи: 4

13-09-2012 дата публикации

Output stage circuit for outputting a driving current varying with a process

Номер: US20120229174A1

Автор: Ching-Ying Hsu, Chun Shiah, Hao-Jan Yang

Принадлежит: Individual

An output stage circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, and a current source. A voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor is a first voltage minus a voltage drop between a first terminal and a second terminal of the first P-type metal-oxide-semiconductor transistor. The N-type metal-oxide-semiconductor transistor is coupled between the third terminal of the first P-type metal-oxide-semiconductor transistor and the current source. A second terminal of the second P-type metal-oxide-semiconductor transistor is coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor. When a second terminal of the N-type metal-oxide-semiconductor transistor receives a kick signal, a driving current flowing through the second P-type metal-oxide-semiconductor transistor is relevant to the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor.

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Номер записи: 5

25-10-2012 дата публикации

Clamping circuit to a reference voltage for ultrasound applications

Номер: US20120268092A1

Автор: Antonio Ricciardo, Davide Ugo Ghisu, Sandro Rossi

Принадлежит: STMICROELECTRONICS SRL

A clamping circuit includes a clamping core connected to an output terminal and having a central node connected to a voltage reference and at least one first and one second clamp transistor, connected to the central node and having respective control terminals, the clamping core being also connected at the input to a low voltage input driver block. The clamping core includes a first switching off transistor connected to the output terminal and to the first clamp transistor, as well as a second switching off transistor connected to the output terminal and to the second clamp transistor.

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Номер записи: 6

13-12-2012 дата публикации

Level shift circuit

Номер: US20120313686A1

Автор: Kazutaka KIKUCHI

Принадлежит: Renesas Electronics Corp

A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

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Номер записи: 7

28-03-2013 дата публикации

Semiconductor device

Номер: US20130076395A1

Автор: Mi-Hye Kim

Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code, and an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code.

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Номер записи: 8

18-04-2013 дата публикации

Device

Номер: US20130093492A1

Автор: Yoshiro Riho

Принадлежит: Elpida Memory Inc

A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

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Номер записи: 9

25-04-2013 дата публикации

Cml to cmos conversion circuit

Номер: US20130099822A1

Автор: Yongfeng Cao

Принадлежит: Individual

The present invention provides a CML to CMOS conversion circuit comprising a first differential unit, a second differential unit, and an output unit. The output unit comprises a series connection of a first inverter and a second inverter, wherein, a resistor is connected with the first inverter in parallel. The CML to CMOS conversion circuit of the present invention omits the amplifier in the conventional circuit and reduces the delay time to 34 ps, which is almost half of the delay time of 64 ps in the conventional circuit, and thus provides more clock delay redundancy for the high speed parallel-serial conversion circuit.

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Номер записи: 10

25-04-2013 дата публикации

Output driver, devices having the same, and ground termination

Номер: US20130099823A1

Автор: David Moon, Min Su Ahn, Yong Cheol Bae, Young Jin Jeon

Принадлежит: Individual

An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.

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Номер записи: 11

23-05-2013 дата публикации

DRIVING CIRCUIT WITH ZERO CURRENT SHUTDOWN AND A DRIVING METHOD THEREOF

Номер: US20130127496A1

Автор: Tseng Jaime

Принадлежит: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD

Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current. 1. A driving circuit comprising:a) a linear regulating circuit configured to receive an input voltage source, and to provide an output voltage based on a first current;c) a first power switch configured to receive said output voltage of said linear regulating circuit and an external enable signal, and to generate an internal enable signal configured to drive a logic circuit; andd) a start-up circuit configured to receive said external enable signal at a gate of a second power switch, wherein when said external enable signal is lower than a threshold voltage that is related to said second power switch, said start-up circuit is configured to disable said first current and said driving circuit, and when said external enable signal is higher than said threshold voltage, said start-up circuit is configured to a generate said first current and enable said driving circuit.2. The driving circuit of claim 1 , further comprising a first current mirror coupled to said input voltage source claim 1 , said linear regulating circuit claim ...

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Номер записи: 12

13-06-2013 дата публикации

SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF

Номер: US20130147517A1

Автор: Shon Kwan-Su, Song Taek-Sang

Принадлежит: SK HYNIX INC.

A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signals, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal. 1. A semiconductor device comprising:a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock;a driving signal generation unit configured to decide logic levels of a first driving signal and a second driving signal based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first driving signal and the second driving signal, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first driving signal and the second driving signal; andan output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal.2. The semiconductor device of claim 1 , wherein the driving signal generation unit comprises:a first driving signal output section configured to decide the logic level of the first driving signal in response to the input data, to determine transition to a second logic level based on the source ...

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Номер записи: 13

27-06-2013 дата публикации

LEVEL SHIFT CIRCUIT AND DRIVE CIRCUIT OF DISPLAY DEVICE

Номер: US20130162294A1

Автор: Henmi Isao, Miyazaki Kiyoshi, SAEKI Yutaka

Принадлежит: RENESAS ELECTRONICS CORPORATION

In a level shift circuit, input signals are input into gates of a first and a second MOS transistors whose sources are coupled to a first supply voltage VSS. Gates of a third and a fourth MOS transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first MOS transistors. A first voltage generation circuit is coupled between the drains of the first and the third MOS transistors, and a second voltage generation circuit is coupled between the drains of the second and the fourth MOS transistors. The gate of the fifth MOS transistor is coupled to a connection node NDB, and the source of the fifth MOS transistor is coupled to the second supply voltage. 1. A level shift circuit comprising:a first MOS transistor of a first conductivity type, into a gate of which an input signal having an amplitude between a third supply voltage indicating a voltage between a first supply voltage and a second supply voltage and the first supply voltage is input;a second MOS transistor of the first conductivity type, into a gate of which an inverted input signal which is an inverted signal of the input signal, is input, sources of the first and the second MOS transistors being commonly coupled to the first supply voltage;a third MOS transistor of a second conductivity type complementary to the first conductivity type, whose gate is coupled to a drain of the second MOS transistor;a fourth MOS transistor of the second conductivity type, whose gate is coupled to a drain of the first MOS transistor, sources of the third and the fourth MOS transistors being commonly coupled to the second supply voltage;a first voltage generation circuit coupled between the drain of the first MOS transistor and a drain of the third MOS transistor;a second voltage generation circuit coupled between the drain of the second MOS transistor and a drain of the fourth MOS transistor;a fifth MOS transistor of the second conductivity type, whose gate is coupled to a ...

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Номер записи: 14

18-07-2013 дата публикации

3x input voltage tolerant device and circuit

Номер: US20130181768A1

Автор: Guang-Cheng Wang, Ming-Hsin Yu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltage at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

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Номер записи: 15

25-07-2013 дата публикации

TECHNIQUES FOR SWITCHING BETWEEN AC-COUPLED CONNECTIVITY AND DC-COUPLED CONNECTIVITY

Номер: US20130187699A1

Автор: SLEZAK Yaron

Принадлежит: TRANSWITCH CORPORATION

A circuit for switching between an AC-coupled connectivity and DC-coupled connectivity of a multimedia interface. The circuit comprises a current source connected in series to a wire of the multimedia interface and a coupling capacitor; and a termination resistor connected to the current source and to the coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, wherein the current source and the termination resistor allows the setting of voltage levels of signals received at the sink line receiver to voltage levels defined by the multimedia interface thereby to switch to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates. 1. A circuit for switching between an AC-coupled connectivity and a DC-coupled connectivity of a multimedia interface , comprising:a first current source connected in series to a first wire of the multimedia interface and a first tap of a first coupling capacitor; anda first termination resistor connected to the first current source and to the first tap of the first coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, thereby the circuit switches to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates, wherein the sink line receiver is connected to the first tap of the first coupling capacitor and the source line driver is connected to a ...

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Номер записи: 16

29-08-2013 дата публикации

PROGRAMMABLE LOGIC SWITCH

Номер: US20130222011A1

Автор: KUSAI Haruka, MATSUMOTO Mari, Oda Masato, Sakuma Kiwamu, TATSUMURA Kosuke, Yasuda Shinichi, Zaitsu Koichiro

Принадлежит: KABUSHIKI KAISHA TOSHIBA

One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory. 1. A programmable logic switch comprising: a first channel region provided between a first source and a first drain;', 'a first insulating film formed on the first channel region;', 'a first charge storage film formed on the first insulating film;', 'a second insulating film formed on the first charge storage film; and', 'a first gate electrode formed on the second insulating film;, 'a first nonvolatile memory having a second channel region provided between a second source and a second drain;', 'a third insulating film formed on the second channel region;', 'a second charge storage film formed on the third insulating film;', 'a fourth insulating film formed on the second charge storage film; and', 'a second gate electrode formed on the fourth insulating film;, 'a second nonvolatile memory havinga first line connected to the first gate electrode and to the second gate electrode;a second line connected to the first source;a third line connected to the first drain and to the second drain;a fourth line connected to the second source;a substrate electrode through which a substrate voltage is applied to a well, the first nonvolatile memory and the second nonvolatile memory being formed in the well;one or more first logic transistors connected to the third line, each first logic transistor being ...

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Номер записи: 17

29-08-2013 дата публикации

Semiconductor integrated circuit

Номер: US20130222038A1

Автор: Hiroyuki Kuge

Принадлежит: Renesas Electronics Corp

A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition.

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Номер записи: 18

29-08-2013 дата публикации

INPUT BUFFER

Номер: US20130222039A1

Автор: LEE Dong Uk

Принадлежит: SK HYNIX INC.

An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal. 1. An input buffer comprising:a first amplification block configured to be driven by an external voltage and differentially amplify an input signal and a reference voltage in response to a bias voltage generated from the reference voltage, and generate first and second differential signals; anda second amplification block configured to be driven by an internal voltage and differentially amplify the first and second differential signals and generate an output signal.2. The input buffer of claim 1 , wherein the levels of the first and second differential signals are adjusted by the bias voltage.3. The input buffer of claim 1 , wherein the first amplification block comprises:a first switch unit configured to be turned on according to the bias voltage and control driving of a first node according to the external voltage; anda differential amplification unit coupled between the first node and a second node and configured to differentially amplify the input signal and the reference voltage and generate the first and second differential signals.4. The input buffer of claim 3 , wherein the differential amplification unit comprises:a load section coupled between the first node and a third node through which the first differential signal is outputted, and the load section coupled between the first node and a fourth ...

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Номер записи: 19

05-09-2013 дата публикации

FLOATING GATE DRIVER WITH BETTER SAFE OPERATION AREA AND NOISE IMMUNITY, AND METHOD FOR LEVEL SHIFTING A SWITCH SIGNAL

Номер: US20130229207A1

Автор: CHEN Isaac Y., TANG Chien-Fu, TSENG Pei-Kai

Принадлежит: RICHTEK TECHNOLOGY CORPORATION

A floating gate driver includes a level shifter to transmit a set signal and a reset signal to a first output terminal and a second output terminal, respectively. The level shifter includes a first high-voltage transistor, a first current limiter and a first input transistor connected in series between the first output terminal and a ground terminal, and a second high-voltage transistor, a second current limiter and a second input transistor connected in series between the second output terminal and the ground terminal, and the first and second high-voltage transistors are remained on. With this arrangement, the level shifter can transmit signals from low side to high side under better safe operating area and has better noise immunity. 1. A floating gate driver , comprising:an edge pulse generator detecting a rising edge and a falling edge of a switch signal to trigger a set signal and a reset signal, respectively;a level shifter having a first input transistor and a second input transistor connected to the edge pulse generator for transmitting the set signal and the reset signal to a first output terminal and a second output terminal to generate a first negative voltage pulse and a second negative voltage pulse, respectively; anda logic regeneration circuit connected to the first output terminal and the second output terminal, responsive to the first negative voltage pulse and the second negative voltage pulse to generate a signal as being level shifted from the switch signal; a first high-voltage transistor and a second high-voltage transistor connected to the first output terminal and the second output terminal, respectively, and remained on;', 'a first current limiter connected between the first high-voltage transistor and the first input transistor; and', 'a second current limiter connected between the second high-voltage transistor and the second input transistor., 'wherein the level shifter further comprises2. The floating gate driver of claim 1 , wherein ...

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Номер записи: 20

19-09-2013 дата публикации

TRANSMISSION CIRCUIT

Номер: US20130241602A1

Автор: SHIROTA Shinichiro

Принадлежит: FUJITSU LIMITED

A transmission circuit includes a first drive part capable of switching to one of an on state that is driven by current and an off state, i.e., a high impedance state in accordance the value of a first input signal; and a first termination resistor part connected in series with the first drive part. The resistance values of the first drive part are switched in accordance with the state of the first drive part. 1. A transmission circuit comprising:a first drive part capable of switching to one of an on state that is driven by current and an off state, that is, a high impedance state in accordance the value of a first input signal; anda first termination resistor part connected in series with the first drive part and the resistance values of which are switched in accordance with the state of the first drive part.2. The transmission circuit according to the claim 1 , further comprising:a second drive part capable of switching to one of an on state that is driven by current and an off state, that is, a high impedance state in accordance the value of a second input signal and configured to enter the off state when the first drive part is in the on state and to enter the on state when the first drive part is in the off state; anda second termination resistor part connected in series with the second drive part and the resistance values of which are switched in accordance with the state of the second drive part.3. The transmission circuit according to claim 2 , whereinthe first termination resistor part has a first base resistor part and a first adjustment resistor part connected in parallel with the first base resistor part and the resistance values of which are switched in accordance with the state of the first drive part, andthe second termination resistor part has a second base resistor part and a second adjustment resistor part connected in parallel with the second base resistor part and the resistance values of which are switched in accordance with the state of the ...

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Номер записи: 21

19-09-2013 дата публикации

Dual Path Level Shifter

Номер: US20130241624A1

Автор: Calanca Neil, Olson Chris

Принадлежит: PEREGRINE SEMICONDUCTOR CORPORATION

Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters. 1. A dual path level shifter comprising:a dual path level shifter input terminal;a dual path level shifter output terminal;a first voltage-to-current converter;a second voltage-to-current converter;a third voltage-to-current converter;a first current-to-voltage converter; anda second current-to-voltage converter,wherein:in a first condition, during operation, an input signal having an input signal level swinging between an input signal low voltage level and an input signal high voltage level is routed from the dual path level shifter input terminal to an input of the first voltage-to-current-converter, from an output of the first voltage-to-current-converter to an input of the second current-to-voltage converter, from an output of the second current-to-voltage converter to an input of the third voltage-to-current converter, from an output of the third voltage-to-current converter to an input of the first current-to-voltage converter and from the output of the first current-to-voltage converter to the dual path level shifter output terminal;in a second condition, during operation, the input signal is routed from the dual path level shifter input terminal to an input of the second voltage-to-current converter, from an output of the second voltage-to-current converter to the input of the first current-to-voltage converter and from the output of first current-to-voltage converter to the dual path level shifter output terminal;during operation in the second condition, no current is flowing through an electrical path defined by the input signal routing of the first condition;the output signal is a replicate of the input signal swinging between an output signal low voltage level and an output signal high voltage level, so that the output signal low/high level is a shifted version of the input signal low/high level ...

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Номер записи: 22

19-09-2013 дата публикации

INTERFACE CIRCUIT

Номер: US20130242664A1

Автор: Koyanagi Masaru, SHIMIZU Yuui, Suematsu Yasuhiro

Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor. 1. An interface circuit comprising:an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor; anda driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.2. The interface circuit according to claim 1 ,wherein the driver circuit is provided with a slew rate control unit which is capable of changing the turn-ON speed of the transistor, and a reset rate control unit which is capable of changing the turn-OFF speed of the transistor.3. The interface circuit according to claim 2 ,wherein the transistor is provided with a first P-channel field-effect transistor and a first N-channel field-effect transistor which is connected to the first P-channel field-effect transistor in series, andthe driver circuit is provided with a P-slew rate control unit which is capable of changing a turn-ON speed of the first P-channel field-effect transistor, a P-reset rate control unit which is capable of changing a turn-OFF speed of the first P-channel field-effect transistor, a N-slew rate control unit which is capable of changing a turn-ON speed of the first N-channel field-effect transistor, and a N-reset rate control unit which is capable of changing a turn-OFF speed of the first N-channel field-effect transistor.4. The interface circuit according to claim 3 , further comprising:a time lag generation circuit which adds a period of time in order to turn off both of the first P-channel field-effect transistor and the first N-channel field-effect transistor at the same time.5. The interface circuit according to claim 4 , further comprising:a level ...

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Номер записи: 23

26-09-2013 дата публикации

SWITCHING ARRANGEMENT, INTEGRATED CIRCUIT COMPRISING SAME, METHOD OF CONTROLLING A SWITCHING ARRANGEMENT, AND RELATED COMPUTER PRORAM PRODUCT

Номер: US20130249616A1

Автор: Priel Michael, Rozen Anton, Seidenwar Yaakov

Принадлежит: FREESCALE SEMICONDUCTOR INC

There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant. 1. A switching arrangement , comprising:a switch comprising a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail, each of said elementary switches being in either one of a closed state and an open state independently of the others; and,a controller adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch, wherein the number of elementary switches in the closed state is variable and wherein the higher is the intensity of the current the higher the number of elementary switches in the closed state.2. The switching arrangement of claim 1 , wherein the controller is further adapted to receive claim 1 , from a load supplied by the second supply rail claim 1 , a current value indication representative of the intensity of the current flowing through the switch claim 1 , and to control the closing or opening of the elementary switches responsive to said current value indication.3. The switching arrangement of claim 1 , wherein the controller comprises a current-sense block adapted to ...

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Номер записи: 24

31-10-2013 дата публикации

Buffering circuit, semiconductor device having the same, and methods thereof

Номер: US20130285702A1

Автор: Jung-Hyun Kim

Принадлежит: MagnaChip Semiconductor Ltd

A multipoint low-voltage differential signaling (mLVDS)receiver of a semiconductor device and a buffering circuit of a semiconductor device, includes: an even-number data buffering unit configured to: sample even-number data from input data, amplify and output the even-number data in a section in which a positive clock is activated, and latch the even-number data in a section in which the positive clock is inactivated, and an odd-number data buffering unit configured to: sample odd-number data from the input data, amplify and output the odd-number data in a section in which a negative clock is activated, and latch the odd-number data in a section in which the negative clock is inactivated.

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Номер записи: 25

31-10-2013 дата публикации

ASYMMETRICAL BUS KEEPER

Номер: US20130285703A1

Автор: MCGINN John Douglas

Принадлежит:

Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level. 2. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a single p-channel transistor wherein a gate of the p-channel transistor is connected to the input node of the asymmetrical inverter stage claim 1 , a source of the p-channel transistor is connected to a positive voltage supply level claim 1 , and a drain of the p-channel transistor is connected to the output node of the asymmetrical inverter stage.3. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a p-channel transistor having a first drive and an n-channel transistor having a second drive claim 1 , the p-channel and n-channel transistors being oriented in an inverter configuration claim 1 , wherein the first drive is at least one order of magnitude larger than the second drive.4. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level and the asymmetrical ...

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Номер записи: 26

31-10-2013 дата публикации

POWER STAGE

Номер: US20130285713A1

Автор: Acar Mustafa, Nowak Katarzyna

Принадлежит:

A power stage has a differential output stage driven by one or more buffer stages The buffer stages are implemented as high and low side buffers each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS. 1. An apparatus , comprising:an input circuit configured and arranged to provide a drive signal in response to receiving an input voltage;a first set of isolation capacitive couplers provided with the drive signal from the input circuit;at least one differential buffer stage, having a high side buffer stage and a low side buffer stage, configured and arranged to receive the drive signal from the first set of isolation capacitive couplers; andan output stage, between a high voltage rail and a low voltage rail, configured and arranged to drive an isolation transformer through a second set of isolation capacitive couplers in response to the drive signal received from the at least one differential buffer stage.2. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a first buffer stage having an inverting output that drives an inverting input of a second buffer stage.3. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a self-biassing bias line connecting parallel ports of a first buffer stage and a second buffer stage and providing an intermediate voltage between the high side line and the low side line.4. The apparatus of claim 1 , wherein the input circuit is further configured and arranged between the low voltage rail and a digital power supply voltage.5. The apparatus of claim 1 , wherein the input circuit provides an input signal that includes a sinusoidal input voltage.6. The apparatus of claim 1 , wherein the at least one differential buffer stage includes a plurality of transistors which are each implemented with an isolated well.7. The apparatus of claim 1 , wherein the at least one differential buffer stage ...

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Номер записи: 27

07-11-2013 дата публикации

Sensor Connection Circuit

Номер: US20130293277A1

Автор: Boulin Martial

Принадлежит:

A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train. 1. A sensor connection circuit comprising:an input node;an output node, the output node being sampled by an acquisition circuit;a comparator connected between the input node and the output node; anda switching element connected between the input node and a ground node, the switching element being controlled by a control signal, wherein the sampling of the output node is synchronized with the control signal.2. The sensor connection circuit of further comprising a level adapter connected between comparator and the output node.3. The sensor connection circuit of claim 1 , wherein the control signal has a duty cycle greater than 10%.4. The sensor connection circuit of claim 1 , wherein the comparator comprises two inputs claim 1 , a first input connected to the input node claim 1 , and a second input connected to a reference voltage.5. The sensor connection circuit of further comprising a current-limiting element connected in series with the switching element.6. The sensor connection circuit of claim 1 , wherein the acquisition circuit comprises a microcontroller.7. The sensor connection circuit of further comprising: a visual indicator; and', 'a second switching element, the second switching element connected in parallel with the visual indicator, the second switching element being controlled by an output of the comparator., 'an indicator circuit connected in series with the switching element, the indicator circuit comprising8. An integrated circuit comprising: an ...

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Номер записи: 28

05-12-2013 дата публикации

Voltage compensated level-shifter

Номер: US20130321026A1

Автор: Alok SHAH, Pravas Pradhan, Venkatesh Rao

Принадлежит: Intel Corp

Described herein is a voltage compensated level-shifter with nearly constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels. The voltage compensated level-shifter comprises a first inverter to receive an input signal for level shifting from a first power supply level to a second power supply level, and to generate a first inverted signal, the first inverter operating on the first power supply level; a second inverter to receive the input signal and to generate a second inverted signal, the second inverter operating on the second power supply level; and a NOR logical gate to receive the first and second inverted signals and to generate an output signal, the NOR logical gate operating on the second power supply level, wherein the output signal is level shifted to the second power supply level.

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Номер записи: 29

05-12-2013 дата публикации

Circuit Arrangements and Methods of Operating the Same

Номер: US20130321027A1

Автор: Jun Zhou

Принадлежит: Agency for Science Technology and Research Singapore

In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.

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Номер записи: 30

12-12-2013 дата публикации

INTERFACE IC AND MEMORY CARD INCLUDING THE SAME

Номер: US20130327838A1

Автор: Kagawa Shuuichi, NAKASHIBA Yasutaka, Nakata Shigeharu, OHKUBO Hiroaki, Okada Mitsuji

Принадлежит: RENESAS ELECTRONICS CORPORATION

A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view. 1. A memory card comprising:a memory that stores data;a driver that transmits the data received from the memory; andat least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit,wherein the driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.2. The memory card according to claim 1 , wherein the at least one transmitter comprises a coil.3. The memory card according to claim 1 , wherein the at least one transmitter comprises a plurality of transmitters.4. The memory card according to claim 3 , wherein the plurality of transmitters transmit the data to the receiver alternately.5. The memory card according to claim 3 , wherein the plurality of transmitters transmit the data to the receiver randomly.6. The memory card according to claim 1 , further comprising a clock receiver that receives a clock signal from the external main unit.7. The memory card according to claim 6 , wherein a size of the at least one transmitter differs from a size of the clock receiver.8. The memory card according to claim 1 , further comprising an encrypting circuit that encrypts the data received from the memory and transmits the encrypted data to the driver.9. The memory card according to claim 8 , wherein the encrypting circuit is provided in the IC chip.10. The memory card according to claim 1 , wherein the memory is provided in the IC chip.11. The memory card according to claim 1 , wherein the data stored in the memory comprises a game software.12. An ...

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Номер записи: 31

12-12-2013 дата публикации

SEMICONDUCTOR DEVICE BASED ON POWER GATING IN MULTILEVEL WIRING STRUCTURE

Номер: US20130328589A1

Автор: ISHII Toshinao

Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively. 1. A device comprising: a first circuit cell array extending in a first direction,', 'a second circuit cell array extending in the first direction substantially in parallel to the first circuit cell array,', 'first and second power lines each of which extends in the first direction and arranged over the first circuit cell array,', 'third and fourth power lines each of which extends in the first direction and arranged over the second circuit cell array,', 'a first transistor coupled between the second and third power supply lines,', 'a plurality of first logic circuits arranged in the first cell array, each of the first logic circuits includes first and second power nodes coupled respectively to the first and second power lines,', 'a plurality of second logic circuits arranged in the second cell array, each of the second logic circuits includes third and fourth power nodes coupled respectively to the third and fourth power lines,', 'a first interconnection connecting an output node of a first one of the first logic circuits to an input node of a first one of the second logic circuits, and', 'a second interconnection connecting an output node of the first one of the second logic circuits to an input node of a second one of the first logic circuits., 'a circuit unit ...

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Номер записи: 32

12-12-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING FLOATING BODY TYPE TRANSISTOR

Номер: US20130328590A1

Автор: YOSHIDA Soichiro

Принадлежит: ELPIDA MEMORY, INC.

A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level. 1. A semiconductor device comprising:a first circuit node supplied with a first signal changing between first and second logic levels;a second circuit node supplied with a second signal changing between the first and second logic levels;a third circuit node;a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level;a fourth circuit node supplied with a voltage level being close to or the same as the second logic level; anda second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level,the first transistor being configured as a floating body type in which a body between a source and a drain is in en electrically floating state.2. The semiconductor device as ...

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Номер записи: 33

26-12-2013 дата публикации

INPUT CIRCUIT ARRANGEMENT, OUTPUT CIRCUIT ARRANGEMENT, AND SYSTEM HAVING AN INPUT CIRCUIT ARRANGEMENT AND AN OUTPUT CIRCUIT ARRANGEMENT

Номер: US20130342260A1

Автор: BÖHM Michael, Feffner Johannes

Принадлежит: ams AG

The invention relates to an input circuit arrangement (), which is designed for operation either in a first or a second operating mode (A, B) and comprises a connection () for supplying a connection signal (SWI) and a detection circuit (). The detection circuit () is coupled on the input side to the connection () and is designed to put the input circuit arrangement () into an operating mode from a group comprising the first and second operating modes (A, B) depending on the steepness of a change of the connection signal (SWI). 1. An input circuit arrangement , which is designed for operation either in a first or a second operating mode , the input circuit arrangement comprising:a connection for supplying a connection signal; anda detection circuit that is coupled on the input side to the connection and is designed to put the input circuit arrangement into an operating mode from a group comprising the first and second operating modes depending on a steepness of a change of the connection signal),wherein, in the first operating mode, via the connection, both data information and also clock information are supplied to the input circuit arrangement, and, in the second operating mode, the input circuit arrangement is designed to provide an input signal that corresponds to the connection signal.2. The input circuit arrangement according to claim 1 , wherein the detection circuit is designed to put the input circuit arrangement into a first operating mode if the steepness of the change of the connection signal is smaller than a predetermined value claim 1 , and to put the input circuit arrangement into the second operating mode if the steepness of the change of the connection signal is greater than the predetermined value.3. The input circuit arrangement according to or claim 1 , wherein the detection circuit is designed to put claim 1 , depending on the steepness of the falling edge of the connection signal claim 1 , the input circuit arrangement into an operating mode ...

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Номер записи: 34

02-01-2014 дата публикации

APPARATUS FOR MIXED SIGNAL INTERFACE ACQUISITION CIRCUITRY AND ASSOCIATED METHODS

Номер: US20140002133A1

Автор: Daigle Clayton, Roy Subrata, Thomsen Axel, Wang Xiaodong, Xiao Jinwen

Принадлежит:

An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation. 1. An integrated circuit (IC) , comprising:a plurality of pads adapted to communicate signals with a circuit external to the IC;a first mixed signal interface block coupled to a first pad in the plurality of pads, the first mixed signal interface block adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal; anda second mixed signal interface block coupled to a second pad in the plurality of pads, the second mixed signal interface block adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC, and to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC,wherein a power consumption of the IC is lower in the first mode of operation than in the ...

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Номер записи: 35

16-01-2014 дата публикации

LEVEL SHIFTER

Номер: US20140015588A1

Автор: Chen Ying-Lieh

Принадлежит: RAYDIUM SEMICONDUCTOR CORPORATION

A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal. 1. A level shifter , comprising: a first Type 1 transistor;', 'a second Type 1 transistor, wherein the gate of the first Type 1 transistor and the gate of the second Type 1 transistor are connected to a first input terminal and a second input terminal respectively, the sources of both the first Type 1 transistor and the second Type 1 transistor are connected to a first voltage terminal;', 'a third Type 1 transistor, wherein the gate and the drain of the third Type 1 transistor are interconnected, the source of the third Type 1 transistor is connected to the drain of the first Type 1 transistor; and', 'a fourth Type 1 transistor, wherein the gate and the drain of the fourth Type 1 transistor are interconnected, the source of the fourth Type 1 transistor is connected to the drain of the second Type 1 transistor; and, 'a plurality of Type 1 transistors, wherein each of the Type 1 transistors includes a source, a gate, and a drain, the Type 1 transistors include a first Type 2 transistor, wherein the drain and the gate of the first Type 2 transistor are interconnected and also connected to the drain of the third Type 1 transistor;', 'a second Type 2 transistor, wherein the drain and the gate of the second Type 2 transistor are interconnected and also connected to the drain of the fourth Type 1 transistor;', 'a third Type 2 transistor, wherein the drain of the third Type 2 transistor is connected to the source of the first Type 2 ...

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Номер записи: 36

30-01-2014 дата публикации

DIFFERENTIAL OUTPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20140028349A1

Автор: NAKAMURA YUTAKA

Принадлежит: KABUSHIKI KAISHA TOSHIBA

A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances. 1. A differential output circuit comprising:a current source;a voltage source;first paired transistors configured to, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and configured to be always turned off in a second operating mode;second paired transistors configured to, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode;third paired transistors configured to, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, depending on the logic levels of the differential input signals, and configured to be always turned on in the first operating mode, the third paired transistors being connected to output current paths of the second ...

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Номер записи: 37

13-02-2014 дата публикации

Output buffer and signal processing method

Номер: US20140043090A1

Автор: Gonggui Xu

Принадлежит: ams AG

An output buffer comprises a series connection of a first field effect transistor and a second field effect transistor, wherein the first field effect transistor is connected to a first supply potential terminal and the second field effect transistor is connected to a second supply potential terminal. An output terminal is connected to a common connection of the first transistor and the second transistor. The output buffer has a series connection of a resistive element and a capacitive element, wherein the capacitive element is connected to the output terminal, and a control circuit, to which an input signal is provided. The control circuit controls the transistors in such a way that turning off of a transistor is performed immediately, while turning on of a transistor is performed depending on the charging or discharging of the capacitive element, thus achieving a defined slew rate of the output signal at the output terminal.

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Номер записи: 38

27-02-2014 дата публикации

LOW VOLTAGE TRANSMITTER WITH VARIABLE OUTPUT SWING

Номер: US20140055163A1

Автор: Song Hongjiang

Принадлежит:

Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source. 1. An apparatus comprising:a voltage mode driver coupled to an output node; anda switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver.2. The apparatus of further comprises:a bias generator to bias the switching current source.3. The apparatus of claim 1 , wherein the switching current source comprises:a first current source, coupled to the output node, to increase the voltage swing of the signal on the output node by raising a logical high level of the signal.4. The apparatus of claim 3 , wherein the switching current source comprises:a second current source, coupled to the output node, to increase the voltage swing of the signal by lowering a logical low level of the signal.5. The apparatus of claim 4 , wherein the voltage mode driver includes pull-up and pull-down devices.6. The apparatus of claim 3 , wherein the first current source is operable to inject current claim 3 , to raise the logical high level of the signal claim 3 , from a power supply node to the output node when a pull-up device is on.7. The apparatus of claim 4 , wherein the second current source is operable to sink current claim 4 , to lower the logical low level of the signal claim 4 , from the output node to a ground node when a pull-down device is on.8. The apparatus of claim 3 , wherein the first current source comprises:a first P-transistor, ...

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Номер записи: 39

27-02-2014 дата публикации

Transmission channel for ultrasound applications

Номер: US20140055188A1

Автор: Antonio Ricciardo, Davide Ugo Ghisu, Giulio Ricotti, Sandro Rossi

Принадлежит: STMICROELECTRONICS SRL

A transmission channel configured to transmit high-voltage pulses and to receive echos of the high-voltage pulses includes a high voltage buffer, a voltage clamp and a switch. The voltage clamp may include clamping transistors and switching off transistors coupled together in series with body diodes in anti-series. The transmission channel may include a reset circuit configured to bias the transmission channel between pulses. The switch may include a bootstrap circuit.

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Номер записи: 40

01-01-2015 дата публикации

PREVENTING REVERSE CONDUCTION

Номер: US20150002192A1

Автор: VU Trang

Принадлежит:

In one embodiment, a circuit includes a resistance including first and second terminals. The first terminal of the resistance is coupled to ground. The circuit also includes a first switching element including first, second, and third terminals. The first terminal of the first switching element is coupled to an output of an integrated circuit and the second terminal of the first switching element is coupled to a voltage supply of the integrated circuit. Additionally, the circuit includes a second switching element including first, second, and third terminals. The first terminal of the second switching element is coupled to an enable input of the integrated circuit. Furthermore, the second terminal of the second switching element is coupled to the third terminal of the first switching element and to the second terminal of the resistance. Moreover, the third terminal of the second switching element is coupled to the ground.

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Номер записи: 41

05-01-2017 дата публикации

System and Method for a Pre-Driver Circuit

Номер: US20170005655A1

Автор: Vashishtha Sameer

Принадлежит:

A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch. 1. A circuit comprising:a driver having an input terminal and an output terminal;a semiconductor switch having a first terminal and a second terminal, the first terminal of the semiconductor switch coupled to the output terminal of the driver; and the semiconductor switch and the capacitance element comprise a variable capacitance,', the variable capacitance provides a capacitance of substantially zero during a first portion of a data transition in the output terminal of the driver from a first state to a second state, and', 'the variable capacitance provides a non-zero capacitance during a second portion of a data transition in the output terminal of the driver from the first state to the second state., 'the variable capacitance is controlled such that'}], 'a capacitance element coupled between the second terminal of the semiconductor switch and a power supply terminal, wherein'}2. The circuit of claim 1 , wherein the semiconductor switch comprises a transistor and the capacitance element is a capacitor.3. The circuit of claim 1 , wherein the semiconductor switch comprises a p-type transistor and the driver is an inverting driver.4. The circuit of claim 1 , wherein the first state represents a 1 and the second state represents a 0. ...

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Номер записи: 42

04-01-2018 дата публикации

HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

Номер: US20180005694A1

Автор: Chevallier Christophe, Siau Chang Hua

Принадлежит:

A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array. 1. (canceled)2. An integrated circuit comprising:a substrate;a base layer formed on the substrate, the base layer comprising a decoder formed with a plurality of transistors configured to operate within a first voltage range; and a plurality of conductive array lines; and', 'a plurality of re-writable two-terminal memory cells formed at intersections of the plurality of conductive array lines, the plurality of re-writable two-terminal memory cells configured to operate within a second voltage range, wherein the first voltage range is smaller than the second voltage range., 'a cross-point memory array formed above the base layer, the cross-point memory array comprising3. The integrated circuit of claim 2 , wherein the plurality of conductive lines comprises a plurality of X-line conductive array lines and a plurality of Y-line conductive array lines.4. The integrated circuit of claim 3 , wherein each of the plurality of re-writable two-terminal memory cells comprises a first terminal electrically coupled with one of the plurality of X-line conductive array lines and second terminal electrically coupled with one of the plurality of Y-line conductive array lines.5. The integrated circuit of claim 4 , wherein the base layer further comprises:an X-line decoder including a first subset of the plurality of ...

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Номер записи: 43

04-01-2018 дата публикации

HIGH SPEED VOLTAGE LEVEL SHIFTER

Номер: US20180006650A1

Автор: Chen Rui, Lu De, Narayanan Venkat, Sinharoy Samrat, Vattikonda Rakesh, Vilangudipitchai Ramaprasath

Принадлежит:

In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain. 1. A voltage level shifter , comprising:a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output; anda second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate;wherein the first and second NOR gates are powered by a supply voltage of the second power domain.2. The voltage level shifter of claim 1 , wherein each of the first and second input signals has a voltage range approximately equal to a first voltage range claim 1 , the enable signal has a voltage range approximately equal to a second voltage range claim 1 , and the second voltage range is greater than the first voltage range.3. The voltage level shifter of claim 2 , wherein the output of each of the first and second NOR gates has a voltage range approximately equal to the second voltage range.4. The voltage level shifter of claim 1 , wherein the first and second input signals are complementary.5. The ...

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Номер записи: 44

04-01-2018 дата публикации

HIGH SPEED VOLTAGE LEVEL SHIFTER

Номер: US20180006651A1

Автор: Chen Rui, Lu De, Narayanan Venkat, Sinharoy Samrat, Vattikonda Rakesh, Vilangudipitchai Ramaprasath

Принадлежит:

In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground. 1. A voltage level shifter , comprising:a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain;a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node;an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor; anda first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.2. The voltage level shifter of claim 1 , wherein the inverter is powered by the supply voltage of the second power domain.3. The voltage level shifter of claim 1 , wherein the input signal has a voltage range that is at least 20 percent lower than the supply voltage of the second power domain.4. The voltage level shifter of claim 1 , further comprising an enable circuit configured to receive an enable signal in the second power domain claim 1 , to enable the voltage level shifter when the enable signal has a first logic state claim 1 , and to disable the voltage level shifter when the enable signal has a second ...

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Номер записи: 45

04-01-2018 дата публикации

APPARATUS FOR PROVIDING A SHARED REFERENCE DEVICE

Номер: US20180006652A1

Автор: Johnson Luke A.

Принадлежит: Intel Corporation

Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time. 1. A system comprising:a memory;a reference device;a processor coupled to the memory and the reference device, the processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.2. The system further comprising:a wireless interface for allowing the processor to communicatively couple to another device.3. The system of claim 1 , wherein the processor includes logic to provide a valid token to one of the circuit units of the plurality to cause that circuit unit to electronically couple with the reference device.4. The system of claim 3 , wherein the logic to provide an invalid token to other circuit units to cause the other circuit units to electronically uncouple with the reference device.5. The system of claim 1 , wherein the processor includes logic to issue tokens for the circuit units at a programmable rate to allow each circuit unit to update their calibration code in view of time varying effects.6. The system of claim 1 , wherein the processor includes logic to issue tokens after a preset change in temperature is detected.7. The system of claim 1 , wherein the reference device to calibrate any number of calibration devices in the circuit units such that the processor to use a single pin for calibration purposes.8. The system of ...

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Номер записи: 46

03-01-2019 дата публикации

GATE STRUCTURE AND METHODS THEREOF

Номер: US20190006488A1

Автор: CHENG Anhao, KUO Fang-Ting

Принадлежит:

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided. 1. A method of fabricating a semiconductor device , comprising:forming a gate dielectric trench within a substrate;depositing a first dielectric layer within the gate dielectric trench, wherein a top surface of the first dielectric layer is co-planar with a top surface of the substrate;forming a second dielectric layer over the first dielectric layer; andforming a metal gate over the second dielectric layer.2. The method of claim 1 , wherein the forming the gate dielectric trench further includes etching the gate dielectric trench to a first depth claim 1 , and wherein the first depth is measured from a plane parallel to the top surface of the substrate to a bottom surface of the gate dielectric trench.3. The method of claim 1 , wherein the forming the gate dielectric trench further includes forming the gate dielectric trench having a first width along the plane parallel to the top surface of the substrate claim 1 , and forming the gate dielectric trench having a second width along a plane parallel to the bottom surface of the gate dielectric trench.4. The method of claim 3 , wherein the second width is less than the first width.5. The method of claim 1 , further ...

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Номер записи: 47

07-01-2021 дата публикации

BIAS CIRCUITRY AND BIASING METHOD

Номер: US20210006249A1

Автор: Liu Jian, YANG Jun

Принадлежит:

A bias circuitry includes a simulation circuit and a level shifter circuit. The simulation circuit is configured to simulate circuit architecture of a processing circuitry, in which the processing circuitry is biased by a bias signal, in order to generate output signals according to input signals. The level shifter circuit is configured to increase a voltage difference between a first node and a second node of the simulation circuit, in which the first node is for tracking an output common mode voltage of the output signals, and the second node is for outputting the bias signal. 1. A bias circuitry , comprising:a simulation circuit configured to simulate a circuit architecture of a processing circuitry, wherein the processing circuitry is biased by a bias signal, in order to generate a plurality of output signals according to a plurality of input signals; anda level shifter circuit configured to increase a voltage difference between a first node and a second node of the simulation circuit, wherein the first node is configured to track an output common mode voltage of the output signals, and the second node is configured to output the bias signal.2. The bias circuitry of claim 1 , wherein the processing circuitry comprises an input pair circuit and a first transistor claim 1 , the input pair circuit receives the input signals and generates the output signals claim 1 , the first transistor generates a first current according to the bias signal to bias the input pair circuit claim 1 , and the simulation circuit comprises:a second transistor coupled to the first node, and configured to simulate the input pair circuit, wherein a control terminal of the second transistor is configured to receive a common mode voltage related to the input signals; anda third transistor coupled between the second transistor and a ground, and configured to simulate the first transistor, wherein a control terminal of the third transistor is coupled to the second node.3. The bias circuitry of ...

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Номер записи: 48

03-01-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190007045A1

Автор: HIRASHIMA Yasuhiro, Koyanagi Masaru, Takayama Yutaka

Принадлежит:

A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter. 1. A semiconductor device comprising:an input/output (IO) signal receiver circuit; anda latch circuit connected to the IO signal receiver circuit, a first inverter configured to output a first signal based on an input signal received from the IO signal receiver circuit,', 'a second inverter configured to output a first clock signal based on a first strobe signal,', 'a third inverter configured to output a second clock signal based on a second strobe signal which is an inversion signal of the first strobe signal,', 'a first clock generation circuit which is connected to an output terminal of the second inverter and is configured to generate a third clock signal from the first clock signal, wherein logical level transitions in the third clock signal are delayed with respect to the first clock signal and are completed in a shorter amount of time than the first clock signal,', 'a second clock generation circuit which is connected to an output terminal of the third inverter and is configured to generate a fourth clock signal from the second clock signal, wherein logical level transitions in the fourth clock signal are delayed with ...

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Номер записи: 49

03-01-2019 дата публикации

GATE CONTROL FOR A TRISTATE OUTPUT BUFFER

Номер: US20190007046A1

Автор: Graves Christopher Michael

Принадлежит:

A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal. 1. A gate control circuit for a tristate output buffer operating in a first voltage domain , the gate control circuit comprising:a pull-up circuit coupled between an upper rail and a first gate control signal;a pull-down circuit coupled between a lower rail and a second gate control signal; anda gate isolation switch coupled between the first gate control signal and the second gate control signal, the gate isolation switch comprising a first PMOS transistor coupled in parallel with a first NMOS transistor, the first NMOS transistor being controlled by a first enable signal and the first PMOS transistor being controlled by a second enable signal.2. The gate control circuit for a tristate output buffer as recited in wherein when the tristate output buffer is enabled claim 1 , the first enable signal is high and the second enable signal is low and when the tristate output buffer is in high impedance claim 1 , the first enable signal is low and the second enable signal is high.3. The gate control circuit for a tristate output buffer as recited in wherein the gate isolation switch further comprising a second PMOS transistor coupled in parallel with a second NMOS transistor claim 2 , the second NMOS transistor being controlled by the first enable signal and the second PMOS transistor being controlled by the second enable signal claim 2 , the first PMOS transistor and ...

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Номер записи: 50

08-01-2015 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20150008958A1

Автор: KUROKAWA Yoshiyuki

Принадлежит:

Path transistor malfunction is reduced. A path gate circuit includes transistors MP, MW, and MC. The transistor MP functions as a path transistor that connects a signal line INL to a signal line OUTL. The transistor MW connects a signal line BL for inputting a signal for setting the on or off state of the transistor MP and a node SN (gate of the transistor MP). When a high-level potential is written to the node SN, the potential of BL is set higher than a normal high-level potential if the potential of INL is high. Thus, even when the potential of the node SN is dropped in accordance with transition of INL from a high level to a low level, the potential drop does not influence the operation of the transistor MP because a high potential is written in advance. 1. A semiconductor device comprising: a first transistor between an input signal line and an output signal line, one of a source and a drain of the first transistor being electrically connected to the input signal line; and', 'a second transistor between a bit line and a gate of the first transistor; and, 'a path gate circuit comprisinga circuit being electrically connected to the gate of the first transistor through the second transistor and the bit line,wherein the circuit is configured to supply a first signal at a first high level when a potential of the input signal line is at a low level, andwherein the circuit is configured to supply a second signal at a second high level when the potential of the input signal line is at a high level, the second high level being higher than the first high level.2. The semiconductor device according to claim 1 ,wherein the other of the source and the drain of the first transistor is electrically connected to the output signal line,wherein one of a source and a drain of the second transistor is electrically connected to the bit line,wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor, ...

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Номер записи: 51

12-01-2017 дата публикации

Electrostatic Discharge Protection for Level-Shifter Circuit

Номер: US20170012038A1

Автор: CHEN Chia-Hui, Chen Kuo-Ji, CHU Chia-Hung, LU Lee-Chung, SONG Ming-Hsiang

Принадлежит:

In some embodiments, a method includes providing an input voltage to a level-shifting circuit, where the input voltage is in a first power domain, shifting the input voltage to an output voltage using the level-shifting circuit, where the output voltage is in a second power domain different from the first power domain, and where the level-shifting circuit is coupled to power supply voltages in the second power domain. The method further includes in response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain. 1. A method comprising:providing an input voltage to a level-shifting circuit, wherein the input voltage is in a first power domain;shifting the input voltage to an output voltage using the level-shifting circuit, wherein the output voltage is in a second power domain different from the first power domain, wherein the level-shifting circuit is coupled to power supply voltages in the second power domain; andin response to an electrostatic discharge (ESD) event, turning off a first transistor coupled between a first node of the level-shifting circuit and a reference low voltage level of the second power domain.2. The method of claim 1 , wherein the first transistor is an N-type transistor claim 1 , wherein the turning off comprises supplying a reference low voltage level of the second power domain to a gate of the first transistor.3. The method of claim 2 , further comprising detecting the ESD event using a control circuit.4. The method of claim 3 , wherein the control circuit is coupled to the power supply voltages of the second power domain claim 3 , wherein an output of the control circuit is coupled to the gate of the first transistor claim 3 , and wherein the control circuit outputs a reference low voltage level of the second power domain during an ESD event.5. The method of claim 4 , wherein the control circuit ...

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Номер записи: 52

12-01-2017 дата публикации

VOLTAGE LEVEL SHIFTER

Номер: US20170012625A1

Автор: LEE Seung-ho

Принадлежит:

A voltage level shifter includes: in stages a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit. 1. A voltage level shifter comprising:a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage;a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal;a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; anda bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull- ...

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Номер записи: 53

12-01-2017 дата публикации

CONFIGURABLE POWER DOMAIN AND METHOD

Номер: US20170012627A1

Автор: Blutman Kristof, Kapoor Ajay, Pineda de Gyvez Jose, van der Wel Arnoud

Принадлежит:

Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication). 1. An apparatus comprising:a first circuit configured and arranged to operate under a first power domain having a first voltage range;a second circuit configured and arranged to operate under a second power domain having a second voltage range; and detect a voltage range of the first power domain,', 'detect a voltage range of the second power domain, and', convert a voltage level of each communication received from one of the first and second circuits to a voltage level of the other one of the first and second circuits in response to the detected voltage ranges being different, and thereafter providing the communication to the other one of the first and second circuits, and', 'pass each communication directly between the first and second circuits in response to the detected voltage ranges being the same., 'for communications between the first and second circuits,'}], 'a level shifter circuit connected to the first circuit and to the second circuit, the level shifter circuit being configured and arranged to2. The apparatus of claim 1 , wherein the level shifter circuit is configured and arranged to:in a first ...

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Номер записи: 54

11-01-2018 дата публикации

I/o cell

Номер: US20180013433A1

Автор: Shoichi Nitta

Принадлежит: Ricoh Co Ltd

An I/O cell includes a reference output circuit that has a reference output transistor, connected to an output terminal, and has a reference pre-buffer, the reference pre-buffer driving the reference output transistor according to an input signal of the input terminal; adjustment output circuits that have an adjustment output transistor, connected to the output terminal and connected in parallel with the reference output transistor, and have an adjustment pre-buffer, the adjustment pre-buffer driving the adjustment output transistor according to the input signal; and a gate voltage detection control circuit that monitors all of gate voltages applied to the output transistors included in the reference output circuit and the adjustment output circuit. The gate voltage detection control circuit generates a timing when all of the output transistors are turned OFF when switching the H/L level of the output current to the load according to the change of the input signal.

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Номер записи: 55

10-01-2019 дата публикации

APPARATUSES AND METHODS FOR PARTIAL BIT DE-EMPHASIS

Номер: US20190013809A1

Автор: Greeff Roy E.

Принадлежит:

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion. 1. An apparatus comprising:an external terminal; and receive a first signal having a first logical value,', 'receive a second signal following the first signal, the second signal having a second logical value different from the first logical value, and', 'drive, in response to receiving the second signal, the external terminal from a first voltage to a second voltage by way of a third voltage, wherein the third voltage is a de-emphasized first voltage based at least in part on a de-emphasis time., 'an output driver coupled to the external terminal, the output driver configured to2. The apparatus of claim 1 , wherein the output driver de-emphasizes the first voltage for two bit periods.3. The apparatus of claim 1 , further comprising a variable delay circuit to introduce a delay interval claim 1 , wherein the delay interval determines the de-emphasis time.4. The apparatus of claim 3 , wherein the delay interval comprises a half bit period to produce a half bit period de-emphasis.5. The apparatus of claim 3 , wherein the variable delay circuit is configured to receive an input signal having first and second logic values claim 3 , and generate a delayed signal that is delayed relative to ...

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Номер записи: 56

15-01-2015 дата публикации

COMPENSATION CIRCUIT FOR USE WITH INPUT BUFFER AND METHOD OF OPERATING THE SAME

Номер: US20150016195A1

Автор: KIM Jun Bae, Yu Hye Seung

Принадлежит:

A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal. 1. A compensation circuit for use with an input buffer , the compensation circuit comprising:an input buffer configured to amplify an input signal and output a compensated signal; anda process detector including a replica of the input buffer, the process detector configured to output at least one comparison signal indicating a variation in the input buffer,wherein the input buffer is configured to control an output signal based on the at least one comparison signal.2. The compensation circuit of claim 1 , wherein the input buffer is configured to control a bias voltage of an output terminal according to the at least one comparison signal.3. The compensation circuit of claim 1 , wherein the input buffer comprises an input buffer differential amplifier configured to receive and differentially amplify a reference voltage and the input signal claim 1 , and the replica comprises a replica buffer differential amplifier including two input terminals to which the reference voltage is applied claim 1 , the replica buffer differential amplifier configured to output a replica voltage.4. The compensation circuit of claim 3 , wherein the input buffer further comprises an output adjust unit configured to decrease a bias voltage of an output terminal when the variation is slow-fast (SF) and to increase the bias voltage of the output terminal when the variation is fast-slow (FS).5. The compensation circuit of claim 3 , further comprising:a first comparator configured to compare the replica voltage with a first reference voltage and output a first comparison signal according ...

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Номер записи: 57

14-01-2021 дата публикации

BUFFER CIRCUIT BETWEEN DIFFERENT VOLTAGE DOMAINS

Номер: US20210013873A1

Автор: Chang Chia-Jung, CHEN Chia-Hui, Lin Wan-Yen

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A circuit includes a first inverter and a second inverter. The first inverter is coupled to an input terminal. The input terminal receives an input signal varying in a first voltage domain. The second inverter is coupled between the first inverter and an output terminal. The second inverter generating an output signal varying in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in the second voltage domain. 1. A circuit , comprising:a first inverter, coupled to an input terminal, the input terminal receiving an input signal varying in a first voltage domain from a negative supply level to a first positive supply level; anda second inverter, coupled between the first inverter and an output terminal, the second inverter generating an output signal varying in a second voltage domain from the negative supply level to a second positive supply level, a first PMOS transistor biased by a first input tracking signal generated from the input signal, the first input tracking signal varies in a third voltage domain from a reference level to the first positive supply level, the reference level is higher than the negative supply level; and', 'a first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varies in the second voltage domain., 'wherein the first inverter comprising2. The circuit of claim 1 , wherein a first voltage difference window of the first voltage domain is larger than a second voltage difference window of the second voltage domain claim 1 , and the first voltage difference window is larger than a third voltage difference window of ...

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Номер записи: 58

14-01-2021 дата публикации

DIFFERENTIAL SIGNAL TRANSMISSION CIRCUIT

Номер: US20210013884A1

Автор: Yano Yuji

Принадлежит: ROHM CO., LTD.

There is provided a differential signal transmission circuit that includes a first output terminal, a second output terminal connected to the first output terminal via a load resistor, a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal, a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal, a high-side pre-driver configured to drive the high-side transistor, a low-side pre-driver configured to drive the low-side transistor, a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor, and a second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor. 1. A differential signal transmission circuit , comprising:a first output terminal;a second output terminal connected to the first output terminal via a load resistor;a high-side transistor formed of a p-channel MOSFET and connected between an application terminal of a power supply voltage and the first output terminal;a low-side transistor formed of an n-channel MOSFET and connected between an application terminal of a ground potential and the second output terminal;a high-side pre-driver configured to drive the high-side transistor;a low-side pre-driver configured to drive the low-side transistor;a first resistance part connected between an output end of the high-side pre-driver and a gate of the high-side transistor; anda second resistance part connected between an output end of the low-side pre-driver and a gate of the low-side transistor.2. The differential signal transmission circuit of claim 1 , wherein the first resistance part and the second resistance part are devices having a same composition.3. The differential signal transmission circuit of claim 2 , wherein the first resistance part and the ...

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Номер записи: 59

09-01-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200014385A1

Автор: HIRASHIMA Yasuhiro, Koyanagi Masaru, Takayama Yutaka

Принадлежит:

A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter. 1. A semiconductor device comprising:an input/output (IO) signal receiver circuit; anda latch circuit connected to the IO signal receiver circuit, a first inverter configured to output a first signal based on an input signal received from the IO signal receiver circuit,', 'a correction circuit configured to output first and second clock signals based on a first strobe signal and a second strobe signal which is an inversion signal of the first strobe signal, and adjust a duty ratio of at least one of the first and second clock signals,', 'a second inverter configured to output a third clock signal based on the first clock signal,', 'a third inverter configured to output a fourth clock signal based on the second clock signal,', 'a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and', 'a data latch circuit configured to latch an output signal of the fourth inverter in accordance with the third and fourth clock signals., 'wherein the latch circuit includes'}2. The semiconductor device according to claim 1 ,wherein when a duration of a first logical ...

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Номер записи: 60

09-01-2020 дата публикации

LEVEL SHIFTING CIRCUIT AND METHOD

Номер: US20200014386A1

Автор: Ma Jun, WANG Xin, YI Jiangtao

Принадлежит: SMARTER MICROELECTRONICS (SHANGHAI) CO., LTD.

A level shifting circuit includes a shift circuit configured to output first and second voltage signals according to level signals, and an input circuit configured to carry out inversion and delay operations on input level signals to obtain first, second, third, and fourth level signals. Rising edge of the first level signal is earlier than falling edge of the second level signal by a first preset time. Falling edge of first level signal is later than rising edge of the second level signal by a second preset time; the third level signal is obtain by delaying the first level signal by a third preset time, and the fourth level signal is obtain by delaying the second level signal by a fourth preset time; the first preset time is longer than the third preset time, and the second preset time is longer than the fourth preset time. 1. A level shifting circuit , comprising an input circuit , and a shifting circuit connected with the input circuit , wherein:the input circuit is configured to perform inversion and delay operations on an input level signal to obtain a first level signal, a second level signal, a third level signal and a fourth level signal;a rising edge of the first level signal occurs a first preset time earlier than a falling edge of the second level signal, and a falling edge of the first level signal occurs a second preset time later than a rising edge of the second level signal; the third level signal is a signal obtained by delaying the first level signal for a third preset time, and the fourth level signal is a signal obtained by delaying the second level signal for a fourth preset time; the first preset time is longer than the third preset time, the second preset time is longer than the fourth preset time; andthe shifting circuit is configured to output a first voltage signal and a second voltage signal based on the level signals, and the first voltage signal and the second voltage signal are inverted with each other.2. The level shifting circuit ...

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Номер записи: 61

19-01-2017 дата публикации

LEVEL SHIFT CIRCUIT

Номер: US20170019090A1

Автор: HONDA Takuya, ISOMURA Hirofumi

Принадлежит:

An input part is supplied with a low voltage from a low voltage power supply line. A level shift part and an output part are supplied with a high voltage from a high voltage power supply line. An input terminal is pulled up by a resistor and connected to the level shift part through a buffer circuit and an inverter circuit. The level shift part is connected in series with an NMOS and turned on when the input terminal changes to a low level. The output terminal is pulled up by a resistor through the buffer circuit. Even when the level shift part operates unstably because of long delay time from rising of a potential of the high voltage power supply line to rising of a potential of the low voltage power supply line, the output voltage is maintained at a high level. 1. A level shift circuit comprising:a common power supply line;a first power supply line, which supplies a first voltage relative to the common power supply line;a second power supply line, which supplies a second voltage relative to the common power supply line, the second voltage being different from the first voltage;an input terminal, to which an input signal is applied;an output terminal, which outputs an output signal;a level shift part provided between the common power supply line and the second power supply line and operable with the second voltage, the level shift part converting the input signal corresponding to the first voltage to the output signal corresponding to the second voltage;an operation control switch for controlling operation of the level shift part;a first potential setting circuit for fixing a potential of the input terminal to a predetermined potential when the input terminal is in a high impedance state with no input signal applied to the input terminal;a second potential setting circuit for setting a potential of the output terminal to a predetermined potential when the input terminal is in the high impedance state; andan off-fixing circuit for inhibiting the operation of the ...

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Номер записи: 62

19-01-2017 дата публикации

LEVEL SHIFT CIRCUIT

Номер: US20170019106A1

Автор: AKAHANE Masashi

Принадлежит:

The present invention provides a level-shift circuit that can suppress the malfunction caused by the noise due to the ON/OFF of a level-shift transistor and the dV/dt noise due to external noise. The present invention provides a level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side, comprising: a first serial circuit a first resistance including serially-connected to a first switching element; a second serial circuit including a second resistance serially-connected to a second switching element; a latch malfunction protection circuit for which the respective output terminals of the first and second serial circuits are connected to an input terminal; a latch circuit for receiving a signal outputted from the latch malfunction protection circuit; and a capacitor connected between drain terminals of the first resistance and the first switching element and between drain terminals of the second resistance and the second switching element. 1. A level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side different from the primary potential side , comprising:a first serial circuit including a first resistance serially-connected to a first switching element, wherein the input of the first switching element is a first input signal for turning ON or OFF the first switching element, and a connecting point of the first resistance and the first switching element acts as an output terminal;a second serial circuit including a second resistance serially-connected to a second switching element, wherein the input of the second switching element is a second input signal for controlling the ON/OFF of the second switching element, a connecting point of the second resistance and the second switching element acts as an output terminal, and the first input signal and the second input signal are not simultaneously turned ON;a latch circuit for changing a status depending on the output of the ...

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Номер записи: 63

19-01-2017 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20170019107A1

Автор: Cho Sun Ki

Принадлежит:

A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied. 1. A semiconductor apparatus comprising:a transmission circuit;a reception circuit; anda pad commonly coupled to the transmission circuit and the reception circuit,wherein parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied when either the transmission circuit or the reception circuit is activated.2. The semiconductor apparatus of claim 1 , wherein the parasitic capacitance is reduced when the reception circuit is activated rather than when the transmission circuit is activated.3. The semiconductor apparatus of claim 2 , wherein the transmission circuit includes a driver including a first transistor and a second transistor claim 2 , andjunction capacitances of the first and second transistors are reduced when the reception circuit is activated rather than when the transmission circuit is activated.4. The semiconductor apparatus of claim 3 , wherein a level of a voltage input to a source and a level of a voltage input to a bulk bias input terminal in each of the first and second transistors are changed when the reception circuit is activated rather than when the transmission circuit is activated.5. The semiconductor apparatus of claim 4 , wherein the level of the voltage input to the bulk bias input terminal in the first transistor is increased when the reception circuit is activated rather than when the transmission circuit is activated.6. The semiconductor apparatus of claim 5 , wherein an external voltage is input to the source and the bulk bias input terminal of the first transistor when the transmission circuit is activated claim 5 , and the external ...

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Номер записи: 64

17-04-2014 дата публикации

Architectural Floorplan for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node or Smaller

Номер: US20140103959A1

Автор: Andreev Alexander, Kung Chee-Wei, Lee Seow-Sung, Lim Chong-Teik, Pavisic Ivan, Scepanovic Ranko L., Udovikhin Mikhail, Vikhliantsev Igor, Yahontov Alexander

Принадлежит: eASIC Corporation

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer. 1. A structured application specific integrated circuit (Structured ASIC) , comprising:a core comprising memory cells and logic cells;a first IO routing fabric comprising a plurality of IO blocks along the sides of the core, operatively connected to the core, the first IO fabric comprising a first routing fabric;a second IO routing fabric comprising a high-speed routing fabric operatively connected to the core; wherein,the second IO fabric is faster in data transfer than the first IO fabric, and the Structured ASIC is configured through via-configurable interconnections in the Structured ASIC.2. The Structured ASIC according to claim 1 , wherein:the core is substantially rectilinear;the core logic cells comprise a module array having a plurality of logic cells arrayed in a repeating pattern;the first routing fabric is configurable through vias in the Structured ASIC, and connects the core to logical pin IO repeater areas;the module array further comprising a plurality of flip-flops, a clock macro, full adders and buffer cells operatively connected; and,the memory cells and logic cells of the ...

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Номер записи: 65

17-04-2014 дата публикации

LEVEL SHIFTERS, METHODS FOR MAKING THE LEVEL SHIFTERS AND METHODS OF USING INTEGRATED CIRCUITS

Номер: US20140103967A1

Автор: LIN Chih-Chang, PU Chiang, SWEI Yuwen, YANG Tien Chun

Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method of making a level shifter includes coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor. An inverter having an input is coupled with the input end. A third transistor having a gate end is coupled with an output of the inverter, the third transistor having a terminal coupled to a pumped voltage (VPP). Additionally, the method includes coupling a fourth transistor with the output end, the fourth transistor having a terminal coupled to the pumped voltage. A fifth transistor is coupled with the input end, the fifth transistor having a terminal coupled to the third and fourth transistors. A sixth transistor is coupled with the input end, the sixth transistor having a terminal. 1. A method of making a level shifter comprising:coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor;coupling an inverter with the input end, the inverter having an input and an output;coupling a third transistor with an output of the inverter, the third transistor having a terminal and a gate end, the terminal of the third transistor being coupled to a pumped voltage (VPP);coupling a fourth transistor with the output end, the fourth transistor having a terminal, the terminal of the fourth transistor being coupled to the pumped voltage;coupling a fifth transistor with the input end, the fifth transistor having a terminal, the terminal of the fifth transistor being coupled to the third and fourth transistors; andcoupling a sixth transistor with the input end, the sixth transistor having a terminal.2. The method of claim 1 , further comprising coupling the gate of the first transistor with the gate of the second transistor.3. The method of claim 1 , further comprising coupling a source end of the first transistor with the pumped voltage.4. The method of claim 1 , further comprising coupling a drain end of the fifth transistor ...

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Номер записи: 66

03-02-2022 дата публикации

LEVEL DOWN SHIFTER

Номер: US20220038101A1

Автор: Blanc Fabrice, Bogi Seshagiri Rao, Chenani Vinay, Gandhi Gayathri

Принадлежит: ARM LIMITED

A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain. 1. A level down shifter circuit comprising:a latch configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal, wherein the digital input signal and the complementary input signal are in a first voltage domain, the digital shifted signal and the complementary shifted signal are in a second voltage domain, and the second voltage domain has a smaller voltage range than the first voltage domain; andan assist circuit configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal, wherein the intermediate voltage is in the second voltage domain; anda header configured to bias the intermediate voltage from a second voltage source of the second voltage domain.2. (canceled)3. The level down shifter circuit according to claim 1 , wherein the header includes a transistor with a gate tied to a first voltage source of the first voltage domain.4. The level down shifter circuit according to claim 1 , further comprising an inverter configured to generate the ...

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Номер записи: 67

18-01-2018 дата публикации

Cross-Coupled, Narrow Pulse, High Voltage Level Shifting Circuit With Voltage Domain Common Mode Rejection

Номер: US20180019749A1

Автор: Aviral Srivastava, Fesler Robert

Принадлежит:

A system for high voltage level shifting includes a level shifting circuit having a high side circuit that receives a mixed signal having a common mode signal and a differential mode signal, and to attenuate the common mode signal in the mixed signal to generate an adjusted signal. The high side circuit generates a high output signal at a high output node in response to the adjusted signal. The system further includes a high side high voltage power transistor having a gate connected to the high output node of the high side circuit. The high side high voltage power transistor configured to provide a high portion of an output signal on a first output node in response to the high output signal. 1. A system , comprising: 'a high side circuit configured to receive a mixed signal having a common mode signal and a differential mode signal, and to attenuate the common mode signal in the mixed signal to generate an adjusted signal, wherein the high side circuit is further configured to generate a high output signal at a high output node in response to the adjusted signal; and', 'a level shifting circuit includinga high side high voltage power transistor having a gate connected to the high output node of the high side circuit, the high side high voltage power transistor configured to provide a high portion of an output signal on a first output node in response to the high output signal.2. The system of claim 1 , further comprising:a low side circuit configured to generate the differential signal in response to a high input signal; anda low side high voltage power transistor having a gate connected to a low output node of the low side circuit;wherein the low side circuit is further configured to generate a low output signal at the low output node in response to a low input signal; andwherein the low side high voltage power transistor is configured to provide a low portion of an output signal on a second output node in response to the low output signal.3. The system of claim 2 ...

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Номер записи: 68

17-04-2014 дата публикации

Electro-optical modulator interface

Номер: US20140104666A1

Автор: Enrico Stefano Temporiti Milani, Gabriele MINOIA, Salvatore Galeone

Принадлежит: STMICROELECTRONICS SRL

A relatively high-speed, high-efficiency CMOS two branch driver core that may operate under relatively low supply voltage may include thin oxide CMOS transistors configured to generate rail-to-rail output swings larger than twice a supply voltage and without exceeding safe operating area limits. Each of the two branches may include two stacked CMOS inverter pairs configured to drive a respective load capacitance coupled between respective CMOS inverter outputs, in phase opposition to the other branch. A pre-driver circuit input with a differential modulating signal may output two synchronous differential voltage drive signals of a swing of half of the supply voltage and DC-shifted by half of the supply voltage with respect to each other and that may be applied to the respective CMOS inverter inputs of the two branches.

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Номер записи: 69

22-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING THE SAME

Номер: US20150023082A1

Автор: KATAKURA Hideaki, YAMAJI Masaharu

Принадлежит:

In a semiconductor device such as a three-phase one-chip gate driver IC, HVNMOSs configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of HVNMOSs of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the HVNMOSs configuring the two set and reset level shift circuits are made equal to or more than 150 μm, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied. 1. A semiconductor device comprising:a plurality of second conductivity type first well regions, each surrounded by a first conductivity type region, which are provided spaced from one another on the front surface layer of a semiconductor substrate; and a first conductivity type second well region, provided in contact with all the plurality of first well regions, which configures the first conductivity type region and to which a low potential is applied, whereinthe plurality of first well regions each include: a high side driver circuit, provided on the front surface layer of the first well region, a potential on the low potential side of which is higher than the low potential; a second conductivity type pickup region, provided on the front surface layer of the first well region, to which is connected the high potential side of a power source of the high side driver circuit; a high voltage junction termination structure provided in the first well region between the second well region and the pickup region; and two level shift elements, each provided in one portion of the high voltage junction termination structure and second well region, which send signals for driving the high side driver circuit, andthe two level shift elements are disposed on respective non-opposed surfaces which are not opposite to the adjacent first well region, ...

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Номер записи: 70

21-01-2021 дата публикации

Multifunction Terminals for Alarm Systems

Номер: US20210020009A1

Автор: Konheim Keith Michael

Принадлежит:

The present invention is directed to circuit that improves alarm systems by adding the flexibility through software to configure an output terminal for typical device functions of Alarm System Devices. With a number of these circuits on a single Circuit Board, installers can use fewer different Circuit Boards. Alarm systems may be constructed from many different components and sensors. These components and sensors may be connected either with wires or wireless networks. This present invention improves the ability to connect components and sensors for a Wired Alarm System. Present Alarm systems have dedicated terminals for each different sensor, keypad or human interface, Contacts for Windows and Doors, Solenoids to remotely unlock Doors. 1. A multifunction terminal for alarm systems comprising: i) measuring an analog signal and a digital signal; and', 'ii) outputting binary numbers at 3.3-volt logic level;, 'a) a first bit capable ofb) a second bit configured to be a terminal with input and output capabilities;c) a third bit configured to enable alarm system analog measurements;d) a fourth bit configured with a 3.3-volt binary output;e) a fifth bit configured with a 3.3-volt binary output and a pulse width modulated output;f) a sixth bit configured to be a terminal for a voltage and current connection;g) a plurality of P-Channel-MOSFETs;h) a plurality of N-Channel-MOSFETs;i) a plurality of resistors;j) an analog measurement mode;k) a test mode to detect a voltage source;l) a data receive mode;m) a data transmit current limited mode;n) a data or high current drive mode; ando) a data drive non-current limited mode.2. The multifunction terminal for alarm systems of claim 1 , wherein the analog measurement mode comprises:a) the first bit being configured to measure analog voltages;b) the fourth bit and the fifth bit being configured to output in a logic low setting; andc) the third bit being configured to be in a logic high setting.3. The multifunction terminal for ...

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Номер записи: 71

16-01-2020 дата публикации

Adiabatic Logic-In-Memory Architecture

Номер: US20200021290A1

Автор: Kumar S. Dinesh, Thapliyal Himanshu

Принадлежит:

An adiabatic logic-in-memory based complementary metal-oxide-semiconductor/magnetic-tunnel-junction (ALiM CMOS/MTJ) circuit utilizes an adiabatic logic based pre-charged sense amplifier (PCSA) to recover energy from its output load capacitors. The ALiM CMOS/MTJ includes a non-volatile magnetic-tunnel-junction (MTJ) based memory. The ALiM CMOS/MTJ also includes a dual rail complementary metal-oxide-semiconductor (CMOS) logic that performs logic operations in association with the MTJ, and thereby generates logic outputs based on logic inputs. The ALiM CMOS/MTJ also includes the adiabatic PCSA, which is operatively coupled to the dual rail CMOS logic. The adiabatic logic based PCSA includes PCSA circuitry for which an input is a multi-phase power clock, and a charge recovery circuit having the output load capacitors. The charge recovery circuit is operatively coupled to the PCSA circuitry such that the ALiM CMOS/MTJ circuit uses the power clock to recover energy from the output load capacitors. 1. An adiabatic logic-in-memory based complementary metal-oxide-semiconductor/magnetic-tunnel-junction (ALiM CMOS/MTJ) circuit , comprising:a set of magnetic-tunnel-junctions (MTJs) configured to store non-volatile data;a logic network, comprising the set of MTJs and a set of complementary metal-oxide-semiconductor (“CMOS”) transistors configured to together perform logic operations so as to generate logic outputs based on logic inputs; and PCSA circuitry for which an input is a multi-phase power clock, the PCSA circuitry including cross-coupled transistors coupled to a common discharge transistor;', 'charge recovery circuitry, including output load capacitors,', 'wherein the charge recovery circuitry is operatively coupled to the PCSA circuitry such that the ALiM CMOS/MTJ circuit uses the power clock to recover energy from output load capacitors., 'an adiabatic logic based pre-charged sense amplifier (PCSA) operatively coupled to the logic network, the adiabatic logic based ...

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Номер записи: 72

26-01-2017 дата публикации

HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY

Номер: US20170025173A1

Автор: Chevallier Christophe, Siau Chang Hua

Принадлежит:

A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array. 1. A decoder circuit comprising: predecode logic to generate a control signal; and', 'a level shifter circuit to generate a voltage signal; and, 'a predecoder comprising a first stage; and', 'a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array., 'a post-decoder coupled to the predecoder, the post-decoder comprising2. The decoder circuit of claim 1 , wherein the level shifter circuit comprises a negative voltage level shifter claim 1 , a positive voltage level shifter and a driver.3. The decoder circuit of claim 2 , wherein the predecode logic to receive one or more address bits to determine whether the predecoder is associated with a conductive array line of the plurality of conductive array lines that is used to access a memory cell in the memory array and to receive mode control signals to determine which of the negative voltage level shifter and the positive voltage level shifter can be used to generate the control signal.4. The decoder circuit of claim 2 , wherein the driver comprises:a first portion to operate during a programming operation of the memory array; anda second ...

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Номер записи: 73

26-01-2017 дата публикации

HYBRID CHIP COMPRISING HYBRID CONNECTOR

Номер: US20170026041A1

Автор: CHO Thomas Byunghak, CHOI Jongwon, HAN SANGWOOK, Lee Joonhee, LEE Sung-Jun, Lim Jaehyun

Принадлежит:

An integrated circuit (IC), a method of testing the IC, and a method of manufacturing the IC are provided. The IC includes analog circuitry, digital circuitry, at least one first connector, and a switching unit operatively coupled with the at least one first connector and configured to, if a first signal is received, couple the analog circuitry and the at least one first connector, and, if a second signal is received, couple the digital circuitry and the at least one first connector. 1. An integrated circuit (IC) , comprising:analog circuitry;digital circuitry;at least one first connector; anda switching unit operatively coupled with the at least one first connector and configured to:if a first signal is received, couple the analog circuitry and the at least one first connector, andif a second signal is received, couple the digital circuitry and the at least one first connector.2. The IC of claim 1 , further comprising:at least one second connector operatively coupled with the analog circuitry; andat least one third connector operatively coupled with the digital circuitry.3. The IC of claim 2 , wherein the analog circuitry is configured to receive at least one first analog signal and at least one second analog signal claim 2 , whereinif the switching unit receives the first signal, the at least one first analog signal is received from at least one electronic device through the at least one first connector, andthe at least one second analog signal is received from the at least one electronic device through the at least one second connector.4. The IC of claim 3 , wherein the digital circuitry is configured to receive at least one first digital signal and at least one second digital signal claim 3 , whereinif the switching unit receives the second signal, the at least one first digital signal is received from at least one electronic device through the at least one first connector, andthe at least one second digital signal is received from the at least one electronic ...

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Номер записи: 74

28-01-2016 дата публикации

NAND GATE CIRCUIT, DISPLAY BACK PLATE, DISPLAY DEVICE AND ELECTRONIC DEVICE

Номер: US20160028398A1

Автор: DUAN Liye, Song Danna, Wu Zhongyuan

Принадлежит: BOE Technology Group Co., Ltd.

The NAND gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module. The input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level. The at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection therebetween when none of the input signals is at the second level. 1. An NAND gate circuit , comprising at least two input transistors , a gate electrode of each input transistor being connected to an input signal , a first electrode of a first input transistor being connected to an NAND gate output end , a second electrode of a last input transistor being connected to a first level , and apart from the last input transistor , a second electrode of each input transistor being connected to a first electrode of a next input transistor , whereinthe NAND gate circuit further comprises at least two pull-up modules and at least two input control transistors,a gate electrode of each input control transistor is connected to the input signal, a first electrode thereof is connected to a control end of the corresponding pull-up module, and a second electrode thereof is connected to the first level,the first electrode of the first input transistor is connected to a second level output end via the pull-up module,the input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate ...

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Номер записи: 75

25-01-2018 дата публикации

LEVEL SHIFTER

Номер: US20180026627A1

Автор: SHIN HO-YOUNG

Принадлежит:

A level shifter includes a driving circuit, which receives an input signal and outputs a driving signal in response to a first voltage level of the input signal; a level shifting circuit, which outputs an output signal of a second voltage level in response to the driving signal; and a leakage prevention circuit, which prevents a leakage current of the driving circuit, wherein the driving circuit may include at least one native transistor. 1. A level shifter , comprising:a driving circuit, which is configured to receive an input signal and to output a driving signal in response to a first voltage level of the input signal;a level shifting circuit, which is configured to output an output signal of a second voltage level in response to the driving signal; anda leakage prevention circuit, which is configured to prevent a leakage current of the driving circuit,wherein the driving circuit comprises at least one native transistor.2. The level shifter of claim 1 , wherein:the driving circuit comprises a first native transistor and a second native transistor that operate complementarily with each other, andthe level shifting circuit comprises a first high voltage transistor and a second high voltage transistor that operate complementarily with each other.3. The level shifter of claim 2 , further comprising a damage prevention circuit that prevents damage to the leakage prevention circuit.4. The level shifter of claim 3 , wherein:the second voltage level is greater than the first voltage level, andthe first voltage level is less than the threshold voltages of the first high voltage transistor and the second high voltage transistor.5. The level shifter of claim 3 , further comprising a contention preventing circuit that reduces possible contention between the level shifting circuit and the driving circuit.6. The level shifter of claim 3 , wherein:the leakage prevention circuit comprises at least one low voltage transistor, andthe damage prevention circuit comprises at least ...

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Номер записи: 76

25-01-2018 дата публикации

A SEMICONDUCTOR LOGIC ELEMENT AND A LOGIC CIRCUITRY

Номер: US20180026639A1

Автор: AUROLA Artto

Принадлежит:

Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element. 1. A semiconductor logic element comprising a field effect transistor of the first conductivity type hereinafter referred to as the first FET and a field effect transistor of the second conductivity type hereinafter referred to as the second FET; wherein the semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with a drain of the first FET and a gate of the second FET , wherein the gate of the first FET is hereinafter referred to as an input of the semiconductor logic element , wherein the input is configured to be coupled either to a first input logic potential or to a second input logic potential , wherein the drain of the second FET is referred to as the output of the semiconductor logic element , wherein a source of the second FET is the source of the semiconductor logic element , wherein the semiconductor logic element is configured so that when a source of the first FET is arranged at a first source potential and when the source of the second FET is at a first output logic potential and when the input is at the first input logic potential , a conductive channel comprising mobile first conductivity type charge carriers is established between the source of the first FET and the drain of the first FET adjusting the internal node to first source potential ...

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Номер записи: 77

10-02-2022 дата публикации

AMPLIFYING APPARATUS

Номер: US20220045652A1

Автор: Cheng Ting-Yuan

Принадлежит: RICHWAVE TECHNOLOGY CORP.

An amplifying apparatus includes a zero point generating circuit, a level shift circuit, a transistor, and an amplifying circuit. A first terminal of the zero point generating circuit is coupled to an output terminal of the amplifying apparatus. A first terminal of the level shift circuit is coupled to the output terminal of the amplifying apparatus. A first terminal of the transistor is coupled to a supply voltage. A second terminal of the transistor is coupled to the output terminal of the amplifying apparatus. A control terminal of the transistor is coupled to a second terminal of the level shift circuit. An input terminal of the amplifying circuit is coupled to an input terminal of the amplifying apparatus. An output terminal of the amplifying circuit is coupled to the output terminal of the amplifying apparatus. 1. An amplifying apparatus , comprising:a zero point generating circuit, having a first terminal coupled to a first output terminal of the amplifying apparatus;a first level shift circuit, having a first terminal directly coupled to the first output terminal of the amplifying apparatus;a first transistor, having a first terminal coupled to a first supply voltage, wherein a second terminal of the first transistor is coupled to the first output terminal of the amplifying apparatus, and a control terminal of the first transistor is coupled to a second terminal of the first level shift circuit;a first amplifying circuit, having an input terminal coupled to a first input terminal of the amplifying apparatus, wherein an output terminal of the first amplifying circuit is coupled to the first output terminal of the amplifying apparatus, a capacitive circuit, having a first terminal coupled to a second terminal of the zero point generating circuit, wherein a second terminal of the capacitive circuit is coupled to a third terminal of the zero point generating circuit; and', 'a resistive circuit, having a first terminal coupled to the first terminal of the zero ...

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Номер записи: 78

10-02-2022 дата публикации

LEVEL CONVERTER CIRCUIT

Номер: US20220045665A1

Автор: Cesar Etienne

Принадлежит:

An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature. 1. A level converter circuit comprising:a first input configured to receive, as a current supply, a current proportional to a temperature.2. The level converter circuit according to claim 1 , further comprising a first inverter circuit comprising a first transistor of a first type and a second transistor of a second type.3. The level converter circuit according to claim 2 , wherein the first and second transistors are metal-oxide-semiconductor (MOS) transistors.4. The level converter circuit according to claim 3 , wherein the first transistor is an N-type MOS transistor and the second transistor is a P-type MOS transistor.5. The level converter circuit according to claim 2 , wherein a gate of the second transistor is configured to receive the current proportional to the temperature.6. The level converter circuit according to claim 2 , wherein a gate of the first transistor is configured to receive an input signal.7. The level converter circuit according to claim 6 , wherein the input signal is representative of a binary value and has a variable high voltage level.8. The level converter circuit according to claim 7 , wherein the variable high voltage level is randomly variable between two voltage levels.9. The level converter circuit according to claim 2 , wherein the first and second transistors are part of a conversion circuit within the level converter circuit.10. The level converter circuit according to claim 1 , further comprising a current supply circuit configured to supply the current proportional to the temperature.11. The level converter circuit according to claim 10 , further comprising:a first inverter circuit comprising a first transistor of a first type and a second transistor of a second type, wherein:the first and second transistors are part of a conversion circuit within the level converter circuit; andthe conversion circuit and ...

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Номер записи: 79

10-02-2022 дата публикации

DRIVE CIRCUIT, DRIVE METHOD, AND SEMICONDUCTOR SYSTEM

Номер: US20220045671A1

Автор: AKAHANE Masashi

Принадлежит:

A drive circuit includes: a control section generating a control signal; a first level shift section raising a level of a signal from the control section; a high side drive section controlling a semiconductor device; and a second level shift section lowering a level of a signal from the high side drive section for input to the control section. The high side drive section has an error detection section maintaining an output of an error detection signal when the semiconductor device is in an error status until a release signal is input, the control section has an error handling section outputting the release signal to the high side drive section via the first level shift section when the error detection signal is input via the second level shift section, and the error detection section stops the output of the error detection signal when the release signal is input. 1. A drive circuit of a semiconductor device comprising:a control section configured to output (i) a control signal in accordance with an input signal and (ii) a release signal when an error detection signal is input thereto;a first level shift section configured to raise a level of the control signal and a level of the release signal input from the control section;a high side drive section configured to control the semiconductor device based on the control signal of which the level has been raised by the first level shift section; anda second level shift section configured to lower a level of a signal from the high side drive section for input to the control section, whereinthe high side drive section has an error detection section configured to output the error detection signal when the semiconductor device is in an error status, and maintain the output of the error detection signal until the release signal of which the level has been raised by the first level shift section is input, a control signal generation section configured to generate the control signal in accordance with the input signal;', 'an ...

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Номер записи: 80

10-02-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220045681A1

Автор: Kinugasa Masanori, Wakahoi Tooru

Принадлежит:

According to one embodiment, a semiconductor device includes first, second, third, and fourth circuits. A first voltage is applied to the first circuit. A second voltage is applied to each of the second, third and fourth circuits. The third circuit is configured to generate a first control signal and a second control signal based on a signal generated by the first circuit and a signal generated by the second circuit. The fourth circuit is configured to output an output signal based on the first control signal and the second control signal. The output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied. 1. A semiconductor device comprising:a first circuit to which a first voltage is applied and which is capable of receiving a first input signal and a second input signal and is capable of generating a first signal based on the first input signal, a second signal based on the second input signal, and a third signal obtained by inverting a logic level of the second signal;a second circuit to which a second voltage different from the first voltage is applied and which is capable of receiving the second input signal and is capable of generating a fourth signal based on the second input signal and a fifth signal obtained by inverting a logic level of the fourth signal;a third circuit to which the second voltage is applied and which is capable of generating a first control signal based on the first signal, the second signal, and the fourth signal, and a second control signal based on the first voltage, the first signal, the third signal, and the fifth signal; anda fourth circuit to which the second voltage is applied and which is capable of outputting an output signal based on the first control signal and the second control signal,wherein the output signal is brought to a high impedance state when at least one of the first voltage or the second voltage is not applied.2. The device according to claim 1 , ...

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Номер записи: 81

10-02-2022 дата публикации

LEVEL SHIFTERS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME

Номер: US20220045682A1

Автор: Seong Ki Hwan

Принадлежит:

A level shifter includes an input circuit configured to generate and output first and second intermediate signals based on an input signal that transitions between a first voltage level and a second voltage level. The level shifter includes a feed forward circuit configured to receive the first intermediate signal from the input circuit and generate and output a third intermediate signal enabled in a part of a period in which the first intermediate signal is enabled and to receive the second intermediate signal from the input circuit and generate and output a fourth intermediate signal enabled in a part of a period in which the second intermediate signal is enabled. Moreover, the level shifter includes a level shifting circuit configured to receive the first through fourth intermediate signals and to shift the input signal to an output signal that transitions between a third voltage level and the second voltage level. 1. A level shifter comprising:an input circuit configured to generate and output first and second intermediate signals based on an input signal that transitions between a first voltage level and a second voltage level;a feed forward circuit configured to receive the first intermediate signal from the input circuit and generate and output a third intermediate signal enabled in a part of a period in which the first intermediate signal is enabled and to receive the second intermediate signal from the input circuit and generate and output a fourth intermediate signal enabled in a part of a period in which the second intermediate signal is enabled; anda level shifting circuit configured to receive the first and second intermediate signals from the input circuit and the third and fourth intermediate signals from the feed forward circuit and to shift the input signal to an output signal that transitions between a third voltage level and the second voltage level, wherein the third voltage level is different from the first voltage level.2. The level shifter of ...

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Номер записи: 82

23-01-2020 дата публикации

Semiconductor Device, and Display Device and Electronic Device Utilizing the Same

Номер: US20200027420A1

Автор: Kimura Hajime, Shionoiri Yutaka

Принадлежит:

A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased. 1. (canceled)2. A semiconductor device comprising:a first transistor;a second transistor;a third transistor;a fourth transistor; anda fifth transistor,wherein:one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;a gate of the first transistor is electrically connected to a first wiring;the one of the source and the drain of the first transistor is electrically connected to a gate of the third transistor;a gate of the first transistor is electrically connected to a second wiring;one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;the other of the source and the drain of the third transistor is electrically connected to a third wiring;the other of the source and the drain of the fourth transistor is electrically connected to a fourth wiring;one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring;the other of the source and the drain of the fifth transistor is electrically connected to a fifth wiring; anda gate of the fifth transistor is electrically connected to a second wiring.3. The semiconductor device according to claim 2 , wherein the first ...

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Номер записи: 83

23-01-2020 дата публикации

GATE STRUCTURE AND METHODS THEREOF

Номер: US20200027964A1

Автор: CHENG Anhao, KUO Fang-Ting

Принадлежит:

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided. 1. A semiconductor device , comprising:a substrate including a gate dielectric trench within an active region of the substrate, wherein the active region is free of a shallow trench isolation feature;a first dielectric layer formed within the gate dielectric trench, wherein a top surface of the first dielectric layer is level with a top surface of the substrate;a second dielectric layer disposed over the first dielectric layer; anda metal gate disposed over the second dielectric layer;wherein the first dielectric layer and the second dielectric layer provide a gate oxide of the semiconductor device.2. The semiconductor device of claim 1 , further including a source region and a drain region formed within the substrate and on either side of the gate dielectric trench.3. The semiconductor device of claim 2 , wherein the gate dielectric trench has a first depth claim 2 , and wherein the source region and the drain region extend into the substrate a second depth greater than the first depth.4. The semiconductor device of claim 1 , wherein the gate dielectric trench has a first width along a plane parallel to the top surface of the substrate claim 1 , and wherein the ...

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Номер записи: 84

23-01-2020 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20200028510A1

Автор: HONG Gi Moon, KIM Kyung Hoon

Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes an input selection circuit that selects one of a first input signal and a second input signal in response to a control signal, and outputs the selected input signal as a selection signal, wherein swing levels of the first input signal and the second input signal are different one another. The semiconductor apparatus also includes a conversion circuit that generates an output signal, in response to the selection signal, which swings to a level substantially identical to a level of the second input signal. 1. A semiconductor apparatus comprising:an input selection circuit configured to select one of a first input signal and a second input signal in response to a control signal and configured to output the selected input signal as a selection signal, wherein swing levels of the first input signal and the second input signal are different from one another; anda conversion circuit configured to generate an output signal, in response to the selection signal, wherein the output signal swings to a level substantially identical to a level of the second input signal,wherein the input selection circuit comprises:a first input circuit configured to transfer the first input signal to an output circuit;a second input circuit configured to transfer the second input signal to the output circuit based on the control signal; andthe output circuit configured to perform at least one of an inverting operation and a resistive feedback inverting operation on the first and second input signals, received from the first and second input circuits, based on the control signal and output a result of the operation as the selection signal.2. The semiconductor apparatus according to claim 1 , wherein the first input signal swings to a current mode logic (CML) level and the second input signal swings to a complementary metal-oxide semiconductor (CMOS) level.3. (canceled)4. The semiconductor apparatus according to claim 1 , wherein an output terminal of the first ...

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Номер записи: 85

28-01-2021 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Номер: US20210028786A1

Автор: NAKATA Shinichiro

Принадлежит:

A semiconductor integrated circuit device includes digital output terminals and output circuits. Each output circuit includes a switch, and applies a potential, which corresponds to either one of binary logic levels, to corresponding one of the digital output terminals through the switch. An indefinite range is interposed between one of the binary logic levels and the other one of the binary logic levels. The output circuits respectively include potential fixers. Each potential fixer has an identical circuit arrangement, and the potential fixer fixes a potential applied to the digital output terminals through the switch to a potential corresponding to either one of the binary logic levels apart from the indefinite range, in response to that a short circuit occurs between the digital output terminals. 1. A semiconductor integrated circuit device comprising:a plurality of digital output terminals being adjacent to each other; anda plurality of output circuits, each output circuit including a switch and configured to apply a potential, which corresponds to either one of binary logic levels, to the digital output terminals through the switch,wherein an indefinite range is interposed between the binary logic levels,wherein the output circuits respectively include potential fixers, andwherein the potential fixers have identical circuit arrangement, and each potential fixer is configured to fix a potential applied to corresponding one of the digital output terminals through the switch to a potential corresponding to either one of the binary logic levels apart from the indefinite range, in response to that a short circuit occurs between the digital output terminals.2. The semiconductor integrated circuit device according to claim 1 ,wherein the digital output terminals are disposed adjacent to each other at an identical side of a package of the semiconductor integrated circuit device.3. The semiconductor integrated circuit device according towherein the output circuits ...

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Номер записи: 86

05-02-2015 дата публикации

High Speed Level Shifter with Amplitude Servo Loop

Номер: US20150035563A1

Автор: Cao Jun, Hu Kangmin, Momtaz Afshin Doctor, NAZEMI Ali

Принадлежит: BROADCOM CORPORATION

A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture. 1. A circuit comprising:a supply input configured to provide a target high output level;a signal input configured to carry an input signal;a signal output configured to carry an output signal; and an amplitude control circuit connected to the supply input and the signal output;', 'an overvoltage protection circuit in series with the amplitude control circuit; and', 'a switching circuit in series with the overvoltage protection circuit and connected to the signal input., 'level translation circuitry configured to generate the output signal by shifting the input signal between a target low output level and the target high output level, the level translation circuitry comprising2. The circuit of claim 1 , where:the amplitude control circuit comprises an amplitude control transistor.3. The circuit of claim 1 , where:the overvoltage protection circuit comprises a cascode connected transistor in series with the amplitude control circuit and the switching circuit.4. The circuit of claim 1 , where:the amplitude control circuit comprises an amplitude control transistor;the amplitude control transistor comprises a gate; and where:the gate is connected to an amplitude control gate voltage.5. The circuit of claim 4 , further comprising:a feedback loop configured to provide the amplitude control gate voltage.6. The circuit of claim 5 , where the feedback loop comprises:a reference voltage input;a feedback voltage input connected to the signal output; ...

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Номер записи: 87

04-02-2016 дата публикации

Output Signal Generation Circuitry for Converting an Input Signal From a Source Voltage Domain Into an Output Signal for a Destination Voltage Domain

Номер: US20160036441A1

Автор: Dey Ranabir, Rien Mikael, Vinukonda Vijaya Kumar

Принадлежит:

Output signal generation circuitry may be used for converting an input signal from a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitry operating from the supply voltage, which is configured to generate at an output node the output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitry A, B, C, D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal. Timing compensation circuitry A, B may also be provided, to control the voltage on the output node in a manner to compensate for the delay introduced by the tracking circuitry. 120-. (canceled)21. An apparatus for converting an input signal from a source voltage domain to an output signal for a destination voltage domain , comprising:level shifting circuitry operating from a supply voltage, configured to generate at an output node the output signal for the destination voltage domain in dependence on the input signal;tracking circuitry associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component is less than or equal to the stressing threshold; andtiming compensation circuitry configured to control a voltage on the output node to compensate for a delay introduced by the tracking circuitry.22. The apparatus of claim 21 , wherein the delay is associated with a change in the output signal in response to a change in the input signal.23. The ...

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Номер записи: 88

04-02-2016 дата публикации

Level shifting apparatus and method of using the same

Номер: US20160036442A1

Автор: Chan-Hong Chern, Chih-Chang Lin, Ming-Chieh Huang, Tsung-Ching (Jim) Huang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A level shifting apparatus includes a first capacitor, a first side of the first capacitor configured to receive a first voltage. The level shifting apparatus further includes an edge detector configured to receive the first voltage. The level shifting apparatus further includes an output inverter connected to a second side of the first capacitor, the output inverter configured to output an voltage-level shifted signal of the level shifting apparatus. The level shifting apparatus further includes a latch loop configured to receive feedback the output signal to an input of the output inverter, wherein the edge detector is configured to selectively interrupt feedback of the output signal to the input of the output inverter.

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Номер записи: 89

04-02-2016 дата публикации

Receiver Circuitry and Method for Converting an Input Signal From a Source Voltage Domain Into an Output Signal for a Destination Voltage Domain

Номер: US20160036445A1

Автор: Mikael Rien, Ranabir Dey, Vijaya Kumar Vinukonda

Принадлежит: ARM LTD

The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range. Signal evaluation circuitry establishes a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and employs the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level (in either direction). Output generation circuitry then generates the output signal in dependence on the detection performed by the signal evaluation circuitry. The first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry. The receiver circuitry is able to reliably detect transitions in the input signal in situations where the supply voltage of the source voltage domain exceeds the stressing threshold of the receiver's components, but without overstress of the receiver's components.

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Номер записи: 90

01-02-2018 дата публикации

LEVEL SHIFTER

Номер: US20180034466A1

Автор: Duncan Joseph, PHILPOTT Justin, WALKER Brett, YUNG Chi Fan, ZHANG Zhiqing

Принадлежит:

Certain aspects of the present disclosure provide methods and apparatus for level shifting an input signal ranging between certain voltage levels to generate an output signal ranging between other voltage levels with low power, high speed, and immunity to noise. One example level-shifting circuit generally includes a node for receiving an input signal ranging between a first voltage level and a second voltage level, a first circuit path coupled to the node and configured to level shift the input signal to generate an output signal ranging between a third voltage level and a fourth voltage level, a pulse generator coupled to the node and configured to generate a pulse based on a transition in the input signal between the first and second voltage levels, and a second circuit path connected in parallel with the first path and configured to temporarily short the first path based on the generated pulse. 1. A level-shifting circuit comprising:an input node for receiving an input signal ranging between a first voltage level and a second voltage level;a first circuit path coupled to the input node and configured to level shift the input signal to generate an output signal ranging between a third voltage level and a fourth voltage level;a pulse generator coupled to the input node and configured to generate a pulse based on a transition in the input signal between the first and second voltage levels; anda second circuit path connected in parallel with the first circuit path and configured to temporarily short the first circuit path based on the generated pulse.2. The level-shifting circuit of claim 1 , wherein the second circuit path comprises a first transistor having:a gate coupled to an output of the pulse generator and configured to receive the generated pulse;a drain coupled to a first terminal of the first circuit path; anda source coupled to a second terminal of the first circuit path.3. The level-shifting circuit of claim 2 , wherein the first circuit path comprises a ...

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Номер записи: 91

17-02-2022 дата публикации

COMMUNICATION DEVICE, AND ELECTRONIC DEVICE COMPRISING SAME

Номер: US20220052692A1

Автор: BYEON Sunghoon, HA Jonghun, JO Suho, KIM Hwasung, YU Odo

Принадлежит:

A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit. 1. A communication device , comprising:a transmission circuit configured to generate a transmission signal by using a signal input from a first control circuit and a first field effect transistor (FET), and transmit the transmission signal to a second control circuit; anda reception circuit configured to generate a reception signal by using a signal received from the second control circuit and a second field effect transistor (FET), and output the reception signal to the first control circuit.2. The communication device of claim 1 , wherein the transmission circuit is configured to generate claim 1 , based on a voltage level of the first control circuit being lower than a voltage level of the second control circuit claim 1 , the transmission signal by performing a level shift to a signal inputted from the first control circuit claim 1 , andwherein the reception circuit is configured to generate, based on a voltage level of the first control circuit being lower than a voltage level of the second control circuit, the reception signal by performing a level shift to a signal received from the second control circuit.3. The communication device of claim 1 , wherein the reception circuit is configured to have a symmetrical structure with the transmission circuit.4. The communication device of claim 1 , wherein the transmission circuit further comprises:a first resistance configured for one end to be connected to the first control circuit, and ...

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Номер записи: 92

31-01-2019 дата публикации

HIGH VOLTAGE LEVEL SHIFTING (HVLS) CIRCUIT AND RELATED SEMICONDUCTOR DEVICES

Номер: US20190036532A1

Автор: KWON Yi Jin, Ni Hao, Yin Chang Wei, Yu Hong

Принадлежит:

A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process. 1. A high voltage level shifting (HVLS) circuit , comprising:a level conversion circuit comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, with the first and the second transistors having a first conductivity type and the third and the fourth transistors having a second conductivity type, wherein the level conversion circuit converts an input signal having a first high voltage to an output signal having a second high voltage that is higher than the first high voltage, and wherein the first transistor is connected to the third transistor at a first connection node, the second transistor is connected to the fourth transistor at a second connection node, and a control node of the first transistor is connected to a control node of the second transistor;a first switch having a first node connected to a first power source and a second node connected to the control node of the first transistor;a second switch having a first node connected to the control node of the first transistor and a second node connected to the first connection node; anda switch control circuit connected to the first switch and the ...

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Номер записи: 93

12-02-2015 дата публикации

LEVEL SHIFTER

Номер: US20150042393A1

Автор: CHEN AN-TUNG, Kuo Chien-Liang, Lee Kuo-Chung, Wang Jo Yu

Принадлежит: RICHTEK TECHNOLOGY CORP

A level shifter includes an input stage circuit, a latch circuit and a transient speed-up circuit. The input stage circuit receives an input signal. The latch circuit is coupled to the input stage circuit through a first output terminal and a second output terminal, and determining steady-state levels of the first and the second output terminals according to the input signal. The transient speed-up circuit is coupled to the first and the second output terminals. When the transient speed-up circuit determines the first and the second output terminals are at the same logic level, the transient speed-up circuit accelerates the positive edge transition of the first or the second terminals. 1. A level shifter , comprising:an input stage circuit, receiving a first input signal and a second input signal, wherein the voltage levels of the first input signal and the second input signal are in an input level section, and the first input signal and the second input signal are out-of-phase;a latch circuit, coupled to the input stage circuit through a first output terminal and a second output terminal, the latch circuit and the input stage circuit determining the steady-state levels of the first output terminal and the second output terminal according to the first input signal and the second input signal, wherein the voltage levels of the first output terminal and the second output terminal are in an output level section, which is defined by a voltage on an output reference voltage terminal and a voltage on the ground terminal; and a first OR gate, having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal and the second input terminal of the first OR gate are coupled to the second output terminal and the first output terminal respectively, and the voltage level of an output signal of the first OR gate is in the output level section;', 'a fifth transistor, a control terminal of the fifth transistor coupled to the output ...

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Номер записи: 94

04-02-2021 дата публикации

VOLTAGE LEVEL SHIFTER

Номер: US20210036704A1

Автор: DEBNATH Sankar, MUDIMELA VENKATA Krishna Reddy, SHETTY Sneha

Принадлежит:

A circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal coupled to the second current terminal. 1. A circuit , comprising:a first transistor having a first control input and first and second current terminals;a second transistor having a second control input and third and fourth current terminals;a third transistor having a third control input and fifth and sixth current terminals, the third control input coupled to the third current terminal, and the fifth current terminal coupled to a supply voltage node;a fourth transistor having a fourth control input and seventh and eighth current terminals, the fourth control input coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node; anda fifth transistor having a fifth control input and ninth and tenth current terminals, the fifth control input coupled to an output node of the circuit;a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the sixth control input coupled to the first current terminal, the eleventh current terminal coupled to the tenth current terminal, and the twelfth current terminal coupled to the third current terminal;an inverter ...

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Номер записи: 95

12-02-2015 дата публикации

Serial communication apparatus

Номер: US20150043663A1

Автор: Yoshiaki Ishizeki

Принадлежит: RENESAS ELECTRONICS CORPORATION

A serial communication apparatus includes a slew rate control circuit, an output circuit, a detection circuit, and a switching circuit. The slew rate control circuit has a predetermined impedance, and supplies a constant current from an output according to an input signal. In the output circuit, first capacitance is charged and discharged by the constant current from the slew rate control circuit. The output circuit outputs a digital signal from an output terminal according to a drive voltage. The noise detection circuit detects noise propagated from the output terminal, and outputs a switching signal according to a detection result. The switching circuit switches an impedance of the slew rate control circuit to a value smaller than the predetermined impedance according to the switching signal.

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Номер записи: 96

11-02-2016 дата публикации

TRANSISTOR SWITCH WITH BACK-GATE BIASING

Номер: US20160043722A1

Автор: Fan Yanli, Hu Yaqi

Принадлежит:

Driving a back-gate of a transistor with a follower signal that corresponds to an information signal. At least some of the illustrative embodiments are methods including: passing an information signal from a source terminal to an drain terminal of a main field effect transistor (FET), the information signal has a peak-to-peak voltage; generating a follower signal that corresponds to the information signal, the follower signal electrically isolated from the information signal, and the follower signal has a peak-to-peak voltage lower than the peak-to-peak voltage of the information signal; and applying the follower signal to a back-gate of the main FET. 1. A method , comprising:passing an information signal from a source terminal to a drain terminal of a main field effect transistor (FET), the information signal having a peak-to-peak voltage;generating a follower signal that corresponds to the information signal, the follower signal electrically isolated from the information signal, and the follower signal has a peak-to-peak voltage lower than the peak-to-peak voltage of the information signal; andapplying the follower signal to a back-gate of the main FET.2. The method of claim 1 , further comprising: grounding a gate of the main FET;', 'grounding the back-gate of the main FET; and', 'ceasing the generation of the follower signal., 'detecting that a select signal is not asserted, and responsive to the detecting that the select signal is not asserted3. The method of wherein grounding the back-gate further comprises grounding the back-gate through a first transistor.4. The method of further comprising claim 3 , responsive to the detecting that the select signal is not asserted claim 3 , grounding the gate of the main FET through a second transistor.5. The method of wherein generating the follower signal further comprises:operating a first follower transistor in an active region by driving a gate of the first follower transistor with the information signal; and ...

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Номер записи: 97

04-02-2021 дата публикации

INTERFACE CIRCUIT, CHIP CONTAINING INTERFACE CIRCUIT AND MANUFACTURING METHOD THEREOF

Номер: US20210037643A1

Автор: CHEN Xiangbing

Принадлежит:

Disclosed is an interface circuit, a chip containing an interface circuit and a manufacturing method thereof. The interface circuit includes an I/O processing sub-circuit, a path selection sub-circuit, and at least two I/O ports. The I/O processing sub-circuit, the path selection sub-circuit, and the at least two I/O ports are electrically connected in sequence. The path selected by the path selection sub-circuit can enable a first and a second electrical signal to be transmitted through the I/O ports that are configured to correspond to the ports of the external device through which the first and second electrical signals are transmitted. That is, the path selection sub-circuit can customize the layout of the signal-input/output I/O ports of the interface circuit according to the layout of the ports of the external device. 1. An interface circuit , comprising:an I/O processing sub-circuit;a path selection sub-circuit; andat least two I/O ports;wherein the I/O processing sub-circuit, the path selection sub-circuit, and the at least two I/O ports are electrically connected in sequence;the I/O processing sub-circuit is configured to generate a first electrical signal to the path selection sub-circuit, and receive a second electrical signal fed back by the path selection sub-circuit;the path selection sub-circuit is configured to select a path to output the first electrical signal to one of the at least two I/O ports; and select a path to feed the second electrical signal that is received by one of the at least two I/O ports from an external device for the interface circuit back to the I/O processing sub-circuit, where the at least two I/O ports are configured to correspond to ports used by the external device for transmitting the first electrical signal or the second electrical signal.2. The interface circuit according to claim 1 , wherein the path selection sub-circuit comprises a first path selection sub-circuit and a second path selection sub-circuit claim 1 , each ...

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Номер записи: 98

09-02-2017 дата публикации

Overdrive Receiver Circuitry

Номер: US20170041002A1

Автор: Dey Ranabir, Kyatsandra Vikas Murli, Rien Mikael, Vinukonda Vijaya Kumar

Принадлежит:

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include signal generation circuitry that receives an input signal from a first voltage domain and generates multiple internal signals based on the input signal. The integrated circuit may include signal evaluation circuitry that receives the multiple internal signals from the signal generation circuitry and provides an intermediate signal based on the multiple internal signals. The integrated circuit may include signal conversion circuitry that receives the intermediate signal and provides an output signal for a second voltage domain based on the intermediate signal. The integrated circuit may include signal protection circuitry that receives the input signal from the first voltage domain, receives the intermediate signal from the signal evaluation circuitry, and allows the input signal until the intermediate signal transitions between a first state and a second state that is different than the first state. 1. An integrated circuit , comprising:signal generation circuitry that receives an input signal from a first voltage domain and generates multiple internal signals based on the input signal;signal evaluation circuitry that receives the multiple internal signals from the signal generation circuitry and provides an intermediate signal based on the multiple internal signals;signal conversion circuitry that receives the intermediate signal and provides an output signal for a second voltage domain based on the intermediate signal, wherein the second voltage domain is different than the first voltage domain; andsignal protection circuitry that receives the input signal from the first voltage domain, receives the intermediate signal from the signal evaluation circuitry, and allows the input signal until the intermediate signal transitions between a first state and a second state that is different than the first state.2. The integrated circuit of claim 1 , wherein ...

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Номер записи: 99

24-02-2022 дата публикации

MILLER CLAMP PROTECTION CIRCUIT, DRIVING CIRCUIT, DRIVING CHIP AND INTELLIGENT IGBT MODULE

Номер: US20220060014A1

Автор: FANG Min Jennifer, ZENG Zhuo

Принадлежит:

Disclosed are a Miller Clamp protection circuit, a driving circuit, a driving chip and an intelligent IGBT module, which are connected to a device to be driven. The Miller Clamp protection circuit comprises a main driving circuit configured to provide a driving signal; a Miller switch configured to reduce a voltage glitch; a Miller switch control circuit configured to automatically control an on and off of the Miller switch according to an intermediate signal of the main driving circuit. The main driving circuit is connected to a power supply, the Miller switch control circuit, one end of the Miller switch and the device to be driven, and another end of the Miller switch is grounded. 1. A Miller Clamp protection circuit being connected to a device to be driven , and comprising:a main driving circuit configured to provide a driving signal;a Miller switch configured to reduce a voltage glitch;a Miller switch control circuit configured to automatically control a on and off of the Miller switch according to an intermediate signal from the main driving circuit;the main driving circuit is connected to a power supply, the Miller switch control circuit, one end of the Miller switch and the device to be driven, and another end of the Miller switch is grounded.2. The Miller Clamp protection circuit according to claim 1 , wherein the main driving circuit comprises:a level shifter configured to level shift;a delay matching circuit configured to delay matching;an output driving circuit configured to output a driving signal;a current limiting circuit configured to limit an output current of an output signal;the level shifter, the delay matching circuit, the output driving circuit, and the current limiting circuit are connected in sequence, the level shifter is also connected to the Miller switch control circuit.3. The Miller Clamp protection circuit according to claim 2 , wherein the current limiting circuit comprises a first resistor claim 2 , one end of the first resistor is ...

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Номер записи: 100