ROOT MONITORING ON AN FPGA USING SATELLITE ADCS

Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuity configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY

System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

CIRCUITS AND METHODS FOR SUPPLY VOLTAGE DETECTION AND TIMING MONITORING

A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY

System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

Methods for programing DDR compatible open architecture resistive change element arrays

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized ...

Training and operations with a double buffered memory topology

System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

Supply voltage compensation for an input/output driver circuit using clock signal frequency comparison

A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.

ROOT MONITORING ON AN FPGA USING SATELLITE ADCS

Small-size, multi-channel and high-isolation switch matrix

Training and operations with a double buffered memory topology

System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

Reconfigurable logic gate device based on magnetic skyrmion crystal

The invention discloses a reconfigurable logic gate device based on a magnetic Skyrmion crystal. The device realizes two logic functions of a NOT gate and an AND gate based on a Hall effect motion characteristic of the Skyrmion crystal in a direction perpendicular to a driving current direction under the driving of the current. The device is of a Hall strip structure and comprises a cross-shaped multilayer film, a current input end, a magnetic field input end and an output end. The cross-shaped multilayer film sequentially comprises a protective layer, a ferromagnetic layer, a heavy metal layer and a substrate layer from top to bottom. The ferromagnetic layer is a chiral magnetic film, and under the action of a magnetic field, the Skyrmion crystal can stably exist. The heavy metal layer is a heavy metal film with a spin Hall angle larger than 0.1. When serving as a NOT gate, the magnetic field input end serves as an enable end, and the current input end serves as an input end. And when ...

Circuits And Methods For Detecting Decreases In A Supply Voltage In An Integrated Circuit

An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.

METHODS FOR PROGRAMING DDR COMPATIBLE OPEN ARCHITECTURE RESISTIVE CHANGE ELEMENT ARRAYS

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized ...

Training and operations with a double buffered memory topology

System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

Resistive change element arrays using a reference line

A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized ...

TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY

System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

Logic circuits with augmented arithmetic densities

Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic cell. A logic cell may include four 4-input lookup tables (LUTs) coupled to an adder carry chain. Each of the four 4-input LUTs may include two 3-input LUTs and a selector multiplexer. The carry chain may include at three or more full adder circuits. The outputs of the 3-input LUTs may be directly connected to inputs of the full adder circuits in the carry chain. By providing at least the same or more number of full adder circuits as the total number of 4-input LUTs in the logic cell, the arithmetic density of the logic is enhanced.

Ring based impedance control of an output driver

In one embodiment, there is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

Semiconductor device and method of adjusting characteristic thereof

To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Method for improving writability of sram memory

A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Memory and method for sensing data in a memory using complementary sensing scheme

In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

Phase change memory device

A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

High resolution output driver

High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

Semiconductor device, circuit board device, and information processing device

In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Differential data sensing

A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Semiconductor device

The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

Driver Calibration Methods and Circuits

Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Semiconductor device operates on external and internal power supply voltages and data processing system including the same

The semiconductor device including an output terminal; and an output unit coupled to the output terminal. The output unit includes an output buffer coupled to the output terminal and operating on a first power supply voltage, a first control circuit operating on a second power supply voltage, receiving an impedance adjustment signal and a data signal and making the output buffer drive the output terminal to a first logic level designated by the data signal with impedance designated by the impedance adjustment signal, and a level shifter coupled between the output buffer and the first control circuit. The second power supply voltage is smaller in level than the first power supply voltage. The level shifter includes a first circuit portion operating on the second power supply voltage and a second circuit portion operating on the first power supply voltage.

TERMINATION DEVICE SYSTEM

A termination device system is provided that includes a device required to be terminated with a resistor and a termination circuit. The termination circuit includes a termination resistor circuit and a judgment circuit connected to the termination resistor circuit. The termination resistor circuit includes at least one controlled termination unit. Each controlled termination unit includes a termination connecting end for connecting the device required to be terminated with a resistor, a controlled switch and a resistor, and provides, based on on/off of the controlled switch, a termination resistor for the device connected to the termination connecting end. The judgment circuit judges whether the device is required to be connected to the termination resistor based on a control instruction of a control device controlling the device connected to the termination connecting end, to output an on/off control signal to the controlled switch of the termination resistor circuit to control on/off. 1. A termination resistor circuit , comprising:at least one controlled termination unit, each of which comprising a termination connecting end for connecting a device required to be terminated with a resistor, a controlled switch and a resistor, for providing a termination resistor for the device connected to the termination connecting end based on on/off of the controlled switch.2. The termination resistor circuit as in claim 1 , wherein the at least one controlled termination unit comprises a voltage divider resistor circuit for performing voltage division on a power supply voltage claim 1 , wherein the voltage divider resistor circuit comprises resistors and controlled switches.3. The termination resistor circuit as in claim 1 , wherein the termination resistor circuit is a termination chip claim 1 , and each controlled termination unit is within the termination chip.4. The termination resistor circuit as in claim 1 , wherein the termination resistor circuit comprises a ...

Device

A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE

A system including a read module and a sequence detector module. The read module is configured to read a plurality of memory cells located along a bit line or a word line of a memory array and to generate a plurality of read signals. The sequence detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes (i) a first signal and (ii) a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal includes interference from the second memory cell. 1. (canceled)2. A system comprising: read a plurality of memory cells located along a bit line or a word line of a memory array, and', 'generate a plurality of read signals based on reading the plurality of memory cells located along the bit line or the word line of the memory array; and, 'a read module configured to'} detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals, and (ii) a plurality of reference signals associated with the plurality of memory cells,', 'wherein one of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes (i) a first signal and (ii) a second signal,', 'wherein the first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line, and', 'wherein the second signal includes interference from the second memory cell., 'a sequence detector module configured to'}3. The system of claim 2 , further comprising a reference generator module configured to generate the plurality of reference signals by (i) writing reference data to the ...

TERMINATION CIRCUIT AND DC BALANCE METHOD THEREOF

A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers. 1. A termination circuit for a plurality of memories controlled by a controller , comprising:a plurality of drivers, each coupled to the memories via a transmission line;a plurality of resistors, each coupled to the corresponding driver via the corresponding transmission line; anda plurality of capacitors, each coupled between the corresponding resistor and a reference voltage,wherein the controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.2. The termination circuit as claimed in claim 1 , wherein the controller further provides data to the memories via the drivers claim 1 , wherein the controller further records the data provided to the memories via each of the drivers and obtains a plurality of statistic values according to a quantity of logic “0” and a quantity of logic “1” of the recorded data.3 ...

Output buffer, operating method thereof and devices including the same

A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals.

HIGH-SPEED DRIVER CIRCUIT

An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream. 1. An inverter-type high speed driver circuit comprising:a first inverter branch and a second inverter branch, wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor, wherein the impedance tuning units are configured to adapt conductivity of a respective inverter branch to set an output impedance of the driver circuit; wherein each of the impedance tuning units is controlled in accordance with a data stream.2. The driver circuit according to claim 1 , wherein each impedance tuning unit comprises a plurality of parallelized impedance tuning transistors separately controlled by respective weighted data control signals claim 1 , and wherein an impedance weighting unit is provided to generate weighted data control signals as a result of an incoming data signal and a given impedance setting signal.3. The driver circuit according to claim 1 , wherein each of the inverter branches comprises a resistor in series to the parallel circuit.4. The driver circuit according to claim 1 , wherein the inverter branches are interconnected at a node wherein a resistor is serially connected between an output of the driver circuit and the node.5. The driver circuit according to ...

MEMORY CONTROL DEVICE

A memory control device that can reduce a power consumption at the time of writing a memory. The memory control device includes a data output buffer circuit that burst-transfers data to a memory device through a data bus, and a mask signal output buffer circuit that outputs, to the memory device, a mask signal indicative of data that prohibits write into a memory cell within the memory device among the data. The data output buffer circuit puts an output node into a high impedance state when the mask signal is indicative of write prohibition. 1. A memory control device , comprising:a data output buffer circuit that burst-transfers data to a memory device through a data bus; anda mask signal output buffer circuit that outputs, to the memory device, a mask signal indicative of data that prohibits write into a memory cell within the memory device among the data,wherein the data output buffer circuit puts an output node into a high impedance state when the mask signal is indicative of write prohibition.2. The memory control device according to claim 1 ,wherein when the mask signal is switched from a state in which th mask signal is not indicative of the write prohibition to a state in which the mask signal is indicative of the write prohibition, the data output buffer circuit delays a timing at which the output node is put into a high impedance state, and extends a period during which the data is output.3. The memory control device according to claim 1 ,wherein when the mask signal is switched from a state in which th mask signal is indicative of the write prohibition to a state in which the mask signal is not indicative of the write prohibition, the data output buffer circuit fastens a timing at which the data is output from the output node, and extends a period during which the data is output.4. The memory control device according to claim 1 , further comprising:an output control signal output node that generates an output control signal for controlling a high ...

Adaptive termination

A system for receiving data is provided the system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.

SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE

A semiconductor device is disclosed which comprises first and second local bit lines coupled to a plurality of memory cells arranged in first and second areas, respectively, a differential type local sense amplifier amplifying a voltage difference between the first and second local bit lines, a global bit line arranged in an extending direction of the first and second local bit lines, and first and second switches controlling electrical connections between the first and second local bit lines and the global bit line, respectively. 1. A semiconductor device comprising:a first local bit line coupled to a plurality of memory cells arranged in a first area;a second local bit line coupled to a plurality of memory cells arranged in a second area;a local sense amplifier of a differential type amplifying a voltage difference between the first and second local bit lines;a global bit line arranged in an extending direction of the first and second local bit lines;a first switch controlling an electrical connection between the first local bit line and the global bit line; anda second switch controlling an electrical connection between the second local bit line and the global bit line.2. The semiconductor device according to claim 1 , further comprising a global sense amplifier of a single-ended type connected to one end of the global bit line.3. The semiconductor device according to claim 1 , further comprising a control circuit controlling the first and second switches claim 1 ,wherein in response to a selected memory cell of the memory cells, the control circuit renders one of the first and second switches conductive and renders the other thereof non-conductive.4. The semiconductor device according to claim 3 , wherein the control circuit renders the first switch conductive when the selected memory cell is in the first area claim 3 , and renders the second switch conductive when the selected memory cell is in the second area.5. The semiconductor device according to claim 4 , ...

ADAPTIVE BUFFER

An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system. 115.-. (canceled)16. A circuit , comprising:a node configured to be coupled to load that includes a signal-propagation medium, the load having an impedance;a driver configured to drive a calibration signal onto the node; anda calibrator coupled to the node and configured to generate, in response to the calibration signal, an impedance signal that is related to the impedance of the load.17. The circuit of wherein the node includes an output node.18. The circuit of wherein the node includes an input node.19. The circuit of wherein the driver has an output impedance and is configured to adjust the output impedance in response to the impedance signal.20. The circuit of claim 16 , further comprising a receiving stage coupled to the node claim 16 , having an input impedance claim 16 , and configured to adjust the input impedance in response to the impedance signal.21. The circuit of claim 16 , further comprising a transmitting stage coupled to the node claim 16 , having an output impedance claim 16 , and configured to adjust the output impedance in response to the impedance signal.22. The circuit of wherein the driver includes driver elements that selectively activate in response to the impedance signal to adjust the output impedance of the driver claim 16 ,23. The circuit of wherein the driver has an output impedance and is configured to set the output impedance approximately equal to the impedance of the load in response to the impedance signal.24. The circuit of claim 16 , further comprising a transmitting stage coupled to the node claim 16 , having an output impedance claim 16 , and configured to set the output impedance approximately equal to the impedance of the load in response to the impedance signal.25. The circuit of wherein:the driver includes a calibration portion that is configured to drive the ...

Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device

Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal. 1. An apparatus , comprising:a first transistor configured to receive an input signal and adjust a resistance of a second transistor based, at least in part, on the input signal, the first transistor configured to provide an output signal based, at least in part, on the input signal,wherein a rate at which the output signal is provided is based, at least in part, on a magnitude of the resistance of the second transistor.2. The apparatus of claim 1 , wherein the resistance is an ON-resistance.3. The apparatus of claim 1 , wherein the input signal comprises an analog signal and the output signal comprises a digital signal.4. The apparatus of claim 3 , wherein the first transistor is configured to provide the output signal having a first state when the input signal has a voltage less than a reference voltage and to provide the output signal having a second state when the input signal has a voltage greater than the reference voltage.5. The apparatus of claim 1 , wherein a terminal of the first transistor and a terminal of the second transistor are capacitively coupled.6. The apparatus of claim 1 , ...

Pld architecture for flexible placement of ip function blocks

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Field programmable gate arrays using resistivity-sensitive memories

Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.

IMPEDANCE CALIBRATION DEVICE AND METHOD

An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code. 1. An impedance calibration device , comprising:a variable impedance;an operational unit, used for receiving a first analog signal and a second analog signal and performing a difference operation to generate an output voltage, wherein the first analog signal has variation amount information of the variable impedance, and the second analog signal is a reference signal;an analog-digital converter, coupled to the operational unit, and used for receiving the output voltage to generate an adjustment code; anda controller, coupled to the analog-digital converter and the variable impedance, and used for adjusting a resistance value of the variable impedance according to the adjustment code.2. The impedance calibration device according to claim 1 , further comprising:a gain controller, coupled between the operational unit and the analog-digital converter, and used for adjusting a voltage of the output voltage.3. The impedance calibration device according to claim 2 , wherein the output voltage is mapped to a full dynamic range of the analog-digital converter.4. The impedance calibration device according to claim 1 , wherein the controller adjusts the resistance value of the variable impedance according to a maximum variation amount of the variable impedance and a full dynamic range of the analog-digital converter.5. The impedance calibration device according to claim 1 , wherein the first analog signal is a first current generated ...

Signal sensing circuit

A signal sensing circuit converts a received current input into a voltage output and provides the voltage output to an analog-to-digital converter (ADC) to generate a digital output signal. The voltage output is associated with a circuit having a first reference impedance, and a reference voltage of the ADC is associated with a circuit having a second reference impedance, wherein the circuit having the first reference impedance and the circuit having the second reference impedance are formed by the same material, so that the ratio between the changes in the current input and the changes in the value of the digital output signal is a constant.

TERMINATION CIRCUIT FOR ON-DIE TERMINATION

In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage. 1. A termination circuit for a terminal of a semiconductor device , the terminal associated with an expected voltage swing , the termination circuit comprising:a transistor connected between the terminal and a power supply at a supply voltage;analog control circuitry for controllably enabling and disabling on-die termination, comprising calibrator circuitry with access to a reference resistance, the calibrator circuitry configured to carry out a calibration process for selecting one of a plurality of analog calibration voltages that would cause the transistor to impart a resistance substantially equal to a multiple of the reference resistance if supplied thereto as gate voltage,wherein the control circuitry is configured to drive the gate of the transistor with said one of a plurality of analog calibration voltages when on-die termination is enabled, said one of a plurality of analog calibration voltages being outside a range of voltages defined by the supply voltage and the expected voltage swing.2. The termination circuit defined in claim 1 , wherein the supply voltage is Vdd claim 1 ,3. The termination circuit defined in ...

NONVOLATILE MEMORY, ELECTRONIC APPARATUS, AND VERIFICATION METHOD

A gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to a memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to a reference cell array is included. An electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line. 1. A nonvolatile memory comprising:a memory cell array having a first bit line connected to N memory cells;a reference cell array having a second bit line connected to M reference cells, the M being smaller than the N;a comparator which compares a first electric current which flows along the first bit line with a second electric current which flows along the second bit line; anda gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in the N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in the M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to the memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to the reference cell array,wherein an electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current ...

Integrated circuit and method for operating the same

A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock.

SEMICONDUCTOR DEVICE, METHOD OF RETRIEVING DATA, AND MICROCOMPUTER

A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing inverted data of the reference data; a sense amplifier unit; and a data output unit. In a first retrieving process, the sense amplifier unit differentially amplifies the data and the reference data, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference. In a second retrieving process, the sense amplifier unit differentially amplifies the data and the inverted data, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the predetermined retrievable voltage difference. The data output unit determines and outputs the data according to a result of the first retrieving process and the second retrieving process. 1. A semiconductor device comprising:a data memory cell for storing data;a reference data memory cell for storing reference data to be compared with the data;an inverted data memory cell for storing inverted data of the reference data;a sense amplifier unit; anda data output unit,wherein said sense amplifier unit is configured to perform a first retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the reference data stored in the reference data memory cell, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference,said sense amplifier unit is configured to perform a second retrieving process, in which the sense amplifier unit differentially amplifies the data stored in the data memory cell and the inverted data stored in the inverted data memory cell, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the ...

SEMICONDUCTOR MEMORY DEVICE AND ERASURE VERIFICATION METHOD FOR SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device including a plurality of memory blocks each including a bit line to which a plurality of memory cells are connected, and a dummy bit line to which a plurality of dummy cells are connected; a reference cell; and a sense amplifier including a first input terminal to which selected memory cell of the plurality of memory cells is to be electrically connected via the bit line, and a second input terminal to which the reference cell is to be electrically connected, the dummy bit line of one memory block of the plurality of memory blocks different from another memory block of the plurality of memory blocks including the selected memory cell being to be electrically connected to the second input terminal of the sense amplifier. 1. A semiconductor memory device comprising:a plurality of memory blocks each including a bit line to which a plurality of memory cells are connected, and a dummy bit line to which a plurality of dummy cells are connected;a reference cell; anda sense amplifier including a first input terminal to which a selected memory cell of the plurality of memory cells is to be electrically connected via the bit line, and a second input terminal to which the reference cell is to be electrically connected,the dummy bit line of one memory block being to be electrically connected to the second input terminal of the sense amplifier, the one memory block being different from another memory block including the selected memory cell.2. The semiconductor memory device according to claim 1 , whereinthe semiconductor memory device is an electrically erasable nonvolatile semiconductor memory device, andthe dummy bit line of the one memory block is electrically connected to the second input terminal of the sense amplifier when an erasure verification of the selected memory cell is performed.3. The semiconductor memory device according to claim 2 , whereinwhen the erasure verification is performed, the plurality of dummy cells are set to erase ...

ON-DIE TERMINATION CIRCUIT

An on-die termination circuit includes: a clock signal generation block configured to output a clock signal in response to a clock enable signal, a termination block configured to perform a termination operation on an input/output pad in response to the clock signal, a first termination control signal, and a second termination control signal, a first termination control block configured to generate the first termination control signal in response to the clock signal and a latency control signal, a second termination control block configured to control a latency of a second command and to generate the second termination control signal in response to the clock signal and the latency control signal, and a clock enable signal generation block configured to generate the clock enable signal in response to the first command, the first termination control signal, and the second is command. 2. The on-die termination circuit according to claim 1 , wherein the first command corresponds to an on-die termination command.3. The on-die termination circuit according to claim 1 , wherein the second command corresponds to a write command.4. The on-die termination circuit according to claim 1 , wherein the clock signal generation block corresponds to a delay-locked loop.5. The on-die termination circuit according to claim 1 , wherein the first termination control block comprises:a timing control block configured to control the timing of an external command by a set time and to generate the first command;a variable delay unit configured to delay the first command and to generate a preliminary control signal; anda first latency shift block configured to delay the preliminary control signal by a predetermined latency in response to the latency is control signal on the basis of the delay-locked clock signal, and to generate the first termination control signal.6. The on-die termination circuit according to claim 5 , wherein the first latency shift block comprises:a shift control unit ...

SEMICONDUCTOR DEVICE

A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed. 1. A semiconductor device , comprising:a first memory cell;a second memory cell;a first bit line extending in a first direction and being connected to the first memory cell;a second bit line extending in the first direction and being connected to the second memory cell;a first power line; anda sense amplifier circuit comprising a first transistor and a second transistor, the first transistor including a first gate electrode that is formed over a first channel region and connected to the first bit line, a first diffusion region that is connected to the second bit line and includes a first side edge defining the first channel region and a second diffusion region that is connected to the first power line and includes a second side edge defining the first channel region, and the second transistor including a second gate electrode that is formed over a second channel region and connected to the second bit line, a third diffusion region that is connected to the first bit line and includes a third side edge defining the second channel region and a fourth diffusion region that is ...

SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION

A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments. 1a connector for connecting to the outlet for coupling to the digital data signal carried over the wire pair; anda termination circuit selectively couplable to said connector and constructed for terminating the digital data signal propagated over the wire pair when said device is connected to said connector,wherein said device is switchable between a first state in which said termination circuit is coupled to said connector and a second state in which said termination circuit is not coupled to said connector.. A device for use with a wire pair in walls of a building and connected to an outlet, the wire pair being connected in a bus topology for carrying a digital data signal, said device comprising: This is a continuation of U.S. application Ser. No. 13/245,433, filed on Nov. 14, 2011, which is a continuation of U.S. application Ser. No. 12/724,952, filed on Mar. 16, 2010, which is a continuation of U.S. application Ser. No. 12/252,025, filed Oct. allowed, which is a continuation of U.S. application Ser. No. 12/026,321, filed Feb. 5, 2008, now U.S. Pat. No. 7,453,284, issued on Nov. 18, 2008, which is a continuation of U.S. application Ser. No. 11/346,396, filed on Feb. 3, 2006, now U.S. Pat. No. 7,336,096, issued on Feb. 26, 2008, which is a division of U.S. application Ser. No. 11/100,453, filed on Apr. 7, 2005, now U.S. Pat. No. 7,068,066, issued on Jun. 27, 2006, which is a continuation of U.S. application Ser. No. ...

On-chip impedance network with digital coarse and analog fine tuning

System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

METHODS AND APPARATUSES INCLUDING A VARIABLE TERMINATION IMPEDANCE RATIO

Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions of a termination circuit coupled to an output pin are selectively activated to change an impedance of the termination circuit to change the centerline voltage of the data signal driven to the output pin. One such apparatus includes pull-up impedances and pull-down impedances that can be activated to change the centerline voltage of the data signal. Additional embodiments are also described. 1. A memory device comprising:a memory array for storing data;a termination register configured to store termination values;a termination control circuit coupled to the termination register; andan I/O circuit, coupled to the memory array and the termination control circuit, for transmitting data from and receiving data to the memory array, the I/O circuit comprising a plurality of driver and receiver circuits, each of the plurality of driver and receiver circuits having an adjustable pull-up impedance and an adjustable pull-down impedance that are adjusted by the termination control circuit in response to the stored termination values.2. The memory device of and further comprising a control circuit to control operation of the memory device claim 1 , the control circuit coupled to the termination register.3. The memory device of wherein the control circuit is configured to write the termination values to the termination register.4. The memory device of wherein each adjustable pull-up impedance and each adjustable pull-down impedance comprises a plurality of resistance circuits coupled together in parallel claim 1 , each resistance circuit having a fuse in series with a resistance.5. The memory device of wherein the plurality of resistance circuits for the adjustable pull-up impedance are coupled in parallel between an output pin of the memory device and a supply voltage.6. The memory device of wherein the plurality of ...

DATA VERIFICATION DEVICE AND A SEMICONDUCTOR DEVICE INCLUDING THE SAME

A semiconductor device includes a data verification device. The data verification device includes a data storage unit for storing data to be input to a memory region in response to a first or second control signal, an input data verifier for deactivating an output of a sense amplifier in response to the first control signal and transmitting the input data stored in the data storage unit to an external pad, and a sense-amplifier verifier for transmitting the input data stored in the data storage unit to the sense amplifier upon in response to the second control signal. 1. A data verification device comprising:a data storage unit configured to store input data in response to a first or second control signal generated in a test mode;an input data verifier configured to deactivate an output of a sense amplifier in response to the first control signal, and transmit the input data provided by the data storage unit to an external pad; anda sense-amplifier verifier configured to transmit the input data provided by the data storage unit to the sense amplifier in response to the second control signal, wherein the sense amplifier senses the input data transmitted thereto and transmits sensed data to the external pad.2. The data verification device according to claim 1 , wherein the data storage unit includes a latch that stores the input data in response to the first or second control signal.3. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the input data verifier in response to the first control signal.4. The data verification device according to claim 2 , wherein the latch transmits the stored input data to the sense-amplifier verifier in response to the second control signal.5. The data verification device according to claim 1 , wherein the data storage unit is coupled to a data input buffer claim 1 , and receives the input data through the data input buffer and stores the input data.6. The data verification device ...

Apparatus and methods for digital configuration of integrated circuits

Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.

Circuits and Methods of a Self-Timed High Speed SRAM

Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power. 1. A SRAM memory , comprising:a plurality of SRAM cells having a bitlines (BL) and wordline (WL) that can be selected for access;at least one reference cell having a reference bitline in (BLin) and a reference bitline (RBL) that can be selected from one of a plurality of wordlines or from at least one reference wordline, the reference cell being selectable not earlier than any selected SRAM cells and the RBL being activatable not later than any selected SRAM cells to activate the selected BL;at least one sense amplifier to sense signals coupled to the selected BL from the at least one selected SRAM cell and convert the signals into digital data; andwherein the sense amplifier can be activated by the RBL signal to track the wordline and BL propagating delay.2. A SRAM memory as recited in claim 1 , wherein the at least one reference cell is placed near the far end of a driver to drive a selected wordline or a reference wordline.3. A SRAM memory as recited in claim 1 , wherein the reference cell has at least one inverter with an input coupled to BLin and an output NB coupled to RBL claim 1 , and wherein the RBL is activated by setting BLin at a voltage close to a supply voltage once the wordline or reference wordline is selected.4. A SRAM memory as ...

HYSTERESIS CONTROL SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES

Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided. 1. A programmable logic device (PLD) comprising:a first hysteresis control circuit configured to generate a first hysteresis control signal based on a core voltage and a first input/output (I/O) voltage; and a first buffer circuit configured to receive a first input voltage and generate a first buffer voltage based on the first input voltage;', 'a first hysteresis generator configured to generate a first hysteresis voltage based on the first hysteresis control signal and the first I/O voltage; and', 'a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the first hysteresis voltage., 'an I/O cell associated with an I/O fabric of the PLD and powered by the first I/O voltage, the I/O cell comprising2. The PLD of claim 1 , further comprising a processing circuit configured to:receive configuration data associated with the PLD; andprogram an array of configuration memory cells of the PLD based on the configuration data, the array of configuration memory cells comprising a plurality of logic block memory cells associated with a logic fabric ...

IMPEDANCE COMPENSATION BASED ON DETECTING SENSOR DATA

A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold. 122-. (canceled)23. A memory device comprising:a register selectively writeable by the memory device with an impedance calibration update flag, to indicate to a memory controller that an impedance calibration update is ready at the memory device; andI/O (input/output) hardware to receive commands from the memory controller when coupled to the memory controller, including an impedance calibration latch signal (ZQCAL LATCH) in response to detection by the memory controller of the impedance calibration update flag being set, to set a new calibration setting in the memory device.24. The memory device of claim 23 , wherein the I/O hardware is to periodically receive a polling request from the memory controller to check the impedance calibration update flag.25. The memory device of claim 23 , wherein the register comprises a Mode Register claim 23 , and the I/O hardware is to periodically receive a command to read the Mode Register to check the impedance calibration update flag.26. The memory device of claim 23 , wherein the I/O hardware is to receive the impedance calibration latch signal with receipt first of an impedance calibration start signal (ZQCAL START).27. The memory device of claim 23 , wherein the memory device is to compute a comparison between a previous impedance calibration setting an updated calibration setting claim 23 , and only set the impedance calibration update flag ...

ON-DIE TERMINATION ENABLE SIGNAL GENERATOR, SEMICONDUCTOR APPARATUS, AND SEMICONDUCTOR SYSTEM

A semiconductor apparatus may include an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal. The semiconductor apparatus may include an ODT circuit configured to perform an ODT operation in response to the ODT enable signal. 1. A semiconductor apparatus comprising:an on-die termination (ODT) enable signal generator configured to enable an ODT enable signal in response to a data strobe signal, or enable the ODT enable signal in response to a command latch enable signal and an address latch enable signal; andan ODT circuit configured to perform an ODT operation in response to the ODT enable signal,wherein the ODT enable signal generator enables the ODT enable signal in response to the data strobe signal in a non-test and enables the ODT enable signal in response to the command latch enable signal and the address latch enable signal in a test.2. (canceled)3. The semiconductor apparatus of claim 1 , wherein the ODT enable signal generator disables the ODT enable signal in response to a chip enable signal claim 1 , the command latch enable signal claim 1 , and the address latch enable signal.4. The semiconductor apparatus of claim 3 , wherein the ODT enable signal generator includes:a set signal generator configured to generate a set signal in response to the data strobe signal, the command latch enable signal, the address latch enable signal, and a test signal;a reset signal generator configured to generate a reset signal in response to the chip enable signal, the command latch enable signal, and the address latch enable signal; andan enable signal generator configured to enable the ODT enable signal in response to the set signal or disable the ODT enable signal in response to the reset signal.5. The semiconductor apparatus of claim 4 , wherein the set signal generator outputs the ...

Programmable High-Speed I/O Interface

Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input Output structure is optimized between speed and functionality depending on the requirements of the application. 1a plurality of buffers;a first pad selectively-coupled to at least one buffer from among the plurality of buffers;a second pad selectively-coupled to at least one buffer from among the plurality of buffers; andprogrammable logic to enable the selectively-configurable I/O interface to be configured in first and second configurations,wherein when in the first configuration the selectively-configurable I/O interface is configured to receive a single-ended signal at the first pad and buffer the signal in a buffer from among the plurality of buffers coupled to the first pad,and wherein when in the second configuration the selectively-configurable I/O interface is configured to receive a differential signal at the first and second pads and buffer the differential signal in a buffer from among the plurality of buffers that is coupled to the first and second pads.. A selectively-configurable I/O interface, comprising: This application is a continuation of U.S. patent application Ser. No. 14/449,521, filed Aug. 1, 2014, which is a division ...

Programmable High-Speed I/O Interface

Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input Output structure is optimized between speed and functionality depending on the requirements of the application.

LATCHING SENSE AMPLIFIER

A latching sense amplifier includes an input stage and an output stage. The output stage is coupled to the input stage. The output stage includes a first output node, a second output node, a pull-up circuit, and a pull-down circuit. The pull-up circuit includes a first transistor, a second transistor, and a latch circuit. The first transistor is configured to pull up the first output node. The second transistor is configured to pull up the second output node. The latch circuit is configured to control the first transistor and the second transistor. The pull-down circuit includes a latch circuit configured to pull-down the first output node based on a voltage of the second output node. 1. A latching sense amplifier , comprising:an input stage comprising a clocked differential amplifier; and a first output node;', 'a second output node;', a first transistor;', 'a second transistor cross-coupled with the first transistor;', 'a third transistor, controlled by the first transistor, and configured to pull up the first output node;', 'a fourth transistor, controlled by the second transistor, and configured to pull up the second output node; and, 'a pull-up circuit, comprising, a fifth transistor configured to pull down the first output node; and', 'a sixth transistor configured to pull down the second output node;', 'wherein the fifth transistor and the sixth transistor are cross-coupled., 'a pull-down circuit, comprising], 'an output stage comprising2. The latching sense amplifier of claim 1 , wherein the pull-up circuit further comprises:a seventh transistor coupled to a first output node of the input stage, and configured to control the first transistor; andan eighth transistor coupled to a second output node of the input stage, and configured to control the second transistor.3. The latching sense amplifier of claim 1 , wherein the pull-down circuit further comprises:a seventh transistor coupled to a first output node of the input stage, and configured to pull-down the ...

CELL-SPECIFIC REFERENCE GENERATION AND SENSING

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison. 1. (canceled)2. A method comprising:capturing, using a first digit line of a first ferroelectric memory cell, a first voltage from the first ferroelectric memory cell;coupling the first digit line with a second digit line of a second ferroelectric memory cell to share the first voltage between the first digit line and the second digit line;decoupling the first digit line and the second digit line to store a second voltage on the second digit line based at least in part on sharing the first voltage;capturing, using the first digit line, a third voltage from the first ferroelectric memory cell; anddetermining a logic state of the first ferroelectric memory cell by coupling the first digit line and the second digit line with a sense component.3. The method of claim 2 , further comprising:storing a fourth voltage on the first digit line based at least in part on decoupling the first digit line and the second digit line after sharing the first voltage; andstoring the fourth voltage on the first ferroelectric memory cell, wherein capturing the third voltage is based at least in part on storing the fourth voltage on the first ferroelectric memory cell.4. The method of claim 3 , wherein the fourth voltage corresponds to an intermediary logic state associated with the logic state of the first ferroelectric memory cell.5. The method of claim 2 , further comprising:activating a selection component of the first ferroelectric memory ...

Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device

A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

SIGNAL TRANSMISSION CIRCUIT

A signal transmission circuit is provided. A tri-state logic circuit includes an enabling terminal, an input terminal and an output terminal, and is conducted and unconducted when the enabling terminal is at a high and a low state respectively. A pull-up circuit pulls up a voltage level of the output terminal. A first and a second multiplexers respectively output an enabling signal and an output signal to the enabling terminal and the input terminal according to a first status of a selection signal and respectively output a high state signal according to a second status of the selection signal. A selection circuit generates the selection signal having the first status when the voltage level is not larger than a first threshold value, having the second status after the voltage level is larger than the first threshold value and having the first status afterwards. 1. A signal transmission circuit , comprising:a tri-state logic circuit comprising an enabling terminal, an input terminal and an output terminal and configured to be conducted when the enabling terminal is at a high state and unconducted when the enabling terminal is at a low state;a pull-up circuit electrically coupled to the output terminal and configured to pull up a voltage level of the output terminal;a first multiplexer and a second multiplexer respectively configured to output an enabling signal to the enabling terminal and output an output signal having a low state to the input terminal according to a first status of a selection signal, and respectively configured to output a high state signal to the enabling terminal and output the high state signal to the input terminal according to a second status of the selection signal opposite to the first status; anda selection circuit configured to generate the selection signal having the first status when the voltage level of the output terminal is not larger than a first threshold value, generate the selection signal having the second status during a ...

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination. 1. (canceled)2. A method for controlling the impedance of a buffer having a plurality of pull-up transistors and a plurality of pull-down transistors , the method comprising:receiving a data output signal;receiving an output enable signal;receiving a termination enable signal;receiving a first plurality of impedance control bits, a second plurality of impedance control bits, a third plurality of impedance control bits, and a fourth plurality of impedance control bits;enabling, when the output enable signal is in a first state and the data output signal is in a first state, one or more of the plurality of pull-up transistors determined by the first plurality of impedance control bits;enabling, when the output enable signal is in a first state and the data output signal is in a second state, one or more of the plurality of pull-down transistors determined by the second plurality of impedance control bits; andenabling, when the termination enable signal is in a first state, one or more of the plurality of pull-up transistors determined by the third plurality of impedance control bits and one or more of the plurality of pull-down transistors determined by the fourth plurality of impedance control bits;wherein the first and second pluralities of impedance control bits ...

MEMORY DEVICE AND OPERATION METHOD THEREOF

A memory device and an operating method thereof are provided. The memory device includes a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data, a transmission circuit configured to output the read data stored in the latch through a page bus line in response to a transmission signal, a cache latch configured to receive the read data through the page bus line and temporarily store the read data, and a pump voltage output circuit coupled to the transmission circuit through a transmission line and configured to apply a second voltage greater than a first voltage after applying the first voltage to the transmission line for a set time. 1. A memory device , comprising:a latch configured to sense a voltage or a current of a bit line coupled to a memory cell and store read data;a transmission circuit configured to output the read data stored in the latch through a page bus line in response to a transmission signal;a cache latch configured to receive the read data through the page bus line and temporarily store the read data; anda pump voltage output circuit coupled to the transmission circuit through a transmission line and configured to apply a second voltage greater than a first voltage after applying the first voltage to the transmission line for a set time.2. The memory device of claim 1 , wherein the cache latch is configured to transfer data input from an external device to the latch through the page bus line during a program operation.3. The memory device of claim 1 , wherein the transmission circuit includes a switch electrically coupling or decoupling the latch and the transmission line in response to the transmission signal.4. The memory device of claim 3 , wherein the switch is configured to turn-on in response to the transmission signal.5. The memory device of claim 1 , wherein the pump voltage output circuit comprises:a first voltage output circuit configured to output the first voltage in response to a ...

Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. 1. (canceled)2. An on-die termination (ODT) control circuit comprising:at least one reference-voltage node;a reference ODT resistor to exhibit a calibrated voltage responsive to an ODT count;a comparator having a first comparator input, a second comparator input, and a comparator output;a first pass gate selectively coupling the first comparator input to the at least one reference-voltage node;a second pass gate selectively coupling the second comparator input to the reference ODT resistor to receive the calibrated voltage;a third pass gate selectively coupling the second comparator input to the at least one reference-voltage node; anda counter coupled between the comparator output and the reference ODT resistor, the counter to issue the ODT count responsive to an output of the comparator.3. The ODT control circuit of claim 2 , further comprising a voltage source between the at least one reference-voltage node and the second comparator input.4. The ODT control circuit of claim 3 , wherein the at least one reference voltage node comprising a reference-voltage node selectively coupled to the first comparator input and a second reference-voltage node selectively coupled to the second comparator input via the ...

Power Saving with Dual-rail Supply Voltage Scheme

In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated circuit includes a voltage regulator that receives the first power supply voltage and generates a second power supply voltage having a magnitude that is lower than the magnitude of the first power supply voltage by a predetermined amount. The second power supply voltage may track the first power supply voltage over dynamic changes during use, either intentional changes to operating state or noise-induced changes. The second power supply voltage may be used to power at least a portion of the clock tree. 1. An integrated circuit comprising:a logic circuit powered by a first power supply voltage having a first magnitude during use;a clock tree circuit coupled to the logic circuit and configured to distribute a clock to the logic circuit, wherein at least a portion of the clock tree circuit is powered by a second power supply voltage having a second magnitude during use; anda voltage regulator coupled to the first power supply voltage and configured to generate the second power supply voltage from the first power supply voltage, wherein the second magnitude is less than the first magnitude by a predetermined amount, and wherein the first magnitude changes dynamically during use and the voltage regulator is configured to track the first magnitude with the second magnitude at the predetermined amount less than the first magnitude.2. The integrated circuit as recited in wherein the predetermined amount is a fixed percentage.3. The integrated circuit as recited in wherein the predetermined amount is a fixed voltage offset.4. The integrated circuit as recited in further comprising a second voltage regulator configured to generate the first supply voltage responsive to a third supply voltage that is input to the integrated circuit.5. (canceled)6 ...

SELF-REFERENCING SENSING SCHEMES WITH COUPLING CAPACITANCE

Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes. 1. (canceled)2. An apparatus , comprising:a sense component in electronic communication with a memory cell via a first access line;a capacitance between a first node of the sense component and a second node of the sense component; and generate a first sense signal at the first node of the sense component while the memory cell is coupled with the first node of the sense component;', 'generate a second sense signal at the second node of the sense component while the memory cell is coupled with the second node of the sense component, wherein the second sense signal is based at least in part on the generated first sense signal and the capacitance between the first node of the sense component and the second node of the sense component; and', 'determine a logic state stored by the memory cell based at least in part on generating the first sense signal and generating the second sense signal., 'a controller in electronic communication with the sense component and the memory cell, wherein the controller is operable to cause the apparatus to3. The apparatus of claim 2 , wherein the memory cell comprises a capacitive memory element.4. The apparatus of claim 2 , ...

APPARATUSES AND METHODS FOR PARTIAL BIT DE-EMPHASIS

Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion. 1. An apparatus comprising:an external terminal; and receive a first signal having a first logical value,', 'receive a second signal following the first signal, the second signal having a second logical value different from the first logical value, and', 'drive, in response to receiving the second signal, the external terminal from a first voltage to a second voltage by way of a third voltage, wherein the third voltage is a de-emphasized first voltage based at least in part on a de-emphasis time., 'an output driver coupled to the external terminal, the output driver configured to2. The apparatus of claim 1 , wherein the output driver de-emphasizes the first voltage for two bit periods.3. The apparatus of claim 1 , further comprising a variable delay circuit to introduce a delay interval claim 1 , wherein the delay interval determines the de-emphasis time.4. The apparatus of claim 3 , wherein the delay interval comprises a half bit period to produce a half bit period de-emphasis.5. The apparatus of claim 3 , wherein the variable delay circuit is configured to receive an input signal having first and second logic values claim 3 , and generate a delayed signal that is delayed relative to ...

LEVEL DOWN SHIFTER

A level down shifter circuit includes a latch and an assist circuit. The latch is configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal. The digital input signal and the complementary input signal are in a first voltage domain. The digital shifted signal and the complementary shifted signal are in a second voltage domain. The second voltage domain has a smaller voltage range than the first voltage domain. The assist circuit is configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal. The intermediate voltage is in the second voltage domain. 1. A level down shifter circuit comprising:a latch configured to generate a digital shifted signal and a complementary shifted signal by a voltage downshift of a digital input signal and a complementary input signal, wherein the digital input signal and the complementary input signal are in a first voltage domain, the digital shifted signal and the complementary shifted signal are in a second voltage domain, and the second voltage domain has a smaller voltage range than the first voltage domain; andan assist circuit configured to alternately pull the digital shifted signal and the complementary shifted signal to an intermediate voltage in response to the digital input signal and the complementary input signal, wherein the intermediate voltage is in the second voltage domain; anda header configured to bias the intermediate voltage from a second voltage source of the second voltage domain.2. (canceled)3. The level down shifter circuit according to claim 1 , wherein the header includes a transistor with a gate tied to a first voltage source of the first voltage domain.4. The level down shifter circuit according to claim 1 , further comprising an inverter configured to generate the ...

IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit. 1. An impedance calibration circuit comprising:a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor;a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad;a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to an internal impedance calibration enable signal and output the selected pull-up impedance detection signal; andan impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.2. The impedance calibration circuit of claim 1 , wherein the first detection unit includes:a replica pull-up driver coupled between a power terminal and the internal reference resistor; anda comparator configured to generate the first pull-up impedance detection signal by comparing a level of a node to which the replica pull-up driver and the internal ...

Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. 1. (canceled)2. A method for calibrating a resistance of an on-die termination (ODT) resistor against an off-die resistor using a single comparator , the method comprising:drawing a reference-resistor current through the off-die resistor to develop a reference-resistor voltage;comparing, with the single comparator, the reference-resistor voltage to a reference voltage;adjusting the reference-resistor current through the off-die resistor responsive to an output of the single comparator until the reference-resistor voltage matches the reference voltage to produce a calibrated reference-resistor current and a calibrated reference-resistor voltage;creating a calibrated ODT current proportional to the calibrated reference-resistor current;drawing the calibrated ODT current through the ODT resistor to develop an ODT voltage; andadjusting the resistance of the ODT resistor responsive to the output of the single comparator until the ODT voltage matches the calibrated reference-resistor voltage and the reference voltage.3. The method of claim 2 , further comprising comparing claim 2 , with the single comparator claim 2 , the ODT voltage to the calibrated reference-resistor voltage.4. The method of claim 2 , ...

APPARATUSES AND METHODS FOR PROVIDING AN INDICATOR OF OPERATIONAL READINESS OF VARIOUS CIRCUITS OF A SEMICONDUCTOR DEVICE FOLLOWING POWER UP

Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in the present disclosure. An example apparatus includes a first circuit configured to receive a supply voltage and further configured to provide an active first signal responsive to the supply voltage exceeding a threshold voltage. The example apparatus further includes a second circuit coupled to the first circuit and activated by the active first signal, the second circuit configured to provide an active second signal when a third circuit is ready for operation. 1. An apparatus , comprising:an oscillator circuit configured to receive an activation signal and provide an oscillating signal based on the received activation signal;a timing circuit coupled to the oscillator circuit and configured to provide an oscillating data signal based at least in part on the oscillating signal; anda flip flop circuit coupled to the timing circuit and configured to latch a logic level of the oscillating data signal and provide an output signal to the oscillator circuit having a logic level based at least in part on the latched logic level.2. The apparatus of claim 1 , wherein the flip flop circuit is a model circuit configured to model other flip flop circuits.3. The apparatus of claim 1 , wherein at least one other flip flop circuit is enabled based on the output signal of the flip flop circuit.4. The apparatus of claim 1 , further comprising:a plurality of other flip flop circuits configured to be enabled,wherein the flip flop circuit is a model circuit, andwherein operation of the plurality of other flip flop circuits is responsive to operation of the model circuit.5. The apparatus of claim 4 , wherein the plurality of other flip flop circuits are configured to be enabled for operation responsive to a change in the logic level of the output signal of the model circuit.6. The apparatus of claim 1 , further comprising:a ...

APPARATUS AND METHOD FOR REPAIRING RESISTIVE MEMORIES AND INCREASING OVERALL READ SENSITIVITY OF SENSE AMPLIFIERS

A memory includes a module and a demultiplexer. The module is configured to monitor outputs of sense amplifiers. Each of the outputs of the sense amplifiers is configured to be in a first state or a second state. The module is configured to determine that two or more of the outputs of the sense amplifiers are in a same state. The same state is the first state or the second state. The module is configured to output the state of the two or more outputs of the sense amplifiers. The demultiplexer is configured to provide the state of the two or more outputs of the sense amplifiers to a latch. 1. A memory comprising: monitor outputs of a plurality of sense amplifiers, wherein each of the outputs of the plurality of sense amplifiers is configured to be in a first state or a second state,', 'determine that a plurality of the outputs of the plurality of sense amplifiers are in a same state, wherein the same state is the first state or the second state, and', 'output the state of the plurality of the outputs of the plurality of sense amplifiers; and, 'a module configured to'}a demultiplexer configured to provide the state of the plurality of the outputs of the plurality of sense amplifiers to a latch.2. The memory of claim 1 , wherein:the module is configured to determine that a majority of the outputs of the plurality of sense amplifiers is in the same state; andthe demultiplexer is configured to provide the same state of the majority of the outputs of the plurality of sense amplifiers to the latch.3. The memory of claim 1 , further comprising:an array of memory cells comprising a plurality of bit lines;a plurality of multiplexers, wherein each of the plurality of multiplexers is configured to receive outputs from two or more of the plurality of bit lines; andthe plurality of sense amplifiers configured to amplify respective outputs of the plurality of multiplexers.4. The memory of claim 3 , further comprising a second module configured to generate one or more selection ...

INTEGRATED CIRCUIT AND DATA INPUT METHOD

An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information. 1. An integrated circuit comprising:a pad configured to receive an external data signal input;an on-die termination (ODT) information input configured to receive ODT information from an external device;an ODT circuit configured to selectively couple a termination resistor to the pad based on the ODT information;an input buffer coupled to the pad and configured to determine a data value based on a reference voltage; anda reference voltage generator coupled to the input buffer and configured to generate the reference voltage based on the ODT information.2. The integrated circuit of claim 1 , wherein the ODT information comprises on/off information indicating whether to perform an ODT operation claim 1 , termination information indicating a pull-up termination or a pull-down termination claim 1 , and resistance information indicating an ODT resistance value.3. The integrated circuit of claim 2 , further comprising a mode register configured to provide least a portion of the ODT information.4. The integrated circuit of claim 1 , wherein the ODT circuit further comprises a pull-up termination circuit including the termination resistor selectively coupled between the pad and a power supply voltage based on the ODT information.5. The integrated circuit of claim 1 , wherein the ODT circuit further comprises a pull-down termination circuit including the termination resistor selectively coupled between the pad and a ...

Output circuit of driver

An output circuit of a driver includes a plurality of output nodes, a first output buffer group and a multiplexer. The first output buffer group is configured to output data to the plurality of output nodes, wherein each output buffer in the first output buffer group is configured to output data to at least two output nodes among the plurality of output nodes. The multiplexer, coupled between the plurality of output nodes and the first output buffer group, is configured to select to couple each output buffer in the first output buffer group to one of the plurality of output nodes. 1. An output circuit of a driver , comprising:a plurality of output nodes;a first output buffer group, configured to output data to the plurality of output nodes, wherein each output buffer in the first output buffer group is configured to output data to at least two output nodes among the plurality of output nodes; anda multiplexer, coupled between the plurality of output nodes and the first output buffer group, configured to select to couple each output buffer in the first output buffer group to one of the plurality of output nodes;wherein a number of output buffers in the first output buffer group is less than a number of the plurality of output nodes receiving data from the first output buffer group.2. The output circuit of claim 1 , wherein the first output buffer group comprises:a first output buffer, configured to output data in a first polarity; anda second output buffer, configured to output data in a second polarity.3. The output circuit of claim 2 , wherein the first output buffer is coupled to a first output node among the plurality of output nodes and the second output buffer is coupled to a second output node among the plurality of output nodes in a polarity non-swapping mode claim 2 , and the first output buffer is coupled to the second output node and the second output buffer is coupled to the first output node in a polarity swapping mode.4. The output circuit of claim 1 , ...

PACKAGED INTEGRATED CIRCUIT MEMORY DEVICES HAVING ENHANCED ON-DIE-TERMINATION CIRCUITS THEREIN AND METHODS OF OPERATING SAME

A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data. 1. A memory device comprising:a pad region having a flag pad and a signal pad thereon;a memory bank region having a plurality of memory cells therein;an on-die-termination (ODT) setting circuit configured to receive a control command including first data corresponding to a termination resistance requested by an external host, and an ODT enable signal, and further configured to generate second data corresponding to an ODT resistance;an ODT enable circuit configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal; anda resistor circuit configured to connect the ODT resistance to the signal pad, in response to the second data.2. The memory device according to claim 1 , further comprising:a transmitter having an output terminal electrically coupled to the flag pad; anda receiver having an input terminal electrically coupled to the flag pad.3. The memory device according to claim 2 , wherein the receiver is turned off and the transmitter is turned on to thereby output the ODT flag signal claim 2 , in response to receipt of the ODT enable signal by the ODT enable circuit.4. The memory device according to claim 3 , wherein the ...

ON-DIE TERMINATION CONTROL WITHOUT A DEDICATED PIN IN A MULTI-RANK SYSTEM

A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting. 1. A method for selectively applying on-die termination , comprising:sending a memory access command concurrently to a number of ranks of memory devices corresponding to a memory access operation, the memory access command directed to a target rank to execute the command;triggering one or more non-target ranks of the number of ranks to change an on-die termination (ODT) setting for a duration of the memory access operation; andselecting the target rank to execute the memory access operation.2. The method of claim 1 , wherein sending the memory access command comprises sending a read command claim 1 , and wherein triggering the one or more non-target ranks to change the ODT setting comprises triggering the a non-target rank to engage ODT.3. The method of claim 1 , wherein sending the memory access command comprises sending a write command claim 1 , and wherein triggering the one or more non-target ranks to change the ODT setting comprises triggering the target rank and at least one non-target rank to engage ODT.4. The method of claim 1 , wherein sending the memory access command comprises sending the memory access command from a memory controller.5. The method of claim 1 , wherein sending the memory access command comprises sending multiple sequential commands to generate the memory access operation.6. The method of claim 5 , wherein the triggering further comprises sending a first command indicating the memory access operation ...

ON-DIE TERMINATION CIRCUIT, A MEMORY DEVICE INCLUDING THE ON-DIE TERMINATION CIRCUIT, AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE

An on-die termination (ODT) circuit connected to an input buffer that receives a data signal, the ODT circuit includes at least one termination resistor connected to the input buffer and at least one switching device configured to control a connection between the termination resistor and the input buffer. The switching device is turned on or off according to information about the data signal. 1. An on-die termination circuit connected to an input buffer that receives a data signal , the on-die termination circuit comprising:at least one termination resistor connected to the input buffer; andat least one switching device configured to control a connection between the termination resistor and the input buffer;wherein the switching device is turned on or off according to information about the data signal,wherein the information about the data signal includes at least one of pattern information of the data signal, frequency information of the data signal, and length information of a channel through which the data signal is transmitted.2. The on-die termination circuit of claim 1 , wherein the switching device is turned on or off according to the pattern information of the data signal.3. The on-die termination circuit of claim 2 , wherein the pattern information of the data signal indicates a level change of the data signal claim 2 ,wherein the switching device is turned on when a level of the data signal changes and is turned off when the level of the data signal remains constant for a predetermined time.4. The on-die termination circuit of claim 1 , wherein the switching device is turned on or off according to a determination result after a predetermined delay interval.5. The on-die termination circuit of claim 4 , wherein the predetermined delay interval is changed based on the frequency information of the data signal or the channel length information.6. The on-die termination circuit of claim 5 , wherein the predetermined delay interval increases with respect to a ...

SCALABLE INTEGRATED MOSFET (SIM)

A high voltage power block includes a high voltage power transistor; and a switch driver configured to drive a gate of the high voltage power transistor. The high voltage power block is integrated in a programmable logic device (PLD) including a programmable fabric, a signal wrapper configured to provide signals between the high voltage power transistor and the programmable fabric, and a plurality of internal components. The plurality of internal components integrated in the PLD are programmably connected and characteristics of the high voltage power transistor are programmably adjusted using the programmable fabric and the signal wrapper. 1. A high voltage power block comprising:a high voltage power transistor; anda switch driver configured to drive a gate of the high voltage power transistor;wherein the high voltage power block is integrated in a programmable logic device (PLD) including a programmable fabric, a signal wrapper configured to provide signals between the high voltage power block and the programmable fabric, and a plurality of internal components, andwherein the plurality of internal components integrated in the PLD are programmably connected and characteristics of the high voltage power transistor are programmably adjusted using the programmable fabric and the signal wrapper.2. The high voltage power block of claim 1 , wherein a source and a drain of the high voltage power transistor are provided on a source pad and a drain pad to connect to external signals and components.3. The high voltage power block of claim 1 , wherein the PLD is configured as one of a buck regulator claim 1 , a boost regulator claim 1 , a multiphase buck regulator claim 1 , a buck-boost regulator claim 1 , a source side regulator claim 1 , a drain-side regulator claim 1 , a push-pull DDR regulator claim 1 , a load switch claim 1 , and a battery charger by programming the programmable fabric and configuring the characteristics of the high voltage power transistor.4. The high ...

METHODS AND SYSTEMS FOR AVERAGING IMPEDANCE CALIBRATION

A semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration codes. The calibration circuit also calibrates impedance of the programmable termination components based on an average impedance calibration code of the impedance calibration codes. The semiconductor device further includes an averaging circuit that determines the average impedance calibration code of the impedance calibration codes. 1. A semiconductor device comprising:one or more programmable termination components; generate a plurality of impedance calibration codes based on a periodic supply voltage signal; and', 'calibrate impedance of the one or more programmable termination components based on an average impedance calibration code of the plurality of impedance calibration codes; and, 'a calibration circuit configured toan averaging circuit configured to determine the average impedance calibration code of the plurality of impedance calibration codes.2. The semiconductor device of claim 1 , wherein the calibration circuit is configured to calibrate the impedance of the one or more programmable termination components based on each impedance calibration code of the plurality of impedance calibration codes.3. The semiconductor device of claim 1 , wherein the one or more programmable termination components comprise a data output circuit of the semiconductor device.4. A system comprising:a controller; one or more programmable termination components;', generate a plurality of impedance calibration codes based on a periodic supply voltage signal in response to receiving a command signal from the controller; and', 'calibrate impedance of the one or more programmable termination components based on an average impedance calibration code of the plurality of impedance calibration codes; and, 'a calibration circuit configured to], 'a semiconductor device communicatively coupled to the controller, wherein the ...

CALIBRATION CIRCUIT FOR CONTROLLING RESISTANCE OF OUTPUT DRIVER CIRCUIT, MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE

A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block. 1. A memory device comprising:a calibration circuit having a pull-up code generator comprising a pull-up resistor block and configured to generate a pull-up code, and a pull-down code generator comprising a replica pull-up resistor block and a pull-down resistor block and configured to generate a pull-down code; andan off chip driver (OCD)/on die termination (ODT) circuit configured to provide a termination resistance having a resistance value set by the calibration circuit in a data reception operation and to output data at an output strength set by the calibration circuit in a data output operation,wherein, in a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.2. The memory device of claim 1 , whereinthe pull-up resistor block comprises at least one pull-up resistor set connected to a power source voltage, the ...

MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data. 1. (canceled)2. An apparatus , comprising:an array of memory cells;a controller configured to control operation of memory cells in the array of memory cells;an interposer formed of a first material and operatively coupled with the array of memory cells and the controller, wherein the interposer comprises a plurality of channels between the array of memory cells and the controller;a substrate coupled with the interposer and formed of a second material different than the first material; anda receiver configured to determine a logic state represented by a signal modulated using a first modulation scheme communicated across at least one channel of the interposer.3. The apparatus of claim 2 , further comprising:a driver configured to generate the signal to be transmitted across the at least one channel of the interposer based at least in part on a plurality of information bits.4. The apparatus of claim 2 , wherein the signal comprises a binary-level signal.5. The apparatus of claim 4 , wherein the first modulation scheme comprises a non-return-to-zero (NRZ) scheme claim 4 , a unipolar encoding scheme claim 4 , a bipolar encoding scheme claim 4 , a Manchester encoding scheme claim 4 , a two-level pulse amplitude modulation (PAM) scheme claim 4 , or a combination thereof.6. The apparatus of claim 2 , wherein the signal comprises a non-binary signal.7. The apparatus of claim 6 , wherein the first modulation scheme comprises a four-level pulse amplitude modulation (PAM ...

IMPEDANCE ADJUSTMENT IN A MEMORY DEVICE

Methods include configuring termination devices of a driver circuit of a memory device, storing a first plurality of trim values representative of the configuration of the termination devices of the driver circuit, transferring a second plurality of trim values to a different memory device, and configuring a plurality of termination devices of a driver circuit of the different memory device in response to the second plurality of trim values. Methods further include determining configuration information corresponding to a configuration of a particular driver circuit of a memory device adjusted to a desired impedance, storing a first set of trim values representative of the configuration information, and adjusting an impedance of a different driver circuit of the memory device in response to the first set of trim values and a correction factor representative of expected differences in characteristics between the particular driver circuit and the different driver circuit. 1. (canceled)2. A method of operating a plurality of memory devices , the method comprising:configuring a plurality of termination devices of a particular driver circuit of a particular memory device of the plurality of memory devices;storing, to the particular memory device, a first plurality of trim values representative of the configuration of the plurality of termination devices of the particular driver circuit;after storing the first plurality of trim values to the particular memory device, transferring a second plurality of trim values from the particular memory device to a different memory device of the plurality of memory devices; andconfiguring a plurality of termination devices of a driver circuit of the different memory device in response to the second plurality of trim values.3. The method of claim 2 , wherein transferring the second plurality of trim values comprises transferring a same plurality of trim values as the first plurality of trim values.4. The method of claim 3 , further ...

COMPENSATED IMPEDANCE CALIBRATION CIRCUIT

Aspects of the invention provide for compensating impedance calibration circuits. In one embodiment, a compensated impedance calibration circuit, includes: a variable resistor network including a tunable resistor and a fixed resistor; and an external resistance network including a target external precision resistor and a parasitic distribution resistance; wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant. 1. A compensated impedance calibration circuit , comprising:a variable resistor network including a tunable resistor and a fixed resistor; andan external resistance network including a target external precision resistor and a parasitic distribution resistance;wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant.2. The compensated impedance calibration circuit of claim 1 , wherein a value for the fixed resistor is selected from a range of discrete values.3. The compensated impedance calibration circuit of claim 1 , further comprising a voltage reference generator for generating a reference voltage.4. The compensated impedance calibration circuit of claim 3 , further comprising a comparator for comparing the reference voltage to the output voltage of the variable resistor network.5. The compensated impedance calibration circuit of claim 4 , further comprising control logic for receiving an output of the comparator and for tuning the variable resistor network claim 4 , such that the output voltage of the variable resistor network is equal to the reference voltage.6. The compensated impedance calibration circuit of claim 1 , wherein the fixed resistor is a pluggable on-chip resistor. The disclosure relates ...

SEMICONDUCTOR MEMORY DEVICE, A MEMORY MODULE INCLUDING THE SAME, AND A MEMORY SYSTEM INCLUDING THE SAME

A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ). 1. A method of operating a memory controller , comprising:receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH);determining a reference voltage according to the VOH; andcomparing the data signal with the reference voltage to determine a received data value,wherein the VOH is proportional to a power supply voltage (VDDQ).2. The method of claim 1 , wherein the VOH has a value of VDDQ/2.5.3. The method of claim 1 , wherein the VOH has a value of VDDQ/3.4. The method of claim 1 , wherein a value of the VOH depends on a resistance of an on-die termination (ODT) resistor of the memory controller.5. The method of claim 4 , wherein the VOH has a value of VDDQ/2.5 when the ODT resistor is 80 claim 4 , 120 or 240 ohms.6. The method of claim 4 , wherein the VOH has a value of VDDQ/3 when the ODT resistor is 40 claim 4 , 60 claim 4 , 80 claim 4 , 120 or 240 ohms.7. The method of claim 1 , wherein the data signal is generated at the memory device in response to an instruction from the memory controller.8. The method of claim 7 , wherein the instruction includes information about the VOH.9. The method of claim 7 , wherein the instruction includes information about an on-die termination (ODT) resistor of the memory controller.10. The method of claim 7 , wherein the instruction causes a mode register set (MRS) signal to be generated by the memory device.11. The method of claim 10 , wherein the MRS signal varies according to the value of an on-die termination (ODT) resistor of the memory controller.12. The method of claim 1 , wherein a mode register in the ...

ADAPTABLE SENSE CIRCUITRY AND METHOD FOR READ-ONLY MEMORY

Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM. 1. A read-only memory (ROM) comprising:a first bit line;a first dummy bit line;a first dummy sense amplifier coupled to the first dummy bit line, the first dummy sense amplifier providing a first output signal;a first sense amplifier coupled to the first bit line; and the first keeper circuit comprising:', 'a first transistor having a first current electrode coupled to the first bit line and a control electrode coupled to an output of the first sense amplifier,', 'a second transistor having a first current electrode coupled to a second current electrode of the first transistor, and a control electrode coupled to a first voltage source, and', 'a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second current electrode of the second transistor, and a control electrode coupled to receive the first output signal., 'a first keeper circuit coupled to the first bit line and the first sense amplifier, the first keeper circuit configured to increase keeper strength based on the first output signal,'}2. The ROM of claim 1 , wherein the first dummy bit line is configured having only one dummy memory cell coupled to the first dummy bit line.3. The ROM of claim 2 , further comprising a flag generation circuit to provide a flag signal indicative that the ROM is no longer in a normal operating condition claim 2 , the flag signal based on the first output signal.4. (canceled)5. The ROM of claim 1 , wherein the first keeper circuit further comprises:a ...

Programmable lsi

A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

NONVOLATILE MEMORY DEVICES WITH ON DIE TERMINATION CIRCUITS AND CONTROL METHODS THEREOF

Non-volatile memory devices including on-die termination circuits connected to an input/output circuit and an on-die termination control logic detecting a preamble of a strobe signal based on a command and a control signal and activating the on-die termination within the preamble period. 136-. (canceled)37. A method of operating a nonvolatile memory device , comprising:receiving a write command via data input/output terminals in synchronization with a write enable signal while a command latch enable signal (CLE) is enabled;receiving an address via the data input/output terminals in synchronization with the write enable signal while an address latch enable signal (ALE) is enabled, wherein after the receiving the write command and the address, the CLE and the ALE is disabled;after the CLE and the ALE is disabled, activating an on-die termination mode of the data input/output terminals in response to a rising edge or a falling edge of a data strobe signal;receiving write data in synchronization with the data strobe signal; anddeactivating the on-die termination mode of the data input/output terminals in response to a transition of at least one of a chip enable signal, the ALE, and the CLE.38. The method of claim 37 , wherein before the receiving the write command or the address claim 37 , the chip enable signal is enabled.39. The method of claim 37 , wherein the activating the on-die termination mode of the data input/output terminals includes adjusting impedance of the data input/output terminals.40. The method of claim 37 , wherein the activating the on-die termination mode of the data input/output terminals includes activating a pseudo differential signaling mode of the data input/output terminals.41. The method of claim 40 , wherein the activating the on-die termination mode of the data input/output terminals includes activating a differential signaling mode of the data strobe signal.42. The method of claim 37 , further comprising:detecting a command attribute of ...

FAST VOLTAGE DOMAIN CONVERTERS WITH SYMMETRIC AND SUPPLY INSENSITIVE PROPAGATION DELAY

In one embodiment, a circuit comprises a phase interpolator that converts a single-ended input to a pair of symmetric differential signals within a first voltage domain. The circuit further comprises a comparator that converts the symmetric differential signals into single-ended output in a second different voltage domain. In one embodiment, the single ended output of the comparator is configured to be coupled to drive a switching driver in a switching regulator. In one embodiment, the interpolator comprises a first inverter, a second inverter, and a third inverter connected in series. The interpolator further comprises a first resistor and a second resistor connected in series. The second inverter provides a first output signal. Outputs of the first inverter and the third inverter are connected by the series connected resistors. A node between the resistors provides a second output signal. The first and second output signals are inverted and symmetric. 1. A level shifter comprising:a phase interpolator configured to convert a single-ended input to a pair of symmetric differential signals within a first voltage domain; anda comparator configured to convert the symmetric differential signals into a single-ended output in a second different voltage domain.2. The level shifter of wherein the single ended output of the comparator is configured to be coupled to drive a switching driver of a switching regulator.3. The level shifter of wherein the interpolator comprises a first inverter claim 1 , a second inverter and a third inverter connected in series claim 1 , and further comprises a first resistor and a second resistor connected in series claim 1 , the second inverter providing a first output signal claim 1 ,wherein the first resistor comprises an input terminal and an output terminal and the second resistor comprises an input terminal and an output terminal, andwherein output of the first inverter is connected to the input terminal of the first resistor and output of ...

TRANSMIT NOISE AND IMPEDANCE CHANGE MITIGATION IN WIRED COMMUNICATION SYSTEM

A method, system and circuit for providing for part or all of a transmitter, when it is in mute mode (not actively transmitting), to be turned off, removed, decoupled or modified in general in order to reduce the total noise submitted by the transmitter to the wired network into network controller. In parallel, an auxiliary circuit or impedance is added or coupled to the transmitter in order to mitigate the total return loss change of the transmitter. When in active transmitter mode, this auxiliary circuit or impedance will be removed or decoupled from the transmitter and transmitter will transmit in normal mode. 1. A method of mitigating transmit noise in a transmission system , comprising: coupling a first stage output to a second stage input; and', 'decoupling an auxiliary circuit from the second stage input to ground; and, 'in an active mode decoupling an output of the first stage to the second stage input; and', 'coupling the auxiliary circuit from the second stage input to ground., 'in a mute mode2. The method of wherein coupling and decoupling comprises using a member from the group consisting of hardware claim 1 , software claim 1 , and firmware.3. The method of further comprising operating the auxiliary circuit to mimic an impedance of a first amplifier of the first stage.4. The method of further comprising configuring the auxiliary circuit to comprise at least one member from the group consisting of a resistive component claim 1 , a capacitive component and a reactive component.5. The method of further comprising selecting the auxiliary circuit based on a frequency range.6. The method of further comprising selecting the auxiliary circuit by circuit simulation or by measurement.7. The method of further comprising synthesizing the auxiliary circuit to achieve a small mismatching error.8. The method of further comprising operating a plurality of active and mute transmitters.9. A method of mitigating effects of an impedance change in a transmission system ...

MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE

The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information. 1. A memory device comprising:a plurality of memory cells;an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells; anda read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.2. The memory device of claim 1 , wherein the first memory cell is an on-cell or an off-cell.3. The memory device of claim 1 , wherein the read voltage controller converts the cell count value corresponding to the default read voltage from an analog value form to a digital value form claim ...

Active Low-Power Termination

An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

SEMICONDUCTOR DEVICE AND MEMORY DEVICE

A semiconductor device of an embodiment includes a buffer configured to perform data transmission by turning on and off a first output transistor group and a second output transistor group; a first correction circuit configured to calibrate a resistance value of the buffer by controlling an on-off state of each of first transistors of the first output transistor group; a second correction circuit configured to calibrate the resistance value of the buffer by controlling an on-off state of each of second transistors of the second output transistor group; and a control circuit configured to cause the calibration by the first correction circuit to be performed in a non-communication duration other than a duration of data transmission from the buffer and cause the calibration by the second correction circuit to be performed in a duration other than a duration of the calibration by the first correction circuit. 1. A semiconductor device comprising:a buffer configured to perform data transmission by turning on and off a first output transistor group and a second output transistor group;a first correction circuit including the first output transistor group and configured to calibrate a resistance value of the buffer by controlling an on-off state of each of first transistors of the first output transistor group;a second correction circuit including the second output transistor group and configured to calibrate the resistance value of the buffer by controlling an on-off state of each of second transistors of the second output transistor group; anda control circuit configured to cause the calibration by the first correction circuit to be performed in a non-communication duration other than a duration of data transmission from the buffer and cause the calibration by the second correction circuit to be performed in a duration other than a duration of the calibration by the first correction circuit.2. The semiconductor device according to claim 1 , whereinthe first correction ...

VARIABLE FILTER CAPACITANCE

Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array. 1. (canceled)2. A method , comprising:determining a filter capacitance for a memory array that comprises capacitive elements, wherein at least one of the capacitive elements comprises cells and access lines in electronic communication with the cells;selecting a subset of the capacitive elements based at least in part on the filter capacitance; andactivating the subset of the capacitive elements based at least in part on the selecting, wherein the filter capacitance is based at least in part on a capacitance of the subset of the capacitive elements after the activation.3. The method of claim 2 , further comprising:electronically coupling a first voltage rail and a second voltage rail with a first subset of the access lines, wherein the capacitance of the subset of capacitive elements regulates a first voltage of the first voltage rail, or a second voltage of the second voltage rail, or both.4. The method of claim 2 , further comprising:measuring, at a first capacitive element of the capacitive elements, a temperature of a first portion of the memory array; and 'selecting other capacitive elements than the first capacitive element for ...

SEMICONDUCTOR DEVICE HAVING IMPEDANCE CALIBRATION FUNCTION TO DATA OUTPUT BUFFER AND SEMICONDUCTOR MODULE HAVING THE SAME

A method for calibrating an output buffer including adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential, applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential, adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential, applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential, and applying the second impedance code to a fourth plurality of second transistor units. 1. A method for calibrating an output buffer , the method comprising:adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential;applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential;adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential;applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential; andapplying the second impedance code to a fourth plurality of second transistor units connected in parallel between the data terminal and the second power supply potential,wherein ...

SIGNAL RECEIVING CIRCUITS INCLUDING TERMINATION RESISTANCE HAVING ADJUSTABLE RESISTANCE VALUE, OPERATING METHODS THEREOF, AND STORAGE DEVICES THEREWITH

A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a first differential signal via a first input terminal and a second differential signal via a second input terminal, and to be selectively connected to the first and second input terminals. The termination resistance circuit has an adjustable resistance value. The resistance adjustment circuit is configured to decrease the resistance value of the termination resistance circuit in response to a signal reception preparation command and connection of the termination resistance circuit to the first and second input terminals. 1. A receiving circuit configured to receive a differential signal , the receiving circuit comprising:a termination resistance circuit connected between a first input terminal and a second input terminal, the termination resistance circuit having a resistance value that is adjustable between a first resistance value and a second resistance value, the second resistance value being less than the first resistance value;a switching circuit configured to control a connection between the termination resistance circuit and each of the first and second input terminals; anda resistance adjustment circuit configured to adjust the resistance value of the termination resistance circuit from the first resistance value to the second resistance value when the termination resistance circuit is disconnected from at least one of the first and second input terminals, and then connected to the first and second input terminals by the switching circuit.2. The receiving circuit of claim 1 , further comprising:the first and second input terminals configured to transmit the received differential signal.3. The receiving circuit of claim 1 , wherein the switching circuit is configured to connect the termination resistance circuit to the first and second input terminals in response to a signal reception preparation ...

MEMORY DEVICE, CONTROLLER CONTROLLING THE SAME, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF

A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode. 1. A memory device comprising:memory device processing circuitry configured totransmit read data to a data channel according to a transmission signaling mode;receive write data from the data channel according to the transmission signaling mode;store the transmission signaling mode; andperform a training operation on the data channel in response to a training request received from an external device, to detect at least one mode parameter in the training operation, to select one of a first transmission signaling mode and a second transmission signaling mode as the transmission signaling mode using the detected mode parameter, and to output mode flag information, associated with the detected mode parameter, to the external device.2. The memory device of claim 1 , wherein the first transmission signaling mode is a non-return-to-zero (NRZ) mode claim 1 , andthe second transmission signaling mode is a pulse amplitude modulation 4-level (PAM4) mode.3. The memory device of claim 1 , wherein the at least one parameter comprises at least one of a termination voltage corresponding to the data channel claim 1 , current consumed by the memory device claim 1 , and channel loss of the data channel.4. The memory device of claim 3 , wherein the memory device processing circuitry comprises a mode detection circuit which further comprises a termination voltage detector configured to detect the transmission signaling mode by comparing the termination voltage with a reference voltage.5. The memory ...

ELECTRONIC DEVICES EXECUTING A TERMINATION OPERATION

An electronic device includes a termination control circuit and a data input/output (I/O) circuit. The termination control circuit is configured to generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed. In addition, the termination control circuit is configured to adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation. The data I/O circuit is configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed. 1. An electronic device comprising:{'claim-text': ['generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed; and', 'adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation; and'], '#text': 'a termination control circuit configured to:'}a data input/output (I/O) circuit configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed.2. The electronic device of claim 1 ,wherein the set detection period is set as a period from a point in time when the write command for the write operation is activated until a point in time when an internal termination-off signal is activated during the write operation; andwherein the internal termination-off signal is generated by delaying a write signal, which is generated based on the write command for the write operation, by a period including a write latency period and a burst length period.3. ...

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit. 1. A semiconductor storage device comprising:an output pad;a first circuit connected to the output pad;a second circuit connected to the first circuit;a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit; anda fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.2. The semiconductor storage device according to claim 1 , wherein the second circuit controls the first circuit.3. The semiconductor storage device according to claim 1 , whereinthe first setting signal adjusts an output resistance of the first circuit, andthe second setting signal adjusts an output timing of the first circuit.4. The semiconductor storage device according to claim 1 , further comprising a temperature sensor claim 1 ,wherein the fourth circuit adjusts the second setting signal based on information related to a temperature output from the temperature sensor.5. The semiconductor storage device according to claim 1 , further comprising a detection circuit configured to detect a supply voltage claim 1 , a voltage having the same magnitude with the supply voltage being supplied to the first circuit claim 1 ,wherein the fourth circuit adjusts the second setting signal based on ...

ASYMMETRICAL I/O STRUCTURE

An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors. 1. An asymmetrical I/O structure , comprising:a first power supply node connected to a first voltage and a second power supply node connected to a second voltage;a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node, wherein a node between the pull-up unit and the pull-down unit is connected to an I/O node;wherein the pull-up unit comprises one or more pull-up transistors, the pull-down unit comprises one or more pull-down transistors, and the number of the pull-up transistors is different from the number of the pull-down transistors, and the first voltage is higher than the second voltage.2. The asymmetrical I/O structure of claim 1 , wherein the pull-up unit comprises a first pull-up transistor claim 1 , the pull-down unit comprises a first pull-down transistor and a second pull-down transistor connected in series claim 1 , wherein the pull-up transistor is a PMOS transistor and the pull-down transistors are NMOS transistors.3. The asymmetrical I/O structure of claim 2 , wherein claim 2 ,a source of the first pull-up transistor is connected to the first power supply node, a drain of the first pull-up transistor is connected to the I/O node, a gate of the first pull-up transistor is connected to an ...

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE

A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a dummy operation on a dummy area among the plurality of memory blocks of the memory cell array. 1. A memory device comprising:a memory cell array including a plurality of memory blocks; anda peripheral circuit configured to perform a dummy program operation on dummy blocks among the plurality of memory blocks of the memory cell array,wherein the peripheral circuit programs dummy data in the dummy blocks in the dummy program operation.2. The memory device of further comprising:a control logic configured to control the peripheral circuit,wherein the control logic controlling the peripheral circuit includes performing the dummy program operation by selecting the dummy blocks from among the plurality of memory blocks.3. The memory device of claim 2 ,wherein the peripheral circuit is configured to perform a program operation and a read operation on the memory cell array, andwherein the control logic controls the peripheral circuit to perform a reprogram operation on the dummy blocks after the program operation and the read operation are performed a set number of times.4. The memory device of claim 2 ,wherein the peripheral circuit is configured to perform a program operation and a read operation on the memory cell array, andwherein the control logic controls the peripheral circuit to perform a reprogram operation on the dummy blocks after a certain time from when the program operation and the read operation are performed.5. The memory device of claim 1 , wherein the peripheral circuit programs all memory cells included in the dummy blocks to have a threshold voltage higher than 0 volts (V) in the dummy program operation.6. The memory device of claim 1 , wherein the dummy blocks are memory blocks disposed at an outermost portion of the memory cell array among the plurality of memory blocks.7. The memory device ...

PROGRAMMABLE VOLTAGE REFERENCE

Subject matter disclosed herein may relate to generation of programmable voltage references. 1. A method , comprising:generating a voltage reference signal, wherein a voltage level of the voltage reference signal is based, at least in part, on a programmable impedance state of a correlated electron switch.2. The method of claim 1 , further comprising adjusting the voltage level of the voltage reference signal by causing a transition in the correlated electron switch from a first impedance state to a second impedance state.3. The method of claim 2 , wherein the adjusting the voltage level of the voltage reference signal comprises adjusting the voltage level to compensate claim 2 , at least in part claim 2 , for temperature variation.4. The method of claim 2 , wherein the adjusting the voltage level of the voltage reference signal comprises adjusting the voltage level to compensate claim 2 , at least in part claim 2 , for process variation.5. The method of claim 2 , further comprising transitioning the programmable impedance state of the correlated electron switch from a first impedance state to a second impedance state at least in part by applying a selectable voltage to the correlated electron device.6. The method of claim 5 , wherein the applying the selectable voltage to the correlated electron device comprises coupling a supply voltage to the correlated electron switch at least in part by enabling a first conductive element through assertion of a write enable signal and at least in part by enabling a second conductive element through assertion of a set signal claim 5 , wherein the first impedance state comprises a higher impedance state and wherein the second impedance state comprises a lower impedance state.7. The method of claim 5 , wherein the applying the selectable voltage to the correlated electron device comprises coupling a supply voltage through a thick oxide transistor to the correlated electron switch at least in part by enabling a first conductive ...

BIT STRING OPERATIONS IN MEMORY

Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings. 1. An apparatus , comprising:sensing circuitry including a sense amplifier and a compute component coupled to a memory array; and one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry, the one or more bit strings each having a same bit string shape; and', 'the sensing circuitry to perform an arithmetic operation, a logical operation, or both using the one or more bit strings., 'a controller coupled to the sensing circuitry and the memory array, wherein the controller is configured to cause2. The apparatus of claim 1 , wherein the sensing circuitry is configured to perform the arithmetic operation claim 1 , the logical operation claim 1 , or both by:performing a first operation phase of the arithmetic operation, the logical operation, or both by sensing a memory cell of the array that contains a first bit of the one or more bit strings;performing a number of intermediate operation phases of the arithmetic operation, the logical operation, or both by sensing a respective number of different memory cells that contain different bits of the one or more bit strings; andaccumulating a result of the of ...

LOW-POWER SENSE AMPLIFIER

A sense amplifier includes: two detection inputs, a latch circuit including two sections coupled to each other and each supplying a data signal. Each section is respectively powered by a P-channel control transistor, having a gate terminal receiving a control signal linked to a respective detection input of the two detection inputs. The sense amplifier includes a control circuit configured to reduce each of the control signals to a sufficiently low voltage to put the corresponding control transistor to the on state, when the control signal reaches a reference voltage. The latch circuit is activated to supply one of the data signals when a corresponding one of the control transistors is in the on state. 1. A sense amplifier , comprising:a first and a second detection input;a latch circuit including a first section configured to supply a first data signal and a second section coupled to the first section and configured to supply a second data signal;a P-channel first control transistor configured to electrically supply the first section, and having a gate terminal configured to receive a first control signal and linked to the first detection input;a P-channel second control transistor configured to electrically supply the second section, and having a gate terminal configured to receive a second control signal and linked to the second detection input;a first control circuit configured to reduce the first control signal to a sufficiently low voltage to put the first control transistor to an on state in response to the first control signal reaching a first reference voltage; anda second control circuit configured to reduce the second control signal to a sufficiently low voltage to put the second control transistor to the on state in response to the second control signal reaching a second reference voltage, the latch circuit being configured to supply the first data signal in response to being activated by the first control transistor being in the on state and being ...

SEMICONDUCTOR DEVICE INCLUDING INPUT/OUTPUT CIRCUIT

Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers. 1. An apparatus comprising:a data terminal;a data output circuit including a plurality of output buffers coupled in common to the data terminal; andan impedance control circuit coupled to the data output circuit, the impedance control circuit configured to generate a first impedance code and a second impedance code different from the first impedance code, and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers.2. The apparatus of claim 1 , wherein the impedance control circuit is configured to apply the selected one of the first impedance code and the second impedance code through a selector.3. The apparatus of claim 2 , wherein the selector is configured to receive the first impedance code and the second impedance code and output the selected one of the first impedance code and the second impedance code.4. The apparatus of claim 3 , wherein the selector is configured to select the first impedance code during a first mode and select the second impedance code during a second mode.5. The apparatus of claim 4 , further comprising:a plurality of bit lines;a plurality of word lines; anda plurality of memory cells arranged at intersections of the bit lines and the word lines, respectively;wherein data is read from at least one of the plurality of memory cells during the first mode, data is written into at least one of the plurality of memory cells during the second mode.6. The apparatus of claim 1 , ...

DIAGNOSTIC MONITORING FOR ANALOG-TO-DIGITAL CONVERTERS

The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected. 1. An analog-to-digital converter (ADC) , comprising:a sampling circuit having a fault tolerance range; and a reception channel having a channel impedance;', 'a diagnostic channel;', 'a switch coupled with the reception channel and the diagnostic channel, and configured to select the reception channel or the diagnostic channel for the sampling circuit; and', 'an impedance compensator coupled with the switch, the impedance compensator having a compensatory impedance equal to or greater than a product of the channel impedance and the fault tolerance range., 'a channel selector having2. The ADC of claim 1 , wherein the impedance compensator is coupled in series between the switch and the sampling circuit.3. The ADC of claim 1 , wherein the impedance compensator is coupled in series between the diagnostic channel and the switch.4. The ADC of claim 1 , wherein the impedance compensator is configured to offset the channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.5. The ADC of claim 1 , wherein:the reception channel includes a first reception channel and a second ...

CALIBRATION CIRCUIT FOR ON-CHIP DRIVE AND ON-DIE TERMINATION

Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed current mirror. In another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed mirror pull-up circuit. In yet another embodiment, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed target impedance. 1. A calibration circuit for setting an on-chip impedance of an integrated circuit to match a target impedance comprising:a first pull-up circuit connected in series with the target impedance between a positive power supply voltage and a reference power supply voltage, the first pull-up circuit being a ratioed pull-up circuit sized to be K/(1−K) times a size of a pull-up circuit unit, K being a number between 0 and 1, other than 0.5, and the positive power supply voltage being a positive power supply voltage for input-output circuits of the integrated circuit;a first comparator configured to compare a voltage at a first common node between the first pull-up circuit and the target impedance to a reference voltage and to generate an output signal to drive the first pull-up circuit so that the voltage at the first common node equals the reference voltage, the reference voltage being K times the positive power supply voltage other than one-half the positive power supply voltage, wherein the first pull-up circuit has an impedance being set equal to (1−K)/K times the target impedance;a second pull-up circuit connected in series with a pull-down circuit between the positive power supply voltage and the ...

CONFIGURABLE OUTPUT DRIVER ASIC

A fuel system includes an electronic control module (ECM), at least one injector coupled to the ECM, and a configurable output driver circuit coupled to the at least one injector. The configurable output driver circuit includes a channel that enables adaptation of ECM outputs. The configurable output driver circuit is configurable based on a value stored in a register circuit. 1. A fuel system , comprising:an electronic control module (ECM);at least one injector coupled to the ECM; anda configurable output driver circuit coupled to the at least one injector, wherein the configurable output driver circuit comprises a channel that enables adaptation of ECM outputs.2. The fuel system of claim 1 , wherein the configurable output driver circuit comprises a configurable output driver application-specific integrated circuit (COD ASIC).3. The fuel system of claim 2 , wherein the COD ASIC is configurable based on a value stored in a register of the ASIC.4. The fuel system of claim 3 , wherein the channel comprises a High-Side (HS)/Low-Side (LS) pair and a boost drive.5. The fuel system of claim 4 , wherein the channel comprises a bootstrap capacitor to create a drive required for the High-Side (HS).6. The fuel system of claim 4 , wherein the channel comprises a charge pump to create a drive required for the High-Side (HS).7. The fuel system of claim 4 , wherein the HS/LS pair drives an un-boosted voltage injector type (solenoid) load.8. The fuel system of claim 4 , wherein the HS/LS pair combined with the boost drive drives a boosted voltage injector type (solenoid) load.9. The fuel system of claim 4 , wherein the channel is a first channel claim 4 , and wherein the configurable output driver circuit further comprises a second channel claim 4 , and wherein the second channel comprises a second HS/LS pair and a second PFET boost drive.10. The fuel system of claim 9 , wherein the second channel is configurable based on a second value stored in a second register of the ASIC.11. ...

PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

TRANSMITTER AND RECEIVER FOR LOW POWER INPUT/OUTPUT AND MEMORY SYSTEM INCLUDING THE SAME

A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

CURRENT LIMITING I/O INTERFACE AND ISOLATED LOAD SWITCH DRIVER IC

Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage. 1. An integrated circuit (IC) , comprising:a first input pin having a reference voltage;a second input pin to receive a digital input voltage signal having a first voltage relative to the reference voltage in a first state, and a different second voltage relative to the reference voltage in a second state; an impedance circuit, including an input connected to the second input pin, and an output to deliver a current signal to a buffer capacitor, the impedance circuit operative in a first mode to connect the second input pin to the buffer capacitor, and in a second mode to provide a controlled impedance between the second input pin and the buffer capacitor to limit an amplitude of the current signal,', 'a precharge circuit to provide a first signal in response to a supply voltage across the buffer capacitor reaching a first threshold voltage, and', 'an impedance connection control circuit to switch the impedance circuit from the first mode to the second mode in response to the first signal;, 'a current limiter circuit, includingan output circuit, including an input connected to the buffer capacitor to receive the supply voltage, and an output isolated from the supply voltage, the output being connected to third and fourth pins of the IC; anda ...

CURRENT LIMITING I/O INTERFACE AND ISOLATED LOAD SWITCH DRIVER IC

Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage. 1. An isolated load switch driver circuit , comprising:a signal input to receive a digital input voltage signal;an output circuit to provide a digital output voltage signal isolated from the digital input voltage signal;a buffer capacitor having a first terminal connected to a reference voltage and a second terminal;current limiter circuit, including first and second transistors connected in a back-to-back configuration between the signal input and the second terminal of the buffer capacitor; a first output to provide a first signal to a control terminal of the first transistor to turn the first transistor on in response to the digital input voltage signal transitioning from the reference voltage to a second voltage, and', 'a second output to provide a second signal to a control terminal of the second transistor to turn the second transistor on in response to the digital input voltage signal transitioning from the reference voltage to the second voltage until a voltage of the second terminal of the buffer capacitor reaches a first threshold voltage; and, 'a first control circuit, includinga second control circuit to provide a third signal to the control terminal of the second transistor to limit an amplitude of a current signal flowing from the ...

Driving integrated circuit

A driving integrated circuit (IC) is disclosed. The driving IC comprises a signal processing circuit, a receiver and a terminal resistance providing circuit. The receiver is coupled to a first transmission line and a second transmission line and is output to the signal processing circuit after receiving a transmission signal through the first transmission line and the second transmission line. The terminal resistance providing circuit is coupled to the receiver.