Адаптивный формирователь импульсов

Изобретение предназначено для задания формы импульсов путем дискретизации сигнала пи времени и амплитуде. Цель изобретения - расширение области применения путем обеспечения автоматической компенсации изменений параметров реальной нагрузки. Для достижения указанной цели в формирователь импульсов, содержащий генератор 3 тактовых импульсов, счетчик 5, запоминающее устройство б и ЦАП О, введены устройство 4 управления, блок 7 стробировэиия и блок 9 адаптации с соответствующими связями, 1 з.п. ф-лы, 6 ил.

VERFAHREN UND ANORDNUNG ZUR STOERIMPULSUNTERDRUECKUNG AN DIGITALEN SIGNALEINGAENGEN

Improvements in or relating to electric timing circuits

... 636,416. Automatic control systems. SPERRY GYROSCOPE CO., Inc. Aug. 1, 1947, No. 21032. Convention date, May 14, 1943. [Class 38 (iv)] [Also in Groups XXXVI and XL (c)] In an arrangement for generating a signal having steep wave-fronts formed by a periodic component that abruptly reverses in sign, this component is synchronized with a similar component of a reference signal. In the embodiment described, the reference signal comprises a rectangular waveform A, Fig. 2, generated at the anode of valve 29, Fig. 3, of a flip-flop multivibrator 11, triggered by pulses applied to terminals 26<1>. The length of the rectangular waveform is set by a manual bias control 34. The controlled waveform B, Fig. 2, is generated at the anode of the second valve of the multivibrator 14 which is triggered by the same pulses from terminals 26<1>. The pentagrid coincidence valve 15 has waveforms A and B<1>, which is an inverted form of B derived from the first valve of multivibrator 14, respectively applied to ...

Clock adjustment

METHOD OF PULSE-FORMING AND RENEWABLE-DURATION VARIABLE PULSE-FORMING CIRCUIT FOR THE APPLICATION OF SAID METHOD

... 1,222,160. Pulse circuits. COMMISSARIAT A L'ENERGIE ATOMIQUE. 14 June, 1968 [21 June, 1967], No. 28473/68. Heading H3P. A method of lengthening a pulse comprises transmitting each incident pulse t 0 to a sealer 18 for resetting the sealer 18, directing the resultant signal 28 to a re-cycling pulse generator 30, re-cycling pulses from generator 30 to the sealer 18 until a predetermined number has been registered and converting (at 32 and 36) to a single long pulse, the successive pulses from generator 30. The circuit described operates at intervals between a few tens of nanosecond and a few microseconds, the sealer 18 being reset by further input pulses occurring during the long output pulse so that the resulting output pulse ends at the predetermined time after the last input pulse. As shown, each pulse at 14 triggers a univibrator 20 giving a pulse of duration p which is delayed at 22 before triggering a second univibrator 24, the output of which resets the scaler 18, comprising three ...

Improvements in or relating to delay circuits

... 756,285. Pulse delaying circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 14, 1954, No. 26657/54. Class 40 (6). [Also in Group XIX] A delay circuit, for use in a digital computer (see Group XIX), receives input data indicative pulses at a terminal B, Fig. 1, and synchronizing pulses at a terminal A, the pulse train being as shown in Fig. 2, and as a result produces a pulse train at E corresponding to the input train at B but delayed by one unit of time, which is amplified by a double triode 35 to give an output at H equivalent to the input train at B delayed by one unit of time, there being feed-back from point H to point E via a resistor 48 for pulse-shaping purposes. The leading negative edge of a data indicative pulse applied to terminal B tends to cause a negative pulse at point C' but this is prevented by a rectifier 23, and the leading edge therefore has a negligible effect. The positive-going trailing edge however does have some effect and causes points C and D to rise ...

CIRCUIT ARRAGEMENT FOR GENERATING SIGNAL EYCURSIONS OF A STANDARD LENGTH IN RESPONSE TO THE OCCURRENCE OF TEMPORARY EXCURSIONS OF AN INPUT SIGNAL IN A GIVEN DIRECTION FROM A STANDARD VALUE

DELAY CLOCK PULSE WIDTH ATTITUDE CIRCUIT FOR INTERMEDIATE FREQUENCY OR HIGH FREQUENCY

TELEPHONE DIALING CIRCUIT

GENERATING PRECISE OVERLAPPING TIMING PULSES

DYNAMIC RATIOLESS CIRCUITRY FOR RANDOM LOGIC APPLICATIONS

INTEGRAL MEMORY IMAGE DISPLAY OR INFORMATION STORAGE SYSTEM

Verfahren zum Veredeln von Textilien aus hochmolekularen Polyestern, insbesondere zur Verbesserung ihrer Anfärbbarkeit

Verfahren zur Herstellung von Fäden aus hochmolekularen Polyestern

Impulsverstärkeranordnung mit Rückkopplung

Dispositif à transistor amplificateur et conformateur d'impulsions, sans circuit de réaction

Verfahren zur Herstellung von besser anfärbbaren Fäden aus hochmolekularen Polyestern

Régénérateur d'impulsions électriques.

Dispositif régénérateur d'impulsions.

Transistor

Frequenz-Spannungs-Wandler

Modulateur de durée d'impulsions

DENSITOMETER.

ELEKTRONISCHE SELBSTHALTESCHALTUNG.

Impulsformschaltung

Schaltung zum verzerrungsfreien Abschalten einer rechteckförmigen Signalwelle in einem beliebigen Zeitpunkt

Elektronische Vorrichtung mit einem Transistor

Procédé de mise en forme d'impulsions et équipement pour la mise en oeuvre de ce procédé

Verfahren zum Veredeln von Textilien aus hochmolekularen Polyestern, insbesondere zur Verbesserung ihrer Anfärbbarkeit

РЕГИСТР СДВИГА

Регистр сдвига относится к технике цифровой обработки информации в ее бинарном представлении (то есть в представлении в виде двоичных единиц и нулей), везде, где необходимо запоминать и хранить полезную текущую цифровую информацию.

Sampling interval non-uniformity correction circuit and method

Triangular carrier generator for random pulse width modulation

Logical circuit with transistron, forming in particular amplifying

TRANSISTORS

Device to convert impulses of entry into impulses of exit of practically invariable width and amplitude

GENERATEUR D'IMPULSIONS DE CADENCEMENT ET MEMOIRE DYNAMIQUE UTILISANT CE GENERATEUR

GENERATEUR D'IMPULSIONS DE CADENCEMENT ET MEMOIRE DYNAMIQUE UTILISANT CE GENERATEUR. CE GENERATEUR COMPORTE UN TRANSISTOR IGFET Q APPLIQUANT UNE IMPULSION D'ENTREE A UN PREMIER NOEUD N1, UN CONDENSATEUR AUTO-ELEVATEUR C BRANCHE ENTRE CE NOEUD ET UN SECOND NOEUD, ET UN ETAGE D'ATTAQUE Q, Q, Q A Q RECEPTIF A UNE TENSION APPARAISSANT SUR LE PREMIER NOEUD POUR PRODUIRE SUR LE SECOND NOEUD UNE TENSION DE SORTIE AMENEE AU NIVEAU BAS LORSQUE LA TENSION D'ENTREE EST INFERIEURE A UNE VALEUR DONNEE, ET AMENEE AU NIVEAU HAUT LORSQUE LA TENSION D'ENTREE EST SUPERIEURE A CETTE VALEUR, CE QUI FOURNIT UN SIGNAL A NIVEAU RELEVE SUR LE PREMIER NOEUD N1. APPLICATION NOTAMMENT AUX MEMOIRES DYNAMIQUES A ACCES DIRECT A TRANSISTORS IGFET.

PROCESS AND DEVICE Of SAMPLING OF NUMERICAL DATA IN SYNCHRONOUS UNETRANSMISSION, WITH MAINTENANCE OF the BINARY INTEGRITY

LOGICAL GENERATOR OF SIGNAL PSEUDOPERIODIQUE.

DEVICE FOR THE STANDARDIZATION OF RAPIDS VIBRATIONS OF SIGNAL

METHOD OF REMOVING THE STREAM JITTER OF AN INPUT DIGITAL SIGNAL.

PULSE GENERATOR TIMING AND DYNAMIC MEMORY USING THE GENERATOR

Synchronization pulse generator for synchronous integrated circuit, has clock input for receiving forcing signal provided by clock output, independent to clock signal, for permitting transparency of register

L'invention concerne un générateur d'impulsions de synchronisation destinées à au moins deux registres, comprenant une première entrée (CK) destinée à recevoir un signal d'horloge et au moins une sortie (CP) destinée à fournir les impulsions sur l'entrée d'horloge desdits registres, caractérisé en ce qu'il comporte au moins une deuxième entrée (SETH) destinée à recevoir un signal de forçage de la sortie, indépendamment du signal d'horloge, pour rendre transparents lesdits registres.

DUTY COMPENSATION VOLTAGE GENERATOR AND THE METHOD THEREOF

INVERTER CIRCUIT CAPABLE OF CONTROLLING DUTY CYCLE

PURPOSE: An inverter circuit is to control a duty cycle of circuit by regulating a threshold voltage of transistor receiving a feedback signal. CONSTITUTION: An inverter circuit(100) includes a first and second transistors(Q1,Q2) sharing common input signals which are provided to gate terminals of the first and second transistors. The gate terminals of the first and second transistors generate output signals having a duty cycle from drain terminals of the first and second transistors. A control circuit(120) is connected between the drain terminal of the frist transistor and back gate terminal of the first transistor, and supplies a feedback signal of the output signals to the back gate terminal of the first transistor. Thereby, the back gate terminal of the first transistor regulates a threshold voltage of the first transistor receiving the feedback signal. The first transistor is PMOS transistor. The second transistor is NMOS transistor. COPYRIGHT 2000 KIPO ...

FREQUENCY GENERATION CIRCUITRY AND METHOD

A method includes generating a plurality of reference phases of a reference signal and selecting a sub-phase from each of the plurality of reference phases to form a set of selected sub-phases. In the method selecting operates in response to synchronized outputs of a multi-phase phase accumulator that operates synchronously in accordance with one of the sub-phases of the set of sub-phases, and where the outputs of the multi-phase phase accumulator may be synchronized using at least one additional sub-phase.

DIGITAL PULSE STRETCHER

An apparatus for varying the pulse width of a computer clock by adding a predetermined amount of time to the clock pulse width. A synchronous counter (10) is combined with a latch (103) into a circuit whereby a pulse input to the circuit resets both the latch (103) and counter (101) on the leading edge, and whereby the trailing edge of the input pulse releases the latch (103) and counter (101) allowing the counter (101) to count clock pulses. On a predetermined pulse the counter's carry-output terminal clocks a logic high into the D latch terminal. Concurrently, an output from the latch (103) is fed back to the counter's count-enable input to disable counting until a subsequent pulse resets the circuit. The net effect is to add a predetermined amount of time to the input pulse so that the extended pulse is available at the output of the latch (103).

Control device for an electronic wrist watch

A control device for an electronic wrist watch to enable resetting of the display. The device includes a pushbutton switch providing a control signal to a memory device. The memory device is connected to a delay means which transmits the information from said memory device in synchronism with a clock signal to provide an output pulse or pulse train dependent upon the length of time for which the pushbutton is actuated.

Circuit for controlling pulse width

Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.

SYSTEM CLOCK STRETCH CIRCUIT

PURPOSE: To expand the period of a system clock at the time of the access of a low-speed device, etc., by providing a system clock stretch circuit to a data processor and expanding the system clock based on a system clock delay signal which is received during processing execution. CONSTITUTION: The stretch circuit 4 which generates an inverted signal synchronizing with a frequency-divided signal is provided in the data processor and the period is delayed based on the system clock delay signal passed during the execution processing is delayed to expand the system clock. Namely, when an input signal C is inputted to a memory access signal/software setting signal circuit 3, this circuit 3 controls the stretch circuit 4 to generate a signal delayed by the specific number of clocks which this input signal C is inputted. The long-period signal which is delayed by the specific number of clocks is supplied to clock phase varying circuits 5-1 and 5-2 to generate system clocks CLKQ and CLKE which ...

SIGNAL-SHOT PULSE GENERATING CIRCUIT

PURPOSE: To obtain a single-shot pulse of long pulse width without using a large scale accumulator, by triggering a generator by a plural number of continuous pulses. COPYRIGHT: (C)1978,JPO&Japio ...

SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that enhances a degree of freedom of waveform generation in pulse waveform generation without the need for increasing a circuit scale, lightens a processing load on a CPU even in a periodic modulation operation and causes no response delay. SOLUTION: The semiconductor integrated circuit includes: a dead time setting register 17 for storing a value to set a dead time; a pulse width setting register 20 for storing a value to set a pulse width; an adder 19 for adding a value to set the dead time to a value to set the pulse width and outputting the sum; a timer counter 12 for counting an elapsed time and outputting a count denoting the elapsed time; a comparator circuit 15 for comparing the count outputted from the timer counter 12 with the sum outputted from the adder 19; and a waveform generating circuit 26 for generating a pulse waveform on the basis of the result of comparison by the comparator circuit 15. COPYRIGHT: (C ...

УСТРОЙСТВО ТАКТОВОЙ СИНХРОНИЗАЦИИ ЦИФРОВОГО СИГНАЛА

Устройство тактовой синхронизации цифрового сигнала относится к импульсной цифровой технике. Техническим результатом является повышение помехоустойчивости устройства и комплексного расширения его функциональных возможностей за счет формирования на выходах устройства синхронизированного сигнала и его тактового синхросигнала с заградительной фильтрацией как помехи входного синхронизируемого цифрового сигнала при длительности его нулевой или единичной фазы, не превышающей длительности периода входных тактовых импульсов. Для этого устройство содержит три триггера, вход Логической "1", тактовый вход, вход синхронизируемого цифрового сигнала и первый выход, кроме того, новым в устройстве является то, что оно дополнительно содержит элемент ИЛИ-НЕ, элемент Исключающее ИЛИ и второй выход, причем первый выход устройства является выходом третьего триггера и синхронизированного сигнала, а второй выход устройства является выходом тактового синхросигнала и соединен с выходом второго триггера, тактовым ...

Формирователь импульсов

Устройство тактовой синхронизации

Формирователь одиночного импульса

Изобретение относится к импульсной- технике, может быть использовано в устройствах измерительной и вычислительной техники, где необходимо формирование одиночного импульса, Целью изобретения является повышение вхождения в синхронизацию. Для этого /4 в устройство, содержащее триггеры 1и 2, блок 3 сравнения, счетчик 4, шину входов задания числа, введены генератор 5 ударного возбуждения, счетчик 6, триггер 7, элементы И 8-11, элемент 12 ИЛИ, причем второй 2и третий 7 триггеры, .RS-типа. Устройство содержит шины 13 запуска, 14 синхронизации, выходную 15. Чтобы длительность импульса была кратна периоду синхронизации импульсов,должно выполняться условие T5. (Na-3)T /N2-2. Тогда Т () Т,, где N - число, заданное на коэффициент пересчета счетчика 11. В предлагаемом устройстве с помощью генератора 5 ударного возбуждения фор- мируетс.я только часть импульса, погрешность длительности, вносимая генератором ударного возбуждения, во столько- же раз меньше. 2 ип. О S (Л с: го 1 00 ...

Vorrichtung zum Erzeugen eines auf einen Referenztakt synchronisierten Taktsignals

Vorrichtung zum Erzeugen eines auf einen Referenztakt synchronisierten Taktsignals, - mit einer digital ausgestalteten, ausschließlich digitale Komponenten oder Baugruppen umfassenden, Oszillatoreinrichtung (4) zum Erzeugen eines Taktsignals mit einer bestimmten Taktfrequenz (fT), und - mit einer ausschließlich digitale Komponenten und Baugruppen umfassenden digitalen Steuereinrichtung (3), die einen dem Referenztakt entsprechenden ersten digitalen Zeitreferenzwert (PCR) und einen der von der digitalen Oszillatoreinrichtung (4) augenblicklich erzeugten Taktfrequenz (fT) entsprechenden zweiten digitalen Zeitreferenzwert (STC) empfängt und derart ausgestaltet ist, daß sie den ersten digitalen Zeitreferenzwert (PCR) mit dem zweiten digitalen Zeitreferenzwert (STC) vergleicht und abhängig von der Abweichung zwischen den beiden digitalen Zeitreferenzwerten einen digitalen Stellwert (INCR) für die digitale Oszillatoreinrichtung (4) erzeugt, wobei die digitale Oszillatoreinrichtung (4) abhängig ...

Electronic circuit for signal standardisation - has AND circuit to whose inputs timing signals and signal to be standardised are applied

The two signals are the signal to be standardised, and a timing signal; this circuit output is connected to the inputs of a first and second OR circuits, whose outputs are connected to the inputs of a second AND circuit. Its output delivering the standardised output signal is connected to the second input of the first OR circuit, and the negated timing signal is connected to the second input of the second OR circuit. The circuit consists of faultless logic units, whose inputs and outputs operate with a.c. signals through input and output transformers, whose windings at the logic unit inputs are connected by one end to the d.c. supply voltage. A dynamic input signal is applied to their other ends.

Schaltungsanordnung zur Feststellung und Speicherung eines Eingangssignals

Improvements in or relating to electric pulse reshaping circuits

... 726,262. Pulse-shaping circuits. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. May 8, 1953 [May 10, 1952], No. 12934/53. Class 40 (6). In a pulse-reshaping circuit of the type in which a distorted input pulse and a synchronizing pulse are applied to a valve having a transformer in its output circuit the primary winding of which serves as an inductive load and from the secondary of which a reshaped output pulse and.a feedback voltage is taken, an inductive load of low impedance is used and the valve circuit is arranged to present a low effective internal resistance. In this way the load is given effectively a large time constant so that a flat top is obtained to the reshaped pulses. Fig. 1 shows a reshaping circuit in which the distorted input pulse 21 and a negative feedback pulse 7 are applied to a comparing circuit comprising germanium rectifiers 15, 16 so that the voltage at point 14 follows the more negative of the two voltages applied at terminals 12, 13. Valve 18 is normally conducting until ...

Delayed clock signal generator

TIMMING SIGNAL GENERATING CIRCUITS

... 1524768 MOS monostable circuit NIPPON ELECTRIC CO Ltd 29 March 1977 [31 March 1976] 13196/77 Heading H3T In a monostable circuit. Fig. 1, a FET Q3 has a capacitor CF between its gate and source, and an input signal # connected to its drain, means Q1 for applying a precharge voltage to the gate, respective means Q2, Q4 for discharging nodes 1 and 2 and a delay circuit 30 connected as shown. Operation: -# is normally low, and complementary signal #. enables Q1 to charge node 1 thus enabling Q3 when # goes High, #. goes Low, turning off Q 1 and allowing 1 to float. As Q3 is kept ON by the stored charge at 1, Node 2 follows # High and forces Node 1 higher by bootstrapping through CF. After the predetermined delay of 30, Node 3 goes High, enabling Q2 and Q4. Then Node I discharges through Q2, Q3 is turned OFF, Node 2 discharges through Q4 and becomes Low, and Node 3 follows after the predetermined delay, turning off Q2, Q4. Thus the duration of an output pulse at OUT is determined by the delay ...

ELECTRIC CIRCUITS

Pulse signal translating apparatus

... 811,943. Pulse delaying circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 21, 1955 [Dec. 31, 1954], No. 36611/55. Class 40 (6). In a pulse train delay circuit the input pulse train and a train of clock pulses are applied to a capacitor, the voltage of one plate of which changes from a first to a second value during the clock pulse period following an input pulse and from the second to a third value in the same period following the absence of an input pulse. An output pulse being produced if the voltage has moved from the second towards the third value immediately preceding a clock pulse. Fig. 1 shows a circuit for producing the delayed complement of a train of binary coded pulses applied to its input. The clock or sync. pulses are applied from a source 15 and a source of negative-going input pulses via diode 12 to a capacitor 10 which is connected by a resistor 11 to a D.C. source which has a value dependent upon the clock pulse frequency. The input pulse level is normally + 30 ...

LINEARIZING CIRCUIT

... 1294489 Measuring frequency non-linearly SOLARTRON ELECTRONIC GROUP Ltd 29 April 1971 [12 May 1970] 23001/70 Heading G1U [Also in Division H4] In order to produce a signal which varies linearly with a physical variable from the output of a transducer that produces a pulse train whose frequency varies non-linearly with the physical variable, every Nth pulse from the transducer 12, Fig.1, both sets a trigger 18 'on' causing its Q output to go high, see Fig. 3, and resets a counter 10 to zero, the trigger 18 remaining 'on' for a fixed duration To until a preset number of pulses from a reference oscillator 11 has been counted, whereupon it is set 'off' by a comparator 16, and the whole process is repeated indefinitely producing waveforms Q and Q, Fig. 3, having the stated mark/period ratios, which waveforms are applied to a circuit Fig. 4 so designed that its effective gain varies in such a way as to produce an output signal whose amplitude varies linearly with the physical variable. In the ...

SIGNAL PROCESSING APPARATUS

... 1357666 Pulse delaying circuits; distortion correction INTERNATIONAL BUSINESS MACHINES CORP 24 May 1972 [21 June 1971] 24382/72 Headings H3P and H4P A circuit for delaying leading and trailing edges of a pulse (e.g. to correct errors determined by a computer analyser or to predistort pulses for testing apparatus response) comprises means for producing signals corresponding to the leading and trailing edges of pulses, means for variably delaying each signal and means for reconstituting the pulses from the delayed signals. In Figs. 1a and 1b input pulses ABC, e.g. from a magnetic store or other multipath system are applied to a circuit 2 which produces pulses d1, d2, d3, &c. at the leading and trailing edges. These are fed to delay circuits #1, #2, #3 having delays determined by a regulator 4 and appropriate output pulses from the delays are selected in accordance with a program applied at t1 t2, t3 to produce, for example, pulses d11, d21, d3< ...

SURGE GENERATOR

DEMODULATOR FUER STATISCHE RUNDSTEUEREMPFAENGER

DEVICE FOR OPTICAL SIGNAL PROCESSING

DEMODULATOR FOR STATIC ROUND TAX RECEIVERS

PROCESS FOR THE EQUALISATION OF PULSE WIDTHS OF A DIGITAL SIGNAL

PROGRAMMABLE SIGNAL DISTRIBUTION SYSTEM

Single direction waveform adjusting device

CHARACTERIZATION OF the GIGUE Of a CLOCK SIGNAL

Generating or regenerating circuits of impulses

Synchronized electronic line of delayed-action

Selector circuit of duration of impulses

PROCESS AND ELECTRONIC DEVICE OF GENERATION Of a VARIABLE CLOCK SIGNAL

Suivant ce procédé on applique répétitivement à une entrée de commande (G) d'un circuit logique (1) à propagation de retenue une commande (M) de génération de retenue, on cadence au moyen d'un signal d'horloge de référence (CLKR) l'application de ladite commande (M) à ladite entrée (G), on cadence, au moyen dudit signal d'horloge de référence (CLKR), l'application à ladite entrée (G) d'une commande d'effacement de la dernière retenue appliquée à ladite entrée, on commande ledit circuit logique (1) pour propager ladite retenue générée et l'effacement consécutif de ladite retenue générée jusqu'à une sortie de retenue (C) dudit circuit logique (1), on modifie d'un cycle à un autre dudit signal d'horloge de référence (CLKR) la commande (M) pour faire varier-la durée de propagation de ladite retenue dans ledit circuit logique (1), et on génère ledit signal d'horloge variable (CLKV) à partir de l'état logique présent sur ladite sortie de retenue (C).

OVERLAP TIMING CONTROL CIRCUIT FOR CONDITIONING SIGNALS IN A SEMICONDUCTOR MEMORY

METHOD OF PULSE-FORMING AND RENEWABLE-DURATION VARIABLE PULSE-FORMING CIRCUIT FOR THE APPLICATION OF SAID METHOD

GENERATOR Of IMPULSES.

Polyphase MOSFET circuit for pulse duration variations - uses ring counters with decoders connected to RS flip flop controlled by digital signal applied to AND gates

APPARATUS AND METHOD INDEPENDENTLY VARYING THE WIDTHS OF A PLURALITY OF PULSES

PULSE WIDTH CONTROL CIRCUIT AND CONTROLLING METHOD OF THE SAME FOR IMPROVING RELIABILITY OF DATA BY GENERATING VARIABLE PULSE WIDTH ACCORDING TO OPERATIONAL FREQUENCY

PURPOSE: A pulse width control circuit and controlling method of the same are provided to remove an operational error of a DRAM or a DDR at a high frequency by securing operations for stably reading and writing data and by securing a precharge time of a local input/output line. CONSTITUTION: A pulse comparison circuit(100) is provided to compare a target pulse with a pulse synchronized with a clock. A counter pulse generation circuit(200) is provided to generate a counter pulse according to an output of the pulse comparison circuit. A pulse counter circuit(300) is provided to output sequentially a plurality of pulse counter signals according to the counter pulse. A pulse delay circuit(400) is provided to control the width of the pulse synchronized with the clock according to the pulse counter signals. © KIPO 2006 ...

ELECTRONIC CIRCUIT OF HOOK

Analog synchronous mirror delay circuit, method of generating a clock and internal clock generator using the same

A method of generating a clock may use an analog synchronous mirror delay (ASMD) circuit with a duty cycle correction scheme, and an internal clock generator may use one or more of the ASMD circuits. The ASMD circuit may include a comparator with a first and a second input terminals that generates an output clock based on a comparison result between a signal on the first input terminal and a signal on the second input terminal, a first precharge circuit connected to the first input terminal and precharging the first input terminal, and a second precharge circuit connected to the second input terminal and precharging the second input terminal. The ASMD circuit may also include a first pair of discharge circuits discharging the first input terminal within the first and the second cycles of the input clock, and a second pair of discharge circuits discharging the second input terminal within the first and the second cycles of the input clock.

METHOD FOR OPERATING A PULSE GENERATOR FOR CAPACITIVE SENSORS, AND PULSE GENERATOR

The invention relates to a method for operating a pulse generator (1) for generating measuring pulses for a capacitive sensor having an adjustable pulse time in the range from 10 ns to 200 ns, having a controllable delay circuit (2) which contains a first integrating RC combination (RT1/CT1) and a second integrating RC combination (RT2/CT2), having a logical combining element (3) having two inputs and one output, an initialization circuit (5) and a control unit (4), wherein the first input of the logical combining element (3) receives a clock signal, and the second input of the logical combining element (3) receives an analog setting signal (SSE) from the output of the delay circuit (2), wherein two simultaneous clock signals are generated, of which the first clock signal (T) is led without delay to the first input of the logical combining element (3), and the second clock signal (T2), delayed by the delay circuit (2), is led to the second input of the logical combining element (3), time-variable ...

Duty cycle correction

Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value.

INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION

Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern. 1. A method of operation of an integrated circuit device , the method comprising:transmitting, from a first integrated circuit device, a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference;transmitting, from the first integrated circuit device, a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference; andgenerating a timing offset for transmitting data from the first integrated circuit device, wherein the timing offset is derived from information received from a second integrated circuit device sampling the differently-delayed rising edge transitions of the first calibration pattern and the differently-delayed falling edge transitions of the second calibration pattern.2. The method of claim 1 , wherein generating the timing offset comprises:determining a first timing location with respect to the timing reference based at least on the sampled differently-delayed rising edge transitions;determining a second timing location with respect to the timing reference based at least on the sampled differently-delayed falling edge transitions;computing a third timing location by averaging the first timing location and the ...

Method and apparatus for determining duty cycle of a clock in a circuit using a configurable phase locked loop

An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples.

Method for Selecting Natural Frequency in Resonant Clock Distribution Networks with no Inductor Overhead

An inductor architecture for resonant clock distribution networks is described. This architecture allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. The proposed architecture exhibits no inductor overheads. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. Moreover, it is applicable to the binning of semiconductor devices according to achievable performance levels. 1. A resonant clock distribution network , comprising: an inductive element electrically coupled with a clock node of the respective resonant clock driver; and', 'a decoupling switch corresponding to the inductive element, wherein the inductive element of each of the plurality of resonant clock drivers is configured to be selectively controlled by the corresponding decoupling switch;, 'a plurality of resonant clock drivers electrically coupled with a clock distribution network, each resonant clock driver includingwherein each of the plurality of resonant clock drivers is electrically coupled with each of the other plurality of clock drivers.2. The resonant clock distribution network of claim 1 , wherein a natural frequency of the resonant clock distribution network is a function of a total number of inductive elements enabled in the resonant clock distribution network and the natural frequency of the resonant clock distribution network is adjusted by selecting a number of inductive elements to be enabled in the resonant clock distribution network claim 1 , the selected number of inductive elements introducing capacitance or inductance via the electrical couplings of each of the plurality of resonant clock drivers with each of the other plurality of clock drivers to adjust the natural frequency of the resonant clock distribution network.3. ...

Correction Circuit for Output Duty of Hall Element, Hall Sensor and Method of Correcting Output Duty of Hall Element

Disclosed herein are a correction circuit for output duty of a Hall element, a Hall sensor, and a method of correcting the output duty of the Hall element. According to an exemplary embodiment of the present invention, the correction circuit includes an amplification and output unit for amplifying an output of the Hall element and outputting a sqaure wave signal; a duty detection unit for detecting a duty ratio of the sqaure wave signal output by the amplification and output unit; and a duty correction unit for applying a feedback correction signal to the amplification and output unit accoring to the detected duty ratio. 1. A correction circuit for output duty of a Hall element , the correction circit comprising:an amplification and output unit for amplifying an output of the Hall element and outputting a sqaure wave signal;a duty detection unit for detecting a duty ratio of the sqaure wave signal output by the amplification and output unit; anda duty correction unit for applying a feedback correction signal to the amplification and output unit accoring to the detected duty ratio.2. The correction circit according to claim 1 , wherein the duty detection unit calculates the duty ratio by counting high sections and low sections according to previously set clocks during one cycle of the square wave signal.3. The correction circit according to claim 1 , wherein the duty correction unit includes:a state machine for generating a duty ratio correction bit according to the duty ratio detected by the duty detection unit; anda hysteresis section control unit for feeding back and controlling a width of a hysteresis section for outputting the square wave signal, according to the duty ratio correction bit generated by the state machine.4. The correction circit according to claim 2 , wherein the duty correction unit includes:a state machine for generating a duty ratio correction bit according to the duty ratio detected by the duty detection unit; anda hysteresis section control ...

Frequency multiplier circuit with function of automatically adjusting duty cycle of output signal and system thereof

A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%. 1. A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal , comprising:an input terminal,a frequency multiplier control unit connected to said input terminal,an output terminal connected to said frequency multiplier control unit,a first detecting unit connected to said frequency multiplier control unit and said output terminal,a second detection unit connected to said frequency multiplier control unit and said output terminal,a duty cycle adjusting unit connected to said first detecting unit, said second detecting unit and said frequency multiplier control unit, anda ground terminal connected to said first detecting unit and said second detecting unit;wherein said frequency multiplier control unit comprises:a first buffer connected to said input terminal,an AND gate connected to said input terminal and said first buffer,a first NOR gate connected to said input terminal and said first buffer, anda second NOR gate connected to said AND gate and said first NOR gate;wherein said first detecting unit comprises: ...

DUTY CYCLE DISTORTION CORRECTION CIRCUITRY

Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high. 1. A circuit , comprising:an input that receives a control signal having a duty cycle; andan output on which an output clock signal is generated, wherein the output clock signal has a duty cycle that is set by the control signal and that is different than the duty cycle of the control signal.2. The circuit defined in claim 1 , wherein the control signal received at the input comprises an input clock signal.3. The circuit defined in claim 1 , further comprising:an additional input that receives another control signal, wherein the control signal is a delayed version of the another control signal.4. The circuit defined in claim 1 , further comprising:an additional input that receives another control signal, wherein the control signal is a delayed version of the another control signal, and wherein the control signal is delayed by an amount with respect to the another control signal that sets the duty cycle of the output clock signal.5. The circuit defined in claim 1 , further comprising:a first additional input that receives a first additional ...

FORWARDED CLOCK JITTER REDUCTION

In some embodiments, a differential amplifier with duty cycle correction is provided. 1. A chip , comprising:a differential amplifier to receive a differential clock; andan offset compensation circuit coupled to the amplifier to adjust offset in the differential clock, the offset compensation circuit to be digitally controlled based on offset in the differential clock.2. The chip of claim 1 , in which the differential clock is a forwarded clock from another chip.3. The chip of claim 1 , in which the offset compensation circuit is disposed between the amplifier and electrical contacts for receiving the clock from off of the chip.4. The chip of claim 1 , in which the offset compensation circuit is part of an active filter circuit.5. The chip of claim 4 , in which the active filter circuit implements a continuous time linear equalizer circuit.6. The chip of claim 1 , comprising a variable offset comparator to receive a low-pass filtered version of the differential clock to generate a digital value representing whether or not a duty cycle of the clock is above or below a threshold.7. The chip of claim 6 , in which the duty cycle threshold is 50%.8. The chip of claim 1 , comprising a switch to receive a failover clock to be used as the differential clock.9. A chip claim 1 , comprising:a differential amplifier having an input to receive a differential clock and an output to provide a duty cycle adjusted clock; andan offset adjustment circuit coupled between the input and output, said offset adjustment circuit including a variable offset comparator (VOC) with self offset correction, a differential offset compensation (DOC) circuit having an output coupled to the input of the differential amplifier, and a control circuit coupled between the VOC and DOC to control output clock duty cycle.10. The chip of claim 9 , in which the differential clock is a forwarded clock from another chip.11. The chip of claim 9 , in which the offset compensation circuit is disposed between the ...

PARTIAL RESPONSE RECEIVER AND RELATED METHOD

A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal. 1. (canceled)2. An integrated circuit comprising:a two phase partial response equalizer circuit;the two phase partial response equalizer circuit having a first sampler circuit to sample an input signal to generate a first sampled signal in response to a first sampling clock having a first phase, and a second sampler circuit to sample the input signal to generate a second sampled signal in response to a second sampling clock having a second phase;the two phase partial response equalizer circuit having a first feedback path to control partial response selection by the first sampler circuit in dependence on the second sampled signal and a second feedback path to control partial response selection by the second sampler circuit in dependence on the first sampled signal;a latch in the first feedback path, the second feedback path not having a latch; andcircuitry to generate a latch clock for the latch in the first feedback path to be phase offset from each of the first sampling clock and the second sampling clock.3. The integrated circuit of claim 2 , wherein:the ...

DUTY RATIO CORRECTION CIRCUIT, DOUBLE-EDGED DEVICE, AND METHOD OF CORRECTING DUTY RATIO

A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal. 1. A duty ratio correction circuit , comprising:a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal;a phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; anda multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.2. The duty ratio correction circuit according to claim 1 , whereinthe first edge corresponds to a rising edge of the first clock signal, andthe second edge corresponds to a falling edge of the first clock signal.3. The duty ratio correction circuit according to claim 1 , whereinthe phase interpolator generates the fourth clock signal by phase interpolation of the second clock signal and the third ...

SAMPLING CLOCK GENERATOR CIRCUIT, AND IMAGE READER AND ELECTRONIC DEVICE INCORPORATING THE SAME

A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero. 1. A sampling clock generator circuit comprising:a reference clock generator;a sampling hold circuit;a sampling clock generator configured to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit;a phase determining element configured to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator; anda controller configured to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.2. A sampling clock generator according to claim 1 , further comprising:a first delay circuit having a plurality of first delay taps to delay the output clock signal input by a tap selection; anda second delay circuit having a plurality of second delay taps having a delay amount smaller than that of the first delay taps to delay the output clock signal ...

Pulsed Gate Driver

A gate driver includes a control input receiving a control signal, an output to provide an amplified output signal to the gate, and controller. The controller produces an adaptive pulse train varying with the control signal. An adaptive incrementer produces a sequence of numbers that set a slew rate of the switch, and a look-up table is fed with the sequence of numbers, and associates the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal to control the slew rate of the switch. The switch can be driven at various intermediate levels, and allows gate drive conditions to adapted to abnormal system states by varying the control input signal. The adaptive response allows the slew rate to vary without replacing any gate driver circuit components. Because the gate current is provided adaptively, the delivery of gate current results in low power dissipation. 1. A gate driver for driving a gate of a switch , the gate driver comprising:a control input which is adapted to receive a control signal;an output which is adapted to provide an amplified output signal to be fed to the gate of the switch for driving the switch; anda controller comprising an adaptive incrementer and a look-up table,wherein the controller is connected between the control input and the output, and is adapted to produce an adaptive pulse train that varies depending on a characteristic of the control signal,wherein the adaptive incrementer is adapted to produce a sequence of numbers, the values of which allow a slew rate of the switch to be set, andwherein the look-up table is adapted to be fed with the sequence of numbers, and to associate the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal so as to control the slew rate of the switch.2. The gate driver of claim 1 , wherein the controller is adapted to vary the adaptive pulse train according to the characteristic of the control signal so as to ...

SYSTEM AND METHOD OF ADJUSTING A CLOCK SIGNAL

A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal. 1. A method comprising:receiving an input clock signal at a programmable buffer;filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, the voltage level indicating a duty cycle of the output signal;comparing the voltage level to a reference voltage; andmodifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal.2. The method of claim 1 , wherein the programmable buffer is configured to selectively charge and discharge a node based on a digital voltage level of the input clock signal and based on the at least one operating parameter claim 1 , wherein the duty cycle of the output signal is responsive to a charging rate and a discharging rate of the node.3. The method of claim 2 , wherein charging the node includes selectively activating at least one p-type metal oxide semiconductor (PMOS) transistor based on the at least one operating parameter.4. The method of claim 2 , wherein discharging the node includes selectively activating at least one n-type metal oxide semiconductor (NMOS) transistor based on the at least one operating parameter.5. The method of claim 1 , wherein the output signal is an output clock signal.6. The method of claim 1 , wherein the output signal has a duty cycle of fifty percent in response to modifying the at least one operating parameter.7. The method of claim 6 , wherein a duty cycle of the input clock signal is not fifty percent.8. ...

Semiconductor device having duty correction circuit

Disclosed herein is a device includes a duty correction circuit adjusting a duty ratio of a first clock signal based on a duty control signal to generate a second clock signal; a delay line delaying the second clock signal to generate a third clock signal; and a duty cycle detector detecting the duty ratio of the second clock signal to generate the duty control signal in a first mode, and detecting the duty ratio of the third clock signal to generate the duty control signal in a second mode.

ERROR DETECTION AND COMPENSATION FOR A MULTIPLEXING TRANSMITTER

Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error. 1. A system for reducing error associated with a multiplexing transmitter , comprising:an error detector circuit configured to measure a quadrature error for a clock associated with a transmitter to generate first error detector information based on a first clock pattern for a first output generated by the transmitter in response to a defined bit pattern, and generate second error detector information based on a second clock pattern for a second output generated by the transmitter in response to an inverted version of the defined bit pattern, wherein the error detector circuit is further configured to determine a first average value of the first error detector information and a second average value of the second error detector information, determine a differential average value of the first average value and the second average value based on a comparison of the first average value to the second average value, and determine an error detector output based on the differential average value; anda duty cycle correction ...

TIME-TO-VOLTAGE CONVERTER WITH EXTENDED OUTPUT RANGE

A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node. 1. An apparatus comprising:a first voltage reference node;a second voltage reference node; and a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period,', 'wherein the shifted reset voltage level is outside a voltage range of the voltage on the output node defined by a first power supply voltage level on the first voltage reference node and a second power supply voltage level on the second voltage reference node., 'a time-to-voltage converter comprising2. The apparatus claim 1 , as recited in claim 1 , wherein the second voltage reference node is a positive power supply node or a ground node claim 1 , the shifted reset voltage level is less than the second power supply voltage level if the second voltage reference node is a ground node claim 1 , and the shifted reset voltage level is greater than the second power supply voltage level if the second voltage reference node is the positive power supply node.3. The apparatus claim 1 , as recited in claim 1 , wherein the shifted ...

APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a first inverter configured to receive first and second clock signals and further includes a second inverter configured to receive the first and second clock signals. The first inverter is configured to provide to an output node an inverted first clock signal as controlled by the second clock signal. The second inverter is configured to provide to the output node an inverted second clock signal as controlled by the first clock signal. Another example apparatus includes a clock generator circuit to provide first and second clock signals responsive to an input clock signal, and further includes a duty phase interpolator circuit, a duty cycle adjuster and a duty cycle detector.

COMMUNICATING ACROSS GALVANIC ISOLATION, FOR EXAMPLE, IN A POWER CONVERTER

A signal transmission system for communicating across galvanic isolation. The signal transmission system includes first circuitry referenced to a first potential, the first circuitry comprising signal transmission circuitry, second circuitry referenced to a second potential and galvanically isolated from the first circuitry, the second circuitry comprising signal reception circuitry, and a magnetic coupling between the first circuitry to the second circuitry across the galvanic isolation, the magnetic coupling comprising a transmitter-side inductor and a receiver-side inductor. The signal transmission circuitry can include a source coupled to output, to the transmitter-side inductor of the magnetic coupling, a first state representation that represents a first logic state with multiple transitions, the first state representation including at least a first upward transition, a first downward transition, a second upward transition, and a second downward transition. 1. A signal transmission system for communicating across galvanic isolation , the signal transmission system comprising:first circuitry referenced to a first potential, the first circuitry comprising signal transmission circuitry;second circuitry referenced to a second potential and galvanically isolated from the first circuitry, the second circuitry comprising signal reception circuitry; anda magnetic coupling between the first circuitry to the second circuitry across the galvanic isolation, the magnetic coupling comprising a transmitter-side inductor and a receiver-side inductor; a first state representation that represents a first logic state with multiple transitions, the first state representation including at least a first upward transition, a first downward transition, a second upward transition, and a second downward transition, and', 'a second state representation that represents a second logic state with multiple transitions., 'wherein the signal transmission circuitry comprises a source coupled ...

SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING PLURALITY OF CHANNELS

A semiconductor apparatus includes a direct access section, an interface section, and a through-via region. The direct access section receives first and second groups of input signals through a direct access pad, and generates first and second groups of control signals based on the first and second groups of input signals. The interface section comprises a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals. The through-via region electrically couples the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively. 1. A semiconductor apparatus comprising:a direct access section suitable for receiving first and second groups of input signals through a direct access pad, and generating first and second groups of control signals based on the first and second groups of input signals;an interface section comprising a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals; anda through-via region suitable for electrically coupling the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively, and transferring signals from the plurality of channel circuits to the plurality of stack dies respectively corresponding to the plurality of channel circuits.2. The semiconductor apparatus of claim 1 , wherein the direct access section comprises:a receiver suitable for generating the first and second groups of control signals by decoding the first and second groups of input signals; anda channel selection unit suitable for generating the plurality of channel selection signals based on a part of the first and second groups of control signals.3. The semiconductor apparatus of claim 2 , wherein the interface section further comprises:a main buffer unit ...

DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR DEVICE

According to one embodiment, there is provided a duty cycle correction circuit including an input inverter, an output inverter, a charge distribution unit, and a drawing-off unit. The input inverter includes a PMOS transistor and an NMOS transistor and receives a clock signal. The output inverter outputs a clock signal according to a signal transmitted via a signal line from the input inverter. The charge distribution unit distributes, when one transistor of the PMOS transistor and the NMOS transistor is turned on, charge to capacitance elements selected from among one or more first capacitance elements placed on side of the signal line and among a plurality of second capacitance elements disposed on side of source of the one transistor. The drawing-off unit draws off the distributed charge from the selected capacitance elements while the one transistor is maintained to be on. 1. A duty cycle correction circuit comprising:an input inverter that includes a PMOS transistor and an NMOS transistor and receives a clock signal;an output inverter that outputs a clock signal according to a signal transmitted via a signal line from the input inverter;a charge distribution unit that distributes, when one transistor of the PMOS transistor and the NMOS transistor is turned on, charge to capacitance elements selected from among one or more first capacitance elements placed on side of the signal line and among a plurality of second capacitance elements disposed on side of source of the one transistor; anda drawing-off unit that draws off the distributed charge from the selected capacitance elements while the one transistor is maintained to be on.2. The duty cycle correction circuit according to claim 1 , wherein the charge distribution unit has:a plurality of the first capacitance elements disposed on the side of the signal line;a first selecting unit that selects first capacitance elements to be used for duty cycle adjustment from among the plurality of first capacitance ...

CLOCK SIGNAL CONTROLLER

The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals. 1. A clock signal controller , comprising:a first clock combiner comprising a plurality of transistors; anda second clock combiner comprising a plurality of transistors, whereina first clock signal input into the first clock combiner is faster than a second clock signal input into the second clock combiner,a trailing edge of a first single clock signal outputted by the first clock combiner corresponds to a rising edge of the first clock signal, and its rising edge corresponds to the trailing edge of the second clock signal, anda trailing edge of a second single clock signal outputted by the first clock combiner corresponds to the rising edge of the second clock signal, and its rising edge corresponds to the trailing edge of the first clock signal.2. The clock signal controller of claim 1 , wherein the plurality of transistors of the first clock combiner comprises a first transistor claim 1 , a second transistor claim 1 , a third transistor and a fourth transistor.3. The clock signal controller of claim 2 , wherein the first transistor is a P-type transistor claim 2 , a source of the first transistor is connected to a working level claim 2 , a drain of the first transistor is connected to a first connecting point claim 2 , and a gate of the first transistor is connected to a first clock signal input end.4. The clock signal controller of claim 3 , wherein the second transistor is an N-type transistor claim 3 , a source of the second transistor is connected to the first connecting point claim 3 , a drain of the second transistor is connected to a reference level claim 3 , and a gate of the second transistor is connected to the first clock signal input end.5. The clock signal controller of claim 4 ...

CLOCK RECOVERY DEVICE AND SOURCE DRIVER FOR RECOVERING EMBEDDED CLOCK FROM INTERFACE SIGNAL

In generating a mask signal to be used when a clock signal embedded in an interface signal is recovered, the mask signal may be generated by compensating for a processing delay time occurring in a mask signal generation circuit, thereby reducing the inaccuracy of the mask signal due to the processing delay time. 1. A clock recovery device comprising:a mask signal generation unit configured to generate a mask signal in accordance with a first mask reference signal;a mask duplication signal generation unit configured to generate a mask duplication signal in accordance with a second mask reference signal;a clock extraction unit configured to extract an extraction clock from an interface signal with a clock signal embedded therein in a time interval indicated by the mask signal;a first time-delay control unit configured to generate a compensation clock by time-delaying the extraction clock so that a phase difference between the extraction clock and the mask duplication signal becomes smaller; anda second time-delay control unit configured to generate the first mask reference signal, and the second mask reference signal by time-delaying the compensation clock, and to generate the first mask reference signal and the second mask reference signal so that a phase of the first mask reference signal is ahead of a phase of the second mask reference signal.2. The clock recovery device of claim 1 , whereinthe mask signal generation unit generates a rising edge of the mask signal in accordance with the first mask reference signal through a first internal circuit,the mask duplication signal generation unit generates a rising edge of the mask duplication signal in accordance with the second mask reference signal through a second internal circuit, anda processing delay time of the first internal circuit and a processing delay time of the second internal circuit are substantially same.3. The clock recovery device of claim 1 , wherein one period of the interface signal is divided into ...

COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME

A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result. 115-. (canceled)16. A duty correction circuit of a semiconductor device , comprising:a duty cycle error detection unit configured to detect a duty cycle error of a source clock;a plurality of counting units configured to count respective bits of duty correction codes in response to a plurality of counting clocks, respectively, and a counting direction of the plurality of counting units is controlled in response to an output signal of the duty cycle error detection unit;a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; anda duty cycle control unit configured to control a duty cycle of the source clock in response to the duty correction codes.17. The duty correction circuit of claim 16 , wherein the plurality of counting units respectively count the plurality of bits included in the duty correction codes in one-to-one correspondence to toggling of the plurality of counting clocks.18. The duty correction circuit of claim 17 , wherein the plurality of counting units respectively perform counting operations by combining carry information between adjoining units.19. The duty correction circuit of claim 16 ,wherein the clock toggling control unit determines the number of counting clocks to toggle in an ...

POWER CONVERTER WITH PHASE ERROR CORRECTION

A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. The power converter circuit may generate a reference clock signal using a system clock signal and a voltage level of the switch node. The reference clock signal may be used to initiate a charge cycle, whose duration may be based on generated ramp signals. 1. An apparatus , comprising:a voltage regulator circuit that includes a switch node coupled to a regulated power supply node via an inductor, wherein the voltage regulator circuit is configured to source a charge current to the switch node during a charge cycle; and determine a phase difference between a system clock signal and a voltage level of the switch node;', 'generate a reference clock signal using the phase difference;', 'generate a plurality of ramp signals using the voltage level of the switch node;', 'initiate the charge cycle using the reference clock signal; and', 'halt the charge cycle using the plurality of ramp signals., 'a control circuit configured to2. (canceled)3. The apparatus of claim 1 , wherein to generate the reference clock signal claim 1 , the control circuit is further configured claim 1 , based on the phase difference claim 1 , to selectively charge or discharge a capacitor.4. The apparatus of claim 3 , wherein the control circuit is further configured to generate a control current using a voltage level across the capacitor.5. The apparatus of claim 4 , wherein the control circuit is further configured to delay the system clock signal to generate the reference clock signal.6. The apparatus of claim 1 , wherein the control circuit is further configured to halt the charge cycle using a result of a comparison of a voltage level of the switch node and a reference voltage level.7. A method claim 1 , comprising:receiving, by a power converter circuit, a system clock signal, wherein the power converter circuit includes a switch node coupled ...

SEMICONDUCTOR APPARATUS RELATED TO RECEIVING CLOCK SIGNALS HAVING VARIABLE FREQUENCIES, AND SYSTEM INCLUDING THE SEMICONDUCTOR APPARATUS

A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus. 1. A system comprising:an external apparatus configured to provide a first clock signal and a second clock signal; anda semiconductor apparatus configured to communicate with the external apparatus by receiving the first clock signal and the second clock signal,wherein the first clock signal has a first frequency and a second frequency higher than the first frequency, and the second clock signal has a third frequency lower than the first frequency.2. The system of claim 1 , wherein the second frequency is double the first frequency and the first frequency is double the third frequency.3. The system of claim 1 , wherein the first clock signal is transferred from the external apparatus to the semiconductor apparatus when a synchronized signal is transferred between the external apparatus and the semiconductor apparatus claim 1 , and the synchronized signal is transferred in synchronization with the first clock signal.4. The system of claim 1 , wherein the external apparatus provides the first clock signal including at least one pulse having the first frequency and a pulse having the second frequency.5. The system of claim 1 , wherein the semiconductor apparatus includes:a frequency divider configured to generate at least one internal clock signal by dividing a frequency of the first clock signal; anda phase detector configured to generate a phase detection signal by comparing phases between the at least one internal clock signal and the second clock signal.6. The system of claim 5 , wherein the phase detection signal is feedback to the external apparatus claim 5 , and the external apparatus changes a phase of the first clock signal based on the phase detection signal.7. The system of claim 5 , wherein the semiconductor ...

DELAY CELL, DELAY LOCKED LOOK CIRCUIT, AND PHASE LOCKED LOOP CIRCUIT

A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell. 1. A delay cell comprising:a first transistor having a first terminal connected to a power supply voltage terminal, a second terminal connected to an output terminal, and a gate terminal connected to an input terminal; anda second transistor having a first terminal connected to a ground terminal, a second terminal connected to the output terminal, and a gate terminal connected to the input terminal,wherein each of the first and second transistors has a fully depleted silicon-on-insulator (FD-SOI) structure, and at least one of a first control voltage is applied to a body of the first transistor and a second control voltage is applied to a body of the second transistors to adjust a delay time of the delay cell.2. The delay cell of claim 1 , wherein the first transistor is a P-type Metal Oxide Semiconductor (PMOS) transistor and the second transistor is an N-type MOS (NMOS) transistor.3. The delay cell of claim 1 , wherein each of the first transistor and second transistor comprises:a body layer;a buried insulation layer on the body layer;a pair of impurity regions disposed on the buried insulation layer to function as source/drain regions;a semiconductor layer disposed between the pair of impurity regions in contact with the buried insulation layer;a gate insulation layer on a top surface of the semiconductor layer opposite to the buried insulation layer; anda gate electrode on the gate insulation layer.4. The delay cell of claim 3 , wherein the body layer of the first transistor is N-type and the pair of impurity regions of the first transistor are P-type claim 3 , ...

PHASE INTERPOLATOR

Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction. 118-. (canceled)19. A method for designing a low power phase interpolator that exhibits high power supply rejection , the method comprising: identifying a positive in-phase current source having a positive in-phase input that is operatively coupled to a positive in-phase control module that receives power from a positive power supply terminal, and produces a positive in-phase output;', 'identifying a positive quadrature phase current source having a positive quadrature phase input that is operatively coupled to a positive quadrature phase control module that receives power from the positive power supply terminal, and produces a positive quadrature phase output;', 'identifying a negative in-phase current source having a negative in-phase input that is operatively coupled to a negative in-phase control module that receives power from a negative power supply terminal, and produces a negative in-phase output;', ' ...

BALANCING DELAY ASSOCIATED WITH DUAL-EDGE TRIGGER CLOCK GATERS

Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode. 1. An apparatus , comprising:a first series of dual-edge triggered (DET) clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry, wherein ones of the DET clock gater circuits are controlled by respective control signals and wherein ones of the DET clock gater circuits are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock; anda first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.2. The apparatus of claim 1 , wherein ones of the DET clock gaters are configured to switch between inverting and non-inverting modes based on whether prior clock gating lasted an even or odd number of clock edges.3. The apparatus of claim 1 , wherein the first adjustable delay circuit includes an inverter and wherein the ...

DEMUX CONTROL CIRCUIT

The present application provides a demux control circuit. The demux control circuit includes a driving chip, a logic circuit, and a demux for providing two or three pulse signals to the logic circuit, the logic circuit including a plurality of NOR Gate and a plurality of buffers which can convert two pulse signals into three control signals or convert the three pulse signals into four control signals through the cooperation of the NOR gates and the buffers to achieve outputting a larger number of control signals by a smaller number of pins, thereby reducing the number of pins outputted from the driving chip and reduce production costs. 1. A demux control circuit , comprising:a driving chip; a logic circuit electrically connected to the driving chip, and a demux electrically connected to the logic circuit;the driving chip for providing a first pulse signal and a second pulse signal to the logic circuit;the logic circuit comprising a first two-input NOR gate, a second two-input NOR gate, a third two-input NOR gate, a first in-phase buffer, a second in-phase buffer, and a third in-phase buffer;a first input terminal and a second input terminal of the first two-input NOR gate respectively accessing the first pulse signal and the second pulse signal, an output terminal electrically connected to an input terminal of the first in-phase buffer; a first input terminal of the second two-input NOR gate accessing the first pulse signal; a second input terminal electrically connected to the output terminal of the first two-input NOR gate, an output terminal electrically connected to an input terminal of the second in-phase buffer; a first input terminal of the third two-input NOR gate accessing the second pulse signal, a second input terminal electrically connected to the output terminal of the first two-input NOR gate, an output terminal electrically connected to an input terminal of the third in-phase buffer; andoutput terminals of the first in-phase buffer, the second in- ...

TIMER, ELECTRONIC APPARATUS, AND VEHICLE

A timer includes a timing counter configured to generate a timing datum, a clock pulse signal generation circuit configured to generate a clock pulse signal used to operate the timing counter, and an interface circuit configured to receive an access signal, wherein the timing counter is an asynchronous counter, and the clock pulse signal generation circuit generates the clock pulse signal having a first pulse width when there is a possibility that the interface circuit receives the access signal, and generates the clock pulse signal having a second pulse width longer than the first pulse width when there is no possibility that the interface circuit receives the access signal. 1. A timer comprising:a timing counter configured to generate a timing datum;a clock pulse signal generation circuit configured to generate a clock pulse signal used to operate the timing counter; andan interface circuit configured to receive an access signal, whereinthe timing counter is an asynchronous counter, and generates the clock pulse signal having a first pulse width when there is a possibility that the interface circuit receives the access signal, and', 'generates the clock pulse signal having a second pulse width longer than the first pulse width when there is no possibility that the interface circuit receives the access signal., 'the clock pulse signal generation circuit'}2. The timer according to claim 1 , whereinthe first pulse width is shorter than a cycle time of the access signal.3. The timer according to claim 1 , whereinthe second pulse width is a length obtained by multiplying a period of a source clock signal by 2 to N-th power, N representing a natural number.4. The timer according to claim 1 , whereinthe clock pulse signal generation circuit determines whether or not there is a possibility that the interface circuit receives the access signal based on a first power supply voltage supplied to the timer.5. The timer according to claim 4 , further comprising:a power supply ...

CONTROL DEVICE, DELAY DIFFERENCE ADJUSTMENT METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR STORING DELAY DIFFERENCE ADJUSTMENT PROGRAM

A control device causes a first transmission system in a MIMO transmission device to transmit a first transmitting-end clock transmission signal (first transmission signal), causes a second transmission system to transmit a second transmission signal, and causes the first transmission system to transmit a third transmission signal. The control device acquires a first phase value and a second phase value. The first phase value is a phase value of the second transmission signal received in the second reception system operating based on a receiving-end clock signal synchronous with a transmitting-end clock signal by the first transmission signal. The second phase value is a phase value of the third transmission signal received in the second reception system in synchronous operation. The control device calculates a first correction value for correcting a first delay amount set value of a delay adjustment processing unit based on the first and second phase values 1. A control device for adjusting a difference in delay between a first transmission system and a second transmission system in a MIMO (multiple-input and multiple-output) transmission device including the first transmission system and the second transmission system operating based on a transmitting-end clock signal and being capable of MIMO communication with a MIMO reception device including a first reception system and a second reception system operating based on a receiving-end clock signal , the control device comprising:hardware including a processor and a memory; anda control unit for implemented at least by the hardware and thatcauses a first transmission radio processing unit in the first transmission system to transmit a first transmitting-end clock transmission signal,causes a second transmission radio processing unit in the second transmission system to transmit a second transmitting-end clock transmission signal,causes the first transmission radio processing mean to transmit a third transmitting-end ...

Delay-locked Loop Arrangement and Method for Operating a Delay-locked Loop Circuit

Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit is configured to generate an error signal depending on a comparison of the reference clock signal and a feedback signal. Furthermore, the delay-locked loop circuit generates the feedback signal depending on the error signal and on the main clock signal. 1. A delay-locked loop arrangement comprising: a first frequency during a performance mode of operation; and', 'a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation; and, 'a steering unit configured to generate a reference clock signal and a main clock signal, wherein the reference clock signal and the main clock signal feature generate an error signal depending on a comparison of the reference clock signal and a feedback signal; and', 'generate the feedback signal depending on the error signal and on the main clock signal., 'a delay-locked loop circuit configured to2. The delay-locked loop arrangement according to claim 1 , wherein the phase delay is determined by a processing time of the delay-locked loop circuit.3. The delay-locked loop arrangement according to claim 1 , wherein during the sleep mode the reference clock signal is delayed with respect to the main clock signal by a clock period of the first frequency.4. The delay-locked loop arrangement according to claim 1 , wherein the steering unit is configured to initiate the sleep mode and the performance mode claim 1 , respectively claim 1 , depending on ...

METHOD FOR OPERATING A PULSE GENERATOR FOR CAPACITIVE SENSORS, AND PULSE GENERATOR

The disclosure relates to a method for operating a pulse generator for generating measuring pulses for a capacitive sensor having an adjustable pulse time in the range from 10 ns to 200 ns, having a controllable delay circuit which contains a first integrating RC combination (RTCT) and a second integrating RC combination (RTCT), having a logical combining element having two inputs and one output, an initialization circuit and a control unit, wherein the first input of the logical combining element receives a clock signal, and the second input of the logical combining element receives an analog setting signal (SSE) from the output of the delay circuit, wherein two simultaneous clock signals are generated, of which the first clock signal (T) is led without delay to the first input of the logical combining element, and the second clock signal (T), delayed by the delay circuit, is led to the second input of the logical combining element, time-variable output pulses are generated with the aid of time-variable preloading signals (VL), wherein the output from the delay circuit after each measuring pulse is discharged or charged by the initialization switch. 1. A method for operating a pulse generator for generating measuring pulses for a capacitive sensor with an adjustable pulse duration in the range from 10 ns to 200 ns , comprising:{'b': 1', '1', '2', '2, 'a controllable delay circuit which includes a first integrating RC combination RT/CT and a second integrating RC combination RC/CT, a logic gate with two inputs and one output, an initialization switch and a control unit, wherein the first input of the logic gate receives a clock signal and its second input receives an analog adjusting signal SSE from the output of delay circuit,'}{'b': 1', '2, 'wherein two simultaneous clock signals are generated, of which the first clock signal T is supplied without delay to the first input of the logic gate and the second clock signal T is delayed by the delay circuit and supplied ...

PWM SIGNAL GENERATOR CIRCUIT AND RELATED INTEGRATED CIRCUIT

A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration. 1. A Pulse-Width Modulated (PWM) signal generator circuit , comprising:{'claim-text': ['generate a PWM signal having a given switching duration including a switch-on duration and a switch-off duration,', 'determine for each switch-on duration a number of clock periods of the switch-on duration and a number of the fractions of the clock period of the switch-on duration, and'], '#text': 'a multiphase clock generator configured to generate phase-shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction of the clock period, the PWM signal generator circuit configured to:'}determine for each switch-off duration a number of clock periods of the switch-off duration, and a number of the fractions of the clock period of the switch-off duration.2. The PWM signal generator circuit of claim 1 , further comprising:a clock switching circuit configured to generate a timer clock signal by selecting one of the phase shifted clock phases as the timer clock signal based on a selection signal.3. The PWM signal generator circuit according ...

INTEGRATED CIRCUIT DEVICE, PHYSICAL QUANTITY MEASURING DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

An integrated circuit device includes a terminal region in which a second signal terminal to which a second signal is input is disposed, an AFE circuit (analog front-end circuit) that performs waveform shaping of the second signal, and a time-to-digital converter that converts a time difference between a transition timing of a first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value. When a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction, the AFE circuit is disposed on the first direction side of the terminal region, and the time-to-digital converter is disposed on at least one side of the first direction side of the AFE circuit and a side of a direction intersecting the first direction. 1. An integrated circuit device that performs signal processing based on a first signal and a second signal , the device comprising:a terminal region in which a second signal terminal to which the second signal is input is disposed;an analog front-end circuit that performs waveform shaping of the second signal; anda time-to-digital converter that converts a time difference between a transition timing of the first signal and a transition timing of the second signal subjected to waveform shaping, to a digital value,wherein, when a direction from a first side of the integrated circuit device toward a second side facing the first side is set as a first direction,the analog front-end circuit is disposed on the first direction side of the terminal region, andthe time-to-digital converter is disposed on at least one side of the first direction side of the analog front-end circuit and a side of a direction intersecting the first direction.2. The integrated circuit device according to claim 1 , further comprising:a first clock signal generation circuit that includes a first oscillation circuit and outputs a first clock signal generated by the first ...

APPARATUSES AND METHODS FOR PROVIDING A SIGNAL WITH A DIFFERENTIAL PHASE MIXER

According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal. The apparatus further comprises a second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal, wherein the second intermediate signal is combined with the first intermediate signal at a node to provide an output signal. 1. An apparatus comprising:first and second phase mixer circuits including corresponding first inverters, corresponding second inverters, corresponding third inverters, and corresponding fourth inverters,the corresponding first inverters of the first and second phase mixer circuits configured to receive, respectively, a first input signal and a complimentary first input signal, each of the corresponding first inverters of the first and second phase mixer circuits configured to be controlled by a first control signal received, via the corresponding second inverter, at a non-inverting control input of the corresponding first inverter, each of the corresponding first inverters of the first and second phase mixer circuits further configured to be controlled by the first control signal received at an inverting control input of the corresponding first inverter,the corresponding third inverters of the first and second phase mixer circuits configured to receive, respectively, a second input signal and a complimentary second input signal, each of the corresponding third inverters of the first and second phase mixer circuits configured to be controlled by a second control signal received, via the corresponding fourth inverter, at an inverting control input of ...

SEMICONDUCTOR MEMORY APPARATUS

A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals. 1. A semiconductor memory apparatus comprising:an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; anda plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals.2. The semiconductor memory apparatus according to claim 1 , wherein the enable signal generation unit comprises delay sections configured to respectively delay the plurality of clocks and respectively output the plurality of enable signals.3. The semiconductor memory apparatus according to claim 2 , wherein each of the delay sections are configured to be inputted with a pair of clocks from among the plurality of clocks claim 2 , and delay at least one of the inputted pair of clocks claim 2 , and output an enable signal with an enable period that overlaps with a period in which the pair of clocks are a specified level.4. The semiconductor memory apparatus according to claim 1 ,wherein the enable signal generation unit comprises signal combining sections configured to respectively generate the plurality of enable signals, andwherein each of the signal combining sections are configured to be input with a pair of clocks from among the plurality of clocks, and generate a corresponding enable signal having an enable period that overlaps with a period in which both of the pair of clocks are a specified level.5. The semiconductor memory apparatus according to claim 4 ...

PULSE WIDTH MODULATION CONTROL CIRCUIT AND CONTROL METHOD OF PULSE WIDTH MODULATION SIGNAL

A pulse width modulation control circuit and a control method of a pulse width modulation signal are provided. A counter circuit generates a count value according to a phase-locked loop clock, and resets the count value according to a transition point of a synchronization signal. A comparison circuit compares the count value with a duty ratio set value, and sets the pulse width modulation signal to a high level while the count value is less than the duty ratio set value. 1. A pulse width modulation control circuit , comprising:a phase-locked loop clock generating circuit, generating a phase-locked loop clock according to a display synchronization signal;a counter circuit, coupled to the phase-locked loop clock generating circuit and generating a count value according to the phase-locked loop clock, wherein the counter circuit is not coupled to an edge detector, and the counter circuit automatically resets the count value by presetting a reset period of the counter circuit equal to a signal cycle of the display synchronization signal, wherein the reset period of the counter circuit meets a form of 2{circumflex over ( )}N, and N=3; anda comparison circuit, coupled to the counter circuit and generating a pulse width modulation signal to control a display period of a display frame by comparing a difference between the count value associated with the display synchronization signal and a duty ratio set value associated with the display period of the display frame,wherein the comparison circuit determines whether the count value associated with the display synchronization signal is less than the duty ratio set value associated with the display period of the display frame,wherein the comparison circuit sets the pulse width modulation signal to a high level while the count value associated with the display synchronization signal is less than the duty ratio set value associated with the display period of the display frame.2. (canceled)3. (canceled)4. The pulse width ...

APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input dock signal. A duty phase interpolator circuit may be coupled to the dock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected dock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error. 1. An apparatus comprising:a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal;a duty phase interpolator circuit coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals, the first and second duty cycle corrected interpolated clock signals approximately 180 degrees out of phase relative to one another;a duty cycle adjuster circuit coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected dock signal responsive thereto, and further configured to adjust a duty cycle responsive to adjustment signals; anda duty cycle detector coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to the duty cycle adjuster circuit to adjust the duty cycle to correct the duty cycle error.2. The apparatus of wherein the duty phase ...

METHOD AND APPARATUS FOR CLOCK SKEW CONTROL WITH LOW JITTER IN AN INTEGRATED CIRCUIT

An apparatus of performing a clock skew adjustment between N clock signals. 2(N−1) skew sensors are configured as successive pairs k, each pair k having a first skew sensor and a second skew sensor. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. A skew controller performs the clock skew adjustment based on the first and second information. 1. An apparatus of performing a clock skew adjustment between N clock signals , wherein N≥3 comprising:2(N−1) skew sensors configured as successive pairs k, each pair k having two skew sensors, where k=1, 2, 3, . . . each successive pair k comprising a first skew sensor and a second skew sensor, wherein a first skew sensor of each pair k of two skew sensors is configured to receive:a third clock signal obtained by delaying a first clock signal of said N clock signals by a first delay and a fourth clock signal obtained by delaying a second clock signal of said N clock signals by a second delay, and to generate first information based on the third and fourth clock signals, the first information varying depending on a clock skew between the first and second clock signals; andwherein a second skew sensor of each pair k is configured to receive:a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and to generate second information based on the fifth and sixth clock signals, the second information varying depending on ...

HIGH-SPEED PHASE INTERPOLATOR

The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. In a specific embodiment, the present invention provides a phase interpolator device that mixes phase-shifted clock signals according to a predetermined weight values at predetermined time intervals. There are other embodiments as well. 1. A phase interpolator device comprising:a clock buffer for receiving input clock signals and providing buffered clock signals, the input clock signals including a first clock signal and a second clock signal, the first clock signal and the second clock signal being separated by a predetermined phase, the buffered clock signals including a first buffered clock signal and a second buffered clock signal,a digital-analog-converter (DAC) module comprising DAC blocks and being configured to generate an intermediate clock signal, the DAC blocks including a first DAC block and a second DAC block, the first DAC block being configured to process the first buffered clock signal and contribute to the intermediate clock signal at a first time interval at a first predetermined weight, the second DAC block being configured to process the second buffered clock signal and contribute to the intermediate clock signal at a second time interval at a second predetermined weight, the first time interval partially overlapping the second time interval; anda clock generator configured to generate an output clock signal using at least the intermediate clock signal;wherein the first DAC block is configured to operate in a mixing mode until a predetermined trip point is reached.2. The device of wherein:the buffered clock signals further comprising a third buffered clock signal and a fourth buffered clock signal;the DAC module further comprising a third DAC block and a fourth DAC block, the third DAC block ...

CLOCK CIRCUIT HAVING A PULSE WIDTH ADJUSTMENT MODULE

A clock circuit has a clock input terminal, a first clock output terminal, and a second clock output terminal. The clock circuit includes a pulse width adjustment module, a sampling module, a comparing module, and a differential signal converting module. A differential input terminal is electrically connected to a pulse width output terminal of the pulse width adjustment module. A positive differential signal output terminal and a negative differential signal output terminal are electrically connected to the first clock output terminal of the clock circuit and the second clock output terminal to output two clock signals with a phase difference of 180 degrees, respectively. A second input terminal of the sampling module is electrically connected to the second clock output terminal. 1. A clock circuit having a clock input terminal and a clock output terminal , wherein the clock input terminal receives an input clock signal , and the clock output terminal outputs an output clock signal , the clock circuit comprising:a pulse width adjustment module including a pulse width input terminal, a control terminal, a power terminal, a ground terminal, and a pulse width output terminal, the pulse width input terminal electrically connected to the clock input terminal to receive the input clock signal, the power terminal electrically connected to a first reference voltage, and the ground terminal electrically connected to a ground voltage;a sampling module including a first input terminal, a second input terminal, and a first output terminal, the first input terminal of the sampling module electrically connected to the clock output terminal of the clock circuit, the sampling module used for sampling an output voltage of the clock output terminal of the clock circuit to generate a first sampling voltage, and the first output terminal used to output the first sampling voltage;a comparing module including a first comparing input, a second comparing input terminal, and a comparing ...

Non-Integer Frequency Divider

A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value. 1. An apparatus , comprising:a first divider configured to divide a frequency of a first signal;a mixer having a first input configured to receive the first signal and a second input coupled to receive a second signal, wherein a frequency of the second signal is equivalent to a signal output by the first divider, wherein the mixer is configured to output a third signal having a frequency based on signals received at its first and second inputs;a filter configured to attenuate sideband components of the third signal; anda second divider configured to divide a frequency of the third signal to produce a fourth signal, wherein a ratio of the frequency of the first signal to a ratio of the fourth signal is a non-integer value.2. The apparatus as recited in claim 1 , wherein the first divider is configured to divide the frequency of the first signal by an odd integer value.3. The apparatus as recited in claim 1 , wherein the second divider is configured to divide the frequency of the third signal by an even integer value.4. The apparatus as recited in claim 1 , wherein the first divider is configured to divide the frequency of the first signal by an odd integer value N claim 1 , wherein the second divider is configured to divide the frequency of the third signal by a value of (N−1)/2 claim 1 , and wherein a ratio of the frequency of the first signal to the frequency of the fourth ...

Complementary Output Generator Module

A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications. 1. A complementary output generator module for a microcontroller , wherein the complimentary output generator is configurable through a processing core of the microcontroller and comprises:a clock input coupled to a clock source;a plurality of rising event inputs that are programmably selectable, wherein at least one of the selected rising event inputs initiates a rising event signal synchronous with the clock source when at least one rising event occurs at a respective selected one of the rising event inputs;a plurality of falling event inputs that are programmably selectable, wherein at least one of the selected falling event inputs initiates a falling event signal synchronous with the clock source when at least one falling event occurs at a respective selected one of the falling event inputs; and a first one of the plurality of outputs asserts a first output drive signal upon detection of the rising event signal until detection of the falling event signal, and', 'a second one of the plurality of outputs asserts a second output drive signal upon detection of the falling event signal until detection of a next rising event signal., 'a plurality of outputs, wherein'}2. The complementary output generator module according to claim 1 , ...

COMPENSATION TIME COMPUTING METHOD and DEVICE FOR CLOCK DIFFERENCE

The present invention provides a method for computing compensation time for clock difference between a first chip and a second chip. The method comprises emitting, by the second chip, a pulse with a fixed pulse length to the first chip; measuring, by the first chip, a pulse length of the pulse; computing the compensation time according to the measure pulse length and the fixed pulse length; and setting the compensation time to the second chip.

DIGITAL CURRENT SENSING IN POWER CONTROLLER

Some embodiments include apparatus and methods having a node to provide a signal, and a control unit arranged to control a value of an output voltage at an output node on an output path based on a duty cycle of the signal and a value of an input voltage. The control unit can also be arranged to cause a change in a resistance on the output path in order to determine a value of a current on the output path based at least on the change in the resistance. 1. An apparatus comprising:a node to provide a signal; anda control unit to determine a value of a current on an output p based at least on a duty cycle of the signal and a value of an input voltage.2. The apparatus of claim 1 , wherein the control unit is to cause a change in a resistance on the output path in order to cause a change in the duty cycle of the signal.3. The apparatus of claim 1 , wherein the control unit includes a current calculator to calculate the value of the current based on the value of the input voltage claim 1 , a value of a change in the duty cycle of the signal claim 1 , and a value of the change in the resistance.4. The apparatus of claim 3 , wherein the control unit is included in an integrated circuit die claim 3 , and the current calculator is to obtain the value of the change in the resistance from a memory included in the integrated circuit die.5. The apparatus of claim 2 , wherein the control unit is to cause the change in the resistance during a time interval of an operation of the apparatus claim 2 , and the control unit includes a generator to generate the signal such that the time interval occurs during multiple cycles of the signal.6. The apparatus of claim 2 , wherein the control unit is to cause the change in the resistance during a time interval of an operation of the apparatus claim 2 , and the control unit is to switch a transistor on the output path from a first state to a second state during the time interval in order to cause the change in the resistance.7. The apparatus of ...

INTEGRATED CIRCUIT

An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode. 1. An integrated circuit comprising:a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions;a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal; anda position controller SU table for varying the first and second target positions according to an operation mode.2. The integrated circuit of claim 1 , wherein the phase detector comprises:an alignment unit suitable for aligning data in response to the first and second clock signals;a first decoding unit suitable for generating a first control signal by decoding the data aligned by the alignment unit;a second decoding unit suitable for generating a second control signal by decoding the data aligned by the alignment unit; anda multiplexing unit suitable for outputting the first or second control signal as the delay control signal according to the operation mode.3. The integrated circuit of claim 1 , wherein the operation ode comprises a first and second operation modes claim 1 ,during the first operation mode, the first target position corresponds to the center of the data and the second target position corresponds to an edge of the data, andduring the second operation mode, the first target position corresponds to the edge of the data and the second target position corresponds to the center of the data.4. The integrated ...

PHASE INTERPOLATOR

Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction. 1. A system on a chip device comprisinga clock data recovery circuit device comprising a phase interpolation device, the phase interpolation device comprising:a positive power supply terminal;a negative power supply terminal; anda first interpolation core comprising:a positive in-phase cascode current source having a positive in-phase input coupled to the positive power supply terminal through a programmable positive in-phase control, and having a positive in-phase output coupled to a first common node;a positive quadrature phase cascode current source having a positive quadrature phase input coupled to the positive power supply terminal through a programmable positive quadrature phase control, and having a positive quadrature phase output coupled to the first common node;a negative in-phase cascode current source having a negative in-phase input coupled to the negative power supply terminal through a ...

METHOD AND APPARATUS FOR CLOCK SKEW CONTROL WITH LOW JITTER IN AN INTEGRATED CIRCUIT

An apparatus of performing a clock skew adjustment between at least first and second clock signals includes first and second skew sensors and a skew controller. The first skew sensor receives a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and generates first information based on the third and fourth clock signals. The second skew sensor receives a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and generates second information based on the fifth and sixth clock signals. Each of the first and second information varies depending on the clock skew. The skew controller performs the clock skew adjustment based on the first and second information. 1. An apparatus of performing a clock skew adjustment between at least first and second clock signals , comprising:a first skew sensor configured to receive a third clock signal obtained by delaying the first clock signal by a first delay and a fourth clock signal obtained by delaying the second clock signal by a second delay, and to generate first information based on the third and fourth clock signals, the first information varying depending on a clock skew between the first and second clock signals;a second skew sensor configured to receive a fifth clock signal obtained by delaying the first clock signal by a third delay and a sixth clock signal obtained by delaying the second clock signal by a fourth delay, and to generate second information based on the fifth and sixth clock signals, the second information varying depending on the clock skew between the first and second clock signals; anda clock skew controller configured to perform the clock skew adjustment based on the first and second information.2. The apparatus of claim 1 , further comprising:a first delay unit configured to ...

CLOCK-DISTRIBUTION DEVICE OF IC AND METHOD FOR ARRANGING CLOCK-DISTRIBUTION DEVICE

A method for arranging a clock-distribution device of an IC is provided. An initial placement of the IC is obtained. The initial placement includes a first portion corresponding to a clock-distribution device, a second portion corresponding to a plurality of modules, and a third portion corresponding to a clock-generation device. The clock-distribution device distributes a plurality of first clock signals to the modules according to a second clock signal from the clock-generation device. The first portion is selected from the initial placement. Clocks within the selected first portion are distributed to obtain a fourth portion of the clock-distribution device. The fourth portion is placed in the initial placement to replace the first portion and to obtain a final placement of the IC. Each module has an input port corresponding to the individual first clock signal, and the clock-generation device has an output port corresponding to the second clock signal. 1. A method for arranging a clock-distribution device of an integrated circuit (IC) , comprising:obtaining an initial placement of the IC, wherein the initial placement comprises a first portion corresponding to a clock-distribution device, a second portion corresponding to a plurality of modules, and a third portion corresponding to a clock-generation device, wherein the clock-distribution device is configured to distribute a plurality of first clock signals to the modules according to a second clock signal from the clock-generation device;selecting the first portion from the initial placement;distributing clocks within the selected first portion to obtain a fourth portion of the clock-distribution device; andplacing the fourth portion in the initial placement to replace the first portion and to obtain a final placement of the IC,wherein each of the modules has an input port corresponding to the individual first clock signal, and the clock-generation device has an output port corresponding to the second clock ...

SEMICONDUCTOR DEVICE

According to one embodiment, there is provided a semiconductor device including an input terminal, an output terminal, an oscillation circuit, an adjuster circuit, a driver circuit, and a detector circuit. The input terminal receives a first clock. The oscillation circuit generates an internal clock. The adjuster circuit corrects a duty ratio of a clock. The driver circuit receives the clock from the adjuster circuit and supplies a third clock to the output terminal. The detector circuit detects that a duty ratio of a clock according to the third clock deviates from a duty ratio of a second clock according to the internal clock. The adjuster circuit adjusts a correction amount in tune with the second clock, and corrects a duty ratio of the first clock with the adjusted correction amount according to a detection result of the detector circuit. 1. A semiconductor device comprising:an input terminal which receives a first clock;an output terminal;an oscillation circuit which generates an internal clock;an adjuster circuit which corrects a duty ratio of a clock;a driver circuit which receives the clock from the adjuster circuit and supplies a third clock to the output terminal; anda detector circuit which detects that a duty ratio of a clock according to the third clock deviates from a duty ratio of a second clock according to the internal clock,the adjuster circuit adjusting a correction amount in tune with the second clock, and correcting a duty ratio of the first clock with the adjusted correction amount according to a detection result of the detector circuit.2. The semiconductor device according to claim 1 , further comprising:a selection circuit connected between the input terminal and the adjuster circuit.3. The semiconductor device according to claim 2 , whereinthe selection circuit includes a first input node connected to the input terminal, a second input node which receives the second clock, and an output node connected to the adjuster circuit.4. The ...

CLOCK SWITCHING CIRCUIT AND METHOD

Circuits and methods for switching between an internal clock and an external clock without causing an interruption or an artifact in the switched clock signal are disclosed. To achieve this, the internal clock signal is synchronized with the external clock signal prior to switching. The synchronization may be accomplished using two possible clock-synchronization methods: a first method that passively waits for the clocks to synchronize over time and a second that adjusts a period of the internal clock signal to actively synchronize the clocks. The method selected for use requires the fewest clock cycles to reach synchronization, which is determined by a frequency difference between the two clock frequencies. After clock-synchronization, the output clock signal spectrum will be substantially the same before and after switching between the clock signals, and therefore is suitable for use with spread spectrum clocks. 1. A clock switch , comprising:a phase shift module configured to receive an internal clock signal from an internal clock coupled to the clock switch, the phase shift module configured to reduce a frequency of the internal clock signal by a controllable divisor to generate an adjusted internal clock signal;a clock-sync controller configured to receive an external clock signal from an external clock coupled to the clock switch, the external clock signal at a frequency different from the adjusted internal clock signal, the clock-sync controller configured to control the controllable divisor of the phase shift module, according to a first method or a second method, in order to synchronize the adjusted internal clock signal with the external clock signal in a time that is shortest by the first method or the second method, the clock-sync controller including a frequency measure module configured to measure a frequency difference between the internal clock and the external clock signal; anda multiplexer configured to switch an output of the clock switch between ...

EYE PATTERN MEASUREMENT APPARATUS, AND CLOCK AND DATA RECOVERY SYSTEM AND METHOD OF THE SAME

An eye pattern measurement apparatus includes: an eye pattern monitoring device, performing first sampling on a data signal by sequentially using scan clock signals having different phases to obtain a plurality of scan data signals; and a data aligning device, connected to the eye pattern monitoring device, receiving the scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal, synchronizing the scan data signals with the synchronization clock signal, and outputting the synchronized scan data signals. 1. An eye pattern measurement apparatus , comprising:an eye pattern monitoring device, performing first sampling on a data signal by sequentially using a plurality of scan clock signals having difference phases to obtain a plurality of scan data signals, wherein a period of the plurality of scan clock signals is equal to a period of a first clock signal synchronous with the data signal; anda data aligning device, connected to the eye pattern monitoring device, receiving the plurality of scan data signals outputted by the eye pattern monitoring device, performing phase-shift on the first clock signal to generate a synchronization clock signal having a phase relationship, with the plurality of scan data signals, that satisfies a setup/hold time requirement, synchronizing the plurality of scan data signals with the synchronization clock signal, and outputting a plurality of synchronized scan data signals;wherein, a phase of the synchronization clock signal further satisfies a condition that, a phase relationship between the plurality of scan data signals synchronized by the synchronization and the first clock signal further satisfies a setup/hold time requirement.2. The eye pattern measurement apparatus according to claim 1 , wherein the eye pattern monitoring device further outputs a second clock signal synchronous with the plurality of scan data signals; and the data ...

DUTY CYCLE CORRECTION CIRCUIT AND CLOCK CORRECTION CIRCUIT INCLUDING THE SAME

A duty cycle correction circuit includes a first inverter suitable for driving a second clock in response to a first clock; a second inverter suitable for driving the first clock in response to the second clock; and a duty cycle detector suitable for detecting a duty cycle of the first clock or the second clock, wherein driving forces of one or more inverters among the first inverter and the second inverter are controlled based on a duty detection result of the duty cycle detector. 1. A duty cycle correction circuit , comprising:a first inverter suitable for driving a second clock in response to a first clock;a second inverter suitable for driving the first clock in response to the second clock; anda duty cycle detector suitable for detecting a duty cycle of the first clock and the second clock,wherein driving forces of one or more inverters among the first inverter and the second inverter are controlled based on a duty detection result of the duty cycle detector.2. The duty cycle correction circuit of claim 1 , wherein when the duty detection result shows that a high pulse width of the first clock is longer than a high pulse width of the second clock claim 1 , a driving force of the second inverter is increased claim 1 , andwhen the duty detection result shows that the high pulse width of the second clock is longer than the high pulse width of the first clock, a driving force of the first inverter is increased.3. The duty cycle correction circuit of claim 1 , wherein when the duty detection result shows that a high pulse width of the first clock is longer than a high pulse width of the second clock claim 1 , a driving force of the first inverter is decreased claim 1 , andwhen the duty detection result shows that the high pulse width of the second clock is longer than the high pulse width of the first clock, a driving force of the second inverter is decreased.4. The duty cycle correction circuit of claim 1 , wherein the duty cycle detector includes:a first low pass ...

SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS INCLUDING SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR CONTROLLING CLOCK SIGNAL IN SEMICONDUCTOR INTEGRATED CIRCUIT

A semiconductor integrated circuit includes a first generation unit configured to generate a fixed frequency division clock signal (first signal) from an output clock signal of a clock source, a fixed frequency division state monitoring unit configured to monitor the first signal, a second generation unit configured to generate a variable frequency division clock signal (second signal) from the output signal, and a variable frequency division state monitoring unit configured to monitor the second signal. In a case where the frequency of the second signal is returned from a reduced frequency to normal, when the variable frequency division state monitoring unit determines that the second signal becomes high in a next cycle, output of the second signal is stopped, and when the fixed frequency division state monitoring unit determines, after the output is stopped, that the first signal becomes high in a next cycle, the output is resumed.

APPARATUS FOR MANAGING CLOCK DUTY CYCLE CORRECTION (DCC)

Embodiments of the present invention disclose an apparatus for managing clock duty cycle. The apparatus comprises a Duty Cycle Control Circuit (DCCC) for receiving at least an input clock signal and generating an output clock signal with adjustable duty cycle, a first Low-Pass Filter with Pull-Up Resistor (LPFPR) for receiving the output clock signal with adjustable duty cycle and simultaneously averaging and raising the common mode of the output thereof, a frequency divider for generating a signal with a 50% duty cycle, a second LPFPR for receiving the generated signal with 50% duty cycle and simultaneously averaging and raising the common mode of the output thereof and an OPAMP for receiving the outputs of the first and second LPFPRs for generating an equivalent reference signal to be fed to the DCCC as a control input, thereby facilitating correction of the duty cycle of the input clock signal. 1. An apparatus for managing clock duty cycle comprising:a Duty Cycle Control Circuit (DCCC) for receiving at least an input clock signal and generating an output clock signal with adjustable duty cycle;a first Low-Pass Filter with Pull-Up Resistor (LPFPR) for receiving the output clock signal with adjustable duty cycle and simultaneously averaging and raising the common mode of the output thereof;a frequency divider for generating a signal with a 50% duty cycle;a second LPFPR for receiving the generated signal with 50% duty cycle and simultaneously averaging and raising the common mode of the output thereof; andan OPAMP for receiving the outputs of the first and second LPFPRs for generating an equivalent reference signal to be fed to the DCCC as a control input, thereby facilitating correction of the duty cycle of the input clock signal.2. The apparatus of claim 1 , wherein the output of the OPAMP is fed back as input to the DCCC.3. The apparatus of claim 1 , wherein the DCCC comprises a first inverter claim 1 , a Low-Pass Filter (LPF) claim 1 , an Alternating Current (AC ...

TRANSMITTER AND RECEIVER CIRCUIT, INTEGRATED CIRCUIT, AND TESTING METHOD

A transmitter and receiver circuit includes a phase interpolator that generates a process clock having a phase based on a reference clock, a first selector that selects a first clock so that the first clock is the process clock in a first mode and is the reference clock in a second mode, a deserializer that converts a serial input data into a parallel output data in accordance with the first clock and outputs the parallel output data, a second selector that selects a second clock so that the second clock is the reference clock in the first mode and is the process clock in the second mode, and a serializer that converts a second parallel input data into a serial output data according to the second clock and outputs the serial output data. 1. A transmitter and receiver circuit comprising:a phase interpolator configured to generate a process clock having a phase based on a reference clock;a first selector configured to select a first clock so that the first clock is the process clock in a first mode and is the reference clock in a second mode;a deserializer configured to convert a serial input data into a parallel output data in accordance with the first clock, and output the parallel output data;a second selector configured to select a second clock so that the second clock is the reference clock in the first mode and is the process clock in the second mode; anda serializer configured to convert a second parallel input data into a serial output data according to the second clock, and output the serial output data.2. The transmitter and receiver circuit as claimed in claim 1 , further comprising:a digital filter configured to accumulate a phase error between the serial input data and the process clock based on the parallel output data, and output a phase adjusting signal that instructs a phase shift amount for shifting the phase of the process clock in accordance with an accumulated result of the phase error;an adjusting node configured to receive a test adjusting ...

CIRCUIT AND METHOD FOR CREATING ADDITIONAL DATA TRANSITIONS

When a data path includes CMOS circuitry, such circuitry may introduce jitter into the data signal. Embodiments are described in which additional data transitions are made to occur, and these additional data transitions may change the characteristics of the data frequency content transferred to the power supply so that such noise may be better filtered. This may have an effect of reducing jitter in the data signal. In one embodiment, a second data signal is generated to be a version of a first data signal with every second bit inverted. Second CMOS circuitry receives the second data signal in parallel to first CMOS circuitry receiving the first data signal. The first CMOS circuitry and the second CMOS circuitry are connected to a same power supply. 1. A circuit comprising:first CMOS circuitry to receive a first data signal representing a plurality of bits;a signal generating circuit to generate a second data signal so that the second data signal is a version of the first data signal with every second bit of the plurality of bits inverted;second CMOS circuitry to receive the second data signal in parallel to the first CMOS circuitry receiving the first data signal to result in a data transition in either the first CMOS circuitry or the second CMOS circuitry every bit period for the plurality of bits;wherein the first CMOS circuitry and the second CMOS circuitry are connected to a same power supply.2. The circuit of claim 1 , wherein the second CMOS circuitry is substantially the same as the first CMOS circuitry.3. The circuit of claim 2 , further comprising:a first multiplexer to multiplex a pair of half-rate data signals to produce the first data signal; andwherein the signal generating circuit comprises:an inverter to invert one of the pair of half-rate data signals to produce an inverted half-rate data signal, anda second multiplexer to multiplex the inverted half-rate data signal with the other one of the pair of half-rate data signals to produce the second data ...

DELAY CIRCUITS

A delay circuit is provided. The delay circuit includes a voltage-generation circuit and a signal-generation circuit. The voltage-generation circuit receives an input signal and generates a first control voltage and a second control voltage. The signal-generation circuit is controlled by the first control voltage and a second control voltage to generate an output signal. A first delay time by which a falling edge of the output signal is delayed from a falling edge of the output signal is determined by the first control voltage. A second delay time by which a rising edge of the output signal is delayed from a rising edge of the output signal is determined by the second control voltage. 1. A delay circuit comprising:a voltage-generation circuit receiving an input signal and generating a first control voltage and a second control voltage, wherein the voltage-generation circuit receives a first high operation voltage and a first low operation voltage which is lower than the first high operation voltage; anda signal-generation circuit controlled by the first control voltage and the second control voltage to generate an output signal, wherein the signal-generation circuit receives a second high operation voltage and a second low operation voltage which is lower than the second high operation voltage,wherein the first high operation voltage is lower than the second high operation voltage, and the first low operation voltage is higher than the second low operation voltage,wherein a first delay time by which a falling edge of the output signal is delayed from a falling edge of the input signal is determined by the second control voltage, and a second delay time by which a rising edge of the output signal is delayed from a rising edge of the input signal is determined by the first control voltage.2. The delay circuit as claimed in claim 1 , wherein the voltage-generation circuit comprises:a boost element receiving the first low operation voltage and generates the first ...

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

A circuit device includes a DLL circuit and an adjustment circuit. The DLL circuit has a plurality of delay elements, and a first clock signal generated using a first resonator and having a first clock frequency is input to the DLL circuit. Delayed clock signals from the delay elements of the DLL circuit, and a second clock signal generated using a second resonator and having a second clock frequency lower than the first clock frequency are input to the adjustment circuit, and the adjustment circuit adjusts delay amounts of the delay elements of the DLL circuit using a frequency difference between the first clock frequency and the second clock frequency. 1. A circuit device comprising:a delay locked loop (DLL) circuit, which has a plurality of delay elements, and to which a first clock signal generated using a first resonator and having a first clock frequency is input; andan adjustment circuit, to which delayed clock signals from the delay elements of the DLL circuit, and a second clock signal generated using a second resonator and having a second clock frequency lower than the first clock frequency are input, and which adjusts delay amounts of the delay elements of the DLL circuit using a frequency difference between the first clock frequency and the second clock frequency.2. The circuit device according to claim 1 , whereinthe adjustment circuit adjusts the delay amounts of the plurality of delay elements of the DLL circuit using a time difference in transition timing between the first clock signal and the second clock signal.3. The circuit device according to claim 1 , whereinthe adjustment circuit adjusts the delay amount of the i-th (i is an integer no smaller than 1) delay element of the plurality of delay elements using a transition of a signal level at i-th transition timing of the second clock signal after phase synchronization timing between the first clock signal and the second clock signal.4. The circuit device according to claim 3 , whereinthe ...

SYSTEM AND METHOD FOR DUTY CYCLE CORRECTION

Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal. 1. An apparatus comprising:a duty cycle corrector (DCC) configured to receive an input clock signal and a control signal and to produce an output clock signal responsive, at least in part, to the input clock signal and the control signal;a circuit configured to divide a frequency of the input clock signal by N and to generate an intermediate clock signal, wherein N being an integer more than 1; anda phase detector configured to generate the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.2. The apparatus of claim 1 , wherein the phase detector is configured to detect a first edge type of the output clock signal every Ncycle and a second edge type of the intermediate clock signal claim 1 , and to compute the difference in phase between the detected first edge type and the detected second edge type.3. The apparatus of claim 1 , further comprising:a replica circuit configured to receive the intermediate clock signal and to model a propagation delay between a node of the input clock signal and a node of the output clock signal.4. The apparatus of claim 1 , further comprising a DCC controller configured to convert the control signal to an internal control signal for the DCC.5. The apparatus of wherein the DCC controller is included in the DCC.6. The apparatus of claim 3 ...

CIRCUITS AND METHODS FOR PERFORMING HASH ALGORITHM

Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency. 1. A circuit for performing a hash algorithm , comprising:an input module for receiving data; andan operation module for calculating a hash value based on received data, the operation module including a plurality of operation stages arranged in a pipeline structure, the plurality of operation stages including a 0th operation stage, a 1st operation stage, up to a P-th operation stage, wherein P is a fixed positive integer greater than 1 and less than the number of operation stages in the pipeline structure,wherein each of the 1st operation stage to the P-th operation stage includes:a plurality of cache registers for storing intermediate values of a current operation stage and operating at a first frequency, anda plurality of extension registers for storing extension data of a current operation stage, and including a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency,wherein the second frequency is 1/N times of the first frequency, and N is a fixed ...

DYNAMIC CONTROL OF EDGE SHIFT FOR DUTY CYCLE CORRECTION

A duty cycle correction device may be provided for correcting a duty cycle of an input signal. The device includes a first duty cycle correction circuit. The first duty cycle correction circuit receives the input signal. The first duty cycle correction circuit generates a first intermediate signal. The device includes a first programmable delay circuit. The first programmable delay circuit is controlled by a first delay control signal. The first programmable delay circuit receives the first intermediate signal. The first programmable delay circuit generates an output signal. The device includes a second duty cycle correction circuit. The second duty cycle correction circuit receives the input signal. The second duty cycle correction circuit generates a second intermediate signal. The device includes a second programmable delay circuit. The second programmable delay circuit generates a reference signal. The device includes a skew control arrangement operable for generating the first delay control signal. 1. A method for operating a skew control arrangement of a duty cycle correction device for correcting a duty cycle of an input signal , wherein the duty cycle correction device comprises a signal path for generating an output signal from the input signal , the method comprising:receiving the input signal;feeding the input signal into a main signal path, wherein the main signal path comprises a first duty cycle correction circuit and a first programmable delay circuit;correcting a duty cycle of the input signal based on a first duty cycle control signal fed to the first duty cycle correction circuit;compensating a phase misalignment by the first programmable delay circuit, wherein the phase misalignment is caused by the first duty cycle correction circuit, and wherein the first programmable delay circuit is controlled by a first delay control signal;feeding the input signal also to a reference signal path in which a reference signal is generated from the input signal, ...

CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS

Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed. 1. An electronic device , comprising:a functional module comprising synchronous logic circuitry that receives an output clock signal from configurable clock circuitry; anda controller coupled to the configurable clock circuitry, wherein the controller is configured to cause a scaling of a frequency of the output clock signal of the configurable clock circuitry; configuring a first clock signal generator of the plurality of clock signal generators to provide an internal clock signal having a target frequency; and', 'providing the internal clock signal as the output clock signal of the configurable clock circuitry., 'wherein the configurable clock circuitry comprises a plurality of clock signal generators, and wherein scaling the frequency of the output clock signal of the configurable clock circuitry comprises2. The electronic device of claim 1 , wherein the electronic device comprises a field-programmable gate array.3. The electronic device of claim 1 , wherein each clock generator of the plurality of clock signal generators comprise a phase-locked loop or a digitally locked loop.4. The electronic device of claim 1 , comprising a second configurable clock and a second functional module comprising synchronous logic circuitry ...

CLOCK BUFFERS WITH PULSE DRIVE CAPABILITY FOR POWER EFFICIENCY

A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification. 1. A clock driver for an integrated circuit , comprisinga multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output, the input for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal for the integrated circuit, the output connected to the positive pulse driving branch and the negative pulse driving branch; anda pulse generator having a positive pulse generator portion that is connected to an output of the positive pulse driving branch of the multi-stage delay cell and a negative pulse generator portion that is connected to an output of the negative pulse driving branch of the multi-stage delay cell,wherein the pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.2. The clock driver of claim 1 , wherein the ...

DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF

A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal. 1. A duty cycle correction circuit , comprising:a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal;a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal; anda control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.2. The duty cycle correction circuit of claim 1 , wherein:the first tracking type comprises a successive approximation register (SAR) tracking type, andthe second tracking type comprises a linear tracking type.3. The duty cycle correction circuit of claim 1 , wherein the control signal generation unit comprises:a duty ratio detection unit configured to detect the duty ratio of the output clock signal and generate a duty information corresponding to the detected duty ratio;a first control signal generation unit configured to generate a first duty control signal, into which the first tracking type is incorporated, based on to the duty information;a second control signal generation unit configured to generate a second duty control signal, into which the second ...

PHASE INTERPOLATOR AND CLOCK GENERATING METHOD

A phase interpolator includes a current generating circuit, a current controlling circuit and a signal generating circuit, wherein the current generating circuit is arranged to generate a current; and the current controlling circuit is arranged to generate a control signal to the current generating circuit to control a current value of the current. The signal generating circuit includes a capacitor, wherein the signal generating circuit generates a phase interpolation signal by using the capacitor to receive the current, wherein a phase of the phase interpolation signal is varied according to the current. 1. A phase interpolator , comprising:a current generating circuit, arranged to generate a current;a current controlling circuit, arranged to generate a control signal to the current generating circuit to control a current value of the current; anda signal generating circuit, comprising a capacitor, wherein the signal generating circuit receives the current via the capacitor to generate a phase interpolation signal;wherein a phase of the phase interpolation signal is varied according to the current value of the current.2. The phase interpolator of claim 1 , further comprising:a feedback circuit, arranged to generate a discharge signal to a switch according to the phase interpolation signal for discharging the capacitor.3. The phase interpolator of claim 2 , wherein the signal generating circuit further comprises a hysteresis circuit claim 2 , and the step of the signal generating circuit receiving the current via the capacitor to generate the phase interpolation signal comprises:receiving the current via the capacitor to generate a trigger voltage signal to the hysteresis circuit, wherein the hysteresis circuit generates the phase interpolation signal according to the trigger voltage signal.4. The phase interpolator of claim 3 , wherein when the trigger voltage signal is greater than a predetermined threshold value claim 3 , the phase interpolation signal reverses ...

OPEN LOOP SOLUTION IN DATA BUFFER AND RCD

An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit and (ii) adjust a delay of transferring a data signal through the apparatus in response to (a) the delay amount and (b) the in-phase clock signal. The data signal may be received from the memory interface. The delay of transferring the data signal may be implemented to keep a latency of a data transfer within a pre-defined range. 1. An apparatus comprising:a delay circuit configured to (i) generate a delayed strobe signal in response to (a) a strobe signal received from a memory interface and (b) a delay amount received from a calibration circuit, (ii) adjust a delay of transferring a data signal through said apparatus in response to (a) a delay amount and (b) an in-phase clock signal and (iii) present said data signal to a host interface; andan open loop circuit configured to (i) generate said in-phase clock signal by performing a phase alignment in response to (a) a clean version of a system clock and (b) said delayed strobe signal and (ii) present said in-phase clock signal to said delay circuit and said host interface, wherein said delay of transferring said data signal is implemented to keep a latency of a data transfer within a pre-defined range.2. The apparatus according to claim 1 , wherein said apparatus reduces a power consumption compared to a PLL/DLL solution.3. The apparatus according to claim 1 , wherein said apparatus is configured to reduce jitter on said strobe signal and said data signal received from a DRAM memory module.4. The apparatus according to claim 1 , ...

ERROR DETECTION AND COMPENSATION FOR A MULTIPLEXING TRANSMITTER

Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error. 1. A system for reducing error associated with a multiplexing transmitter , comprising:an error detector circuit configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern; anda duty cycle correction circuit configured to adjust the clock associated with the transmitter based on the error detector output.2. The system of claim 1 , wherein the error detector circuit is configured to measure the duty cycle error for an in-phase clock associated with the transmitter to generate the error detector output based on an in-phase clock pattern for the output generated by the transmitter in response to the defined bit pattern.3. The system of claim 1 , wherein the error detector circuit is configured to measure the duty cycle error for a quadrature clock associated with the transmitter to generate the error detector output based on a quadrature clock pattern for the output ...

EFFICIENT SKEW SCHEDULING METHODOLOGY FOR PERFORMANCE & LOW POWER OF A CLOCK-MESH IMPLEMENTATION

According to one aspect, a method may include receiving a circuit model that includes a clock mesh that controls each of a plurality of logic circuits by inputting a respective clock signal to an end-point of each logic circuit. The method may include providing an incremental latency adjustment to the circuit model by determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule. And, for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of an end-point by a quantized amount. Further, for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of an end-point that is associated by a quantized amount. The method may also include repeating, the step of providing an incremental timing update. The method may include performing a timing evaluation upon the circuit model. 1. A method of adjusting clock skews , the method comprising:receiving a circuit model that includes logic circuits at least partially controlled by a clock mesh, wherein the clock mesh, at least partially, controls each of the logic circuits by inputting a respective clock signal to an end-point of a respective logic circuit; ["determining one or more end-points that are candidates for adjustment of a respective end-point's clock skew schedule,", 'for each end-point that is associated with a negative front slack, adjusting a clock skew schedule of a respective end-point by a quantized amount, up to a maximum push threshold,', 'for each end-point that is associated with a negative back-slack, adjusting the clock skew schedule of a respective end-point that is associated by a quantized amount, up to a maximum pull threshold,, 'providing an incremental latency adjustment to the circuit model byrepeating, a plurality of times, the step of providing an incremental timing update to the circuit model; andperforming a timing evaluation upon the circuit model via either ...

Apparatus and method of monitoring chip process variation and performing dynamic adjustment for multi-chip system by pulse width

A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips include at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip transmits an output signal to the second chip via the chip-to-chip connection, and the second chip processes an input signal that is derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system calibrates a chip setting of at least one of the first chip and the second chip for pulse width calibration of the input signal.

CLOCK GENERATION CIRCUIT HAVING DESKEW FUNCTION AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING SAME

A clock generation circuit having a deskew function and a semiconductor integrated circuit device including the same are provided. The clock generation circuit includes a clock gating circuit configured to gate an input clock signal based on a first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times a period of the input clock signal. 1. A clock generation circuit comprising:a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and generate a first output signal;a flip-flop configured to receive the input clock signal and a second waveform signal and generate a second output signal; andan OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times that of a period of the input clock signal, where ‘N’ is a positive real number.2. The clock generation circuit of claim 1 , wherein the clock gating circuit comprises:a latch configured to latch the first waveform signal in response to the input clock signal; andan AND element configured to perform an AND operation on an output signal of the latch and the input clock signal.3. The clock generation circuit of claim 1 , further comprising:a waveform generator configured to generate the first waveform signal and the second waveform signal in response to the input clock signal.4. The clock generation circuit of claim 3 , wherein the waveform generator divides a frequency of the input clock signal by N to generate the first and second waveform signals having a period that is N times the period of the input clock signal and having the same duty ratio.5. The clock ...

DIRECT DRIVE RF CIRCUIT FOR SUBSTRATE PROCESSING SYSTEMS

A direct drive circuit for providing RF power to a component of a substrate processing system includes a clock generator to generate a clock signal at a first frequency, a gate driver to receive the clock signal and a half bridge circuit. The half bridge circuit includes a first switch with a control terminal connected to the gate driver, a first terminal and a second terminal; a second switch with a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal; a first DC supply to supply a first voltage to the first terminal of the first switch; and a second DC supply to supply a second voltage to the second terminal of the second switch. The first and the second voltages have opposite polarities and are approximately equal in magnitude. 1. A direct drive circuit for providing RF power to a component of a substrate processing system , comprising:a clock generator to generate a clock signal;a gate driver to receive the clock signal; a first switch with a control terminal connected to the gate driver, a first terminal, and a second terminal;', 'a second switch with a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal;, 'a half bridge circuit includinga first DC supply to supply a first voltage to the first terminal of the first switch;a second DC supply to supply a second voltage to the second terminal of the second switch, the first and second voltages being approximately equal and of opposite polarities; andat least one of an inductor and a capacitor connecting the output node to the component of the substrate processing system,wherein the direct drive circuit supplies the RF power to the component of the substrate processing system connected across a reference potential and the at least one of the inductor and the capacitor.2. The direct drive circuit of further ...

TIMING EVENT DETECTION

It is an objective to provide timing event detection. According to a first aspect, a device, comprises: a clocked conditional buffer configured to set an output of the clocked conditional buffer to a first state during a non-detection period; the clocked conditional buffer further configured to toggle the output from the first state to the second state during a detection period, wherein the toggling being enabled by either one of the two states; and the clocked conditional buffer further configured to guarantee that the output is toggling only to one direction during the detection period. This may prevent false event detections. Furthermore, with respect to a timing point of view, one is able to operate without pulses, where pulse width may be difficult to manage in low voltages. 120.-. (canceled)21. A device , comprising:a clocked conditional buffer having a data input, a further input, and an output,the clocked conditional buffer configured to set the output to a first state during a non-detection period defined by a first value at the further input;the clocked conditional buffer further configured to toggle the output from the first state to the second state during a detection period defined by a second value at the further input, wherein the toggling is enabled by only one of the two possible states at the data input; andthe clocked conditional buffer further configured to guarantee that the output is toggling only to one direction during the detection period.22. The device of claim 21 , wherein the clocked conditional buffer is further configured to lack an ability to toggle claim 21 , during the detection period claim 21 , to an additional direction other than the one direction.23. The device of claim 21 , wherein:the device comprises a generate block and an event detection device coupled to receive signals generated by the generate block, and{'claim-ref': {'@idref': 'CLM-00021', 'claim 21'}, 'the generate block comprises at least one of the clocked ...

DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE CORRECTION AND QUADRATURE PLACEMENT

A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal. 1. An apparatus , comprising:a delay line configured to receive a clock signal and to output a recovered clock signal, the delay line having a delay value that is usable to adjust timing of at least one edge of the recovered clock signal relative to the received clock signal; anda finite state machine (FSM) coupled to the delay line and configured to generate a code and to provide the generated code to the delay line to select the delay value.2. The apparatus of wherein the delay line is configured to use the delay value to adjust timing of a rising edge and a falling edge of the recovered clock signal relative to the received clock signal.3. The apparatus of wherein:the delay line is configured to time the rising edge of the recovered clock signal to occur in a middle between a rising edge of the received clock signal and an immediate falling edge of the received clock signal; andthe delay line is configured to time the falling edge of the recovered clock signal to occur in a middle between the falling edge of the received clock signal and an immediate rising edge of the received clock signal.4. The apparatus of wherein the delay line is configured to use the delay value to adjust a duty cycle of the recovered clock signal to a 50% duty cycle.5. The apparatus of claim 1 , further comprising:a first instance of a measurement structure coupled to ...

Semiconductor device

To provide a semiconductor device capable of adjusting the timing of a clock signal or a high-quality semiconductor device. The semiconductor device includes a first transistor and a circuit including a second transistor. A channel of the first transistor is formed in an oxide semiconductor layer. A first signal is input to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor. A first clock signal is input to the circuit. The circuit outputs a second clock signal. The timing of the second clock signal is different from that of the first clock signal.

DIGITAL-TO-PHASE CONVERTER

Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input. 1. A digital-to-phase converter circuit for producing a clock output having a digitally controlled phase , the circuit comprising:a first pre-driver module configured to receive complementary in-phase clock signals and produce a first pair of complementary buffered clock signals having controlled slew rates;a second pre-driver module configured to receive complementary quadrature clock signals and produce a second pair of complementary buffered clock signals having controlled slew rates; anda mixer module configured to produce the clock output by forming a weighted combination of the buffered clock signals based on a phase control input.2. The circuit of claim 1 , wherein the controlled slew rates are controlled to produce full swings on the first pair of complementary buffered clock signals and the second pair of complementary buffered clock signals.3. The circuit of claim 1 , wherein the first pre-driver module comprises:a variable strength source configured to control rising slew rates of the first pair of complementary ...

Apparatuses and methods for duty cycle adjustment

Apparatuses and methods for duty cycle adjustment are disclosed herein. An example apparatus may include a node, a phase mixer, and a duty cycle adjuster circuit. The phase mixer may have a first step duty cycle response and may be configured to provide a first output signal to the node in accordance with the first step duty cycle response. The duty cycle adjuster circuit may have a second step duty cycle response complementary to the first step duty cycle response and may be configured to provide a second signal to the node in accordance with the second step duty cycle response.

RC OSCILLATOR, MOTOR-DRIVEN INTEGRATED CIRCUIT, AND MOTOR DEVICE

A RC oscillator comprises a resistor unit. The resistor unit can comprise at least one set of compensation resistor. Each set of compensation resistor comprises a positive temperature coefficient resistor and a negative temperature coefficient resistor coupled in series with the positive temperature coefficient resistor. 1. A RC oscillator , comprising:a resistor unit having at least one set of compensation resistor, wherein each set of compensation resistor comprises a positive temperature coefficient resistor and a negative temperature coefficient resistor coupled in series with the positive temperature coefficient resistor.2. The RC oscillator of claim 1 , wherein the RC oscillator comprises a plurality of sets of compensation resistor.3. The RC oscillator of claim 2 , wherein the plurality of sets of compensation resistor are coupled in series claim 2 , each of or some of plurality of sets of compensation resistor are coupled with a selection switch in parallel.4. The RC oscillator of claim 2 , wherein the plurality of sets compensation resistor are disposed in a plurality of parallel branches claim 2 , each of or some of plurality of parallel branches are coupled with a selection switch in series.5. The RC oscillator of claim 1 , wherein the positive temperature coefficient resistor is made of at least one of N+ diff w/o silicide claim 1 , P+ poly w/i silicide claim 1 , P+ diff w/o silicide claim 1 , P+ diff w/i silicide claim 1 , N+ poly w/i silicide claim 1 , N+ diff w/i silicide.6. The RC oscillator of claim 1 , wherein the negative temperature coefficient resistor is made of at least one of P+ poly w/o silicide and N+ poly w/o silicide.7. The RC oscillator of claim 1 , wherein the positive temperature coefficient resistor is made of N+ diff w/o silicide and the negative temperature coefficient resistor is made of N+ poly w/o silicide.8. The RC oscillator of claim 7 , wherein an absolute value of a linear temperature coefficient of the positive temperature ...

VARIABLE DELAY CIRCUITS

A passable latch circuit and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit has a dynamic latch including a first P-transistor, a first N-transistor, a second P-transistor, a second N-transistor and a clock input circuitry. The passable latch circuit further includes a control switch connected between the gates of the second P-transistor and the second N-transistor. The control switch has an on state and an off state, and the passable latch circuit is configured to have different delays by controlling the state of the control switch. 2. The passable latch circuit according to claim 1 , wherein the passable latch circuit can be configured to provide a pass delay or a clocked delay depending on the state of the control switch.3. The passable latch circuit according to claim 1 , wherein the control switch comprises any one of an N-transistor claim 1 , a P-transistor or a transmission gate.4. The passable latch circuit according to claim 1 , wherein the clock input circuitry comprises an N-transistor having a drain connected to the first node of the clock input circuitry claim 1 , a source connected to the second node of the clock input circuitry and a gate connected to a clock input.5. The passable latch circuit according to claim 1 , wherein the clock input circuitry comprises a P-transistor having a source connected to the first node of the clock input circuitry claim 1 , a drain connected to the second node of the clock input circuitry and a gate connected to a clock input.6. The passable latch circuit of claim 1 , wherein the passable latch circuit is a single phase retiming unit.7. The passable latch circuit according to claim 1 , wherein the passable latch circuit is a multiple M-phase retiming unit and wherein the clock input circuitry comprises:a plurality of M clock input branches, wherein each clock input branch comprises a first N-transistor and a second N transistor connected in series between ...

DELAY CIRCUIT

A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit. 1. A delay circuit comprising:a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to timing of any one of an even cycle and an odd cycle based on a clock;a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal; anda fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit.2. The delay circuit of claim 1 , further comprising:a frequency division unit suitable for generating the frequency divided clock by dividing a frequency of the clock by 2.3. The delay circuit of claim 1 , wherein the fine timing measurement unit comprises:a plurality of first shift units suitable for generating a first shift signal and a second shift signal by sequentially shifting the input signal in synchronization with the clock; anda sampling unit suitable for generating the fine timing information by sampling the frequency divided clock in synchronization with the first shift signal.4. The delay circuit of claim 3 , wherein the fine timing measurement unit further comprises a summation unit suitable for adding up activation sections of the first shift signal and the second shift signal and outputting a summation signal having the added activation ...

SEMICONDUCTOR DEVICE

The problem was that the noise superimposed on a touch electrode via the human body can incur erroneous touch determination by a touch sensor circuit. The invention provides a semiconductor device including a terminal to which a touch electrode may be coupled; a source voltage drop circuit generating a constant voltage; a phase shift circuit generating a phase shifted clock in response to a first clock and a phase control signal; and a switching circuit to which the constant voltage is supplied. The switching circuit generates drive pulses for applying the constant voltage to the terminal in response to the phase shifted clock. The phase shift circuit varies the phase of the drive pulses based on the phase control signal. 1. A semiconductor device comprising:a terminal to which a touch electrode may be coupled;a source voltage drop circuit which generates a constant voltage;a phase shift circuit which generates a phase shifted clock in response to a first clock and a phase control signal; anda switching circuit to which the constant voltage is supplied;wherein the switching circuit generates a drive pulse for applying the constant voltage to the terminal in response to the phase shifted clock, andwherein the phase shift circuit varies the phase of the drive pulse based on the phase control signal.2. The semiconductor device according to claim 1 , further comprising:a current control oscillation circuit; anda counter;wherein the source voltage drop circuit supplies a first current to the switching circuit;wherein the current control oscillation circuit generates a second clock of which the frequency varies depending on the value of the first current;wherein the counter counts the number of pulses in the second clock over a counting period, andwherein the phase shift circuit varies the phase of the drive pulse in such a manner that the number of the drive pulses in effect when a noise superimposed on the touch electrode causes an increase in the value of the first ...

APPARATUS FOR CONTROLLING SEMICONDUCTOR CHIP CHARACTERISTICS

Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit. 12-. (canceled)3. An apparatus comprising:an electronic circuit defined on a semiconductor chip, wherein the electronic circuit includes modifiable operating characteristics;a performance measuring component configured to provide an output indicative of operating characteristics of the electronic circuit; andsoftware configured to control a value of at least one of the modifiable operating characteristics of the electronic circuit.4. The apparatus of claim 3 , wherein the software is further configured to select clock delays of the electronic circuit so that the timing of data transfer made with respect to a clock signal is controlled.5. The apparatus of claim 3 , wherein the performance measuring component comprises ring oscillators.6. The apparatus of claim 3 , wherein the modifiable operating characteristics are configured to be modified by selecting clock delays that are managed so that the timing of data transfer made with respect to a clock signal is controlled.7. The apparatus of claim 3 , wherein the modifiable operating characteristics are configured to be measured utilizing a ring oscillator.8. The apparatus of claim 3 , wherein the electronic circuit is configured to provide an output signal that is provided as input to circuitry located on a different semiconductor chip than the electronic circuit.9. The apparatus of claim 8 , wherein the software is further configured to ...

SYSTEMS AND METHODS FOR PHASE SYNCHRONIZATION OF LOCAL OSCILLATOR PATHS IN OSCILLATOR-OPERATED CIRCUITS

Embodiments described herein provide a system having phase synchronized local oscillator paths. The system includes a first circuit, which in turn includes a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter. The first circuit also includes a first phase-locked loop coupled to the first counter. The first phase-locked loop is configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal. 1. A system having phase synchronized local oscillator paths , the system comprising: a first counter configured to generate a first counter output signal in response to a first clock signal controlling the first counter; and', 'a first phase-locked loop coupled to the first counter, the first phase-locked loop being configured to receive the first counter output signal as a first synchronization clock for the first phase-locked loop and to generate a first output signal having rising edges aligned according to the first counter output signal., 'a first circuit including2. The system of claim 1 , wherein the first phase-locked loop circuit includes:an oscillator configured to generate an oscillator clock;a multi-modulus divider configured to divide the oscillator clock by a non-integer value to match a reference frequency; a multiplier configured to generate a multiplier output signal representing a product of a fractional part of a frequency control word and the first counter output signal;', 'an adder configured to generate a sum of an integer part of the frequency control word and the generated product of the fractional part of the frequency control word and the counter value corresponding to the first counter output signal, send the generated sum as a division ratio to the multi-modulus divider., 'a first sigma-delta modulator ...

SYSTEM ON CHIP

A system on chip (SOC) is provided. The SOC includes a system core logic, a voltage regulator, a clock generator and a system balance circuit. The voltage regulator provides an operating voltage to the system core logic and receives a current setting signal to set the voltage regulator to a low current mode or a high current mode. The clock generator provides a reference clock signal. The system balance circuit receives the reference clock signal to provide the current setting signal to the voltage regulator and provides the system clock signal to the system core logic, wherein the current setting signal is used to set the voltage regulator to the high current mode before the system clock signal is enabled, and set the voltage regulator to the low current mode after the system clock signal is enabled. 1. A system on chip , comprising:a system core logic;a voltage regulator coupled to the system core logic, receiving a power supply voltage to provide an operating voltage to the system core logic, and receiving a current setting signal to set the voltage regulator to a low current mode or a high current mode;a clock generator providing a reference clock signal; anda system balance circuit coupled between the system core logic, the voltage regulator and the clock generator to receive the reference clock signal, providing the current setting signal to the voltage regulator according to the reference clock signal, and providing a system clock signal to the system core logic, wherein the current setting signal is used to set the voltage regulator to the high current mode before the system clock signal is enabled, and set the voltage regulator to the low current mode after the system clock signal is enabled.2. The system on chip as recited in claim 1 , wherein the system balance circuit comprises:a first delayer having an input terminal that receives the reference clock signal and having an output terminal that provides the system clock signal;a second delayer having an ...

DUTY CYCLE MONITOR CIRCUIT AND METHOD FOR DUTY CYCLE MONITORING

An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold. A reference voltage generation circuit provides the first respective reference voltage threshold associated with the averaged inverted representation of the generated clock signal and provides the second respective reference voltage threshold associated with the non-inverted representation of the generated clock signal. A summing circuit is sums outputs of the first and second comparators and outputs a monitored duty cycle of the generated clock signal. 1. An electronic system comprising:a clock generation circuit configured to generate a clock signal; anda duty cycle monitoring circuit, DTC, operably coupled to the clock generation circuit and configured to monitor a duty cycle of the generated clock signal; a differential signal generator configured to receive the generated clock signal and generate an inverted representation of the generated clock signal, and generate a non-inverted representation of the generated clock signal;', 'an averaging circuit operably coupled to the differential signal generator and configured to average the generated non-inverted clock signal and average the inverted representation of the generated clock signal;', 'a comparison circuit comprising at least a first ...

GLITCH FREE ASYNCHRNOUS CLOCK MULTIPLEXER

Apparatus for glitch-free switching between multiple asynchronous clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters is synchronized to the destination clock domain and provides the ability to shut all clocks off for a period of time equal to the longest clock period. By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch —between different, asynchronous clocks without causing erratic behavior. 1. A glitch free , multi-clock , asynchronous control circuit comprisingN clock gater circuits, each having a clock input, a gate input, and a gated clock output; 'wherein each said clock gater circuit and said corresponding synchronizer circuit share a common clock selected from the group consisting of a main clock and a JTAG clock;', 'N−1 synchronizer circuits, each having a control input, a clock input, and an output, each said output being connected to a gate input of a corresponding said clock gater circuit;'}an OR gate having inputs and an output, each said input being connected to a corresponding gated clock output of said N clock gater circuits; and each said latch has a clock input, a set input, and an output, wherein said output of each of N−1 latches is connected to said gate input of each of a corresponding N−1 synchronizer circuit;', {'sup': th', 'th, 'the output of an Nlatch is connected to the gate input of an Nclock gater circuit;'}, {'sup': 'th', 'each of said N latches shares a common input clock with each other and with an Nclock gater circuit.'}], 'N latches wherein each of said N latches is connected to a corresponding one of said N clock gater ...

APPARATUSES AND METHODS FOR PROVIDING A SIGNAL WITH A DIFFERENTIAL PHASE MIXER

According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal. The apparatus further comprises a second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal, wherein the second intermediate signal is combined with the first intermediate signal at a node to provide, an output signal. 1. An apparatus comprising:a first phase mixer circuit configured to receive a first signal and a second signal and provide a first intermediate signal having a phase between a phase of the first signal and a phase of the clock signal; anda second phase mixer circuit configured to receive a complement of the first signal and a complement of the second signal and provide a second intermediate signal having a phase between a phase of the complement of the first signal and a phase of the complement of the second signal,wherein the second intermediate signal is combined with the first intermediate signal at a node to provide an output signal.2. The apparatus of claim 1 , further comprising:an output inverter coupled to the first intermediate signal between the first phase mixer circuit and the node.3. The apparatus of claim 2 , wherein the first intermediate signal experiences a first duty cycle variation and the second intermediate signal experiences a second duty cycle variation that is complementary to the first duty cycle variation.4. The apparatus of claim 2 , further comprising:a second output inverter cross-coupled to the output inverter.5. The apparatus of claim 1 , wherein the first phase mixer circuit and the second phase mixer circuit is ...

APPARATUSES AND METHODS FOR ADJUSTING TIMING OF SIGNALS

Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary. 1. An apparatus comprising: a first inverter configured to receive a first internal input signal and produce a first internal output signal, and', 'a second inverter configured to have a first drive strength that is changed responsive to first bias information and change a slew rate of one of the first internal input signal and the first internal output signal;, 'an adjuster circuit configured to receive a first input signal and produce a first output signal responsive to the first input signal, the adjuster circuit comprisinga duty cycle detector configured to detect a duty cycle of the first output signal and produce duty cycle information; anda bias generator configured to generate the first bias information responsive to the duty cycle information.2. The apparatus as claimed in claim 1 , wherein the second inverter circuit is configured to change the slew rate of one of a rising and a falling edge of the one of the first internal input signal and the first internal output signal greater than the other of the rising and the falling edges of the one of the first internal input signal and ...

Apparatus and method for compensating for duty signals

An apparatus and method for compensating for duty signals are disclosed herein. The apparatus for compensating for duty signals includes a signal input unit, a signal control unit, a combined signal control unit, a determination unit, and a signal output unit. The signal input unit receives a first signal and a second signal. The signal control unit controls the timing of the first and second signals based on first and second control signals, and outputs a combined signal. The combined signal control unit outputs first and second logic operation signals. The determination unit generates the first and second control signals if the timing of the first signal does not match the timing of the second signal, outputs the generated first and second control signals, and applies a third control signal to the combined signal control unit. The signal output unit outputs the first and second signals.

TIPLESS TRANSISTORS, SHORT-TIP TRANSISTORS, AND METHODS AND CIRCUITS THEREFOR

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor. 119-. (canceled)20. An integrated circuit , comprising:a plurality of first deeply depleted channel (DDC) transistors formed in a substrate and having controllable source-drain current paths coupled between a first and second node, the first DDC transistors having a first source and a first drain, the first DDC transistors having first extension regions that extend in a lateral direction on an inner side of the first source and the first drain, and under a gate electrode of the first DDC transistors, the first DDC transistors being configured to selectively couple a first output node to the first or second node in response to one or more input signals, the first DDC transistors having drawn gate lengths of less than one micron;a plurality of second deeply depleted channel (DDC) transistors formed in the substrate and having controllable source-drain current paths coupled between the first node and the second node, the second DDC transistors having a second source and a second drain, the second DDC transistors having second extension regions that extend in a lateral direction on an inner side of the second source and the second drain, and under a gate ...

SIGNAL RECEIVING CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SIGNAL RECEIVING CIRCUIT

A signal receiving circuit includes a buffer, a sampling circuit, and an equalizer. The buffer generates first and second amplified signals by amplifying a currently-inputted received signal in synchronization with an amplification clock signal. The sampling circuit generates an output signal by sampling the first and second amplified signals in synchronization with a sampling clock signal. The equalizer changes voltage levels of the first and second amplified signals based on third and fourth amplified signals which are generated from a previously-inputted received signal in synchronization with the amplification clock signal. 1. A signal receiving circuit comprising:a first buffer configured to generate a first amplified signal and a second amplified signal by amplifying a received signal which is currently inputted in synchronization with an amplification clock signal;a sampling circuit configured to generate an output signal by sampling the first and second amplified signals in synchronization with a sampling clock signal; andan equalizer configured to change voltage levels of the first and second amplified signals based on a third amplified signal and a fourth amplified signal which are generated from the received signal which is previously inputted in synchronization with the amplification clock signal.2. The signal receiving circuit according to claim 1 , wherein the amplification clock signal is aligned with an edge of the received signal and has a pulse width equal to or less than a duration of the received signal.3. The signal receiving circuit according to claim 1 , wherein the sampling clock signal has a phase that lags behind the amplification clock signal.4. The signal receiving circuit according to claim 1 , further comprising a synchronization switch configured to output the first and second amplified signals to the sampling circuit in synchronization with the amplification clock signal.5. The signal receiving circuit according to claim 4 , further ...

Gate driver circuit outputting superimposed pulses

Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.

High-resolution pulse width modulation signal generation circuit and method

A pulse width modulation (PWM) signal generation circuit and method are disclosed herein. The PWM signal generation circuit includes an integer part pulse generation circuit, and a fractional part pulse generation circuit. The integer part pulse generation circuit generates an integer part pulse using the integer part of the digitized value of a duty cycle, i.e., the ratio of the time during which any one of high and low levels is maintained to the period of a PWM signal. The fractional part pulse generation circuit generates the PWM signal using the integer part pulse and the fractional part of the digitized value of the duty cycle.

CLOCK-DISTRIBUTION DEVICE AND CLOCK-DISTRIBUTION METHOD

A clock-distribution device for dividing a clock signal into a plurality of clock signals for a plurality of registers is provided. The clock-distribution device includes at least one mesh driver and a clock mesh. The mesh driver is coupled to an input port of the clock-distribution device to transmit and divide the clock signal from the input port. The clock mesh is driven by the mesh driver and is utilized to uniformly distribute the clock signals for the registers. 1. A clock-distribution device for dividing a clock signal into a plurality of clock signals for a plurality of registers , comprising:a plurality of clock gates, utilized to transmit the clock signals to the registers; anda clock mesh, arranged between the clock gates and an input port of the clock-distribution device, utilized to distribute the clock signals to the clock gates uniformly, wherein the clock signals are provided from the input port.2. The clock-distribution device as claimed in claim 1 , further comprising at least one mesh driver arranged between the clock mesh and the input port to drive the clock mesh.3. The clock-distribution device as claimed in claim 2 , further comprising at least one pre-mesh driver arranged between the mesh driver and the input port to drive the mesh driver.4. The clock-distribution device as claimed in claim 3 , wherein the number of mesh drivers and pre-mesh drivers is determined by the number of registers and/or transition of the clock signal.5. The clock-distribution device as claimed in claim 3 , further comprising at least one buffer arranged between the pre-mesh driver and the input port to transmit the clock signal from the input port to the pre-mesh driver.6. The clock-distribution device as claimed in claim 1 , wherein the input port is coupled to a clock-generation module to receive the clock signal generated by the clock- generation-module.7. The clock-distribution device as claimed in claim 1 , wherein the clock gates connect to a plurality of ...

OPEN-LOOP CORRECTION OF DUTY-CYCLE ERROR AND QUADRATURE PHASE ERROR

A Phase Interpolator (PI) may be employed as a precisely-controlled delay element in a transmit path, for example in clock forwarded serial links. Methods and circuits are disclosed for estimating a delay needed to correct duty-cycle/and or phase errors of the received clock. These corrections or delta values may be transmitted back to the transmitter side, preferably expressed directly in terms of PI phase codes, for convenient adjustment in the transmitter clock circuitry. Various techniques also are disclosed for measuring and mitigating the effects on PI integral non-linearity.

PHASE CORRECTION CIRCUIT, CLOCK BUFFER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews. 1. A phase correction circuit comprising:a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals;a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and generate the plurality of selection signals;', 'detect phase skews of the plurality of signal paths according to the plurality of detection voltages; and', 'generate the plurality of phase control signals for correcting the phase skews of the plurality of signal paths., 'a control unit configured to2. The phase correction circuit according to claim 1 , wherein the test clock generation unit is configurable to block input of external signals to the plurality of signal paths in response to the plurality of selection signals.3. The phase correction circuit according to claim 1 , wherein the test clock generation unit is configurable to:stop generating the plurality of test clock signals in response to the plurality of selection signals; andallow external signals to pass through the plurality of signal paths.4. The phase correction circuit according to claim 1 , wherein the test clock generation unit includes a plurality of test clock generation units claim 1 , each of ...

METHOD AND SYSTEM FOR CONTROLLING A CHARGE PUMP

Embodiments of a method for controlling a charge pump and a control device for a charge pump are described. In one embodiment, a method for controlling a charge pump involves monitoring a power-on status of the charge pump, calculating a duty cycle of the charge pump within a time period based on the power-on status of the charge pump, and adjusting at least one of a clock frequency setting and a capacitance setting of the charge pump in based on the duty cycle of the charge pump. Other embodiments are also described. 1. A method for controlling a charge pump , the method comprising:monitoring a power-on status of the charge pump;calculating a duty cycle of the charge pump within a time period based on the power-on status of the charge pump; andadjusting at least one of a clock frequency setting and a capacitance setting of the charge pump based on the duty cycle of the charge pump.2. The method of claim 1 , wherein the time period is a multiple of one clock time period of a clock signal.3. The method of claim 1 , wherein the time period is one clock time period of a first clock signal with a frequency that is not correlated with the frequency of a second clock signal.4. The method of claim 1 , wherein calculating the duty cycle of the charge pump based on the power-on status comprises:determining an amount of time that the charge pump is powered on during the time period; andcalculating the duty cycle as a ratio of the amount of time that the charge pump is powered on to the time period.5. The method of claim 1 , wherein adjusting the at least one of the clock frequency setting and the capacitance setting of the charge pump comprises changing a frequency of a clock signal that is used to drive the charge pump or a total pumping capacitance of the charge pump if the duty cycle of the charge pump is larger than at least one maximum threshold or smaller than at least one minimum threshold within the time period.6. The method of claim 5 , wherein changing the frequency ...

DIGITAL DUTY CYCLE CORRECTION CIRCUIT

A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal. 1. A digital duty cycle correction circuit comprising:a duty cycle controller configured to generate a first output clock signal and a second output clock signal by compensating a duty cycle of a first input clock signal and a duty cycle of a second input clock signal based on a digital duty control code, the first and second input clock signals being a pair of differential signals, the first and second output clock signals being a pair of differential signals; anda digital duty control code generator configured to generate the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.2. The digital duty cycle correction circuit of claim 1 , wherein the digital duty control code generator comprises:a monitor configured to generate a first direct current (DC) voltage and a second DC voltage by monitoring the first output clock signal and the second output clock signal;a voltage-frequency converter configured to generate a reference frequency signal, a first frequency signal and a second frequency signal by performing a voltage-frequency conversion on a reference voltage, the first DC voltage and the second DC voltage;a frequency counter configured to generate a reference count value, a first count value and a second count value by counting pulses of the reference frequency signal, pulses of the first frequency signal and pulses of the second frequency ...

DUTY-CYCLE CORRECTION CIRCUIT AND METHOD

A duty-cycle correction circuit may include a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values, an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, and generating an up/down signal according to the lengths of a second section of the target clock and the first section of the selected delayed clock, a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal, a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock, and a control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction period. 1. A duty-cycle correction circuit comprising:a delayed clock generation unit suitable for generating a plurality of delayed clocks by delaying a target clock by different delay values;an up/down signal generation unit suitable for selecting a delayed clock having a delay value corresponding to a first section of the target clock, from the plurality of delayed clocks, and generating an up/down signal according to a length of a second section of the target clock and a length of a first section of the selected delayed clock;a duty-cycle control code generation unit suitable for generating a duty-cycle control code in response to the up/down signal;a duty-cycle adjusting unit suitable for generating a duty-cycle correction clock by adjusting the duty-cycle of a source clock according to the duty-cycle control code; anda control unit suitable for enabling the delayed clock generation unit during a duty-cycle correction period, and disabling the delayed clock generation unit during periods except for the duty-cycle correction ...