СИСТЕМА АВТОМАТИЧЕСКОЙ ПОДСТРОЙКИ ЧАСТОТЫ ПО ЗАДЕРЖКЕ

Изобретение относится к области цифрового синтеза частот. Достигаемый технический результат - уменьшение уровня паразитных сигналов. Система автоматической подстройки частоты по задержке содержит источник подстраиваемой частоты для генерации тактового сигнала, контроллер подстройки и выбора отвода, линию задержки, сконфигурированную таким образом, чтобы принять тактовый сигнал для генерации множества смещенных по фазе тактовых сигналов, первую схему выбора для приема множества смещенных по фазе тактовых сигналов и для выбора под управлением контроллера подстройки и выбора отвода, первой последовательности смещенных по фазе тактовых сигналов для генерации первого выходного сигнала, имеющего вторую частоту. Способ автоматической подстройки частоты по задержке содержит этапы: определяют первую частоту в качестве функции второй частоты, которая является требуемой частотой первого выходного сигнала, выводят, по меньшей мере, одно значение подстройки частоты для того, чтобы обусловить генерацию ...

ТАЙМЕР

Изобретение относится к устройствам времени и может найти применение в системах управления, контроля, измерения, вычислительных устройствах, устройствах связи различных отраслей техники. Таймер содержит однотактный D-триггер (3), управляемый посредством элементов И, ИЛИ, НЕ (2, 1, 6), а также линию задержки (4) на диоде (5) и RС-цепочке. Технический результат: устройство позволяет выдерживать выходной сигнал заданной длительности при поступлении импульсного входного сигнала. 1 ил.

Блок задержки импульсов

Предлагаемая полезная модель относится к измерительной технике, а именно к устройствам многоканальной программируемой цифровой задержки пускового импульса. Техническим результатом полезной модели является уменьшение погрешности времени задержки пускового импульса при заданной тактовой частоте в ПЛИС. Технический результат достигается тем, что в блоке задержки импульсов, содержащем канал пускового импульса, генератор, микроконтроллер, канал выходного импульса, ПЛИС, содержащую умножитель частоты, четыре триггеры, первый элемент И, первый счетчик задержки, первый счетчик длительности, регистр кода задержки, при этом генератор соединен с входом умножителя частоты, первый выход которого соединен с тактовым входом четырех триггеров и первых счетчиков задержки и длительности; канал пускового импульса соединен с входом второго триггера, выход которого соединен с входом третьего триггера и с первым входом первого элемента И, второй вход которого соединен с инверсным выходом третьего триггера, а ...

УСТРОЙСТВО ДЛЯ ЗАДЕРЖКИ СИГНАЛОВ

Использование: импульсная техника. Сущность изобретения заключается в том, что последовательные кванты задержки преобразуют в разрядные слова до максимальной задержки n = 4,8,16 за m операций, где m = log2n увеличивая за каждую операцию разрядность каждого слова в 2 раза, при этом частоту квантования понижают также в 2 раза, и обратное преобразование осуществляют коммутацией сигналов отдельных разрядов слоев с пропорционально пониженными частотами преобразования в трансформированном масштабе времени. 3 з.п.ф-лы, 4 ил.

УСТРОЙСТВО ДЛЯ ЗАДЕРЖКИ СИГНАЛОВ

Изобретение относится к области импульсной техники. Достигаемый технический результат - упрощение устройства и снижение уровня его помехоизлучаемости. Устройство для задержки сигналов содержит трехразрядный двоичный счетчик 1 импульсов, двунаправленные ключи 2, 3, 4, коммутирующие узлы 5, 6, 7, резистор 8, плюсовую шину 9 питания, общую шину 10 питания, выход 11, тактовый вход 12, вход 13 начальной установки. Технический результат достигнут введением двунаправленных ключей 2, 3, 4, резистора 8 и новых связей между элементами. 1 ил.

УПРАВЛЯЕМЫЙ ФОРМИРОВАТЕЛЬ ИМПУЛЬСОВ

Изобретение относится импульсной цифровой технике, предназначено для формирования выходных импульсов с требуемой длительностью по каждому из трех событий: по фронту сигнала на первом управляющем входе, по нулевому уровню сигнала от замыкающей кнопки с подавлением дребезга, при обнаружении пропуска импульса на импульсном входе сигнала. Технический результат заключается в расширении функциональных возможностей. Устройство содержит семь резисторов (1)-(7), два конденсатора (11), (18), кнопку (10), 1-й и 2-й управляющие входы (12), (13), импульсный вход (14), элемент И (17), элемент НЕ (8), два элемента И-НЕ (9)-(16), элемент НЕ с открытым коллекторным выходом (15), детектор огибающей импульсного сигнала (19). Устройство может быть использовано, например, в качестве формирователя импульсов системного сброса устройства программного управления. 1 ил.

УСТРОЙСТВО ДЛЯ ФОРМИРОВАНИЯ ИМПУЛЬСОВ

Устройство относится к импульсной цифровой технике и может использоваться для формирования выходных импульсов с требуемой длительностью по каждому из трех событий (при включении питания, по сигналу от замыкающей кнопки с подавлением дребезга, при обнаружении пропуска или “зависания” (прекращения изменения) импульсов входного импульсного сигнала, при разрешении обнаружения). Технический результат заключается в расширении функциональных возможностей устройства за счет формирования выходного импульса при включении питания и обеспечения возможности выполнения устройством функции аппаратного сторожевого таймера с разрешением формирования выходного импульса при пропуске или “зависании” импульсов входного импульсного сигнала. Устройство содержит первый и второй резисторы (1, 2), замыкающую кнопку (4), конденсатор (5), логический повторитель (6), выход инверсного импульсного сигнала, общую шину и шину источника питания. Устройство дополнительно содержит третий резистор (3), элемент И-НЕ (7), первый ...

УСТРОЙСТВО ДЛЯ ЗАДЕРЖКИ СИГНАЛОВ

Изобретение относится к области импульсной техники. Достигаемый технический результат - упрощение устройства и снижение уровня его помехоизлучаемости. Устройство для задержки сигналов содержит трехразрядный двоичный счетчик импульсов, двунаправленные ключи, коммутирующие узлы, резистор, плюсовую шину питания, общую шину питания, выход, тактовый вход, вход начальной установки. Технический результат достигнут введением двунаправленных ключей, резистора и новых связей между элементами.

Устройство задержки

Изобретение относится к импульсной технике, в частности к устройствам обработки информации, и может быть использовано в дешифраторах время-импульсных кодов. Цель - расширение функциональных возможностей за счет осуществление задержки сигналов, поступающих по двум входам. Устройство задержки содержит счетчик 1, датчик 2 кода, блок 3 памяти, формирователь 4 сигналов Запись-считывание, первый 5, второй 6, третий 10 и четвертый 11 элементы совпадения, элемент ИЛИ 12, инвертор 7, первый 8 и второй 9 D-триггеры, входные шины 13, 14, выходные шины 15, 16 и тякто- вую шину 17. Наличие инвертора 7 обеспечивает поочередное формирование управляющих сигналов, с помощью которых D-триггеры 8, 9 записывают разделенную информацию, поступающую с выхода блока 3 памяти. Поочередное подключение входных шин 13, 14 обеспечивает поочередное выполнение задержки. 2 ил.

Устройство для задержки импульсов

Устройство для формирования сигнала

Устройство для задержки импульсов

Генератор задержанных импульсов

Синхронизирующее устройство

Устройство для синхронизации импульсов

Система стабилизации задержки

Устройство синхронизации

Формирователь импульсов

Устройство задержки импульсов

Изобретение относится к импульсной технике, может использоваться в устройствах сравнения и селекции импульсов . Целью изобретения является повьшение точности и расширение области применения устройства путем повьшения быстродействия и возможности программирования задержки. Устройство содержит кодирующий блок 1, счетчик 2, счетный триггер 3, первое 4 и второе 5 запоминающие устройства (ЗУ) с произвольной выборкой, клеммы: входную 6, тактовых импульсов 7, выходную 8. Поставленная цель достигается введением ЗУ 5, При этом осуществляется чередование режимов работы первого и второго ЗУ с произвольной выборкой, что обеспечивает задержку любой последовательности импульсов с высокой точностью на время , задаваемое кодирующим блоком 1. 1 ил. i (П to о ю tc ...

Устройство выделения одиночного @ -го импульса

Изобретение может быть использовано в цифровой вычислительной тех-, нике, Устройство содержит вычитающий счетчик 1, триггеры 2-4, элементы 5 и 6 совпадения и элемент НЕ 7, Введение элемента 12 совпадения и триггера 13 расширяет функциональные возможности устройства за счет выделения первого импульса, 1 ют. (Л со со 00 о к ...

Устройство промежуточной памяти разравнивающего типа

Формирователь задержанных импульсов

ФОРМИРОВАТЕЛЬ ЗАДЕРЖАННЫХ ИМПУЛЬСОВ, сбдержащий входную шину двоичный счетчик, счетный вход которого соединен с шиной тактовых импульсов , а выходы - с входами дешифратора , входной RS-триггер, R-вход которого через элемент совпадения соединен с установочным входом двоичного счетчика, а инверсный выход входного RS-триггера подключен к второму входу элемента совпадения, о тличающийся тем, что, с целью расширения функциональных возможностей путем формирования выходньк импульсов длительностью, равной так- товым, и автоматического регулирования времени задержки, в него введены управляющие шины, элемент НЕ, группа элементов ЗАПРЕТ и элемент ИЛИ-НЕ, причем вькод элемента ИПИ-НЕ подключен к R-входу входного RS-триггера , входы элемента ШТИ-НЕ подключен к выходам элементов ЗАПРЕТ, у которых первые входы подключены к управляющим шинам, вторые входы соединены с соответствукн ими выхода (Л ми дешифратора, у которого стробирующий вход Через элемент НЕ подключен с к счетному входу двоичного счетчика ...

Аналого-цифровое устройство задержки

АНАЛОГО-ЦИФРОВОЕ УСТРОЙСТВО ЗАДЕРЖКИ, содержащее масштабный блок, вход которого является входом устройства, п-разрядный аналого-цифровой преобразователь, вход которо го соединен с выходом масштабного блока, п регистров сдвига, входы которых соединены с выходами аналого-цифрового преобразователя, генератор тактовых импульсов, подключенный выходом к тактовым входам регистров сдвига, цифроаналоговый преобразователь, отличающееся тем, что, с целью расширения области .применения за счет возможности получения плавной перестройки времени задержки по закону, близкому к линейному, и возможности изменения скорости перестройки задержки, в него введены п мультиплексоров, распределитель импульсов и делитель частоты с переменным коэффициентом деления, вход которого соединен с выходом генератора тактовых импульсов , а выход соединен с входом распределителя импульсов, выход которого соединен с управляющими входами мультиплексоров, информационные выходы которых соединены с разрядными вькодами регистров ...

Программируемый таймер Димитраки-Урсу

Изобретение относится к области приборостроения и может быть использовано в. качестве устройства для генерирования точных интервалов времени различной длительности в течение суток. Цель изобретения - расширение функциональных возможностей и повышение надежности управления исполнительным органом. Таймер содер- жит электронные часы 1, согласующие по уровню сигнала логические элементы 2, постоянно-запоминающие устрой- . ства 3, 4 и 5, счетчик 6 импульсов , коммутирующий триггер 7, ключ 8 напряжения, токовый ключ 9 и исполнительный орган 10. Компаратор кодов выполнен из двух постоянных запоминающих устройств. Дост1-1жению с fB поставленной цели способствует введение в устройство логических элемен л тов , счетчика импульсов, коммутирующего триггера, токового ключа и клю- ча напряжения. I ил. ел ...

Устройство для регулируемой задержки импульсов

Формирователь импульсов

Устройство задержки

Устройство для формирования апериодической последовательности импульсов

Устройство задержки

Изобретение относится к импульсной технике и может быть использовано для построения устройств задержки как непрерывной последовательности импульсов, так и одиночных импульсов без искажения их длительности. Цель - расширение диапазона величины задержки. Устройство задержки содержит генераторы 1,2 пилообразного напряжения, нормально разомкнутые ключи 3.4, два компаратора 5,6, входную и выходную шины 7,8, шину 9 управления временем задержки, триггер 10, элемент 11 запрета, инвертор 12. Раздельная задержка переднего и заднего фронтов входного импульса с помощью генераторов 1,2 пилообразного напряжения, компараторов 5,6 обеспечивает достижение поставленной цели , при этом длительность выходного иМ- пульса равна длительности входного. 2 ил.

Устройство преобразования входного сигнала для синхронизации однотактных устройств с разбитыми на группы элеметами памяти

Устройство для задержки импульсов

Дискретная линия задержки

... 1. даСКРЕТНАЯ ЛИНИЯ ЗАДЕРЖКИ, содержащая первый блок управления, вход которого объединен с одним из входов элемента И и подключен к выходу генератора, а выход соединен с входом первого счетчика импульсов, запоминающее устройство, информационный вход которого подключен к дополнительному выходу блока управления , вход управления считыванием объединен с выходом второго счетчика импульсов и подключен к выходу дискретной линии задержки, а вход управления записью объединен с. дополнит тельным входом блока управления и подключен к входу дискретной линии .задержки, а также третий счетчик импульсов , вход установки которого соединен с выходом датчика кода, а выход подключен к входу триггера, выход которого соединен с другим входом элемента И, отличающаяся тем, что, с целью повышения точности, в нее введен дополнительньй блок управления, вход которого соединен с выходом элемента И, выход - с входом второго счетчика импульсов, вход синхронизации соединен с информационным выходом запоминающего устройства ...

Устройство задержки сигналов

УСТРОЙСТВО ЗАДЕРЖКИ СИГНАЛОВ по авт. св. № 944094, отличающееся тем, что, с целью расширения функциональных возможностей устройства за счет формирования из пачки импульсов с произвольной длительностью между импульсами пачки импульсов с длительностью между импульсами , определяемой задержкой устройства с одновременным исключением потери импульсов во время задержки, оно дополнительно содержит пороговый элемент, последовательно соединенные реверсивный счетчик , дешифратор и элемент И, выход которого соединен с управляющим электродом тиристора запуска, зарядный конденсатор через пороговый элемент соединен со вторым входом элемента И, шина прямого счета реверсивного счетчика соединена с входной шиной устройства, а шина обратного счета- с выходной шиной устройства.

Диапазонный делитель частоты

Ячейка временной задержки импульсов

Формирователь одиночных импульсов

Устройство задержки

Селектор импульсов по длительности с задержкой

Изобретение относится к импульсной технике и может быть использовано в устройствах автоматики, телемеханики и вычислительной техники. Целью изобретения является обеспечение возможности независимой установки порога селекции и времени задержки . Селектор импульсов по длительности с задержкой содержит входную шину 1, элементы НЕ 3 и 9, элементы И-НЕ 4 и 6, генератор 5 импульсов , счетчик 11 импульсов, выходную шину 12, триггер 13, шину 16 предварительной установки. Цель достигается за счет ведения формирователей 2 и 14 коргтних импульсов, элемента И-НЕ 7, элементов И 10 и 15 и образования новых функциональных связей. 2 ил.

Управляемая линия задержки импульсных радиосигналов

Устройство для синхронизации импульсов

Устройство задержки импульсов

... 1. УСТРОЙСТВО ЗАДЕРЖКИ ИМПУЛЬСОВ, содержащее инерционное звено, компаратор и формирователь, вход которого является входом устройст а , выход подсоединен к входу инерционного звена, а выход компаратора является вьгходом устройства, отличающееся тем, что, с целью расширения функциональных возможностей за счет формирования случайной задержки с регулируемыми статистическими параметрами, в него, введены три ключа, генератор случайного напряжения и блок сигналов коммутации , выходы которого подключены к управляющим входам соответствувощих ключей, основной вход первого ключа подсоединен к выходу инерционного звена, а выход - к первому входу компаратора , выход которого подсоединен к первому входу блока сигналов коммутации , второй вход которого подсоединен к выходу формирователя, а третий вход- является управляющим, основ ной вход второго ключа подсоединен к прямому выходу генератора случайного напряжения, инверсньй выход которого подсоединен к основному входу третьего ключа, выход которого соединен ...

Устройство для синхронизации импульсов

УСТРОЙСТВО ДЛЯ СИНХРОНИЗАЦИИ ЛМПУЛЬСОВ, содержащее триггер , элемент совпадения и два элемента задержки, выход первого из которых соединен с / -входом триггера, отличающееся тем, что, с целью повышения его надежности и расширения функциональных возможностей , С-вход триггера соединен с выходом элемента совпадения, первый вход которого подключен к входной шине, а второй соединен с выходом первого элемента задержки, вход которого подключен к шине синхронизирующих импульсов, а инверсный выход триггера через второй элемент задержки соединен с третьим входом элемента совпадения.

СИНХРОНИЗИРУЮЩЕЕ УСТРОЙСТВО

Формирователь импульсов

Изобретение может быть использовано в интегральных схемах динамического типа на ЬЩП - транзисторах. Целью изобретения является повышение быстродействия формирователя и расширение области его применения. Формирователь содержит шину 1 питания, общую шину 2, входы: выключения 3 и 4, инверсный включения 5, прямой включения 6, прямой адресный 7, инверсный адресный 8, подброса 9, перезаряда 10, удержания 11, бутстреп- ный 12, подготовки 13; выходные шины: первую 14, вторую 15; транзисторы: включения 16 и 24, включения 17 и 25, проходной 18, ключевые 19 и 27, адресные 20, 22, 28 и 30, перезаряда 21 и 29, входные 23 и 31, проходной 26, удержания 32, подготовки 33, бутстрепный 34; конденсаторы: управляющие 35 и 36, выходной 37. Расширение области применения достигается за счет введения второй выходной шины 15, что позволяет использовать формирователь без дополнительного блока селекции сигнала при получении сигнала по двум шинам. Формирователь предпочтительно использовать для формирования сигнала ...

Устройство задержки широтно-импульсного сигнала

Устройство задержки

Устройство для синхронизации импульсов

Устройство для задержки импульсов

Дисретная линия задержки

Линия задержки

Цифровая регулируемая линия задержки

Изобретение относится к импульсной технике и может использоваться в устройствах обработки дискретной информации с повышенной помехозащищенностью. Цель - повышение надежности устройства - достигается путем исключения возможности формирования искаженного по длительности выходного импульса в случае совпадения во времени моментов окончания входного и начала формирования выходного импульсов. Цифровая регулируемая линия задержки содержит триггер 1, генератор 2 тактовых импульсов, элемент 3 задержки, инвертор 4, элемент ИСКЛЮЧАЮЩЕЕ ИЛИ 5 и счетчик 6, соединенные соответствующим образом между собой, и формирует на выходе задержанную последовательность импульсов, неискаженных по длительности, очищенную от помех, типа "провал", а также от помех, длительность которых не превышает установленного времени задержки Τз. При этом на C-входе счетчика 6 формируется стандартный по длительности импульс, достаточный для надежной записи кода числа K с 1-го по 2N - 1-й разряд счетчика 6 с кодовой шины 8 и уровня ...

Устройство задержки

Изобретение относится к области цифровой обработки сигналов. Цель изобретения - увеличение быстродействия за счет уменьшения времени перестройки на величину задержки. Устройство содержит блок 1 оперативной памяти , цифровой ключ 2, генератор 3 тактовых импульсов, счетчик 4 адреса, регистр 5 управления величиной задержки и вычитатель 6. В устройстве задержки реализовано временное разделение режимов работы блока 1 временной памяти. В течение первого полупериода (нулевое состояние на вЕаходе генератора 3 тактовых импульсов) происходит запись входного сигнала, а в течение второго полупериода (единичное состояние на выходе генератора 3 тактовых импульсов) - считывание задержанного сигнала из блока 1 оперативной памяти, информационный выход которого является выходом устройства задержки. В описании даны временные диаграммы, пояснякицие работу устройства . 2 ил. 9 1C ГС tsS OQ Фиг, 1 ...

Устройство задержки

Формирователь парных импульсов

Распределитель импульсов

Устройство калибровки временной развертки электроннооптических фоторегистраторов

Устройство задержки

Программное устройство для выдачи импульсных команд

Распределитель импульсов

Формирователь импульсов

Полупроводниковое устройство задержки

Бесконтактное реле времени

PEЛE BPEMEHИ

GENERATOR OF PAIR PULSES

Устройство задержки импульсов

Входное устройство счетчика импульсов

Устройство управляемой задержки импульсов

Изобретение относится к импульсной технике и может быть использовано в телеметрии, измерительной и вьмиспительной технике. Цель изобретения - расширение области применения - достигается за счет возможности работы с нулевыми кодами задержки . Другая цель - повышение надежности - достигается за счет сокращения количества схемных элементов и блокировки устройства при несоответствии длительности входного сигнала выбранному диапазону задержки. Устройство содержит триггеры 1 и 2, D-триггер 3, формирующий триггер 4, элементы И 5-9, элементы ИЛИ 10-13, элементы НЕ 14 и 15, генератор 16 тактовых импульсов, счетчик 17, вход 18 устройства, шины 19 кода, выходную шину 20. С помощью кода, подаваемого на шины 19, осуществляется дискретное управление выбором величины задержки выходного импульса. При подаче на эти тины нулевого кода устройство переключается в исходное состояние. 2 ил. S (Л О СП о оо фае1 ...

Синтезатор дискретных прецизионных задержек импульсных сигналов

Нуль-орган

Линия задержки

Реле времени

Реле времени относится к элементам автоматики и может быть использовано, например , в машиностроении в качестве формирователя временных интервалов при управлении технологическими процессами. Цель изобретения - расширение диапазона формируемых выдержек времени. Реле времени содержит источник опорных последовательностей импульсов (ОПИ), первый вход которого подключен к входу схемы выделения первого импульса первого разряда и второму входу схемы И, первый вход которой подключен к выходу управляемого од- новибратора, времл выдержки которого определяется цепью RiCi, а вход запуска подключен к выходу ыделения первого импульса . Выход схемы И первого разряда реле времени подключен к входу схемы выделения импульса второго разряда, с выхода которой сигнал поступает на запускающий вход управляемого одновибратора второго разряда и на первый вход схемы ИЛИ, на второй вход которой поступает сигнал с второго выхода источника ОПИ. Выход схемы ИЛИ подключен к второму входу схемы И второго разряда. Выход ...

Устройство для разделения и синхронизации сигналов

Изобретение может быть исполь- зовано для синхронизации сигналов, имеющих дребезг при изменении уровня активности. Цель изобретения - повышение помехоустойчивости. Устройство содержит мультиплексор 1, счетчик 3 импульсов, дешифратор 4, инвертор 6, элемент И 7 и D-триггер 8. Введение элемента И 10 и D-триггера 9 исключает влияние дребезга на фронтах входного информационного сигнала. 2 ил. Г 2 2 ; г 3 If S 6 7 8 п ...

Датчик временных интервалов

Изобретение может быть использовано для формирования временных интервалов , величина которых изменяется во времени . Цель изобретения - расширение функциональных возможностей устройства. Датчик содержит RS-триггеры 1 и 6, элемент И 3, 8 и 14, одновибратор 4, генератор 5 импульсов и счетчик 10. Введение счетчика 11, дешифраторов 12 и 13, элементов ИЛИ 2, 7 и 9 и образование новых функциональных связей обеспечивает формирование двух линейно изменяющихся интервалов времени, один из которых убывает , а другой возрастает. 2 ил. со ND ГС 4 СО СХ) ...

Аналого-цифровое устройство задержки

АНАЛОГО-ЦИФРОВОЕ УСТРОЙСТВО ЗАДЕРЖКИ, содержащее п цифроаналоговых преобразователей, выходы которых являются выходами устройства задержки, отличающееся тем, что, с целью расширения функциональных возможностей устройства задержки за счет обеспечения управления величиной задержки нескольких независимых аналоговых сигналов, в него введены преобразователь напряжение - частота, два счетчика, два дешифратора, R5-триггер, элемент 2 ИЛИ, мультиплексор, аналого-цифро вой преобразователь, оперативное запоминающее устройство, п элементов 2 И и п регистров, выходы которьк соединены с соответствующими входами соответствующих цифроаналоговых преобразователей, информационные входы - с соответствуюыщми выходами оперативного запоминающего :устройства, а С-входы - с выходами ;соответствующих элементов 2 И, при ,чем D -входы оперативного запоминающего устройства соединены с соот- , ветствующими выходами аналого-цифрового преобразователя, С-вход - с выходом элемента 2 ИЛИ, вход управления режимом работы с ...

Устройство для задержки видеосигналов

... 1. УСТРОЙСТВО ДЛЯ ЗАДЕРЖКИ : ВИДЕОСИГНАЛОВ, содержащее формирующий триггер, входной дифференцирую-щий элемент, вход которого подключен к первому входу устройства, а выход соединен .с объединенными входами первого и второго блоков ограничения амплитуды сигналов, выходы KOTOjaix соединены с первыми входами соответственно первого и второго узлов задержки , вторые входы которых объединены и подключены к второму входу . устройства, а их выходы подключены к соответствующим входам формирующего триггера, отлич-ающе ес я тем, что,, с цельна расширения функциональных возможностей путем обеспечения возможности управляемой . задержки видеосигналов с амплитудноимпульсной модуляцией, в него введены первый и второй блоки выделения маркера, блок раскоммутации каналов, К блоков памяти, К элементов И, элемент ИЛИ и блок раскоммутации иитульсов , к выходов которого подключены к. вторым входам соответствукааих элементов И, первые входы котогялх соединены с выходами соответствующих блоков па.мяти, а выходы ...

Устройство задержки импульсов

УСТРОЙСТВО ЗАДЕРЖКИ ИМПУЛЬСОВ , содержащее последовательно соединенные формирователь коротких импульсов по переднему фронту входного сигнала и элемент ИЛИ, другой вход которого соединен с тактовым входом устройства, а вход этого формирователя подключен к входу устройства , регистр сдвига, соединенный своим выходом с выходом устройства, отличающееся тем, что, с целью повышения стабильности времени задержки, в него введен тактируемый D-триггер, информационный вход которого подключен к входу устройства, тактовый вход к выходу элемента ИЛИ, а выход соединен с информационным входом регистра (Л сдвига, подсоединенного своим тактовым входом к тактовому входу.устройства .

Устройство регулируемой задержки импульсов

Изобретение относится к импульсной технике и может быть использовано для формирования регулируемой задержки импульсов в широком диапазоне. Цель изобретения - увеличение диапазона регулируемой задержки при одновременном повышении точности - достигается за счет дополнительного введения в состав устройства триггеров 5-7, счетчиков 8,9, элементов И-НЕ 10,11, элементов ИЛИ-НЕ 12-15, генератора 16, формирователя 17. Кроме того, устройство содержит компаратор 1, делитель 2 напряжения, времязадающую RC-цепь 3, триггер 4, входную 18 и выходную 19 шины. Устройство обеспечивает, по сравнению с прототипом, при одних и тех же значениях параметров RC-цепи увеличение в Кд раз времени задержки импульсов, где Кд - коэффициент деления счетчика 8. При этом формируемая задержка не зависит от значения частоты генератора 16, т.е. требования к параметрам генератора могут быть ослаблены при обеспечении высокой точности работы устройства в целом. 1 ил.

Устройство для задержки импульсов

Линия задержки

Изобретение относится к микроэлектронике и вычислительной технике, а именно к схемам линий задержки, широко применяемым для обеспечения синхронизации между электронными системами различного назначения. Целью изобретения является повышение надежности и точности задания величины задержки. Линия задержки имеет п ячеек задержки, каждая из которых содержит выходной инвертор, первый и второй времязадающие конденсаторы. В каждую ячейку введены элемент 2ИЛИ-НЕ, элемент 2И с прямым и инверсным входами, первый и второй переключатели тока, шина опорного напряжения, двойной инвертор с прямым и инверсным выходами, элемент НЕ, первый и второй транзисторы, первый и второй диоды, первый и второй резисторы. По сравнению с прототипом, имеющим навесные времязадающие конденсаторы в каждой ячейке линии задержки, предлагаемое устройство содержит два времязадающих конденсатора на всю линию задержки, один из которых осуществляет задержку фронта входного сигнала, а другой - задержку среза . 2 ил. (Л ...

Цифровое устройство для задержки импульсов

Использование: область автоматики и вычислительной техники, а именно устройства для задержки прямоугольных импульсов на основе цифровых элементов. Предлагаемое устройство позволяет сочетать реализацию задержки как меньше, так и больше длительности задерживаемых импульсов вплоть до больших величин задержки (от единиц мксек до единиц сек и более) с точностью, определяемой частотой заполнения и стабильностью воспроизведения длительности задерживаемых прямоугольных импульсов. Целью изобретения является повышение точности воспроизведения задерживаемых импульсов, в частности, когда эта деятельность на несколько порядков меньше времени задержки. Указанная цель достигается тем, что триггер, формирующий задержанный прямоугольный импульс , запускается в момент окончания импульса, длительность которого равна заданной задержке, а сбрасывается - в момент возврата в состояние О реверсивного счетчика в процессе обратного счета тактовых импульсов, записанных этим счетчиком при прямом счете в течение длительности ...

Устройство задержки

Использование: в микроэлектронике и вычислительной технике, для замедления скорости передачи данных и обеспечения синхронизации при обмене между подсистемами памяти и процессорными логическими схемами. Целью изобретения является упрощение устройства задержки, повышение точности длительности задержания импульса, увеличение диапазона задержки , Сущность: в устройство, содержащее два элемента задержки и вре- мязадающий конденсатор, введены первый, второй и третий инверторы, вентильная схема 2И-2ИЛИ, первый и второй генераторы тока, первый, второй, третий, четвертый резисторы , шина опорного напряжения. Подключение времязадающего конденсатора к первому и второму инверторам позволяет коммутировать времязадающий конденсатор на каждый фронт импульса поочередно к первому и второму элементам задержки устройства.2 ил.

Устройство задержки импульсов

Устройство задержки импульсов относится к импульсной технике и предназначено для задержки прямоугольных импульсов. Устройство содержит интегрирующий элемент 1, триггер 2, операционный усилитель 3, диод 4, элемент ИСКЛЮЧАЮЩЕЕ ИЛИ 5. источник 6 тока, резистор 7, входную и выходную шины 8 и 9. 1 з.п. ф-лы, 3 ил, ...

Генератор парных импульсов

Использование: импульсная техника, системы управления. Сущность: генератор парных импульсов содержит счетчик, элемент равнозначности, входную и выходную шины, D-триггер. С целью расширения области применения путем обеспечения уп,- равления как длительностью выходных импульсов, так и их паузой пропорционально амплитуде управляющего напряжения, введены преобразователь напряжения в код, одновибратор, первая и вторая линии управления, а счетчик использован реверсивный . 1 ил.

Устройство для выравнивания времени задержки при многодорожечной записи на магнитной ленте"

Формирователь импульсов

Изобретение может быть использовано в радиоизмерительной технике. Формирователь содержит элемент И 3, 1 блок 7 задержки, элемент ИЛИ 10, элемент НЕ 13. В устройство введены элементы И 4, 15 и 16, генератор (г) 5 импульсов, делитель 6 частоты, блок 8 задержки, сумматоры 9 и 11 по модулю два, элемент НЕ 14. Благодаря этому повышается точность работы и расширяется диапазон длительности формируемых импульсов. Разница между длительностями сформированного импуль са, вызванная несинхронностью работы Г, определяется только периодом (частотой ) выходного сигнала Г 5 и будет тем меньше, чем вьш1е частота Г 5. 3 ил. 12 г 15 17 (Л ...

Устройство постоянного запаздывания

Формирователь временных интервалов

Изобретение может быть использовано в устройствах а втоматики и вычислительной техники. Целью изобретения является расширение функциональных возможностей. Для достижения цели в формирователь временных интервалов введен элемент ШШ 6. Форьшрователь временных интервалов также содержит формирователь 1 импульсов, генераторы 2, 5 импульсов, делители 3, 7 частоты, ключи 4, 8, Данный формирователь позволяет управлять длительностью формируемого интервала его цифровым кодом, а также управлять длительностью формируемого временного интервала в пределах периода генератора 5 изменением коэффициента деления только делителя 3 частоты при постоянном коэффициенте деления, ю делителя 7 частоты, 2 ил. (Л ...

Устройство задержки последовательнос-Ти иМпульСОВ

Устройство для синхронизацииСигНАлОВ

Устройство выделения первого импульса и вычитания первого импульса из последовательности импульсов

Устройство задержки импульсов

Устройство задержки

Изобретение относится к импульсной технике и может использоваться в радиолокации. Цель изобретения - повышение надежности за счет исключения сбоев, возникающих при обращении к последним ячейкам некоторых блоков ОЗУ, в момент формирования сигнала "Установка" времязадающим блоком. Устройство содержит фазосдвигающий блок, времязадающий блок, счетчик, N регистров, блок формирования сигналов "Запись-считывание", блок памяти, содержащий оперативных запоминающих устройств, элемент ИЛИ. Устройство позволяет задержать сигналы длительностью Τи/Τ с высокой точностью. Задержка осуществляется путем разделения входной информации на M потоков, сдвинутых относительно друг друга на время T=Τ/M. В каждом потоке информация запоминается, хранится и считывается через время, формируемое времязадающим блоком. Введение регистров позволяет исключить сбои. Регистры перебирают адресные ячейки блока памяти, на входы которого подаются тактовые импульсы, задержанные друг относительно друга на Τ/M. С выхода блока памяти ...

Устройство для задержки фронтов импульсных сигналов

Изобретение относится к импульсной технике и может быть использовано в устройствах для формирования задержек фронтов импульсных сигналов в управляющих устройствах систем передачи и обработки информации. Цель изобретения - увеличение стабильности формируемых задержек - достигается за счет сокращения времени подготовки устройства. Для этого в устройство введены ключ отрицательной обратной связи и два резистора смещения. На чертеже показаны входной ключ 1 с открытым коллектором, пороговый элемент 2 с релейной переходной характеристикой, ключ 3 отрицательной обратной связи, интегрирующая RC-цепь 4, резисторы 5,6 и 7, вход 9 устройства, шина 10 питания. 1 ил.

Устройство для формирования синхронизированных импульсов

УСТЮЙСТВО ДЛЯ ФОРМИРОВАНИЯ СИНХРОНИЗИРОВАННЫХ ИМПУЛЬСОВ, содержащее инвертор, два элемента И-ИЛИ, Два синхронных триггера, тактовые входа которых, объединены с входной тактовоЯ шиной устройства, первые входы первого и второго элементов и первого элемента И-мли соединены с управляющим входом каждого из синхронных триггеров, второй вход первого элемента И первого элемента,ИгИЛИ и первый вход первого) элемента И второго элемента И-Ш1И соединены с инверсным выходом первого синхронного триггера, прямой выход которого подключён к второму входу второго элемента И первого элемента И-ИЛИ и к первому входу второго элемента И второго элемента И-ИЛИ, третий вход второго элемента И первого элемента И-ИЛИ и второй вход второго 3JieMeHта и второго элемента И-ИЛИ соединен с инверсным выходом второго синхронного триггера,прямой выход которого соединен с третьим входом первого элемента И первого элемента Й-ИЛИ и с вторым входом первого элемента И второго элемента .И-ИЛИ, о т л и ч а «о щ ее с я тем, чтоf ...

Устройство задержки импульсов

Формирователь прямоугольных импульсов

Устройство для задержки импульсной последовательности случайной длины на время ее длительности

Устройство для синхронизации импульсов

Устройство для задержки импульсов

Устройство задержки

Изобретение, относится к импульсной технике, является дополнительным к авт. ев. № 519855 и может быть использовано для формирования высокостабильных интервалов времени в аппаратуре автоматики, телемеханики, измерительной технике. Цель изобретения - повышение стабильности формируемых временных интервалов путем компенсации дестабилизирующего влияния внутреннего сопротивления триггера (ТГ). Устройство содержит ТГ 1, установочный вход которого является запускающим входом устройства, времязадающую КС- цепь 2j состоящую из резистора 3 и конденсатора 4, делитель напряжения 5, состоящий из резисторов 6 и 7. К выходам времязадающей RC-цепи 2 и делителя напряжения 5 подключены входы компаратора напряжений 8, выход которого соединен с входом сброса ТГ 1. Времязадакщая RC-цепь 2 и делитель 5 включены между входами ТГ 1. Новым техническим решением, обеспечивающим достижение поставленной цели , в данном устройстве является подключение параллельно времязадакнцей RC-цепи 2, цепи 9 из резистора 10 и диода ...

System, method and apparatus for an open loop calibrated phase wrapping phase modulator for wideband rf outphasing/polar transmitters

A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.

1 to 2n-1 fractional divider circuit with fine fractional resolution

A fractional divider has been provided that allows for division ratios of 1:1 to 1:2 N-1 with fine fractional resolution. To accomplish this, a phase blender (which is under the control of a state machine) is used to “blend” or interpolate consecutive phases of a clock signal from a delay locked loop to achieve a low deterministic jitter, while a sigma delta modulator can also be used to maintain low deterministic jitter while achieving the desired frequency resolution.

Fine-grained Clock Skew Tuning in an Integrated Circuit

An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.

Semiconductor integrated circuit

Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state.

Circuit and method for delaying signal

A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal.

Apparatus and system of implementation of digital phase interpolator with improved linearity

An apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first precharge transistor coupled to the first intermediate node, wherein the precharge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second precharge transistor coupled to the second intermediate node, wherein the second precharge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first precharge transistor and the second precharge transistor.

Adjustable capacitance structure

A capacitance structure comprises a plurality of metal oxide silicon (MOS) capacitors. A first end of each MOS capacitor of the plurality of MOS capacitors is coupled together at an effective node. A second end of each MOS capacitor of the plurality of MOS capacitors is configured to receive a respective different signal. Each first end of each MOS capacitor of the plurality of MOS capacitors thereby functions as an input end of a capacitor with a capacitance value determined based on the respective different signal. An effective capacitance value thereby results at the effective node.

Aging degradation diagnosis circuit and aging degradation diagnosis method for semiconductor integrated circuit

Provided is an aging degradation diagnosis circuit, including: a first delay circuit including a gate array for allowing aging degradation to progress, the first delay circuit being configured to delay an input signal and output a first output signal; a second delay circuit including a gate array having the same number of stages as the first delay circuit, the second delay circuit being configured to delay an input signal and output a second output signal; and an arbitrary delay unit, which is capable of varying a delay period in the second delay circuit by a predetermined amount. A delay comparison unit outputs comparison information obtained by relatively comparing delays between the first output signal and the second output signal. An adjustment unit uses the comparison information, to thereby readjust the delay period in the second delay circuit.

Fractional and integer pll architectures

A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Frequency-agile strobe window generation

The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.

Integrated Circuit With an Adaptable Contact Pad Reconfiguring Architecture

An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation.

Polyphase clock generator

A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.

Pulsed level gauge system with controllable delay path through selected number of delay cells

A level gauge system comprising transmission signal generating circuitry for generating a transmission signal; a propagation device connected to the transmission signal generating circuitry and arranged to propagate the transmission signal towards a surface of the product inside the tank, and to return a reflected signal resulting from reflection of the transmission signal at the surface of the product contained in the tank. The level gauge system further comprises reference signal providing circuitry configured to provide a reference signal. At least one of the transmission signal generating circuitry and the reference signal providing circuitry comprises delay circuitry. The delay circuitry comprises a plurality of delay cells, and controllable switching circuitry arranged and configured to allow formation of a delay path comprising a subset of the plurality of delay cells connected in series, to thereby allow control of a signal propagation delay of the delay circuitry.

Pulsed level gauge system with supply voltage controlled delay

A level gauge system comprising transmission signal generating circuitry for generating a transmission signal; a propagation device connected to the transmission signal generating circuitry and arranged to propagate the transmission signal towards a surface of the product inside the tank, and to return a reflected signal resulting from reflection of the transmission signal at the surface of the product contained in the tank. The level gauge system further comprises reference signal providing circuitry configured to provide a reference signal. At least one of the transmission signal generating circuitry and the reference signal providing circuitry comprises delay circuitry. The delay circuitry comprises at least one delay cell exhibiting a propagation delay for pulses passing through the at least one delay cell that varies in dependence of a supply voltage provided to the at least one delay cell, and voltage control circuitry connected to the at least one delay cell.

PHASE INTERPOLAR, RECEPTION CIRCUIT AND INFORMATION PROCESSING APPRATUS

A third periodic signal is synthesized using a first output signal having a phase corresponding to a first periodic signal and a second output signal having a phase corresponding to the second periodic signal. A value of the third periodic signal is detected at a timing of the phase of the delayed first periodic signal. The value of the third periodic signal detected with the delayed first periodic signal is compared with the value of the third periodic signal detected by the first periodic signal delayed by the different delay amount. The delay amount is obtained for the detected third periodic signal being a maximum or a minimum. In a state of the optimum delay amount, an amplitude of the third periodic signal is adjusted so that the detected value of the third periodic signal falls within a predetermined range. 1. A phase interpolator comprising:a first signal generation circuit that generates a first output signal that has a phase corresponding to a phase of a first periodic signal that has been input;a second signal generation circuit to which a second periodic signal having a phase different from that of the first periodic signal is input, the second signal generation circuit generating a second output signal that has a phase corresponding to a phase of the second periodic signal;a third signal generation circuit that generates a third periodic signal by synthesizing the first output signal and the second output signal;a delay circuit that provides a variable delay amount to the first periodic signal;a detection circuit that detects a value of the third periodic signal at a timing corresponding to the phase of the first periodic signal that is delayed by the delay circuit;an optimum delay amount obtaining circuit that compares the value of the third periodic signal detected by the detection circuit according to the first periodic signal that has the delay amount with the value of the third periodic signal detected by the detection circuit according to the ...

UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL

Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell. 1. A delay cell for a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) , the delay cell comprising:a delay stage configured to provide an output signal having a programmable delay through the delay cell, the delay cell having (i) a selectable delay value from a plurality of delay values, (ii) a selectable skew value of a rise time and fall time of an output signal of the delay cell, and (iii) relatively uniform cell size and terminal layout over a range of the plurality of delay values and the range of the plurality of skew values;an input inverter stage comprising a PMOS and NMOS transistor pair, the input inverter stage configured to transfer an input signal of the delay cell to the delay stage;an output inverter stage configured to generate a selectable drive strength for the output signal from the delay stage, thereby to provide an output signal of the delay cell as a delayed version of the input signal of the delay cell; M series-coupled inverter stages driven between first and ...

INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION

Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern. 1. A method of operation of an integrated circuit device , the method comprising:transmitting, from a first integrated circuit device, a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference;transmitting, from the first integrated circuit device, a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference; andgenerating a timing offset for transmitting data from the first integrated circuit device, wherein the timing offset is derived from information received from a second integrated circuit device sampling the differently-delayed rising edge transitions of the first calibration pattern and the differently-delayed falling edge transitions of the second calibration pattern.2. The method of claim 1 , wherein generating the timing offset comprises:determining a first timing location with respect to the timing reference based at least on the sampled differently-delayed rising edge transitions;determining a second timing location with respect to the timing reference based at least on the sampled differently-delayed falling edge transitions;computing a third timing location by averaging the first timing location and the ...

Critical-path circuit for performance monitoring

An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.

DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME

A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal. 125-. (canceled)26. A delay circuit comprising:a pulse generation unit configured to synchronize an input signal with a clock, and generate a pulse signal which is activated in response to the synchronized input signal and has a pulse width corresponding to delay information; andan output unit configured to activate a final output signal in response to a deactivation of the pulse signal.27. The delay circuit of claim 26 , wherein the pulse generation unit comprises:a synchronization section configured to synchronize the input signal with the clock;at least one shift section configured to sequentially shift the synchronized input signal;a selection section configured to select one output signal of the at least one shift section in response to delay information; anda latch section configured to activate the pulse signal in response to the synchronized input signal and deactivate the pulse signal in response to an output signal of the selection section.28. The delay circuit of claim 27 , wherein the latch section comprises an SR latch.29. The delay circuit of claim 26 , wherein the output unit is configured to output the final output signal by performing a logic operation on the clock and the pulse signal.30. The delay circuit of claim 26 , wherein the output unit comprises:a pass gate configured to transfer the pulse signal in response to the clock;an inverter configured to invert the pulse signal; anda logic gate configured to perform an AND operation on an output signal of the pass gate and an output signal of the inverter and output the final output signal.31. A method for driving a delay circuit comprising first and second delay units claim 26 , which receive ...

Signal delay circuit and signal delay method

A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Semiconductor device

A semiconductor device includes a first signal delay block configured to delay a first edge of an input signal with varying delay amounts, maintain a second edge of the input signal, and output at least one first driving signal, a second signal delay block configured to delay the second edge of the input signal with the varying delay amounts, maintain the first edge of the input signal, and output at least one second driving signal, and an output pad driving block configured to drive a data output pad with a first voltage in response to the first driving signal and drive the data output pad with a second voltage in response to the second driving signal.

FAILURE DETECTOR CIRCUIT AND ASSOCIATED METHOD

A failure detector circuit for detecting status of a protected circuit, the failure detector circuit having an operating cycle, has an enabling signal generator, a comparator circuit, a delay circuit. The enabling signal generator enables the comparator for an enable time in each operating cycle. The comparator circuit compares an output of the protected circuit with a reference signal. The delay circuit receives an output signal of the comparator to decide whether a failure occurred within a give delay time. 1. A failure detector circuit for detecting status of a protected circuit , the failure detector circuit comprising:an enabling signal generator, generating a periodic enabling signal which has an operating cycle, configured to indicate an enable time in every operating cycle;a comparator circuit, having an enabling terminal, two input terminals and an output terminal, wherein the enabling terminal is configured to receive the enabling signal, and wherein the two input terminals are configured to respectively receive an output signal from the protected circuit and a reference signal, and wherein the output terminal is configured to provide a comparative result signal according to the enabling signal, the output signal and the reference signal; anda delay circuit, receiving the comparative result signal and detecting the comparative result signal for a given delay period, generating a delay signal according to the comparative result signal, wherein the given delay period is larger than the operating cycle.2. The failure detector circuit according to claim 1 , wherein the enabling signal is a square wave signal.3. The failure detector circuit according to claim 2 , wherein the active state of the enabling signal is in high level.4. The failure detector circuit according to claim 1 , wherein the enable time is 1% of the operating cycle.5. The failure detector circuit according to claim 1 , wherein the comparative result signal is set to high level out of the ...

DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS

Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals. 1. A phase inverter , comprising:an odd number of first inverters coupled in series between a first input and a first output, the odd number of first inverters having a collective propagation delay from the first input to the first output that is equal to a first delay value; andan even number of second inverters coupled in series between a second input and a second output, the second input being isolated from the first input, the even number of second inverters having a collective propagation delay from the second input to the second output that is equal to a second delay value, the second delay value being substantially equal to the first delay value.2. The phase inverter of claim 1 , wherein an inverter of the odd number of first inverters has an input impedance that is different from an input impedance of an inverter of the even number of second inverters claim 1 , and wherein the phase inverter further comprises:a first inverter having an input coupled to the second input; anda second inverter having an input coupled to the first input.3. The phase inverter of claim 2 , ...

High-resolution phase interpolators

A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

High-resolution phase interpolators

A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Variable unit delay circuit and clock generation circuit for semiconductor apparatus using the same

A clock generation circuit includes, inter alia, a first phase detection block comparing initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and outputting an initial phase difference detection signal corresponding to a comparison result; a second phase detection block comparing phases of the reference clock signal and the output clock signal, and outputting a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and delaying the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and outputting the output clock signal; and a delay control block generating the control voltage which has the voltage level corresponding to the phase detection signal.

DELAY MEASURING CIRCUIT AND DELAY MEASURING METHOD

A delay measuring circuit includes a first trigger-signal generating unit that, when a value of a signal input to a circuit under test, changes, generates a first trigger signal. The delay measuring circuit includes a second trigger-signal generating unit that, when a value of a signal output from the circuit under test changes, generates a second trigger signal. The delay measuring circuit includes a delay unit that includes a plurality of delay elements connected in series. The delay measuring circuit includes a delay information retaining unit that individually captures and retains the first trigger signal output from each of the delay elements included in the delay unit between when the first trigger signal is generated by the first trigger-signal generating unit and when the second trigger signal is generated by the second trigger-signal generating unit. 1. A delay measuring circuit comprising:a first trigger-signal generating unit that, when a value of a signal input to a circuit under test, in which an input signal and an output signal have a one-to-one correspondence with each other, changes, generates a first trigger signal;a second trigger-signal generating unit that, when a value of a signal output from the circuit under test changes, generates a second trigger signal;a delay unit that includes a plurality of delay elements, which delay the first trigger signal generated by the first trigger-signal generating unit, connected in series; anda delay information retaining unit that individually captures and retains the first trigger signal output from each of the delay elements included in the delay unit between when the first trigger signal is generated by the first trigger-signal generating unit and when the second trigger signal is generated by the second trigger-signal generating unit.2. The delay measuring circuit according to claim 1 , whereinwhen a value of a signal input to the circuit under test transitions from high to low or when the value of the ...

POWER SUPPLY INDUCED SIGNAL JITTER COMPENSATION

Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response. 1. An apparatus , comprising:a delay element having a delay; anda bias-controlled delay element, the bias-controlled delay element configured to exhibit an increased drive strength to increase the delay of the delay element and exhibit a decreased drive strength to decrease the delay of the delay element to compensate for a response of the delay based on changes in power applied to the delay element.2. The apparatus of claim 1 , further comprising a signal path claim 1 , wherein the signal path includes the delay element and the bias-controlled delay element.3. The apparatus of claim 1 , wherein the bias-controlled delay element is configured to receive a bias signal.4. The apparatus of claim 3 , wherein changes in magnitude of the bias signal are proportionate to the changes in power applied to the delay element.5. The apparatus of claim 3 , wherein the drive strength of the bias-controlled delay element is controlled based on the magnitude of the bias signal.6. The apparatus of claim 4 , wherein the delay element is configured to receive an input signal and to provide an output signal delayed relative to the input signal.7. An apparatus comprising:a delay element having a first delay, wherein the first delay of the delay element exhibits a first response to changes in applied power; anda bias-controlled delay element having a second delay, ...

Delaying Data Signals

In one embodiment, multiple (serializer-deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

COMMAND LATENCY SYSTEMS AND METHODS

Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required. 1. An apparatus , comprising:a delay circuit configured to receive a first command signal and delay the first command signal based, at least in part, on first and second clock signals to provide a delayed command signal; andan output flip-flop configured to provide a second command signal in accordance with the first clock signal, the second command signal based, at least in part, on the delayed command signal and phase information indicating a cycle of the first clock signal corresponding to receipt of the first command signal by the delay circuit.2. The apparatus of claim 1 , wherein the delay circuit is further configured to lengthen the command signal.3. The apparatus of claim 1 , wherein the second clock signal is based claim 1 , at least in part claim 1 , on the first clock signal.4. The apparatus of claim 1 , further comprising storage circuitry configured to receive the second command signal and provide the phase information responsive claim 1 , at least in part claim 1 , to cycling through a plurality of states.5. The apparatus of claim 4 , wherein the storage circuitry comprises a flip-flop pipeline.6. The apparatus of claim 1 , wherein the apparatus is included in a memory.7. The apparatus of claim 1 , wherein the delay circuit comprises a first number of flip-flops and wherein the delay circuit is configured to delay the first command signal by a second number of cycles of the first clock signal claim 1 , the second number greater than the first number.8. An apparatus claim 1 , ...

CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF

A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock. 1. A clock generator , comprising: an oscillator, arranged to provide a first clock; and', 'a delay locked loop (DLL), arranged to generate said second clock according to said first clock; and, 'an oscillator block, arranged to provide a second clock of multiple phases, comprisingan output block, arranged to receive said second clock and generate a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.2. The clock generator of claim 1 , wherein said output block comprises:a multiplexer, arranged to generate a multiplexer output by multiplexing said multiple phases according to a control signal; anda controller, arranged to receive said multiplexer output and generate said control signal according to said multiplexer output.3. The clock generator of claim 2 , wherein said multiplexer output is cyclically set by said signals of said multiple phases.4. The clock generator of claim 2 , wherein said controller is arranged to update said control signal when said multiplexer output has a transition from a first logic level to a second logic level.5. The clock generator of claim 2 , wherein said output block further comprises:a toggle circuit, arranged to receive said multiplexer output and generate said third clock according to said multiplexer output, wherein said third clock is toggled when said toggle circuit is triggered by said multiplexer output.6. The clock generator of claim 5 , ...

PROGRAMMABLE DELAY UNIT

A tunable delay unit and methods of tuning are provided, comprising a plurality of first delay elements and a plurality of first delay element taps between the first delay elements, wherein the first delay element taps are inputs to a first multiplexer and wherein the output of the first multiplexer is selected from among the inputs according to a first tap select input, further comprising a plurality of second delay elements connected in series to the output of the first multiplexer and a plurality of second delay element taps between the second delay elements, wherein the second delay element taps are inputs to a second multiplexer and wherein the output of the second multiplexer is selected from among the inputs according to a second tap select input, the output of the second multiplexer forming the output of the programmable delay unit. The programmable delay unit provides for highly accurate calibration of timed circuits, in particular delay lines. 1. A programmable delay unit comprising a plurality of first delay elements and a plurality of first delay element taps between the first delay elements , wherein the first delay element taps are inputs to a first multiplexer and wherein the output of the first multiplexer is selected from among the inputs according to a first tap select input , and further comprising a plurality of second delay elements connected in series to the output of the first multiplexer and a plurality of second delay element taps between the second delay elements , wherein the second delay element taps are inputs to a second multiplexer and wherein the output of the second multiplexer is selected from among the inputs according to a second tap select input , the output of the second multiplexer forming the output of the programmable delay unit.2. The programmable delay unit of claim 1 , wherein the second delay elements provide shorter delays than the first delay elements.3. The programmable delay unit of claim 1 , further comprising a ...

PARTIAL RESPONSE RECEIVER AND RELATED METHOD

A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal. 1. (canceled)2. An integrated circuit comprising:a two phase partial response equalizer circuit;the two phase partial response equalizer circuit having a first sampler circuit to sample an input signal to generate a first sampled signal in response to a first sampling clock having a first phase, and a second sampler circuit to sample the input signal to generate a second sampled signal in response to a second sampling clock having a second phase;the two phase partial response equalizer circuit having a first feedback path to control partial response selection by the first sampler circuit in dependence on the second sampled signal and a second feedback path to control partial response selection by the second sampler circuit in dependence on the first sampled signal;a latch in the first feedback path, the second feedback path not having a latch; andcircuitry to generate a latch clock for the latch in the first feedback path to be phase offset from each of the first sampling clock and the second sampling clock.3. The integrated circuit of claim 2 , wherein:the ...

SIGNAL PROCESSING APPARATUS

A delay element delays an output signal Dt from an arithmetic circuit and outputs a delayed signal Dd. An XOR element compares the output signal Dt with the delayed signal Dd, and outputs an XORout signal with the signal value “0” when the signals match each other, and outputs an XORout signal with the signal value “1” when the signals do not match each other. In a flip-flop when the signal value of the XORout signal at the rise of a clock of a clock signal CK is “0”, the output signal Dt is output from a flip-flop and when the signal value of the XORout signal at the rise of the clock becomes “1” even once, a fixed value of the signal value “0” continues to be output. 1. A signal processing apparatus comprising:a delaying unit that inputs an output signal output continuously from an arithmetic circuit, delays the output signal input, and outputs the output signal delayed as a delayed signal;a comparing unit that inputs the output signal from the arithmetic circuit and inputs the delayed signal from the delaying unit in parallel with the input of the output signal from the arithmetic circuit, compares signal values between the output signal and the delayed signal input at same timing, and outputs one of a match signal and a mismatch signal as a comparison result signal, the match signal notifying that the compared signal values of the output signal and the delayed signal match each other, and the mismatch signal notifying that the compared signal values of the output signal and the delayed signal mismatch each other;a determining unit that inputs a clock signal and inputs the comparison result signal from the comparing unit in parallel with the input of the clock signal, and determines, every time determination timing comes, whether the comparison result signal input in parallel at the determination timing is a match signal or a mismatch signal, the determination timing being at least one of clock rise timing and clock fall timing; andan output unit that inputs the ...

DYNAMIC CLOCK PHASE CONTROL ARCHITECTURE FOR FREQUENCY SYNTHESIS

Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal. 1. A synthetic frequency generator comprising; to receive a master oscillator signal having a frequency and a period;', 'to receive a plurality of phase-control signals;', 'to receive a plurality of selection signals synchronized with the master oscillator; and', 'to provide first and second multiplexer clock signals having transitions synchronized with transitions of the master oscillator signal using a selection of the plurality of phase control signals, the selection based on the plurality of selection signals;', 'wherein the first and second multiplexer clock signals are configured to include a phase offset, and wherein a period of the phase offset is equal to or greater than one half the period of the master oscillator signal; and, 'a multiplexer configured'}an interpolator configured to receive the first and second multiplexer clock signals and to interpolate an output clock signal using the first and second multiplexer clock signals, wherein the output clock signal includes an average frequency greater than zero.2. The synthetic frequency generator of claim 1 , wherein the phase offset is about 45 degrees.3. The synthetic frequency generator of claim 1 , including a digital control circuit configured to provide the plurality of phase control signals.4. The synthetic frequency generator of claim 3 , wherein the multiplexer is configured to provide a clock signal to drive the digital control ...

Delay circuit and electronic device having the same

An electronic device receives a voltage from a power supply. The electronic device includes a load, a first adjusting module, a switching module, a delay module, and a second adjusting module. The first adjusting module produces a working voltage when the electronic device is powered on. The switching module establishes an electrical connection between the first adjusting module and the load when receiving the working voltage, and cuts off the electrical connection when not receiving the working voltage. The delay module delays outputting the working voltage to the load for a first predetermined time period on power on, and maintains a power supply to the load for a second predetermined time period after power off. Both the first predetermined time period and the second predetermined time period are independently adjustable.

Analog delay lines and adaptive biasing

Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.

Feed-forward equalizer architectures

Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.

SIGNAL DELAY DEVICE AND CONTROL METHOD

A signal delay device includes a delay unit including delay parts connected to one another in series and generating a delay signal; a selection unit to output the delay signal and including selectors connected to one another in series and outputting the delay signal, each selector receiving an output of one of the delay parts, being supplied with an output of former selector, and outputting the output of the delay part or the output of the former selector, based on a selection signal; a register unit holding delay setting data to set an amount of delay of the signal delay device; and a selection signal generator generating a selection signal indicating one of the selectors selecting an output of one of the delay parts based on the delay setting data and outputting the generated selection signal to the selection unit. 1. A signal delay device outputting a delay signal obtained by assigning a delay to an input signal , the signal delay device comprising:a delay unit including a plurality of delay parts connected to one another in series and configured to generate the delay signal, the delay signal being obtained by causing at least one of the delay parts to assign the delay to the input signal;a selection unit configured to output the delay signal, the selection unit including a plurality of selectors connected to one another in series, each of the selectors being configured to receive an output of a corresponding one of the delay parts, each of the selectors excluding a head one of the selectors being supplied with an output of a corresponding one of the former selectors, and outputting one of the output of the corresponding one of the delay parts and the output of the corresponding one of the former selectors, based on a selection signal supplied therein;a register unit configured to hold delay setting data to set an amount of delay of the signal delay device; anda selection signal generator configured to generate the selection signal indicating one of the selectors ...

Multi-Point Analog to Single-Line Input for a PLC System

A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs. 1. A multiple channel system for a single input of a controller comprising:a first multiplexer having a plurality of inputs and an output;a binary counter circuit coupled to the first multiplexer; and,a controller having a first input coupled to the output of the first multiplexer, the first input selectively receiving data from the plurality of inputs to the first multiplexer.2. The system of wherein the controller is a PLC.3. The system of further comprising a clock coupled to the binary counter circuit.4. The system of wherein each input of the first plurality of inputs of the first multiplexer is coupled to a device providing an analog voltage signal.5. The system of further comprising a voltage to frequency converter coupled to the multiplexer.6. The system of wherein one of the plurality of inputs of the first multiplexer is coupled to a reference voltage to synchronize the system.7. The system of further comprising a second multiplexer having a plurality of inputs and an output claim 1 , the output of the second multiplexer coupled to the first input of the controller claim 1 , the first input selectively receiving data from the plurality of inputs to the second multiplexer.8. The system of wherein the binary counter is coupled to the second multiplexer.9. The system of wherein each of the plurality of inputs of the second multiplexer is coupled to an analog ...

CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information. 1. A clock generation circuit comprising:a delay line configured to delay an input clock and generate a delayed clock;a delay modeling block configured to delay the delayed clock by a modeled delay value, and generate a feedback clock;a phase detection block configured to compare phases of the input clock and the feedback clock and generate phase information, and to quantize a phase difference between the input clock and the feedback clock to generate phase codes;a multi-update signal generation block configured to generate a multi-update signal in response to the phase codes; anda delay line control block configured to change a delay amount is of the delay line in response to the multi-update signal and the phase information.2. The clock generation circuit according to claim 1 , wherein the phase detection block comprises:a first phase detection signal generating section configured to generate a plurality of input sampling clocks with different phases, from the input clock, and compare phases of the plurality of input sampling clocks and the feedback clock and generate first phase detection signals;a second phase detection signal generating section configured to generate a plurality ...

DELAY CIRCUIT AND DELAY METHOD USING THE SAME

A delay circuit includes a delay unit configured to generate a delayed transmission signal by delaying a transmission signal activated when a first signal or a second signal is activated, a signal type storing unit configured to store whether the first signal and the second signal is activated, and a transmitting unit configured to transmits the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit. 1. A delay circuit comprising:a delay unit configured to generate a delayed transmission signal by delaying a transmission signal that is activated when a first signal or a second signal is activated;a signal type storing unit configured to store whether the first signal or the second signal is activated; anda transmitting unit configured to transmit the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit.2. The delay circuit of claim 1 , wherein the signal type storing unit stores a first value when the first signal is applied claim 1 , and stores a second value inverted from the first value when the second signal is activated.3. The delay circuit of claim 1 , wherein the transmitting unit transmits the delayed transmission signal as the first delayed signal when the value stored in the signal type storing unit is the first value claim 1 , and transmits the delayed transmission signal as the second delayed signal when the value stored in the signal type storing unit is the second value.4. The delay circuit of claim 1 , wherein the delay unit delays the transmission signal by a delay value determined in response to delay information.5. The delay circuit of claim 4 , wherein the first signal is a read command claim 4 , the second signal is a write command claim 4 , and the delay information is latency information.6. A delay circuit comprising:a delay unit configured to generate a delayed ...

SAMPLING CLOCK GENERATOR CIRCUIT, AND IMAGE READER AND ELECTRONIC DEVICE INCORPORATING THE SAME

A sampling clock generator circuit includes a reference clock generator, a sampling hold circuit, a sampling clock generator to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit, a phase determining element to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator, and a controller to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero. 1. A sampling clock generator circuit comprising:a reference clock generator;a sampling hold circuit;a sampling clock generator configured to delay an output clock signal from the reference clock generator by a predetermined delay amount to generate and supply a sampling clock signal to the sampling hold circuit;a phase determining element configured to compare phases of a drive clock signal for an image reading unit and the sampling clock signal to output a result of the phase comparison, the drive clock signal generated according to the output clock signal of the reference clock generator; anda controller configured to adjust the delay amount of the sampling clock generator on the basis of the result of the phase comparison so that a phase difference between the drive clock signal and the sampling clock signal becomes zero.2. A sampling clock generator according to claim 1 , further comprising:a first delay circuit having a plurality of first delay taps to delay the output clock signal input by a tap selection; anda second delay circuit having a plurality of second delay taps having a delay amount smaller than that of the first delay taps to delay the output clock signal ...

MULTI-STAGE PHASE MIXER CIRCUIT

A multi-stage phase mixer circuit includes: a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal; a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; and a third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal. 1. A multi-stage phase mixer circuit comprising:a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal;a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; anda third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal.2. The multi-stage phase mixer circuit of claim 1 , wherein the multi-stage phase mixer circuit performs a phase mixing operation through two stages by performing a first phase mixing operation using the first and second phase mixers and performing a second phase mixing operation using the third phase mixer.3. The multi-stage phase mixer circuit of claim 1 , wherein the first and second coarse control signals have a difference of 1 least significant bit (LSB).4. The multi-stage phase mixer circuit of claim 1 , wherein the first and second intermediate clock signals have a delay time difference corresponding to 1 LSB of the first and second coarse control signals.5. The multi-stage phase mixer circuit of claim 1 , wherein each of the first claim 1 , second claim 1 , and third phase mixers comprises two or more inverting ...

PROGRAMMABLE DELAY CIRCUITRY

Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay. 1. Programmable delay circuitry comprising:an input buffer circuit coupled to an input stage; and the input stage;', 'a correction start voltage circuit coupled to the input stage; and', 'a variable delay capacitor coupled to the input stage, wherein the programmable delay circuitry is configured to provide a fixed time delay and a variable time delay., 'variable delay circuitry comprising2. The programmable delay circuitry of wherein the input buffer circuit is configured to provide a first portion of the fixed time delay and the variable delay circuitry is configured to provide a second portion of the fixed time delay and the variable time delay.3. The programmable delay circuitry of further configured to receive and delay an input voltage to provide an output voltage.4. The programmable delay circuitry of wherein the input stage comprises a first P-type field effect transistor element (PFET) and a first N-type field effect transistor element (NFET) claim 1 , such that a drain of the first PFET and a drain of the first NFET are both coupled to the variable delay capacitor.5. The programmable delay circuitry of wherein the correction start voltage circuit is configured to provide a first known voltage level at a source of the first PFET while the first PFET is in a non-conducting state.6. The programmable delay circuitry of wherein the first known voltage level is substantially equal to a ground.7. The programmable delay circuitry of wherein the ...

Phase interpolator for clock data recovery circuit with active wave shaping integrators

A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

SAMPLE-AND-HOLD CIRCUIT FOR GENERATING A VARIABLE SAMPLE DELAY TIME OF A TRANSFORMER AND METHOD THEREOF

A sample-and-hold circuit for generating a variable sample delay time of a transformer includes a discharge detection unit, a sample delay time generation unit, and a comparator. The discharge detection unit generates a first voltage according to a first turning-on signal and a first reference current. Length of the first turning-on signal is varied with a discharge time of a present period of the transformer. The sample delay time generation unit generates a second voltage according to the first turning-on signal and a second reference current. The comparator generates a sample signal to a control circuit of the transformer according to a first voltage corresponding to a previous period of the transformer and a second voltage corresponding to the present period of the transformer. The first reference current is K times the second reference current, and 0 Подробнее

Integrated circuit having a multiplying injection-locked oscillator

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

SIGNAL TRANSMISSION CIRCUITS

A signal transmission circuit includes a pre-driver and a driver. The pre-driver is configured to generate a first drive signal in response to a first delay signal and a first selection signal and to generate a second drive signal in response to a second delay signal, a second selection signal, and a pulse signal. The driver is configured to drive a transmission signal in response to the first and second drive signals. The first delay signal is enabled at a second time which is later than a first time when an input signal is received, the second delay signal is enabled at a third time which is later than the second time, and the pulse signal is enabled at a fourth time which is delayed by a predetermined delay period from the first time. 1. A signal transmission circuit , the circuit comprising:a pre-driver configured to generate a first drive signal in response to a first delay signal and a first selection signal and to generate a second drive signal in response to a second delay signal, a second selection signal, and a pulse signal; anda driver configured to drive a transmission signal in response to the first and second drive signals,wherein the first delay signal is enabled at a second time which is later than a first time when an input signal is received, the second delay signal is enabled at a third time which is later than the second time, and the pulse signal is enabled at a fourth time which is delayed by a predetermined delay period from the first time.2. The circuit of claim 1 , wherein the first and second selection signals are set by a mode register setting operation.3. The circuit of claim 1 , wherein the second drive signal is enabled from the third time to the fourth time when the second selection signal is disabled.4. The circuit of claim 1 , wherein the driver includes:a first driver configured to drive the transmission signal when the first drive signal is enabled; anda second driver configured to drive the transmission signal when the second ...

Programmable Global Shutter Timing to Mitigate Transient Glitching

An image sensor system using a circuit that automatically provides a multiple point output which represents, in a first mode, each of the multiple points receiving outputs at substantially the same time delayed only by a transit time across a wire connecting the multiple point outputs, and in a second mode, each of the multiple points producing outputs that are delayed by a delay time, where each output is delayed relative to each other output by said delay time in the second mode. 1. A system comprising:a circuit that automatically provides a multiple point output which represents, in a first mode, each of the multiple points receiving outputs at substantially the same time delayed only by a transit time across a wire connecting the multiple point outputs, and in a second mode, each of the multiple points producing outputs that are delayed by a delay time, where each output is delayed relative to each other output by said delay time in said second mode.2. The system as in claim 1 , wherein said circuit includes a delay line with plural different taps claim 1 , each tap producing one of the outputs for said delay line.3. The system as in claim 1 , wherein said delay lines are programmable to produce outputs that are delayed relative to one another via a programmable amount.4. The system as in claim 1 , wherein the propagation delays of rising and falling edges of signals are separately programmable.5. The system in claim 3 , where the programmability is achieved via an analog current limiting structure.6. The system in claim 3 , further comprising a feedback circuit that can measure the overall end-to-end delay of the system and automatically adjust the individual element delays to achieve and maintain a specified end-to-end delay.7. The system in claim 1 , wherein the each delay element in the daisy chain has a separately programmable delay.8. The system in claim 1 , wherein both the rising and falling edge delay of each element in the daisy chain has a separately ...

SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME

A semiconductor device includes a division unit configured to divide an oscillation signal and to generate a plurality of divided signals having different division ratios each other, a delay amount determination unit configured to combine an source signal, the oscillation signal, and the plurality of divided signals and to generate a delay amount information signal with information on a given delay amount, and an edge-delayed signal output unit configured to generate at least one edge-delayed signal corresponding to the given delay amount in response to the source signal and the delay amount information signal. 1. A semiconductor device , comprising:a division unit configured to divide an oscillation signal and to generate a plurality of divided signals having different division ratios each other;a delay amount determination unit configured to combine an source signal the oscillation signal, and the plurality of divided signals and to generate a delay amount information signal with information on a given delay amount; andan edge-delayed signal output unit configured to generate at least one edge-delayed signal corresponding to the given delay amount in response to the source signal and the delay amount information signal.2. The semiconductor device of claim 1 , wherein the edge-delayed signal output unit generates a rising edge-delayed signal and a falling edge-delayed signal in response to the source signal and the delay amount information signal.3. The semiconductor device of claim 1 , further comprising an oscillation unit configured to generate the oscillation signal in response to an enable signal and supply the oscillation signal to the division unit claim 1 , wherein the division unit generates the plurality of divided signals corresponding to the oscillation signal in response to the enable signal.4. The semiconductor device of claim 3 , wherein the oscillation unit receives an internal voltage as a driving voltage and the oscillation signal is level-shifted ...

POWER EFFICIENT MULTIPLEXER

A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs. 1. A method comprising:outputting at least one bit and a complement of the at least one bit;selectively passing one of a plurality of input signals by using the at least one bit and the complement; andindependently of the at least one bit and the complement and a state of a clock signal, inverting an input signal from said selectively passing.2. The method of claim 1 , wherein said selectively passing comprises:applying the at least one bit to a first transmission gate and a second transmission gate; andapplying the complement to the first transmission gate and the second transmission gate.3. The method of claim 2 , wherein said selectively passing further comprises:if the at least one bit is a first value, outputting a first input signal from the first transmission gate.4. The method of claim 3 , wherein said selectively passing further comprises:if the at least one bit is a second value, outputting a second input signal from the second transmission gate.5. The method of claim 1 , wherein said inverting comprises:using a stacked inverter to invert the input signal from said selectively passing, wherein the stacked inverter includes a first number of transistors arranged as a low-to-high transition leg and a second number of transistors arranged as a high-to-low transition leg.6. The method of claim 5 , wherein the first number equals the second number.7. The method of claim 5 , wherein the first number is greater than the second number.8. The method of claim 5 , wherein the first number is less than the second number.9. A ...

CLOCK SIGNAL GENERATING CIRCUIT AND POWER SUPPLY INCLUDING THE SAME

The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal. 1. A power supply for generating a reference signal by using an input clock signal following a full wave rectified voltage , and controlling a switching operation of a power switch according to the reference signal , comprising:a voltage sensor for generating a sense voltage corresponding to the full wave rectified voltage;a zero crossing detector for generating the input clock signal according to a result of comparing the sense voltage and a predetermined zero crossing reference voltage; anda clock signal generating circuit for generating a quotient and a remainder by dividing a count signal following a result of counting one period of the input clock signal by using a reference clock signal, setting the quotient as a reference period of the output clock signal, and distributing and disposing the remainder to an output clock signal of a plurality of periods occurring for one period of the input clock signal.2. The power supply of claim 1 , whereinthe clock signal generator sets a plurality of periods of the reference clock signal that correspond to the quotient as a reference period of the output clock signal, and sets a period that corresponds to the remainder from among the plurality of periods of the output clock signal occurring for one period of the input clock signal as a modulation period that is an addition of a period of the ...

Semiconductor integrated circuit and signal transmission method thereof

A semiconductor integrated circuit includes a plurality of semiconductor chips stacked in a multi-layer structure; a correction circuit in each semiconductor chip configured to reflect a delay time corresponding to the position of the chip in the stack into an input signal to output to each semiconductor chip; and a plurality of through-chip vias formed vertically through each of the semiconductor chips and configured to transmit the input signal to the semiconductor chip.

INTEGRATED CIRCUIT

An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock. 1. An integrated circuit comprising:a clock control unit configured to transfer a first reference voltage or a second reference voltage as a first selection reference voltage in response to a divided clock which is generated by dividing an external clock when a test mode is entered, and generate an input clock by comparing the first selection reference voltage and the external clock; andan internal circuit configured to operate in response to the input clock.2. The integrated circuit according to claim 1 , wherein the clock control unit comprises:a control signal generating section configured to output the divided clock as a control signal when the test mode is entered;a first reference voltage transferring section configured to transfer the first reference voltage or the second reference voltage as the first selection reference voltage in response to the control signal; anda comparing section configured to compare the first selection reference voltage and the external clock and generate the input clock.3. The integrated circuit according to claim 2 , wherein the control signal generating section outputs the ground voltage as the control signal when the test mode is not entered.4. The integrated circuit according to claim 2 , wherein the first reference voltage transferring section transfers the second reference voltage with a higher level than the first reference voltage as the first selection reference voltage when the test mode is entered.5. The integrated circuit according to claim 1 , further comprising:a voltage control unit configured to generate an internal voltage and supply the internal voltage to the internal ...

Method and circuit for adjusting the frequency of a clock signal

In a general aspect, a method for adjusting an oscillator clock frequency can include applying a first control value to a first oscillator, applying a second control value, different from the first control value, to a second oscillator, measuring a frequency of each of the first and second oscillators, determining, by interpolation, a corrected frequency measurement of the second oscillator depending on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the control value applied to the second oscillator, determining by interpolation a new first control value depending on the measured frequency of the first oscillator, on the corrected frequency, on the first and second control values, and on a desired frequency, and applying the new first control value to the first oscillator.

PULSE GENERATOR

A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality of switching elements in a predetermined sequence so as to generate a predetermined pulse waveform at a pulse generator output. The switching elements of the signal generating arm and the inductor together form a pulse synthesizer that takes the signal from the controller and uses it to synthesize an output pulse. Compared with conventional transmitter architectures, the functions of the upconversion mixer, the DAC, and the power amplifier are all performed by a single simplified circuit. This is both area efficient and power efficient. 1. A pulse generator comprising:a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; anda controller arranged to activate the plurality of switching elements in a predetermined sequence so as to generate a predetermined pulse waveform at a pulse generator output.2. A pulse generator as claimed in claim 1 , wherein:the plurality of switching elements in the first signal generating arm are arranged to draw different amounts of current.3. A pulse generator as claimed in claim 2 , wherein the plurality of switching elements are transistors and the current drawing ability of each transistor is defined by sizing of the transistors.4. A pulse generator as claimed in claim 1 , further comprising:a second signal generating arm comprising a second inductor and a plurality of switching elements, each arranged to draw current through the second inductor; andwherein the controller is arranged to activate the plurality of switching elements of the first and second signal generating arms in a predetermined sequence so as to generate a predetermined pulse waveform as a differential signal between a first pulse ...

Phase synchronized lo generation

Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

CLOCK SYNTHESIS FOR FREQUENCY SCALING IN PROGRAMMABLE LOGIC DESIGNS

Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed. 1. A method , comprising:generating, by a first configurable clock signal generator of a configurable clock, a first internal clock signal having a first frequency;generating, by a second configurable clock signal generator of the configurable clock, a second internal clock signal having a second frequency;providing, as an output signal of the configurable clock, the first internal clock signal having the first frequency, the second internal clock signal having the second frequency, or both;in response to determining that the first internal clock signal and the second internal clock signal do not match a target frequency, reconfiguring the first configurable clock signal generator to generate the first internal clock signal having a third frequency, reconfiguring the second configurable clock signal generator to generate the second internal clock signal having a fourth frequency, or both; andproviding, as the output signal of the configurable clock, the first internal clock signal having the third frequency, the second internal clock signal having the fourth frequency, or both.2. The method of claim 1 , wherein a difference between the first frequency and the second frequency comprises an incremental difference.3. The method of ...

DELAY LINE SYSTEM, HIGH FREQUENCY SAMPLER, ANALOG-TO-DIGITAL CONVERTER AND OSCILLOSCOPE

A delay line system for high frequency signal transmission comprises a first delay line and a second delay line that are each tapped. The first delay line comprises a first terminal and a second terminal, and the second delay line comprises a first terminal and a second terminal. The first delay line and the second delay line are configured in a manner whereby an analog input signal applied to the first terminal of the first delay line propagates through the first delay line in a first direction, a clock signal applied to the first terminal of the second delay line propagates through the second delay line in a second direction, and the first direction is opposite to the second direction. Further, an oscilloscope for measuring high frequency signals comprises an ADC, which comprises a high frequency sampler, which comprises such a delay line system. 1. A delay line system comprising:a first delay line that comprises a first terminal and a second terminal;a second delay line that comprises a first terminal and a second terminal;wherein the first delay line and the second delay line are each tapped; andwherein the first delay line and the second delay line are configured in a manner whereby an analog input signal applied to the first terminal of the first delay line propagates through the first delay line in a first direction, a clock signal applied to the first terminal of the second delay line propagates through the second delay line in a second direction, and the first direction is opposite to the second direction.2. The delay line system according to claim 1 , wherein the first delay line is arranged in parallel to the second delay line claim 1 , and the first terminal of the first delay line is arranged at an end opposite to an end of the first terminal of the second delay line.3. The delay line system according to claim 1 , wherein the first delay line and the second delay line each comprises a number of delay elements of equal dimensions claim 1 , and the number ...

DEVICE, METHOD AND SYSTEM FOR PROVIDING A DELAYED CLOCK SIGNAL TO A CIRCUIT FOR LATCHING DATA

Techniques and mechanisms for determining a delay to be applied to a clock signal for synchronizing data communication. In an embodiment, a delay is applied to a first clock signal to generate a second clock signal, which is then communicated to a latch circuit via a clock signal distribution path. The delay is determined based on an evaluation of a first time needed for signal communication via a model of the clock signal distribution path. Such determining is further based on an evaluation of a second time for one cycle of a cyclical signal, where said cycle correspond to that of the first clock signal. In another embodiment, multiple different delays are applied each to a different respective clock signal, where each of said delays is based on both the evaluation of the first time and the evaluation of the second time. 1. An integrated circuit (IC) chip comprising:first circuitry to receive a first clock signal, to generate a second clock signal based on the first clock signal, and to communicate the second clock signal via a first signal path which comprises a clock signal distribution path;{'b': 1', '1, 'second circuitry to generate a signal S, wherein a second signal path of the second circuitry comprises a model of the first signal path, wherein the signal S comprises a first indication of a first delay corresponding to the model; and'}{'b': 1', '2, 'third circuitry to receive the signal S and a signal S comprising a second indication of a second delay based on a cycle of a cyclical signal, the third circuitry further to provide to the first circuitry a control signal based on the first indication and the second indication, wherein the first circuitry is to apply a third delay to the first clock signal based on the control signal, wherein the third delay is based on a sum of a first value and a second value, wherein the first value represents the first delay, and wherein the second value represents a time for a scalar multiple of one cycle of the cyclical ...

CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0. 1. A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation , comprising;receiving a first stream of data bits input to the data interface circuit;initially establishing, using a first calibration method, an optimal sampling point for sampling the data bits input to the data interface circuit;receiving a second stream of data bits input to the data interface circuit during normal system operation; establishing at least one reference data path for sampling transition edges of the second stream of data bits input to the data interface during normal system operation;', 'using the at least one reference data path, sampling a plurality of fringe timing points associated with transition edges of the second stream of data bits input to the data interface circuit;', 'comparing a first fringe timing measurement made during a first performance of the second calibration method, with a second fringe timing measurement made during a second ...

Multi-signal realignment for changing sampling clock

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

ERROR DETECTION AND COMPENSATION FOR A MULTIPLEXING TRANSMITTER

Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error. 1. A system for reducing error associated with a multiplexing transmitter , comprising:an error detector circuit configured to measure a quadrature error for a clock associated with a transmitter to generate first error detector information based on a first clock pattern for a first output generated by the transmitter in response to a defined bit pattern, and generate second error detector information based on a second clock pattern for a second output generated by the transmitter in response to an inverted version of the defined bit pattern, wherein the error detector circuit is further configured to determine a first average value of the first error detector information and a second average value of the second error detector information, determine a differential average value of the first average value and the second average value based on a comparison of the first average value to the second average value, and determine an error detector output based on the differential average value; anda duty cycle correction ...

HIGH-SPEED INTERFACE APPARATUS AND DESKEW METHOD THEREOF

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode. 1. A high-speed data transmitter comprising:a first buffer connected to a first channel;a second buffer connected to a second channel; anda third buffer connected to a third channel, toggle the first channel from a first voltage level to a second voltage level different from the first voltage level over a predetermined interval;', 'maintain the second channel at the first or second voltage level during the predetermined interval; and', 'start a skew calibration mode based on the first channel and at least one of the second or third channel., 'wherein the high-speed data transmitter is configured to2. The high-speed data transmitter of claim 1 , wherein the predetermined interval is a period of transmitting a deskew synchronous code.3. The high-speed data transmitter of claim 2 , wherein the deskew synchronous code includes serial data “11111111”.4. The high-speed data transmitter of claim 1 , further configured to transmit normal data in a Mobile Industry Processor Interface (MIPI) standard.5. The high-speed data transmitter of claim 4 , wherein the normal data includes display data or image data.6. The high-speed data transmitter of claim 1 , configured to transmit normal data after the predetermined interval.7. The high-speed data transmitter of claim 1 , further comprising a clock generator configured to generate a clock signal.8. The high-speed data transmitter of claim 1 , wherein at least one of the first to third channels includes differential data lines.9. The ...

APPARATUS AND METHODS FOR COMPENSATION OF SIGNAL PATH DELAY VARIATION

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation. 1. An electronic system with compensation for signal path delay variation , the electronic system comprising: a timing circuit configured to generate an output signal based on timing of an input reference signal;', 'an output pin configured to receive the output signal from the timing circuit and', 'a delay compensation circuit configured to provide one or more compensation signals to the timing circuit; and, 'an integrated circuit (IC) comprisinga signal path configured to route the output signal from the output pin to a destination node,wherein the one or more compensation signals are operable to digitally compensate the timing circuit for a variation in delay of the signal path.2. The electronic system of claim 1 , wherein the delay compensation circuit comprises a delay model configured to generate an estimate of the variation in delay based on one or more operating conditions.3. The electronic system of claim 2 , wherein the delay model is configured to receive a temperature signal indicating a temperature condition.4. The electronic system of claim 2 , wherein the IC further comprises an interface ...

OPTICAL DRIVING DEVICE AND OPTICAL COMMUNICATION SYSTEM

An optical driving device and an optical communication system are provided which can improve signal quality of laser light that uses a PAM method. A laser driver drives a semiconductor laser by using an N-level (N is an integer of 3 or more) PAM signal. A clock control circuit determines a driving timing of the laser driver. In a case where N=4, for example, the clock control circuit determines a driving timing in association with a transition of the PAM signal from a fourth level to a first level to be earlier than a driving timing in association with a transition in an opposite direction by a first time, assuming that levels are the first level, . . . , and the fourth level in an order from a level at which light intensity is minimum. 1. An optical driving device that drives a direct modulation type semiconductor laser , comprising:a laser driver that drives the semiconductor laser by using an N-level (N is an integer of 3 or more) PAM (Pulse Amplitude Modulation) signal; anda clock control circuit that determines a driving timing of the laser driver,wherein the clock control circuit determines the driving timing in association with a transition from an N-th level to a first level to be earlier than the driving timing in association with a transition from the first level to the N-th level by a first time, assuming that N levels are the first level, a second level, . . . , and the N-th level in an order from a level at which light intensity is minimum.2. The optical driving device according to claim 1 ,wherein the N levels are four levels.3. The optical driving device according to claim 2 ,wherein the first time is “(Tf−Tr)/2”, assuming that a time required for the transition from the N-th level to the first level is “Tf” and a time required for the transition from the first level to the N-th level is “Tr”.4. The optical driving device according to claim 2 ,wherein the clock control circuit determines all the driving timings in association with transitions except ...

PROGRAMMABLE DELAY CIRCUIT INCLUDING HYBRID FIN FIELD EFFECT TRANSISTORS (FINFETS)

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins. 1. A programmable delay circuit , comprising:a first stage comprising a first hybrid fin field effect transistor (finFET), the first hybrid finFET comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins; anda second stage connected in series with the first stage, the second stage comprising a second hybrid finFET, the second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins,wherein the first default FET and the second default FET each receive a gate voltage from a power supply rail of the programmable delay circuit.2. (canceled)3. The programmable delay circuit of claim 1 , wherein the first default FET and the first control FET are in parallel in the ...

PROGRAMMABLE DELAY CIRCUIT INCLUDING HYBRID FIN FIELD EFFECT TRANSISTORS (FINFETS)

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins. 1. A method for providing a programmable delay circuit , comprising:forming a first stage comprising a first hybrid fin field effect transistor (finFET), the first hybrid finFET comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins; andforming a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET, the second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of finsthe first default FET and the second default FET each receive a gate voltage from a power supply rail of the programmable delay circuit.2. (canceled)3. The method of claim 1 , wherein the first default FET and the first control FET are in parallel ...

EXPANSION CONTROL CIRCUIT

An expansion control circuit includes a delay circuit coupled to a first expansion module and a switching circuit coupled to a second expansion module. The switching circuit includes a buffer and a switching module. The buffer is coupled to the first expansion module. The first expansion module outputs a first control signal upon being switched on and outputs a second control signal after a working time. The delay circuit outputs a disconnecting signal upon being switched on. The buffer is switched off upon receiving the disconnect signal. The delay circuit further outputs a connecting signal after a delay time after outputting the disconnecting signal. The buffer is switched on upon receiving the connect signal. The buffer further outputs the second control signal to the switching module upon being switched on. The switching module controls the second expansion module to be switched on v receiving the second control signal. 1. An expansion control circuit comprising:a delay circuit coupable to a first expansion module; and a buffer coupable to the first expansion module, and', 'a switching module configured to couple to a second expansion module;, 'a switching circuit having output a first control signal upon being switched on, and', 'output a second control signal after a preset working time;, 'wherein the first expansion module is configured to enable the buffer to be switched off subsequent to being switched on, and', 'enable the buffer to be switched on subsequent to being switched off;, 'wherein the delay circuit is configured towherein the buffer is configured to output the second control signal to the switching module upon being switched on; andwherein the switching module is configured to control the second expansion module to be switched on upon receiving the second control signal.2. The expansion control circuit of claim 1 , wherein the switching module comprises a first field effect transistor (FET) and a second FET claim 1 , the first FET is switched ...

SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE

While transmission of data to be transmitted and gap data to be transmitted by the same transmission path as that data is controlled so that a frequency of a data signal may become equal to or more than a certain frequency, a data output driver selects and outputs the data or the gap data as the data signal, a valid signal generation circuit outputs a valid signal that indicates whether or not the data is effective, and a reception circuit that is formed in a different die receives the data signal and the valid signal transmitted via the transmission path that includes a through silicon via and acquires the data from the data signal based on the valid signal. 1. A semiconductor device comprising:a holding circuit that holds first data to be transmitted;a data generation circuit that generates second data to be transmitted by the same transmission path as the first data;a control circuit that controls transmission of the first data and the second data so that a frequency of a data signal becomes equal to or more than a certain frequency;an output circuit that selects and outputs the first data held by the holding circuit or the second data generated by the data generation circuit as the data signal in correspondence with control by the control circuit;a valid signal generation circuit that outputs a valid signal that indicates that the data is effective when the output circuit is outputting the first data; anda reception circuit that is formed in a second die different from a first die that includes the holding circuit, the data generation circuit, the control circuit, the output circuit, and the valid signal generation circuit, receives the data signal and the valid signal transmitted from the first die via the transmission path that includes a through silicon via, and acquires the first data from the data signal based on the valid signal.2. The semiconductor device according to claim 1 , comprisingan inversion control circuit that outputs an inversion control ...

CMOS Pulse Shrinking, Stretching or Shrink-and-Stretch Mixing Method and Device Thereof

A CMOS pulse shrinking or stretching device includes a basic element sequence, including odd combination positions and even combination positions, and homogeneous logic elements connected to form the basic element sequence. The device further includes an inhomogeneous logic element serially connected between two of the basic elements at the odd or even combination position for shrinking or stretching a pulse signal. A CMOS pulse shrink-and-stretch mixing device further includes an inhomogeneous logic element set, including an odd-positioned inhomogeneous logic element and an even-positioned inhomogeneous logic element to combine stretching and shrinking functions of the pulse signal by adding a stretched pulse and a shrunk pulse signal together. 1. A CMOS pulse shrinking or stretching method comprising:providing a plurality of odd combination positions and a plurality of even combination positions on a basic element sequence which is formed from a series of basic elements;providing a plurality of homogeneous logic elements and at least one odd-positioned inhomogeneous logic element or at least one even-positioned inhomogeneous logic element for forming a pulse shrinking or stretching device;serially connecting the odd-positioned inhomogeneous logic element at the odd combination position or serially connecting the even-positioned inhomogeneous logic element at the even combination position to form the pulse shrinking and stretching device; andutilizing the odd-positioned inhomogeneous logic element to stretch a pulse signal or utilizing the even-positioned inhomogeneous logic element to shrink the pulse signal.2. The CMOS pulse shrinking or stretching method as defined in claim 1 , wherein the odd-positioned inhomogeneous logic element and the even-positioned inhomogeneous logic element are arranged together to provide a neutralizer or a neutralizing function of pulse shrinking and stretching.3. The CMOS pulse shrinking or stretching method as defined in claim 1 , ...

DELAY CIRCUIT, ELECTRONIC CIRCUIT USING DELAY CIRCUIT AND ULTRASONIC IMAGING DEVICE

A delay circuit and an ultrasonic imaging apparatus with the higher-accuracy delay time, the longer maximum delay time, and the lower power consumption are provided. An input line to which an analog input signal is input, a plurality of analog signal memory devices, an output line, a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices, a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line, and a clock generation part that generates sampling switch control signals for controlling the sampling switches and output switch control signals for controlling the output switches are provided, and phase of the sampling switch control signals may be shifted with respect to phase of the output switch control signals. 1. A delay circuit comprising:an input line to which an analog input signal is input;a plurality of analog signal memory devices;an output line from which an analog output signal is output;a plurality of sampling switches that control connection/disconnection between the input line and the plurality of analog signal memory devices;a plurality of output switches that control connection/disconnection between the plurality of analog signal memory devices and the output line; anda clock generation part that generates sampling switch control signals for respectively controlling the plurality of sampling switches and output switch control signals for respectively controlling the plurality of output switches from a reference clock,the delay circuit delaying signals by controlling the plurality of sampling switches to accumulate the analog input signal in the plurality of analog signal memory devices and controlling the plurality of output switches to output the signals accumulated in the plurality of analog signal memory devices to the output line,wherein phase of the plurality of sampling switch ...

SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING PLURALITY OF CHANNELS

A semiconductor apparatus includes a direct access section, an interface section, and a through-via region. The direct access section receives first and second groups of input signals through a direct access pad, and generates first and second groups of control signals based on the first and second groups of input signals. The interface section comprises a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals. The through-via region electrically couples the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively. 1. A semiconductor apparatus comprising:a direct access section suitable for receiving first and second groups of input signals through a direct access pad, and generating first and second groups of control signals based on the first and second groups of input signals;an interface section comprising a plurality of channel circuits suitable for receiving a part or all of the first and second groups of control signals in response to a plurality of channel selection signals; anda through-via region suitable for electrically coupling the plurality of channel circuits and a plurality of stack dies to form a plurality of channels, respectively, and transferring signals from the plurality of channel circuits to the plurality of stack dies respectively corresponding to the plurality of channel circuits.2. The semiconductor apparatus of claim 1 , wherein the direct access section comprises:a receiver suitable for generating the first and second groups of control signals by decoding the first and second groups of input signals; anda channel selection unit suitable for generating the plurality of channel selection signals based on a part of the first and second groups of control signals.3. The semiconductor apparatus of claim 2 , wherein the interface section further comprises:a main buffer unit ...

SIGNAL ADJUSTMENT CIRCUIT

A circuit may include a phase detector circuit, a charge pump circuit, a delay circuit, and a multiplexer circuit. The phase detector circuit may be configured to output a comparison signal based on a comparison of a phase of an inversion of a first clock signal and a phase of a multiplexer signal. The charge pump may be configured to integrate the comparison signal and to output a control voltage based on the integration of the comparison signal. The delay circuit may be configured to receive a second clock signal, to delay the second clock signal based on the control voltage, and to output the delayed second clock signal. The second clock signal may be a divided version of the first clock signal. The multiplexer circuit may be configured to output the multiplexer signal based on the delayed second clock signal. 1. A circuit , comprising:a phase detector circuit, the phase detector circuit configured to output a comparison signal based on a comparison of a phase of an inversion of a first clock signal and a phase of a multiplexer signal;a charge pump circuit coupled to the phase detector circuit, the charge pump circuit configured to integrate the comparison signal and to output a control voltage based on the integration of the comparison signal;a delay circuit coupled to the charge pump circuit, the delay circuit configured to receive a second clock signal, to delay the second clock signal based on the control voltage, and to output the delayed second clock signal, the second clock signal is a divided version of the first clock signal; anda multiplexer circuit coupled to the delay circuit and the phase detector circuit, the multiplexer circuit configured to output the multiplexer signal based on the delayed second clock signal.2. The circuit of claim 1 , further comprising a divider circuit coupled to the delay circuit claim 1 , the divider circuit configured to divide the first clock signal to generate the second clock signal.3. The circuit of claim 2 , wherein ...

INTERPOLATOR

An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal. 1. An interpolator , comprising:a first delay circuit, delaying a first input signal for a fixed delay time, so as to generate a first output signal;a second delay circuit, delaying a second input signal for the fixed delay time, so as to generate a second output signal; anda tunable delay circuit, delaying the first input signal for a tunable delay time, so as to generate an output interpolation signal, wherein the tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal,wherein the first output signal, the second output signal, and the output interpolation signal have the same frequency, and a phase of the first output signal leads a phase of the second output signal, and a phase of the output interpolation signal is substantially between the phase of the first output signal and the phase of the second output signal.2. The interpolator as claimed in claim 1 , wherein the phase of the output interpolation signal is substantially in the middle of the phase of the first output signal and the phase of the second output signal.3. The interpolator as claimed in claim 1 , wherein each of the first delay circuit and the second delay circuit is formed by cascading two fixed inverters.4. The interpolator as claimed in claim 1 , wherein the tunable delay circuit comprises a tunable unit which is formed by ...

A SYSTEM FOR STABILIZING DELAY

The present invention relates to pulse power technology. The system includes an input channel, a pulse edge detector () connected in series with two inputs, a filter (), a variable delay unit (), and a feedback channel from the generator to one of the inputs of the pulse edge detector (). The system comprises a reference delay unit (), and the input channel is connected both to the variable delay unit () and to a reference delay unit () for simultaneous supply of input to said units. Signals to both inputs of the pulse edge detector () are synchronous on average, i.e. tstab.avg=1/τ∫ tstab dt=tref with τ>>τest.oper where: tstab.avg—generator output delay relative to the input signal, averaged over the operation time of the system τ at a given tref; tref—reference unit () output delay relative to the input signal; τest.oper—stabilization system time response to changes in external parameters, with the stabilization delay tstab determined from the condition tstab=tvar+tunstab where: tvar—delay of the variable delay unit (); tunstab—unstable delay of the generator. The stabilization of the delay is independent of the pulse repetition frequency. 1at least one input channel connected in series;a pulse edge detector with two inputs;a filter;a variable delay unit, and a feedback channel of the pulse voltage generator connected to one of the inputs of the pulse edge detector, with a special feature;a reference delay unit wherein the at least one input channel is connected both to the variable delay unit and to the reference delay unit for simultaneous input signal to the variable delay unit and the reference delay unit, whereby the signals to both inputs of the pulse edge detector are synchronous on average, i.e. tstab.avg=1/τ∫ tstab dt=tref with τ>>τest.oper where: tstab.avg is a generator output delay relative to the input signal, averaged over the operation time of the delay stabilization system ti at a given tref; wherein tref is a reference unit output delay relative to ...

DC-TO-DC DRIVERS WITH HIGH RESOLUTION DIMMING

One aspect of the invention provides a DC-to-DC driver including: a converter including an output configured to drive a load with an output current; and a feedback controller coupled to the converter. The feedback controller includes: a pulse-width modulator configured to output a first pulse-width modulated signal to the converter; a first switching mechanism coupled to the pulse-width modulator; a compensator having an output coupled to the first switching mechanism, the compensator configured to generate a first duty cycle control signal based on a comparison of the output current and a first reference voltage; and a sampler having an input coupled to the output of the compensator and an output coupled to the switching mechanism, the sampler configured to generate a second duty cycle control signal based on the first duty cycle control signal. 1. A DC-to-DC driver comprising:a converter comprising an output configured to drive a load with an output current; and a pulse-width modulator configured to output a first pulse-width modulated signal to the converter;', 'a first switching mechanism coupled to the pulse-width modulator;', 'a compensator having an output coupled to the first switching mechanism, the compensator configured to generate a first duty cycle control signal based on a comparison of the output current and a first reference voltage; and', 'a sampler having an input coupled to the output of the compensator and an output coupled to the switching mechanism, the sampler configured to generate a second duty cycle control signal based on the first duty cycle control signal;, 'a feedback controller coupled to the converter and comprisingwherein the switching mechanism selectively couples one of the compensator and the sampler with the pulse-width modulator based at least in part on a dimming signal.2. The driver of claim 1 , wherein the converter further comprises a switch network comprising a first operating state and a second operating state and ...

CLOCK SIGNAL CONTROLLER

The present invention provides a clock signal controller structure. The invention allows for the large-skew clock signals to be converted into small-skew clock signals. The technical solution of the present invention may be adopted to synchronize two large-skew clock signals. 1. A clock signal controller , comprising:a first clock combiner comprising a plurality of transistors; anda second clock combiner comprising a plurality of transistors, whereina first clock signal input into the first clock combiner is faster than a second clock signal input into the second clock combiner,a trailing edge of a first single clock signal outputted by the first clock combiner corresponds to a rising edge of the first clock signal, and its rising edge corresponds to the trailing edge of the second clock signal, anda trailing edge of a second single clock signal outputted by the first clock combiner corresponds to the rising edge of the second clock signal, and its rising edge corresponds to the trailing edge of the first clock signal.2. The clock signal controller of claim 1 , wherein the plurality of transistors of the first clock combiner comprises a first transistor claim 1 , a second transistor claim 1 , a third transistor and a fourth transistor.3. The clock signal controller of claim 2 , wherein the first transistor is a P-type transistor claim 2 , a source of the first transistor is connected to a working level claim 2 , a drain of the first transistor is connected to a first connecting point claim 2 , and a gate of the first transistor is connected to a first clock signal input end.4. The clock signal controller of claim 3 , wherein the second transistor is an N-type transistor claim 3 , a source of the second transistor is connected to the first connecting point claim 3 , a drain of the second transistor is connected to a reference level claim 3 , and a gate of the second transistor is connected to the first clock signal input end.5. The clock signal controller of claim 4 ...

Serializer, data transmitting circuit, semiconductor apparatus and system including the same

A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

Output circuit

A drive assist circuit includes a pulse generation circuit which outputs a pulse to control an assist operation when an assist signal makes a first transition corresponding to a transition of a gate signal from a high level to a low level. The pulse generation circuit includes a delay circuit provided in one of two inputs of a logic gate. The delay circuit is configured such that a delay is greater when an input makes a transition corresponding to the first transition of the assist signal, as compared to a case where the input makes a transition corresponding to an inverse of the first transition.

CLOCK RECOVERY DEVICE AND SOURCE DRIVER FOR RECOVERING EMBEDDED CLOCK FROM INTERFACE SIGNAL

In generating a mask signal to be used when a clock signal embedded in an interface signal is recovered, the mask signal may be generated by compensating for a processing delay time occurring in a mask signal generation circuit, thereby reducing the inaccuracy of the mask signal due to the processing delay time. 1. A clock recovery device comprising:a mask signal generation unit configured to generate a mask signal in accordance with a first mask reference signal;a mask duplication signal generation unit configured to generate a mask duplication signal in accordance with a second mask reference signal;a clock extraction unit configured to extract an extraction clock from an interface signal with a clock signal embedded therein in a time interval indicated by the mask signal;a first time-delay control unit configured to generate a compensation clock by time-delaying the extraction clock so that a phase difference between the extraction clock and the mask duplication signal becomes smaller; anda second time-delay control unit configured to generate the first mask reference signal, and the second mask reference signal by time-delaying the compensation clock, and to generate the first mask reference signal and the second mask reference signal so that a phase of the first mask reference signal is ahead of a phase of the second mask reference signal.2. The clock recovery device of claim 1 , whereinthe mask signal generation unit generates a rising edge of the mask signal in accordance with the first mask reference signal through a first internal circuit,the mask duplication signal generation unit generates a rising edge of the mask duplication signal in accordance with the second mask reference signal through a second internal circuit, anda processing delay time of the first internal circuit and a processing delay time of the second internal circuit are substantially same.3. The clock recovery device of claim 1 , wherein one period of the interface signal is divided into ...

Device for detecting margin of circuit operating at certain speed

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result. 1. A device for detecting a margin of a circuit operating at a circuit operating speed , the device comprising:a signal generating circuit configured to generate an input signal including predetermined data at a beginning of a detection process;a first adjustable delay circuit coupled to the signal generating circuit, and configured to delay the input signal by a first delay amount to generate a delayed input signal;a circuit under test (CUT) coupled to the first adjustable delay circuit, and configured to perform a predetermined operation after the beginning of the detection process to generate a to-be-tested signal according to the delayed input signal, wherein the predetermined operation is based on a predetermined operation timing;a second adjustable delay circuit coupled to the CUT, and configured to delay the to-be-tested signal by a second delay amount in the detection process to generate a delayed to-be-tested signal;a comparison circuit coupled to the second adjustable delay circuit, and ...

DELAY CONTROL SYSTEM HAVING TOLERANCE FOR PVT VARIATION

A delay control system has a tolerance for process, voltage, and temperature (PVT) variations. The delay control system includes a detection compensation block configured to receive a constant current source, detect a PVT variation, and supply a compensation current; a current summation block configured to receive the compensation current and supply a summation current; a current-to-voltage converter configured to receive the summation current and supply a bias voltage depending on the amount of the summation current; and a delay chain block configured to adjust a delay time in response to the bias voltage. Related methods are also described.

DRIVING SIGNAL CONTROL CIRCUIT AND DRIVING APPARATUS

A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal. 1. A driving signal control circuit , comprising:a discharge circuit configured to compare a monitored voltage and a reference voltage, and generate a discharge signal, the monitored voltage being proportional to a core voltage;a counter circuit configured to perform an up/down count operation according to the discharge signal, and generate a count signal; anda control circuit configured to generate a driving signal which has an enable period that is proportional to the count signal.2. The driving signal control circuit according to claim 1 , wherein the counter circuit comprises:a start signal generator configured to generate a clock signal based on a command signal;a flag signal generator configured to generate a flag signal based on the discharge signal; anda counter configured to count the flag signal based on the clock signal, and generate the count signal.3. The driving signal control circuit according to claim 2 ,wherein the counter comprises a plurality of count circuits which perform the up/down count operation,wherein the count circuits are electrically coupled sequentially, andwherein the respective count circuits generate a plurality of count bits comprising the count signal.4. The driving signal control circuit according to claim 3 , wherein the counter circuit further comprises:a counter controller configured to provide a count output signal based on the clock signal and a carry output signal.5. The driving signal ...

MUX-BASED DIGITAL DELAY INTERPOLATOR

A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal. 18-. (canceled)9. A digital delay interpolator comprising: be input with first and second input voltages, one of the first and second input voltages being delayed with respect to the other, and', 'receive a respective selection signal;, 'at least one array of multiplexers, each multiplexer configured to'}a plurality of output lines respectively coupled to said at least one array of multiplexers; andan output terminal configured to be coupled in common to said plurality of output lines;each multiplexer of said at least one array thereof being configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.10. The digital delay interpolator of wherein said at least one array of multiplexers comprises a single array of multiplexers to define a single-stage digital delay interpolator.11. The digital delay interpolator of wherein said at least one array of multiplexers comprises a first set claim 9 , and a second set; wherein each multiplexer of said first set comprises a first input terminal configured to receive the first input voltage claim 9 , and a second input terminal configured to receive the second input voltage; and wherein each multiplexer of said second set comprises a first input terminal configured to receive the ...

PHASE DIFFERENCE QUANTIZATION CIRCUIT, DELAY VALUE CONTROL CIRCUIT THEREOF, AND DELAY CIRCUIT

A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to N(N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an A(2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1delay unit and a phase of a second output signal generated from delaying the input signal with the Adelay unit and the replica delay unit and configured to control a delay value of the Adelay unit using a comparison result. 19-. (canceled)10. A delay circuit comprising:a first delay unit configured to add a delay of two unit delays;a second delay unit configured to add a delay of one unit delay;a replica delay unit replicating the second delay unit; anda delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with the first delay unit and a phase of a second output signal generated from delaying the input signal with the second delay unit and the replica delay unit and configured to control a delay value of the second delay unit using a comparison result.11. The delay circuit of claim 10 , wherein the second delay unit is configured to delay the input signal using a capacitor section and the delay control unit is configured to control a capacitance of the capacitor section of the second delay unit.12. The delay circuit of claim 10 , wherein the delay control unit comprises:a phase comparing section configured to compare the phase of the first output signal and the phase of the second output signal and output an up/down signal; anda control section configured to generate delay codes for controlling the delay value of the second delay unit and the replica delay unit in response to the up/down signal.13. A delay circuit comprising:a first delay unit configured to add a delay ...

POWER CONVERTER WITH PHASE ERROR CORRECTION

A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. The power converter circuit may generate a reference clock signal using a system clock signal and a voltage level of the switch node. The reference clock signal may be used to initiate a charge cycle, whose duration may be based on generated ramp signals. 1. An apparatus , comprising:a voltage regulator circuit that includes a switch node coupled to a regulated power supply node via an inductor, wherein the voltage regulator circuit is configured to source a charge current to the switch node during a charge cycle; and determine a phase difference between a system clock signal and a voltage level of the switch node;', 'generate a reference clock signal using the phase difference;', 'generate a plurality of ramp signals using the voltage level of the switch node;', 'initiate the charge cycle using the reference clock signal; and', 'halt the charge cycle using the plurality of ramp signals., 'a control circuit configured to2. (canceled)3. The apparatus of claim 1 , wherein to generate the reference clock signal claim 1 , the control circuit is further configured claim 1 , based on the phase difference claim 1 , to selectively charge or discharge a capacitor.4. The apparatus of claim 3 , wherein the control circuit is further configured to generate a control current using a voltage level across the capacitor.5. The apparatus of claim 4 , wherein the control circuit is further configured to delay the system clock signal to generate the reference clock signal.6. The apparatus of claim 1 , wherein the control circuit is further configured to halt the charge cycle using a result of a comparison of a voltage level of the switch node and a reference voltage level.7. A method claim 1 , comprising:receiving, by a power converter circuit, a system clock signal, wherein the power converter circuit includes a switch node coupled ...

Digital Timer Delay Line with Sub-Sample Accuracy

The present document relates to a timer which is counter-based and uses an asynchronous circuitry to improve the accuracy between the available clock cycles. In particular, a timer is presented which may comprise a first timer circuit configured to receive a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal. The first timer circuit may be configured to determine, in a capture phase, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal.

Semiconductor module, vehicle and elevator

A semiconductor module of an embodiment includes a first switching device, a first gate drive circuit controlling ON/OFF of the first switching device, a second switching device connected with the first switching device in parallel or in series, a second gate drive circuit controlling ON/OFF of the second switching device, and a control circuit controlling timing of transmitting a gate drive signal from the first gate drive circuit and transmitting a gate drive signal from the second gate drive circuit by synchronizing the first gate drive circuit and the second gate drive circuit.

VOLTAGE GENERATING SYSTEM, VOLTAGE GENERATING CIRCUIT AND ASSOCIATED METHOD

A voltage generating system including: a voltage source, a clock generating circuit, and a voltage generating circuit. The voltage source generates a reference voltage. The clock generating circuit generates a first clock signal and a second clock signal according to the reference voltage. The voltage generating circuit including an output circuit and a switch circuit. The output circuit generates a control signal at a control node according to the first clock signal and the reference voltage, generates an output signal at an output node according to the second clock signal and the reference voltage. An absolute value of an amplitude of the output signal is greater than the reference voltage while an absolute value of an amplitude of the control signal is greater than the reference voltage. The switch circuit selectively outputs the output signal to an output terminal according to the control signal. 1. A voltage generating system , comprising:{'sub': 'ref', 'a voltage source, arranged to generate a reference voltage (V);'}{'sub': H', 'L, 'b': 2', '1, 'a clock generating circuit, arranged to generate a first clock signal (CLK) and a second clock signal (CLK) according to the reference voltage, wherein a first amplitude (VDD) of the first clock signal is greater than the reference voltage and a second amplitude (VDD) of the second clock signal; and'} [{'sub': out', 'ctrl, 'an output node (N) and a control node (N);'}, {'sub': 'out', 'an output circuit, coupled to the clock generating circuit, wherein the output circuit is arranged to generate a control signal (CTRL) at the control node according to the first clock signal and the reference voltage, generate an output signal (V) at the output node according to the second clock signal and the reference voltage, and an absolute value of a third amplitude of the output signal is greater than the reference voltage while an absolute value of a fourth amplitude of the control signal is greater than the reference voltage; and ...

SEMICONDUCTOR APPARATUS RELATED TO RECEIVING CLOCK SIGNALS HAVING VARIABLE FREQUENCIES, AND SYSTEM INCLUDING THE SEMICONDUCTOR APPARATUS

A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus. 1. A system comprising:an external apparatus configured to provide a first clock signal and a second clock signal; anda semiconductor apparatus configured to communicate with the external apparatus by receiving the first clock signal and the second clock signal,wherein the first clock signal has a first frequency and a second frequency higher than the first frequency, and the second clock signal has a third frequency lower than the first frequency.2. The system of claim 1 , wherein the second frequency is double the first frequency and the first frequency is double the third frequency.3. The system of claim 1 , wherein the first clock signal is transferred from the external apparatus to the semiconductor apparatus when a synchronized signal is transferred between the external apparatus and the semiconductor apparatus claim 1 , and the synchronized signal is transferred in synchronization with the first clock signal.4. The system of claim 1 , wherein the external apparatus provides the first clock signal including at least one pulse having the first frequency and a pulse having the second frequency.5. The system of claim 1 , wherein the semiconductor apparatus includes:a frequency divider configured to generate at least one internal clock signal by dividing a frequency of the first clock signal; anda phase detector configured to generate a phase detection signal by comparing phases between the at least one internal clock signal and the second clock signal.6. The system of claim 5 , wherein the phase detection signal is feedback to the external apparatus claim 5 , and the external apparatus changes a phase of the first clock signal based on the phase detection signal.7. The system of claim 5 , wherein the semiconductor ...

SYSTEMS AND METHODS FOR OPTICAL DISTANCE MEASUREMENT

Systems and methods for performing optical distance measurement are provided. In one aspect, a system for measuring a distance to an object comprises a light emitter configured to emit an outbound light pulse, and a light sensor configured to receive a returning light pulse reflected from the object and output an analog pulse signal representing the returning light pulse. The system also comprises a field-programmable gate array (FPGA) coupled to the light sensor. The FPGA is configured to convert the analog pulse signal to a plurality of digital signal values, and generate a plurality of time measurements corresponding to the plurality of digital signal values. The system also comprises a controller configured to calculate the distance to the object based on the plurality of digital signal values and the plurality of time measurements. 1. A system for measuring a distance to an object , the system comprising:a light emitter configured to emit an outbound light pulse;a light sensor configured to receive a returning light pulse reflected from the object and output an analog pulse signal representing the returning light pulse; convert the analog pulse signal to a plurality of digital signal values, and', 'generate a plurality of time measurements corresponding to the plurality of digital signal values by sampling each digital signal value, wherein a time resolution of the sampling is shorter than a clock period of the FPGA; and, 'a field-programmable gate array (FPGA) coupled to the light sensor and configured toa controller configured to calculate the distance to the object based on the plurality of digital signal values and the plurality of time measurements.2. The system of claim 1 , wherein the light emitter claim 1 , light sensor claim 1 , FPGA claim 1 , and controller are carried by an unmanned vehicle claim 1 , an autonomous vehicle claim 1 , or a robot.3. The system of claim 1 , wherein the time resolution is at least 5 times shorter than the clock period of ...

Modified Flying Adder Architecture

According to an embodiment, an improved flying adder circuit, comprises a fine clock, a coarse pulse clock, a rising edge triggered output connected to both the fine clock and the coarse pulse clock, a pulse clock connected to the rising edge triggered output, an adder, a 12-bit register situated to receive a signal from the adder and the pulse clock, and a single bit register situated to receive a signal from the pulse clock. 1. A flying adder circuit , comprising:a fine pulse clock;a coarse pulse clock;a rising edge triggered output circuit, connected to both the fine pulse clock and the coarse pulse clock to provide a pulse train;an adder;a register/accumulator situated to receive a signal from said adder and said pulse train; anda single bit register situated to receive a signal from said rising edge triggered output.2. The flying adder circuit of claim 1 , wherein the fine clock has a 256 picosecond period.3. The flying adder circuit of claim 1 , wherein the fine clock has 16 picosecond steps.4. The flying adder circuit of claim 1 , wherein the coarse pulse clock has a period between approximately 3840 picoseconds and 4096 picoseconds.5. The flying adder circuit of claim 1 , wherein the coarse pulse clock has 256 picosecond steps.6. The flying adder circuit of claim 1 , wherein said fine pulse clock outputs a number of fine pulse clock pulse trains selectable by a first multiplexer and wherein the fine pulse clock pulse train selected by said first multiplexer is controlled by middle significant bits from said register/accumulator.7. The flying adder circuit of claim 1 , wherein said coarse pulse clock outputs a number of coarse pulse clock pulse trains selectable by a second multiplexer and wherein the coarse pulse clock pulse train selected by said second multiplexer is controlled by most significant bits from said register/accumulator.8. The improved flying adder circuit of claim 1 , further comprising a delay circuit coupled to said rising edge triggered ...

System and method for clocking integrated circuit

A system and method of clocking an integrated circuit (IC) includes determining operating characteristics of the IC. The IC has multiple domains and each domain receives a respective domain clock signal. A skew value is determined for each of the domain clock signals, where each skew value is associated with a respective domain of the IC. The domain clock signals are generated from a reference clock signal and each domain clock signal is skewed from the reference clock according to the respective skew value.

DELAY CIRCUIT

A delay circuit includes a current circuit, a first current mirror circuit, a second current mirror circuit, a self-compensation circuit, and a delay capacitor. A fixed ratio is between the first current and the second current provided by the current circuit. The first current mirror circuit generates a first mirror current in response to the first current. A partial current of the second current flowing through the second current mirror circuit is a base current, and the second current mirror circuit generates a second mirror current in response to the base current. The self-compensation circuit generates a feedback current in response to the second mirror current. The delay capacitor generates a delay signal. The charging current is equal to the second current subtracting the base current. The first mirror current is the sum of the base current, the second mirror current, and the feedback current. 1. A delay circuit comprising:a current circuit for providing a first current and a second current, a fixed ratio being between the first current and the second current;a first current mirror circuit coupled to the current circuit and configured to generate a first mirror current in response to the first current;a second current mirror circuit coupled between the current circuit and the first current mirror circuit, wherein a partial current of the second current flowing through the second current mirror circuit is a base current, and the second current mirror circuit generates a second mirror current in response to the base current;a self-compensation circuit coupled to the second current mirror circuit and configured to generate a feedback current in response to the second mirror current; anda delay capacitor coupled to the second current mirror circuit and the current circuit for receiving a charging current to generate a delay signal;wherein the charging current is equal to the second current subtracting the base current, and the first mirror current is a sum of the ...

DELAY CELL, DELAY LOCKED LOOK CIRCUIT, AND PHASE LOCKED LOOP CIRCUIT

A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell. 1. A delay cell comprising:a first transistor having a first terminal connected to a power supply voltage terminal, a second terminal connected to an output terminal, and a gate terminal connected to an input terminal; anda second transistor having a first terminal connected to a ground terminal, a second terminal connected to the output terminal, and a gate terminal connected to the input terminal,wherein each of the first and second transistors has a fully depleted silicon-on-insulator (FD-SOI) structure, and at least one of a first control voltage is applied to a body of the first transistor and a second control voltage is applied to a body of the second transistors to adjust a delay time of the delay cell.2. The delay cell of claim 1 , wherein the first transistor is a P-type Metal Oxide Semiconductor (PMOS) transistor and the second transistor is an N-type MOS (NMOS) transistor.3. The delay cell of claim 1 , wherein each of the first transistor and second transistor comprises:a body layer;a buried insulation layer on the body layer;a pair of impurity regions disposed on the buried insulation layer to function as source/drain regions;a semiconductor layer disposed between the pair of impurity regions in contact with the buried insulation layer;a gate insulation layer on a top surface of the semiconductor layer opposite to the buried insulation layer; anda gate electrode on the gate insulation layer.4. The delay cell of claim 3 , wherein the body layer of the first transistor is N-type and the pair of impurity regions of the first transistor are P-type claim 3 , ...

PHASE INTERPOLATOR

Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction. 118-. (canceled)19. A method for designing a low power phase interpolator that exhibits high power supply rejection , the method comprising: identifying a positive in-phase current source having a positive in-phase input that is operatively coupled to a positive in-phase control module that receives power from a positive power supply terminal, and produces a positive in-phase output;', 'identifying a positive quadrature phase current source having a positive quadrature phase input that is operatively coupled to a positive quadrature phase control module that receives power from the positive power supply terminal, and produces a positive quadrature phase output;', 'identifying a negative in-phase current source having a negative in-phase input that is operatively coupled to a negative in-phase control module that receives power from a negative power supply terminal, and produces a negative in-phase output;', ' ...

PRINTED CIRCUIT BOARD AND METHOD FOR CONTROLLING SIGNAL TIMING SEQUENCE THEREOF

A printed circuit board includes multiple receiving components for respectively receiving control signals and a transmitting component coupled to the receiving component through multiple leads. Given that the lengths of the leads may be different to each other, the control unit generates the control signals to the leads according to the information about the leads, and firstly delivers at least one of the control signals to the corresponding receiving component(s), and then delivers the remaining control signals to the receiving components after a predetermined time. Furthermore, a method for controlling a signal sequence for the printed circuit board includes generating multiple control signals depending on the information about leads and delivering at least one of the control signals to the corresponding receiving component and delivering the remaining control signals to the remaining receiving components after the predetermined time. 1. A printed circuit board comprising:a plurality of receiving components configured to receive control signals respectively; anda transmitting component coupled to the receiving components through at least two leads respectively, the transmitting component including a control unit equipped with a look-up table storing information of the leads, wherein when the transmitting component employs the control unit to output the control signals to the receiving components, the control unit generates said control signals according to the information of the leads, said control unit delivers at least one of the control signals to the corresponding receiving component through a corresponding lead, and delivers the remaining control signals to the other receiving components through other corresponding leads to delay by a predetermined time;wherein the lengths of the leads are different to each other.2. The printed circuit board according to claim 1 , wherein the information of the leads includes the length of the leads and transmission speeds of ...

Variable Delay Element

A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor. 1. A delay circuit comprising:an input node;an output node;a first transistor of a first conductivity type, the first transistor having a control node coupled to the input node, a first main current node coupled to a first supply voltage node, and a second main current node coupled to the output node;a second transistor of a second conductivity type, the second transistor having a control node coupled to the input node, a first main current node coupled to a second supply voltage node, and a second main current node coupled to the output node; anda biasing circuit having a first differential control voltage output coupled to a further control node of the first transistor and a second differential control voltage output coupled to a further control node of the second transistor.2. The delay circuit of claim 1 , wherein the biasing circuit is configured to adjust a delay of the delay circuit by modifying voltage levels of the first and second differential control voltages.3. The delay circuit of claim 1 , wherein the biasing circuit comprises a differential amplifier.4. The delay circuit of claim 1 , further comprising a control circuit coupled to a control input of the biasing circuit to ...