ЦИФРОВОЕ УСТРОЙСТВО ДЛЯ ФОРМИРОВАНИЯ ПОСЛЕДОВАТЕЛЬНОСТЕЙ УПРАВЛЯЮЩИХ СИГНАЛОВ

Изобретение относится к области цифровой техники и может быть использовано при построении различного рода цифровых автоматов циклического действия. Техническим результатом является экономия количества оборудования, повышение быстродействия, обеспечение регулярности (однородности) структуры. Устройство содержит последовательно соединенные блоки, имеющие по несколько входов и выходов, меняющие свое внутреннее состояние только при воздействии активного уровня на один из входов и не меняющие внутреннее состояние при переходе активного уровня в пассивный, в сочетании с предложенной организацией связей между выходами и входами соседних блоков таких, что после сигнала на очередном входе последующего блока, переключающего этот блок в очередное внутреннее состояние «j» в данном цикле предыдущего блока, следующим сигналом, переключающим последующий блок в следующее внутреннее состояние (j+1) в следующем цикле предыдущего блока, является сигнал, предшествующий по циклу предыдущего блока сигналу, переключающему ...

УСТРОЙСТВО ДЛЯ ВРЕМЕННОГО РАЗДЕЛЕНИЯ ДВУХ ИМПУЛЬСНЫХ СИГНАЛОВ

Использование: в автоматике и импульсной технике в различных системах управления. Сущность изобретения: устройство содержит три элемента И, три элемента задержки, два элемента ИЛИ, элемент ИЛИ-НЕ, два мультиплексора, два счетчика импульсов, генератор импульсов. При полном или частичном совпадении во времени входных импульсов устройство формирует на своих выходах импульсы, равные по длительности входным и разнесенные по времени. При этом задний фронт импульса, проходящего на вход устройства первым, совпадает с передним фронтом второго выходного импульса. Если импульсы приходят на входы устройства одновременно, то приоритетом пользуется импульс, пришедший на первый вход. 2 ил.

ФОРМИРОВАТЕЛЬ ПРЯМОУГОЛЬНОГО ИМПУЛЬСА С ИЗМЕНЯЕМОЙ ДЛИТЕЛЬНОСТЬЮ

Изобретение относится к импульсной технике и может быть использовано для формирования прямоугольных импульсов с изменяемой длительностью в устройствах радиоавтоматики и системах автоматического управления летательными аппаратами. Техническим результатом является обеспечение возможности изменения длительности импульса в пределах от сотен миллисекунд до единиц-десятков секунд путем раздельного управления положением переднего и заднего фронтов формируемого импульса. Устройство содержит два триггера Шмитта, источник колебаний произвольной формы, два переключателя на два положения, источник постоянного напряжения, два делителя напряжения, интегратор, перемножитель сигналов и вычитающее устройство. 2 ил., 1 табл.

ИНТЕГРАЛЬНЫЙ ФОРМИРОВАТЕЛЬ ИМПУЛЬСОВ

Изобретение может быть использовано для управления интегральными микросхемами с зарядовой связью. Цель изобретения - повышение быстродействия, надежности и расширение функциональных возможностей формирователя. Формирователь содержит триггеры 1, 2 и 3, элементы И-НЕ 5, 6 и 7 и шины 15 - 24. Введение триггера 4, элемента И-НЕ 8, элемента НЕ 9, блоков 10 - 13 задания перекрытия импульсов, дешифратора 14 и образование функциональных связей расширяют диапазон регулировки времени перекрытия фазовых импульсов и обеспечивают возможность управления четырехфазными интегральными схемами с зарядовой связью. 2 з.п. ф-лы, 1 табл., 3 ил.

РАЗДЕЛИТЕЛЬ ИМПУЛЬСНЫХ ПОСЛЕДОВАТЕЛЬНОСТЕЙ

Предложен разделитель импульсных последовательностей, образовавших аддитивную смесь импульсов, использующий различение импульсов по длительности. Предложенный разделитель состоит из генератора тактовых импульсов, первого, второго и третьего конъюнкторов, счетчика импульсов, первого и второго формирователя импульса. Выход генератора тактовых импульсов соединен с первым входом первого конъюнктора, второй вход которого соединен с входной клеммой и входом первого формирователя импульса, подключенного своим выходом к входу второго формирователя импульса, одному входу второго и одному входу третьего конъюнкторов. Выход первого конъюнктора соединен со счетным входом счетчика импульсов, выход конечного разряда которого соединен с другим входом второго конъюнктора, а инверснный выход конечного разряда счетчикаа импульсов - с третьим входом первого конъюнктора и с другим входом третьего конъюнктора, подключенного своим выходом к одной выходной клемме. Выход второго формирователя импульса соединен ...

Распределитель импульсов

Формирователь импульсов

Устройство для формирования импульсов

Изобретение относится к импульсной технике и может быть использовано в вычислительной технике и радиотехнике при построении регистров и запоминающих устройств, фильтров и устройств задержки с использованием приборов с переносом заряда на основе коммутируемых конденсаторов.Целью изобретения является повьшение надежности работы. Устройство содержит IK- триггеры 1 и 4, регистр 2 сдвига,тактовую шину 3, управляющую шину 5, триггер 6, D-триггер 7 и делитель 8 частоты. По сравнению с прототипом предложенное устройство содержит меньшее число элементов и связей между ними, что повышает его надежность. В устройстве исключена дополнительная шина установки в нулевое состояние, т.к. из любого произвольного состояния оно всегда приходит в исходное состояние. В устройстве обеспечивается жесткая привязка импульсов управления к тактовым. 1 ил. с (Л ...

УСТРОЙСТВО СИНХРОНИЗАЦИИ

Устройство для временного разделения двух импульсов

Изобретение может быть использовано в измерительной технике, в система.х управления и контроля. Цель изобретения - упрощение устройства и повышение его надежности . Устройство содержит формирователи 1 и 2 импульсов и элемент НЕ 8. Для достижения поставленной цели в устройство введены элементы ЗИ-НЕ 3 и 4 с образованием новых функциональных связей. 3 нл. e.f 5 (Л со о со го 00 о Ср1/2.7 ...

Устройство для временного разделения импульсов записи и считывания реверсивного счетчика

Изобретение может быть использовано в системах автоматики и измерительных приборах. Цель изобретения - расширение функциональных возможностей устройства. Устройство содержит шины 1 и 11 samicK входную и выходную соответственно, шину 3 считывания , элемент ИЛИ-НЕ 5, триггер 6 и формирователь 7 импульсов. Введение шин 2 и 12 записи входную и выходную соответственно, элемента ИЛИ 4, триггера 8, элементов И 9 и 10 и образование новых функциональных свя- . зей обеспечивает возможность работы устройства с двумя информационными последовательностями импульсов, т.е. разделяет во времени импульсы считывания с двумя случайными или закос номерными последовательностями инС/ ) формационных импульсов, появляющихся не одновременно, что обеспечивает надежное считывание информации с реверсивного счетчика.I ил. Ю --J // 4; ...

Трехтактный распределитель

Формирователь импульсов

Изобретение может быть использовано в устройствах управления, электронных коммутаторах. Формирователь содержит счетчик импульсов, запоминающее устройство, выходной регистр, включающий триггеры и элементы И, коммутатор и блок управления, в который входит генератор импульсов. С целью расширения функциональных возможностей за счет обеспечения возможности программирования длительности цикла, прерывания цикла, с последующим продолжением прерванного цикла до его завершения, а также многопрограммной работы формирователя импульсов, в него введены шина запускающего сигнала, шина "Останов", шины кода номера программы, первый и второй триггеры, первый и второй элементы ИЛИ и элемент ИЛИ - НЕ, 1 ил.

Распределитель частотно-импульсных сигналов

Изобретение может быть исгю.пьзо- вано в устройствах приема и временного разделения частотно-импульсных сигналов с временным уплотнением по измерительным каналам. Цель изобретения - по вышение информационной емкости распределителя . Устройство содержит блок I регулируемых задержек, элемент ИЛИ 2, распределители 5 импульсов и регулируемые линии 6 задержки. Введение блока 4 управления и коммутатора 3 с образованием новых функциональных связей иск.иочает из передаваемой информации синхронизирующие импульсы. I з.п. ф-лы, 3 ил. Uynp Bx.i Вых. В.(2 (Л В Вх.З Вь1Х. вх.Н Вых. :i ГС сд 0 установка ...

Двухканальное устройство для временного разделения импульсов

Устройство для выделения импульсов из последовательности

УСТРОЙСТВО ДЛЯ ВВДЕЛЕНИЯ ИМПУЛЬСОВ ИЗ ПОСЛЕДОВАТЕЛЬНОСТИ, содержащее три триггера, два элемента И и элемент НЕ, вход которого соединен с шиной стробирующих импульсов и с входом синхронизации первого триггера, а выход - с входом синхронизации второго триггера, при этом информационные входы первого и второго триггеров подключены к шине единичного уровня, их установочные входы соединены соответственно с инверсным и прямым выходами третьего триггера, а выходы с первыми входами элементов И, вторые входы которых подключены к шине входных импульсов, а выходы являются выходными шгнами устройства , отличающееся тем, что, с целью улучшения стабильности длительности выделяемых импуш сов, в него введены элемент ИЛИ-Н и два дополнительных триггера, причем вход синхронизации первого дополнительного триггера соединен с входом элемента НЕ, выход которого подключен к входу синхронизации второго дополнительного триггера, информационный и установочный входы которого соединены с аналогичными входами первого ...

Селектор импульсов по длительности

Hochgeschwindigkeitsparallel-/Serienschnittstelle

Treiberschaltung für eine kapazitive Last

Abtastschaltung.

DIGITAL TIMING UNIT

VERFAHREN UND SCHALTUNG ZUR VERWENDUNG EINES ADRESSIERBAREN SPEICHERS ALS TAKTPULSGENERATOR

Vorrichtung zur Erzeugung und Verteilung von Taktimpulsfolgen

Anzeigentreiberschaltung.

HF-Verteilnetz

Verfahren und Vorrichtung zur Erzeugung von verzögerten Signalen

Zur Erzeugung von einem gegenüber einem Eingangssignal verzögerten Ausgangssignal (AS) mit definiertem Tastverhältnis wird vorgeschlagen, mindestens zwei gegenüber dem Eingangssignal unterschiedliche verzögerte Zwischensignale (ZS1, ZS2) zu erzeugen und so zu dem Ausgangssignal (AS) zu kombinieren, dass eine ansteigende (bzw. abfallende) Flanke eines ersten Zwischensignals (ZS1) der Zwischensignale eine ansteigende Flanke des Ausgangssignals (AS) und eine ansteigende (bzw. abfallende) Flanke eines zweiten Zwischensignals (ZS2) der Zwischensignale eine abfallende Flanke des Ausgangssignals (AS) bestimmt. Mit einer erfindungsgemäßen Vorrichtung können insbesondere mehrere um einen gleichen Betrag sukzessive verzögerte Versionen eines Eingangstaktsignals mit einem 50%-Tastverhältnis erzeugt werden.

Schaltungsanordnung zum Ansteuern einzelner Schaltungselemente innerhalb einer Mehrzahl von Schaltungselementen mittels codierter Steuersignale

MEMORY REFRESH CONTROL APPARATUS

VERFAHREN ZUR ABLEITUNG EINES N-PHASIGEN TAKTSYSTEMS AUS EINEM EIN-PHASEN-TAKT

Anordnung zur statischen Untersetzung einander antivalenter binaerer Impulsfolgen

Aktiver Taktbaum für Datenumsetzer

Taktverteilungssystem zum Verringern von Zeitfehlanpassungen in einem Umsetzer, der ausgestaltet ist, zwischen einem analogen Signal und einem digitalen Signal umzusetzen, und wo Anforderungen an die zeitliche Steuerung strenger sind, da der Umsetzer in einem Gigahertz-Frequenzbereich arbeitet, das Folgendes aufweist: mehrere Taktempfänger, die ein Taktsignal mit einer Frequenz empfangen, die mindestens ein Gigahertz (Ghz) beträgt, einen mehrstufigen Taktbaum, der einen Eingang für ein gemeinsames Taktsignal und Ausgänge aufweist, die an die Taktempfänger gekoppelt sind, wobei jede Stufe eine Anordnung von Taktpuffern aufweist, wobei Ausgänge von mehreren Taktpuffern von einer gemeinsamen Stufe mit mindestens einer Verbindung zusammen verbunden sind, die ausgestaltet ist, um gekoppelt zu sein, um Zeitfehlanpassungen in dem Umsetzer zu verringern und eine Signalumsetzung mit hoher Geschwindigkeit zu ermöglichen.

Quadraturmodulator

Schieberegister und Treiberverfahren für dieses sowie LCD-Treibervorrichtung mit einem solchen

Es wird ein Schieberegister mit mehreren Stufen zum Verschieben eines Startimpulses (Vst) zum Ausgeben eines verschobenen Startimpulses an eine nächste Stufe angegeben, wobei jede der mehreren Stufen Folgendes aufweist: DOLLAR A - einen Pullup-Transistor (T5), der durch einen ersten Knoten (Q) gesteuert wird, um ein erstes Taktsignal (C1) an eine Ausgangsleitung (OUT) zu legen; DOLLAR A - einen ersten Pulldown-Transistor (T6), der durch einen zweiten Knoten (QB) gesteuert wird, um eine erste Ansteuerspannung (VSS) an die Ausgangsleitung zu legen; DOLLAR A - eine Steuerungseinrichtung (10) zum Steuern des ersten und des zweiten Knotens und DOLLAR A - einen Kompensationskondensator (CC), der zwischen den ersten Knoten und eine Eingangsleitung für ein zweites Taktsignal (/C1) geschaltet ist, das vom ersten Taktsignal verschieden ist.

SPEICHEREINRICHTUNG MIT MEHREREN BISTABILEN KIPPSTUFEN

SCHALTUNGSANORDNUNG ZUR ERZEUGUNG VON GLEICH LANGEN, UM 180 GRAD VERSETZTEN IMPULSEN

Schaltungsanordnung zur Ansteuerung der Ruecksetz-Eingaenge einer Mehrzahl von bistabilen Kippstufen

SCHALTUNGSANORDNUNG ZUR REGELUNG DER SCHALTVERZOEGERUNG UND/ODER VERLUSTLEISTUNGSAUFNAHME VON INTEGRIERTEN FET- SCHALTKREISEN

Interpolationsschaltung, DLL-Schaltung und integrierte Halbleiterschaltung

Interpolationsschaltung, die erste und zweite Signale empfängt, zum Erzeugen eines Ausgabesignals mit einer Phase, die einem Wert entspricht, der durch Teilen einer Phasendifferenz zwischen dem ersten und dem zweiten Signal in Übereinstimmung mit einem Teilungsverhältnis erhalten wird, das durch ein eingegebenes Steuersignal gesetzt wird, wobei die Interpolationsschaltung eine Signalverlaufssyntheseeinheit und eine Vorspannungssteuereinheit aufweist; wobei die Signalverlaufssyntheseeinheit enthält: eine Logikschaltung, die erste und zweite Signale empfängt, zum Ausgeben des Ergebnisses einer vorbestimmten Logikoperation, die auf die ersten und zweiten Signale angewandt wird; ein erstes Schaltbauteil, das zwischen einer ersten Stromzufuhr und einem Knoten eingefügt ist, der mit einem Ausgabeanschluss verbunden ist, von dem das Ausgabesignal zugeführt wird, wobei es einen Steueranschluss zum Empfangen eines Ausgabesignals von der Logikschaltung hat, um dieses erste Schaltbauteil ein- und ...

Steuerbarer Taktimpulserzeuger

Interpolationsschaltung, DLL-Schaltung und integrierte Halbleiterschaltung

Es wird eine Interpolationsschaltung zum Erzeugen eines Ausgabesignals mit einer Verzögerungszeit offenbart, die einem Wert entspricht, der durch Durchführen einer inneren Teilung einer Phasendifferenz durch ein voreingestelltes inneres Teilungsverhältnis zwischen eingegebenen ersten und zweiten Signalen. Die Interpolationsschaltung enthält eine Signalverlaufssyntheseeinheit (1) und eine Vorspannungssteuereinheit (2). Die Signalverlaufssyntheseeinheit (1) enthält ein ODER-Gatter (OR1), das erste und zweite Signale (FINO und FINE) zum Ausgeben des logischen ODER der beiden Eingangssignale empfängt; ein erstes Schaltbauteil (MP1), das zwischen einer ersten Stromzufuhr (VDD) und einem mit einem Ausgabeanschluss (OUT) verbundenen Knoten (N1) eingefügt ist und das durch das Ausgabesignal des ODER-Gatters ein- und ausgeschaltet wird; eine Reihenschaltung, die eine erste Stromquelle (MN2) und ein zweites Schaltbauteil (MN4) aufweist, das durch das erste Signal (FINO) ein- und ausgeschaltet wird ...

Multistable circuits

... 1,120,994. Electronic counters. BOOKHIRST IGRANIC Ltd. 13 July, 1965] 13 July, 1964], No. 28224/65. Heading G4A. A multi-stable circuit operates in the manner of a Johnson counter to apply +ve potential to one half of the outlets and - ve potential to the other half. A six-stage circuit for controlling a threephase inverter such as described in Specification 1,047,917 comprises silicon-controlled rectifiers SOR1-SOCR6, the anode circuits of which halves of primary windings Pa so arranged that, considered as a ring, diametrically opposite windings are on a common core, as indicated by dashed lines TR1-TR3. Closure of switches S1, S2 causes unijunotion oscillator UT to pulse diode 17 and capacitor 18 to render SCR1 conducting. A potential applied to input sets UT oscillating at a frequency dependent on the potential to produce waveform VB1 which is applied in common to the gating circuits such as D1, C1 of all stages. SCR2 and SCR3 turn on to the first two pulses after which the system operates ...

PULSE GENERATOR

... 1333762 Pulse generators INTERNATIONAL BUSINESS MACHINES CORP 3 Dec 1970 [22 Dec 1969] 57391/70 Heading H3P A pulse generator comprises a reference source 10, a frequency divider 22 for deriving a train of timing pulses from the source 10 output, controllable delay circuit 24, 26 or 28 for delaying the timing pulses by a predetermined amount, and an output circuit 36, 38 or 40 adapted when enabled by the delayed timing pulses to develop an output pulse from each trigger pulse derived from the source 10 and whose beginning is coincident with a predetermined reference transition, e.g. a positive transition at a zero crossing, in the source 10 output. Thus by using a plurality of delay circuits 24, 26, 28 and a plurality of output circuits 36, 38, 40, a plurality of output pulse trains in precise timed relationship to one another may be developed. Adjustable fine delays 48, 50, 52 may be provided to control the time of occurrence of the output pulse trains.

DIGITAL PHASE SHIFTER

A digital phase shift arrangement comprising a frequency multiplier (10) to which an input signal can be applied, frequency division means to which the output of the multiplier is applied, the frequency division means (11,12) being arranged to produce a plurality of outputs of identical frequency each delayed by a different amount with respect to the input frequency and means (13,14) for selecting one of the outputs of the frequency division means.

Frequency-multiplying delay locked loop

A frequency multiplier circuit (100) comprising a delay line receiving at one end thereof a reference clock (102) for generating clock tap outputs from respective ones of a plurality of period matched delay elements (101); a clock combining circuit (TOG) responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period. The delay line may be included in a delay-locked loop to match the period of the delay elements (101). A plurality of combining circuits cells (TOG) are provided, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each cell providing complementary outputs. A selector (106) is responsive to a selection control signal from a phase detector (112) for selecting an output from one of a pair of complementary outputs of one of the combining cells.

A drive circuit including a voltage booster

A drive circuit (10) comprises: a logic block (3) connected between a source of a first voltage (VDD) and a source of a second voltage (VSS), and a sampler (5) having a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output (O). The drive circuit further comprises a voltage booster (11) having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage (VDD) and the source of the second voltage (VSS). The logic block (3) may be, but is not limited to, a shift register.

Clock divider

A frequency divider receiving L(=4) phase clock signals has L counters 22 and counter controllers 24 connected in series. The output is provided by an OR gate 42. Each counter 22 counts an integer (N-D), D being a number which allows the counter to settle, and each counter controller 24 provides a delay of D to the output of the counter 22. ...

ANALOG TIMING GENERATOR AND METHOD

Improvements in or relating to clock pulse distribution

... 1,099,495. Semi-conductor oscillator circuits. INTERNATIONAL COMPUTERS & TABULATORS Ltd. April 12, 1965 [April 29, 1964], No. 17884/64. Heading H3T. In a timing system, particularly for distributing clock pulses in a high speed computer, a master signal generator is coupled via a transmission line to at least one slave generator the length of the transmission line being such that any signals reflected from the remote end arrive at the master generator in phase with its output. As shown in Fig. 2, 100 Mc/s. pulses from a master oscillator 9 are fed via matched transmission lines 12, 13 to synchronize slave oscillators 10, 11, 15. A further transmission line 20 which provides a delay of an appropriate integral multiple of half the period of the master oscillator 9 provides load sharing. The lines 12, 13 maybe coaxial or strip lines and may have different lengths so that slave oscillators 10, 11 provide two-phase outputs. The oscillators 9, 10, 11 may be transistorized blocking oscillators ...

OSCILLATION GENERATION

Digital signal delay circuit

A digital signal delay circuit which delays a plurality of digital input signals by a use of a single delay device group and a plurality of delay sections is disclosed. The delay device group generates a plurality of different phase clock signals. Each of the delay sections includes selection means for selecting one of the clock signals from the delay device group and latch means for latching the digital input signal in response to the output signal from the selection means. The output signal from the latch means is the delayed input signal, and a delay time is controlled by the selection means. The delay device group is used in common for the plurality of delay sections, so that the digital signal delay circuit is simple and inexpensive in construction.

Improvements in or relating to generators for generating time-related signals

A voltage comparator with several parallel output channels connected to respective threshold circuits is responsive to the increase of the charge voltage of a capacitor with a linear variation of output currents in the channels. The different output currents, equal or different to each other but all with the same variation rates, are converted into control voltages of the threshold circuits, which are of different value but change with identical rates, so as to reach the threshold value of the respective threshold circuits at different times. From the outputs of the threshold circuits there exit the desired timely connected synchronously related signals, which may be either simple leading or trailing fronts or pulses.

Phase disoverlapper for MOS integrated circuits particularly for controlling switched-capacitor filters

A two-phase clock disoverlapper comprises a NAND gate and a NOR gate each provided with a first input clock signal and a second input controlled by a circuit suitable to supply the delayed form of the clock signal, consisting of an analog delay circuit (38,40,42) provided with the input clock signal, the two phase clock outputs being provided at the outputs of the NAND (30) and NOR (32) gates and via further inverters (44,46) as necessary. The first inverter (38) of the analog delay circuit may be a CMOS gate having high ON resistance transistors.

Improvements in or relating to delay circuits

... 756,285. Pulse delaying circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 14, 1954, No. 26657/54. Class 40 (6). [Also in Group XIX] A delay circuit, for use in a digital computer (see Group XIX), receives input data indicative pulses at a terminal B, Fig. 1, and synchronizing pulses at a terminal A, the pulse train being as shown in Fig. 2, and as a result produces a pulse train at E corresponding to the input train at B but delayed by one unit of time, which is amplified by a double triode 35 to give an output at H equivalent to the input train at B delayed by one unit of time, there being feed-back from point H to point E via a resistor 48 for pulse-shaping purposes. The leading negative edge of a data indicative pulse applied to terminal B tends to cause a negative pulse at point C' but this is prevented by a rectifier 23, and the leading edge therefore has a negligible effect. The positive-going trailing edge however does have some effect and causes points C and D to rise ...

Switching apparatus

... 1,105,322. Switching means. JAMES SCOTT (ELECTRONIC ENGINEERING) Ltd. May 20, 1965 [April 13, 1964], No.15153/64. Heading G4D. When a relay e.g. RL2 Fig.2 of one set of control devices is energized an associated switch RL2/B in the next control device changes state so that a capacitor C3 is charged, discharging, when the relay RL2 is cut out, to energize the next relay RL3. Thereafter the relays are energized in succession, the relay RLN changing the switch RLN/B in the first control device so that the process is repeated. In the form shown the even and odd relays are connected to different outputs of a bi-stable device so that as it changes state the relay which has been energized is cut out. A switch 53A may be positioned for either automatic scanning or manual selection. Lamps L1-LN are illuminated when the associated relay is energized. Successive control devices may be by-passed by a switch S5 which may be used to connect, for example, the input to relay RL3 to relay RL (N-1) as shown ...

Process and apparatus for generating series of electrical pulses

... 833,454. Electron beam apparatus. KIENZLE APPARATE G.m.b.H. June 11, 1956 [June 13, 1955 ; Aug. 8, 1955], No. 17919/56. Class 39(1). [Also in Groups XIX and XL(c)] Fig. 4 shows an electron beam deflector tube 401 used in a circuit for producing a predetermined number of output pulses by multiplication from an input pulse, (see Group XL(c)). The beam 408 is normally incident on rest anode 406 a saw tooth pulse Je sweeps the beam over anodes 411 . . . 420 to produce negative output pulses from them which are fed to output line 404. The number of pulses in the output series is controlled by a blocking pulse on control grid 407 of the tube the duration of which corresponds to the time required by the beam to sweep over a given number of anodes. In the modification shown in Fig. 5, the beam deflector tube 501 has a slotted grid 508 and a common anode 504. The beam is deflected by saw tooth pulse Je so that it touches in turn the slots and bridges of grid 508 and produces a pulse series on the ...

LOGIC CIRCUITS

CLOCK GENERATOR FOR A INTERGRIERTE CIRCUIT

STEUERPULSGENERATOR ZUM ZYCLISCHEN ERZEUGEN EINER SIGNALTECHNISCH SICHEREN FOLGE VON STEUERIMPULSEN

ANORDNUNG ZUR TAKTERZEUGUNG FUER LADUNGSGEKOPPELTE SCHALTUNGEN

SCHALTUNGSANORDNUNG ZUR BILDUNG VON PERIODISCHEN IMPULSMUSTERN, INSBESONDERE ZUR STEUERUNG IMPULSGESTEUERTER HALBLEITER-SCHALTELEMENTE

ARRANGEMENT FOR GENERATING SYNKRONISIERSIGNALEN WITH VERY LOW JITTER

STORAGE FACILITY WITH SEVERAL BISTABILE TRIGGER STAGES

TAX PULSE GENERATOR FOR ZYCLI PRODUCING OF A SIGNAL-TECHNICALLY SAFE ONE CONSEQUENCE OF CONTROL PULSES

BLOCKING CIRCUIT FOR THE PHASE FRAGMENTATION AND LEVEL CONVERSION OF AN TTL INPUT SIGNAL WITH FIELD-EFFECT TRANSISTORS AND APPROPRIATE OPERATING PROCEDURE.

SYNCHRONOUS MULTI-PHASE CLOCK DISTRIBUTING SYSTEM

HOCHGESCHWINGKEITSDATENERFASSUNGSSCHALTUNG FOR DIGITAL EQUIPMENT

Switching configuration for the production temporal distances given by impulses with

Electronic frequency divider

PRODUCTION SIGNALS OUT OF PHASE OF TWO BY 90 DEGREES

SIGNALLING AND TIMING DEVICE SIGNALLING AND TIMING DEVICE

CLOCK GRID SKEW REDUCTION TECHNIQUE USING BIASABLE DELAY DRIVERS

CLOCK DISTRIBUTOR CIRCUIT FOR MAINTAINING A PHASE RELATIONSHIP BETWEEN REMOTE OPERATING NODES AND A REFERENCE CLOCK ON A CHIP

Clock generator for integrated circuit

Apparatus for triggering a plurality of thyristor devices

MULTIPLE PHASE CLOCK BUFFER MODULE WITH NON-SATURATED PULL-UP TRANSISTOR TO AVOID HOT ELECTRON EFFECT

CIRCUIT FOR GENERATING SCANNING PULSES

DI-PHASE PULSE RECEIVING SYSTEM

MULTIPLE PHASE CLOCK BUFFER MODULE WITH NON-SATURATED PULL-UP TRANSISTOR TO AVOID HOT ELECTRON EFFECT

A clock buffer circuit for multiple phase complementary clocking signals that receives a plurality of corresponding enabling signals and generates a like plurality of clock signals in response thereto. Each clocking signal is generated by a buffer module including a resistor, a pull-up transistor and a pull-down transistor, which are connected in series between a positive power supply and ground, with the clocking signal being taken from the node between the pull-up and pull-down transistors. In each module, before the clocking signal shifts from a low state to a high, the pull-down transistor is on so that the clocking signal is at a low state. The pull-up transistor in each module is controlled by the corresponding enabling signal and is enabled to begin conducting at the time that the clocking signal is to shift to a high state. The resistor keeps the pull-up transistor in its linear, non-saturated operating regions, which results in an increase in the intrinsic capacitance in the pull-up ...

DIGITAL SIGNAL DELAY CIRCUIT

... 14 A digital signal delay circuit which delays a pluraliry of digital input signals by a use of a single delay device group and a pluraliry of delay sections is disclosed. The delay device group generates a pluraliry of different phase clock signals. Each of the delay sections includes selection means for selecting one of the clock signals from the delay device group and latch means for latching the digital input signal in response to the output signal from the selection means. The output signal from the latch means is the delayed input signal, and a delay time is controlled by the selection means. The delay device group is used in common for the plurality of delay sections, so that the digital signal delay circuit is simple and inexpensive in construction.

SEQUENTIAL SELECTION CIRCUIT

A protective circuit for a sequentially selecting circuit which selects a series of circuit elements electrodes and the like one by one which are generated by a shift register and including a counter for generating a count output corresponding to the total selection number. An input pulse of the shift register is formed according to the output from the counter and the timing pulse and the counter is reset according to the timing pulse and a clock pulse of the selection. With such arrangement when the timing pulse is not generated, the counter will not operate and an effective input pulse to the shift register will not be generated and therefore the shift register will not sequentially read erroneous inputs and a plurality of shift stage outputs will not be generated at the same time. In this manner, the selected circuits, elements, electrodes and drive circuit of power supply will be prevented from being damaged.

TIME-ERROR COMPENSATOR

PULSE CONTROLLED SWITCHING CIRCUITS

A logic circuit is described for controlling a plurality of solid state switches in a wired broadcasting system. The circuit is arranged to distinguish between dialling and reset pulse signals applied to an input, and has a plurality of outputs to which the solid state switches are connected. The circuit sequentially switches the condition of the outputs in response to dial pulse signals, and resets the outputs to a datum condition in response to the reset pulse signal.

GENERATOR OF DELAYED SEQUENCES EMPLOYING SHIFT REGISTER TECHNIQUES

SYSTEM AND METHOD FOR MULTIPLE-PHASE CLOCK GENERATION

Published without an Abstract ...

CIRCUIT ARRANGEMENT FOR PRODUCING CHRONOLOGICALLY CONSECUTIVE CURRENT PULSES

CIRCUIT ARRANGEMENT INCLUDING AN OSCILLATOR

REQUENCY RESPONSIVE MULTI-PHASE PULSE GENERATOR

SWITCHING TRANSIENT SUPPRESSION CIRCUIT

DIFFERENTIAL CLOCK SIGNAL GENERATOR

Disclosed is a differential clock signal generator (100) which processes a first differential clock signal (101) using a combination of differential and non-differential components to generate a second differential clock signal (111). Specifically, the first differential clock signal (101) is converted into a single-ended clock signal (103), which is used either by a finite state machine (105) to generate two single-ended control signals (106,107) or by a waveform generator (705) to generate a single-ended waveform control signal (706). In any case, a deskewer (110), which comprises a pair of single-ended latches (201,202) and either multiplexer(s) (250) or logic gates, processes the first differential clock signal (101), the single-ended clock signal (103), and the control signal(s) (106, 107) in order to output a second differential clock signal(l 11) that is different from the first differential clock signal (101) in terms of delay and, optionally, frequency, but synchronously linked ...

A CLOCK BUFFER WITH ADJUSTABLE DELAY AND FIXED DUTY CYCLE OUTPUT

A clock buffer circuit for a computer system, and a computer system incorporating the same, are disclosed. The clock buffer circuit includes a differential input buffer for receiving the input clock signal, with its output coupled to the input of a phase locked loop (PLL). The switching level of the differential input buffer is adjustable, either by adjusting the DC bias applied to the input clock signal, or by adjusting the reference signal, which changes the point in the cycle of the input clock signal at which the differential buffer switches. The PLL synchronizes its output to an edge of the output of the differential buffer, but maintains the same duty cycle (e. g., 50%). Accordingly, the clock buffer circuit may have its delay adjusted, by modifying a voltage divider, applying a variable voltage, or programmably via a digital-to-analog converter, to match the delays of other clock buffer circuits in the computer system, reducing the clock skew in the system. A sine wave may be used ...

Impulsverteiler.

Signalübermittlungsanlage mit Einrichtung zur Speicherung einer Anzahl von Impulsen.

Dispositif distributeur d'impulsions.

Réseau à transistors

Rfid access method using an indirect memory pointer

A method of operating a memory in an RFID application includes locating a memory pointer at a fixed read/writeable memory location in the memory, determining a range of a pedigree buffer, initializing the memory pointer to a lowest value in the range, providing a second memory location that serves as a trigger address for an indirect write, and writing to a next location in the pedigree buffer by directing write data to the trigger address, which is then automatically written at a location pointed to by the memory pointer.

Serial link voltage margin determination in mission mode

This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.

Hybrid equalization system

A hybrid equalization system includes an equalization device, a target channel impulse response device, a maximum likelihood sequence estimation device and a multiplexer. The equalization device receives a sampled baseband signal and performs an equalization operation thereon for generating first estimated symbols. The target channel impulse response device convolutes the first estimated symbol and a predetermined target channel response function for generating a training symbol corresponding to a target channel. The maximum likelihood sequence estimation device performs a maximum likelihood sequence estimation on the sampled baseband signal trained by first estimated symbols based on the target channel impulse response for generating second estimated symbols. The multiplexer selects the first estimated symbol or the second estimated symbol as an output of the hybrid equalization system according to a selection signal.

Decision directed timing recovery using multi-phase detection

A set of one or more samples is received. Using a first signal processor associated with a first phase offset, a first decision and a first error value are generated using the set of samples. Using a second signal processor associated with a second phase offset, a second decision and a second error value are generated using the set of samples. This includes interpolating the set of samples to obtain a set of interpolated samples at the second phase offset and generating the second decision and the second error value using the set of interpolated samples at the second phase offset. A selection associated with the first decision and the second decision is made based at least in part on the first error value and the second error value.

Analog Continuous-Time Phase Equalizer for Data Transmission

In particular embodiments, a method includes receiving as an input signal a phase-distorted signal or a transmitted-data signal, the phase-distorted signal having been distorted from a phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising transmitted data; generating a non-derivative version of the input signal by applying a delay operator in a continuous-time domain to the input signal; generating a derivative version of the input signal by applying a derivative operator in a continuous-time domain to the input signal; generating a first product signal by multiplying the non-derivative version of the input signal by a first coefficient, the first coefficient being a positive number; generating a second product signal by multiplying the derivative version of the input signal by a second coefficient, the second coefficient being a negative number; and generating an output signal by summing the first and second product signals.

Circuit with passive components for high-speed drive of an optoelectronic device

A circuit for the ultra-quick control of an optoelectronic device, includes a generator of voltage pulses having a pulse duration of less than 400 ps, and a circuit ( 17 ) for shaping control pulses including: an output suitable for being connected in series to a line terminal ( 13 ) of the optoelectronic device, and an input connected to the voltage-pulse generator and receiving the voltage pulses formed by the latter, between a terminal of the input and a terminal of the output, mounted in parallel in relation to one another: a first branch ( 20 ) made up of a passive rectifier circuit ( 22 a, 22 b ) having non-zero threshold voltage and, in series in the first branch in forward direction relative to the line terminal ( 13 ) of the optoelectronic device, a second capacitive branch ( 21 ).

Duty cycle correction

Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value.

Clock signal generators having a reduced power feedback clock path and methods for generating clocks

Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.

Clock generation circuit, display device drive circuit, and control method of clock generation circuit

A clock generation circuit that can reliably recover from a state in which generation of a clock is stopped even during a power-on process and a normal operation. The clock generation circuit includes a clock extraction circuit that extracts an extracted clock from an embedded signal on which a clock and data are superimposed, and a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state.

Duty cycle based phase interpolators and methods for use

Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals.

Sample and hold circuit and the method thereof

A sample and hold circuit and the method thereof are disclosed. The sample and hold circuit may be applied in voltage regulators or other circuits. The sample and hold circuit comprises: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a control circuit configured to receive the input signal and the output signal, and wherein based on the input signal and the output signal, the control circuit generates a digital signal, and wherein the digital signal increases when the output signal is lower than the input signal, and maintains when the output signal is larger than or equal to the input signal; a digital-to-analog converter (DAC) configured to convert the digital signal to the output signal.

Data transfer circuit and method with compensated clock jitter

A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

Active clamp circuit

According to one embodiment, an active clamp circuit includes a first switch element, a first diode, a first resistance, a first control circuit and a second control circuit. The first diode is connected to the first switch element and breaks down by an overvoltage applied to the first switch element. The first resistance is connected to the first diode and detects a current through the first diode. The first control circuit is configured to amplify a voltage across the first resistance and controls a current through the first switch element. The second control circuit is configured to control a conduction of the first switch element in accordance with the voltage across the first resistance.

Automatic blade leveler right tilt-left tilt-null control and method

In one embodiment a dozer blade controller, which may comprise two-way, four-way, or six-way dozer blade position control such as, for example, a two-way control only for blade tilt. In one embodiment, a pulse width control is provided for use in a blade tilt electronic controller, which controls blade tilt independently of movement of the body of the bull dozer. And in another embodiment, a pulse width controller is operable to multiply and/or divide the width of a variable pulse by a preset multiplier factor or divider factor, e.g. by 100 or dividing by 100.

Power analysis module for monitoring an electrical power source

A method of analyzing the characteristics of a power source includes receiving a power source having at least one phase and sensing voltage signals of each phase of the at least one phase. The method includes detecting a zero crossing event of a selected phase of the at least one phase based on the sensed voltage signals of the selected phase. The method also includes determining, using a processor, voltage information for each phase of the at least one phase based on the corresponding sensed voltage signals. The method further includes outputting a series of pulses via a galvanic isolator in response to the zero crossing event. Respective lengths of some or all of the pulses in the series are based on the corresponding voltage information for each of the at least one phase.

Techniques for setting feedback coefficients of a pam-n decision feedback equalizer

A decision feedback equalizer (DFE) for equalizing PAM-N signals comprises a coefficient setting unit for setting a first group of most significant feedback coefficients of the DFE to a predefined value selected from a group of predefined values; a coefficients computation unit coupled to the coefficient setting unit for computing values of feedback coefficients of a second group of feedback coefficients other than the first group of most significant feedback coefficients; a feedback (FB) unit for mitigating, using a complete group of feedback coefficients, effects of interference from data symbols that are adjacent in time to an input data symbol, wherein most significant feedback coefficients of the first group are set to an optimal value computed during an initialization of the DFE and feedback coefficients of the second group are computed by the coefficients computation unit.

INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS

The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal. 1. An input buffer circuit of a semiconductor apparatus , comprising:a bias voltage level control unit configured to output a control bias voltage by decreasing a bias voltage, when a level of the bias voltage becomes higher than a target level;a first buffering unit configured to generate a compare signal by comparing a voltage level of an input signal with a level of a reference voltage, when being activated by receiving the control bias voltage; anda second buffering unit configured to generate an output signal by comparing the voltage levels of the input signal and the compare signal.2. The input buffer circuit of a semiconductor apparatus according to claim 1 , wherein the bias voltage level control unit outputs the bias voltage as the control bias voltage claim 1 , when the bias voltage level is lower than the target voltage level.3. The input buffer circuit of a semiconductor apparatus according to claim 2 , wherein the bias voltage level control unit includes:a level detector configured to generate a detection signal by detecting the bias voltage level;a voltage dropper configured to generate a down voltage by decreasing the bias voltage; anda selector configured to selectively output the bias voltage or the down voltage as the control bias voltage, in response to the detection ...

DIGITALLY CONTROLLED PULSE WIDTH MODULATOR UTILIZING REAL TIME CALIBRATION

A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay. 1. A system for controlling pulse width for electronic devices in real time comprising:a digitally controlled pulse width modulator; anda real time calibration circuit configured to ensure proper fractional delay which is applied to yield a correct duty cycle of said digitally controlled pulse width modulator.2. The system of wherein a defy line circuit is configured to modulate pulse width for a fractional clock cycle delay.3. The system of claim 2 , wherein the delay line circuit comprises a multiplexer delay line with built in decoders.4. The system of claim 1 , wherein said digitally controlled pulse width modulator provides proper duty cycle pulse to a plurality of gate drivers.5. The system of claim 2 , wherein said delay line circuit allows modulation of pulse width for said fractional clock cycle delay.6. The system of claim 2 , wherein said fractional clock cycle delay comprises an upper delay claim 2 , a lower delay and a very fine resolution delay.7. The system of claim 1 , wherein said digitally controlled pulse width modulator allows for digital filtering and programmable resolution.8. The system of claim 1 , wherein digital pulse width modulation is performed with real time calibration to compensate for environmental variations due to radiation claim 1 , aging claim 1 , temperature claim 1 , and voltage changes.9. A method for controlling pulse width for electronic devices in real time comprising:configuring a real time calibration circuit to ensure proper fractional ...

CONTROL OF INPUTS TO A MEMORY DEVICE

A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. 1. A semiconductor integrated circuit device comprising:a command decoder configured to control a memory system by decoding a memory system input signal;interface logic electrically coupled to the command decoder and configured to receive the memory system input signal and a control signal, the interface logic further configured to disable the memory system input signal based at least in part on the control signal;self-refresh logic configured to provide a self-refresh signal based at least in part on an external clock enable signal, the control signal based at least in part on the self-refresh signal; anda path-gate electrically coupled to the self-refresh logic and configured to receive the external clock enable signal and provide the external clock enable signal to the self-refresh logic, the path-gate receiving power from a main voltage generator and a secondary voltage generator in the event that the main voltage generator powers off.2. The semiconductor integrated circuit device of wherein the main voltage generator is configured to provide a generator state signal indicating a voltage level of the main voltage generator.3. The semiconductor integrated circuit device of wherein the control signal is based at least in part on the self refresh signal and the generator state signal.4. The semiconductor integrated circuit device of wherein the control signal causes the interface logic to disable the memory system input signal when the main voltage generator ...

GATE DRIVER ON ARRAY, SHIFTING REGESTER AND DISPLAY SCREEN

The embodiment of the present disclosure relates to a technical field of liquid crystal display, and particularly, to a gate driver on array, a shifting register and a display screen. The gate driver on array comprises: a first TFT, a second TFT, a third TFT, a fourth TFT, a capacitor and a pulling-down module, the pulling-down module is connected among a first clock signal input terminal, a second clock signal input terminal, a first node and an output terminal, and is connected with a low voltage signal terminal, for maintaining the first node and the output terminal being in a low level during a non-operation period of the gate driver on array. Thus, the gate driver on array may achieve a bidirectional scan by designing the functions of the input terminal and the reset terminal in the gate driver on array as being implemented symmetrically, without changing a charging-discharging characteristic of nodes, which ensures a reliability and stabilization of the circuit. 1. A gate driver on array , comprising:a first thin film field effect transistor TFT, a gate of which is connected with an input terminal of the gate driver on array, a drain of which is connected with a power supply voltage terminal VDD, and a source of which is connected with a first node being a pulling-up node;a second TFT, a gate of which is connected with a reset terminal of the gate driver on array, a source of which is connected with a common connection voltage terminal VSS, and a drain of which is connected with the first node;a third TFT, a gate of which is connected with the first node, a drain of which is connected with a first clock signal input terminal, and a source of which is connected with an output terminal;a fourth TFT, a gate of which is connected with a second clock signal input terminal, a drain of which is connected with the output terminal, and a source of which is connected with a low voltage signal terminal;a capacitor which is connected between the first node and the output ...

Method and apparatus for determining duty cycle of a clock in a circuit using a configurable phase locked loop

An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples.

Peak Detector with Extended Range

According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching to devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.

High-speed duty cycle correction circuit

A circuit for correcting a duty-cycle comprises a duty-cycle adjuster for changing a duty-rate of an input clock signal according to a duty control signal; a duty-cycle detector for detecting a duty-rate of an output clock signal based on the input clock signal and the output clock signal from the duty-cycle adjuster; and an algorithm-based digital controller for performing an algorithm according to a duty-rate detection signal outputted from the duty-cycle detector to generate the duty control signal.

PULSE WIDTH ADJUSTING CIRCUIT AND METHOD

The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b, b, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b, b, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate. 1. A pulse width adjusting circuit comprising:a pulse delaying circuit for inputting an inputted pulse signal and for outputting a plurality of different delayed pulse signals;a transmission gate for inputting an inputted pulse signal and controlling the passage of the inputted pulse signal in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals; anda pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal generated on the basis of the inputted pulse signal passing through the transmission gate.2. A pulse width adjusting circuit according to claim 1 , wherein the transmission gate is turned on until the leading edge of the inputted pulse signal passes by applying the two delayed pulse signals claim 1 , is turned off before passage of the trailing edge of the inputted pulse signal claim 1 , and is turned off when the outputted pulse signal reaches a predetermined pulse width or thereafter.3. A pulse width adjusting circuit according to claim 2 , wherein the pulse width setting circuit is maintained in a state displaced by the leading edge of the inputted pulse signal while the outputted pulse signal is a predetermined pulse width when the transmission gate has been turned off.4. A pulse ...

PULSE STRETCHING CIRCUIT AND METHOD

A pulse stretching circuit having a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal, and a pulse adjustment circuit, connected to the pulse delay circuit, receiving the input pulse signal and the delay pulse signal and for outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal. The pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, keeps a state in which the output pulse signal is displaced with the leading edge thus caused longer than a total time of times for both pulse widths of the input pulse signal and the delay pulse signal, and causes a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal. 1. A pulse stretching circuit , comprising:a pulse delay circuit for receiving an input pulse signal and for outputting a delay pulse signal; anda pulse adjustment circuit connected to the pulse delay circuit, the pulse adjustment circuit receiving the input pulse signal and the delay pulse signal and outputting an output pulse signal having a pulse width longer than a pulse width of the input pulse signal, wherein the pulse adjustment circuit causes a leading edge of the output pulse signal in response to a leading edge of the input pulse signal, and a trailing edge of the output pulse signal in response to a trailing edge of the delay pulse signal.2. The pulse stretching circuit according to claim 1 , wherein the pulse adjustment circuit includes:a latch circuit set by a set signal generated from the input pulse signal, reset by a reset signal generated from the delay pulse signal, and causing an output; andan OR circuit connected to the pulse delay circuit and the latch circuit, the OR circuit outputting a logical sum of the input pulse signal, the delay pulse signal, and the output pulse signal of the latch circuit.3. The pulse stretching circuit ...

APPARATUS AND METHOD FOR DUTY CYCLE CALIBRATION

An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal. 1. An apparatus for duty cycle calibration , comprising:an input calibration circuit, calibrating an input clock signal according to a first control signal so as to generate an input calibration clock signal;a delay chain, comprising a plurality of delay units coupled in series, and delaying the input calibration clock signal so as to generate a first delay clock signal at a first node of the delay chain and generate a second delay clock signal at a second node of the delay chain, wherein at least two of the plurality of delay units each have an adjustable delay time which is controlled according to a second control signal;a first comparator, comparing the input calibration clock signal with the first delay clock signal so as to generate the first control signal; anda second comparator, comparing the input calibration clock signal with the second delay clock signal so as to generate the second control signal.2. The apparatus as claimed in claim 1 , wherein the input calibration clock has a duty cycle of about 50%.3. The apparatus as claimed in claim 1 , further comprising:a ...

METHOD FOR GENERATING A MULTIPHASE PWM SIGNAL

A method and a circuit configuration are provided for generating a multiphase PWM signal. For this purpose a number of PWM generators are provided, which respectively have one counter, two comparators and one state memory, each PWM generator outputting a PWM signal, which represents a phase of the multiphase PWM signal, the PWM generators being coupled with one another via multiplexers such that the counters of the PWM generators that are coupled with one another are clocked identically. 110-. (canceled)11. A method for generating at least a multiphase PWM signal , comprising:providing multiple PWM generators which each have one counter, two comparators, and one state memory, wherein the PWM generators are coupled with one another via multiplexers such that the counters of the PWM generators are clocked identically; andgenerating multiple PWM signals using the multiple PWM generators, wherein each PWM generator outputs a respective PWM signal which represents a phase of the multiphase PWM12. The method as recited in claim 11 , wherein all the comparators of the PWM generators are updated simultaneously when the counters are reset.13. The method as recited in claim 12 , wherein the reset of all the comparators is ensured by a synchronization logic circuit.14. The method as recited in claim 12 , wherein the multiphase PWM signal is generated to control an H bridge circuit with arbitrary timeouts.15. The method as recited in claim 12 , wherein a single-phase PWM signal is additionally generated.16. A circuit configuration for generating a multiphase PWM signal claim 12 , comprising:multiple PWM generators which each contain one counter, two comparators, one state memory, and a multiplexer, wherein the multiple PWM generators are coupled with one another via the multiplexers.17. The circuit configuration as recited in claim 16 , wherein a flipflop is used as the state memory.18. The circuit configuration as recited in claim 16 , wherein the multiplexer is a 1-bit ...

Pattern detector for serializer-deserializer adaptation

In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

MEMORY SYSTEM AND DATA TRANSMISSION METHOD

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks. 1. A memory system comprising:a substrate;a plurality of memory chips mounted over the substrate, the plurality of memory chips receiving a first signal and a second signal;a memory buffer mounted over the substrate, the memory buffer including a detection circuit which detects a skew between the first signal and the second signal, and the memory buffer including an adjustment circuit which adjusts a relationship between the first signal and the second signal based on the skew.a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common; anda plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips.2. ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks. 14-. (canceled)5. A semiconductor memory device , comprising:first and second memory banks each of which includes a plurality of sub-memory banks corresponding to data width option information;a plurality of write driving blocks each of which performs a data write operation on each of the sub-memory banks in response to a first or second bank strobe signal;a control signal generating block to generate a plurality of input control signals dependent on access information of the first and second memory banks the data width option information; anda plurality of common input driving blocks each of which transmits data through a common data line to a write driving block, among the plurality of write driving blocks, for each of the first and second memory banks, wherein the plurality of common input driving blocks are activated in response to the plurality of input control signals.6. The semiconductor memory device of claim 5 , wherein enable periods of the plurality of input control signals are defined by enable periods of the first and second bank strobe signals.7. The semiconductor memory device of claim 5 , wherein the first and second memory banks are stacked with each other.8. The semiconductor memory device of claim 5 , wherein the access information of the first and second memory banks corresponds to the first and second bank strobe signals.9. The semiconductor memory device of claim 5 , wherein the common data lines are disposed to cross one of the first and second memory banks.10. The semiconductor memory device of claim 5 , further comprising an activation signal ...

Power quality monitoring apparatus and method thereof

The present invention includes a calculating unit for calculating an absolute value of an applied commercial voltage, an accumulating unit for accumulating the absolute value of the applied commercial voltage per a constant period to output, an extracting unit for sampling an absolute value accumulative maximum value of the commercial voltage for each period and a determining unit for determining a quality of the commercial voltage by using the absolute value accumulative maximum value of the sampled commercial voltage. It has an advantage that the power quality can be monitored at high speed.

PEAK VOLTAGE DETECTOR AND RELATED METHOD OF GENERATING AN ENVELOPE VOLTAGE

A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor. 1. An integrated detector of peaks of an oscillating voltage , comprising:a rectifying circuit, having an input and an output, configured to generate an rectified voltage at the output corresponding to an oscillating voltage at the input;an integrated capacitor configured to store an envelope voltage representing a last detected peak value of the oscillating voltage;a first switch configured to electrically couple said integrated capacitor to the output of the rectifying circuit when the first switch is closed, and to isolate the integrated capacitor from the rectifying circuit when the first switch is open;a comparator configured to compare the envelope voltage with the oscillating voltage, and to generate a command signal that closes said first switch when a difference between the envelope voltage and the oscillating voltage is smaller than a first offset voltage.2. The detector of claim 1 , comprising a clamping circuit configured to clamp said envelope voltage to an instantaneous value of the oscillating voltage claim 1 , the clamping circuit including:a timer configured to be ...

PEAK VOLTAGE DETECTOR AND RELATED METHOD OF GENERATING AN ENVELOPE VOLTAGE

A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. A comparator continually compares the signal with the value stored on the capacitor. When the signal rises to within a selected threshold, relative to the stored value, the comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit configured to close the switch and activate the tracking circuit if more than a selected time passes without production of a command signal, and a circuit configured to control the polarity of a leakage current of the capacitor. 1. An integrated detector of peaks of an oscillating voltage , comprising:a rectifying circuit, having an input and an output, configured to generate an rectified voltage at the output corresponding to an oscillating voltage at the input;an integrated capacitor configured to store an envelope voltage representing a last detected peak value of the oscillating voltage;a first switch configured to electrically couple said integrated capacitor to the output of the rectifying circuit when the first switch is closed, and to isolate the integrated capacitor from the rectifying circuit when the first switch is open;a comparator configured to compare the envelope voltage with the oscillating voltage, and to generate a command signal that closes said first switch when a difference between the envelope voltage and the oscillating voltage is smaller than a first offset voltage.2. The detector of claim 1 , comprising a clamping circuit configured to clamp said envelope voltage to an instantaneous value of the oscillating voltage claim 1 , the clamping circuit including:a timer configured to be ...

SEMICONDUCTOR DEVICE THAT CAN ADJUST PROPAGATION TIME OF INTERNAL CLOCK SIGNAL

Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal. 1. A semiconductor device comprising:a measurement circuit measuring propagation time of an internal clock signal inside the semiconductor device;a delay adjustment circuit adjusting the propagation time of the internal clock signal; anda data output circuit outputting a data signal in response to the internal clock signal.2. The semiconductor device as claimed in claim 1 , wherein the measurement circuit includes a replica circuit of a propagation path of the internal clock signal claim 1 , the measurement circuit measuring the propagation time of the internal clock signal by measuring a time from when a test signal that is different from the internal clock signal is supplied to the replica circuit until when the test signal is output from the replica circuit.3. The semiconductor device as claimed in claim 2 , wherein the time from when the test signal is supplied to the replica circuit until when the test signal is output from the replica circuit is longer than the propagation time of the internal clock signal.4. The semiconductor device as claimed in claim 2 , wherein the measurement circuit further includes a latch circuit that latches the test signal output from the replica circuit at a time when the test signal supplied to the replica circuit is changed from a second logic level to a first logic level after the test signal is changed from the first logic level to the second logic level.5. The semiconductor device as claimed in claim 4 , wherein the measurement circuit further includes:a counter circuit outputting a different count value each time the test signal ...

MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE

A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. 120-. (canceled)21. A memory controller comprising: address information indicating a storage address for first write data; and', 'a first timing signal to time reception of the address information within a first dynamic random access memory (DRAM), the first timing signal requiring a first propagation time to propagate from the memory controller to the first DRAM;, 'first circuitry to output a chain of delay elements to generate a plurality of delayed timing signals, and', 'first select circuitry to select, as a transmission timing source of the second timing signal, a first one of the delayed timing signals, wherein the memory controller is operable in a calibration mode to enable the first select circuitry to select the first one of the delayed timing signals to time transmission of the second timing signal, wherein, during the calibration mode, the second circuitry outputs multiple delayed versions of the timing signals and selects, as the first one of the delayed timing signals, one of the delayed timing signals that compensates for mismatch between the first and ...

SELF CLOCKING FOR DATA EXTRACTION

A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art. 1. A method of data extraction of data in a plurality of signal channels , comprising the steps of:for each signal channel taking a group of samples distributed throughout a bit period interval; determining an edge in said signal channel at said sample if said sample differs from said prior sample, and', 'determining no edge in said signal channel at said sample if said sample equals said prior sample;, 'for each signal channel comparing each sample of said group of samples with a prior sample'} (1) a sample during which an edge is determined in at least one signal channel, followed by', '(2) a second predetermined time Y during which no edge is determined for any signal channel., 'extracting data from all signal channels at a sample of said group of samples following detection of'}2. The method of claim 1 , wherein:said first predetermined time X is a first number of sampled of said group of samples.3. The method of claim 1 , wherein:said second predetermined time Y is a second number of sampled of said group of samples.4. The method of claim 1 , wherein:said group of samples is m samples n through n+m−1;sample data [(m/2)−1:00] is used to extract data within a window A; ansample data [m−1;m/2] is used to extract data within a window B.5. The method of claim 4 , wherein: calculating the logical AND of data [n] with a delayed version of sample value [n], and', ' ...

Analog peak hold circuits

A peak hold circuit includes an input node configured to receive an input waveform, a peak hold component coupled to the input node and configured to sample and hold a peak value of the input waveform at a peak value node, a reset node configured to receive a reset signal, a reset circuit coupled to the peak hold component and the reset node, the reset circuit configured to reset the peak hold value, and a voltage clamp coupled to the input node, the reset circuit, and the reset node, the voltage clamp configured to clamp the input node in response to the reset signal.

SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES

A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal. 1. A semiconductor memory device comprising:a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal, the clock input buffer configured to buffer a clock signal in order to output a buffered clock signal; andan internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal, wherein the generation of the internal clock signal is started in response to a second control signal.2. The semiconductor memory device of claim 1 , wherein the first control signal is a clock enable signal claim 1 , the second control signal is a chip selection signal claim 1 , and wherein the internal clock generator generates the internal clock signal by starting a division of the buffered clock signal in response to a first pulse of the chip selection signal being input to the internal clock generator.3. The semiconductor memory device of claim 2 , wherein a pulse width of the first pulse of the chip selection signal is greater than one clock cycle of the clock signal.4. The semiconductor memory device of claim 1 , wherein claim 1 , the internal clock generator is configured to start to generate the internal clock signal by dividing the buffered clock signal in response to the first pulse of the second control signal being input to the internal clock generator while the first control signal is activated.5. The semiconductor memory device of claim 1 , wherein the clock input buffer buffers the clock signal in response ...

MONITORING DEVICE AND METHOD FOR MONITORING A LINE SECTION USING A MONITORING DEVICE

A monitoring device is provided that includes a first line section with a first connection point and a second connection point spaced apart from the first connection point in the direction of the line, and with a control unit and with a first current sensing unit, having a current source. A first switch is inserted into the first connecting line and connects the first current source to the first connection point or disconnects it therefrom. In a first state the first switch is closed and the first current is impressed on the first line section and a first voltage determined by the amplitude of the actual current, and in a second state the first switch is open and a second voltage is determined, and the control unit is configured to ascertain the amplitude of the first actual current from the two voltages. 1. A monitoring device comprising:a first line section with a first connection point and a second connection point spaced apart from the first connection point in a direction of the line;a control unit; a first current source connectable to the first connection point via a first connecting line and connectable to the second connection point via a second connecting line, the first current source being configured to output a first current;', 'a first switch having a control input, the first switch being inserted into the second connecting line and being configured to connect or disconnect the first current source to the second connection point; and', 'a first differential amplifier having a first input, a second input, and an output, the first input being connectable to the first connection point via a third connecting line, the second input being connectable to the second connection point by a fourth connecting line;, 'a first current sensing unit comprisingwherein the control unit is inserted between the output of the first differential amplifier and the control input of the first switch,wherein an actual current is passed through the first line section,wherein, in ...

Dead time generation circuit and load driving apparatus

A dead time generation circuit includes a high-side control signal generation circuit and a low-side control signal generation circuit which are separate circuits. The high-side control signal generation circuit inverts a level of a high-side control signal from a driving prohibition level to a driving permission level when a time corresponding to a first clock number has elapsed in a state where a control signal keeps a first level after the control signal transitions from a second level to the first level. The low-side control signal generation circuit inverts a level of a low-side control signal from the driving prohibition level to the driving permission level when a time corresponding to a second clock number has elapsed in a state where the control signal keeps the second level after the control signal transitions from the first level to the second level.

ELECTRONIC APPARATUS, DRAM CONTROLLER, AND DRAM

The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal. 1. An electronic apparatus , comprising:a Dynamic Random Access Memory (DRAM), receiving at least one control and address signal and a clock signal, delaying the clock signal by a predetermined value to obtain a delayed clock signal, sampling the control and address signal according to the clock signal to obtain a first sample signal, sampling the control and address signal according to the delayed clock signal to obtain a second sample signal, and comparing the first sample signal with the second sample signal to obtain a status signal; anda DRAM controller, sending the at least one control and address signal and the clock signal to the DRAM, receiving the status signal from the DRAM, and adjusting a phase difference between the clock signal and the at least one control and address signal according to the status signal.2. The electronic apparatus as claimed in claim 1 , wherein the DRAM comprises:a delay unit, delaying the clock signal by the predetermined value to obtain the delayed clock signal;a first latch, sampling the control and address signal according to the clock signal to obtain the first sample signal;a ...

LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME

A latency control circuit is configured to delay a read information signal in response to a CAS latency signal and an internal clock signal to generate a delayed read information signal, and is further configured to generate a latency control signal based on the delayed read information signal in response to a plurality of sampling control signals and a plurality of transfer control signals. 1. A latency control circuit , comprising:a sampling clock signal generating circuit configured to generate a plurality of sampling clock signals having different phases from each other based on an internal clock signal;a multiplexer configured to multiplex the sampling clock signals in response to a column address strobe (CAS) latency signal to generate a plurality of sampling control signals;a transfer control signal generating circuit configured to generate a plurality of transfer control signals having different phases from each other based on an output clock signal; anda latency control signal generating circuit configured to delay a read information signal in response to the CAS latency signal and the internal clock signal to generate a delayed read information signal, and further configured to generate a latency control signal based on the delayed read information signal in response to the sampling control signals and the transfer control signals.2. The latency control circuit of claim 1 , wherein the sampling clock signals are configured to have a phase difference of an integer multiple of a clock cycle of the internal clock signal.3. The latency control circuit of claim 2 , wherein the sampling clock signal generating circuit comprises:a shift register synchronized with the internal clock signal and configured to generate the sampling clock signals that are sequentially enabled with a delay time of the clock cycle.4. The latency control circuit of claim 1 , wherein the latency control signal generating circuit comprises:a delay circuit configured to delay the read ...

CIRCUIT FOR FILTERING NARROW PULSE AND COMPENSATING WIDE PULSE, AND MOTOR CONTROLLER COMPRISING THE CIRCUIT

A circuit for filtering narrow pulse and compensating wide pulse, including a signal shaping circuit, a filter circuit, and a pulse width compensating circuit. The signal shaping circuit processes an input signal and transmits the input signal to the filter circuit. The filter circuit filters off narrow pulses of the input signal. The pulse width compensating circuit compensates the wide pulses of the input signal and outputs an output signal. 22. The circuit of claim 1 , wherein the filter circuit () is an RC filter circuit.311. The circuit of claim 1 , wherein the signal shaping circuit () comprises a first Schmitt trigger (ICA).411. The circuit of claim 2 , wherein the signal shaping circuit () comprises a first Schmitt trigger (ICA).5. The circuit of claim 3 , wherein{'b': 3', '1', '1', '3', '4', '2, 'the pulse width compensating circuit () comprises a second Schmitt trigger (ICB), a triode (Q), a first resistor (R), a second resistor (R), and a capacitor (C);'}{'b': 2', '1, 'the input signal processed through the filter circuit () is connected with the second Schmitt trigger (ICB);'}{'b': '1', 'the signal is output from an output end of the second Schmitt trigger (ICB);'}{'b': 2', '4', '1, 'the capacitor (C) and the second resistor (R) are connected in series and connected to the output end and a grounded end of the Second Schmitt trigger (ICB), respectively;'}{'b': 2', '4', '1', '3, 'a node between the capacitor (C) and the second resistor R is connected with a base electrode of the triode (Q) after being connected with the first resistor (R);'}{'b': '1', 'an emitting electrode of the triode (Q) is grounded; and'}{'b': 1', '1, 'a collecting electrode of the triode (Q) is connected with an input end of the Second Schmitt trigger (ICB).'}6. The circuit of claim 4 , wherein{'b': 3', '1', '1', '3', '4', '2, 'the pulse width compensating circuit () comprises a second Schmitt trigger (ICB), a triode (Q), a first resistor (R), a second resistor (R), and a capacitor ( ...

COMPARATOR, ANALOG-TO-DIGITAL CONVERTOR, SOLID-STATE IMAGING DEVICE, CAMERA SYSTEM, AND ELECTRONIC APPARATUS

A comparator includes a first amplifier, a second amplifier, and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors compare a reference voltage with a potential of an input signal. The second amplifier gain up the signal output from the first output node of the first amplifier and outputs the signal from a second output node. The level holding part holds a level of the second output node at a predetermined level. The second amplifier includes a transistor for amplification and a transistor for a current source. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source does not fall into a level at which a saturated operation condition is not satisfied. 1. A comparator , comprising: 'the differential-pair transistors serving as a comparison part configured to compare a reference voltage with a potential of an input signal;', 'a first amplifier including differential-pair transistors and configured to output a signal of a level corresponding to a comparison result from a first output node,'}a second amplifier configured to gain up the signal output from the first output node of the first amplifier and output the signal from a second output node; and the second amplifier including', 'a transistor for amplification connected between the second output node and a power supply or a reference potential source and', 'a transistor for a current source connected between the second output node and the reference potential source or the power supply,', 'the level holding part holding the level of the second output node of the second amplifier such that the transistor for the current source of the second amplifier does not fall into a level at which a saturated operation condition is not satisfied., 'a level holding part configured to hold a level ...

Physical unclonable function cell and array

A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.

SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM

A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, 1. A system , comprising:a controller comprising a plurality of first external terminals configured to supply a command and an address, to communicate data, and to communicate a strobe signal related to the data; anda semiconductor memory device comprising a plurality of second external terminals corresponding to the plurality of first external terminals,the semiconductor memory device further comprising a system clock external terminal provided to receive a system clock with a first frequency or a second frequency,one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively.2. The system as claimed in claim 1 , the device further comprising:a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the data strobe signal to communicate the data.3. The system as claimed in claim 1 , wherein the more the frequency of the system clock is increased claim 1 , the longer the length of the preamble is.4. The system as claimed in claim 3 , wherein the larger a CAS latency is claim 3 , ...

Signal duty cycle detector and calibration system

A duty cycle detector and calibration system is disclosed. In some embodiments, a duty cycle calibration system includes a first tuning circuit operative to receive an input signal, tune a duty cycle of the input signal to within a first error range, and provide a first output signal. A second tuning circuit tunes a duty cycle of the first output signal to within a second error range and provides a second output signal, where the second error range has more precision than the first error range. A duty cycle detector provides a duty cycle detection signal indicative of a duty cycle of the second output signal, and logic controls the first and second tuning circuits based upon the duty cycle detection signal.

DRIVER CIRCUIT CONFIGURED WITH TRAVELLING WAVE AMPLIFIER

A driver with the arrangement of the travelling wave amplifier is disclosed. The driver provides n counts of cells each configuring the open collector arrangement and amplifying an input signal. The cells are arranged between an input interconnection and an output interconnection, and powered through the output interconnection. The power supply line to power the output interconnection is connected between m-th and (m+1)-th cells not through the output terminal of the output interconnection. 1. A driver for modulating light coming from an optical source , comprising:an input interconnection for propagating an input signal, the input interconnection providing first to N-th input delay lines connected in series, each of input delay lines having a delay time substantially equal to each other;an output interconnection for propagating amplified signals, the output interconnection providing first to N-th output delay lines connected in series, each of output delay lines having a delay time substantially equal to each other and equal to the delay time of the input delay line;first to N-th cells, wherein the n-th cell is connected to the n-th input delay line to receive the input signal and to the n-th output delay line to output the amplified signal to the n-th output delay line, where n is an integer between 1 and N;a power line for supplying electrical power to the output interconnection, the power line being connected between the m-th output delay line and (m+1)-th output delay line, where m is an integer between 2 to N−2.2. The driver of claim 1 ,wherein each of input delay lines and each of output delay lines includes a first delay element and a second delay element connected in series to the first delay element, the first and second delay elements having a delay time substantially equal to each other,wherein the n-th cell is connected between the first and second delay element in the n-th input delay line to receive the input signal, and between the first and second ...

SEMICONDUCTOR MEMORY DEVICE AND ACCESS METHOD THEREOF

Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time. 1. (canceled)2. A method of accessing memory banks in a cell array , the cell array including a plurality of bank groups , wherein each bank group includes at least two banks , the method comprising:receiving a first command to access a first bank of a first bank group;receiving a second command to access a first bank of a second bank group; andreceiving a third command to access a second bank of the first bank group,wherein the third command is received after a first delay time from the received first command,the second command is received after a second delay time from the received first command, andwherein the first and second delay times are different.3. The method of claim 2 , wherein the first delay time is programmed by a mode register setting.4. The method of claim 2 , wherein the first delay time is a first command delay for accesses within a same bank group claim 2 , and the second delay time is a second command delay for accesses within different bank groups.5. The method of claim 2 , wherein the first delay time is greater than the second delay time.6. The method of claim 2 , wherein each of the first claim 2 , second and third commands is a write command or a read command.7. The method of claim 2 , wherein the first claim 2 , second or third command includes a column address strobe signal. This application is a continuation of U.S. application Ser. No. 13/360,093 filed on Jan. 27, 2012, which is a Continuation of U.S. Pat. No. 8,125,847, issued on Feb. 28, 2012, which claims priority to Korean Patent ...

Extension of ethernet phy to channels with bridged tap wires

In one embodiment, receiving an Ethernet signal over a channel, the Ethernet signal comprising a preamble frame, an idle frame, and a data frame, the preamble frame comprising one or more preamble codes; synchronizing to the Ethernet signal based on the preamble frame; replicating the one or more preamble codes; and training a decision feedback equalizer (DFE) based on the one or more replicated codes, the training enabling the DFE to use decision values at the DFE output to track channel variations.

PWM DUTY CYCLE CONVERTER

A PWM duty cycle converter includes a PWM signal generator, a timing signal generator, a limit signal generator, and a duty cycle limiter. The PWM signal generator generates a first PWM signal by comparing a triangular carrier wave with a duty command from a signal source. The timing signal generator generates a timing signal synchronously with at least one of a maximum value and a minimum value of the amplitude of the carrier wave. The limit signal generator generates a limit signal in response to the timing signal. The limit signal sets at least one of an upper limit and a lower limit on a duty cycle of the first PWM signal. The duty cycle limiter combines the first PWM signal and the limit signal to output a second PWM signal having a limited duty cycle. 1. A pulse width modulation (PWM) duty cycle converter comprising:a PWM signal generator configured to generate a first PWM signal by comparing a triangular carrier wave with at least one duty command from at least one signal source;a timing signal generator configured to generate a timing signal synchronously with at least one of a maximum value and a minimum value of an amplitude of the carrier wave;a limit signal generator configured to generate a limit signal in response to the timing signal, the limit signal setting at least one of an upper limit and a lower limit on a duty cycle of the first PWM signal, anda duty cycle limiter configured to combine the first PWM signal and the limit signal to output a second PWM signal having a limited duty cycle.2. The PWM duty cycle converter according to claim 1 , whereinthe PWM signal generator serially arranges a plurality of duty commands from a plurality of signal sources and generates the first PWM signal by comparing the carrier wave with the serially-arranged plurality of duty commands.3. The PWM duty cycle converter according to claim 2 , whereinthe duty cycle limiter adds a 100% duty cycle pulse to the second PWM signal, anda width of the 100% duty cycle pulse ...

DELAY CIRCUIT, FAN ASSEMBLY, AND ELECTRONIC DEVICE USING THE DELAY CIRCUIT

A delay circuit for a fan includes a signal generation circuit, a first switch, a delay microchip, and a second switch. The signal generation circuit receives a driving signal and generates a control signal according to the driving signal. The first switch is electronically connected to the signal generation circuit to receive the control signal. The second switch is electronically connected between the delay microchip and the fan. When the signal generation circuit is electronically connected to the fan via the first switch, the control signal is transmitted to the fan to activate the fan. When the signal generation circuit is electronically connected to the delay microchip, the delay microchip receives the control signal and outputs a delayed control signal after a predetermined delay time, and the delayed control signal is transmitted to the fan via the second switch to activate the fan. 1. A delay circuit for an electronic component of an electronic device , the delay circuit comprising:a signal generation circuit receiving a driving signal from the electronic device, and generating a control signal according to the driving signal;a first switch electronically connected to the signal generation circuit to receive the control signal;a delay microchip configured to delay the control signal; anda second switch electronically connected between the delay microchip and the electronic component;wherein manipulation of the first switch causes the signal generation circuit to be electronically connected to the electronic component via the first switch, and the control signal is transmitted to the electronic component to activate the electronic component; andwherein manipulation of the first switch causes the signal generation circuit to be electronically connected to the delay microchip, the delay microchip receives the control signal and outputs a delayed control signal after a predetermined delay time, and the delayed control signal is transmitted to the electronic ...

RECEIVER WITH TIME-VARYING THRESHOLD VOLTAGE

A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system. 1. An apparatus , comprising:an input node to receive a signal representing a series of logical values, wherein a given logical value is within a corresponding bit-duration;a threshold generator circuit to generate a time-varying threshold voltage during the bit-duration; anda slicer, coupled to the input node and the threshold generator circuit, to resolve the logical values from the signal based at least on the time-varying threshold voltage.2. The apparatus of claim 1 , wherein the time-varying threshold voltage varies linearly with time during the bit-duration.3. The apparatus of claim 1 , wherein the time-varying threshold voltage varies non-linearly as a function of time.4. The apparatus of claim 1 , wherein a waveform of the time-varying threshold voltage is configured to match portion of a pulse response of a communication channel to which the slicer is coupled.5. The apparatus of claim 1 , further comprising: a clock input node claim 1 , coupled to the threshold generator circuit claim 1 , to receive a clock signal; wherein the threshold generator circuit generates the time-varying threshold voltage based on the clock signal.6. The apparatus of claim 5 , wherein the clock signal includes a source-synchronous clock signal that is communicated in a communication channel to which the slicer is coupled.7. The apparatus of claim 1 , further comprising:a register to store an activation bit; andcontrol logic, coupled to the register, to selectively enable or disable the time-varying threshold voltage based at least ...

Correction Circuit for Output Duty of Hall Element, Hall Sensor and Method of Correcting Output Duty of Hall Element

Disclosed herein are a correction circuit for output duty of a Hall element, a Hall sensor, and a method of correcting the output duty of the Hall element. According to an exemplary embodiment of the present invention, the correction circuit includes an amplification and output unit for amplifying an output of the Hall element and outputting a sqaure wave signal; a duty detection unit for detecting a duty ratio of the sqaure wave signal output by the amplification and output unit; and a duty correction unit for applying a feedback correction signal to the amplification and output unit accoring to the detected duty ratio. 1. A correction circuit for output duty of a Hall element , the correction circit comprising:an amplification and output unit for amplifying an output of the Hall element and outputting a sqaure wave signal;a duty detection unit for detecting a duty ratio of the sqaure wave signal output by the amplification and output unit; anda duty correction unit for applying a feedback correction signal to the amplification and output unit accoring to the detected duty ratio.2. The correction circit according to claim 1 , wherein the duty detection unit calculates the duty ratio by counting high sections and low sections according to previously set clocks during one cycle of the square wave signal.3. The correction circit according to claim 1 , wherein the duty correction unit includes:a state machine for generating a duty ratio correction bit according to the duty ratio detected by the duty detection unit; anda hysteresis section control unit for feeding back and controlling a width of a hysteresis section for outputting the square wave signal, according to the duty ratio correction bit generated by the state machine.4. The correction circit according to claim 2 , wherein the duty correction unit includes:a state machine for generating a duty ratio correction bit according to the duty ratio detected by the duty detection unit; anda hysteresis section control ...

MEMORY MODULE

A memory module having memory components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective memory components, and the address/control signal path and clock signal path are coupled in common to all the memory components. The address/control signal path extends along the memory components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components. 1. A memory module comprising:a circuit board;a first plurality of memory components disposed on the circuit board, each of the memory components having an address/control input, a clock input, a data input and a strobe input;a termination structure disposed on the circuit board;an address/control signal path that extends from an edge of the circuit board to the termination structure, the address/control signal path being coupled along its length to the address/control input of each of the memory components such that control signals propagating toward the termination structure on the address/control signal path arrive at the address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components;a clock signal path extending from the circuit board edge and coupled along its length to the clock input of each of the memory components such that a clock signal propagating on the clock signal path arrives at the clock inputs of respective memory components at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the memory components, the clock signal indicating to the memory components respective times at which to sample the control ...

SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME

A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin. 1. A semiconductor memory apparatus comprising:a memory cell area comprising a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; anda control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.2. The semiconductor memory apparatus according to claim 1 , wherein the control unit generates the plurality of control signals using a command signal and an address signal which are outputted in synchronization with the same clock claim 1 , andthe plurality of control signals are generated at substantially the same time.3. The semiconductor memory apparatus according to claim 2 , wherein the control unit comprises:a command address signal shifter configured to shift the command signal and the address signal, inputted from outside, such that the shifted signals have a predetermined margin;a data enable signal generator configured to generate a data enable signal having a predetermined margin, using the command signal and the address signal;a first latch signal generator configured to generate a first latch signal to latch a data signal inputted to the octet banks of the first group, using the command signal and the address signal;a second latch signal generator configured to generate a second latch signal for latching a data signal inputted to the octet banks of the second group, using the command signal ...

High speed duty cycle correction and double to single ended conversion circuit for pll

The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

Frequency multiplier circuit with function of automatically adjusting duty cycle of output signal and system thereof

A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%. 1. A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal , comprising:an input terminal,a frequency multiplier control unit connected to said input terminal,an output terminal connected to said frequency multiplier control unit,a first detecting unit connected to said frequency multiplier control unit and said output terminal,a second detection unit connected to said frequency multiplier control unit and said output terminal,a duty cycle adjusting unit connected to said first detecting unit, said second detecting unit and said frequency multiplier control unit, anda ground terminal connected to said first detecting unit and said second detecting unit;wherein said frequency multiplier control unit comprises:a first buffer connected to said input terminal,an AND gate connected to said input terminal and said first buffer,a first NOR gate connected to said input terminal and said first buffer, anda second NOR gate connected to said AND gate and said first NOR gate;wherein said first detecting unit comprises: ...

PROXIMITY SWITCH ASSEMBLY AND CALIBRATION METHOD THEREFOR

A proximity switch assembly and method for detecting activation of a proximity switch assembly and calibrating the switch assembly. The assembly includes proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field to sense activation. The control circuitry generates an activation output when a differential change in the signal exceeds a threshold and distinguishes an activation from an exploration of the plurality of switches. The control circuit further determines a rate of change and generates an output when the rate of change exceeds a threshold rate to enable activation of a switch and performs a calibration of the signals to reduce effects caused by changes in condensation. 1. A method of calibrating a proximity switch comprising:generating an activation field with a proximity sensor;monitoring amplitude of a signal generated in response to the activation field;detecting the signal amplitude exceeding a threshold for a time period; andcalibrating the signal by adjusting the signal to a predefined level when the signal amplitude exceeds the threshold for the time period and reaches a peak value.2. The method of claim 1 , wherein the method comprises generating an activation field for each of a plurality of proximity sensors and monitoring amplitude of signals generated in response to the activation fields claim 1 , wherein the step of calibrating comprises calibrating all signals when a maximum signal is above a first threshold for a first time period and the maximum signal reaches a peak value.3. The method of claim 2 , wherein the method determines when all signals are negative and detects when a lowest signal is below a second threshold for a second time period claim 2 , wherein the step of calibrating comprises calibrating all signals when the lowest signal is below the second threshold for the second time period and the lowest signal reaches a bottom value.4. The method of claim ...

Proximity switch assembly and activation method using rate monitoring

A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field of each proximity switch to sense activation. The control circuitry monitors the signal responsive to the activation field and determines a differential change in generated signal, and further generates an activation output when the differential signal exceeds a threshold. The control circuitry further distinguishes an activation from an exploration of the plurality of switches and determines activation upon detection of a stable signal. The control circuit further determines a rate of change and generates an output when the rate of change exceeds a threshold rate to enable activation of a switch.

ZERO CROSSING DETECTOR (ZCD) CIRCUIT

A system for detecting a Zero Crossing point is provided. The system includes: a coupling unit connected between a high voltage side and a low voltage side of the system; and a zero crossing detector connected to the high voltage side and configured to divide a filtered mains voltage signal and to generate an output signal that indicates a zero crossing point of the filtered mains voltage signal. 1. A method comprising:filtering noise in a mains voltage signal;dividing the mains voltage signal in order to obtain a low voltage signal; andgenerating an output signal from the low voltage signal, wherein the output signal indicates a zero crossing point of the mains voltage signal.2. The method of claim 1 , wherein the zero crossing point is used to provide synchronization of additional voltage signals with the mains voltage signal.3. The method of claim 1 , wherein the low voltage signal comprises a first low voltage signal and a second low voltage signal.4. The method of claim 1 , wherein generating the output signal comprises:generating a first low voltage signal and a second low voltage signal;comparing the first and second low voltage signals;outputting a positive pulse if the first low voltage signal is greater than the second low voltage signal; andoutputting a negative pulse if the first low voltage signal is less than the second low voltage signal.5. The method of claim 1 , further comprising:providing a given amount of voltage biasing to the low voltage signal prior to generating the output signal from the low voltage signal.6. The method of claim 5 , wherein providing the given amount of voltage biasing comprises: controlling an impedance value that is presented to the low voltage signal.7. The method of claim 5 , wherein providing the given amount of voltage biasing further comprises: controlling a DC value of the voltage biasing that is presented to the low voltage signal.8. The method of claim 5 , wherein providing the given amount of voltage biasing ...

SYSTEMS AND METHODS FOR COMPENSATING THE INPUT OFFSET VOLTAGE OF A COMPARATOR

Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator. 110-. (canceled)11. A system to compensate for an input offset voltage of a zero crossing detection circuit for a power stealing circuit , the system comprising:an input configured to connect to an AC power source that provides power to a load;a zero crossing detection circuit responsive to the input, the zero crossing detection circuit configured to determine a zero crossing of an input signal provided by the ac power source, and wherein the zero crossing detection circuit includes a comparator having an input offset voltage; anda compensation circuit responsive to the zero crossing detection circuit, wherein the compensation circuit is configured to provide a first compensation signal to an inverting input of the comparator of the zero crossing detection circuit, and a second compensation signal to a non-inverting input of the comparator of the zero crossing detection circuit, wherein the polarity of the first compensation signal is opposite to the polarity of the second compensation signal.12. The system of claim 11 , further comprising a switch to activate the power stealing circuit claim 11 , the switch activated by an output ...

Interference Cancellation with Time-Varying Interference and/or Distortion

A communications receiver includes a noise analyzer to characterize the composition of the interference and/or distortion impressed onto a transmitted communications signal in the presence of one or more time-varying conditions. The noise analyzer may provide a selection signal indicating the composition of the interference and/or distortion impressed onto a transmitted communications signal in the presence of one or more time-varying conditions to be used by the communications receiver. In an exemplary embodiment, the communications receiver selects at least one set of filter coefficients to compensate for the interference and/or distortion impressed onto a transmitted communications signal in the presence of a particular time-varying interference and/or distortion condition. In another exemplary embodiment, the communications receiver selects a corresponding interference cancellation filter hank to compensate for the interference and/or distortion impressed onto a transmitted communications signal in the presence of the particular time-varying interference and/or distortion condition.

DUTY CYCLE DISTORTION CORRECTION CIRCUITRY

Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high. 1. A circuit , comprising:an input that receives a control signal having a duty cycle; andan output on which an output clock signal is generated, wherein the output clock signal has a duty cycle that is set by the control signal and that is different than the duty cycle of the control signal.2. The circuit defined in claim 1 , wherein the control signal received at the input comprises an input clock signal.3. The circuit defined in claim 1 , further comprising:an additional input that receives another control signal, wherein the control signal is a delayed version of the another control signal.4. The circuit defined in claim 1 , further comprising:an additional input that receives another control signal, wherein the control signal is a delayed version of the another control signal, and wherein the control signal is delayed by an amount with respect to the another control signal that sets the duty cycle of the output clock signal.5. The circuit defined in claim 1 , further comprising:a first additional input that receives a first additional ...

FORWARDED CLOCK JITTER REDUCTION

In some embodiments, a differential amplifier with duty cycle correction is provided. 1. A chip , comprising:a differential amplifier to receive a differential clock; andan offset compensation circuit coupled to the amplifier to adjust offset in the differential clock, the offset compensation circuit to be digitally controlled based on offset in the differential clock.2. The chip of claim 1 , in which the differential clock is a forwarded clock from another chip.3. The chip of claim 1 , in which the offset compensation circuit is disposed between the amplifier and electrical contacts for receiving the clock from off of the chip.4. The chip of claim 1 , in which the offset compensation circuit is part of an active filter circuit.5. The chip of claim 4 , in which the active filter circuit implements a continuous time linear equalizer circuit.6. The chip of claim 1 , comprising a variable offset comparator to receive a low-pass filtered version of the differential clock to generate a digital value representing whether or not a duty cycle of the clock is above or below a threshold.7. The chip of claim 6 , in which the duty cycle threshold is 50%.8. The chip of claim 1 , comprising a switch to receive a failover clock to be used as the differential clock.9. A chip claim 1 , comprising:a differential amplifier having an input to receive a differential clock and an output to provide a duty cycle adjusted clock; andan offset adjustment circuit coupled between the input and output, said offset adjustment circuit including a variable offset comparator (VOC) with self offset correction, a differential offset compensation (DOC) circuit having an output coupled to the input of the differential amplifier, and a control circuit coupled between the VOC and DOC to control output clock duty cycle.10. The chip of claim 9 , in which the differential clock is a forwarded clock from another chip.11. The chip of claim 9 , in which the offset compensation circuit is disposed between the ...

Receiver Having Limiter-Enhanced Data Eye Openings

A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Driver circuits for dimmable solid state lighting apparatus

A voltage regulator for generating a housekeeping voltage in a high voltage power supply circuit includes a charging switch coupled to a high voltage node and to a storage device at an output node, and a control voltage regulation circuit coupled to the charging switch and configured to cause the charging switch to generate a current pulse for charging the storage device.

CONTROL DEVICE

A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other. 1. A control device comprising:a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices; anda plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other.2. The control device according to claim 1 , further comprising:a first data input terminal to be connected in common to data terminals that are included respectively in the first memory devices;a first phase detector coupled to the first data input terminal and a common output terminal of the first sub-units,the first phase detector detecting a phase of a data strobe signal supplied via the first data strobe input terminal in response to a data signal supplied via the first data input terminal, so that each of the sub-units holds the data strobe delay value corresponding to the associated one of the first memory devices.3. The control device according to claim 2 , wherein the phase detector comprises:a latch circuit coupled to the first data input terminal and latching the data signal supplied via the data input terminal in response to the data strobe signal supplied via the output terminal of the first sub-units.4. The control device according to claim 1 , whereinthe first memory devices to which the first data strobe input terminal is connected in common are ranked ...

METHOD AND DEVICE FOR GENERATING SHORT PULSES

There is described a method and corresponding pulse generating device, for generating an output pulse signal having an output pulse duration. The method comprises: receiving at an input port an input pulse signal comprising an input pulse duration; duplicating the input pulse signal into a first digital pulse signal and a second digital pulse signal each comprising the input pulse duration; delaying at least one of the first and the second digital pulse signals by a time delay to obtain respectively a first and a second delayed digital pulse signal, a time delay difference between the first and the second delayed digital pulse signals being substantially equal to the output pulse duration; logically combining the first and the second delayed digital pulse signals to generate the output pulse signal with the output pulse duration smaller than the input pulse duration; and outputting the output pulse signal at an output port. 1. A pulse generating device for generating an output pulse signal having an output pulse duration , the device comprising:a signal duplicator for receiving an input pulse signal comprising an input pulse duration, the signal duplicator for duplicating the input pulse signal into a first digital pulse signal and a second digital pulse signal each comprising the input pulse duration;a delay component operatively coupled to the signal duplicator, the delay component for delaying at least one of the first and the second digital pulse signals by a time delay to obtain respectively a first and a second delayed digital pulse signal, a time delay difference between the first and the second delayed digital pulse signals being substantially equal to the output pulse duration; anda logic circuit coupled to the delay component, the logic circuit for combining logically the first and the second delayed digital pulse signals to generate the output pulse signal with the output pulse duration smaller than the input pulse duration, the logic circuit for ...

EDGE SELECTION TECHNIQUES FOR CORRECTING CLOCK DUTY CYCLE

Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit. 1. A circuit for generating a clock signal , comprising:a multiplexer circuit to selectively output one of a plurality of input clock signals; andan edge-triggered flip-flop circuit comprising a clock signal port, a data signal port, and an output port, wherein the clock signal port is connected to an output of the multiplexer circuit, wherein the data signal port receives a data signal, and wherein the output port of the edge-triggered flip-flop is connected to a select control port of the multiplexer circuit,wherein the edge-triggered flip-flop detects a transitioning edge of an input clock signal that is selectively output from the multiplexer circuit, and in response to said detection, samples a logic level of the received data signal, and generates a transition of an output clock signal at the output port, andwherein the multiplexer circuit selectively outputs one of the plurality of input clock signals to the clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the ...

Zero-Crossing Detector for Industrial Control with Low Heat Dissipation

An I/O circuit for use with an industrial controller provides a zero-crossing detector circuit with low power dissipation through the use of a zero-crossing circuit that activates a light emitting diode of a photo coupler only for a very brief period of time at the zero-crossing (as opposed to at all times other than the zero-crossing). The circuit is coupled with a power supply circuit that uses a reactive element for voltage dropping as opposed to a resistive voltage drop element further reducing power consumption possible with the low power consumption of the photo coupler.

PULSE WIDTH MODULATION CIRCUIT AND PULSE WIDTH MODULATION SIGNAL GENERATING METHOD HAVING TWO FRESH RATES

A PWM circuit that can have two fresh rates, including: a first PWM signal generator and a second PWM signal generator; wherein the first PWM signal generator and the second PWM signal generator respectively control refresh rates in two dimensions of an output data generated from a target apparatus. A PWM signal generation method that can have two fresh rates, including: generating a first PWM signal; generating a second PWM signal; and controlling refresh rates in different dimensions of an output data generated from a target apparatus respectively by using the first PWM signal and the second PWM signal. 1. A pulse width modulation (PWM) circuit having two fresh rates , comprising:a first PWM signal generator; anda second PWM signal generator;wherein the first PWM signal generator and the second PWM signal generator control refresh rates in different dimensions of an output data generated from a target apparatus, respectively.2. The PWM circuit of claim 1 , wherein the target apparatus is a light processing device claim 1 , and the first PWM signal generator and the second PWM signal generator are arranged to control brightness of the output data in the different dimensions claim 1 , respectively.3. A pulse width modulation (PWM) circuit having two fresh rates claim 1 , the PWM circuit being employed in a target apparatus to make the target apparatus generate an output data claim 1 , the output data comprising a plurality of data units claim 1 , the PWM circuit comprising:a first PWM signal generator; anda second PWM signal generator;wherein the first PWM signal generator controls a first part of each of the data units, and the second PWM signal generator controls a second part of each of the data units, such that the output data has two refresh rates.4. The PWM circuit of claim 3 , wherein the second part is located in a same position in each of the data units.5. The PWM circuit of claim 3 , wherein a position of the second part of each of the data units meets a ...

DUTY CYCLE CORRECTOR

A duty cycle corrector includes an SR latch, a first switch and a second switch. The SR latch is configured to generate first and second control signals according to first and second clocks. The first switch is coupled between a work voltage and an output node, and selectively closes and opens according to the first control signal. The second switch is coupled between the output node and a ground voltage, and selectively closes and opens according to the second control signal. The output node is used to output an output clock. 1. A duty cycle corrector , comprising:an SR latch, generating a first control signal and a second control signal according to a first clock and a second clock;a first switch, coupled between a work voltage and an output node, and selectively closing and opening according to the first control signal; anda second switch, coupled between the output node and a ground voltage, and selectively closing and opening according to the second control signal,wherein the output node is used to output an output clock.2. The duty cycle corrector as claimed in claim 1 , wherein a phase difference between the first clock and the second clock is equal to 180 degrees.3. The duty cycle corrector as claimed in claim 1 , wherein the SR latch comprises: a first input terminal, receiving the first clock;', 'a second input terminal; and', 'a first output terminal, outputting the first control signal; and, 'a first NAND gate, having a third input terminal, coupled to the first output terminal;', 'a fourth input terminal, receiving the second clock; and', 'a second output terminal, coupled to the second input terminal, and outputting the second control signal., 'a second NAND gate, having4. The duty cycle corrector as claimed in claim 3 , wherein the first switch comprises:a first transistor, coupled between the work voltage and the output node, anda second transistor, coupled between the work voltage and the output node, and having a second gate coupled to the first ...

INPUT DECISION CIRCUIT

An input decision circuit includes a comparator outputting either one of a high voltage or a low voltage on the basis of the result of a comparison between a reference voltage and an input voltage, a base voltage source acting as a base common to the reference voltage and the input voltage, a constant current source supplying a constant current to a constant current path from a DC power supply to the base voltage source, and a resistor inserted in the constant current path. A constant voltage is produced across the resistor for the reference voltage with the electric potential of the base voltage source acting as a base. This provides an input decision circuit in which a threshold voltage is hard to shift even when the driving voltage of the comparator or the electric potential of the ground acting as the base voltage source is varied. 1. An input decision circuit , comprising:a comparator that outputs one of a high voltage or a low voltage on the basis of a result of a comparison between a reference voltage and an input voltage;a base voltage source that acts as a base common to the reference voltage and the input voltage;a constant current source that supplies a constant current to a constant current path formed between a DC power supply and the base voltage source; anda resistor inserted in the constant current path, wherein with an electric potential of the base voltage source as a base, a constant voltage produced across the resistor acts as the reference voltage.2. The input decision circuit of claim 1 , wherein the input decision circuit further comprises:a first constant current source that makes a constant current flow in a first constant current path;a second constant current source that makes a constant current flow in a second constant current path;a switching device inserted in the second constant current path; anda third constant current path from a joining point of the first constant current path and the second constant current path to the base ...

SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND OPERATING METHOD THEREOF

A semiconductor memory device includes an input/output circuit configured to receive an address and data from an exterior, and a peripheral circuit configured to receive the address through the input/output circuit and generate a chip selection signal based on the address. The input/output circuit may include a control pad circuit configured to apply or block at least one data strobe signal in response to the chip selection signal, and one or more input/output pad circuits configured to transfer the data to the peripheral circuits in response to the at least one data strobe signal. 1. A semiconductor memory device , comprising:an input/output circuit configured to receive an address and data from an exterior; anda peripheral circuit configured to receive the address through the input/output circuit and generate a chip selection signal based on the address,wherein the input/output circuit comprises:a control pad circuit configured to apply or block at least one data strobe signal in response to the chip selection signal; andone or more input/output pad circuits configured to transfer the data to the peripheral circuit in response to the at least one data strobe signal.2. The semiconductor memory device of claim 1 , wherein the input/output pad circuits are configured to transfer the data to the peripheral circuit when the at least one data strobe signal is applied and block the data to the peripheral circuit when the at least one data strobe signal is blocked.3. The semiconductor memory device of claim 1 , wherein the control pad circuit is configured to receive an original data strobe signal from the exterior and apply the at least one data strobe signal based on the original data strobe signal.4. The semiconductor memory device of claim 3 , wherein the at least one data strobe signal includes a first data strobe signal that is substantially the same as the original data strobe signal and a second data strobe signal obtained by inverting the original data strobe ...

DUTY RATIO CORRECTION CIRCUIT, DOUBLE-EDGED DEVICE, AND METHOD OF CORRECTING DUTY RATIO

A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal. 1. A duty ratio correction circuit , comprising:a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal;a phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; anda multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.2. The duty ratio correction circuit according to claim 1 , whereinthe first edge corresponds to a rising edge of the first clock signal, andthe second edge corresponds to a falling edge of the first clock signal.3. The duty ratio correction circuit according to claim 1 , whereinthe phase interpolator generates the fourth clock signal by phase interpolation of the second clock signal and the third ...

INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING

Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle. 1. Duty cycle distortion correction circuitry , comprising:a driver circuit that outputs a first clock signal;an input that receives a second clock signal, wherein the second clock signal is generated based on the first clock signal;a first register transfer circuit that receives the second clock signal and generates a first error signal;a second register transfer circuit that receives the second clock signal and generates a second error signal; andcontrol circuitry that receives the first and second error signals and that controls the driver circuit so that the second clock signal exhibits a predetermined duty cycle.2. The duty cycle distortion correction circuitry defined in claim 1 , wherein the first register transfer circuit includes a test data generation circuit.3. The duty cycle distortion correction circuitry defined in claim 2 , wherein the test data generation circuit includes a flip-flop coupled to an inverter.4. The duty cycle distortion correction circuitry defined in claim 2 , wherein the first register transfer circuit further includes a delay circuit coupled to the test data ...

Method Of Controlling Electronic Device And Electronic Device

A control method and an electronic device are described. The method is applied in an electronic device which includes a first body, a second body and a rotary apparatus. On at least one body of the first body and the second body, there are provided M number of input apparatuses; the first body and the second body are rotatably connected together, where M is an integer greater than or equal to 1. The state-information of the first body and/or the second body is detected, to obtain a detection result; when the detection result indicates that the first body and/or the second body are/is in a motion state, a disable command is generated; the disable command is executed, so that N number of input apparatuses from the M number of input apparatuses are in a disabled state, where N is an integer less than or equal to M. 1. A method of controlling an electronic device , applied in an electronic device that comprises a first body , a second body and a rotary apparatus; on at least one body of the first body and the second body , there are provided M number of input apparatuses; the first body and the second body are rotatably connected together through the rotary apparatus , where M is an integer greater than or equal to 1; wherein the method comprises:detecting a state-information of the first body and/or the second body to obtain a detection result;generating a disable command when the detection result indicates that the first body and/or the second body are/is in a motion state;wherein the disable command is executed, so that N number of input apparatuses from the M number of input apparatuses are in a disabled state, where N is an integer less than or equal to M.2. The method according to claim 1 , wherein said step of detecting the state-information of the first body and/or the second body comprises:a first absolute included-angle between the first body and a first reference plane is detected, and/or, a second absolute included-angle between the second body and a second ...

METHOD FOR GENERATING PWM SIGNALS AND A PULSE WIDTH MODULATION POWER CONVERTER

A method and an apparatus for generating PWM signals is provided. Upon detection of a load transient, a new PWM period is started if the load transient occurs during the off-time of a PWM signal and exceeds a specific magnitude. 1. A method for generating PWM signals , wherein an output voltage is generated according to a pulse width modulation signal and an input voltage;an error signal is generated by sampling the output voltage and differencing the sampled output voltage and an output voltage reference;a duty ratio that defines a duty cycle of a pulse width modulation signal is determined by a PID controlling algorithm;the pulse width modulation signal is generated by providing the duty ratio to a pulse width modulator; andthe duty ratio is continuously monitored within one PWM period and compared to its predecessor by computing a duty ratio difference and in case the duty ratio difference exceeds a threshold during an off-time of the pulse width modulation signal, the pulse width modulator is triggered to start a new nominal pulse width modulation period.2. The method according to wherein the duty ratio is monitored in case a load transient is detected.3. The method according to wherein the load transient is detected by continuously monitoring the error signal.4. The method according to claim 1 , wherein the output voltage and/or the error signal is oversampled by sampling a plurality of error signals within one PWM period.5. The method according to claim 1 ,wherein a moving average of the sampled error signal is computed.6. The method according to claim 1 , wherein a first set of PID coefficients is selected in case a steady state is detected and a second set of PID coefficients is selected in case a load transient is detected.7. The control method according to claim 6 , wherein a nonlinear gain KP is selected in case of load transient detection.8. A pulse width modulation power converter claim 6 , comprising:an output stage generating an output voltage ...

Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation

The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.

TEMPERATURE-INDEPENDENT OSCILLATORS AND DELAY ELEMENTS

Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current source and provide a delay that is dependent on the charging current. Each delay element may be a current-starved delay element. The delay element(s) may be coupled in series to implement a delay line or in a loop to implement an oscillator. The bias circuit controls generation of the charging current based on a function of at least one parameter (e.g., a switching threshold voltage) of the at least one delay element in order to reduce variations in delay with temperature. The current source provides the charging current for the delay element(s) and is controlled by the bias circuit. 1. An apparatus comprising:at least one delay element configured to receive a charging current and to provide a delay that is dependent on the charging current; anda bias circuit configured to control generation of the charging current based on a function of at least one parameter of the at least one delay element to reduce variations in the delay of the at least one delay element with temperature.2. The apparatus of claim 1 , wherein each of the at least one delay element comprises a current-starved delay element configured to receive the charging current and provide a delay that is dependent on the charging current.3. The apparatus of claim 1 , wherein each of the at least one delay element comprisesa first inverter coupled between a common node and circuit ground and configured to receive a non-inverting input signal and provide an inverting output signal,a second inverter coupled between the common node and circuit ground and configured to receive an inverting input signal and provide a non-inverting output signal, wherein the charging current is applied to the common node, andat least one capacitor coupled between outputs of the first and second ...

Decision feedback equalizer

A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

MAXIMUM VOLTAGE SELECTION CIRCUIT AND METHOD AND SUB-SELECTION CIRCUIT

A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS. 1. A sub-selection circuit , comprising an enable mode circuit and a disable mode circuit ,wherein the enable mode circuit includes a comparator, and is configured to operate when an operating mode signal is an enable signal, and to set itself to an output enable state, set other sub-selection circuits to an output disable state, and output its input voltage as a maximum voltage through a P-type metal oxide semiconductor field effect transistor (PMOS transistor) when its input voltage is larger than a reference voltage, andwherein the disable mode circuit includes a power latch, and is configured to operate when the operating mode signal is a disable signal, and to set itself to the output enable state, set other sub-selection circuits to the output disable state, and output its input voltage as the maximum voltage through the PMOS transistor when its input voltage is larger than the reference voltage.2. The sub-selection circuit according to claim 1 , wherein when there is a bias current in the sub-selection circuit claim 1 , the operating mode signal having a high level is used as the enable signal claim 1 , and when there is no bias current in the ...

Clock correction circuit and clock correction method

An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

DUTY CYCLE ERROR ACCUMULATION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT HAVING THE SAME

A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal. 1. A duty cycle error accumulation circuit , comprising:{'sup': 'th', 'first to ndelay units (n is an integer of 2 or more) to receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from the first and second input signals based on a logic level of the clock signal; and'}{'sup': th', 'th, 'a feedback unit to supply the second input signal to a kdelay unit based on the second output signal of a (k+1)delay unit (k is a positive integer of (n−1) or less),'}{'sup': th', 'th', 'th, 'wherein the first output signal of the kdelay unit is supplied to the (k+1)delay unit as the first input signal, and the clock signal is supplied to the first delay unit as the first input signal and to the ndelay unit as the second input signal.'}2. The duty cycle error accumulation circuit of claim 1 , wherein each of the first to ndelay units generates the first output signal by delaying the first input signal for a first time when the clock signal has a logic low level claim 1 , and generates the second output signal by delaying the second input ...

HIGH-SPEED FULLY-DIFFERENTIAL CLOCK DUTY CYCLE CALIBRATION CIRCUIT

A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ and ADJ, a first buffer level BUF, a second buffer level BUF and a duty cycle detection level DCD. 11122. A duty cycle calibration circuit for a high-speed full-differential clock , comprising: a first adjustment stage ADJ , a first buffer stage BUF , a second adjustment stage ADJ , a second buffer stage BUF , and a duty cycle detection stage DCD , wherein:{'b': '1', 'a first and a second signal input terminal at the left side of the first adjustment stage ADJ are connected to raw differential input signals (CLK+ and CLK−) to be calibrated;'}{'b': 1', '1', '1', '1, 'output signals OUT− and OUT+ from a first and a second output terminal of the first adjustment stage ADJ are connected to a first and a second signal input terminal of the first buffer stage BUF;'}{'b': 1', '1', '1', '2, 'output signals OUTB+ and OUTB− from a first and second signal output terminal of the first buffer stage BUF are connected to a first and a second signal input terminal of the second adjustment stage ADJ, to continue to calibrate the duty cycle further;'}{'b': 2', '2', '2', '2, 'output signals OUT− and OUT+ from a first and a second signal output terminal of the second adjustment stage ADJ are connected to a first and a second signal input terminal of the second buffer stage BUF;'}{'b': 2', '2, 'output signals CKO+ and CKO− from a first and a second signal output terminal of the second buffer stage ...

MEMORIES AND METHODS FOR SHARING A SIGNAL NODE FOR THE RECEIPT AND PROVISION OF NON-DATA SIGNALS

Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals. 1. A memory , comprising:a first signal node;a second signal node;a first signal buffer coupled to the first signal node and configured to provide a first data strobe signal to the first signal node, wherein the first data strobe signal pertains to a first memory operation, and wherein the first signal buffer is configured to receive a first non-data signal from the first signal node during a time the first data strobe signal is not provided by the first signal buffer to the first signal node, and wherein the first non-data signal pertains to a second memory operation different from the first memory operation; anda second signal buffer coupled to the second signal node, wherein the second signal buffer is configured to provide a second data strobe signal to the second signal node, and wherein the second signal buffer is configured to receive a second non-data signal from the second signal node during a time the second data strobe signal is not provided by the second signal buffer to the second signal node.2. The memory of claim 1 , wherein at least one of the first non-data signal or the second non-data signal is a data mask signal.3. The memory of claim 1 , wherein the first data strobe signal comprises:a ...

Phase correction circuit and phase correction method

A variable delay circuit outputs a first delay signal obtained by variably adding a delay value to a first signal having a predetermined phase. A mixer receives the first delay signal and a second signal having a phase different from the predetermined phase, and outputs a synthesized signal of the first delay signal and the second signal. A peak voltage detection unit detects the maximum value of an amplitude voltage of the synthesized signal output from the mixer. A comparator controls the delay value added by the variable delay circuit to match the maximum value detected by the peak voltage detection unit and a predetermined voltage.

EDGE BASED PARTIAL RESPONSE EQUALIZATION

A device implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit that sets the tap weights that are used for adjustment of a received data signal. The tap weight adapter circuit sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer. 1sampling a data signal having a voltage value at an expected edge time of the data signal:generating a first alpha value and a second alpha value in dependence upon the voltage value;adjusting the data signal by the first alpha value to derive a first adjusted signal;adjusting the data signal by the second alpha value to derive a second adjusted signal;sampling the first adjusted signal to output a first data value;sampling the second adjusted signal to output a second data value; andselecting between the first data value and the second data value as a function of a prior received data value to determine a received data value.. A method comprising: This application is a Continuation of U.S. application Ser. No. 12/513,898, filed Dec. 23, 2009, which is the national phase entry of International Application No. PCT/U.S.2007/023600, filed Nov. 9,2007, which claims benefit of priority to U.S. Provisional Application No. 60/859,820, filed Nov. 16, 2006; all of the priority claims are hereby incorporated by Reference in their entirety for all purposes.The performance of conventional digital systems is limited by the transmission interconnection ...

High speed signal detecting circuit and system

A high speed signal detecting circuit includes an input terminal, a reference terminal, an output terminal, a power source terminal, a ground terminal, a front-end receiver which is connected to the input terminal, the reference terminal and the ground terminal, a secondary amplifier which is connected to the front-end receiver and the ground terminal, a final amplifier which is connected to the secondary receiver, the output terminal, the power source terminal and the ground terminal, and a biasing circuit which is connected to the front-end receiver, the secondary amplifier, the final amplifier, the power source terminal and the ground terminal. A high speed signal detecting method is also provided to precisely detect high speed signal and change a detection threshold value of the high speed signals by changing a voltage value of the reference terminal and thus has a great flexibility. 1. A high speed signal detecting circuit , comprising an input terminal , a reference terminal , an output terminal , a power source terminal , a ground terminal , a front-end receiver which is connected to said input terminal , said reference terminal and said ground terminal , a secondary amplifier which is connected to said front-end receiver and said ground terminal , a final amplifier which is connected to said secondary amplifier , said output terminal , said power source terminal and said ground terminal , and a biasing circuit which is connected to said front-end receiver , said secondary amplifier , said final amplifier , said power source terminal and said ground terminal.2. The high speed signal detecting circuit claim 1 , as recited in claim 1 , wherein said front-end receiver comprises a first FET which is connected to said input terminal and said ground terminal claim 1 , and a second FET which is connected to said reference terminal and said ground terminal; said secondary amplifier comprises a third FET connected to said first FET claim 1 , a fourth FET connected to ...

ZERO-CROSSING DETECTION METHOD AND CIRCUIT

Embodiments of the present invention disclose a zero-crossing detection method and circuit. The zero-crossing detection method includes: detecting a time point t0 when a mains voltage jumps from a low electrical level to a high electrical level and an adjacent time point t1 when the mains voltage jumps from a high electrical level to a low electrical level at a port of a detection end; and determining, according to the detected time points t0 and t1, a time point t when the mains voltage crosses zero. 1. A zero-crossing detection method , comprising:detecting a time point t0 when a mains voltage jumps from a low electrical level to a high electrical level and an adjacent time point t1 when the mains voltage jumps from a high electrical level to a low electrical level at a port of a detection end; anddetermining, according to the detected time points t0 and t1, a time point t when the mains voltage crosses zero.2. The zero-crossing detection method according to claim 1 , wherein the determining claim 1 , according to the detected time points t0 and t1 claim 1 , the time point t when the mains voltage crosses zero comprises:t=t0+0.5(t1−t0)−5.3. A zero-crossing detection circuit for implementing the zero-crossing detection method according to claim 1 , comprising a live line and a zero line of the mains claim 1 , wherein the live line and the zero line of the mains are connected to a rectifier circuit claim 1 , the rectifier circuit is connected to an output circuit claim 1 , and a current-limiting circuit is connected between the live line and the zero line of the mains and the rectifier circuit.4. The zero-crossing detection circuit according to claim 3 , wherein the current-limiting circuit comprises a first current-limiting resistor and a second current-limiting resistor claim 3 , the first current-limiting resistor is connected in the live line claim 3 , and the second current-limiting resistor is connected in the zero line.5. The zero-crossing detection circuit ...

RECEPTION DEVICE AND RECEPTION METHOD

The present technique relates to a reception device and a reception method which can improve equalization performance. An equalization processing unit has a time domain equalization unit which equalizes a received signal in a time domain and a frequency domain equalization unit which is provided in parallel to the time domain equalization unit and which equalizes the received signal in a frequency domain, and performs control of switching between the time domain equalization unit and the frequency domain equalization unit. The present technique can be applied to, for example, equalize a signal of data transmitted by way of single carrier transmission or data transmitted by way of multicarrier transmission. 1. A reception device comprising:a time domain equalization unit which equalizes a received signal in a time domain;a frequency domain equalization unit which is provided in parallel to the time domain equalization unit and which equalizes the received signal in a frequency domain; andan equalization method control unit which performs control of switching between the time domain equalization unit and the frequency domain equalization unit.2. The reception device according to claim 1 , wherein the received signal is a signal defined according to a GB20600-2006 standard claim 1 , and claim 1 , when a C3780 signal defined according to the GB20600-2006 standard is received claim 1 , the frequency equalization unit equalizes the received signal and claim 1 , when a C1 signal defined according to the GB20600-2006 standard is received claim 1 , the equalization method control unit switches between the time domain equalization unit and the frequency domain equalization unit to equalize the received signal.3. The reception device according to claim 1 , wherein the frequency domain equalization unit comprises:a FFT operating unit which converts the received signal into a frequency domain signal; anda distortion compensation unit which compensates for distortion of the ...

TRANSIENT RECOVERY VOLTAGE MEASURING DEVICE, TRANSIENT RECOVERY VOLTAGE MEASURING METHOD, AND TRANSIENT RECOVERY VOLTAGE MEASURING PROGRAM

A common tangent line drawn between a rise portion present from the origin to a second reference voltage and a rise portion corresponding to the second reference voltage can be easily generated through a waveform conversion. A transient recovery voltage measuring device includes a memory storing a transient recovery voltage waveform of a multiple frequency, a waveform conversion unit converting the transient recovery voltage waveform, a wave height determination unit determining two points having the same maximum value on the converted waveform, an adjustment unit adjusting the proportional constant of the waveform conversion unit to determine those two points by the wave height determination unit, a contact point detection unit obtaining two points corresponding to the determined two points determined by the wave height determination unit, and a tangent line generation unit generating a first tangent line passing through the detected two points on the transient recovery voltage waveform. 1. A transient recovery voltage measuring device comprising:a waveform memory that stores a transient recovery voltage waveform of a multiple frequency;a waveform conversion unit that converts the transient recovery voltage waveform based on a proportional value obtained by multiplying a time from an origin by a proportional constant;a wave height determination unit that determines two points having a same maximum value on a converted waveform;an adjustment unit that adjusts the proportional constant of the waveform conversion unit until two points having the same maximum value are determined by the wave height determination unit;a contact point detection unit that detects two points on the transient recovery voltage waveform corresponding to two points determined by the wave height determination unit; anda first tangent line generation unit that generates a first tangent line passing through the two points detected by the contact point detection unit.2. The transient recovery ...

COMPARATOR WITH TRANSITION THRESHOLD TRACKING CAPABILITY

A comparator is provided having a voltage generator, having an output terminal for providing a reference voltage. The comparator also has a buffer unit, providing an output signal according to a first input signal and the reference voltage; wherein the voltage generator provides the reference voltage according to a second input signal, and the output signal represents a compare result of the first and second input signals. 1. A comparator , comprising:a voltage generator, having an output terminal for providing a reference voltage;a buffer unit, providing an output signal according to a first input signal and a bias signal; anda threshold control loop, providing the bias signal to the buffer unit according to a second input signal, so as to regulate a transition threshold of the buffer unit to close to the second input signal,wherein the output signal represents a compare result of the first and second input signals,wherein the buffer unit and the threshold control loop are powered by the reference voltage.2. The comparator as claimed in claim 1 , wherein the buffer unit comprises:a first PMOS transistor coupled between the output terminal of the voltage generator and a first node, having a gate for receiving the first input signal;a first NMOS transistor coupled to a ground, having a gate for receiving the bias signal;a second NMOS transistor coupled between the first NMOS transistor and the first node, having a gate for receiving the first input signal;a second PMOS transistor coupled between the output terminal of the voltage generator and a second node, having a gate coupled to the first node;a third NMOS transistor coupled to the ground, having a gate for receiving the bias signal; anda fourth NMOS transistor coupled between the third NMOS transistor and the second node, having a gate coupled to the first node,wherein a voltage of the second node represents the compare result of the first and second input signals.3. The comparator as claimed in claim 2 , ...

System and Method for Bootstrapping a Switch Driver

In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

Techniques for Aligning and Reducing Skew in Serial Data Signals

A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals. 1. A circuit comprising:a first aligner circuit operable to align a first input serial data signal with a first control signal to generate a first aligned serial data signal;a second aligner circuit operable to align a second input serial data signal with the first control signal to generate a second aligned serial data signal; anda deskew circuit operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.2. The circuit of claim 1 , wherein the first aligner circuit comprises:first storage circuits operable to store values of the first input serial data signal as first stored signals in response to the first control signal and a second control signal;second storage circuits operable to store values of the first stored signals as second stored signals in response to the first and the second control signals;a first multiplexer circuit operable to receive the second stored signals at multiplexing inputs and to select a first selected signal based on the first and the second stored signals; anda third storage circuit operable to store the first selected signal as the first aligned serial data signal in response to the first control signal.3. The circuit of claim 2 , wherein the second aligner circuit comprises:fourth storage circuits operable to store values of the second input serial data signal as third stored signals in response to the first and the ...

Pulsed Gate Driver

A gate driver includes a control input receiving a control signal, an output to provide an amplified output signal to the gate, and controller. The controller produces an adaptive pulse train varying with the control signal. An adaptive incrementer produces a sequence of numbers that set a slew rate of the switch, and a look-up table is fed with the sequence of numbers, and associates the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal to control the slew rate of the switch. The switch can be driven at various intermediate levels, and allows gate drive conditions to adapted to abnormal system states by varying the control input signal. The adaptive response allows the slew rate to vary without replacing any gate driver circuit components. Because the gate current is provided adaptively, the delivery of gate current results in low power dissipation. 1. A gate driver for driving a gate of a switch , the gate driver comprising:a control input which is adapted to receive a control signal;an output which is adapted to provide an amplified output signal to be fed to the gate of the switch for driving the switch; anda controller comprising an adaptive incrementer and a look-up table,wherein the controller is connected between the control input and the output, and is adapted to produce an adaptive pulse train that varies depending on a characteristic of the control signal,wherein the adaptive incrementer is adapted to produce a sequence of numbers, the values of which allow a slew rate of the switch to be set, andwherein the look-up table is adapted to be fed with the sequence of numbers, and to associate the numbers produced by the adaptive incrementer with values representing the duty cycle of the output signal so as to control the slew rate of the switch.2. The gate driver of claim 1 , wherein the controller is adapted to vary the adaptive pulse train according to the characteristic of the control signal so as to ...

INTERCHANNEL SKEW ADJUSTMENT CIRCUIT

An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption. 1. An interchannel skew adjustment circuit adjusting signal skew between a first channel and a second channel , the circuit comprising:a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal;a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; anda controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit.2. The interchannel skew adjustment circuit of claim 1 , further comprising:a PVT variation detection circuit configured to detect PVT variations of the phase adjustment circuit, and output PVT information indicating the PVT variations; anda PVT variation compensation circuit configured to compensate a control value output from the controller to the phase adjustment circuit based on the PVT information to control the delay amount in the phase adjustment circuit.3. The interchannel skew adjustment circuit of claim 2 , further comprising:another phase ...

Integrated circuit having a multiplying injection-locked oscillator

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

INTEGRATED CIRCUIT

There is disclosed an integrated circuit comprising a management unit for managing the occurrence of predetermined events in the integrated circuit. The management unit comprises: a processing unit adapted to determine the occurrence of a predetermined event in the integrated circuit; a data storage unit adapted to store information regarding the determined event occurrence; an output interface adapted to output a signal based on the stored information regarding the determined event occurrence; and an output generating unit adapted to analyse the stored information and to generate a signal to be output by the output interface based on results of the analysis. 1. An integrated circuit comprising a management unit for managing the occurrence of predetermined events in the integrated circuit , wherein the management unit comprises:a processing unit adapted to determine the occurrence of a predetermined event in the integrated circuit;a data storage unit adapted to store information regarding the determined event occurrence;an output interface adapted to output a signal based on the stored information regarding the determined event occurrence; andan output generating unit adapted to analyse the stored information and to generate a signal to be output by the output interface based on results of the analysis.2. The integrated circuit of claim 1 , wherein the management unit further comprises an input interface adapted to receive a signal from the integrated circuit and to pass the received signal to the processing unit.3. The integrated circuit of claim 1 , wherein the signal to be output by the output interface comprises information regarding at least one occurrence of the predetermined event.4. The integrated circuit of claim wherein the output generating unit is adapted to determine a number of occurrences of a predetermined event and to generate the signal to be output if the determined number of occurrences of the predetermined event exceeds a predetermined threshold ...