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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1172. Отображено 100.
23-08-2012 дата публикации

Adpll circuit, semiconductor device, and portable information device

Номер: US20120212266A1
Автор: Jiro Shimbo, Ryo Endo, Tomomitsu Kitamura
Принадлежит: Renesas Electronics Corp

The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

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Номер записи: 1
27-06-2013 дата публикации

Oscillator with highly-adjustable bang-bang control

Номер: US20130162357A1
Автор: Alvin L. LOKE, Bruce A. Doyle, Emerson S. Fang, Shawn Searles, Stephen F. Greenwood
Принадлежит: Advanced Micro Devices Inc

A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

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Номер записи: 2
22-08-2013 дата публикации

FREQUENCY SYNTHESIZER

Номер: US20130214836A1
Автор: Hieda Morishige, Nakamizo Hideyuki, Tajima Kenichi
Принадлежит: Mitsubishi Electric Corporation

A phase difference detecting circuit includes a sync detecting circuit for detecting establishment of phase sync from phase difference signals D and U generated by a D-type flip-flop and a switch for supplying, unless the sync detecting circuit detects the establishment of the phase sync, the control voltage Vgenerated by the current-output-matching loop filter to a voltage-controlled oscillator and for supplying, when the sync detecting circuit detects the establishment of the phase sync, the control voltage Vgenerated by the voltage-output-matching loop filter to the voltage-controlled oscillator 1. A frequency synthesizer including a reference signal source for generating a reference signal , a sync signal output circuit for dividing a high-frequency signal and for outputting a high-frequency signal after division as a sync signal , a phase difference detecting circuit for detecting phase difference between the reference signal generated by the reference signal source and the sync signal output from the sync signal output circuit and for outputting control voltage corresponding to the phase difference , and a voltage-controlled oscillator for generating a high-frequency signal with a frequency corresponding to the control voltage output from the phase difference detecting circuit and for outputting the high-frequency signal to the sync signal output circuit and to an outside , wherein the phase difference detecting circuit comprises:a first phase comparator for generating a phase difference signal from detection timing of a signal edge of the reference signal and a signal edge of the sync signal;a first control voltage generating circuit for generating the control voltage corresponding to the phase difference signal generated by the first phase comparator;a first flip-flop for inverting amplitude of its output signal every time it detects a signal edge of the sync signal;an inverter for inverting amplitude of the reference signal;a second flip-flop for inverting ...

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Номер записи: 3
19-09-2013 дата публикации

Pll circuit, method of controlling pll circuit, and digital circuit

Номер: US20130241610A1
Автор: Koji Nakamuta, Yoshito Koyama
Принадлежит: Fujitsu Ltd

A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.

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Номер записи: 4
31-10-2013 дата публикации

Reference-Less Frequency Detector

Номер: US20130285752A1
Автор: Afshin Momtaz, Mahyar Kargar, Mehdi KHANPOUR, Namik Kocaman, Siavash Fallahi
Принадлежит: Broadcom Corp

Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

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Номер записи: 5
26-12-2013 дата публикации

PHASE-LOCKED LOOP

Номер: US20130346004A1
Автор: DISSELNKÖTTER Rolf, HOZOI Adrian
Принадлежит: ABB AG

A phase-locked loop is provided for estimating a phase angle of a three-phase reference signal. The phase-locked loop includes a device for calculating an estimated first state and an estimated second state at a fundamental frequency on the basis of the reference signal and the estimated fundamental frequency, a device for calculating a fundamental positive sequence component of the reference signal on the basis of the first state and the second state, a device for calculating a direct component and a quadrature component in a reference frame synchronous with the phase angle on the basis of the fundamental positive sequence component and an estimated phase angle, and a device for determining estimates of the estimated fundamental frequency and the estimated phase angle on the basis of the quadrature component. 1. A phase-locked loop for estimating a phase angle of a three-phase reference signal , wherein the phase-locked loop comprises:means for calculating an estimated first state and an estimated second state of a model of an unbalanced three-phase system at a fundamental frequency of the reference signal on the basis of the reference signal and an estimated fundamental frequency, wherein the model comprises a first state representing a sum of a positive and a negative sequence component of the reference signal at a harmonic frequency, and a second state representing a difference between the positive sequence component and the negative sequence component;means for calculating a fundamental positive sequence component of the reference signal on the basis of the estimated first state and the estimated second state;means for calculating a direct component and a quadrature component in a rotating reference frame synchronous with the estimated phase angle on the basis of the fundamental positive sequence component and an estimated phase angle;means for determining an estimate of an amplitude of the fundamental positive sequence component on the basis of the direct ...

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Номер записи: 6
01-01-2015 дата публикации

Analog Phase-Locked Loop with Enhanced Acquisition

Номер: US20150004919A1
Автор: Ek Staffan
Принадлежит:

An analog phase-locked loop, PLL, () is disclosed, comprising a voltage controlled oscillator (); a frequency divider () having its input connected to an output of the VCO; a first phase detector () arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump () connected to an output of the first phase detector and arranged to divider output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter () connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO. The PLL further comprises a second phase detector () arranged to detect a number of cycles in phase difference between the output signal of the frequency divider and the reference frequency signal and provide an output signal based on the number of cycles in phase difference; and a second charge pump () connected to an output of the second phase detector and arranged to provide a charge per detected phase error, based on the output of the second phase detector, to the loop filter. A radio circuit, a communication device and a communication node are also disclosed. 115-. (canceled)16. An analog phase-locked loop (PLL) comprisinga voltage controlled oscillator (VCO);a frequency divider having its input connected to an output of the VCO;a first phase detector arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal on an output of the first phase detector based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency;a first charge pump connected to the output of the first phase detector and arranged to output a charge per ...

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Номер записи: 7
07-01-2016 дата публикации

APPARATUS AND SYSTEM FOR DIGITALLY CONTROLLED OSCILLATOR

Номер: US20160006443A1
Автор: Abdelmoneum Mohamed A., ABDELSALAM Mohamed A., EL MAHALAWY Mohammed W., KURD Nasser A., LOTFY Amr M.
Принадлежит:

Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply. 123-. (canceled)24. An apparatus comprising:a digitally controlled oscillator (DCO);a supply node to provide a regulated power supply to the DCO through a variable resistor; anda digital loop filter (DLF) coupled to the DCO to generate a digital code according to a phase error, wherein the digital code is to adjust resistance of the variable resistor to modify the regulated power supply.25. The apparatus of comprises a circuit to receive the digital code and to generate a control signal according to the digital code.26. The apparatus of comprises a phase detector to detect the phase error between a reference signal and a feedback signal.27. The apparatus of claim 26 , wherein the phase detector is to provide the phase error indicating a phase lead condition or a phase lag condition.28. The apparatus of comprises a divider to receive an output of the DCO and to provide the feedback signal.29. The apparatus of claim 24 , wherein the DCO comprises an odd number of delay cells.30. The apparatus of claim 29 , wherein at least one of the delay cells is an inverter.31. The apparatus of claim 24 , wherein the DCO comprises an even number of delay cells.32. The apparatus of claim 31 , wherein at least one of the delay cells is an inverter.33. The apparatus of claim 24 , wherein the DCO comprises delay cells ...

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Номер записи: 8
04-01-2018 дата публикации

METHODS AND APPARATUS FOR PERFORMING A HIGH SPEED PHASE DEMODULATION SCHEME USING A LOW BANDWIDTH PHASE-LOCK LOOP

Номер: US20180006856A1
Автор: Bonu Madhulatha, Mukherjee Subhashish, Patki Abhijit Anant, Shrivastava Kumar Anurag
Принадлежит:

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop. 1. An apparatus comprising:a low bandwidth phase lock loop to:lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; andoutput a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop; anda fast phase change detection circuit coupled to the low bandwidth phase lock loop to:determine whether the data signal is oscillating at the first phase or the second phase;when the data signal is oscillating at the first phase, output a first logic value; andwhen the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal ...

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Номер записи: 9
18-01-2018 дата публикации

RADAR TARGET DETECTION SYSTEM FOR AUTONOMOUS VEHICLES WITH ULTRA-LOW PHASE NOISE FREQUENCY SYNTHESIZER

Номер: US20180019755A1
Автор: Josefsberg Yekutiel, Lavian TaI
Принадлежит:

An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method for autonomous vehicle is also disclosed. 1. An autonomous vehicle system , comprising: a). at least one transmitter for transmitting at least one radio signal to the at least one object;', 'b). at least one receiver for receiving the at least one radio signal returned from the at least one object;', (i) at least one clocking device configured to generate at least one clock signal of at least one clock frequency;', (a) at least one sampling phase detector configured to receive the at least one clock signal and a single reference frequency to generate at least one first analog control voltage; and', '(b) at least one reference Voltage Controlled Oscillator (VCO) configured to receive the at least one first analog control voltage or at least one second analog control voltage to generate the single reference frequency, wherein at least one digital control voltage controls one of the at least one first analog control voltage or the at least one second analog control voltage received by the at least one reference VCO;, '(ii) at least one sampling Phase ...

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Номер записи: 10
18-01-2018 дата публикации

FRACTIONAL-N PHASE LOCKED LOOP DELTA SIGMA MODULATOR NOISE REDUCTION USING CHARGE PUMP INTERPOLATION

Номер: US20180019756A1
Автор: Bossu Frederic, CHEN Xinhua, Tang Yiwu, ZHUANG Jingcheng
Принадлежит:

A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider. 1. A phase locked loop , comprising:a frequency divider included in a feedback path, the frequency divider generating a first frequency divider output and a delayed frequency divider output that is a delayed version of the first frequency divider output;a charge pump to generate an output current based at least in part on the first frequency divider output and the delayed frequency divider output of the frequency divider; andat least one phase frequency detector (PFD) coupled between the frequency divider and the charge pump, the at least one PFD generating multiple down control signals.2. The phase locked loop of claim 1 , further comprising a voltage controlled oscillator (VCO) claim 1 , in which the delayed frequency divider output is based at least in part on a cycle of the VCO.3. The phase locked loop of claim 1 , in which the frequency divider is controlled by a delta sigma modulator.4. The phase locked loop of claim 1 , further comprising a delay block that generates the delayed frequency divider output.5. The phase locked loop of claim 4 , in which the frequency divider includes the delay block.6. (canceled)7. The phase locked loop of claim 1 , in which the at least one PFD receives the first frequency divider output and the delayed frequency divider output as inputs.8. The phase locked loop of claim 1 , in which the at least one PFD outputs a control signal used by the charge pump to generate the output current.9. The phase locked loop of claim 1 , in which the charge pump comprises multiple current sources claim 1 , each of the multiple current sources being controlled based on a corresponding one of the down control signals to generate the output current claim 1 , ...

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Номер записи: 11
18-01-2018 дата публикации

Signal recovery circuit, electronic device, and signal recovery method

Номер: US20180019864A1
Автор: Yukito Tsunoda
Принадлежит: Fujitsu Ltd

A signal recovery circuit includes an oscillator that generates a first clock of which a frequency is variable, and a feedback circuit that controls the oscillator to synchronize the first clock with input data, depending on a phase relationship between the input data and the first clock, the feedback circuit including a control portion that controls the oscillator depending on the phase relationship between the input data and the first clock, a first phase detection circuit that generates a clock phase control signal depending on the phase relationship between the input data and the first clock, an output data generation circuit that generates output data by latching the input data at a change edge of the first clock, and a lock detection circuit that outputs a lock detection signal indicating whether a state is a lock state or a non-lock state.

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Номер записи: 12
17-01-2019 дата публикации

Pll circuit

Номер: US20190020348A1
Автор: Takeshi Endo
Принадлежит: Nihon Dempa Kogyo Co Ltd

A PLL circuit includes a voltage control oscillator, a frequency difference detector, a phase difference detector, and an outputter. The frequency difference detector detects a frequency difference between a reference signal and the oscillation signal and outputs a first control value based on the detected frequency difference. The phase difference detector detects a phase difference between the reference signal and the oscillation signal, and outputs a second control value based on the detected phase difference. The outputter outputs the control voltage based on the first control value and the second control value to the voltage control oscillator while the second control value does not exceed a predetermined range, and outputs the control voltage based on a corrected value obtained by correcting the first control value and the second control value to the voltage control oscillator while the second control value exceeds a predetermined range.

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Номер записи: 13
23-01-2020 дата публикации

COMPACT PHASE-LOCKED LOOP WITH LOW JITTER AND REFERENCE SPURS

Номер: US20200028515A1
Автор: Kinget Peter R., Nagam Shravan Siddartha
Принадлежит:

The present disclosure relates to a phase-locked loop (PLL) including a frequency detector, a sub-sampling phase detector (SSPD), and a voltage-controlled oscillator (VCO). The frequency detector is configured to receive a reference signal and an output signal, and to generate a coarse-tuning voltage that indicates a frequency difference between the reference signal and the output signal. The SSPD is configured to sub-sample the output signal using the reference signal, and to generate a fine-tuning voltage that indicates a phase difference between the reference signal and the output signal. The VCO is configured to update the output signal based on the coarse-tuning voltage and the fine-tuning voltage. 1. A phase-locked loop (PLL) comprising:a frequency divider, which is configured to receive an output signal and generate a divided signal by frequency dividing the output signal with a frequency divide ratio;a frequency detector, which is configured to receive a reference signal and the divided signal, and generate a coarse-tuning voltage, wherein the coarse-tuning voltage indicates a frequency difference between the reference signal and the divided signal; the buffered divided signal and the divided signal have a same frequency; and', 'the buffered divided signal has a higher slope and shorter rising time than the divided signal;, 'a controlled slope buffer configured to receive the divided signal and generate a buffered divided signal, whereina sub-sampling phase detector (SSPD), which is configured to sub-sample the buffered divided signal using the reference signal, and generate a fine-tuning voltage, wherein the fine-tuning voltage indicates a phase difference between the reference signal and the buffered divided signal; anda voltage-controlled oscillator (VCO), which is configured to adjust the output signal based on the coarse-tuning voltage and the fine-tuning voltage.2. The PLL of wherein the frequency divide ratio is 2.3. The PLL of wherein the VCO is a ...

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Номер записи: 14
17-02-2022 дата публикации

SIGNAL GENERATION CIRCUIT AND METHOD, AND DIGIT-TO-TIME CONVERSION CIRCUIT AND METHOD

Номер: US20220052703A1
Автор: Wei Xiangye, Xiu Liming
Принадлежит:

A signal generating electric circuit, a signal generating method, a digit-to-time converting electric circuit and a digit-to-time converting method. The signal generating electric circuit includes: a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; and a second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal. The first frequency control word includes a first integer part and a first fractional part, the second frequency control word includes a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part is not zero, the second fractional part is zero, and a period of the first output signal and a period of the second output signal are not equal. 1. A signal generating electric circuit , comprising:a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; anda second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal;wherein the first frequency control word comprises a first integer part and a first fractional part, the second frequency control word comprises a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part is not zero, the second fractional part is zero, and a period of the first output signal and a period of the second output signal are not equal.2. The signal generating electric circuit according to claim 1 , wherein a periodic inequality between the period of the first output signal and the period of the second output signal is related to the reference time unit and the first ...

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Номер записи: 15
31-01-2019 дата публикации

DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS

Номер: US20190036534A1
Автор: DENG Jingdong, FLYE David, HO Rupert Shiu Chung, JIN Zhenrong, MALLADI Ramana M.
Принадлежит:

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator. 1. A phase locked loop circuit , comprising a feedback path connecting an output of a mixed mode controlled ring oscillator to a digital path and an analog path , wherein the digital path and the analog path modify a frequency of the mixed mode controlled ring oscillator simultaneously.2. The phase locked loop circuit of claim 1 , wherein the mixed mode controlled ring oscillator has different inputs claim 1 , with an input connected to the digital path and another input connected to the analog path3. The phase locked loop circuit of claim 1 , wherein the digital path discretely controls a frequency of the mixed mode controlled ring oscillator and the analog path progressively controls a frequency of the mixed mode controlled ring oscillator.4. The phase locked loop circuit of claim 1 , wherein the analog path includes a linear phase detector.5. The phase locked loop circuit of claim 4 , wherein the mixed mode controlled ring oscillator includes an analog control logic and a ring oscillator array.6. The phase locked loop circuit of claim 5 , wherein the analog control logic determines a plurality of control signals for modifying a frequency of the mixed mode controlled ring oscillator based ...

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Номер записи: 16
15-02-2018 дата публикации

DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS

Номер: US20180048321A1
Автор: DENG Jingdong, FLYE David, HO Chung S., JIN Zhenrong, MALLADI Ramana M.
Принадлежит:

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator. 1. A phase locked loop circuit , comprising:a mixed mode controlled ring oscillator having different inputs, with an input connected to a digital path and another input connected to an analog path; anda feedback path connecting an output of the mixed mode controlled ring oscillator to the digital path and to the analog path.2. The phase locked loop circuit of claim 1 , wherein the digital path and the analog path control a frequency of the mixed mode controlled ring oscillator.3. The phase locked loop circuit of claim 1 , wherein the digital path discretely controls a frequency of the mixed mode controlled ring oscillator and the analog path progressively controls a frequency of the mixed mode controlled ring oscillator.4. The phase locked loop circuit of claim 1 , wherein the analog path includes a linear phase detector.5. The phase locked loop circuit of claim 4 , wherein the mixed mode controlled ring oscillator includes an analog control logic and a ring oscillator array.6. The phase locked loop circuit of claim 5 , wherein the analog control logic determines a plurality of control signals for modifying a frequency of the mixed mode controlled ring oscillator based on an analog tuning ...

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Номер записи: 17
15-05-2014 дата публикации

LOSS OF LOCK DETECTOR FOR CLOCK AND DATA RECOVERY SYSTEM

Номер: US20140132320A1
Автор: Mobin Mohammad S., Sindalovsky Vladimir, Smith Lane A.
Принадлежит: LSI Corporation

An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values. 1. An apparatus comprising:a clock and data recovery system; anda loss of lock detector associated with the clock and data recovery system and configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system.2. The apparatus of wherein the loss of lock signal has a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate claim 1 , the second rate being associated with a loss of lock condition.3. The apparatus of wherein the loss of lock detector is at least partially implemented within the clock and data recovery system.4. The apparatus of wherein the clock and data recovery system comprises:slicer circuitry configured to sample a serial data stream;a phase detector configured to process samples from the slicer circuitry; anda phase control loop having an input coupled to an output of the phase detector and an output ...

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Номер записи: 18
25-02-2021 дата публикации

Phase locked loop circuit

Номер: US20210058090A1
Автор: Maksim Kuzmenka, Mani Balakrishnan, Martin Brox, Yasuhiro Takai
Принадлежит: Micron Technology Inc

Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.

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Номер записи: 19
17-03-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220085818A1
Автор: MATSUI Katsuaki, Ogawa Junya
Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit , and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal. 1. A semiconductor device that is configured to output , as an output signal synchronized to a phase-locked loop clock signal , a synchronized input signal having been synchronized to a reference clock signal of a phase-locked loop circuit , the semiconductor device comprising:the phase-locked loop circuit configured to receive as an input signal the reference clock signal;a first flip-flop that is configured to receive at a first data input terminal an input signal in synchronization with the reference clock signal and at a first clock terminal a feedback signal inputted to a phase comparator of the phase-locked loop circuit; anda second flip-flop having a second data input terminal connected to a first output terminal of the first flip-flop,{'claim-text': ['the phase-locked loop circuit, the first flip-flop, and the second flip-flop are configured such that a setup time in the feedback signal for the first flip-flop to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal,', 'the phase-locked loop circuit comprises a frequency divider configured to frequency-divide the phase- ...

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Номер записи: 20
19-03-2015 дата публикации

Clock data recovery circuit

Номер: US20150078427A1
Автор: Shih-Chun Lin
Принадлежит: Himax Technologies Ltd

A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.

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Номер записи: 21
17-03-2016 дата публикации

Fractional n-pll circuit, oscillator, electronic device, and moving object

Номер: US20160079988A1
Автор: Nobutaka Shiozaki
Принадлежит: Seiko Epson Corp

In order to appropriately set an operation range of a voltage controlled oscillator without excessively increasing a frequency at which delta-sigma modulation is performed, a fractional N-PLL circuit includes: a voltage controlled oscillator that is configured to set plural output frequency ranges; a frequency selection circuit that selects one output frequency range; a division circuit; and a division setting circuit that sets a division ratio of the division circuit. The division setting circuit performs, while the frequency selection circuit is searching for the plural output frequency ranges of the voltage controlled oscillator, the delta-sigma modulation at a frequency lower than a frequency after the frequency selection circuit terminates the search.

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Номер записи: 22
15-03-2018 дата публикации

SYSTEM AND METHOD OF CALIBRATING INPUT SIGNAL TO SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) IN ADC-ASSISTED TIME-TO-DIGITAL CONVERTER (TDC)

Номер: US20180076821A1
Автор: Loke Wing-Fai, Yao Chih-Wei
Принадлежит:

An apparatus and a method. The apparatus includes a counter array; a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator; an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; and an ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator. 1. An apparatus , comprising:a counter array;a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator;an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; andan ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator.2. The apparatus of claim 1 , further comprising a phase/frequency detector (PFD) connected to the ring oscillator that includes a first input for receiving a reference clock signal claim 1 , a second input for receiving a feedback clock signal claim 1 , and an output for providing an enable signal.3. The apparatus of claim 1 , further comprising a plurality of time-to-digital-converter (TDC) buffers connected to the outputs of the ring oscillator.4. The apparatus of claim 3 , further comprising an interpolating resistive network connected to outputs of the plurality of TDC buffers.5. The apparatus of claim 3 , further comprising a multiplexer connected to the outputs of the TDC buffers.6. The apparatus of claim 5 , further comprising a programmable analog-to-digital converter (ADC) driver connected to an output of the multiplexer.7. The apparatus of claim 1 , wherein the ring oscillator includes a plurality of buffers connected in a ring claim 1 , and wherein each of the outputs of the ring oscillator are connected to one of the plurality of buffers claim 1 , respectively.8. The apparatus of claim 1 , further comprising a ...

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Номер записи: 23
18-03-2021 дата публикации

EFFICIENT FREQUENCY DETECTORS FOR CLOCK AND DATA RECOVERY CIRCUITS

Номер: US20210083839A1
Автор: Abramzon Valentin
Принадлежит:

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low. 1. A method of frequency detection comprising:sampling a data input to obtain an odd data sample of the input data (Dodd);sampling the data input to obtain an odd crossing sample of the input data (Xodd);sampling the data input to obtain an even data sample of the input data (Deven);sampling the data input to obtain an even crossing sample of the input data (Xeven);generating an UP odd signal according to the Dodd, Xodd, and Deven samples;generating a DOWN odd signal according to the Dodd, Xodd, and Deven samples;generating an UP even signal according to the Deven, Xeven, and Dodd samples; andgenerating a DOWN even signal according to the Deven, Xeven, and Dodd samples.2. The method of frequency detection of claim 1 , wherein generating the UP odd signal according to the Dodd claim 1 , Xodd claim 1 , and Deven samples comprises:determining an odd first edge signal according to the Dodd and Xodd samples, wherein the odd first edge signal is high when the Dodd and Xodd samples have different values;determining an odd second edge signal according to the Xodd and Deven samples, wherein the odd second edge signal is high when the Xodd and Deven samples have different values; andoutputting the UP odd signal when the odd first edge signal and the odd second edge signal are both high.3. The method of frequency detection of claim 1 , wherein generating the DOWN odd signal ...

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Номер записи: 24
22-03-2018 дата публикации

DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS

Номер: US20180083640A1
Автор: DENG Jingdong, FLYE David, HO Chung S., JIN Zhenrong, MALLADI Ramana M.
Принадлежит:

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator. 1. A circuit , comprising:a digital path outputting a digital tuning signal to an input of a ring oscillator;an analog path outputting an analog tuning signal to a different input of the ring oscillator; anda feedback path directly connecting an output of the ring oscillator to the digital path and to the analog path.2. The phase locked loop circuit of claim 1 , wherein the analog path includes a linear phase detector and a proportional gain device.3. The phase locked loop circuit of claim 2 , wherein the linear phase detector determines whether a reference signal leads or lags a feedback signal from the feedback path.4. The phase locked loop circuit of claim 3 , wherein based on the determination that the reference signal leads or lags the feedback signal claim 3 , the linear phase detector generates one or more outputs proportional to a phase difference between the reference signal and the feedback signal.5. The phase locked loop circuit of claim 4 , wherein the proportional gain device receives an output from the linear phase detector and generates the analog tuning signal having a voltage proportional to the phase difference between the reference signal and the feedback signal.6. The ...

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Номер записи: 25
22-03-2018 дата публикации

DATA-DRIVEN PHASE DETECTOR ELEMENT FOR PHASE LOCKED LOOPS

Номер: US20180083809A1
Автор: Hormati Ali, Tajalli Armin
Принадлежит:

Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition. 1. An apparatus comprising: receive (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals;', 'responsive to a determination that a transition occurred in the corresponding data signal, generate a partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal; and, 'a data-driven phase comparator circuit configured to receive a plurality of data signals in parallel from a plurality of multi-input comparators (MICS) connected to a multi-wire bus, wherein at least one MIC is connected to at least three wires of the multi-wire bus, and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, each partial phase comparator configured toa summation circuit configured to receive each partial phase-error signal and to generate a composite phase-error signal to set a local oscillator generating the one ...

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Номер записи: 26
12-03-2020 дата публикации

Sub sampling phase locked loop (sspll) with wide frequency acquisition

Номер: US20200083892A1
Автор: ABHISHEK Agrawal, Somnath Kundu, Stefano Pellerano
Принадлежит: Apple Inc

A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.

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Номер записи: 27
31-03-2022 дата публикации

PHASE LOCK LOOP REFERENCE LOSS DETECTION

Номер: US20220103181A1
Автор: Das Venkatseema, Fu Wei, Ghotgalkar Shailesh Ganapat
Принадлежит:

In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator. 1. A circuit , comprising:a first input configured to receive a first clock signal;a second input configured to receive a second clock signal;a comparator coupled to the first input and the second input, the comparator configured to perform a comparison of the first clock signal and the second clock signal; andan output configured to output a fault signal based on the comparison.2. The circuit of claim 1 , wherein:the first clock signal is an output from a clock divider.3. The circuit of claim 1 , wherein:the second clock signal is an output from a code generator configured to generate a code in response to an input reference signal.4. The circuit of claim 1 , further comprising:a first register having a first register input coupled to the first clock signal, a second register input coupled to the second clock signal, and a first register output;a second register having a third register input coupled to the first clock signal, a fourth register input coupled to the first register output, and a second register output; anda third register having a fifth register input coupled to the first clock signal, sixth register input coupled the second register output, and a third register output.5. The circuit of claim 4 , wherein:the comparator includes a first comparator configured to compare the first register output and the second register output; andthe comparator includes a second comparator configured to compare the second register output and the third register output.6. The circuit of claim 5 , wherein:the first ...

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Номер записи: 28
29-03-2018 дата публикации

DUAL-PFD FEEDBACK DELAY GENERATION CIRCUIT

Номер: US20180091157A1
Автор: Goyal Jagdish Chand, Mirajkar Peeyoosh, Srinivas Theertham
Принадлежит:

A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal. the dual-PFD circuit can be used with a charge-pump coupled to the dual PFD circuit, and responsive the phase comparison signal to generate a frequency tuning voltage, for input to a VCO for generating the VCO clock signal. The dual PFD circuit, charge pump and VCO can be used in a PLL frequency synthesizer. 1. A circuit for phase detection , comprisinga PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals, includinga dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 based on a divide mode control input to generate a prescaled divide signal;a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal;a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal;the prescaler responsive to the pre-defined delay from the delay generation circuit to change divide modes;a dual PFD circuit response to the FB and FB_DLY signals in ...

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Номер записи: 29
29-03-2018 дата публикации

CIRCUIT DEVICE, PHYSICAL QUANTITY MEASUREMENT APPARATUS, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20180091158A1
Автор: Haneda Hideo, KURASHINA Takashi, MAKI Katsuhiko, SUDO Yasuhiro, TSUTSUMI Akio
Принадлежит:

A circuit device includes: a time-to-digital conversion circuit to which a first clock signal with a first clock frequency and a second clock signal with a second clock frequency different from the first clock frequency are input and that converts a time difference in transition timings of first and second signals into a digital value; and a synchronization circuit that synchronizes phases of the first and second clock signals. The time-to-digital conversion circuit calculates the digital value corresponding to the time difference by transitioning a signal level of the first signal based on the first clock signal after a phase synchronization timing of the first and second clock signals and compares the phase of the second clock signal to a phase of the second signal having a signal level is transitioned to correspond to the first signal. 1. A circuit device comprising:a time-to-digital conversion circuit configured to receive a first clock signal and a second clock signal, and to convert a time difference in transition timings of first and second signals into a digital value, the first clock signal having a first clock frequency, the second clock signal having a second clock frequency, the second clock frequency being a different frequency than the first clock frequency; anda synchronization circuit configured to synchronize phases of the first and second clock signals input to the time-to-digital conversion circuit,wherein the time-to-digital conversion circuit is configured to calculate the digital value corresponding to the time difference by transitioning a signal level of the first signal based on the first clock signal after a phase synchronization timing of the first and second clock signals and to compare the phase of the second clock signal to a phase of the second signal having a signal level transitioned to correspond to the first signal.2. The circuit device according to claim 1 ,wherein the time-to-digital conversion circuit is configured to transition ...

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Номер записи: 30
26-06-2014 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20140176207A1
Автор: KIM Kwan Dong
Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal. 1. A semiconductor apparatus comprising:a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal;a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; anda data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.2. The semiconductor apparatus according to claim 1 , wherein the delay amount control unit comprises:a first converter configured to generate the phase of the external data as the first code;a second converter configured to generate the phase of the data latch clock signal as the second code; anda calculator configured to calculate a difference between the first and second codes and generate a delay code.3. The semiconductor apparatus according to claim 2 , wherein the first converter generates a rising time point of the external data before a rising time point of the data latch clock signal as the first code claim 2 , based on the rising time point of the data latch clock signal.4. The semiconductor apparatus according to claim 2 , wherein the first converter comprises:a plurality of first delays configured to sequentially delay the external data by a first delay amount;a plurality of second delays ...

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Номер записи: 31
19-03-2020 дата публикации

HYBRID PHASE LOCK LOOP

Номер: US20200091919A1
Автор: CHANG Chih-Hsien, Hsieh Cheng-Hsiang, Sheen Ruey-Bin, TSAI Tsung-Hsien
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operational mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operational mode of the hybrid PLL. 1. A phase lock loop (PLL) , comprising:a first loop configured to provide a digital output signal based upon on a comparison of a reference input signal and an output signal of the PLL in a first operational mode of the PLL;a second loop configured to provide an analog output signal based on a comparison of the reference input signal and a feedback signal that is proportional to the output signal in a second operational mode of the PLL; andan oscillator coupled to the first loop and the second loop, configured to tune the output signal in accordance with the digital output signal in the first operational mode of the PLL and to tune the output signal in accordance with the analog output signal in the second operational mode of the PLL,wherein the first loop comprises an oscillator controller configured to disable the second loop in the first operational mode of the PLL and to enable the second loop in the second operational mode of the PLL.2. The PLL of claim 1 , wherein the first loop further comprises:a frequency detector configured to compare the reference input ...

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Номер записи: 32
19-03-2020 дата публикации

EFFICIENT FREQUENCY DETECTORS FOR CLOCK AND DATA RECOVERY CIRCUITS

Номер: US20200092077A1
Автор: Abramzon Valentin
Принадлежит:

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low. 1. A frequency detector circuit comprising:a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input;a first circuit configured to generate a second edge output;a second circuit configured to generate a third edge output; and output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high; and', 'output a DOWN output when the first edge output, the second edge output, and the third edge output are all low,, 'a combinational logic configured towherein the first circuit comprises a first delay circuit and the second circuit comprises a second delay circuit.2. (canceled)3. The frequency detector of claim 1 , wherein the combinational logic comprises:a DOWN logic; andan UP logic.4. A frequency detector circuit comprising:a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input;a first circuit configured to generate a second edge output;a second circuit configured to generate a third edge output; and output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high; and', 'output a DOWN output when the first edge output, the second edge output, and the third edge output are all low,, 'a combinational logic configured to a ...

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Номер записи: 33
06-04-2017 дата публикации

Ultra low phase noise frequency synthesizer

Номер: US20170099058A1
Автор: Tal I. Lavian, Yekutiel Josefsberg
Принадлежит: Lavian Tal I, Yekutiel Josefsberg

A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate.

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Номер записи: 34
20-04-2017 дата публикации

FREQUENCY GENERATING CIRCUIT USING QUARTZ CRYSTAL RESONATOR

Номер: US20170111051A1
Автор: Wang Ping-Ying
Принадлежит:

A frequency generating circuit includes: a differential delay circuit arranged to operably delay an input signal to generate a first delayed signal and a second delayed signal; a quartz crystal resonator arranged to operably conduct a band-pass filtering operation on one of the first and second delayed signals to generate a frequency signal; a compensation capacitor, coupled between another output of the differential delay circuit and an output of the quartz crystal resonator, arranged to operably suppress noise in the frequency signal; an oscillator arranged to operably generate an oscillating signal under control of a control signal; a frequency divider arranged to operably conduct a frequency-dividing operation on the oscillating signal to generate the input signal; and a feedback control circuit arranged to operably generate the control signal according to the frequency signal. 1100. A frequency generating circuit () , comprising:{'b': '110', 'a differential delay circuit (), arranged to operably delay an input signal (Sin; Sin+, Sin−) to generate a pair of differential delayed signals (Sd+, Sd−), wherein the pair of differential delayed signals (Sd+, Sd−) includes a first delayed signal (Sd+) and a second delayed signal (Sd−);'}{'b': 120', '110, 'a quartz crystal resonator (), coupled with one output of the differential delay circuit (), arranged to operably conduct a band-pass filtering operation on one of the first and second delayed signals (Sd+, Sd−) to generate a frequency signal (Fout);'}{'b': 130', '110', '120, 'a compensation capacitor (), coupled between another output of the differential delay circuit () and an output of the quartz crystal resonator (), arranged to operably suppress noise in the frequency signal (Fout);'}{'b': '140', 'an oscillator () arranged to operably generate an oscillating signal (Fosc; Fosc+, Fosc−) under control of a control signal (CTL);'}{'b': 150', '140', '110, 'a frequency divider (), coupled with the oscillator () and the ...

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Номер записи: 35
11-04-2019 дата публикации

PHASE-LOCKED LOOP (PLL) CIRCUIT

Номер: US20190109596A1
Автор: DAKE Tuli, EL MARKHI Mustapha, OZALEVLI ERHAN
Принадлежит:

One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current. 1. A phase-locked loop (PLL) circuit comprising:a frequency divider configured to generate a first set of non-overlapping switching signals based on an input signal;a phase detector configured to generate a second set of non-overlapping switching signals based on an input signal and a PLL output signal;at least one linear frequency-to-analog converter configured to generate a control signal having an amplitude that is based on the first and second sets of non-overlapping switching signals; anda linear oscillator configured to generate the PLL output signal to have a frequency and phase that approximate the input signal based on the amplitude of the control signal.2. The circuit of claim 1 , wherein the at least one linear frequency-to-analog converter is configured as at least one linear frequency-to-current converter that is configured to generate the control signal as a control current based on the frequency of the input signal claim 1 , and is further configured to adjust the amplitude of the control current in a feedback manner based on a phase difference between the input signal and the PLL output signal to substantially phase-align the PLL output signal to the input signal.3. The circuit of claim 1 , wherein the frequency divider and phase detector is configured to generate a first set of non- ...

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Номер записи: 36
09-04-2020 дата публикации

COMPUTER READABLE STORAGE MEDIUM, QUICK-START CLOCK SYSTEM AND CONTROL METHED THEREOF

Номер: US20200112315A1
Автор: ZHANG Mengwen
Принадлежит:

The present disclosure discloses a quick-start clock system, which includes: a digital subsidiary circuit configured to output a digital control value; a phase-locked loop including a programmable voltage-controlled oscillator circuit and a frequency dividing circuit connected to each other and both connected to the digital subsidiary circuit, the programmable voltage-controlled oscillator circuit obtains the digital control value output, and output a clock signal according to the digital control value, the frequency dividing circuit performs a frequency dividing operation on the clock signal; and a crystal oscillator circuit connected to the phase-locked loop, which includes a crystal and an oscillation injecting circuit connected to the crystal, the oscillation injecting circuit converts the clock signal performed with the frequency dividing operation to a co-frequency fully differential signal, and inject the co-frequency fully differential signal into the crystal. 1. A quick-start clock system , comprising:a digital subsidiary circuit, configured to output a digital control value;a phase-locked loop, comprising a programmable voltage-controlled oscillator circuit and a frequency dividing circuit, wherein the programmable voltage-controlled oscillator circuit and the frequency dividing circuit are connected to the digital subsidiary circuit, and the frequency dividing circuit is connected to the programmable voltage-controlled oscillator circuit, the programmable voltage-controlled oscillator circuit is configured to obtain the digital control value output by the digital subsidiary circuit, and output a clock signal according to the digital control value, the frequency dividing circuit is configured to perform a frequency dividing operation on the clock signal output by the programmable voltage-controlled oscillator circuit; and,a crystal oscillator circuit connected to the phase-locked loop, comprising a crystal and an oscillation injecting circuit connected to ...

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Номер записи: 37
14-05-2015 дата публикации

Apparatus and method for frequency locking

Номер: US20150131766A1
Автор: Kuan-Yu Chen, Yuan-Min Hu
Принадлежит: Faraday Technology Corp

An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address.

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Номер записи: 38
16-04-2020 дата публикации

INTEGRATED CIRCUIT DETECTING FREQUENCY AND PHASE OF CLOCK SIGNAL AND CLOCK AND DATA RECOVERY CIRCUIT INCLUDING THE INTEGRATED CIRCUIT

Номер: US20200119739A1
Автор: BURM Jin-wook, CHOI Jung-myung, KWAK Myoung-bo, LEE Dae-wung, SHIN JONG-SHIN, SHIN Seong-kyun, YU Chang-zhi
Принадлежит:

An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal. 1. An integrated circuit comprising:a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal;a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; anda control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.2. The integrated circuit of claim 1 , wherein the at least one phase-shifted clock signal includesa plurality of equally divided clock signals having a phase difference of a constant first interval, andat least one unequally divided clock signal having a phase difference of a second interval that is less than the first interval from one ...

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Номер записи: 39
10-05-2018 дата публикации

Phase-locked loop (pll) circuit

Номер: US20180131377A1
Автор: Erhan Ozalevli, Mustapha El Markhi, Tuli DAKE
Принадлежит: Texas Instruments Inc

One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.

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Номер записи: 40
10-05-2018 дата публикации

METHODS AND APPARATUS FOR PERFORMING A HIGH SPEED PHASE DEMODULATION SCHEME USING A LOW BANDWIDTH PHASE-LOCK LOOP

Номер: US20180131545A1
Автор: Bonu Madhulatha, Mukherjee Subhashish, Patki Abhijit Anant, Shrivastava Kumar Anurag
Принадлежит:

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase. 1. An apparatus comprising:a first bandwidth phase lock loop to:lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; andoutput a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the first bandwidth phase lock loop; anda fast phase change detection circuit coupled to the first bandwidth phase lock loop to:determine whether the data signal is oscillating at the first phase or the second phase;when the data signal is oscillating at the first phase, output a first logic value; andwhen the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the first bandwidth phase lock loop.2. The apparatus of claim 1 , wherein the first bandwidth phase lock loop includes:a first phase frequency detector to (A) receive the data signal and the first output signal and (B) output a first pulse signal corresponding to a first phase difference between the data signal ...

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Номер записи: 41
11-05-2017 дата публикации

ALL-DIGITAL PHASE LOCK LOOP SPUR REDUCTION USING A CRYSTAL OSCILLATOR FRACTIONAL DIVIDER

Номер: US20170134030A1
Автор: Lopelli Emanuele, Mofidi Mahbod, WANG Charles, WIKLUND Magnus Olov
Принадлежит:

Disclosed are methods and apparatuses for reducing fractional spurs in an All-Digital Phase Lock Loop (ADPLL). An exemplary apparatus includes a crystal oscillator configured to generate a first frequency reference signal, a non-integer divider coupled to the crystal oscillator and configured to divide the first frequency reference signal by a non-integer variable to generate a second frequency reference signal, and a multiplexor coupled to the non-integer divider and the crystal oscillator and configured to output the first frequency reference signal or the second frequency reference signal to the ADPLL, wherein the multiplexor is configured to output the second frequency reference signal based on the ADPLL being tuned to a low fractionality channel. 1. An apparatus for reducing fractional spurs in an All-digital Phase Lock Loop (ADPLL) , comprising:a crystal oscillator configured to generate a first frequency reference signal;a non-integer divider coupled to the crystal oscillator and configured to divide the first frequency reference signal by a non-integer variable to generate a second frequency reference signal; anda multiplexor coupled to the non-integer divider and the crystal oscillator and configured to output the first frequency reference signal or the second frequency reference signal to the ADPLL,wherein the multiplexor is configured to output the second frequency reference signal based on the ADPLL being tuned to a low fractionality channel.2. The apparatus of claim 1 , wherein the low fractionality channel occurs when a ratio of an output of the ADPLL to the first frequency reference signal results in a ratio that has a low fractional part.3. The apparatus of claim 2 , wherein the ratio that has the low fractional part comprises a ratio that has a fractional part below a fractionality threshold.4025. The apparatus of claim 3 , wherein the fractionality threshold comprises a value of ..5. The apparatus of claim 2 , wherein a fractional part of the ratio ...

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Номер записи: 42
07-08-2014 дата публикации

Methods and devices for multiple-mode radio frequency synthesizers

Номер: US20140218086A1
Автор: CAO-THONG Tu, Olivier Burg
Принадлежит: MARVELL WORLD TRADE LTD

Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.

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Номер записи: 43
02-05-2019 дата публикации

Method And System For Phase Alignment Of Multiple Phased Locked Loops

Номер: US20190131979A1
Автор: NILSSON MAGNUS
Принадлежит:

A system and method for phase alignment of multiple PLLs are disclosed. The system comprises a plurality N of PLLs (PLL_ . . . PLL_N) and a plurality N of phase detectors (DET_ . . . DET_N). The plurality N of phase detectors and the plurality N of PLLs are connected in a loop such that an i-th phase detector (DET_i) is configured to receive an i-th feedback signal (FB_i) generated from the i-th PLL and an (i+1)-th feedback signal (FB_i+1) generated from the (i+1)-th PLL, and the N-th phase detector (DET_N) is configured to receive the first feedback signal (FB_) generated from the first PLL and the N-th feedback signal (FB_N) generated from the N-th PLL. The an i-th phase detector (DET_i) is configured to generate an i-th adjustment signal indicating an i-th phase difference between the i-th and (i+1)-th feedback signals for adjusting a phase of the i-th or (i+1)-th PLL, wherein i=1, 2, 3, . . . N−1. The N-th phase detector (DET_N) is configured to generate a N-th adjustment signal indicating a N-th phase difference between the first and N-th feedback signals. 116-. (canceled)17. A system for phase alignment of multiple phase adjustable Phased Locked Loops (PLLs) , the system comprising: an oscillator configured to generate a respective output signal;', 'a frequency divider configured to generate a respective feedback signal by dividing the respective output signal;', 'a phase comparator arrangement configured to output a respective control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal;, 'a plurality N of PLLs, wherein each PLL comprises an i-th phase detector is configured to receive an i-th feedback signal generated from the i-th PLL and an (i+1)-th feedback signal generated from the (i+1)-th PLL, wherein i=1, 2, 3, . . . N−1;', 'the N-th phase detector is configured to receive the first feedback signal generated from the first PLL and the N-th feedback signal generated from the ...

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Номер записи: 44
23-04-2020 дата публикации

PHASE LOCK LOOP REFERENCE LOSS DETECTION

Номер: US20200127667A1
Автор: Das Venkatseema, Fu Wei, Ghotgalkar Shailesh Ganapat
Принадлежит:

In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator. 1. Apparatus , comprising:a first clock generator arranged to generate an output clock signal in response to an input reference signal and in response to a feedback signal generated in response to the output clock signal;a code generator arranged to generate a code in response to the input reference signal; anda loss detector arranged to generate an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.2. The apparatus of claim 1 , wherein the code generator is arranged to generate a pseudo-random number code.3. The apparatus of claim 1 , wherein claim 1 , in response to the feedback signal claim 1 , the loss detector is arranged to store the code as a new value in a first-stage register and to store a previous value of the first-stage register as a new value in a second-stage register.4. The apparatus of claim 3 , wherein the loss detector is arranged to generate the indication of a loss of the input reference signal in response to the stored values of the first- and second-stage registers.5. The apparatus of claim 1 , wherein claim 1 , in response to the feedback signal claim 1 , the loss detector is arranged to store the code as a new value in a first-stage register claim 1 , to store a previous value of the first-stage register as a new value in a second-stage register claim 1 , and to transfer a previous value of the second-stage register as a new value to a third-stage register.6. The apparatus of claim 5 , wherein the ...

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Номер записи: 45
18-05-2017 дата публикации

POWER TRANSMISSION NETWORK

Номер: US20170141574A1
Автор: Jasim Omar Fadhel
Принадлежит:

A power transmission network is disclosed, which includes an AC electrical network connected to a point of common coupling, the point of common coupling being connectable to a further electrical device; and a processing circuit configured to receive and process a voltage of the point of common coupling to determine a phase difference between the voltages of the AC electrical network and the point of common coupling during an exchange of power between the AC electrical network and the point of common coupling. 1. A power transmission network comprising:an AC electrical network connected to a point of common coupling, the point of common coupling being connectable to a further electrical device; anda processing circuit configured to receive and process a voltage of the point of common coupling to determine a phase difference between the voltages of the AC electrical network and the point of common coupling during an exchange of power between the AC electrical network and the point of common coupling.2. A power transmission network according to claim wherein the voltages of the AC electrical network and the point of common coupling are in-phase prior to the exchange of power between the AC electrical network and the point of common coupling.3. A power transmission network according to claim 1 , wherein the point of common coupling is connected to a converter.4. A power transmission network according to claim 3 , wherein the processing circuit is configured to process the phase difference in combination with the voltage and current of the point of common coupling to determine a network impedance of the AC electrical network claim 3 , to process the network impedance to define the operating requirements of the converter claim 3 , and to operate the converter in accordance with the defined operating requirements.5. A power transmission network according to claim 4 , wherein the processing circuit is configured to process the network impedance to define the real and/or ...

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Номер записи: 46
08-09-2022 дата публикации

Loop Gain Auto Calibration Using Loop Gain Detector

Номер: US20220286141A1
Автор: CHANG Chih-Hsien, Chang Ya-Tin, CHOU Mao-Hsuan, Sheen Ruey-Bin
Принадлежит:

A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit. 1. A device comprising:a first phase detector circuit configured to detect a clock skew between a reference signal and an input signal;a charge pump circuit configured to translate the clock skew into a voltage; anda comparator configured to detect a loop gain associated with the input signal based on the voltage and output a loop gain signal for adjustment of the input signal.2. The device of claim 1 , further comprising:a sample and hold circuit configured to sample the voltage and maintain the sampled voltage, wherein the comparator is further configured to detect the loop gain based on the sampled voltage; anda controller coupled to the first phase detector, the comparator, and the sample and hold circuit, the controller configured to generate a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit, wherein the reference signal comprises a plurality of cycles and the plurality of control signals comprise:a sample and hold circuit control signal configured to operate the sample and hold circuit during a first cycle ...

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Номер записи: 47
01-06-2017 дата публикации

LOCAL PHASE DETECTION IN REALIGNED OSCILLATOR

Номер: US20170155395A1
Автор: GROLLITSCH Werner, Vitrenko Oleg
Принадлежит:

Representative implementations of devices and techniques provide reduced jitter and local phase detection for a controlled oscillator. An edge of a reference signal is injected at a point within the oscillator, and replaces an edge of the generated oscillation signal at the injection point. A phase difference of the injected reference signal and the oscillation signal is measured locally and is used to tune the oscillator. 1. A ring oscillator circuit , comprising:a plurality of inverters coupled in series;a multiplexer coupled to an output of an inverter of the plurality of inverters at a first input of the multiplexer and coupled to an input of another inverter of the plurality of inverters at an output of the multiplexer, the multiplexer arranged to receive a reference signal at a second input of the multiplexer and to output the reference signal when an enable signal received at the multiplexer is in a first state and to output an oscillation signal received at the first input of the multiplexer when the enable signal is in a second state; anda phase detector coupled to the first input of the multiplexer at a first input of the phase detector and coupled to the second input of the multiplexer at a second input of the phase detector.2. The ring oscillator circuit of claim 1 , further comprising a charge pump and/or an analog or digital loop filter coupled to an output of the phase detector and arranged to tune a frequency of the oscillation signal based on the output of the phase detector by controlling the delay of the inverter stages.3. The ring oscillator circuit of claim 2 , wherein the phase detector is arranged to output an error signal to the charge pump and/or the loop filter claim 2 , the charge pump and/or the loop filter increasing or decreasing a frequency of the oscillation signal based on the error signal.4. The ring oscillator circuit of claim 1 , wherein the phase detector is arranged to measure a phase difference or a frequency difference between ...

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Номер записи: 48
11-06-2015 дата публикации

CIRCUIT AND OPERATING METHOD OF PLL

Номер: US20150162921A1
Автор: CHEN Yen-Jen, HSIEH Hsieh-Hung, HSUEH Fu-Lung, JOU Chewn-PU
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time. 1. A phase locked loop (PLL) , comprising:{'sub': 'VCO', 'a voltage controlled oscillator (VCO) configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal, the second oscillating signal being an inverted version of the first oscillating signal, the first and second oscillating signals having a predetermined VCO period (T);'}a loop filter configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter; and [{'sub': CP1', 'REF', 'REF', 'VCO, 'apply a first predetermined amount of current (I), along a first current direction, to the first feedback control output node during a variable period of time, the variable period of time being defined by a reference signal, the first oscillating signal, and the second oscillating signal, the reference signal having a predetermined reference period (T), a predetermined ratio of Tto Tbeing (N+f), N being a positive integer, and f being a fraction; and'}, {'sub': 'CP2', 'apply one of K second predetermined amounts of current (I[0:K−1]), along a second current ...

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Номер записи: 49
17-06-2021 дата публикации

SYNCHRONIZATION OF CLOCK SIGNALS GENERATED USING OUTPUT DIVIDERS

Номер: US20210184687A1
Автор: Anker William, Barnette James D., Gong Xue-Mei
Принадлежит:

A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop. 1. A method for operating a clock product comprising:selectively coupling a first output divider responsive to a first divider value and a second output divider responsive to a second divider value based on a determination of whether the first divider value is integrally related to the second divider value,wherein in response to the first divider value being integrally related to the second divider value, the selectively coupling comprises cascading the first output divider with the second output divider, andwherein in response to the first divider value being non-integrally related to the second divider value, the selectively coupling comprises configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.2. The method claim 1 , as recited in claim 1 , wherein the first ...

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Номер записи: 50
23-05-2019 дата публикации

SUB-SAMPLING PHASE-LOCKED LOOP

Номер: US20190158101A1
Автор: Jakobsson Anders
Принадлежит:

A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLY at a first point t in time and a second delay signal SDLY at a second point in time t. The sampler module is configured to provide a first sample S of the oscillator output signal SOUT at the first point in time t and a second sample S of the oscillator output signal SOUT at the second point in time t. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample S and the second sample S. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL. 1. A sub-sampling phase-locked loop comprising:a digital-to-time converter (DTC),a sampler module,an interpolator, andan oscillator which is voltage controlled;wherein the digital-to-time converter is configured to provide a first delay signal and a second delay signal to the sampler module,wherein the sampler module is configured to provide a first sample of an oscillator output signal based on the first delay signal and a second sample of the oscillator output signal based on the second delay signal;wherein the interpolator is configured to provide a sampler signal by interpolating the first sample and the second sample; andwherein the oscillator is configured to control the oscillator output signal based on the sampler signal, and provide the oscillator output signal to the sampler module.2. The sub-sampling phase-locked loop according to claim 1 , wherein the digital-to-time converter further is configured to:receive a reference signal and a control signal, the control signal defining a factor between a desired frequency of the oscillator output signal and a frequency of the reference signal;produce a converter signal defining possible points in time for sampling; ...

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Номер записи: 51
23-05-2019 дата публикации

HYBRID PHASE LOCK LOOP

Номер: US20190158102A1
Автор: CHANG Chih-Hsien, Hsieh Cheng-Hsiang, Sheen Ruey-Bin, TSAI Tsung-Hsien
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL. 1. A phase lock loop (PLL) , comprising:a first loop configured to provide a digital output signal based upon on a comparison of a reference input signal and an output signal of the PLL in a first operational mode of the PLL;a second loop configured to provide an analog output signal based on a comparison of the reference input signal and a feedback signal that is proportional to the output signal of the PLL in a second operational mode of the PLL; andan oscillator, coupled to the first loop and the second loop, configured to tune a frequency of the output signal of the PLL in accordance with the digital output signal in the first operational mode of the PLL and to tune an output phase of the output signal of the PLL in accordance with the analog output signal in the second operational mode of the PLL,wherein the first loop comprises an oscillator controller configured to disable the second loop in the first operational mode of the PLL.2. The PLL of claim 1 , wherein the first loop further comprises:a frequency detector configured to compare the reference input signal and ...

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Номер записи: 52
18-06-2015 дата публикации

PHASE LOCKED LOOP (PLL) APPARATUS AND OPERATING METHOD OF PLL APPARATUS

Номер: US20150171874A1
Автор: RYU Joon Gyu
Принадлежит:

Provided are a phase locked loop (PLL) apparatus and an operating method of the PLL apparatus including a PLL unit to provide a fixed frequency signal, a converter to convert, using the fixed frequency signal, a frequency of a first signal oscillated by a first voltage-controlled oscillator (VCO) based on a first control voltage, a first frequency divider to divide the converted frequency of the first signal, and a first phase comparator to compare the divided frequency of the first signal to an input first reference frequency and detect a first phase difference, wherein the first VCO may adjust the first control voltage based on the detected first phase difference to equalize the divided frequency of the first signal to the first reference frequency. 1. A phase locked loop (PLL) apparatus comprising:a PLL unit to provide a fixed frequency signal;a converter to convert, using the fixed frequency signal, a frequency of a first signal oscillated by a first voltage-controlled oscillator (VCO) based on a first control voltage;a first frequency divider to divide the converted frequency of the first signal; anda first phase comparator to compare the divided frequency of the first signal to an input first reference frequency and detect a first phase difference,wherein the first VCO adjusts the first control voltage based on the detected first phase difference to equalize the divided frequency of the first signal to the first reference frequency.2. The apparatus of claim 1 , wherein the PLL unit comprises:a second frequency divider to divide a frequency of a second signal oscillated by a second VCO based on a second control voltage; anda second phase comparator to compare the divided frequency of the second signal to an input second reference frequency and detect a second phase difference, andthe second VCO adjusts the second control voltage based on the detected second phase difference to equalize the divided frequency of the second signal to the second reference frequency ...

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Номер записи: 53
15-06-2017 дата публикации

Radio communication device and radio communication method

Номер: US20170170837A1
Автор: Akihide Sai, Hidenori Okuni, Masanori Furuta
Принадлежит: Toshiba Corp

A radio communication device has an analog control loop unit to generate an analog control signal that adjusts a phase of a voltage control oscillation signal, a digital control loop unit to generate a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and a phase opposite to a phase of the analog control signal, a voltage controlled oscillator to generate the voltage control oscillation signal, a data slicer to generate a digital signal including the reception signal, an automatic offset controller to generate a correction signal in response to an error between a frequency of the reception signal and a frequency of the voltage control oscillation signal, and a setting code adjuster to adjust the frequency setting code signal, wherein gain of the digital control loop unit is higher than gain of the analog control loop unit.

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Номер записи: 54
30-05-2019 дата публикации

FULL RANGE REALIGNMENT RING OSCILLATOR

Номер: US20190165769A1
Автор: CHANG Chih-Hsien, Hsieh Chen-Hsiang, Sheen Ruey-Bin, TSAI Tsung-Hsien
Принадлежит:

A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate. A drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate. 1. A realignment ring-cell circuit , comprising:a single-to-differential unit having an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output;an OR gate, wherein the first output for outputting is a first input to the OR gate;an AND gate, wherein the second output for outputting is a first input to the AND gate;a first P-type metal-oxide-semiconductor transistor, wherein a gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate; anda first N-type metal-oxide-semiconductor transistor, wherein a gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate, wherein a drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are ...

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Номер записи: 55
30-05-2019 дата публикации

SYNTHESIZER AND PHASE FREQUENCY DETECTOR

Номер: US20190165794A1
Автор: Krempig Mathias, Ott Arndt Thomas
Принадлежит: SONY CORPORATION

A synthesizer comprises a two-point modulation phase locked tow, TPM PLL, circuit configured to receive a frequency tuning signal and to generate a stepped chirp signal in an intermediate frequency range by applying a two-point modulation PLL on the frequency tuning signal, and a subsampling PLL circuit configured to receive the stepped chirp signal in a mm-wave frequency range and to generate a smoothened chirp signal in a mm-wave frequency range by applying a subsampling PLL on the stepped chirp signal. 1. A synthesizer comprisinga two-point modulation phase locked loop, TPM PLL, circuit configured to receive a frequency tuning signal and to generate a stepped chirp signal in an intermediate frequency range by applying a two-point modulation PLL on the frequency tuning signal, anda subsamplinq PLL circuit configured to receive the stepped chirp signal in a mm-wave frequency range and to generate a smoothened chirp signal in a mm-wave frequency range by applying a subsampling PLL on the stepped chirp signal.2. The synthesizer as claimed in claim 1 , a first phase detector circuit configured to receive the frequency tuning signal and the stepped chirp signal and to generate a first phase detection signal,', 'a first frequency divider configured to apply a frequency division on the stepped chirp signal, and', 'a first phase-frequency detector and charge pump circuit configured to receive the frequency tuning signal and the stepped chirp signal after application of the frequency-division and to generate a second phase detection signal., 'wherein the TPM PLL circuit comprises'}3. The synthesizer as claimed in claim 2 , a first loop fitter configured to receive the first phase detection signal and the second phase detection signal or to receive a first combined phase detection signal resulting from a combination of the first phase detection signal and the second phase detection signal and generate a first oscillator tuning signal and', 'a first oscillator configured to ...

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Номер записи: 56
21-05-2020 дата публикации

SYSTEM OF REFERENCELESS CLOCK AND DATA RECOVERY AND FREQUENCY DETECTOR THEREOF

Номер: US20200162080A1
Автор: CHEN Wei-Zen
Принадлежит:

A system of referenceless clock and data recovery and a frequency detector thereof has been provided. The output clock of the system initially works at the lowest frequency, the frequency of the output clock is monotonically increased in accordance with the control of the frequency detector, thereby gradually approximating a target value. The edge extraction circuit receives the data signal and the clock signal, identifies the transition edges of the signals and generates a data transition signal and a clock transition signal representing the transition edges of the data signal and the transition edges of the clock signal respectively. The edge detector then determines the data period of the data signal and the clock period of the clock signal. When the data period is smaller than half of the clock period, the edge detector generates a frequency-up signal and the frequency of the output clock is increased. 1. A frequency detector suitable for a clock and data recovery system to monotonically increase a frequency of a clock signal outputted by the clock and data recovery system , the frequency detector comprising:an extraction circuit receiving a data signal and the clock signal, and distinguishing a plurality of data transition edges of the data signal and a plurality of clock transition edges of the clock signal, and respectively generating a data transition signal representing the plurality of data transition edges and a clock transition signal representing the plurality of clock transition edges; anda determination circuit connected to the extraction circuit, and receiving the data transition signal and the clock transition signal, the determination circuit respectively determining a data signal period of the data signal and a clock signal period of the clock signal based on the data transition signal and the clock transition signal;wherein when the data signal period is lower than a half of the clock signal period, the determination circuit generates a frequency ...

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Номер записи: 57
18-09-2014 дата публикации

SIGNAL GENERATING CIRCUIT AND METHOD THEREOF

Номер: US20140266350A1
Автор: Cheng Ching-Sheng, TSAI Chao-Yang
Принадлежит: Realtek Semiconductor Corp.

A signal generating circuit comprises a signal synchronizing module and a control circuit. The signal synchronizing module includes: a first delay path for delaying a target signal to generate a first delayed target signal by utilizing a first delay amount; a second delay path for delaying the target signal to generate a second delayed target signal by utilizing a second delay amount larger than the first delay amount; and a logic module, for gating the target signal to generate a first output signal according to the first delayed target signal, or gating the target signal to generate a second output signal according to the second delayed target signal. The control circuit controls the signal synchronizing module to output one of the first output signal and the second output signal according to phase difference between the target signal and a reference signal. 1. A signal generating circuit , comprising: a first delay path, for utilizing a first delay amount to delay an input signal to generate a first delayed input signal;', 'a second delay path, for utilizing a second delay amount to delay the input signal to generate a second delayed input signal, wherein the first delay amount is smaller than the second delay amount; and', 'a logic module, receiving one of the first delayed input signal and the second delayed input signal, wherein the logic module gates at least part of a target signal to generate a first output signal according to the first delayed input signal while receiving the first delayed input signal, where the logic module gates at least part of the target signal to generate a second output signal according to the second delayed input signal while receiving the second delayed input signal; and, 'a signal phase synchronizing module, comprisinga control circuit, for controlling the signal generating circuit to output one of the first output signal and the second output signal according to a phase difference between the target signal and a reference signal ...

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Номер записи: 58
22-06-2017 дата публикации

PHASE FREQUENCY DETECTOR

Номер: US20170179962A1
Автор: Jia Wenyan Vivian, LI SHENGGAO, Spagna Fulvio
Принадлежит:

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference. 1. An apparatus comprising:a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; anda second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.2. The apparatus of further comprises an adder to sum the first and second outputs to generate a resultant phase difference between the first clock signal and the second clock signal.3. The apparatus claim 1 , wherein the first PFD to provide a substantially linear characteristic over a wide phase difference of the first clock signal and the second clock signal.4. The apparatus of claim 1 , wherein the first and second PFDs operate in parallel.5. The apparatus of claim 1 , wherein the first and second PFDs operate sequentially.6. The apparatus of claim 1 , wherein the first PFD is a time-to-digital converter (TDC).7. The apparatus of claim 1 , wherein the second PFD is a bang-bang PFD (BBPFD).8. The apparatus of claim 7 , wherein the BBPFD comprises a first stage to detect edges of the first and second clock signals claim 7 , the first stage to generate a phase difference between the first and second clock signals.9. The apparatus of claim 8 , wherein the BBPFD comprises a second stage claim 8 , coupled to the first stage claim 8 , to sense a fine ...

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Номер записи: 59
02-07-2015 дата публикации

CLOCK RECOVERY USING QUANTIZED PHASE ERROR SAMPLES USING JITTER FREQUENCY-DEPENDENT QUANTIZATION THRESHOLDS AND LOOP GAINS

Номер: US20150188551A1
Автор: Aziz Pervez M., Kotagiri Shiva Prasad, Malipatil Amaresh V., Srinivasa Sunil, Venkatraman Sundeep
Принадлежит: LSI Corporation

A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples. 1. A clock and data recovery device comprising:a phase detector coupled to an input node for producing phase error samples at an output;a quantizer, coupled to the output of the phase detector and responsive to a high threshold value and a low threshold value different from the high threshold value, for producing tri-valued quantized phase error samples at an output; anda loop filter coupled to the output of the quantizer.2. The clock and data recovery device of wherein the quantizer is configured to produce as the quantized phase error samples 1) a first one of the tri-valued phase error values when a phase error sample has a value that is greater than the high threshold value claim 1 , 2) a second one of the tri-valued phase error values when a phase error sample has a value that is less than the low threshold value claim 1 , and 3) a third one of the tri-valued phase error values when a phase error sample has a value that is between the high and low threshold values.3. The dock and data recovery device of wherein the loop ...

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Номер записи: 60
28-06-2018 дата публикации

Lock detector for phase lock loop

Номер: US20180183566A1
Автор: Armin TAJALLI
Принадлежит: Kandou Labs SA

Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.

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Номер записи: 61
04-06-2020 дата публикации

Systems and Methods for Mitigation of Nonlinearity Related Phase Noise Degradations

Номер: US20200177190A1
Автор: Horovitz Gil, Shumaker Evgeny
Принадлежит:

A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency. 1. A phase locked loop (PLL) system for mitigating non-linear phase errors , the system comprising:a modulation circuit configured to generate a plurality of phase shifts, select a phase shift based on the plurality of phase shifts and introduce the selected phase shift into one of a reference signal and a feedback signal to generate a phase shifted signal, the phase shifted signal having a relative phase shift between the reference signal and the feedback signal; anda time to digital converter (TDC) configured to generate a phase detection signal based on the phase shifted signal.2. The system of claim 1 , wherein the modulation circuit is configured to generate a compensation signal based on the introduced selected phase shift.3. The system of claim 2 , further comprising circuitry configured to combine the compensation signal with the phase detection signal.4. The system of claim 1 , wherein the plurality of phase shifts include fractional phase ...

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Номер записи: 62
05-07-2018 дата публикации

BAND SELECTED CLOCK DATA RECOVERY CIRCUIT AND ASSOCIATED METHOD

Номер: US20180191358A1
Автор: HSU Chuan-Chien, Wang Jing-Yuan
Принадлежит:

A clock data recovery (CDR) circuit includes: a band select circuit, a low dropout regulator (LDO), a charge pump and a voltage-controlled oscillator (VCO), wherein the band select circuit is arranged to generate a digital signal according to at least a reference voltage; the LDO is arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; the charge pump is arranged to generate a control voltage according to at least a part of the digital signal; and the VCO is arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO. 1. A clock data recovery (CDR) circuit , comprising:a band select circuit, arranged to generate a digital signal according to at least a reference voltage;a low dropout regulator (LDO), arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO;a charge pump, arranged to generate a control voltage according to at least a part of the digital signal; anda voltage-controlled oscillator (VCO), arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.2. The CDR circuit of claim 1 , wherein the LDO comprises:a bias control circuit, arranged to receive at least a part of the digital signal to control the bias current passing through the amplifier of the LDO.3. The CDR circuit of claim 1 , wherein the LDO receives a regulating ground voltage generated by the VCO to regulate the ground voltage.4. The CDR circuit of claim 1 , wherein the VCO comprises:a current generating ...

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Номер записи: 63
11-06-2020 дата публикации

SIGNAL SOURCE

Номер: US20200186153A1
Автор: Mizutani Hiroyuki, Tajima Kenichi, WADA Osamu
Принадлежит: Mitsubishi Electric Corporation

Conventional signal sources each have a disadvantage that the noise in a control voltage of a VCO increases, thereby deteriorating the phase noise of an output signal of the signal source. 1. A signal source comprising:a reference signal source to output a reference signal;a phase frequency comparator to detect a phase difference between the reference signal and an oscillation signal and output a signal corresponding to the phase difference;a filter to smooth the signal output by the phase frequency comparator;an oscillator to output the oscillation signal depending on the signal smoothed by the filter;an S/H circuit to receive a clock signal for controlling a phase of the oscillation signal by controlling sampling operation and holding operation, sample at least one of the oscillation signal and the reference signal in synchronization with the clock signal, and output at least one of the sampled reference signal and the sampled oscillation signal to the phase frequency comparator, the S/H circuit disposed between the oscillator and the phase frequency comparator or between the reference signal source and the phase frequency comparator; anda clock signal generating circuit to control the clock signal so as to vary a frequency of the clock signal without varying the phase of the clock signal when the phase of the oscillation signal output from the oscillator is varied.2. The signal source according to claim 1 , wherein a frequency of the output signal of the S/H circuit is in a first Nyquist zone.3. A signal source comprising:a reference signal source to output a reference signal;a phase frequency comparator to detect a phase difference between the reference signal and an oscillation signal and output a signal corresponding to the phase difference;a filter to smooth the signal output by the phase frequency comparator;an oscillator to output the oscillation signal depending on the signal smoothed by the filter;an S/H circuit to receive a clock signal for controlling a ...

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Номер записи: 64
11-06-2020 дата публикации

FREQUENCY SYNTHESIZER WITH DYNAMICALLY SELECTED LEVEL SHIFTING OF THE OSCILLATING OUTPUT SIGNAL

Номер: US20200186155A1
Автор: GUPTA Nitin
Принадлежит: STMICROELECTRONICS INTERNATIONAL N.V.

An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage. 1. A circuit , comprising:an oscillator circuit powered at a source voltage and configured to generate an oscillating output signal with an amplitude at a level of the source voltage;a first level shifter circuit powered by a first power supply voltage and configured to level shift the oscillating output signal to generate a level shifted oscillating output signal;a first multiplexer circuit having a first input configured to receive the oscillating output signal and a second input configured to receive the level shifted oscillating output signal, wherein the first multiplexer circuit selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal;a locked loop circuit configured to control a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal; anda first voltage regulator circuit configured to generate the first power supply voltage using the source voltage as an error amplifier reference voltage.2. The circuit of claim 1 , wherein the locked loop circuit comprises: ...

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Номер записи: 65
27-06-2019 дата публикации

INTEGRATED PROCESSOR AND CDR CIRCUIT

Номер: US20190199507A1
Автор: MIAO Jason Y.
Принадлежит:

A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate. 1. A system , comprising:a clock and data recovery circuit; andprocessing circuitry configured to control the clock and data recovery circuit based on previously stored data that includes a data rate of a previously received data signal from the clock and data recovery circuit, the processing circuitry controlling the clock and data recovery circuit by directing the clock and data recovery circuit to begin at the data rate of the previously received data signal when locking to a data signal.2. The system of claim 1 , wherein the clock and data recovery circuit is an analog circuit and the processing circuitry is a digital circuit claim 1 , wherein transistors in the clock and data recovery circuit and the processing circuitry are formed on a single substrate.3. The system of claim 1 , wherein the clock and data recovery circuit includes an oscillator claim 1 , wherein the processing circuitry directs the oscillator to being at the data rate of the previously received data signal when locking to the data signal.4. The system of claim 1 , wherein the clock and data recovery circuit includes a charge pump claim 1 , wherein the processing circuitry is configured to set rail voltages of the charge pump at a first set of voltages when the clock and data recovery circuit locks to the data signal and to set the rail voltages of the charge pump at a second set of voltages after the clock and data recovery circuit locks to the data signal claim 1 , wherein a first difference between voltages of the first set of voltages is smaller than a second difference between voltages of the second set of voltages.5. The system of claim 4 , wherein the processing circuitry is further ...

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Номер записи: 66
06-08-2015 дата публикации

Apparatus and Methods for Phase-Locked Loop Startup Operation

Номер: US20150222275A1
Автор: Janbu Øyvind, Reichelt Pål Øyvind
Принадлежит: SILICON LABORATORIES, INC.

A phase-locked loop (PLL) is provided. The PLL may include a local oscillator configured to generate an output signal, a feedback divider configured to generate a feedback signal in response to the output signal, a phase detector configured to operate the local oscillator based on a comparison between a reference signal and the feedback signal, and a reset controller in communication with each of the phase detector and the feedback divider. The reset controller may be configured to hold each of the phase detector and the frequency divider in reset, and enable each of the phase detector and the frequency divider such that at least the feedback signal is in substantial synchronization with the reference signal. 1. A method of operating a phase-locked loop (PLL) upon startup , the PLL having at least a phase detector and a frequency divider , the method comprising:receiving a clock reference signal having a significant edge;maintaining each of the phase detector and the frequency divider of the PLL in a disabled state; andenabling each of the phase detector and the frequency divider such that at least the frequency divider is in substantial synchronization with the significant edge of the clock reference signal.2. The method of claim 1 , wherein each of the phase detector and the frequency divider is enabled such that a significant edge of a resulting feedback signal is substantially synchronized with a next significant edge of the clock reference signal.3. The method of claim 1 , wherein each of the phase detector and the frequency divider is maintained in reset in response to a non-synchronized reset signal.4. The method of claim 1 , wherein enabling the frequency divider generates a feedback signal having a frequency proportional to an output frequency of a local oscillator of the PLL claim 1 , and wherein enabling the phase detector causes the phase detector to determine a phase difference between the clock reference signal and the feedback signal and to adjust the ...

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Номер записи: 67
06-08-2015 дата публикации

DOUBLE PHASE-LOCKED LOOP WITH FREQUENCY STABILIZATION

Номер: US20150222276A1
Автор: Milijevic Slobodan
Принадлежит:

A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks. 1. A double phase-locked loop , comprising a first narrowband phase-locked loop including a first loop filter configured to reduce phase noise in a first input clock; a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source , said second clock having a frequency close to said first clock; said first phase-locked loop having a bandwidth at least an order of magnitude less than said second phase-locked loop; and a coupler configured to couple said first and second phase-locked loops to provide a common output whereby said second phase locked loop stabilizes said first phase locked loop.2. A double phase-locked loop as claimed in claim 1 , wherein said first phase locked loop is embedded in said second phase-locked loop claim 1 , said first and second phase locked loops sharing a common controlled oscillator driven by a local oscillator.3. A double phase-locked loop as claimed in claim 2 , wherein said combiner comprises an adder in said second phase-locked loop configured to add an output of said first loop filter to an output of a phase detector forming part of said second phase locked loop upstream of said second loop filter.4. A double phase-locked loop as claimed in claim 1 ...

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Номер записи: 68
27-07-2017 дата публикации

OSCILLATOR, RADIO COMMUNICATION DEVICE, AND RADIO COMMUNICATION METHOD

Номер: US20170214409A1
Автор: Furuta Masanori, Kondo Satoshi, SAI Akihide
Принадлежит: KABUSHIKI KAISHA TOSHIBA

An oscillator has an oscillator which comprises a first variable capacitor to adjust capacitance based on a first signal and a second variable capacitor to adjust capacitance, generates an oscillation signal having a frequency in accordance with the capacitance of the first variable capacitor and the second variable capacitor, an integer phase detector to detect an integer phase of the oscillation signal, a fractional phase detector to detect a fractional phase of the oscillation signal, a phase error generator to generate a fourth signal indicating a phase error of the oscillation signal, a first filter to extract the first signal in a predetermined frequency band, included in the fourth signal, and to output the first signal, and a second filter to extract the second signal in a predetermined frequency band, included in the fourth signal, and to output the second signal. 1. An oscillator comprising:an oscillator which comprises a first variable capacitor to adjust capacitance based on a first signal and a second variable capacitor to adjust capacitance based on a second signal, generates an oscillation signal having a frequency in accordance with the capacitance of the first variable capacitor and the second variable capacitor;an integer phase detector to detect an integer phase of the oscillation signal;{'sub': '[t1]', 'a fractional phase detector to detect a fractional phase of the oscillation signal based on a third signal as a reference and the oscillation signal;'}a phase error generator to generate a fourth signal indicating a phase error of the oscillation signal, based on the integer phase, the fractional phase, and a frequency control signal;a first filter to extract the first signal in a predetermined frequency band, included in the fourth signal, and to output the first signal in asynchronization with the third signal; anda second filter to extract the second signal in a predetermined frequency band, included in the fourth signal, and to output the ...

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Номер записи: 69
02-07-2020 дата публикации

DATA RECEPTION DEVICE AND DATA TRANSMISSION/RECEPTION DEVICE

Номер: US20200213076A1
Автор: Kikuchi Hidekazu, Morohashi Hideo, TANAKA Tomokazu
Принадлежит:

A data reception device that can improve communication quality when transmitting/receiving serial data is to be provided. There is provided the data reception device including: a signal generation unit that generates, from serial data received, a first signal whose value is inverted at a rising timing of the serial data and a second signal whose value is inverted at a falling timing of the serial data; and a clock recovery unit that performs clock recovery using the first signal and the second signal generated by the signal generation unit. 1. A data reception device comprising:a signal generation unit that generates, from serial data received, a first signal whose value is inverted at a rising timing of the serial data and a second signal whose value is inverted at a falling timing of the serial data; anda clock recovery unit that performs clock recovery using the first signal and the second signal generated by the signal generation unit.2. The data reception device according to claim 1 , wherein the clock recovery unit includes phase detection units that individually perform phase detection on corresponding ones of the first signal and the second signal.3. The data reception device according to claim 2 , whereineach of the phase detection units includes a flip-flop circuit that inputs the first signal or the second signal, andthe flip-flop circuit includes a first D latch circuit that inputs the first signal or the second signal and a clock signal, a delay device that delays the clock signal by a predetermined time, and a second D latch circuit that inputs an output of the first D latch circuit and an output of the delay device.4. The data reception device according to claim 3 , wherein each of the phase detection units further includes a reset release circuit that releases reset of the first D latch circuit and the second D latch circuit at a timing when a code of the serial data transitions.5. The data reception device according to claim 2 , further comprising a ...

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Номер записи: 70
02-07-2020 дата публикации

EFFICIENT FREQUENCY DETECTORS FOR CLOCK AND DATA RECOVERY CIRCUITS

Номер: US20200213078A1
Автор: Abramzon Valentin
Принадлежит:

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low. 1. A phase/frequency detector circuit comprising:a first slicer configured to sample a data input according to a first clock and output an odd data sample (Dodd);a second slicer configured to sample the data input according to a second clock and output an odd crossing sample (Xodd);a third slicer configured to sample the data input according to a third clock and output an even data sample (Deven);a fourth slicer configured to sample the data input according to a fourth clock and output an even crossing sample (Xeven);a first data alignment circuit configured to temporally align the Dodd, Xodd, and Deven;a second data alignment circuit configured to temporally align the Deven, Xeven, and Dodd; and generate a first edge output according to Dodd and Xodd;', 'generate a second edge output according to Xodd and Deven;', 'generate a third edge output according to Deven and Xeven;', 'generate a fourth edge output according to Xeven and Dodd;', 'generate an UP odd signal when the first edge output and the second edge output are both high;', 'generate a DOWN odd signal when the first edge output and the second edge output are both low;', 'generate a UP even signal when the third edge output and the fourth edge output are both high; and', 'generate a DOWN even signal when the third edge output and the fourth edge output are both low., 'a combinational logic circuit configured to2. ...

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Номер записи: 71
13-11-2014 дата публикации

PHASE-ROTATING PHASE LOCKED LOOP AND METHOD OF CONTROLLING OPERATION THEREOF

Номер: US20140333346A1
Автор: Bae Junhan, CHUN Jung Hoon, KIM Kyoungho, KIM Seok, KWON KEE-WON, Sohn Youngsoo
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code. 1. A phase locked loop (PLL) comprising:first and second loops sharing a loop filter and a voltage controlled oscillator (VCO) so as to perform the operation of a phase-rotating PLL in response to an enable signal; anda phase frequency detection controller (PFDC) configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal.2. The phase locked loop of claim 1 , wherein the first loop comprises:a first phase frequency detector configured to compare a phase of a reference clock signal with a phase of a first input clock signal to generate a first up signal or a first down signal if the enable signal is in a first logic state; anda first charge pump configured to generate a first charge pumping current in response to the first up signal or the first down signal.3. The phase locked loop of claim 2 , wherein the first charge pump is a weighted charge pump.4. The phase locked loop of claim 2 , wherein the second loop comprises:a second phase frequency detector configured to compare the phase of the reference clock signal with a phase of a second input clock signal to generate a second up signal or a second down signal if the enable signal is in the first logic state; anda second charge pump configured to generate a second charge pumping current in response to the second up signal or the second down signal.5. The phase locked loop of claim 4 , wherein the first charge pump is a weighted charge pump.6. The phase locked loop of ...

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Номер записи: 72
23-08-2018 дата публикации

MULTI-PHASE CLOCK GENERATION EMPLOYING PHASE ERROR DETECTION IN A CONTROLLED DELAY LINE

Номер: US20180241403A1
Автор: Sun Bo
Принадлежит:

Multi-phase clock generation employing phase error detection between multiple delay circuit outputs in a controlled delay line to provide error correction is disclosed. A multi-phase clock generator is provided that includes a controlled delay line and a phase error detector circuit. Tap nodes are provided from outputs of one or more delay circuits in the controlled delay line. To detect and correct for phase errors in the controlled delay line, a phase detection circuit is provided that includes at least two phase detectors each configured to measure a phase offset error between tap nodes from the delay circuit(s) in the controlled delay line. These phase errors are then combined to create an error correction signal, which is used to control the delay of the delay circuit(s) in the controlled delay line to lock the phase of the output of the final delay circuit to an input reference clock signal. 1. A multi-phase clock generator , comprising:a delay circuit comprising a clock input and two clock signal outputs;at least two phase detectors each comprising a mixer, each mixer comprising at least two phase signal inputs and an error signal output, wherein one of the at least two phase signal inputs is coupled to at least one of the two clock signal outputs; anda feedback circuit comprising two inputs coupled to the error signal output of the at least two phase detectors and a delay control signal output configured to output a delay control signal based on a combination of signals received at the two inputs.2. The multi-phase clock generator of claim 1 , wherein the feedback circuit comprises a summing circuit and the delay control signal based on the combination of the signals is based on an output of the summing circuit.3. (canceled)4. The multi-phase clock generator of claim 2 , wherein the feedback circuit comprises a low pass filter and a charge pump.5. The multi-phase clock generator of claim 2 , wherein the delay circuit comprises a ninety degree phase delay ...

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Номер записи: 73
24-08-2017 дата публикации

SIGNAL RECOVERY CIRCUIT, ELECTRONIC DEVICE, AND SIGNAL RECOVERY METHOD

Номер: US20170244545A1
Автор: TSUNODA Yukito
Принадлежит: FUJITSU LIMITED

A signal recovery circuit includes an oscillator configured to control a frequency of generating first clock, and a feedback circuit configured to control the oscillator in order that input data is synchronized with the first clock in accordance with a phase relation between the input data and the first clock, wherein the feedback circuit includes a controller configured to control the oscillator in accordance with the phase relation between the input data and the first clock, a first phase detector configured to generate a clock phase control signal in accordance with the phase relation between the input data and the first clock, and a state detection circuit configured to detect whether the signal recovery circuit is in a locked state or an unlocked state, based on a magnitude of an amplitude of a first component or a second component of the clock phase control signal. 1. A signal recovery circuit comprising:an oscillator configured to control a frequency of generating first clock; and a controller configured to control the oscillator in accordance with the phase relation between the input data and the first clock;', 'a first phase detector configured to generate a clock phase control signal in accordance with the phase relation between the input data and the first clock; and', 'a state detection circuit configured to detect whether the signal recovery circuit is in a locked state or an unlocked state, based on a magnitude of an amplitude of a first component or a second component of the clock phase control signal, a frequency of the first component being higher than a frequency of the second component., 'a feedback circuit configured to control the oscillator in order that input data is synchronized with the first clock in accordance with a phase relation between the input data and the first clock, wherein the feedback circuit includes2. The signal recovery circuit according to claim 1 , whereinthe oscillator generates a second clock having a frequency the same ...

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Номер записи: 74
31-08-2017 дата публикации

PHASE LOCK LOOP WITH A DIGITAL CHARGE PUMP

Номер: US20170250693A1
Автор: Goyal Jagdish Chand, Janardhanan Jayawardan, Thiagarajan Krishnaswamy
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A phase lock loop (PLL) includes a voltage-controlled oscillator (VCO) and a frequency detector to generate a FAST signal responsive to a frequency of a reference signal being greater than the frequency of a feedback signal derived from the VCO and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal. The PLL also includes a digital charge pump, a loop filter, and a state machine circuit. Responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, the state machine circuit reconfigures the digital charge pump to increase the charging current to the loop filter. Responsive to receipt of multiple consecutive SLOW signals when the loop filter is discharging, the state machine circuit reconfigures the digital charge pump to cause the loop filter's discharge current to increase. Upon detection of a terminal condition, the state machine circuit may disable the digital charge pump and enable operation of an analog charge pump. 1. A phase lock loop (PLL) , comprising:a voltage-controlled oscillator (VCO) configured to generate an output signal;a frequency detector configured to determine whether a frequency of a reference signal is greater or smaller than a frequency of a feedback signal derived from the VCO's output signal and to generate a FAST signal responsive to the frequency of the reference signal being greater than the frequency of the feedback signal and to generate a SLOW signal responsive to the frequency of the reference signal being smaller than the frequency of the feedback signal;a digital charge pump including a plurality of selectable current sources;a loop filter coupled to the digital charge pump and comprising a capacitor; and responsive to receipt of multiple consecutive FAST signals when the digital charge pump is providing a charging current to the loop filter, reconfigure the digital charge ...

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Номер записи: 75
30-07-2020 дата публикации

Clock and data recovery and associated signal processing method

Номер: US20200244272A1
Автор: Chien-Kai Kao, Shih-Che Hung, Tse-Hsien Yeh
Принадлежит: MediaTek Inc

The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

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Номер записи: 76
30-07-2020 дата публикации

Initialization Method for Precision Phase Adder

Номер: US20200244275A1
Автор: Giovanni Marzin, Yiping Feng
Принадлежит: Blue Danube Systems Inc

A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency fo, a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO), the method including: during a first phase, determining a reference voltage which when applied to the VCO causes it to produce a signal having a frequency of nf0; during a second phase, supplying a signal of frequency nfo to a first input of the mixer and a signal of frequency (nfo+Δf) to a second input of the mixer; and determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and during a third phase, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and applying the adjustment signal to the amplifier circuit.

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Номер записи: 77
15-09-2016 дата публикации

DUAL-LOOP PROGRAMMABLE AND DIVIDERLESS CLOCK GENERATOR FOR ULTRA LOW POWER APPLICATIONS

Номер: US20160269035A1
Автор: FAISAL Muhammad, Wentzloff David D.
Принадлежит: THE REGENTS OF THE UNIVERSITY OF MICHIGAN

A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region. 1. A programmable clock generator , comprising:an oscillator circuit configured to receive a control signal and generate an output signal oscillating at a frequency, where the frequency of the output signal is set in accordance with the control signal;a frequency-locked loop circuit configured to receive a desired output frequency and the output signal from oscillator circuit, wherein the frequency-locked loop circuit determines frequency of the output signal and generates an error signal without the use of a frequency divider, where the error signal indicates a difference between the desired output frequency and the determined output frequency;a phase-locked loop circuit configured to receive a reference signal and the output signal from oscillator circuit, wherein the phase-locked loop circuit determines a phase error between the reference signal and the output signal without the use of a frequency divider and generates an error signal from the phase error, where the error signal indicates a difference between the desired output frequency and the determined output frequency;a loop selector circuit configured to receive the error signal from the frequency-locked loop circuit and the error signal from the phase-locked loop circuit, wherein the loop selector circuit selects one of the error signals and ...

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Номер записи: 78
15-08-2019 дата публикации

FREQUENCY DETECTOR, AND CLOCK AND DATA RECOVERY CIRCUIT INCLUDING THE FREQUENCY DETECTOR

Номер: US20190253234A1
Автор: Bai Rui, Chen Xuefeng, Chiang Patrick Yin, He Wenjun, HU Shang, Pan Wenzong, WANG Juncheng, WANG Xin, Wang Zhichun, XIA Tao, Zhang Yuanxi
Принадлежит: PhotonIC Technologies (Shanghai) Co., Ltd.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal. 1. An apparatus comprising:a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal;a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal; anda first delay buffer coupled to at least one of the plurality of sampling circuits, wherein the plurality of sampling circuits is further configured to receive different clock signals, the different clock signals comprising a first clock signal, a second clock signal, and a third clock signal, wherein the frequency of the clock signal is a frequency of one of the different clock signals, and wherein the first delay buffer is configured to provide the second clock signal by delaying the first clock signal by 180 degrees.2. The apparatus of claim 1 , further comprising a second delay buffer coupled to the first delay buffer claim 1 , wherein the second delay buffer is configured to provide the third clock signal by delaying the second clock signal by an amount between zero degree and 180 degrees.3. The apparatus of claim 2 , wherein the plurality of sampling circuits are further configured to provide a plurality of sampled data signals by sampling the non-NRZ data signal according to the different clock signals.4. The apparatus of claim 3 , wherein the plurality of sampling circuits comprises a first sampling circuit claim 3 , a second ...

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Номер записи: 79
11-12-2014 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20140361818A1
Автор: KIM Kwan Dong
Принадлежит:

A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal. 1. A semiconductor apparatus comprising:a data latch clock generator configured to generate a data latch clock signal by delaying a reference clock signal in response to external data and the data latch clock signal;a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.2. The semiconductor apparatus according to claim 1 ,wherein the data latch clock generator controls a delay amount of the reference clock signal such that the external data and the data latch clock signal have a preset phase difference.3. The semiconductor apparatus according to claim 2 ,wherein the preset phase difference is substantially 90 degrees.4. The semiconductor apparatus according to claim 2 ,wherein the data latch clock generator generates a delay code according to a difference between a phase of the data latch clock signal and a phase of the external data, and generates the data latch clock signal by delaying the reference clock signal in response to the delay code.5. The semiconductor apparatus according to claim 4 , 'a first converter configured to generate the phase of the external data as a first code;', 'wherein the data latch clock generator comprisesa second converter configured to generate the phase of the data latch clock signal as a second code;a calculator configured to calculate a difference between the first and second codes and generate the delay code; anda variable delay unit ...

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Номер записи: 80
01-10-2015 дата публикации

DISTRIBUTED PHASE DETECTION FOR CLOCK SYNCHRONIZATION IN MULTI-LAYER 3D STACKS

Номер: US20150280722A1
Автор: Liu Yong, PANG LIANG-TECK, RESTLE PHILLIP J.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution circuit includes, on each of the two or more strata, phase detectors, a logic circuit, and a phase de-skewing element. Each phase detector has a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata. The logic circuit is connected to the respective outputs of the phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information. The phase de-skewing element is for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan. 1. A clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata , the clock distribution circuit comprising: a plurality of phase detectors, each having a respective output for providing phase information relating to a phase difference between two of the global clocks signals on respective different ones of the two or more strata;', 'a logic circuit connected to the respective outputs of the plurality of phase detectors for determining a phase adjustment plan for a given one of the two or more strata upon which the logic circuit is located responsive to the phase information; and', 'a phase de-skewing element for adjusting a clock skew of a same stratum located one of the two of the global clock signals responsive to the phase adjustment plan., 'on each of the two or more strata,'}2. The clock distribution circuit of claim 1 , wherein at least one of the logic circuit and the phase de-skewing element is centrally located on a corresponding one of the two or more strata.3. The clock distribution circuit of claim 1 , further comprising a ...

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Номер записи: 81
22-08-2019 дата публикации

Phase Locked Loop, Phase Locked Loop Arrangement, Transmitter And Receiver And Method For Providing An Oscillator Signal

Номер: US20190260443A1
Автор: Påhlsson Tony, Sjöland Henrik
Принадлежит:

A phase locked loop, for a particularly in a beamforming system comprises a loop filter () to provide a control signal (FC) to a controllable oscillator (); a frequency divider () configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path () configured to receive the first feedback signal (FB) and a second comparator path () configured to receive the second feedback signal (FBD), each of the first and second comparator path () configured to provide a respective current signal (CS CS) to the loop filter () in response to a respective adjustment signal (FA FA) and a phase deviation between a common reference signal (FR) and the respective feedback signal (FB, FBD). 124-. (canceled)25. A phase locked loop for a beamforming system , the phase locked loop comprising:a loop filter configured to provide a control signal to a controllable oscillator, the controllable oscillator configured to provide an oscillator signal in response to the control signal;a frequency divider configured to provide a first feedback signal and a second feedback signal in response to the oscillator signal, the second feedback signal delayed with respect to the first feedback signal;a first comparator path configured to receive the first feedback signal;a second comparator path configured to receive the second feedback signal; andwherein each of the first and second comparator paths are configured to provide a respective current signal to the loop filter in response to a respective phase adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.26. The phase locked loop of claim 25 , wherein each of the first and second comparator paths comprise:a phase comparator configured to output a respective phase control signal in response to the phase deviation; andan ...

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Номер записи: 82
20-09-2018 дата публикации

Precision high frequency phase adders

Номер: US20180269836A1
Автор: Mihai Banu, Yiping Feng
Принадлежит: Blue Danube Systems Inc

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

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Номер записи: 83
08-10-2015 дата публикации

Digital phase locked loop for low jitter applications

Номер: US20150288370A1
Автор: Chung S. HO, David FLYE, Jingdong DENG, Ramana M. MALLADI, Zhenrong Jin
Принадлежит: International Business Machines Corp

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

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Номер записи: 84
29-09-2016 дата публикации

HYBRID PHASE LOCKED LOOP HAVING WIDE LOCKING RANGE

Номер: US20160285467A1
Автор: Reddy Prakash
Принадлежит: Microsemi SoC Corporation

A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator from an output of the phase comparator. A frequency error measuring circuit coupled to the output of the phase comparator produces a frequency error signal. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and provides the combined control signals to the digital controlled oscillator. 1. A digital phased lock loop comprising:a digital controlled oscillator configured to produce an output signal at a frequency;a phase comparator configured to compare the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal;a first loop filter configured to produce a first control signal for the digital controlled oscillator from an output of the phase comparator;a frequency error measuring circuit coupled to the output of the phase comparator and configured to produce a frequency error signal;a second loop filter configured to produce a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit; anda circuit for combining the first and second control signals and providing the combined control signals to the digital controlled oscillator.2. The digital phased lock loop of claim 1 , wherein:the first loop filter comprises a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder configured to receive the respective proportional and integral components at first and second inputs ...

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Номер записи: 85
27-09-2018 дата публикации

DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS

Номер: US20180278258A1
Автор: DENG Jingdong, FLYE David, HO Chung S., JIN Zhenrong, MALLADI Ramana M.
Принадлежит:

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator. 1. A phase locked loop circuit , comprising:a ring oscillator;a digital path which outputs a digital tuning signal to input into the ring oscillator;an analog path which outputs an analog tuning signal to input into the ring oscillator simultaneously with the digital tuning signal; anda feedback path connecting an output of the ring oscillator to the digital path and to the analog path.2. The phase locked loop circuit of claim 1 , wherein the digital tuning signal modifies a frequency of the output of the ring oscillator.3. The phase locked loop circuit of claim 2 , wherein the analog tuning signal modifies the frequency of the output of the ring oscillator simultaneously with the digital tuning signal.4. The phase locked loop circuit of claim 1 , wherein the digital path includes an integral gain device.5. The phase locked loop circuit of claim 1 , wherein the ring oscillator includes a digital control logic claim 1 , a ring oscillator array and varactors.6. The phase locked loop circuit of claim 5 , wherein the digital control logic discretely modifies an oscillation frequency of the ring oscillator based on the digital tuning signal.7. The phase locked loop circuit of claim 6 , wherein ...

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Номер записи: 86
13-10-2016 дата публикации

TEMPERATURE COMPENSATED PLL CALIBRATION

Номер: US20160301415A1
Автор: Fan Yongping, LI Jing, Waldrip Jeffrey W.
Принадлежит:

In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control. 1. (canceled)2. An apparatus comprising:a phase frequency detector (PFD);a charge pump coupled to the PFD;a low pass filter (LPF) coupled to the charge pump;an oscillator;a first switch operable to couple an input of the oscillator with the LPF during a first operation mode;a circuit to provide an output which is a temperature compensated calibrated voltage; anda second switch operable to couple the input of the oscillator with the output of the circuit during a second operation mode.3. The apparatus of claim 2 , wherein the first operation mode is a normal mode claim 2 , wherein the second operation mode is a calibration mode claim 2 , and wherein the second operation mode is to be performed before the first operation mode.4. The apparatus of claim 2 , wherein the circuit comprises:a temperature sensor; anda digital-to-analog converter coupled to the temperature sensor, wherein the DAC is to provide the output of the circuit.5. The apparatus of claim 4 , wherein the digital to analog converter is generate one or more signals indicating a high limit and a low limit for the temperature calibrated voltage.6. The apparatus of comprises:a first comparator to compare an operational control voltage with the high limit; anda second comparator to compare the operational control voltage with the low limit.7. The apparatus of claim 6 , wherein a number of enabled capacitors in the oscillator are reduced if an output of the first comparator indicates that the operational control voltage is higher than the high limit.8. The apparatus of claim 6 , wherein a number of enabled capacitors in the oscillator are increased if an output of the second comparator indicates that the operational control voltage is lower than the low limit.9. The apparatus of comprises a calibration logic to provide a code to ...

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Номер записи: 87
19-09-2019 дата публикации

THREE LOOP PHASE-LOCKED LOOP

Номер: US20190288695A1
Автор: Janardhanan Jayawardan, PAREKH Sinjeet Dhanvantray, SRIDHAR Arvind, Yao Henry
Принадлежит:

A phase-locked loop (PLL) system includes a first PLL coupled to receive a first reference clock. The PLL system also includes a second PLL coupled to receive a second reference clock. The output of the second PLL is coupled to the first PLL, and the second PLL is configured to control the first PLL. The PLL system further includes a third PLL coupled to receive an input reference clock. The output of the third PLL is coupled to the second PLL. The third PLL is configured to control the second PLL. 1. A phase-locked loop (PLL) system , comprising:a first PLL coupled to receive a first reference clock;a second PLL coupled to receive a second reference clock, the output of the second PLL being coupled to the first PLL, and the second PLL configured to control the first PLL; anda third PLL coupled to receive an input reference clock, the output of the third PLL coupled to the second PLL, and the third PLL configured to control the second PLL.2. The phase-locked loop system of claim 1 , wherein the first PLL comprises an analog PLL (APLL).3. The phase-locked loop system of claim 2 , wherein the second PLL comprises a digital PLL (DPLL).4. The phase-locked loop system of claim 2 , wherein the third PLL comprises a digital PLL (DPLL).5. The phase-locked loop system of claim 1 , wherein:the second PLL comprises a digital PLL (DPLL); andthe third PLL comprises a DPLL.6. The phase-locked loop system of claim 1 , wherein:the first PLL comprises an analog PLL;the second PLL comprises a digital PLL (DPLL); andthe third PLL comprises a DPLL.7. The phase-locked loop system of claim 1 , wherein the first PLL includes a first frequency divider claim 1 , and the second PLL is to control a divide ratio of the first frequency divider.8. The phase-locked loop system of claim 7 , wherein the second PLL includes a second frequency divider claim 7 , and the third PLL is to control a divide ratio of the second frequency divider.9. The phase-locked loop system of claim 1 , wherein a ...

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Номер записи: 88
20-10-2016 дата публикации

Circuit for digitizing phase differences, pll circuit and method for the same

Номер: US20160308541A1
Автор: Chih-Min Liu, Chin-Hao Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A phase-locked loop (PLL) circuit is disclosed. The PLL circuit includes a detecting circuit configured to detect a phase difference between a digitally controlled oscillator (DCO) clock signal and a reference clock signal, and generate a difference signal based on the detected phase difference; a digitized difference generator, coupled to the detecting circuit, configured to generate a control code based upon the difference signal; and a DCO configured to generate the DCO output signal responsive to the control code of the digitized difference generator; wherein the detecting circuit, the digitized difference generator and the DCO form a closed loop and reduce the phase difference between the DCO output signal and the reference clock signal. An associated method and a circuit are also disclosed.

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Номер записи: 89
19-10-2017 дата публикации

RADAR TARGET DETECTION SYSTEM FOR AUTONOMOUS VEHICLES WITH ULTRA-LOW PHASE NOISE FREQUENCY SYNTHESIZER

Номер: US20170302282A1
Автор: Josefsberg Yekutiel, Lavian Tal
Принадлежит:

An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method or autonomous vehicle is also disclosed. 1. An object detection system for autonomous vehicles , comprising: a transmitter for transmitting at least one radio signal to the one or more objects; and', 'a receiver for receiving the at least one radio signal returned from the one or more objects; and, 'a radar unit coupled to at least one ultra-low phase noise frequency synthesizer, configured for detecting the presence of one or more objects in one or more directions, the radar unit comprising (i) at least one clocking device configured to generate at least one first clock signal of at least one first clock frequency;', (a) at least one sampling phase detector configured to receive the at least one first clock signal and a single reference frequency to generate at least one first analog control voltage; and', '(b) at least one reference Voltage Controlled Oscillator (VCO) configured to receive the at least one analog control voltage to generate the single reference frequency; and', '(c) a Digital Phase/Frequency detector configured to receive the at ...

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Номер записи: 90
03-10-2019 дата публикации

FAST SETTLING RAMP GENERATION USING PHASE-LOCKED LOOP

Номер: US20190305785A1
Автор: Chillara Vamshi Krishna, Dalton Declan M., Dato Pablo Cruz
Принадлежит:

Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal. 1. A phase-locked loop with fast settling ramp generation , the phase-locked loop comprising:a phase detector comprising an output; anda loop filter comprising an integrator and an input coupled to the output of the phase detector, the loop filter configured to provide a ramp signal;wherein the phase-locked loop is configured to apply an offset signal to adjust an input signal provided to the integrator to cause settling time of the ramp signal to be reduced.2. The phase-locked loop of claim 1 , wherein the phase-locked loop is configured to apply the offset signal between the output of the phase detector and an input of the integrator.3. The phase-locked loop of claim 1 , further comprising:an oscillator comprising an input coupled to an output of the loop filter; anda phase error circuit configured to compute the offset based on (i) a change in slope of the ramp signal and (ii) an indication of gain of the oscillator.4. The phase-locked loop of claim 3 , further comprising an oscillator gain estimation circuit configured to provide the indication of gain of the oscillator to the phase error circuit.5. The phase-locked loop of claim 4 , wherein the oscillator gain estimation circuit comprises a correction loop configured to generate the indication of gain of the oscillator based on an output signal at the output of the phase detector.6. The phase-locked loop of claim 4 , wherein the oscillator gain estimation circuit is configured to compute the indication of gain of the oscillator based on measurements of a parameter of the phase-locked loop changing ...

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Номер записи: 91
01-11-2018 дата публикации

DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS

Номер: US20180316357A1
Автор: DENG Jingdong, FLYE David, HO Chung S., JIN Zhenrong, MALLADI Ramana M.
Принадлежит:

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator. 1. A circuit , comprising:a digital tuning signal being outputted into a ring oscillator; andan analog tuning signal being outputted into the ring oscillator, wherein the digital tuning signal and the analog tuning signal modify a frequency of the output of the ring oscillator array simultaneously.2. The phase locked loop circuit of claim 1 , wherein the analog tuning signal is part of an analog path which includes a linear phase detector and a proportional gain device.3. The phase locked loop circuit of claim 2 , further comprising a feedback path directly connecting an output of the ring oscillator to the analog path.4. The phase locked loop circuit of claim 3 , wherein the linear phase detector determines whether a reference signal leads or lags a feedback signal from the feedback path.5. The phase locked loop circuit of claim 4 , wherein based on the determination that the reference signal leads or lags the feedback signal claim 4 , the linear phase detector generates one or more outputs proportional to a phase difference between the reference signal and the feedback signal.6. The phase locked loop circuit of claim 5 , wherein the proportional gain device receives an output from the ...

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Номер записи: 92
01-11-2018 дата публикации

DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS

Номер: US20180316358A1
Автор: DENG Jingdong, FLYE David, HO Chung S., JIN Zhenrong, MALLADI Ramana M.
Принадлежит:

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator. 1. A phase locked loop circuit , comprising:a feedback path connecting an output of the oscillator to a digital path and an analog path, wherein a digital tuning signal and an analog tuning signal modify a frequency of the output of the oscillator simultaneously.2. The phase locked loop circuit of claim 1 , wherein the analog tuning signal continuously controls the frequency of the oscillator.3. The phase locked loop circuit of claim 2 , wherein the oscillator includes one or more devices that control the frequency of the oscillator based on the analog tuning signal.4. The phase locked loop circuit of claim 3 , wherein the analog path further includes a linear phase detector which generates the analog tuning signal based on a phase difference between a reference signal and the output of the oscillator.5. The phase locked loop circuit of claim 4 , wherein the analog path further includes a gain device which receives the analog tuning signal from the linear phase detector.6. The phase locked loop circuit of claim 5 , wherein the gain device is a proportional gain device which generates the analog tuning signal to have a voltage that is proportional to a phase difference between the reference ...

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Номер записи: 93
01-10-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200313679A1
Автор: MATSUI Katsuaki, Ogawa Junya
Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit , and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal. 1. A semiconductor device that is configured to output , as an output signal synchronized to a phase-locked loop clock signal , a synchronized input signal having been synchronized to a reference clock signal of a phase-locked loop circuit , the semiconductor device comprising:the phase-locked loop circuit configured to receive as an input signal the reference clock signal;a first flip-flop that is configured to receive at a first data input terminal an input signal in synchronization with the reference clock signal and at a first clock terminal a feedback signal inputted to a phase comparator of the phase-locked loop circuit; anda second flip-flop having a second data input terminal connected to a first output terminal of the first flip-flop,wherein the phase-locked loop circuit, the first flip-flop, and the second flip-flop are configured such that a setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.2. The semiconductor device according to claim 1 ,wherein the first flip-flop latches the input signal at a falling edge of the feedback signal,wherein the ...

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Номер записи: 94
01-10-2020 дата публикации

METHODS AND APPARATUS FOR PERFORMING A HIGH SPEED PHASE DEMODULATION SCHEME USING A LOW BANDWIDTH PHASE-LOCK LOOP

Номер: US20200313945A1
Автор: Bonu Madhulatha, Mukherjee Subhashish, Patki Abhijit Anant, Shrivastava Kumar Anurag
Принадлежит:

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase. 1. An apparatus comprising: receive, at the first input of the first bandwidth phase lock loop, a data signal at a first phase;', 'output, at the first output of the first bandwidth phase lock loop, a first output signal at the first phase; and', 'output, at the second output of the first bandwidth phase lock loop, a second output signal at a second phase; and, 'a first bandwidth phase lock loop with a first input, a second input, a first output, and a second output, the first bandwidth phase lock loop is configured to generate a phase-difference pulse by comparing the first output signal and the second output signal;', 'comparing the phase-difference pulse to a threshold;', 'generating a fast phase change detection signal based on the comparison of the phase-different pulse to the threshold;', 'output, at the first output of the fast phase change detection circuit, the fast phase change detection signal., 'a fast phase change detection circuit having a first input, a second input, and a first output, and a second output, the first input is coupled to the first output of the first bandwidth phase lock loop, the second input is coupled to the second output of the first bandwidth phase lock loop, and the output is coupled to the ...

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Номер записи: 95
17-10-2019 дата публикации

Method for Enhancing Linearity of a Receiver Front-End System by using a Common-Mode Feedback Process and Receiver Front-End System Thereof

Номер: US20190319589A1
Автор: Chen-Lun Lin, Mike Chun Hung Wang, Pang-Ning Chen, Wei-Jyun Wang, Ying-Chia Chen
Принадлежит: Kaikutek Inc

A method for enhancing linearity of the receiver front-end system includes receiving a radio frequency signal by an antenna, converting the radio frequency signal to first differential signals by a transformer module, adjusting frequencies of the first differential signals to generate second differential signals by a mixer module, detecting a common signal in order to reduce a common error of the second differential signals, and generating third differential signals according to a reference signal after the common error is reduced from the second differential signals. The first differential signals, the second differential signals, and the third differential signals are unbalanced.

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Номер записи: 96
17-10-2019 дата публикации

Divider-Less Phase Locked Loop

Номер: US20190319630A1
Автор: Chen-Lun Lin, Mike Chun-Hung Wang, Pang-Ning Chen, Wei-Jyun Wang, Ying-Chia Chen
Принадлежит: Kaikutek Inc

A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.

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Номер записи: 97
03-12-2015 дата публикации

Clock Recovery Techniques

Номер: US20150349784A1
Автор: Bogdan John W.
Принадлежит:

Clock recovery techniques (CRT) useful in a wide variety of communication systems based on wireless, optical and wireline links, include: a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality, a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing clocks, waveforms or messages, receiver synchronization techniques (RST) contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock. 1. A method for implementing a hybrid phase locked loop (HPLL) combining a digital phase locked loop (DPLL) with an analog phase locked loop (APLL) in order to maintain a preprogrammed phase and frequency transfer function between a reference clock and an output clock; wherein the HPLL method comprises the steps of:controlling operations of the HPLL by using the DPLL comprising a frequency phase detector (FPD) and a programmable control unit (PCU);producing the output clock by using the APLL comprising a phase synthesizer (PS) and an analog phase detector (APD) and a voltage controlled oscillator, wherein a first input of the PS and a first input of the APD are connected to the output clock and a second input of the APD is connected to an output of the PS;wherein the FPD measures digital phase errors between the output clock and the reference clock;wherein the PCU uses the digital phase errors for producing control signals applied to a second input of the PS;wherein the PS uses the control signals to insert phase differences, between the first APD input and the second APD input, needed for implementing the preprogrammed phase and frequency transfer function.2. A method for implementing a software controlled synchronizer (SCS) for maintaining a programmed phase frequency transfer function between a ...

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Номер записи: 98
03-12-2015 дата публикации

FAST ACQUISITION FREQUENCY DETECTOR

Номер: US20150349785A1
Автор: ERDOGAN Mustafa Ulvi, RAMASWAMY Sridhar
Принадлежит:

A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison. The binary phase detector is also configured to be disabled based on the PFD circuit being in a frequency locked state. The ternary phase detector is configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison. 1. A phase-frequency detector (PFD) circuit , comprising:a binary phase detector configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison; anda ternary phase detector coupled to the binary phase detector, the ternary phase detector configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison,wherein the binary phase detector is further configured to be disabled based on the PFD circuit being in a frequency locked state.2. The PFD circuit of claim 1 , further comprising:a first charge pump connected to the binary phase detector, the first charge pump configured to output a first charge pump output signal at a first current; anda second charge pump connected to the ternary phase detector, the second charge pump configured to output a second charge pump output signal at a second current.3. The PFD circuit of claim 2 , wherein the first charge pump output signal is configured to combine with the second charge pump output signal to form a combined charge pump output signal at a third current.4. The PFD circuit of claim 3 , wherein the third current is configured to be at a higher value during the frequency acquisition state than during the frequency locked state.5. The PFD ...

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Номер записи: 99
03-12-2015 дата публикации

HIGH SPEED CURRENT MODE LATCH

Номер: US20150349786A1
Автор: ERDOGAN Mustafa Ulvi
Принадлежит:

A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal. 1. A current mode logic (CML) latch , comprising:a first transistor coupled to a second transistor, the first and second transistors configured to receive a data signal;a third transistor coupled to a fourth transistor, the third and fourth transistors configured to receive a clock signal,a first capacitor connected to the first, second, third, and fourth transistors; anda second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors such that parasitic capacitance in the CML latch is offset.2. The CML latch of claim 1 , wherein the data signal is a differential signal comprising first and second data signals out of phase with respect to each other claim 1 , the first transistor being configured to receive the first data signal and the second transistor being configured to receive the second data signal.3. The CML latch of claim 2 , wherein the clock signal is a differential signal comprising a first and second clock signals out of phase with respect to each other claim 2 , the third transistor being configured to receive the first clock signal and the fourth transistor being configured to receive the second clock signal.4. The CML latch of claim 1 , wherein the first capacitor is connected to a source of the first and second transistors claim 1 , a drain of the third transistor claim 1 , and a gate of the fourth transistor.5. The CML latch of claim 4 , wherein the second capacitor is connected to a gate of the third transistor and a drain ...

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Номер записи: 100