АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ И СПОСОБ ПРЕОБРАЗОВАНИЯ ДЛЯ НЕГО

Изобретение относится к аналого-цифровому преобразователю и способу аналого-цифрового преобразования для него. Техническим результатом является снижение нагрузок на процессор цифровых сигналов за счет исключения необходимости компенсации фазовой задержки цифровых сигналов, а также обеспечение простоты и надежности конструкции аналого-цифрового преобразователя. Аналого-цифровой преобразователь содержит: блок прямой/обратной коммутации для попеременного последовательного выбора аналоговых сигналов множества каналов в прямом и обратном направлениях; блок дискретизации/хранения для дискретизации и хранения аналоговых сигналов, выбранных блоком прямой/обратной коммутации; блок аналого-цифрового преобразователя для преобразования аналоговых сигналов, дискретизированных и сохраненных блоком дискретизации/хранения, в соответствующие цифровые сигналы; и процессор цифровых сигналов для обработки цифровых сигналов, преобразованных блоком аналого-цифрового преобразователя, и для формирования управляющих ...

УСТРОЙСТВО ДЛЯ ГЕНЕРИРОВАНИЯ АНАЛОГОВЫХ СИГНАЛОВ С ИСПОЛЬЗОВАНИЕМ ЦИФРОАНАЛОГОВЫХ ПРЕОБРАЗОВАТЕЛЕЙ,ПРЕЖДЕ ВСЕГО ДЛЯ ПРЯМОГО ЦИФРОВОГО СИНТЕЗА

Изобретение относится к устройствам для генерирования аналоговых сигналов с использованием цифроаналоговых преобразователей. Технический результат заключается в уменьшении эффекта нелинейности таких преобразователей. Устройство содержит блок для генерирования слов, кодированных N битами, сигма-дельта-модулятор, соединенный с выходной шиной указанного блока, разделенной на М старших разрядов, подаваемых с задержкой на вход цифроаналогового преобразователя, и N-M младших бит, поступающих в сигма-дельта-модулятор, выход которого представляет собой М-битовую шину, выходной сигнал которой суммируется цифровым сумматором с выходными М-битами блока для генерирования слов. Изобретение используется в цифровых синтезаторах. 4 з.п. ф-лы, 7 ил.

Способ преобразования электрических импульсов в код Манчестер и устройство для его осуществления

Изобретение относится к электронным информационным техническим решениям общего назначения. Технический результат заключается в обеспечении устранения взаимовлияния прямого тракта и обратной связи, а также устранение апериодического эффекта от обратной связи. Предлагаемый способ состоит в том, что последовательность импульсов с входа устройства подвергается инверси знака для каждого четного импульса, посредством сохранения в памяти состояния входа на предыдущем шаге с помощью вспомогательного триггера, если на предыдущем шаге уровень сигнала был зафиксирован, то текущий шаг вычислений рассматривается в качестве четного. Последовательность импульсов на входе подвергается инверсии, чтобы обеспечить срабатывание триггера детектора сигнала на предыдущем шаге в противофазе по отношению к основному триггеру, на который и поступает полученная промежуточная последовательность импульсов с инверсией знака для каждого четного импульса, которая перед этим подвергается дополнительной коррекции. 2 н.п ...

Способ диагностики сверточных кодов

Изобретение относится к технике связи и может быть использовано для определения неизвестной структуры сверточного кодера со скоростью кодирования, равной, и кодовым ограничением, равным K, на основе анализа принимаемой кодовой последовательности. Технический результат – определение структуры используемого кодера для обеспечения работоспособности декодеров и повышение помехоустойчивости передачи информации. При осуществлении декодирования сверточных кодов необходимо знание структуры используемого кодера и сверточного кода, так как при отсутствии этой информации невозможно производить исправление ошибок. В данном способе повторно кодируют составляющие принимаемой общей кодовой последовательности с различными порождающими полиномами, перебирая их структуру, сравнивают результаты повторного кодирования. Поскольку символы исходной кодовой последовательности взаимно независимы, то результаты сравнения для всех сочетаний вида полиномов будут также случайны, кроме искомого вида полиномов. Для него ...

МНОГОКАНАЛЬНЫЙ ЦИФРОАНАЛОГОВЫЙ ПРЕОБРАЗОВАТЕЛЬ СИГНАЛОВ

Многоканальный цифроаналоговый преобразователь (ЦАП) сигналов, состоящий из последовательно включенных усилителя входных импульсов, регенератора импульсов, регистра сдвига, декодера, экспандера, параллельно соединенных своими информационными входами ключей модулей отсчетов, число которых равно числу уплотненных каналов, а также из распределительной линии, подключенной к выходу регистра сдвига, включающей в себя последовательно включенные опознаватель синхроимпульса, который имеет место в первом канале, генератор импульсов, счетчик импульсов, дешифратор импульсов, каждый выход которого подключен к управляющему входу ключа модуля отсчета, соответствующего номеру выхода дешифратора, отличающийся тем, что в него введены дополнительно ключи знака отсчетов и перемножители сигналов, причем число ключей знака отсчетов и перемножителей равно числу ключей модуля отсчетов и все ключи знака отсчетов подключены своими информационными входами параллельно к выходу первого триггера регистра сдвига, а их ...

АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ

Аналого-цифровой преобразователь, состоящий из последовательно соединенных источника аналогового сигнала, широтно-импульсного модулятора (ШИМ), первой схемы совпадений, первого цифрового счетчика импульсов, первого регистра сдвига, а также из генератора импульсов, подключенного ко второму входу модулятора ШИМ, мультивибратора, подключенного ко второму входу первой схемы совпадений, и генератора тактовых импульсов, подключенного ко второму входу первого регистра сдвига, первого дифференциатора, подключенного входом к выходу модулятора ШИМ, а выходом - к входу разрешения считывания регистра сдвига, и блока задержки, подключенного между выходом дифференциатора и входом сброса счетчика в нуль, отличающийся тем, что в него введены дополнительно вторая и третья схемы совпадений, два цифровых инвертора, делитель частоты в 2 раза, три дифференциатора, две схемы 2И-НЕ, цифровой последовательный сумматор, причем генератор импульсов подключен ко второму входу модулятора ШИМ через последовательно соединенные ...

Оптоэлектронный цифровой преобразователь угла

Полезная модель относится к автоматике и вычислительной технике и может быть использовано в системе контроля и управления подвижными объектами. Устройство содержит измерительный вал, на котором укреплена оптическая маска инверсного кода Грея, считывающую диафрагму, группу излучателей, оптически связанных через кодовый диск и диафрагму с соответствующими фотоприемниками, подключенными ко входам фотоусилителей, микроконтроллер с группой аналоговых входов встроенного АЦП и ячейками ввода/вывода цифровых сигналов, аналоговый ключ, управляющий вход которого связан первой ячейкой микроконтроллера, а информационные входы аналогового ключа подключены к источнику опорного напряжения и общей точке цепи питания группы излучателей, механический переключатель режимов работы, подключенный ко второй и третьей ячейкам ввода/вывода микроконтроллера, причем выходы фотоусилителей связаны с соответствующими входами АЦП, а также блок индикации, подключенный к четвертой и пятой ячейкам ввода/вывода. Техническим ...

ЭЛЕКТРОННЫЙ ПРОГИБОМЕР

Полезная модель относится к измерительной технике и может быть использована для определения прогибов при проведении испытаний строительных конструкций, при деформации эксплуатируемых изделий, поверхностей, материалов и т.п. В основу настоящей полезной модели положено решение задачи, позволяющей обеспечить удобство передачи информации и стабильность результатов измерений с высоким быстродействием, расширить эксплуатационные возможности прогибомера и уменьшить его габариты. Электронный прогибомер содержит измеритель перемещений, регистрирующее устройство, передаточный механизм, включающий тяговый элемент, взаимодействующий с объектом измерения. Измеритель перемещений и регистрирующее устройство размещены в одном корпусе с лицевой и задней стенками, измеритель перемещений выполнен в виде фотоэлектрического преобразователя угла с излучателями, индикаторным диском и фотоприемниками, установленными неподвижно, с поворотной осью вращения, установленной в подшипниках, на одном конце которой закреплен ...

АДАПТЕР ТЕЛЕМЕТРИЧЕСКИЙ

Адаптер телеметрический, содержащий управляющий контроллер с АЦП и ЦАП, ОЗУ и ПЗУ, встроенный загрузчик и технологический TTL порт, модуль питания, функциональные модули, отличающийся тем, что содержит модуль дискретного ввода, модуль ввода аналоговых сигналов, модуль дискретных выходов с гальванической развязкой, модуль аналогового входа, модуль интерфейса «аналоговая токовая петля», модуль цифровых интерфейсов, модуль связи по каналам GSM/UHF, регистры перепрограммируемой внутренней карты памяти имеют по несколько адресов, имеющих разное местоположение в карте памяти, которые доступны всем функциям протокола ModBus.

АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ С ВНУТРЕННЕЙ ПАМЯТЬЮ (ВАРИАНТЫ)

МНОГОКАНАЛЬНЫЙ АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ СИГНАЛОВ

Многоканальный анолого-цифровой преобразователь (АЦП) сигналов, состоящий из последовательно включенных многоканального ключевого дискретизатора по времени речевых сигналов, осуществляющего амплитудно-импульсную модуляцию АИМ-1, компрессора уровня отсчетов, преобразователя АИМ-1 в АИМ-2, кодера сигналов, регистра сдвига с генератором тактовых импульсов, подключенным к его второму входу, а также распределительной линии, включающей в себя последовательно подключенные к управляющим входам ключей дискретизатора генератор импульсов, первый счетчик импульсов, дешифратор, причем выход генератора импульсов подключен также ко второму входу кодера непосредственно и ко второму входу преобразователя АИМ-1 в АИМ-2 через первый блок временной задержки, отличающийся тем, что в него дополнительно введены двухполупериодный выпрямитель отсчетов речевых сигналов, RS-триггер, два блока задержки по времени, две схемы совпадения И, второй счетчик импульсов, схема 2И-НЕ, дифференцирующая цепь, причем через двухполупериодный ...

ИНТЕГРИРУЮЩИЙ АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ

Устройство относится к области вычислительной техники, предназначено для преобразования аналогового сигнала в код, например двоичный, и может использоваться в системах управления при автоматизации технологических процессов. Технический результат заключается в повышении точности работы АЦП за счет применения арифметико-логического устройства в замкнутой реверсивной автоколебательной системе МРП. Интегрирующий АЦП состоит из многозонного развертывающего преобразователя (МРП), содержащий два сумматора, интегратор и релейные элементы, ключевых элементов, дифференцирующего звена, демодулятора, генератора одиночного импульса, элемента задержки, АЛУ, регистра памяти, входной и выходной клеммы. 7 ил.

АНАЛОГО-ЦИФРОВОЙ МОДУЛЬ

Изобретение относится к области цифровой пространственно-временной обработки сигналов в радиотехнических устройствах и может быть использовано в цифровых антенных решетках. Технический результат заключается в повышении отношения сигнал-шум при обработке широкополосных сигналов. Он достигается тем, что аналого-цифровой модуль содержит малошумящий усилитель (МШУ), смеситель, усилитель промежуточной частоты (УПЧ), фильтр спектральных составляющих, группу из m фильтров деления, где m - количество участков спектра, на которые разделен спектр широкополосного сигнала, группу из m делителей, постоянный фазовращатель на 90o, два блока управляемых фазовращателей, две группы синхронных фазовых детекторов (СФД), каждая из которых содержит m детекторов, две группы АЦП, по m элементов в каждой, и два цифровых сумматора. 2 ил.

СИСТЕМА СЧИТЫВАНИЯ ИНФОРМАЦИИ АНАЛОГО-ИНФОРМАЦИОННОГО ПРЕОБРАЗОВАТЕЛЯ (АИП) С ДИНАМИЧЕСКИМ ПРОФИЛЕМ ИНТЕГРИРОВАНИЯ (ДПИ)

Изобретение относится к области аналого-цифровых преобразований. Техническим результатом изобретения является создание системы считывания аналого-информационного преобразователя (АИП) со сниженным энергопотреблением, за счет уменьшенного времени сбора информации о сигнале; с увеличенной производительностью, за счет использования ДПИ; с расширенной областью применения не только для частотно-разреженного сигнала, в режиме, когда минимальный интервал интегрирования не меньше времени оцифровки используемого АЦП; с увеличенной скоростью функционирования, за счет использования блока управления АЦП интегратором; с улучшенной функциональностью, за счет использования смешивающего устройства на базе УВХ на переключаемых конденсаторах; с улучшенной производительностью, за счет использования смешивающего устройства и фильтра низких частот, что позволяет обрабатывать целевой сигнал из широкой полосы частот. 2 з.п. ф-лы, 4 ил.

УСТРОЙСТВО ДЛЯ ПРЕОБРАЗОВАНИЯ АНАЛОГОВЫХ СИГНАЛОВВ КОД

Использование: в области вычислительной и измерительной техники. Технический результат заключается в повышении точности и расширении функциональных возможностей устройства. Устройство для преобразования аналоговых сигналов в код содержит первый аналого-цифровой преобразователь (АЦП), второй АЦП, ключи, устройство управления, генератор тактовой частоты. В него введены источник прецизионного опорного напряжения, снабженный системой термостатирования, регистр управления, буферный регистр, процессор, постоянное запоминающее устройство с прошивкой программ процессора для управления устройством для преобразования аналоговых сигналов в код, ключи выполнены в виде релейных ключей, каждый первый и второй АЦП выполнены как сигма-дельта аналого-цифровой преобразователь, к контактам ключей подключены вывод нулевого потенциала источника аналогового сигнала и выход источника прецизионного опорного напряжения. 3 ил.

СПОСОБ И УСТРОЙСТВО КОДИРОВАНИЯ И ДЕКОДИРОВАНИЯ ДАННЫХ

Описаны способ и устройство, предназначенные для разуплотнения и уплотнения данных. Настоящее изобретение относится к кодирующему устройству, предназначенному для использования в системах уплотнения, имеющих декодирующее устройство для декодирования информации, вырабатываемой кодирующим устройством. Соответствующее настоящему изобретению кодирующее устройство включает в себя кодер, предназначенный для генерирования информации кодовых слов в ответ на данные. Кодирующее устройство включает в себя также переупорядочивающий блок, который вырабатывает поток кодированных данных в ответ на информацию кодовых слов, поступающую с кодера. Переупорядочивающий блок включает в себя блок переупорядочивания счета прогонов, предназначенный для расположения кодовых слов в последовательность декодирования, и блок компоновки двоичных разрядов для объединения кодовых слов переменной длины в слова с чередованием фиксированной длины и для вывода этих слов фиксированной длины в последовательности, требуемой декодирующим ...

БАЗОВАЯ СИСТЕМА УСТРОЙСТВА ВВОДА ДЛЯ ЦИФРОВОГО ПРЕОБРАЗОВАТЕЛЯ

Изобретение относится к области электроники, в частности к элементам ввода систем управления технологическими процессами при цифровом преобразовании кода. В состав системы входят акустические датчики, генератор, контроллер, ключ. Датчики могут быть установлены на емкости. В качестве ключа может быть использовано реле.

СПОСОБ И УСТРОЙСТВО КОРРЕКЦИИ ПОГРЕШНОСТЕЙ АНАЛОГО-ЦИФРОВОГО ПРЕОБРАЗОВАНИЯ

... 1. Способ коррекции погрешностей аналого-цифрового преобразования, включающий аналого-цифровое (прямое) преобразование исходного сигнала, отличающийся тем, что, с целью уменьшения сложности реализации, при одновременном повышении точности и быстродействия, корректируемый k-разрядный аналого-цифровой преобразователь с момента включения переводится в режим непрерывного тестирования, которое осуществляется 2раз (k и m связаны соотношением: k=m+n), причем тестовый сигнал представляет собой ступенчатую функцию напряжения, изменяющегося в диапазоне входных сигналов корректируемого аналого-цифрового преобразователя и отождествляемого с 2эталонными сигналами, кодовый эквивалент порядкового номера которых служит адресом ячеек памяти оперативно-запоминающего устройства, в которые записывается выходной код тестируемого аналого-цифрового преобразователя; в ходе непрерывного тестирования режим коррекции блокируется; по завершению этапа непрерывного тестирования, начинается этап коррекции погрешностей ...

СПОСОБ И СИСТЕМА ДЛЯ МНОГОСКОРОСТНОГО РЕШЕТЧАТОГО ВЕКТОРНОГО КВАНТОВАНИЯ СИГНАЛА

... 1. Способ кодирования с многоскоростным решетчатым квантованием, содержащий i) обеспечение вектора х источника, представляющего кадр из сигнала источника; ii) обеспечение основной кодовой книги С, полученной из решетки Λ; iii) связывание с вектором х узла y решетки в решетке Λ; iv) если y включен в основную кодовую книгу С, то индексирование y в основной кодовой книге С для получения индексов квантования, и завершение способа, если нет, то v) расширение основной кодовой книги для формирования расширенной кодовой книги; vi) связывание с y кодового вектора с из расширенной кодовой книги; и vii) индексирование y в расширенной кодовой книге для получения индексов квантования. 2. Способ по п.1, в котором расширенная кодовая книга представляется выражением mC+V, в котором С - основная кодовая книга, V - соответствующее множество узлов в решетке Λ. 3. Способ по п.1, в котором на этапе iii) узел y решетки в решетке Λ выбирают в качестве ближайшего соседа х в решетке Λ. 4. Способ по п.1, в котором ...

СПОСОБ ОПРЕДЕЛЕНИЯ ИСКАЖЕНИЙ ТЕСТОВЫХ СИГНАЛОВ И ПАРАМЕТРОВ ТРАКТОВ ПЕРЕДАЧИ СИГНАЛОВ

Изобретение относится к измерительной технике и может быть использовано при создании измерительных комплексов повышенной точности для измерения всего комплекса параметров текстируемых трактов. Известен способ, в соответствии с которым формируют тестовый сигнал, состоящий из повторяющихся последовательностей сигналов в виде сумм из опорной низкочастотной компоненты, зависящей от времени t и номера последовательности с которым связано определенное сочетание погрешностей квантования, цифро-аналогового преобразования тестового сигнала и ограничения его спектра, и радиоимпульсной компоненты с радиочастотным заполнением с частотой ω, зависящей от времени t, пропускают тестовый сигнал через испытуемый тракт, определяют мгновенные значения искаженного сигнала на выходе тракта в каждый момент времени t, определяют по ним мгновенные значения опорной низкочастотной компоненты, амплитудной и фазовой огибающих радиоимпульсной компоненты, по которым определяют искомые параметры. Новым является то, что ...

СПОСОБ ОЦИФРОВКИ АНАЛОГОВОЙ ВЕЛИЧИНЫ, ОЦИФРОВЫВАЮЩЕЕ УСТРОЙСТВО, ОСУЩЕСТВЛЯЮЩЕЕ УКАЗАННЫЙ СПОСОБ, И ДЕТЕКТОР ЭЛЕКТРОМАГНИТНОГО ИЗЛУЧЕНИЯ, СОДЕРЖАЩИЙ ТАКОЕ УСТРОЙСТВО

... 1. Способ для оцифровки аналоговой величины (VE), произведенной детектором электромагнитного излучения, в частности, инфракрасного излучения, причем упомянутый детектор содержит матрицу смежно-расположенных элементарных датчиков, взаимодействие которых с упомянутым излучением образует упомянутую аналоговую величину (VE), причем способ содержит для каждой строки или для каждого столбца упомянутой матрицы этапы, состоящие: ! в выполнении первой фазы (302) интегрирования упомянутой аналоговой величины по первому временному интервалу с использованием каскада (410) интегратора; ! в задании прерывания упомянутой первой фазы (302) интегрирования посредством каскада (420) компаратора, у которого один вход связан с выходом упомянутого каскада (410) интегратора, и другой вход - с опорной схемой, подающей опорное значение (Vref); ! в преобразовании аналоговой величины, тем самым интегрировании (VS) до первого числового значения (B) посредством двоичного счетчика (442) и элемента (441) памяти, соединенного ...

Схема обработки сигнала с тензодатчика

Схема обработки сигнала с тензодатчика, содержащая первый источник опорного напряжения, измерительный усилитель, состоящий из первого и второго (ОУ), семи резисторах и АЦП, отличается тем, что дополнительно введены: тензодатчик, третий операционный усилитель, схема коррекции дрейфа нуля, содержащая, четвертый и пятый (ОУ), ключ, четыре резистора и конденсатор, а также анализатор нажатия кнопки тензодатчика, содержащий, второй, и третий источник опорного напряжения, компаратор, логический элемент "И-НЕ", логический элемент "ИЛИ", логический элемент "И" и таймер, причем выход тензодатчика, соединен со входом измерительного усилителя, а выход измерительного усилителя поступает на входы АЦП, схему коррекции дрейфа нуля и анализатор нажатия кнопки, причем выход анализатора соединен со входом схемы коррекции дрейфа нуля а выход со схемы коррекции дрейфа нуля поступает на вход измерительного усилителя.

КОДИРУЮЩАЯ ТРУБКА

Кодирующая трубка, содержащая последовательно расположенные в вакуумном баллоне электронную пушку, отклоняющие системы, кодирующую маску и коллектор, отличающаяся тем, что, с целью повышения выходной мощности трубки, в ней коллектор выполнен в виде диэлектрического концентратора, хладопровода и полупроводниковых преобразователей пучка электронов в оптическое излучение, расположенных на внутренней поверхности хладопровода и связанных с диэлектрическим концентратором, а кодирующая маска расположена между первой и второй отклоняющими системами.

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Изобретение относится к вычислительной технике, автоматике и системам управления. Цель: повышение точности преобразования код-напряжение достигается за счет введения масштабного регистра опорного напряжения, задающего диапазоны работы, наряду с входным кодом, и формирователя сигналов записи.

СПОСОБ КОДИРОВАНИЯ И СПОСОБ ДЕКОДИРОВАНИЯ ДЛЯ ПОДАВЛЕНИЯ БЛОКИРУЮЩИХ ИСКАЖЕНИЙ И УСТРОЙСТВА ДЛЯ ЕГО ОСУЩЕСТВЛЕНИЯ

Способ и устройство устранения блокирующих искажений. Система, применяющая указанные метод и аппаратуру, содержит кодирующую аппаратуру, содержащую задерживающее устройство для задержки информации входящего кадра, декодирующее устройство для декодирования сжатой информации и выпуска информации восстановления кадра, и устройство измерения блокирующих искажений, которое получает информацию восстановленного кадра и подаваемую информацию исходного кадра, и измеряет степень блокирующих искажений, используя информацию двух вышеупомянутых кадров, для того чтобы таким образом выработать определенный параметр последующей обработки, и аппаратуру декодирования, содержащую приемное устройство для принятия переданной информации и параметра последующей обработки, закодированных в вышеупомянутой кодирующей аппаратуре, второе декодирующее устройство для декодирования и восстановления кодированной переданной информации и фильтр для адаптации фильтрации выхода восстановленной информации от второго декодирующего ...

ОПТИКО-ЭЛЕКТРОННЫЙ КООРДИНАТОР

Оптико-электронный координатор, содержащий объектив и окуляр телескопической системы, анализатор изображений, конденсор, приемник излучения, отличающийся тем, что анализатор изображений выполнен в виде двухлинейных поляризаторов, причем первый выполнен в виде трех полосок поляризационной пленки, нанесенных на вращающуюся клиновую пластину вдоль ее радиуса через 45°, а второй поляризатор установлен неподвижно.

МАГНИТОТРАНЗИСТОРНЫЙ ПРЕОБРАЗОВАТЕЛЬ ТОКА В НАПРЯЖЕНИЕ И(ИЛИ) ЦИФРОВОЙ КОД

Магнитотранзисторный преобразователь тока в напряжение и/или цифровой код, содержащий несколько, например, n двухколлекторных магнитотранзисторов, расположенных по контуру вокруг шинопровода, отличающийся тем, что коллектора магнитотранзисторов соединены в две группы по n штук в каждой, по признаку одинакового знака приращения тока в каждом из коллекторов группы под действием приращения тока в шинопроводе, коллектора подключены на дифференциальный вход усилителя и/или аналого-цифрового устройства, аналоговый и/или цифровой выходы которых являются выходом преобразователя.

ЦИФРОАНАЛОГОВЫЙ ПРЕОБРАЗОВАТЕЛЬ И СПОСОБ ЕГО КАЛИБРОВКИ

... 1. Сегментированный N-разрядный цифроаналоговый преобразователь (ЦАП), включающий K-разрядный ЦАП1 старших разрядов, состоящий из 2-1 одинаковых сегментов и N-K-разрядный ЦАП0 младших разрядов, подключенные к общему источнику опорного напряжения Vref и имеющие общий выход, образующий выход ЦАП, блок калибровки, содержащий ЦАП2 источника тока калибровки, подключенного к выходу ЦАП, отличающийся тем, что блок калибровки определяет коды ЦАП2, дополняющие ток каждого сегмента ЦАП1 до тока опорного сегмента в стадии калибровки, а при работе подает на ЦАП2 коды компенсации ошибок ЦАП1, вычисленные для каждого значения кода старших разрядов по кодам ЦАП2, определенным при калибровке.2. Сегментированный N-разрядный ЦАП по п.1, отличающийся тем, что сегмент ЦАП1 включает резистор 2R, соединенный с выходом и ключом, коммутирующим его к источнику Vref или земле, ЦАП0 включает R-2R резистивный делитель и ключи, коммутирующие резисторы 2R к Vref или земле, опорный сегмент образован делителем из резистора ...

СПОСОБ ОПРЕДЕЛЕНИЯ ХАРАКТЕРИСТИКИ ЦАП С ИСПОЛЬЗОВАНИЕМ ТЕСТОВОГО СИГНАЛА

Изобретение относится к измерительной технике и может быть использовано при создании измерительных комплексов повышенной точности для измерения всего комплекса параметров ЦАП - статических и динамических нелинейных искажений, дифференциального усиления, амплитудной, амплитудно-частотной и импульсной характеристик и др. Известен способ определения характеристик ЦАП с использованием тестового сигнала, в соответствии с которым формируют тестовый сигнал, состоящий из повторяющихся последовательностей сигналов в виде сумм из опорной низкочастотной компоненты, зависящей от времени t и номера последовательности с которым связано определенное сочетание погрешностей квантования и цифро-аналогового преобразования тестового сигнала, и радиоимпульсной компоненты p-го сигнала, зависящей от времени t с радиочастотным заполнением частоты ω, пропускают цифровой тестовый сигнал через ЦАП, преобразуют выходной сигнал ЦАП в цифровую форму, в результате чего получают цифровой искаженный сигнал, определяют ...

Элемент с управляемой проводимостью

Изобретение относится к аналоговой вычислительной технике и может быть использовано при моделировании функций двух переменных В состав элемента входят конденсатор, два квадратичных преобразователя кода в ток, два импульсно-управляемь1Х ключа и инвертор, Элемент позволяет моделировать полиномальную функцию двух переменных, одна из которых задана кодом, а другая - широтно-импульсным сигналом. 1 ил.

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Устройство для импульсно-кодовой модуляции

Следящий аналого-цифровой преобразователь

... 1. СЛЕДЯЩИ АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ, содержащий первый блок сравнения, первый вход которого соединен с входной шиной, а второй вход - с выходом первого цифроаналогового преобразователя, входы которого соединены с первыми выходами первого реверсивного счетчика , выход блока сравнения соединен с первым входом первого блока управления , второй вход которого соединен с выходом генератора тактовых импульсов, третий вход - с вторым выходом первого реверсивного счетчика , четвертый вход - с шиной Запуск , а пятый вход - с шиной Стоп, первый выход - с первыми входами первого реверсивного счетчика, второй выход - с вторыми входами первого реверсивного счетчика, третьи входы которого соеданены с выходами первого распределителя импульсов, третий выход первого блока управления соединен с первым входом первого распределителя импульсов, четвертый выход - с первым входом логического блока, а пятый выход - с четвертым входом первого -реверсивного счетчика и вторым входом первого распределителя ...

Устройство выборки для преобразователя "напряжение-код"

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Преобразователь частоты следования импульсов в постоянный ток

Масштабный преобразователь напряжения

Аналого-цифровой преобразователь

Аналого-цифровой преобразователь

Устройство для формирования импульсов с переменным порогом чувствительности

SPATIAL DISPLACEMENT CHECKING DEVICE

Преобразователь угла в код и кода в угол

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SHAFT ROTATION ANGLE MEASURING METHOD

УСТРОЙСТВО ДЛЯ ЛИНЕАРИЗАЦИИ ХАРАКТЕРИСТИК ЧАСТОТНЫХ ДАТЧИКОВ

Способ измерения напряжения с применением цифрового вольтметра и устройство для осуществления этого способа

Преобразователь угла поворота вала в код

Изобретение относися к автоматике и вычислительной технике и предназначено для регистрации угловых перемещений объектов в цифровой форме, удобной для визуального наблюдения. Целью изобретения является расширение области применения преобразователя . Для этого в преобразователь, содержащий три диска, чувствительные элементы, два редуктора, два блока формирования сигналов, формирователь импульсов, пороговый элемент, введены шесть чувствительных элементов, два блока формирования сигналов, два формирователя импульсов, диски выполнены с синхронизирующими дорожками, активные участки которых совместно с активными участками, основных и дополнительных дорожек дисков, против которых расположены чувствительные элементы, позволяют получить на выходе значения кода с переменным основанием счисления. При врашении дисков свет от источника проходит через активные участки дорожек дисков и попадает на соответствующие чувствительные элементы. Освещенные и не- освеп1енные чувствительные элементы образуют на ...

Преобразователь цифрового кода в интервал времени

Изобретение относится к области импульсной техники и позволяет расши рить функциональные возможности преобразователя за счет обеспечения задания закона преобразования. Преобразователь содержит счетчик 1 импульсов. 9 в который записывается преобразуемый код по сигналу, поступающему по стартовой шине 10. По тому же сигналу триггер 8 устанавливается в состояние 1, открывая ключевой элемент 6, через который импульсы генератора 7 импульсов через делитель 5 частоты поступают на управляемый делитель 4 частоты , выходом соединенный с вычитающим входом счетчика 1 импульсов. Управляющие входы управляемого делителя 4 частоты соединены с выходом дешифратора 3 участков аппроксимации, входы которого через дешифратор 2 подключены к выходам счетчика 1 импульсов. В данном преобразователе путем соответствующей настройки дешифратора 3 участков аппроксимации обеспечивается наперед заданный закон преобразования цифрового кода в интервал времени. 1 -fo а & (Л ...

Преобразователь выходных сигналов параметрических датчиков в код

Изобретение относится к технике аналого-цифрового преобразования и может быть использовано в измерительно-информационных системах и системах регулирования . Целью изобретения является повышение точности. Преобразователь работает циклически в соответствии с периодами тока , питающего опорный и измерительный датчики, на выходе которых формируются напряжения, сдвинутые по фазе. На первом этапе осуществляется интегрирование положительных полуволн выходных напряжений датчиков с помощью опорного и измерительного интеграторов. На втором этапе, когда оба выходных напряжения датчиков становятся отрицательными, в б.токе управления и регистрации осуществляется подсчет импульсов тактовой частоты с помощью счетчика импульсов, код с выхода которого управляет выходным сигналом резистивной матрицы, на вход которой поступает сигнал с выходного опорного интегратора. При совпадении на нуль-органе сигналов с резистивной матрицы и измерительного интегратора подсчитанный код фиксируется и схема возвращается ...

Преобразователь угла поворота вала в код

ПРЕОБРАЗОВАТЕЛЬ УГЛА.ПОВОРОТА ВАЛА В КОД, содержаощй установленный на валу измерительный диск с концентричной и эксцентричной кольцевыми дорожками, неподвижный индикаторный диск со щелями, источники возбуждения и оптически с ними соединенные через эксцентричную кольцевую дорожку измерительного диска и щели индика- . торного диска основные чувствительные элементы, разнесенные один относительно другого на 90 , первый и второй дифференциальные усилители, выходы которых подключены к блоку преобразования амплитудно-модулированных сигналов в код, входы каждого дифференциального усилителя подключены к выходам диаметрально противоположных основных чувствительных элементов, отличающийся тем, что, с целью повышения точности преобразователя, в него введены дополнительные чувствительные элементы, размещенные на концентричной кольцевой дорожке через 90° радиально по отношению к основным чувствительным элементам, а выходы каждых диаметрально противоположных основного и дополнительного чувствительных ...

Устройство преобразования аналоговых сигналов

Изобретение относится к преобразованию аналоговых сигналов в цифровую форму с последующим восстановлением в аналоговую форму и может быть использовано в системах передачи сигналов, имеющих широкий динамический диапазон. Цель изобретения - повышение разрешающей способности преобразования и снижение уровня шума квантования. Устройство преобразования аналоговых сигналов содержит последовательно соединенные сумматор, аналого-цифровой преобразователь, канал связи, первый цифроаналоговый преобразователь, первый фильтр нижних частот, а также последовательно соединенные второй цифроаналоговый преобразователь, второй фильтр нижних частот, блок сравнения, причем вход второго цифроаналогового преобразователя подключен к выходу аналогоцифрового преобразователя, а выход блока сравнения соединен с первым входам сумматора. В устройство введены первый блок управления, состоящий из последовательно соединенных дешифратора и блока выделения постоянной составляющей, и второй блок управления, состоящий из последовательно ...

Устройство для ввода аналоговой информации

Формирователь импульсов для измерения частоты периодического сигнала

Изобретение относится к импульсной технике, в частности к измерительной технике, а именно к измерению частоты периодических колебаний. Цель изобретения - повышение помехоустойчивости путем повышения точности измерения частоты периодического сигнала за счет исключения влияния его неинформативных параметров. Формирователь содержит компараторы верхнего и нижнего уровней 1 и 2, бистабильный элемент 4 и элемент И 5. Новым в формирователе являются детектор нуля 3, второй элемент 6 и второй бистабильный элемент 7, что позволяет исключить влияние неинформативных параметров периодического сигнала. 2 ил.

Установка для поверки аналого-цифровых преобразователей

Преобразователь сопротивления в цифровой код

Квантующее устройство

Устройство для суммирования токов

Устройство для определения углеродногоэКВиВАлЕНТА B жидКОМ МЕТАллЕ

Следящий переключатель направления вращения вала

Аналого-цифровой преобразователь активной мощности

VERFAHREN UND GERAET ZUR SYNTHETISCHEN ERZEUGUNG VON WELLENFORMEN (WELLENFORMSYNTHESIZER)

D-A converter for digitally coded numbers - has signals applied to digitally controlled frequency divider whose output operates switch

The digital-analogue converter is for digitally coded positive and negative numbers having a sign digit in addition to other digits, and converts the numbers into positive or negative analogue voltages. Digital signals are applied to a digitally controlled frequency divider whose output signals operate a switch through which, depending on the input signal sign, a constant positive or negative voltage is applied to a frequency-to-voltage or frequency-to-current converter, connected between a negative and a positive supply potential. The frequency divider is connected to one input of an EXCLUSIVE-OR gate which feeds one input of an AND gate.

MEGNETFELDFUEHLVORRICHTUNG

Analog-/Digitalwandler mit automatischer Offsetsbereichregelung

IR temp. sensor for high temps.

The IR temp. sensor, providing an analogue output signal, uses an A/D converter with a variable resolution and measuring range for providing a corresponding digital signal. This is fed to a digital processing stage (52..88) allowing linearisation and evaluation of the digital signal. Pref. the A/D converter comprises a voltage/frequency converter (50) and a programmable frequency counter (54), supplied in alternation with the analogue signal provided by the sensor element (40) and with a reference signal provided by a reference source (44) under control of a temp. sensor (42).

SCHALTUNGSANORDNUNG UND VERFAHREN ZUM ANNAEHERN EINER NICHTLINEAREN UEBERTRAGUNGSFUNKTION

Einrichtung zur Abtastung der Position von getriebegekoppelten Scheiben mit modifiziertem Gray-Code

Elektrische Positionsmessvorrichtung mit einem die Position eines Geraeteteils in den Phasenwinkel einer Wechselspannung abbildenden Wandler

METHOD OF EVALUATING OUTPUT PULSE TRAINS OF AN INCREMENTAL DISPLACEMENT SENSOR, AND CIRCUIT ARRANGEMENT FOR CARRYING OUT THIS METHOD

VERFAHREN ZUR SELBSTKORREKTUR FEHLERHAFTER ERGEBNISSE SOWIE DIESES VERFAHREN VERWENDENDES SYSTEM ZUR GEWINNUNG ODER WIEDERHERSTELLUNG VON GROESSEN

DIGITAL-/ANALOG-WANDLERSYSTEM

Schaltung zur Kompensierung der Nichtlinearität der Ein-/Ausgangscharakteristik eines AD-Wandlers vom Parallel-Typ.

DIGITAL-ANALOG-WANDLER.

Digitaler Spitzenspannungsmesser

SCHALTUNGSANORDNUNG ZUM ERZEUGEN UND SPEICHERN EINES MIT STELLSIGNALEN VERAENDERBAREN ANALOGEN ELEKTRISCHEN SIGNALS

DIGITAL-ANALOG- UND ANALOG-DIGITAL- UMSETZERSCHALTUNG

SCHALTUNGSANORDNUNG ZUR BESTIMMUNG DER UMSCHALTPOTENTIALE VON DIGITAL-ANALOG-WANDLERN

DATENSAMMELKONSOLE

Switchable interpolator

The invention relates to a switchable interpolator for incremental measuring systems for distance and angle measurement, with the aim of reducing the circuit complexity and improving the adaptability of the measuring systems to different scales. The object is, above all, to achieve different interpolation factors with one interpolator. The switchable interpolator comprises mink-times interpolators which are logically combined by logic circuits and connected to a counting direction and edge evaluating device. An adjusting device for adjusting the interpolation factor is provided. The logic circuits comprise logic circuits known per se such as AND gates, or EXCLUSIVE-OR gates, inverters and NAND gates operating in various functions. ...

OFFSETKALIBRATIONSSYSTEM

ANALOG-DIGITAL-WANDLER

Bezugsgenerator

Ein-Chip-Halbleitervorrichtung

Method and device for improving the resolution in the digitisation of an analog signal

To improve the quantisation-related resolution accuracy in the digitisation of analog signals with a wide dynamic range, it is proposed to digitise the unamplified analog signal and the amplified analog signal separately. The resultant amplified digital signal is then amplified or correspondingly divided by the reciprocal gain factor. The digital signals thus produced are finally combined area by area by a weighting-type of adding up. In the area of large values of the analog signal, only the unamplified digital signal is used. In the area of small values of the analog signal, only the digital signal amplified back to normal level is used. In a transition area of medium-sized values of the analog signal, a sliding, preferably linear signal transition occurs between the two digital signals. For this purpose, a weighting factor, which is variable in the transition area, is derived from the amplified digital signal and is correspondingly taken into consideration in an addition circuit for ...

DIGITAL WAEHLBARE MEHRFACHSTROMQUELLE MIT PROPORTIONALITAET ZU EINEM REFERENZSTROM.

Treiberschaltung für eine Anzeige bestehend aus einer Vielzahl von Einzelelementen.

Einrichtung zur Messung von Winkeln durch Impulszaehlung

QAM Modulator und Demodulator.

Интегральный датчик перегрева ключа

Полезная модель относится к коммутационной технике и может быть использована в качестве встроенного устройства контроля управления силовым ключевым устройством. Технический результат заключается в точном контроле перегрева тепловыделяющего кристалла ключевого МОП транзистора, расположенного на одном кристалле с сенсором.Для достижения данного технического результата встроенный температурный датчик, формирователь опорного напряжения, аналоговый компаратор сигналов и схема управления затвором МОП транзистора выполнены в едином КМОП базисе и располагаются на одном кристалле с ключевым МОП транзистором, при этом настройка и регулировка температуры перегрева устанавливаются посредством дополнительного вывода. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 180 943 U1 (51) МПК H02H 9/00 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК G01K 7/00 (2006.01); H01L 27/00 (2006.01); H03M 1/00 (2006.01); H02H 9/00 (2006.01); H03K 17/00 (2006.01) (21)(22) Заявка: 2017132135, 13.09.2017 13.09.2017 (73) Патентообладатель(и): Акционерное общество "Протон" (АО "Протон") (RU) Дата регистрации: 02.07.2018 (56) Список документов, цитированных в отчете о поиске: RU 2244936 C2, 20.01.2005. RU (45) Опубликовано: 02.07.2018 Бюл. № 19 1 8 0 9 4 3 R U (54) ИНТЕГРАЛЬНЫЙ ДАТЧИК ПЕРЕГРЕВА КЛЮЧА (57) Реферат: Полезная модель относится к коммутационной формирователь опорного напряжения, технике и может быть использована в качестве аналоговый компаратор сигналов и схема встроенного устройства контроля управления управления затвором МОП транзистора силовым ключевым устройством. Технический выполнены в едином КМОП базисе и результат заключается в точном контроле располагаются на одном кристалле с ключевым перегрева тепловыделяющего кристалла МОП транзистором, при этом настройка и ключевого МОП транзистора, расположенного регулировка температуры перегрева на одном кристалле с сенсором. устанавливаются посредством дополнительного Для достижения ...

Receiver with Orthogonal Beam Forming Technique

A receiver with orthogonal beam forming technique is achieved that is capable of differentiating different signal components within the received composite signal. An adaptive processor is used to eliminate the signal component whose phase information is known or can be calculated. The phase information of the major component of a signal can be easily acquired by using a limiter. The phase information of other signal components can be acquired by their direction information and other characteristics, such as modulation scheme, etc. Multiple orthogonal beams can be formed by eliminating one unwanted signal component each time by the adaptive processor until all unwanted signal is eliminated. Thus, a composite signal from multiple sources can be broken down into their component signals.

Semiconductor device

There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Hearing aid with audio codec and method

A hearing aid comprising a time domain codec. The codec comprises a decoder adapted to generate a decoded output signal based on an input quantization index and an encoder for generating an output quantization index based on an input signal, said encoder comprising said decoder and a predictor receiving an excitation signal derived from said decoder output signal and outputting a prediction signal. The output quantization index is determined by repeated decoding of the quantization indices in order to minimize the error between the input signal and the prediction signal, and the predictor uses a recursive autocorrelation estimate for the error minimization. The invention further provides a method of encoding an audio signal.

Data look ahead to reduce power consumption

Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa. Eventually, the portions of the digital signal are provided to the sub-system so that the sub-system can respond to the portions of the digital signal.

Successive approximation register analog-to-digital converter

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Solid-state image sensing device

A solid-state image sensing device according to the invention which can reduce an instantaneous current occurring in transferring image digital signals from analog-digital converters to registers to reduce noise sneaking into the analog-digital converters and a pixel array includes a pixel array, a vertical scanning circuit, a plurality of column ADCs, a plurality of registers, and control signal generation units. The control signal generation units are provided for respective groups into which the column ADCs and the registers disposed on one side of the pixel array are divided, and generate control signals of different timings, for respective units including at least one group, of transfer of converted image digital signals to the registers from the column ADCs operating in parallel.

PIPELINED ANALOG-TO-DIGITAL CONVERTER

An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage. 1. An analog-to-digital converter (ADC) , comprising:a stage including an amplifier including an input and an output; anda plurality of copies of a circuit block, each copy of the circuit block including at least one capacitor,wherein, for a clock cycle that drives the ADC,the plurality of copies of the circuit block operate interleavingly in a plurality of modes, the plurality of modes including a pre-gain mode and a gain mode,the copies of the circuit block in the pre-gain mode are decoupled from the amplifier, andthe copies of the circuit block in the gain mode are coupled to the amplifier to produce an output signal for a following stage.2. The ADC of claim 1 , wherein the plurality of modes further includes at least one of a sample mode and a reset mode.3. The ADC of claim 2 , wherein claim 2 , for the clock cycle claim 2 , the circuit block in the sample mode receives an input signal that is supplied to a first capacitor to charge the first capacitor with the input signal claim 2 , and wherein the input signal is supplied to an input of a flash during the sample mode.4. The ADC of claim 3 , wherein the circuit block in the pre-gain mode regenerates a comparator in the flash claim 3 , drives a second capacitor in a digital-to-analog converter (DAC) based on an output of the comparator claim 3 , and distributes voltage charges between the first and second capacitors of the circuit ...

Sensor Circuit for Concurrent Integration of Multiple Differential Signals and Operating Method Thereof

The present invention provides a circuit for concurrent integration of multiple differential signals. The circuit comprises a plurality of Stage 1 integration circuit arranged in array and a plurality of Stage 2 integration circuit arrange in array. Each of said Stage 1 integration circuit is configured to concurrently integrate an input signal to send out a Stage 1 positive signal and a Stage 1 negative signal which is reverse to said Stage 1 positive signal. Each of said Stage 2 integration circuit is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to said corresponding Stage 1 integration circuit to output a Stage 2 signal. 1. A circuit for concurrent integration of multiple differential signals , comprises:a plurality of Stage 1 integration circuit arranged in array, wherein each of said Stage 1 integration circuit is configured to concurrently integrate an input signal to send out a Stage 1 positive signal and a Stage 1 negative signal which is reverse to said Stage 1 positive signal; anda plurality of Stage 2 integration circuit arranged in array, wherein each of said Stage 2 integration circuit is configured to integrate a differential signal from a Stage 1 positive signal sent from a corresponding Stage 1 integration circuit and a Stage 1 negative signal sent from another Stage 1 integration circuit next to said corresponding Stage 1 integration circuit to output a Stage 2 signal.2. The circuit of claim 1 , further comprises:a plurality of analog to digital converters arranged in array, wherein each of analog to digital converter converts a Stage 2 signal from a corresponding Stage 2 integration circuit to a digital signal.3. The circuit of claim 2 , wherein at least one of said plurality of analog to digital converters and corresponding Stage 2 integration circuit is a first successive ...

Method and System for Minimizing Variation of Converter Voltage Reference

A system for minimizing variation of a voltage reference includes a voltage reference generator and a power converter. The voltage reference generator is configured to generate a voltage reference from a supply voltage. The power converter, such as a flyback converter, is configured to supply an adjustable supply voltage to the voltage reference generator. The voltage reference generator generates the voltage reference from the adjustable supply voltage. 1. A system for minimizing variation of a voltage reference , the system comprising:a voltage reference generator configured to generate a voltage reference from a supply voltage; anda power converter configured to supply an adjustable supply voltage to the voltage reference generator;wherein the voltage reference generator generates the voltage reference from the adjustable supply voltage.2. The system of wherein:the power converter is further configured to adjust the adjustable supply voltage to account for external variations which would otherwise cause the voltage reference generator to generate the voltage reference with corresponding variations.3. The system of wherein:the power converter is a flyback converter.4. The system of wherein:the voltage reference generated by the voltage reference generator varies as a function of temperature variation of the voltage reference generator for a given supply voltage;wherein the power converter is configured to adjust the adjustable supply voltage such that the voltage reference generated by the voltage reference generator does not vary in the presence of the temperature variation of the voltage reference generator.5. The system of wherein:the power converter is configured to convert an input voltage into the adjustable supply voltage and is further configured to adjust the adjustable supply voltage independent of variation of the input voltage.6. The system of wherein:the voltage reference generated by the voltage reference generator varies as a function of variation ...

STABILITY CORRECTION FOR A SHUFFLER OF A SIGMA-DELTA ADC

A sigma-delta analog-to-digital converter (“ΣΔ ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ΣΔ ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ΣΔ ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler. 1. A second order shuffler , comprising:a first set of N accumulators, each first accumulator to receive corresponding digital-to-analog converter (DAC) unit element selection signals, each to accumulate values representing the corresponding selection signals and to generate corresponding first accumulator output values;a first corrector provided for the first accumulators to compress a range of the first accumulator output values for each first accumulator while maintaining context of each first accumulator with reference to the other first accumulators;a second set of N accumulators, each second accumulator to receive corresponding first accumulator output values, each to accumulate the corresponding output values and to generate corresponding second accumulator output values;a second corrector provided for the second accumulators to compress a range of the second accumulator output values for each second accumulator while maintaining context of each second ...

Low power slope-based analog-to-digital converter

Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.

INPUT CONVERTER FOR A HEARING AID AND SIGNAL CONVERSION METHOD

In order to minimize noise and current consumption in a hearing aid, an input converter including a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage includes an amplifier (Q) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (C, C, C, C). The invention further provides a method of converting an analog signal. 1. A sigma-delta converter converting an analog signal into a digital signal , and comprising:an input transformer receiving an input voltage and outputting a transformed voltage to a summation point;an integrator integrating a voltage present in the summation point;a comparator comparing an output from the integrator with a predetermined threshold and outputting a logical level in accordance with the comparison; anda feedback loop coupling a feedback signal back to the summation point;wherein said input transformer includes a switchable capacitor configuration.2. The converter according to claim 1 , wherein the input transformer includes at least two capacitors claim 1 , a plurality of switching elements and control logic claim 1 , and wherein the control logic switches the input transformer between a first and a second phase of operation.3. The converter according to claim 2 , wherein said plurality of switching elements and control logic is configured to arrange said ...

MULTI-PRIORITY ENCODER

A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input. 117-. (canceled)18. A multi-priority encoder comprising:a highest-priority single-priority encoder configured to indicate only a first match output signal corresponding to a first match line input signal; andone or more lower-priority single-priority encoders arranged in descending priority order, each configured to indicate only a lower-priority match output signal corresponding to a lower-priority match line input signal,wherein each of the single-priority encoders is comprised of at least as many single-priority stages as there are match line input signals, the single-priority stages being arranged in descending order, each stage having an arrangement of switching transistors configured to receive a match line input signal and to link the received match line input signal and an enable signal to a next lower priority single-priority stage.19. The multi-priority encoder of claim 18 , further comprising a NOR gate whose inputs include the match line input signal and a constant voltage signal and which is configured to link the received match line input signal and the enable signal to the a next lower priority single-priority stage.20. The multi-priority encoder of claim 19 , wherein the constant voltage signal is input to the NOR gate using one of the ...

Analog to digital converter

An analog to digital converter generating a number of corresponding voltages in response to a number of values of a grey level is provided. The analog to digital converter includes a decoder and an operational amplifier. The decoder provides first to third output voltages having the same level when w most significant bits (MSBs) of the grey level correspond to the same value, provides first and second intermediate voltages in response to the x MSBs next to the w MSBs when the w MSBs correspond to different values, and selectively has the first to the third output voltages equal to one of the first and the second intermediate voltages. The operational amplifier obtains a pixel voltage by interpolating the first to the third output voltages, wherein the sum of w and x is smaller than or equal to the bit number of the gray level.

SEMICONDUCTOR INTEGRATED CIRCUIT AND IMAGE SENSOR

According to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator. 1. A semiconductor integrated circuit configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal , the semiconductor integrated circuit comprising:m (m is an integer greater than or equal to 2) first capacitors, each of which comprises a first electrode and a second electrode, the first electrodes being connected to each other;m second capacitors, each of which comprises a third electrode and a fourth electrode, the third electrodes being connected to each other;a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; anda logic circuit configured to generate the digital signal based on a comparison result of the comparator,wherein the first analog voltage is inputted into the first electrode,the second analog voltage is inputted into the third electrode, andone of a ground voltage and substantially ½ of a voltage of an input voltage range of the semiconductor integrated circuit is inputted into each second electrode and each fourth electrode.2. The circuit of claim 1 , whereinonly two switches are connected to each second electrode ...

Integrating A/D Converter

In an integrating A/D converter, first and second reference voltage inputs () alternatingly connect through a reference voltage switch () via a first reference resistor (R) to an inverting input () of an integrator (). A comparator () connected downstream of the integrator () compares a test voltage applied to its test voltage input () with a comparator reference voltage applied to its reference voltage input (). This input () is connected to the output () of the integrator (). A control device () actuates the first reference voltage switch () in a pulsed manner and measures the time intervals between the individual switching processes. An inverter () inverting a measuring voltage (U) and a first heating resistor (R) coupled thermally with a measuring resistor (R), are connected in series between the measuring voltage input () and the output of the first reference voltage switch (). 1. An integrating analog-to-digital (A/D) converter , comprising:a measuring voltage input for an analog measuring voltage, which is connected via a measuring resistor to an inverting input of an integrator,a first reference voltage input for a first reference voltage and a second reference voltage input for a second reference voltage,a first reference voltage switch configured to alternatively connect the first and the second reference voltage inputs via a first reference resistor to the inverting input of the integrator,a comparator connected downstream of the integrator and configured to compare a test voltage applied to a test voltage input of the comparator with a comparator reference voltage applied to a reference voltage input of the comparator, wherein the comparator test voltage input is connected to an output of the integrator,a control device configured to actuate the first reference voltage switch in a clocked manner and to measure time intervals between individual switching processes, andan inverter configured to invert the measuring voltage and a first heating resistor ...

Adjustable and buffered reference for adc resolution and accuracy enhancements

An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

Efficient Front End Module

Example aspects of the present disclosure are directed to front end modules for use in communication systems. In one example aspect, a front end module can include a receive path. The receive path can include a low noise amplifier. The receive path can include an analog to digital converter (ADC) circuit operable to receive an analog signal from the low noise amplifier and convert the analog signal to a digital RF receive signal. The receive path can include an ADC post processing circuit operable to process the digital RF receive signal in the digital domain. The front end module can include a transmit path. The transmit path can include a digital to analog converter circuit operable to convert the digital RF transmit signal to an analog RF transmit signal. The transmit path can include a power amplifier. 1. A front end module comprising: a low noise amplifier operable to receive an RF signal from an antenna;', 'an analog to digital converter (ADC) circuit operable to receive an analog signal from the low noise amplifier and convert the analog signal to a digital RF receive signal;', 'an ADC post processing circuit operable to process the digital RF receive signal in the digital domain;', 'a digital down converter circuit operable to convert the digital RF receive signal to a digital baseband receive signal;, 'a receive path, the receive path comprising a digital up converter circuit operable to convert the digital baseband transmit signal to a digital RF transmit signal;', 'a digital to analog converter circuit operable to convert the digital RF transmit signal to an analog RF transmit signal;', 'a power amplifier configured to provide the analog RF transmit signal to the antenna., 'a transmit path, the transmit path comprising2. The front end module of claim 1 , wherein the ADC circuit is operable to convert analog RF signals across a span of about 800 MHz or greater in the 5 GHz band.3. The front end module of claim 1 , wherein the ADC circuit is a gigabit ADC ...

Delta/sigma modulator

According to one embodiment, a delta/sigma modulator includes a first multiplier based on a reference capacitor having capacitance C R and a first variable capacitor having capacitance C S1 according to a distance between electrodes thereof, the first multiplier being defined by a first multiplier factor given by C R /C S1 and being supplied with a reference voltage, a second multiplier based on a second variable capacitor having capacitance C S2 and a third variable capacitor having capacitance C S3 , the second multiplier being defined by a second multiplier factor given by C S3 /C S2 and being provided in a feedback path, and an adder configured to add an output of the first multiplier and an output of the second multiplier, wherein C S1 , C S2 and C S3 are the same.

Analog-digital converter

AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

KICKBACK COMPENSATION FOR A CAPACITIVELY DRIVEN COMPARATOR

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference. 1. An analog-to-digital converter (ADC) , comprising:a comparator having a first input and a second input;a voltage reference circuit having an output; a top plate coupled to the first input of the comparator; and', 'a bottom plate switchably coupled to the output of the voltage reference circuit;, 'a plurality of capacitors, each comprising, 'a first capacitive digital-to-analog converter (CDAC) comprising a top plate coupled to the second input of the comparator; and', 'a bottom plate switchably coupled to a ground reference., 'a plurality of capacitors, each comprising, 'a second CDAC comprising2. The ADC of claim 1 , wherein:the first CDAC comprises a first plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the first CDAC to the output of the voltage reference circuit;the second CDAC comprises a first plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the second CDAC to the ground reference.3. The ADC of claim 2 , wherein:the first CDAC comprises a second plurality of switches, each of the switches configured to switchably couple the bottom plate of one of the capacitors of the first CDAC to the ground reference;the second CDAC comprises a second plurality of switches, each of the switches configured to ...

Decision Feedback Equalizer

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Device for converting analogue signals into digital signals

Method and device for converting analogue signals, of a plurality of pathways, into digital signals. A common circuit ( 2, 3 ) generates first analogue signals corresponding to high-order bits of digital signals For each pathway, a first means compares the first analogue signals with the signal to be converted. A first means ( 18 ) stores high-order bits corresponding to the value of a first analogue signal close to the signal to be converted. A means ( 9 ) stores the deviation between the analogue signal to be converted and said first detected value. A generator means ( 11, 12 ) generates a predetermined number of second analogue signals. A second means compares by successive approximations said second analogue signals with said deviation. A means ( 20 ) stores said low-order bits corresponding to the results arising from said second means of comparison. A means ( 22 ) assembles said high-order bits and said low-order bits.

Comparator for low-banding noise and cmos image sensor including the same

A comparator may include: a comparison block suitable for comparing a ramp signal and a pixel signal and outputting a comparison signal; and a gain acquisition and noise reduction block suitable for amplifying the comparison signal outputted from the comparison block to acquire a gain and reduce an occurrence of noise.

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING ANALOG-TO-DIGITAL CONVERTER

To reduce power consumption of a sequential comparison analog-to-digital converter. An analog-to-digital converter includes a sequential conversion unit, a determination unit, and a stop control unit. The sequential conversion unit is configured to sequentially generate a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input. The determination unit is configured to determine whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated. The stop control unit is configured to stop the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range. 1. An analog-to-digital converter comprising:a sequential conversion unit configured to sequentially generate a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input;a determination unit configured to determine whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated; anda stop control unit configured to stop the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range.2. The analog-to-digital converter according to claim 1 , a comparator configured to compare the analog signal to a reference signal and generate the bits on a basis of a result of the comparison, and', 'a reference signal control unit configured to update a value of the reference signal whenever the bits are generated., 'wherein the sequential conversion unit includes'}3. The analog-to-digital converter according to claim 1 , further comprising:an output control unit configured to output a determination result obtained by determining whether the value of the digital signal is within the predetermined range.4. The analog-to-digital converter according to claim 3 ,wherein the output ...

SUCCESSIVE-APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) WITH ULTRA LOW BURST ERROR RATE

Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment. 1. A method , comprising:applying analog-to-digital conversion, in a signal processing component, to an analog input via a plurality of successive conversion cycles, wherein each conversion cycle corresponds to a particular bit in a corresponding digital output;for each one of the plurality of successive conversion cycles, triggering a next one of the plurality of successive conversion cycles based on a cycle termination event;detecting meta-stability during each one of the plurality of successive conversion cycles;retaining information relating to result of said detecting of meta-stability during each conversion cycle until end of the analog-to-digital conversion;after completing all of the plurality of successive conversion cycles, assessing a meta-stability state based on retained information for results of all of the plurality of successive conversion cycles; andcontrolling the digital output based on the assessing.2. The method of claim 1 , wherein assessing meta-stability state of a conversion cycle is based on settling of a matching search for that conversion cycle.3. The method of claim 2 , comprising determining that ...

Signal converter and method for operating a signal converter

In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

Multi-zone data converters

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Circuit for sensing an analog signal, corresponding electronic system and method

A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND SENSING METHOD

In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit. 1. A semiconductor device comprising:a timer circuit for generating a piece of time information and a first activation signal which is flowing periodically;a determination circuit for determining whether the value of an analog input signal exists within a predetermined range, in response to the first activation signal;a first conversion circuit for converting the analog input signal to a digital signal, in response to a second activation signal; anda processing circuit for processing the digital signal converted by the first conversion circuit, in response to a third activation signal,wherein, when the analog input signal does not exist within the predetermine range, the determination circuit generates the second activation signal and the third activation signal,wherein the processing circuit stores a piece of digital information corresponding to the digital signal, as well as the piece of time information from the timer circuit, into a storage circuit.2. A semiconductor device according to claim 1 ,wherein the determination circuit is supplied with its operation voltage in response to the first activation signal,wherein the second activation signal and the third activation signal are used as a common ...

Using a sampling switch for multiple evaluation units

In some examples, an integrated circuit device includes a sampling switch configured to sample an input signal. The integrated circuit device also includes a first evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The integrated circuit device further includes a second evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The sampling switch is configured to deliver the sampled input signal to the first evaluation unit and deliver the sampled input signal to the second evaluation unit.

MULTI-PATH ANALOG SYSTEM WITH MULTI-MODE HIGH-PASS FILTER

A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode. 152.-. (canceled)53. A system comprising:an input for receiving an input signal;an output for generating an output signal;a capacitor coupled between the input and the output;a resistance circuit coupled to the output and having a plurality of modes including a first mode in which a frequency transfer function of the system has a first high-pass corner frequency and a second mode in which the frequency transfer function of the system has a second high-pass corner frequency; and determine a difference between the input signal and the output signal; and', 'switch between modes of the plurality of modes when the difference is less than a predetermined threshold., 'control circuitry configured to54. The system of claim 53 , wherein the input claim 53 , the output claim 53 , the capacitor claim 53 , and the resistance circuit are arranged as a high-pass filter to generate the output signal as a high-pass filtered version of the input signal.55. The system of claim 54 , wherein: a first processing path configured to generate a first digital signal based on an analog input signal; and', 'a second processing path configured to generate a ...

Analog-to-digital converter circuitry with offset distribution capabilities

Analog-to-digital converter (ADC) circuitry may receive multiple analog signals and output corresponding digital signals. During the conversion process, comparators may receive the analog signals and a ramp waveform and compare the two inputs to generate logic signals. The logic signals correspond to digital signals that are outputted by ADC circuitry. To enable offset distribution capabilities, offset distribution circuitry may be selectively coupled to the inputs of the comparators. The offset distribution circuitry may include switches that couples a voltage supply providing reference voltages to the comparators. The reference voltages may be conveyed via a capacitor to the comparators as offset voltages. The offset voltages may provide may be different for different ADC units to offset power consumption of different ADC units and reduce power surges in power sources coupled to ADC circuitry.

Kickback compensation for a capacitively driven comparator

An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.

SAMPLING

There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. 1. An analogue-to-digital conversion circuit , comprising:a first node configured to receive a current signal, the current signal being configured to change in response to an input signal;a plurality of first switch circuits including a plurality of first terminals and a plurality of second terminals, each of the plurality of first terminals being coupled to the first node, the plurality of first switch circuits being configured to sample the current signal in accordance with a plurality of sinusoidal control signals and generate a plurality of sampled signals; anda plurality of analogue-to-digital converters coupled to the plurality of second terminals and configured to convert the plurality of sampled signals and generate a plurality of converted signals.2. The analogue-to-digital conversion circuit of claim 1 ,wherein the plurality of first switch circuits are configured to be sequentially selected during corresponding ones of a plurality of selection periods which occur in succession, successive selection periods of the plurality of selection periods are partially overlapped.3. The analogue-to-digital conversion circuit of claim 2 ,wherein the plurality of selection periods which occur in non-succession are non-overlapped.4. The analogue-to-digital conversion circuit of claim 1 , comprisinga digital circuit configured to generate a digital output signal on the basis of the plurality of converted signals.5. The analogue-to-digital conversion circuit of claim 1 , comprisinga plurality of demultiplexers coupled between the plurality of second terminals and the plurality of analogue-to-digital converters, each of the plurality of demultiplexers ...

Methods and apparatus for reducing timing-skew errors in time-interleaved analog-to-digital converters

A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

Readout circuit and method of using the same

A readout circuit includes a first analog circuit configured to receive an output of a first sub-array of a pixel array and to output a first signal based on the received output of the first sub-array. A second analog circuit is configured to receive an output of a second sub-array of the pixel array and to output a second signal based on the received output of the second sub-array. A first digital circuit is configured to receive the first signal and convert the first signal to a first digital signal, and receive the second signal and convert the second signal to a second digital signal.

Systems and methods for controlling switching circuitry

An electronic device for controlling switching circuitry is described. The electronic device includes line voltage measuring circuitry configured to measure a line voltage to produce a line voltage measurement. The electronic device also includes load voltage measuring circuitry configured to measure a load voltage to produce a load voltage measurement. The electronic device further includes a processor coupled to the line voltage measuring circuitry and the load voltage measuring circuitry. The processor is configured to adjust a control signal for a transition of the switching circuitry based on the line voltage measurement and the load voltage measurement to minimize heat generation and electromagnetic interference creation by the switching circuitry.

Analog-to-digital converter with bandpass noise transfer function

Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

Digital-to-Analog Converter

An apparatus and method for digital-to-analog conversion. A digital-to-analog converter includes a sampler for resampling a digital signal and a DAC array. The DAC array includes a sequencer, a unit element activator, and an array of one-bit DACs (unit elements). The unit elements are activated in a cyclical sequence, based on the resampled digital signal. Unit elements in the sequence may be skipped, based on a disruption probability. The disruption probability may be determined randomly, or pseudo-randomly. Output signals of the unit elements are summed or averaged to form an analog signal. The converter may include a filter to filter the analog signal.

ANALOG-TO-DIGITAL CONVERTER

According to embodiments of the present invention, an analog-to-digital converter is provided. The analog-to-digital converter includes an input configured to receive an input signal, a feed-forward path connected to the input configured to feed forward the input signal, a processing path including a loop filter, wherein the loop filter includes at least one local feedback path configured to feed back an output signal of the loop filter to an input of the loop filter, a first combiner configured to combine the input signal fed forward by the feed-forward path with an output of the processing path, a quantizer configured to generate an output signal of the converter, a feed-back path configured to feed back the output signal, and a second combiner wherein the processing path is connected to the second combiner and the second combiner is configured to combine the input signal with the fed back output signal of the converter and supply the result of the combination to the processing path. 1. An analog-to-digital converter comprising:an input configured to receive an input signal;a feed-forward path connected to the input configured to feed forward the input signal;a processing path comprising a loop filter, wherein the loop filter comprises at least one local feedback path configured to feed back an output signal of the loop filter to an input of the loop filter;a first combiner configured to combine the input signal fed forward by the feed-forward path with an output of the processing path;a quantizer configured to generate an output signal of the converter;a feed-back path configured to feed back the output signal; anda second combiner wherein the processing path is connected to the second combiner and the second combiner is configured to combine the input signal with the fed back output signal of the converter and supply the result of the combination to the processing path.2. The analog-to-digital converter according to claim 1 , wherein the loop filter comprises a ...

Analog-to-digital converter for a capacitive adiabatic logic circuit

An analog-to-digital converter for an adiabatic logic circuit, including at least one variable-capacitance cell, the cell including first and second main terminals and at least one control terminal insulated from its first and second main terminals and capable of receiving a control voltage to vary the capacitance between its first and second main terminals between a low value and a high value, wherein: the cell has its first main terminal coupled to a node of application of a variable periodic converter power supply voltage; the cell has its second main terminal coupled to a node for supplying a binary output signal of the converter; and the cell receives on its first control terminal an analog input voltage of the converter.

DAC CAPACITOR ARRAY, SAR ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR REDUCING POWER CONSUMPTION THEREOF

The present disclosure relates to a method for reducing power consumption, including: connecting one terminal of each capacitor in a first and a second capacitor array of an SAR ADC to a first reference voltage via a corresponding primary switch, connecting the other terminal of the capacitors to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array. 1. A digital-to-analog converter (DAC) capacitor array , comprising:a first capacitor array and a second capacitor array, each of the capacitor array comprises:a primary switch;a plurality of multiplexers; anda capacitor group, comprising a most-significant-bit capacitor, a least-significant-bit capacitor, a supplement-bit capacitor, and at least one second-most-significant-bit capacitor;wherein one terminal of each capacitor in the first capacitor array is connected to one input terminal of a comparator and is connected to a first reference voltage via the primary switch in the first capacitor array, and the other terminal of each capacitor in the first capacitor array is connected to a plurality of input sources via a corresponding multiplexer in the first capacitor array; andone terminal of each capacitor in the second capacitor array is connected to the other input terminal of the comparator and is connected to the first reference voltage via the primary switch in the second capacitor array, and the other terminal of each ...

DIGITAL-TO-ANALOG CONVERTER AND SOURCE DRIVER USING THE SAME

A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors. 128-. (canceled)29. A source driver , comprising:a digital-to-analog converter including a decoder which receives a digital signal, a resistor string which provides a plurality of gradation voltages, and a plurality of pass transistors which output a gradation voltage corresponding to the digital signal; anda buffer amplifier configured to providing an amplified gradation voltage by amplifying the gradation voltage output from the digital-to-analog converter, wherein the plurality of pass transistors are included in any one a plurality of groups according to output gradation voltages, and the number of pass transistors included in the groups are not expressed as a power of 2.30. The source driver of claim 29 , wherein the digital-to-analog converter further comprises a plurality of group selection transistors configured to provide a gradation voltage provided from a pass transistor included in any one among the plurality of groups to the buffer amplifier.31. The source driver of claim 30 , wherein the decoder decodes the digital signal and forms a signal which controls the plurality of ...

Method of dynamic element matching and an apparatus thereof

A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.

DIGITAL TO ANALOG CONVERTER

A digital to analog converter includes a reference voltage generation unit that generates a reference voltage, and a plurality of unit conversion units. A number of unit conversion units to be activated are decided in response to digital codes. An activated unit conversion unit drives a control node to a voltage level corresponding to a voltage level of the reference voltage, and a deactivated unit conversion unit substantially maintains the control node to a voltage level greater than a voltage level of a ground voltage. 1. A digital to analog converter comprising:a reference voltage generation unit that generates a reference voltage; anda plurality of unit conversion units, and a number of unit conversion units to be activated being decided in response to digital codes,wherein an activated unit conversion unit drives a control node to a voltage level corresponding to a voltage level of the reference voltage, and a deactivated unit conversion unit substantially maintains the control node to a voltage level greater than a voltage level of a ground voltage.2. The digital to analog converter according to claim 1 , wherein the deactivated unit conversion unit is configured to substantially maintain the control node to the set voltage level between a voltage level of the control node of the activated unit conversion unit and the voltage level of the ground voltage.3. The digital to analog converter according to claim 1 , wherein the deactivated unit conversion unit commonly electrically couples the control node and an output node.4. The digital to analog converter according to claim 1 , wherein each of the plurality of unit conversion units receives each bit of the digital codes and is activated when one of the bits has a specific level.5. The digital to analog converter according to claim 4 , wherein each of the plurality of unit conversion units comprises:a voltage applying section that drives the control node in response to the voltage level of the reference voltage; ...

ANALOG/DIGITAL CONVERTER

An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage. 1. An analog/digital converter comprising:a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period;a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; anda first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and whereinthe second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.2. The analog/digital converter according to claim 1 , whereinthe second analog/digital conversion unit performs digital conversion on lower bits that follow bits on which digital conversion is performed in the first analog/digital conversion unit.3. The analog/digital converter according to claim 1 , whereinin the first time period, when the first analog/digital conversion unit executes movement ...

DIGITAL-TO-ANALOG CONVERTER AND SOURCE DRIVER USING THE SAME

A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors. 117-. (canceled)18. A digital-to-analog converter , comprising:a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end;a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; anda decoder configured to control the plurality of pass transistors,wherein the plurality of the pass transistors are included in any one group of a plurality of groups according to values of the gradation voltages, and pass transistors included in the same group have the same type.19. The digital-to-analog converter of claim 18 , wherein the pass transistors included in the same group are arranged in the same deep well.20. The digital-to-analog converter of claim 18 , wherein the pass transistors included in the same group are NMOS pass transistors claim 18 , and the decoder controls the pass transistors using a control signal that swings between a minimum voltage of ...

SENSOR DEVICE INCLUDING HIGH-RESOLUTION ANALOG TO DIGITAL CONVERTER

Provided is a sensor device including: a sensor unit converting a voltage of a periodically switched capacitor into a pulse signal by referring to a clock signal to provide the pulse signal as a first sensing signal; and a high-resolution analog to digital converter (ADC) amplifying a period of the first sensing signal 2times (n is an integer), amplifying a period of the clock signal 2times, and generating a second sensing signal where a switching time of the capacitor is removed by removing the amplified clock signal from the amplified first sensing signal. 1. A sensor device comprising:a sensor unit converting a voltage of a periodically switched capacitor into a pulse signal by referring to a clock signal to provide the pulse signal as a first sensing signal; and{'sup': n', 'n−1, 'a high-resolution analog to digital converter (ADC) amplifying a period of the first sensing signal 2times (n is an integer), amplifying a period of the clock signal 2times, and generating a second sensing signal where a switching time of the capacitor is removed by removing the amplified clock signal from the amplified first sensing signal.'}2. The sensor device of claim 1 , wherein the sensor unit comprises:a first current source providing a charging current for charging the capacitor;a switch discharging the capacitor according to a switch control signal provided from the high-resolution ADC; anda comparator comparing the voltage of the capacitor with a reference voltage to output a comparison result as the first sensing signal.3. The sensor device of claim 2 , wherein the capacitor comprises a variable capacitance capacitor varying according to an external physical/chemical change.4. The sensor device of claim 2 , wherein the sensor unit comprises:a second current source providing the reference voltage; anda variable resistor providing the reference voltage according to a current provided from the second current source,wherein the capacitor is provided as a fixed capacitance ...

Ad converter

A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator.

System and method of improving stability of continuous-time delta-sigma modulators

An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Analog-to-digital converter

A system includes an analog-to-digital converter receiving a plurality of input signals. One particular input signal has a particular analog value and the analog-to-digital converter uses a fixed reference to convert the particular analog value to a particular digital value. The analog-to-digital converter uses the particular analog value as a reference for converting the analog values of the remaining input signals.

SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. 1. A system for providing a pipelined Analog-to-Digital Converter , comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal;', 'at least two reference capacitors that are charged to a reference voltage;', 'at least two sampling capacitors that are charged to a sampling voltage: and', 'a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage., 'a first multiplying Digital-to-Analog Converter (MDAC) stage comprising2. The system of claim 1 , wherein the first MDAC stage further comprises a first current source coupled to a first of the at least two reference capacitors and a ...

Dac capacitor array, analog-to-digital converter, and method for reducing power consumption of analog-to-digital converter

This disclosure discloses a DAC capacitor array, which includes a plurality of sub-capacitor arrays that are connected in parallel. Each sub-capacitor array includes: a capacitor group, including N capacitors connected in parallel, N being a positive integer; and a primary switch and a plurality of multiplexers; wherein one terminal of each capacitor in the capacitor group is connected to an input terminal of a comparator, and is connected to an input source via the primary switch; and the other terminals of the capacitors in the capacitor group are connected to a plurality of input sources via corresponding multiplexers respectively. The DAC capacitor array is optimized by adjusting the reference voltage to which the capacitors in the DAC capacitor array are connected, which reduces the overall capacitance of the DAC capacitor array.

SEMICONDUCTOR INTEGRATED CIRCUIT

A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group. 1. A semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal , the semiconductor circuit comprising:an analog circuit that quantizes the measured signal inputted; anda digital circuit that outputs the digital output signal, a correction element group including one or more correction elements each for correcting nonlinearity that occurs during a process of converting the measured signal into the digital output signal in the analog circuit; and', 'a test element group including one or more test elements for testing the one or more correction elements, and, 'wherein the analog circuit includesthe digital circuit tests the correction element group using the test element group.2. The semiconductor circuit according to claim 1 , a self-diagnostic code generation circuit that generates a self-diagnostic code for (i) enabling or disabling each of the one or more correction elements included in the correction element group and (ii) enabling or disabling each of the one or more test elements included in the test element group;', 'an error detection circuit that detects, as an error signal, a difference between a quantizer output signal of the analog circuit and a predetermined threshold value, the quantizer output signal being outputted in response to the self-diagnostic code; and', 'a self-diagnostic circuit ...

Current amplifier circuit, integrator, and ad converter

In one embodiment, a current amplifier circuit includes a first transistor, a first resistor, a second transistor, a second resistor, a first passive element, and a control circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The first resistor has one end connected to the first terminal of the first transistor. The second transistor has a first terminal, a second terminal, and a control terminal. The second resistor has one end connected to the first terminal of the second transistor. The first passive element is connected between the first terminals of the first transistor and the second transistor. The control circuit controls at least one of voltage at the control terminals of the first transistor and the second transistor such that the voltage at the other end of the first resistor becomes equal to the voltage at the other end of the second resistor.

Digital Modulator Entropy Source

An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.

Method and Apparatus for Generating OFDM Signals

A method in a transmitter circuit ( 200 ) of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first CP of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating ( 100 ) the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting ( 110 ) a sampling phase during CPs.

Method for processing continuous sensor signals, and sensor system

A method for processing continuous sensor signals of a sensor in which a sensor signal is sampled at a sampling frequency and a series of sampled values able to be classified in terms of time is generated in this way, the sampling frequency is dynamically adapted to the spectral signal properties of the sensor signal variable over time and an item of time information is allocated to the thereby generated sampled values, which allows an allocation of the sampled values in terms of time.

Capacitor circuit, circuit device, physical quantity detecting device, electronic apparatus, and moving object

A capacitor circuit includes: a capacitor array including a plurality of capacitors; a switch array including a plurality of switch circuits, the switch circuits being respectively connected to the capacitors of the capacitor array; a plurality of switch control signal lines supplied with a plurality of switch control signals; and a substrate having a major surface on which the switch circuits are formed. At least part of the capacitors of the capacitor array is formed of a first conductive layer. The switch control signal lines are formed of a second conductive layer provided between the major surface and the first conductive layer. The capacitor array and the switch array are disposed so as to overlap each other at least in part in a plan view when viewed in a normal direction of the major surface.

TRACK AND HOLD CIRCUITS FOR HIGH SPEED AND INTERLEAVED ADCS

Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC. 1. A low-power track and hold circuit , the low-power track and hold circuit comprising:a sampling buffer;a sampling network, with dither injection, to receive a buffered input from the sampling buffer; anda hold buffer to receive a held signal from the sampling network.2. The low-power track and hold circuit of claim 1 , wherein the sampling network comprises a node to receive an additive dither.3. The low-power track and hold circuit of claim 1 , further comprising:a chopper integrated with the sampling network to inject a multiplicative dither.4. The low-power track and hold circuit of claim 1 , wherein the sampling network comprises a switched-capacitor network to sample the buffered input from the sampling buffer onto one or more capacitors.5. The low-power track and hold circuit of claim 1 , wherein the hold buffer comprises a variable gain amplifier.6. The low-power track and hold circuit of claim 5 , further comprising:a signal level detector to detect an overload condition and generate a gain control signal of the variable gain amplifier.7. The low-power track and hold circuit of claim 2 , wherein the sampling network comprises:an input switch to receive the buffered input from the ...

Adc self-test using time base and current source

A constant current source, a stable time base and a capacitor are used to self-check operation of an analog-to-digital convertor (ADC) by charging the capacitor for a pre-determined amount of time to produce a voltage thereon. This voltage will be proportional to the amount of time that the capacitor was charged. Multiple points on the ADC transfer function can be verified in this self-check procedure simply by varying the amount of time for charging of the capacitor. Relative accuracy among test points may then be easily obtained. Absolute accuracy may be obtained by using an accurate clock reference for the time base, a known current source and capacitor value.

Digital-to-analog converters having a resistive ladder network

According to an embodiment, a digital-to-analog converter may be provided. The digital-to-analog converter may include a resistive ladder network including a plurality of paths corresponding to bit currents, respectively. The digital-to-analog converter may include a switching circuit configured to include a plurality of weighted elements respectively coupled to the paths. The digital-to-analog converter may include a reference voltage setting circuit coupled to the weighted elements and the paths, and configured to minimize a variation of threshold voltages of the weighted elements.

SYSTEMS AND METHODS FOR DELAY-BASED CONTINUOUS TIME PROCESSING

Disclosed herein are some continuous time systems and methods. Some of the disclosed systems and methods use a continuous-time analog-to-digital converter (ADC) configured to receive an analog input and to generate an ADC output, a continuous-time digital signal processor configured to receive the ADC output and generate one or more digital outputs, one or more digital-to-analog converters configured to receive the one or more digital outputs, each digital-to-analog converter configured to receive a corresponding digital output and generate an analog output, and an adder configured to receive the analog outputs of the one or more digital-to-analog converters and to generate a summed analog output. 1. A continuous-time system comprising:a continuous-time analog-to-digital converter (ADC) configured to receive an analog input and to generate an ADC output;a continuous-time digital signal processor configured to receive the ADC output and generate one or more digital outputs;one or more digital-to-analog converters configured to receive the one or more digital outputs, each digital-to-analog converter configured to receive a corresponding digital output and generate an analog output; andan adder configured to receive the analog outputs of the one or more digital-to-analog converters and to generate a summed analog output.2. The continuous-time system of claim 1 , wherein the ADC output comprises one or more continuous-time digital fixed-width pulses having a repetition rate determined based on an amplitude of the analog signal.3. The continuous-time system of claim 1 , wherein the continuous-time analog-to-digital converter comprises one or more asynchronous digital delay blocks claim 1 , each asynchronous digital delay block having a tunable delay.4. The continuous-time system of claim 3 , wherein the tunable delay is determined based on the analog input.5. The continuous-time system of claim 3 , wherein the one or more asynchronous digital delay blocks form a ...

Binary signal detection based on non-uniform adc

In an embodiment, a receiver comprises: a linear equalizer for receiving an input signal and outputting a partly equalized signal; a VGA (variable-gain amplifier) for receiving the partly equalized signal and outputting an amplitude-adjusted signal in accordance with a gain control signal; a non-uniform ADC (analog-to-digital converter) for receiving the amplitude-adjusted signal and outputting a digitized signal; and a DSP (digital signal processing) circuit for receiving the digitized signal and outputting a bit stream by performing a signal detection and establishing the gain control signal by performing an amplitude comparison. The non-uniform ADC has a lower precision when the amplitude-adjusted signal lies in a region where the signal detection is of a higher confidence, and has a higher precision when the amplitude-adjusted signal lies in a region where the signal detection is of a lower confidence. In an embodiment, the DSP circuit includes a decision feedback equalizer.

METHOD AND APPARATUS FOR CALIBRATING DIGITAL BACKGROUND THROUGH CAPACITOR DIVISION AND SWAPPING FOR REDUCING CAPACITOR MISMATCH EFFECT OF ANALOG-TO-DIGITAL CONVERTER

A high-quality Analog to Digital Converter (ADC) is used to calibrate a difference attributable to a capacitor mismatch in a Digital to Analog Converter (DAC). The present invention is advantageous in that it can fabricate a low-power high-resolution ADC by calibrating an error attributable to a capacitor mismatch through a digital background calibration apparatus and method using a Successive Approximation Register (SAR). 1. A digital background calibration apparatus using capacitor division and swapping in order to reduce a capacitor mismatch effect of an Analog to Digital Converter (ADC) , the apparatus comprising:a Digital to Analog Converter (DAC) configured to select any one of an input signal, a ground voltage, and a reference voltage in response to a first control signal and a second control signal, convert the selected signal or voltage into an analog signal, and output a first conversion signal and a second conversion signal as the converted analog signal;a comparator configured to convert the first conversion signal and the second conversion signal into digital signals, output a first digital signal and a second digital signal as the converted digital signals, and output a third digital signal as a comparison value of the first conversion signal and the second conversion signal;a Successive Approximation Register (SAR) configured to output a first register signal and a second register signal using the first digital signal and the second digital signal and output the first control signal using the third digital signal;a calibration unit configured to output a digital code calibration signal by calibrating a mismatch value of the first register signal in response to an external control signal; anda bit controller configured to output the second control signal using the second register signal in response to the external control signal,wherein the digital code calibration signal is fed back to one side of the calibration unit, and the input signal comprises a ...

ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD

An analog-to-digital converter according to the present invention includes first and second analog-to-digital conversion cells (), control means () for, when a mode specifying signal MD indicates a first mode, generating a control signal that sets first and second input ranges to the same voltage range and sets first and second clocks to different phases, and when the mode specifying signal MD indicates a second mode, generating the control signal that sets the first and second input ranges to one continuous voltage range and sets the first and second clocks to the same phase, ADC cell control means () for controlling the voltage ranges of the first and second input ranges according to the control signal, and a sampling clock generation unit () that generates the first and second sampling clocks according to the control signal. 1. An analog-to-digital converter comprising:a first analog-to-digital conversion cell that quantizes a voltage level of an analog signal within a first quantization range at a first quantization step and outputs a first digital value;a second analog-to-digital conversion cell that quantizes the voltage level of the analog signal within a second input range at a second quantization step and outputs a second digital value;control means for, when a mode specifying signal indicates a first mode, generating a control signal that sets the first and second input ranges to the same voltage range and sets first and second sampling clocks to different phases, and when the mode specifying signal indicates a second mode, generating the control signal that sets the first and second input ranges to one continuous voltage range and sets the first and second sampling clocks to the same phase;ADC cell control means for controlling the voltage ranges of the first and second input ranges according to the control signal;sampling clock generation means for supplying the first and second sampling clocks to the first and second analog-to-digital conversion cells, ...

Energy-proportional image sensor

The subject disclosure is directed towards energy saving mechanisms of image sensor circuitry (e.g., in a camera). Image quality data, such as provided by an application, is processed to make energy consumption of image sensor circuitry more proportional to output image quality by controlling the operation of one or more controllable power saving mechanisms of the image sensor circuitry. Power saving mechanisms may include a frequency controlled clock, the ability to turn off unneeded components, an inter-frame standby mode that puts the image sensor circuitry into a standby mode between capturing sequential frames, selectable parallel analog chains having different energy usage properties and column circuitry that allows turning off circuitry corresponding to unneeded columns of the sensor array.

BASELINE COMPENSATION SYSTEM

An analog to digital converter (ADC) system that includes a first amplifier configured to amplify an analog input signal to produce an amplified direct current (DC) signal, an ADC configured to receive the amplified DC signal and convert the amplified DC signal into a digital DC signal, a digital to analog converter configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal, and a second amplifier configured to receive an analog alternating current (AC) signal comprising the analog DC signal subtracted from the analog input signal and amplify the analog AC signal to produce an amplified AC signal. The ADC is further configured to receive the amplified AC signal and produce a digital AC signal. The second amplifier has a gain greater than a gain of the first amplifier. 1. An analog to digital converter (ADC) system , comprising:a first amplifier configured to amplify an analog input signal to produce an analog amplified direct current (DC) signal;an ADC configured to receive the analog amplified DC signal and convert the analog amplified DC signal into a digital DC signal;a digital to analog converter (DAC) configured to receive the digital DC signal and convert the digital DC signal into an analog DC signal; anda second amplifier having a gain greater than a gain of the first amplifier, the second amplifier configured to receive an analog alternating current (AC) signal, the analog AC signal comprising the analog DC signal subtracted from the analog input signal, and amplify the analog AC signal to produce an amplified AC signal;wherein the ADC is further configured to receive the amplified AC signal and produce a digital AC signal.2. The ADC system of claim 1 , further comprising a subtracting circuit configured to subtract the analog DC signal from the analog input signal.3. The ADC system of claim 1 , wherein the ADC is further configured to transmit the digital AC signal to a digital signal processor (DSP).4. The ADC ...

Signal processing apparatus, signal processing method, and non-transitory computer-readable storage medium storing program

To enable processing of a signal at an appropriate level. An analog section in which an acquired signal is processed in an analog fashion and a digital section in which the signal processed in the analog section is digitally processed are included, wherein the analog section includes an adjustment unit that adjusts a gain discretely and the digital section includes a digital step compensation unit that compensates for discrete gain adjustments in the analog section. The digital step compensation unit responds to a transient step in which a gain steeply converts in the analog section and compensates with inverse characteristics of a transient response. The present technology can be applied to an AGC (Automatic Gain Control) system.

Semiconductor integrated circuit device and data processing system

The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer.

ANALOGUE TO DIGITAL CONVERTER

An Analogue to Digital Converter (ADC) having a Gated Ring Voltage Controlled Oscillator, GRVCO, to generate a phase signal according to an input voltage; and a quantization circuit to generate a quantized phase output signal according. The GRVCO operates in either a first or second mode of operation according to a gating control signal. In the first mode of operation, the GRVCO operates in a VCO mode with gating disabled. In the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal. 1. An analogue to digital converter , ADC , comprising:a Gated Ring Voltage Controlled Oscillator, GRVCO, configured to generate a phase signal according to an input voltage; anda quantization circuit configured to generate a quantised phase output signal,wherein the GRVCO is configured to operate in either a first or a second mode of operation according to a mode control signal, wherein, in the first mode of operation, the GRVCO operates in a VCO mode with gating disabled and, in the second mode of operation, the GRVCO operates in a GRVCO mode wherein gating is enabled or disabled according to a gating signal.2. The ADC of claim 1 , wherein claim 1 , when gating is disabled claim 1 , oscillations of the ring oscillator are permitted and claim 1 , when gating is enabled claim 1 , oscillations of the ring oscillator are suspended and a state of the ring oscillator is preserved.3. The ADC of claim 1 , wherein the GRVCO comprises a gating signal generator configured to generate the gating control signal according to a clock signal and the mode control signal.4. The ADC of claim 3 , wherein the gating signal generator comprises a logic arrangement and a multiplexer claim 3 ,wherein the logic arrangement is configured to generate a first input signal of the multiplexer from a reference clock signal,wherein a supply voltage is supplied to the second input of the multiplexer,and wherein the mode control signal is ...

Asynchronous successive approximation analog-to-digital converter and related methods and apparatus

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

HYBRID ANALOG-TO-DIGITAL CONVERTER

An analog-to-digital converter (ADC) circuit includes a first ADC stage comprising a first successive approximation register (SAR) circuit that is configured to convert a current analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a current digital output signal, and to generate a residual voltage corresponding to a voltage value difference between the current analog input signal and the first digital signal; a second ADC stage, coupled to the first ADC stage, comprising an amplifier circuit that is configured to amplify the residual voltage; and a third ADC stage, coupled to the second ADC stage, comprising a second SAR circuit that is configured to convert the amplified residual voltage into a second digital signal corresponding to a least-significant-bits (LSB) portion of the current digital output signal when the first SAR circuit receives a subsequent analog input signal. 1. An analog-to-digital converter (ADC) circuit , comprising:a first ADC stage comprising a first successive approximation register (SAR) circuit that is configured to convert a current analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a current digital output signal, and to generate a residual voltage corresponding to a voltage value difference between the current analog input signal and the first digital signal;a second ADC stage, coupled to the first ADC stage, comprising an amplifier circuit that is configured to amplify the residual voltage; anda third ADC stage, coupled to the second ADC stage, comprising a second SAR circuit that is configured to convert the amplified residual voltage into a second digital signal corresponding to a least-significant-hits (LSB) portion of the current digital output signal when the first SAR circuit receives a subsequent analog input signal.2. The circuit of claim 1 , wherein the second SAR circuit of the third ADC stage is further configured to ...

Analog-digital converter

A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

ULTRA-HIGH SPEED DIGITAL-TO-ANALOG (DAC) CONVERSION METHODS AND APPARATUS HAVING SUB-DAC SYSTEMS FOR DATA INTERLEAVING AND POWER COMBINER WITH NO INTERLEAVING

A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules. 1. A digital-to-analog converter (DAC) apparatus for a ultra-high speed operation having a full sampling frequency of 2 GHz or higher for interleaving data using multiple sub-DAC systems , followed by combining the interleaved data using a power combiner network without interleaving , the DAC apparatus comprising:one or more digital pre-coders configured to process digital signals; a first current-mode DAC system comprising a first sub-DAC system and a second sub-DAC system;', 'a second current-mode DAC system comprising a third sub-DAC system and a fourth sub-DAC system; and', 'a first power combiner network comprising a first input node, a second input node, and an output node, wherein the first power combiner network is coupled to the first current-mode DAC system at the first input node and coupled to the second current-mode DAC system at the second input node,', the first current-mode DAC system comprises a first transmission line coupled to the first and second sub-DAC systems and the first power combiner network, wherein the first transmission line has a length greater than ...

DIGITAL TO ANALOG CONVERTER WITH AN INTRA-STRING SWITCHING NETWORK

A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. In one configuration, the multi-string DAC is configured to use the voltage change at terminals of a first string separately to the voltage drop across a first switching network that couples the first and second strings to provide an analog output in response to a digital input to the DAC. 1. A multistring digital to analog converter , DAC , comprising:a first string with a plurality of impedance elements;a second string with a plurality of impedance elements;a first switching network adapted to couple a voltage produced across at least one of the impedance elements in the first string across the second string in response to a digital input signal, said digital signal comprising a digital bit stream, the impedance elements in the second string configured to produce voltages in response to current passing from the first string through the first switching network to the second string to produce a corresponding analog signal to said digital input signal to an output node,a second switching network comprising non-current carrying switches configured to provide at least one least significant bit, LSB, transition at the output node in response to a sensed change across the first switching network.2. The DAC of comprising a third switching network coupling terminals of the second string directly to the output node.3. The DAC of wherein the first switching network is responsive to the most significant bits claim 1 , MSBs claim 1 , and the least significant bits claim 1 , LSBs claim 1 , of said digital input signal.4. The DAC of comprising a control circuit configured to provide code dependent compensation for claim 1 , or control of claim 1 , variances in a response of switches within the DAC.5. The DAC of wherein the second switching network is configured to provide the LSB transition at the output node separately to a ...

Novel Wide Null Forming System with Beam forming

A novel wide null forming system achieves both wide bandwidth and beam width null through employing an antenna array to receive and transmit signals to which a complex null weight vector, calculated by perturbation program, is applied. The novel wide null forming system includes a multiple-element antenna array for receiving or transmitting signals. Multiple conditioning units matching the number of elements is present to condition the signals for proper reception and analysis, after which a series of complex multiplier processors adds complex weights. After being weighted each constituent beam is combined in an adding processor to form one composite beam for use by the user.

A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value. 1. An analog-to-digital converter circuit that converts an analog input signal into a digital quantity comprising:an analog-to-digital converter unit that converts the analog input signal into a pre-correction digital value; anda corrector unit that digitally corrects the pre-correction digital value output from the analog-to-digital converter unit,wherein the corrector unit includes:a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the analog-to-digital converter unit and summing them, anda weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.2. The analog-to-digital converter circuit according to claim 1 ,wherein the weighting coefficient search unit ...

Customized Data Converters

A method is provided for supplying a customized data converter fabricated from a universal function die. The method initially fabricates a plurality of universal data converter dice. Each universal data converter die is capable of performing a first plurality of data conversion algorithms. After the dice are made, each universal data converter die is tested to verify the performance of the first plurality of data conversion algorithms. Subsequently, a request is received for a customized data converter capable of performing a first data conversion function, which is selected from among the first plurality of data conversion algorithms. The method then fabricates a customized data converter capable of performing the first data conversion function, using a tested universal data converter die. The unselected data converter functions are disabled (not enabled). A configuration interface may be used to enable the requested data conversion function.

Analog-to-digital converter

An analog-to-digital converter that converts an inputted analog signal into a digital value is disclosed that may include unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal, and an adder that adds the digital values converted by the unit circuits. Each unit circuit may include coupling switches that couple the series resistor circuit with the series resistor circuit of another one of the unit circuits and connect the series resistor circuits between the high potential side reference voltage and the low potential side reference voltage and a sharing switch that shares the inputted analog signal with the other unit circuit that is coupled with the series resistor circuit.

SYSTEM, ANALOG TO DIGITAL CONVERTER, AND METHOD OF CONTROLLING SYSTEM

Power consumption of a successive-approximation type analog to digital converter is reduced. A system is provided with an analog to digital converter and a power-supply voltage generation unit. In the system provided with the analog to digital converter and the power-supply voltage generation unit, the analog to digital converter compares an analog signal with a reference signal and outputs frequency information indicating the number of times of comparison. Also, in the system, the power-supply voltage generation unit generates power-supply voltage on the basis of the frequency information output by the analog to digital converter and supplies the same to the analog to digital converter. 1. A system comprising:an analog to digital converter which compares an analog signal with a reference signal and outputs frequency information indicating the number of times of comparison; anda power-supply voltage generation unit which generates power-supply voltage on the basis of the frequency information to supply to the analog to digital converter.2. The system according to claim 1 , further comprising:a conversion time measurement unit which measures conversion time from when the analog signal is sampled until the number of times of comparison indicated by the frequency information reaches a certain number of times,wherein the power-supply voltage generation unit generates the power-supply voltage corresponding to the measured conversion time, andthe analog to digital converter includesa comparator which compares the analog signal with the reference signal to generate the comparison result,a digital signal holding unit which holds the comparison result each time the comparison result is generated and outputs a signal indicating the held value as a digital signal,a reference signal supply unit which changes a value of the reference signal on the basis of the digital signal to supply to the comparator, anda frequency information output unit which outputs the frequency ...

DELTA-SIGMA MODULATOR

Provided is a delta-sigma modulator including a summer summing an input signal and an analog signal, a first integrator integrating an output signal from the summer and outputting a first integration signal, a second integrator integrating the first integration signal and outputting a second integration signal, a comparator comparing the second integration signal and a reference signal and outputting a digital signal according to the comparison result, and a digital-to-analog converter converting the digital signal into an analog signal in response to a clock signal and outputting the converted analog signal, wherein the second integrator operates based on an Nth order (where N is natural number of 1 or greater) transfer function. 1. A delta-sigma modulator comprising:a summer summing an input signal and an analog signal;a first integrator integrating an output signal from the summer and outputting a first integration signal;a second integrator integrating the first integration signal and outputting a second integration signal;a comparator comparing the second integration signal and a reference signal and outputting a digital signal according to the comparison result; anda digital-to-analog converter converting the digital signal into an analog signal in response to a clock signal and outputting the converted analog signal,wherein the second integrator operates based on an Nth order (where N is natural number of 1 or greater) transfer function.2. The delta-sigma modulator of claim 1 , wherein the digital signal output from the comparator is delivered to the summer through the digital-to-analog converter as a negative feedback structure.3. The delta-sigma modulator of claim 1 , wherein each of the first and second integration signals comprises positive and negative signals.4. The delta-sigma modulator of claim 3 , wherein claim 3 , when the second integrator operates based on a 2nd-order transfer function claim 3 , the second integrator comprises:a first resistor ...

ANALOG-TO-DIGITAL CONVERTER WITH AN INCREASED RESOLUTION FIRST STAGE

One example includes a pipelined analog-to-digital converter device. The pipelined analog-to-digital converter device includes a capacitive digital-to-analog converter, a first analog-to-digital converter, and a second analog-to-digital converter. The capacitive digital-to-analog converter includes a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device while the capacitor is grounded, holding the sampled analog input while the top plate is floated, and outputting a residue voltage. The second analog-to-digital converter is coupled to the top plate of the capacitor, the second analog-to-digital converter producing a second digital representation of voltage on the top plate of the capacitor after the top plate is floated, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device. 1. A pipelined analog-to-digital converter device , comprising:a first stage comprising:a capacitive digital-to-analog converter including a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device on the bottom plate of the capacitor while the top plate of the capacitor is grounded, holding the sampled analog input while the top plate is floated, and outputting a residue voltage;a first analog-to-digital converter coupled to the bottom plate of the capacitor, the first analog-to-digital converter producing a first digital representation of voltage on the bottom plate of the capacitor while the capacitor is grounded, wherein the first digital representation represents course bits produced by the first stage of the pipelined analog-to-digital converter device; anda second analog-to-digital converter coupled to the top plate of the capacitor, the ...

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING ANALOG-TO-DIGITAL CONVERTER

The present invention aims to reduce power consumption in an ADC that performs AD conversion of a single-ended signal. A pair of sampling capacitors samples the single-ended signal. After the single-ended signal has been sampled, the connection control unit performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined ground potential and performs negative-side connection control of connecting both ends of the other of the pair of sampling capacitors across a negative-side signal line and the predetermined ground potential. A conversion unit converts a differential signals from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal. 1. An analog-to-digital converter comprising:a pair of sampling capacitors that samples a single-ended signal;a connection control unit that, after the single-ended signal has been sampled, performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined terminal and performs negative-side connection control of connecting both ends of another of the pair of sampling capacitors across a negative-side signal line and the predetermined terminal; anda conversion unit that converts a differential signal from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal.2. The analog-to-digital converter according to claim 1 , further comprising a pair of common voltage generating capacitors charged with a predetermined internal potential claim 1 ,wherein the pair of sampling capacitors samples the single-ended signal in a state where the capacitor is connected in parallel ...

Self-Tracking and Self-Ranging Window Analog-to-Digital Converter

This disclosure relates to an analog-to-digital converter, ADC. The ADC comprises a first detection and second detection line, each including a plurality of serially arranged detection units, where the detection units of the first line are controlled in accordance with a first signal and the detection units of the second line are controlled in accordance with a second signal, and each line comprises a first group of serially arranged detection units and a second group of serially arranged detection units, a pulse generator for generating a periodic pulse signal that is fed to each of the lines, a sampling unit configured to read out values held by the detection units of the first group in one of the first and second lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second lines, and a detection line control unit configured to adjust a delay of the second group of detection units in the one of the first and second lines in accordance with a read out of the detection units of the first group of detection units. 1. An analog-to-digital converter , ADC , comprising:a first detection line and a second detection line, each including a plurality of serially arranged detection units, wherein the detection units of the first detection line are controlled in accordance with a first signal and the detection units of the second detection line are controlled in accordance with a second signal and wherein each detection line comprises a first group of serially arranged detection units and a second group of serially arranged detection units;a pulse generator for generating a periodic pulse signal that is fed to each of the first and second detection lines;a sampling unit configured to read out values held by the detection units of the first group of detection units in one of the first and second detection lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other ...

Alias Rejection Through Charge Sharing

An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter. 1. An apparatus comprising:an input node;a charge-sharing node;a filter-sampling network including a capacitor and a first switch, the first switch coupled between the input node and the capacitor, the filter-sampling network configured to connect or disconnect the capacitor to or from the input node via the first switch;a digital-to-analog converter including a capacitor array and a second switch, the second switch coupled between the input node and the capacitor array, the capacitor array coupled between the second switch and the charge-sharing node, the digital-to-analog converter configured to connect or disconnect the capacitor array to or from the input node via the second switch; anda charge-sharing switch coupled between the charge-sharing node and the capacitor, the charge-sharing switch configured to connect or disconnect the capacitor to or from the digital-to-analog converter.2. The apparatus of claim 1 , wherein:the input node is configured to accept an analog signal;the ...

Multichannel analog-to-digital converter

Multichannel successive approximation register (SAR) analog-to-digital converters (ADC), along with methods and systems for multichannel SAR analog-to-digital conversion, are disclosed herein. An exemplary multichannel SAR ADC can include a first SAR ADC for each of a plurality of input channels, and a second SAR ADC, a multiplexer, and a residue amplifier shared among the plurality of input channels. The multiplexer can select an analog residue signal from one of the first SAR ADCs for conversion by the second SAR ADC. The residue amplifier can amplify the selected analog residue signal. The second SAR ADC, multiplexer, and/or residue amplifier may be shared among all of the plurality of input channels. Where the multichannel SAR ADC includes N input channels, the second SAR ADC, multiplexer, and/or residue amplifier may be shared among b channels of the N input channels.

Versatile detection circuit

A versatile detection circuit is optimized for low sensor voltages and contains a microprocessor. The microprocessor contains an integrated analog-to-digital converter with an input pin. The integrated analog-to-digital converter is configured to rely on a reference voltage of no more than 2 volts. The detection circuit also has a transformation circuit for transforming a sensor signal, the transformation circuit being connected to the input pin of the integrated analog-to-digital converter. The transformation circuit contains an impedance converter and with the exception of the impedance converter relies only on passive electric elements.

Digital to analog converter with thermometer coding and methods for use therewith

A digital to analog converter (DAC) includes a thermometer coder that processes a digital input based on a thermometer coding, and generates a plurality of micro-current source inputs and a plurality of micro-current source analog controls. A plurality of micro-current sources generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls. A summing circuit generates an analog output based on a sum of the corresponding plurality of micro-current source outputs.

SIGMA-DELTA MODULATOR AND ANALOG-TO-DIGITAL CONVERTER

A Sigma-Delta modulator and an analog-to-digital converter. The Sigma-Delta modulator comprises a quantizer, a correction module and an RC integrator. The correction module comprises a predetermined resistance through which a correction level is generated. The correction module is used to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer, so as to generate a digital correction signal, based on which the resistance in a resistance correction array in the RC integrator is corrected. The predetermined resistance is of the same type as the resistance in the resistance correction array in the RC integrator. The Sigma-Delta modulator and the analog-to-digital converter can correct the resistance deviation in the RC integrator. 1. A Sigma-Delta modulator , comprising a quantizer , a correction module and an RC integrator; whereinthe correction module comprises a predetermined resistor through which a correction level is generated;the correction module is configured to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer, to generate a digital correction signal, and correct resistance of a resistance correction array in the RC integrator based on the digital correction signal, wherein the predetermined resistor is of the same type as resistors in the resistance correction array in the RC integrator.2. The Sigma-Delta modulator according to claim 1 , wherein the Sigma-Delta modulator further comprises a DAC and a D flip-flop claim 1 , an input end of the D flip-flop is electrically connected to an output end of the comparator claim 1 , an output end of the D flip-flop is connected to an input end of the DAC claim 1 , and an output signal of the DAC is fed back to an input end of the RC integrator; and whereinthe D flip-flop is configured to synchronize a comparison signal A between the RC integrator and the predetermined reference voltage, the synchronized ...

Adjustment Module and Battery Management System Thereof

An adjustment module for an analog to digital converter (ADC) of a battery management system (BMS) includes a detection unit, for detecting a slop of an input current, to generate a sampling control signal; and a sampling frequency adjustment unit, for adjusting a sampling frequency of the ADC according to the sampling control signal.

Single-ended Linear Current Operative Analog to Digital Converter (ADC) with Thermometer Decoder

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

Digital signal processing waveform synthesis for fixed sample rate signal sources

A test and measurement instrument including a digital-to-analog converter having an output sample rate configured to receive a digital sample waveform and a reference clock and output an analog waveform at the sample rate, a waveform synthesizer configured to receive an input waveform having a baud rate and output a digital sample waveform having a baud rate less than the sample rate of the digital-to-analog converter, and a port configured to output the analog waveform.

Solid-state imaging apparatus and camera

A solid-state imaging apparatus, including a plurality of pixels, and an A/D conversion unit configured to convert a pixel signal of an analog signal into a digital signal, wherein the A/D conversion unit comprises a comparator, a sampling unit, a counter, and an output unit configured to output the digital signal based on a count result of the counter and a sampling result of the sampling unit, and the sampling unit comprises first and second latch units configured to latch an output from the comparator in response to first and second clock signals, respectively, and a third latch unit configured to latch an output from the first latch unit in response to an output of the second latch unit.

METHODS AND DEVICES FOR AN ENERGY EFFICIENT DIGITAL TO ANALOG CONVERSION

Methods and devices for an energy efficient digital to analog conversion are disclosed. With the achievable sampling rates and output voltage levels, high power RF signals can be synthesized. A plurality of pulses are generated and coupled onto transmission lines. On the other end of the transmission line the pulses are either reflected or transmitted to a load line depending on the status of a termination element. In one embodiment the reflected pulses are collected and sent to a load. The energy in the transmitted pulses can be recovered and reused. In another embodiment the transmitted pulses are collected and transmitted to a load and the energy in the reflected pulses is recovered and reused. 1. A pulse digital to analog converter circuit comprising:a pulse source;a wave propagation medium having a first end and a second end that is arranged remote from the first end;a switching element arranged between the pulse source, the first end, and a load, wherein the switching element is configured to switch an electrical connection from the wave propagation medium to either the pulse source or the load;a termination element coupled to the second end, wherein the termination element has a state and is configured to absorb and/or reflect a pulse from the wave propagation medium based on the state; andan energy recovery circuit configured to recover the energy of a portion of the pulse that is not reflected by the termination element.2. (canceled)3. The pulse digital to analog converter of claim 1 , and further comprising a controller configured to interact with the pulse source claim 1 , the termination element claim 1 , and/or the switching element.4. The pulse digital to analog converter of claim 1 , wherein the pulse digital to analog converter includes a plurality of wave propagation media claim 1 , each of the plurality of the wave propagation media electrically coupled to a corresponding termination element at its respective second end and each of the pulse ...

TIME-DOMAIN INCREMENTAL TWO-STEP CAPACITANCE-TO-DIGITAL CONVERTER

An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion. 1. A capacitance-to-digital converter (CDC) comprising:{'sup': 'st', 'a first stage successive approximation register capacitance-to-digital converter (1stage SAR CDC) circuit portion configured to perform a plurality of successive approximations of an input capacitance signal to generate a SAR conversion residue and a first set of converted outputs; and'}{'sup': nd', 'nd', 'nd, 'a second stage time-domain incremental delta-sigma modulator capacitance-to-digital converter (2stage TD incremental ΔΣM CDC) circuit portion that quantizes the SAR conversion residue, using, in part, a voltage-controlled oscillator (VCO) based integrator of the 2stage TD incremental ΔΣM CDC operating in a closed-loop control with a digital-to-analog converted signal generated, in part, by the first set of converted outputs, wherein the 2stage TD incremental ΔΣM CDC generates a second set of converted outputs as a representation of an input sensed capacitance signal.'}2. The capacitance-to-digital converter of claim 1 , wherein the 2stage TD incremental ΔΣM CDC circuit portion comprises:a N-stage ring VCO circuit; anda phase and frequency detector (PFD) coupled to the N-stage ring VCO circuit to an output for the closed-loop control.3. The capacitance-to-digital converter of claim 2 , wherein the 2stage TD incremental ΔΣM CDC circuit portion further comprises a passive charge sharing (CS) circuit coupled to the N-stage ring VCO circuit.4. The capacitance-to-digital converter of claim 1 , wherein the N-stage ring VCO circuit is implemented as a G-stage-driven current-controlled oscillator (CCO).5 ...

SUCCESSIVE-APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) WITH ULTRA LOW BURST ERROR RATE

Systems and methods are provided for enhanced analog-to-digital conversions, particularly by allowing for an ultra-low burst error rate. Analog-to-digital conversion may be applied to an analog input via one or more conversion cycles; and performance related parameter corresponding to the analog-to-digital conversion may be assessed. A digital output corresponding to the analog input may be generated, with the generating being controlled based on the assessing of the performance related parameter. The controlling may include adjusting at least a portion of the digital output. The assessing may include determining, for at least one conversion cycle, whether a performance related condition, corresponding to the performance related parameter, occurs. The determination may be based on an outcome of a matching search performed for that conversion cycle. The determination that the performance related condition occurs may be made when the matching search fails to settle within a corresponding time period. 120-. (canceled)21. A method , comprising:applying analog-to-digital conversion to an analog input via one or more conversion cycles; 'determining, for at least one conversion cycle, whether a performance related condition, corresponding to said performance related parameter, occurred, based on an outcome of a matching search performed for that conversion cycle; and', 'assessing a performance related parameter corresponding to said analog-to-digital conversion, said assessing comprisingcontrolling generating a digital output corresponding to said analog input based on said assessing of said performance related parameter.22. The method of claim 21 , comprising assessing said outcome of said matching search after triggering of a next conversion cycle.23. The method of claim 21 , comprising triggering at least one conversion cycle based on a cycle termination event associated with a prior conversion cycle.24. The method of claim 23 , wherein said cycle termination event ...

Dynamic gain switching digital to analog converter

A digital to analog converter that may include a digital gain block; an analog gain block; a digital to analog conversion (DAC) block and a controller that is configured to: determine a digital gain factor, selected out of multiple digital gain factors, of the digital gain block and an analog gain factor, selected out of multiple analog gain factors of the analog gain block; wherein the DAC block is preceded by the digital gain block and is followed by the analog gain block; wherein the digital gain block is configured to multiply a digital input signal by the digital gain factor to provide an intermediate digital signal; wherein the DAC block is configured to convert the intermediate digital signal to a converted analog signal; and wherein the analog gain block is configured to multiply the converted analog signal by the analog gain factor to provide an output signal; wherein an increment of the analog gain factor results in a decrement of the digital gain factor.