Hybrid analog-to-digital converter having multiple adc modes

A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

Mixed mode analog to digital converter and method of operating the same

An analog to digital converter in accordance with the inventive concept may include a reference voltage generation circuit outputting first and second reference voltages; a decompression part decompressing amplitude of an analog input signal and the first and second reference voltages; a flash ADC converting the decompressed analog input signal into a first digital signal with reference to the decompressed first and second reference voltages; and a successive approximation ADC converting the analog input signal into a second digital signal according to a successive approximation operation with reference to the first digital signal and the first and second reference voltages.

Signal converting apparatus and related method

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.

ANALOG-TO-DIGITAL CONVERSION DEVICE

An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of the rear SAR ADCs is electrically coupled to the front SAR ADC and is configured to receive the analog input signal and the corresponding group of higher bits in response to the different time periods. The rear SAR ADCs convert the analog input signal into a group of lower bits of the digital output signal corresponding to the time period of the group of higher bits. 1. An analog-to-digital conversion device comprising:a clock circuit configured to generate p multi-phase clocks;a front successive-approximation analog-to-digital converter (SAR ADC) electrically coupled to the clock circuit, and configured to convert an analog input signal into p groups of higher bits of a digital output signal in response to different time periods according to the p multi-phase clocks; anda plurality of rear SAR ADCs each electrically coupled to the clock circuit and the front SAR ADC, and configured to receive the analog input signal and one of p groups of higher bits corresponding to each other in response to the different time periods according to the p multi-phase clocks, wherein the number of the plurality of rear SAR ADCs equals the number of phases of the p multi-phase clocks, so that the plurality of rear SAR ADCs convert the analog input signal into p groups of lower bits of the digital output signal corresponding to the time period of the p groups of higher bits; anda combining circuit electrically coupled to the clock circuit, the front SAR ADC and the rear SAR ADCs, and configured to receive the p multi-phase clocks and combine the p groups of higher bits and the p groups of lower bits that correspond to the same time period according to the p multi-phase clocks, so as to generate the digital ...

SUB-RANGING ANALOG TO DIGITAL CONVERTER

Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output. 1. A system for assigning a digital value to a current or voltage signal level , the system comprising:a coarse ADC block for receiving an input signal and for performing a coarse analog-to-digital conversion process on said input signal; anda delay block for delaying said input signal prior to passing said input signal to a further processing block that is configured based on an output of said coarse ADC block;wherein said delay block delays said input signal to allow said further processing block to be configured by said output of said coarse ADC block and wherein said coarse analog-to-digital conversion process is applied over a full input signal range.2. The system according to claim 1 , wherein said further processing block is a fine ADC block for receiving said input signal from said delay block claim 1 , said fine ADC block being for performing a fine analog-to-digital conversion process on said input signal claim 1 , said fine analog-to-digital conversion process being focused around a voltage level of said input signal.3. The system according to claim 1 , wherein said further processing block is a signal ...

A/d conversion device

An A/D conversion device, which operates in one mode including at least one of a ΔΣ mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.

SYSTEM AND METHODS FOR MIXED-SIGNAL COMPUTING

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes. 1. An integrated circuit comprising:a signal source that sources one or more signals to an array of local signal sources, wherein a distinct one local signal source of the array of local signal sources is arranged in electrical communication with a pair of electrical conduits; (i) determines a summed difference current value between electrical current values of the pair of electrical conduits; and', '(ii) computes a binary output value based on the summed difference current value., 'a circuit that2. The integrated circuit according to claim 1 , wherein a control circuit that sources to or sinks from each electrical conduit of the pair of electrical conduits an electrical current value; and', 'sets a target voltage condition between the pair of electrical conduits based on the electrical current value., 'the circuit comprises3. The integrated circuit according to claim 2 , whereinthe control circuit generates the electrical current value based on a measured voltage value of the pair of electrical conduits.4. The integrated circuit according to ...

ANALOG TO DIGITAL CONVERTER WITH CURRENT STEERING STAGE

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values. 1. An analog-to-digital converter (ADC) , comprising:an input terminal configured to receive an analog input voltage;a first MDAC stage including a first sub-ADC stage coupled to the input terminal and configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to the analog input voltage in response to a second phase clock signal, and a current steering DAC stage connected to the input terminal and the output terminal of the first sub-ADC stage, the current steering DAC stage including a transconductance amplifier (Gm) and a current steering digital to analog converter (DAC), the transconductance amplifier configured to sample the analog input voltage in response to the first phase clock signal and convert the analog input voltage to a first current signal, the current steering DAC configured to convert the first digital value to a second current signal, the current steering DAC stage configured to determine a residue current signal representing a difference between the first current ...

DIGITAL CORRELATED DOUBLE SAMPLING CIRCUITS AND IMAGE SENSORS INCLUDING THE SAME

A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code. 1. A digital correlated double sampling (CDS) circuit comprising:a first latch circuit configured to latch an input phase shift code based on a first control signal to sequentially store a first phase shift code and a second phase shift code, the first phase shift code representing a reset component, the second phase shift code representing an image component;a first converting circuit configured to convert the first phase shift code and the second phase shift code into a first Gray code and a second Gray code, respectively;a second converting circuit configured to convert the first Gray code and the second Gray code into a first binary code and a second binary code, respectively;a second latch circuit configured to latch an output of the second converting circuit based on a second control signal to store the first binary code; anda calculating circuit configured to subtract the reset component from the image component based on the first binary code and the second binary code to generate a third binary code, and to sequentially output the third binary code, the third binary code representing an effective image ...

ANALOG TO DIGITAL CONVERTER

An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal. 1. An analog-to-digital converter (“ADC”) , comprising:an input terminal configured to receive an analog input voltage signal;a first ADC stage coupled to the input terminal and configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal;an amplifier receiving the analog residue signal output by the first ADC stage, wherein the amplifier is configured to apply a predetermined gain to the analog residue signal and output the amplified analog residue signal;a second ADC stage coupled to the amplifier to receive the amplified analog residue signal, and configured to convert the amplified analog residue signal to a second digital value;at least one of the first ADC stage and the second ADC stage including a first sub- ...

ANALOG TO DIGITAL CONVERTER

An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal. 1. An analog-to-digital converter (“ADC”) , comprising:an input terminal configured to receive an analog input voltage signal;a first ADC stage coupled to the input terminal and configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal;the first ADC stage including a first sub-stage coupled to the input terminal and configured to convert the analog input signal to a first number of bits of the first digital value;the first ADC stage including a second sub-stage coupled to the input terminal and configured to convert the analog input signal to a second number of bits of the first digital value, the second sub-stage configured to output the analog residue signal;a second ADC stage coupled to the first ADC stage and ...

ANALOG TO DIGITAL CONVERTER

An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal. 1. An analog-to-digital converter (“ADC”) , comprising:an input terminal configured to receive an analog input voltage signal;a first ADC stage coupled to the input terminal and configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal;a second ADC stage coupled to the first ADC stage and configured to convert the analog residue signal to a second digital value, wherein the second ADC stage includes a first sub-stage configured to convert the analog residue signal to a first number of bits of the second digital value representing the analog reside signal, and a second sub-stage configured to convert the analog residue signal to a second number of bits of the second digital value, where the second number of bits is ...

SYSTEM AND METHODS FOR MIXED-SIGNAL COMPUTING

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes. 1. An integrated circuit comprising: (i) accumulates a plurality of distinct analog signals from an analog signal source;', '(ii) performs one or more summation operations using the plurality of distinct analog signals based on an encoding scheme of the analog signal source; and', '(iii) outputs an aggregated analog signal comprising a sum of the plurality of distinct analog signals; and, 'analog signal accumulator thatanalog processing circuitry that performs weighted computations based on the aggregated analog signal.2. The integrated circuit according to claim 1 , wherein:the analog signal source comprises a binary-weighted digital-to-analog converter; andthe plurality of distinct analog signals comprises a plurality of binary-weighted analog signals.3. The integrated circuit according to claim 1 , wherein:the analog signal source comprises an N-bit digital-to-analog converter (DAC);N is a number of bits that the N-bit DAC produces over N clock cycles; andthe analog signal accumulator completes the one or more summation operations during the ...

Digital readout method and apparatus

Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and in combination with a sensor array, forms a digital focal plane array

SYSTEM AND METHODS FOR MIXED-SIGNAL COMPUTING

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes. 1. An integrated circuit comprising:a signal source that sources one or more signals to a plurality of signal sources, wherein a distinct one signal source of the plurality of signal sources is arranged in electrical communication with one or more electrical conduits; (i) identifies current values along the one or more electrical conduits; and', '(ii) computes a binary output value based on the current values along the one or more electrical conduits., 'a circuit that2. The integrated circuit according to claim 1 , further comprising:an integrator that sums the one or more signals based on the binary output value.3. The integrated circuit according to claim 1 , whereinthe distinct one signal source includes an integrator circuit that sums the one or more signals based on an input of the binary output value.4. The integrated circuit according to claim 1 , further comprising:an integrator that increments or decrements a charge on a capacitor or a storage device based on the binary output value.5. The integrated circuit according to claim 1 , ...

Reference precharge techniques for analog-to-digital converters

Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.

Analog to digital converter for solid-state image pickup device

There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.

A/D CONVERTER

An input signal Vin is sampled, when a first terminal of a sampling capacitor is connected to a node and a second terminal of the sampling capacitor is connected to an analog ground. A charge transfer operation is performed, when the first terminal of the sampling capacitor is connected to the analog ground and the second terminal of the sampling capacitor is connected to an inverting input terminal of an operational amplifier. A quantization is performed, when an output of the operational amplifier is input to a quantizer. Most significant bits are generated by repeating a subtraction operation in which a charge subtraction unit subtracts a charge accumulated in the integration capacitor based on a quantization result a predetermined number of times. Least significant bits are generated when a voltage provided by amplifying a voltage corresponding to a charge remaining in the integration capacitor is input to a sub-A/D converter after generation of the most significant bits. A sum of the most significant bits and the least significant bits are output as an output signal. Initialization of the charge of the integration capacitor, the charge transfer operation for a next A/D conversion, and generation of the most significant bits are performed in parallel with the A/D conversion in the sub-A/D converter after the generation of the most significant bits. 1. An A/D converter for converting an analog signal applied as an input signal to a digital value , the A/D converter comprising:a sampling capacitor for sampling the analog signal;an integrator including an operational amplifier and an integration capacitor provide between a first input terminal and an output terminal of the operational amplifier;a quantizer for outputting a quantization result provided by quantizing an output signal of the operational amplifier;a charge subtraction unit including a D/A converter that determines a DAC voltage for subtracting a charge of the integration capacitor based on the ...

ANALOG TO DIGITAL CONVERTER STAGE

A stage, suitable for use in an analog to digital converter or a digital to analog converter where the stage comprises a plurality of slices that can be operated together to form a composite output, can have reduced thermal noise, whilst each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. 120-. (canceled)21. A digital to analog converter (DAC) arrangement for utilization within a converter , comprising:a first DAC slice to receive a signal via an input line of the first DAC slice, the first DAC slice having a first resistor coupled in series on the input line of the first DAC slice, wherein a value of the first resistor is selected to reduce a thermal noise of the first DAC slice; anda second DAC slice coupled in parallel with the first DAC slice, the second DAC slice to receive the signal via an input line of the second DAC slice, the second DAC slice having a second resistor coupled in series on the input line of the second DAC slice, wherein a value of the second resistor is selected to reduce a thermal noise of the second DAC slice.22. The DAC arrangement of claim 21 , wherein a first analog representation output by the first DAC slice is formed as a function of a first sampled input voltage sampled by the first DAC slice and a first digital word applied to the first DAC slice claim 21 , and wherein the second analog representation output by the second DAC slice is formed as a function of a second sampled input voltage sampled by the second DAC slice and a second digital word applied to the second DAC slice.23. The DAC arrangement of claim 21 , wherein the first DAC slice has a first time constant claim 21 , and wherein the second DAC slice has a second time constant claim 21 , the second time constant within a threshold value of the first time constant.24. The DAC arrangement of claim 23 , wherein the first ...

BIT ERROR RATE TIMER FOR A DYNAMIC LATCH

A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions. 1. A converter system , comprising:a first converter that digitizes the a first portion of an input signal, the first converter including a comparator;a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator;a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer; anda combiner having inputs to generate a digital code from the digitized first and second portions.2. The converter according to claim 1 , wherein the timer includes an output terminal coupled to a first voltage supply by a pair of series-connected transistors and coupled to second supply voltage by a pair of parallel-connected transistors.3. The converter according to claim 2 , wherein the timer is a NAND gate having its inputs connected together.4. The converter according to claim 2 , wherein the timer is a NOR gate having its inputs connected together.5. The converter according to claim 1 , wherein circuit components the timer and the comparator have are approximately equal trans-conductance in ratio to their respective output capacitances.6. The converter according to claim 1 , wherein the transistors in the timer and the latch have approximately equal drive strength in ratio to their ...

Programmable trim filter for successive approximation register analog to digital converter comparator

The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

Semiconductor Device

A semiconductor device having an analog/digital conversion circuit converting an analog signal to a digital signal, includes a holding circuit outputting an analog signal having a value according to a value of an analog signal supplied in a first period; and a prediction circuit generating a first digital signal based on bit position information from a prediction table corresponding to the supplied analog signal.

Two-Stage Analog-To-Digital Converter For High-Speed Image Sensor

The present invention relates to a two- or multiple-stage analog to digital converter. The converter preferably includes an incremental ADC in the first stage. The incremental ADC comprises an integrator and a comparator. After the predefined number of comparisons performed by the comparator, the output of the integrator appropriately scaled is provided to the second stage where it is further sampled. In particular, the scaling gain is inversely proportional to the integrator gain. The second ADC performs the conversion of the remaining least significant bits and then the output of both stages is combined. Moreover, a calibration and correction approaches are provided for the multi-stage ADC. 115-. (canceled)16. An analog to digital converter for converting an analog signal from an image sensor to a digital value , the converter comprising:a first stage including a first analog to digital converter for obtaining a first number of bits of the digital value, the first analog to digital converter comprising an integrator with a first gain and a comparator for comparing the integrated signal with a first reference signal;an intermediate amplifier for multiplying the output of the integrator after conversion of the first number of bits in the first stage by a predetermined gain based on the first gain; anda second stage including a second analog to digital converter for obtaining a second number of bits of the digital value based on the signal input from the intermediate amplifier, wherein the second analog to digital converter is a ramp analog to digital converter and comprisesa comparator for comparing the signal input to the second analog to digital converter with a reference analog ramp signal, anda digital register for storing the digital value corresponding to the time period in which the analog ramp signal crosses the input signal.17. The analog to digital converter according to claim 16 , wherein the first analog to digital converter is an incremental analog to ...

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC. 1. A semiconductor device comprising:a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal;a first analog to digital converter (ADC) that receives the residue signal and generates a first digital representation;a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal; anda digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal,wherein the first ADC is a multi-bit Successive Approximation Register ADC using a first step voltage.2. The semiconductor device of claim 1 , wherein the second ADC is a multi-bit SAR ADC using a second step voltage less than or equal to the first step voltage.3. The semiconductor device of claim 1 , further comprising:a first node that performs a subtraction operation between the analog input signal and the feedback signal to generate the differential analog signal.4. The semiconductor device of claim 3 , wherein the loop filter further comprises:a gain block that receives the differential analog signal and performs a scaling operation on the differential analog signal to ...

PROGRAMMABLE TRIM FILTER FOR SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER COMPARATOR

The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold. 1. A converter for a successive approximation register analog to digital conversion , comprising:a capacitive network configured to store a sample of an analog signal;a plurality of comparator preamplifiers;a process monitor configured to determine a frequency response of the plurality of comparator preamplifiers; anda programmable trim filter selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with preamplifier settling time less than a preamplifier settling threshold based on the frequency response of the plurality of comparator preamplifiers.2. The converter of wherein the process monitor includes a ring oscillator.3. The converter of wherein the processor monitor is further configured to determine the frequency response of the plurality of comparator preamplifiers by determining the frequency response of the ring oscillator.4. The converter of wherein the ring oscillator includes a plurality of process monitor preamplifiers having a same configuration as the plurality of comparator preamplifiers.5. The converter of wherein the ring oscillator includes a test filter to vary capacitance applied to the process monitor preamplifiers.6. The converter of wherein the process monitor further includes a processor to measure the frequency ...

PIPELINE ANALOG-TO-DIGITAL CONVERTER

A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle. 1. A pipeline analog-to-digital converter (ADC) , comprising:a plurality of stages, wherein a first stage of the plurality of stages is adapted to receive an external analog signal and each of the plurality of stages is adapted to output an analog signal serving as an input analog signal for a next stage, wherein each odd-number-th stage and an adjacent next even-number-th stage thereof form a periodic unit;a first capacitor network and a second capacitor network for each periodic unit, the first and second capacitor networks both coupled to a corresponding periodic unit and having an identical structure;a first clock signal and a second clock signal inverted in phase and both coupled to each periodic unit, wherein the first and second clock signals are adapted to control one of the odd-number-th and even-number-th stages of each periodic unit to operate in a sampling phase, and to control the other of the odd-number-th and even-number-th stages of each periodic unit to operate in a holding phase; anda third ...

MEMORYLESS SLIDING WINDOW HISTOGRAM BASED BIST

A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source. 1. A method for determining nonlinearity characteristics of an analog-to-digital converter (ADC) , comprising:incrementally supplying an input analog voltage to the ADC;determining first nonlinearity values for a first subset of digital codes generated by the ADC in response to the input analog voltage;determining second nonlinearity values for a second subset of digital codes generated by the ADC in response to the input analog voltage;incrementing one or more counters when the first and second nonlinearity values exceed nonlinearity value thresholds; anddetermining nonlinearity characteristics about the ADC based, at least in part, on the one or more counters.2. The method of claim 1 , wherein the first and second nonlinearity values comprise differential nonlinearity (DNL) values.3. The method of claim 2 , further comprising calculating integral nonlinearity (INL) values for each code in the subset based on the DNL values and incrementing the one or more counters based on the INL values exceeding an INL maximum or being less than an INL minimum.4. The method of claim 3 , wherein the DNL values are ...

ANALOG TO DIGITAL CONVERTER STAGE

A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance. 1. A stage of an analog to digital converter , comprising:an analog to digital converter coupled to an acquisition circuit having a first time constant; anda plurality of circuits, each comprising an acquisition circuit having substantially the same time constant as the first time constant and a digital to analog converter for receiving a respective control signal based on a digital output of the analog to digital converter and for forming a difference signal as a difference between a sampled voltage held by the acquisition circuit and the digital to analog converter output.2. The stage according to claim 1 , in which respective control signals to the digital to analog converters are variable.3. The stage according to claim 1 , in which at least two outputs of the plurality of circuits are combined.4. The stage according to claim 1 , in which the acquisition circuits of the plurality of circuits are sampling capacitor digital to analog converters.5. The stage according to claim 1 , wherein the analog to digital converter comprises a switched capacitor array forming a first sampling digital to analog converter.6. The stage according to claim 5 , in which each of the plurality of circuits comprise a switched capacitor array forming further sampling digital to analog converters claim 5 , matched to the first sampling digital to analog converter.7. The stage according to claim 6 , in which the sampling digital to analog converters of the plurality of circuits are formed from a plurality of unit cells.8. The stage according to claim 1 ...

Analog-to-digital converter and an image sensor including the same

An analog-to-digital converter includes a modulator, a controller, and a digital filter. The modulator generates a modulated signal based on an analog signal. The controller generates a weight control signal. The digital filter includes a weight signal generator and a first integrator. The weight signal generator generates a weight signal based on the weight control signal. The first integrator generates a digital signal corresponding to the analog signal by integrating the weight signal in response to the modulated signal. The weight control signal corresponds to a type and an order of the digital filter.

Analog-to-digital converter and solid-state imaging apparatus

An analog-to-digital (AD) converter has a latch section having latch units, a capacitor, and a latch control signal line connected to the latch units. A third voltage less than a first voltage and greater than a second voltage is applied as a power supply voltage to the latch units. When the capacitor is electrically connected to the latch control signal line, a potential of the latch control signal line becomes greater than or equal to the third voltage. Only when the electrical connection between the capacitor and the latch control signal line is disconnected, the first voltage is applied to the capacitor and the second voltage is applied to the latch control signal line. When the potential of the latch control signal line becomes greater than or equal to the third voltage, the latch units latch clock signals.

SYSTEM AND METHODS FOR MIXED-SIGNAL COMPUTING

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes. 1. An integrated circuit comprising:an array of distinct pairs of tunable resistors arranged along a pair of electrical conduits;a binary reference signal source that sources one or more signals to an array of local signal sources, wherein a distinct one local signal source of the array of local signal sources is arranged in electrical communication with the pair of electrical conduits; (i) changes a differential current value between the pair of electrical conduits based on the one or more signals from the binary reference signal source;', '(ii) determines a summed difference current value between the electrical current values of the pair of electrical conduits; and', '(iii) computes a binary output value based on the summed difference current value., 'a readout circuit that2. The integrated circuit according to claim 1 , wherein a common-mode control circuit that sources to or sinks from each electrical conduits of the pair of electrical conduits a common current value; and', 'sets a target voltage condition between the pair of electrical ...

MASSIVELY PARALLEL THREE DIMENSIONAL PER PIXEL SINGLE SLOPE ANALOG TO DIGITAL CONVERTER

An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.

較正機能付きａ／ｄ変換器

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Analog-to-digital conversion circuit and method for converting analog signals to digital signals in data acquisition systems

고속도, 고해상도, 타임-시프트 2단계 아날로그-디지틀 변환(ADC)은 조 및 정밀 신호 변환들 모두에 대해 단지 하나의 ADC 모듈을 이용한다. 동일의 ADC 모듈은 이후의 보정 처리를 위해 변환 에러를 방생시키도록 ACD가 보다 늦은 정밀 신호 변환을 완료하기까지 그 저장된 출력 신호와 함께 조악 신호 변환에 대해 우선 사용된다. 다음으로 2 두 개의 신호들이 변환 에러를 보정하도록 처리하는 디지틀 신호를 사용함으로써 처리된 후, 디지틀 신호가 발생된다. High speed, high resolution, time-shift two-stage analog-to-digital conversion (ADC) utilizes only one ADC module for both coarse and precision signal conversions. The same ADC module is first used for coarse signal conversion with its stored output signal until the ACD completes the later fine signal conversion to generate conversion errors for later correction processing. Next, after the two two signals are processed by using a digital signal that processes to correct the conversion error, a digital signal is generated.

Ａｄ変換回路

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A / D converter

Device for transferring data in a image sensor and method for transferring data thereof

본 발명은, 이미지 센서에 관한 것이다. 본 발명에서는, 단위 화소에서 광전 변환된 아날로그 신호를 다수의 비트로 구성된 디지털 신호로 변환하는 컨버터와,상기 컨버터로부터의 출력 신호를 제어 신호에 응답하여 비트 별로 선택적으로 출력하고, 다수의 스위칭 회로가 직렬로 연결되는 데이터 이송부와, 상기 데이터 이송부에서 출력된 데이터를 저장하는 메모리를 포함하는 이미지 센서가 개시된다.

Flash type a/d converter

본 발명은 단순한 구성으로 고속의 아나로그-디지탈 변환이 가능하도록 된 플래시형 아날로그-디지탈 변환기에 관한 것으로서, 입력신호에 대한 레벨 판정범위의 1/2의 기준값을 갖고, 입력신호가 기준값 이상인지 이하인지를 판정하는 제1비교수단과, 이 제1비교수단에 의한 비교결과 데이터를 근거로 출력될 디지탈 데이터의 최상위 비트를 생성하는 제1인코더수단, 상기 제1비교수단에 의해 1/2 이상으로 판정된 경우에는 입력신호에 대해 상기 1/2의 기준값을 감가산하는 가산수단, 이 가산수단으로부터 출력되는 신호의 레벨을 판정하기 위한 적어도 2개 이상의 제2비교수단 및, 이 제2비교수단의 비교결과 데이터를 근거로 상기 최상위 비트를 제외한 나머지 출력데이터를 생성하는 제2인코더수단을 포함하여 구성된 것을 특징으로 한다. The present invention relates to a flash type analog-to-digital converter capable of high-speed analog-to-digital conversion in a simple configuration and has a reference value of 1/2 of a level determination range for an input signal, A first encoder means for generating a most significant bit of digital data to be output on the basis of the comparison result data by the first comparison means, At least two second comparison means for determining the level of the signal output from the addition means, and a second comparing means for comparing the second comparison means with the second comparison means, And second encoder means for generating output data excluding the most significant bit based on the comparison result data.

Time shift two-step analog to digital converter

A method of and apparatus for high speed, high resolution, time-shift two-step analog-to-digital conversion (ADC) employing only one ADC module for both coarse and fine signal conversions. The same ADC module is used first for the coarse signal conversion with its output signal stored until the ADC completes the slower fine signal conversion to generate the conversion error for the subsequent compensation process. A digital signal is then generated after the two signals are processed by using a digital signal processing to compensate for conversion error.

METHOD AND SYSTEM FOR BROADBAND AND HIGH DYNAMIC ANALOGUE / DIGITAL CONVERSION

La présente invention concerne un procédé de conversion analogique/numérique d'un signal analogique (SA) en un signal numérique (SN) qui est caractérisé en ce qu'il comporte au moins une étape de numérisation intermédiaire et une étape de numérisation finale comportant une sous-étape (SENi) de numérisation des seules composantes fréquentielles d'un signal analogique (SAi), dit signal analogique à traiter à l'étape d'ordre i, ayant des niveaux de puissance qui sont compris entre une valeur supérieure Nimax et une valeur de seuil Si associées à ladite étape de numérisation intermédiaire (ENi), ladite sous-étape (SENi) délivrant un signal numérique (SNi), et une sous-étape (SEEi) d'extraction dudit signal analogique à traiter (SAi) d'ordre i les composantes fréquentielles numérisées pour délivrer ainsi un signal analogique à traiter (SAi+1) pour l'étape de numérisation intermédiaire ou finale (ENi+1) d'ordre suivant, et une étape de combinaison (EC). La présente invention concerne également un système de conversion analogique/numérique pour mettre en œuvre ledit procédé de conversion. The present invention relates to a method for analog / digital conversion of an analog signal (SA) into a digital signal (SN) which is characterized in that it comprises at least one intermediate digitization stage and a final digitization step comprising a sub-step (SENi) for digitizing the only frequency components of an analog signal (SAi), said analog signal to be processed at the step of order i, having power levels which are between a higher value Nimax and a threshold value Si associated with said intermediate digitizing step (ENi), said substep (SENi) delivering a digital signal (SNi), and a substep (SEEi) for extracting said analog signal to be processed (SAi) d order i digitized frequency components to thereby provide an analog signal to be processed (SAi + 1) for the next intermediate or final digitization step (ENi + 1), and a combination ...

IMPROVEMENTS TO ANALOGUE-DIGITAL CONVERTERS

L'invention concerne des perfectionnements aux convertisseurs analogique-numérique. L'objet de l'invention est un dispositif de conversion analogique-numérique qui se compose de plusieurs étages de conversion analogique-numérique branchés est converti en un signal numérique se composant de plusieurs bits, caractérisé en ce qu'un étage de conversion d'ordre très inférieur faisant partie du groupe d'étages de conversion analogique-numérique comprend au moins un comparateur comparant un signal analogique d'entrée respectif avec au moins un niveau de référence respectif en relation avec un niveau moyen dudit signal analogique d'entrée respectif afin de former un signal analogique de sortie correspondant audit signal analogique d'entrée. Application aux convertisseurs analogique-numérique à haute résolution. The invention relates to improvements to analog-to-digital converters. The object of the invention is an analog-to-digital conversion device which consists of several connected analog-to-digital conversion stages is converted into a digital signal consisting of several bits, characterized in that a conversion stage of much lower order being part of the group of analog-to-digital conversion stages comprises at least one comparator comparing a respective input analog signal with at least a respective reference level in relation to an average level of said respective input analog signal in order to form an analog output signal corresponding to said analog input signal. Application to high resolution analog-to-digital converters.

BROADBAND AND HIGH DYNAMIC ANALOG / DIGITAL CONVERSION METHOD AND SYSTEM

La présente invention concerne un procédé de conversion analogique/numérique d'un signal analogique (SA) en un signal numérique (SN) qui est caractérisé en ce qu'il comporte au moins une étape de numérisation intermédiaire et une étape de numérisation finale comportant une sous-étape (SENi) de numérisation des seules composantes fréquentielles d'un signal analogique (SAi), dit signal analogique à traiter à l'étape d'ordre i, ayant des niveaux de puissance qui sont compris entre une valeur supérieure Ni max et une valeur de seuil Si associées à ladite étape de numérisation intermédiaire (ENi), ladite sous-étape (SENi) délivrant un signal numérique (SNi), et une sous-étape (SEEi) d'extraction dudit signal analogique à traiter (SAi) d'ordre i les composantes fréquentielles numérisées pour délivrer ainsi un signal analogique à traiter (SAi+1) pour l'étape de numérisation intermédiaire ou finale (ENi+1) d'ordre suivant, et une étape de combinaison (EC). La présente invention concerne également un système de conversion analogique/numérique pour mettre en œuvre ledit procédé de conversion. The present invention relates to a method of analog / digital conversion of an analog signal (SA) into a digital signal (SN) which is characterized in that it comprises at least one intermediate digitization step and a final digitization step comprising a sub-step (SENi) of digitizing only the frequency components of an analog signal (SAi), said analog signal to be processed in step of order i, having power levels which are between a higher value Ni max and a threshold value Si associated with said intermediate digitization step (ENi), said sub-step (SENi) delivering a digital signal (SNi), and a sub-step (SEEi) for extracting said analog signal to be processed (SAi) of order i the frequency components digitized to thereby deliver an analog signal to be processed (SAi + 1) for the intermediate or final digitization step (ENi + 1) of the following order ...

Patent FR2374778B1

SUBTRACTOR-AMPLIFIER CIRCUIT FOR A DIGITAL CASCADE ANALOG CONVERTER

METHOD FOR REALIZING ANALOGUE / DIGITAL CONVERSION OF SIGNALS, CONVERTER USING THE SAME, AND DEVICE FOR DETECTING ELECTROMAGNETIC RADIATION INTEGRATING SUCH CONVERTER

Analog-to-digital converter and sensor device comprising such a converter

The present invention relates to a periodically integrating analog-to-digital converter and a sensor device comprising such a converter. The analog-to-digital converter comprises a measured-value-to-pulse-amount converter, i.e. a sigma-delta converter of the first order that is reset to zero before each new period, and a digital counter for the number of feedback signals of known reference value in the measured-value-to-pulse-amount converter. This constitutes a rough measure of the input signal. It further comprises an analog-to-digital converter which converts the residual value of the measured-value-to-pulse-amount converter at the end of the period to a digital value, and an adder which adds this value to the output signal from the digital counter, resulting in a more accurate measure of the input signal.

Reservoir capacitor based analog-to-digital converter

Techniques to use reservoir capacitors in ADC to supply most of the charge to bit-trial capacitors as bit-trials are performed. An accurate reference voltage source, e.g., a reference buffer circuit, only needs to supply the difference, e.g., an inaccuracy, in the charge supplied by the reservoir capacitors. Instead of having to resettle for each bit-trial, the accurate reference voltage source has only to deliver the initial charge to the reservoir capacitors during acquisition and once more when the ADC is ready to sample onto the residue amplifier. These techniques can ease the demands on the reference buffer circuit and requirement of external decoupling capacitors, for example.

Sub-ranging analog to digital converter

Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output.

Analog-digital converter, solid-state imaging device using the same, and driving method thereof

Least recently used ADC

During the last 75 years Analog to Digital converters revolutionized the signal processing industry. As transistor sizes reduced, higher resolution of bits is achieved. But FLASH and other full blown faster ADC implementations always consumed relatively higher power. As the analog signal comes into ADC frontend, conversion is initiated from the beginning. ADC conversion process is a highly mathematical number system problem, especially FLASH ADCs are. With faster, low power, and partitioned ADCS, better solutions can be built in so many vast expanding signal processing fields. It is time to come up with logical ADCS instead of brute force, start from the beginning conversion for every sample of analog signal. When the signal does not change abruptly, there is room for applying CACHE principles as it is done in this invention! The approach is to use a smaller ADC for full blown start from the beginning conversions and store it in upfront signal path as CACHED value. Then start using that Cached value set. There must be a balance between number of Cache entries, consumed power, and backend full blown ADC. It is obvious, backend ADC is rarely engaged in conversion when there are too many cache hits, which is desirable.

Analog-digital converter

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High speed analog-to-digital converter

A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells (Cci) which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

ANALOG-DIGITAL CONVERTER, SOLID SOLUTION FOR CAPTURE OF THE IMAGE AND METHOD OF ITS EXCITATION, AND ELECTRONIC DEVICE

1. Аналого-цифровой (АЦ) преобразователь, содержащий:секцию сравнения для сравнения опорного напряжения с входным напряжением, причем опорное напряжение имеет пилообразную форму, причем значение напряжения изменяется во времени;секцию хранения для хранения значения счета в предопределенной счетной последовательности на основании выходного сигнала от секции сравнения;секцию преобразования для преобразования значения счета в счетной последовательности, хранящейся в секции хранения, в двоичные данные; исекцию подачи для подачи импульсного сигнала, соответствующего двоичным данным, полученным при преобразовании в секции преобразования, на первый счетчик.2. АЦ преобразователь по п.1, в котором секция хранения выполнена с возможностью подачи на второй счетчик сигнала наиболее значимого бита, представляющего собой наиболее значимый бит значения счета в счетной последовательности пока не инвертирован выходной сигнал, подаваемый секцией сравнения, и хранения младших битов, менее значимых, чем наиболее значимый бит значения счета в счетной последовательности при инвертировании выходного сигнала от секции сравнения.3. АЦ преобразователь по п.2, в которомсекция преобразования выполнена с возможностью преобразования младших битов значения счета в счетной последовательности в двоичные данные, асекция подачи выполнена с возможностью подачи, на первый счетчик, импульсного сигнала, соответствующего значению каждого бита в двоичных данных опорного сигнала, в качестве опорного импульсного сигнала.4. АЦ преобразователь по п.3, в которомопорный сигнал представляет собой импульсный сигнал, сконфигурированный из n ч РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК H04N 5/378 (13) 2013 143 173 A (2011.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ЗАЯВКА НА ИЗОБРЕТЕНИЕ (21)(22) Заявка: 2013143173/08, 23.03.2012 (71) Заявитель(и): СОНИ КОРПОРЕЙШН (JP) Приоритет(ы): (30) Конвенционный приоритет: 30.03.2011 JP 2011-075959 (85) Дата начала рассмотрения заявки PCT на национальной фазе: ...

Analog to digital converter

The invention relates to an analog-to-digital converter comprising a reference voltage generating circuit, two coarse/fine comparators and two encoders for encoding the comparison result of the two coarse/fine comparators. In the invention, the two coarse/fine comparators processes a coarse comparison procedure and a fine comparison procedure on an input voltage in different clock cycle, thus, a sampling voltage error caused by an error of sampling time decreases. In another aspect of the invention, the capacitance of the input capacitor of the analog-to-digital converter decreases because the comparators for coarse comparison and fine comparison are the same, thus, a large power amplifier is not required for driving the input capacitor.

Analog-to-digital converter and sensor device comprising such a converter

Reducing residue signals in analog-to-digital converters

A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to the digital output from the quantizer to generate a digital input to a feedforward DAC, based on which the DAC can generate a feedforward path analog output. The apparatus further includes means for applying a second, continuous-time, transfer function to the analog input provided to the quantizer to generate a forward path analog output, and a subtractor for generating a residue signal based on a difference between the forward path analog output and the feedforward path analog output. Proposed apparatus allows selecting a combination of the first and second transfer functions so that, when each is applied in its respective path, the residue signal passed to further stages of an ADC is reduced.

A-to-D Converter of the successive-approximation type

An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I 2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Analog to digital converter, image sensor having the same, and method of converting analog to digital

아날로그 투 디지털 컨버터는 선택 제어 신호에 기초하여 기준 전압들 중에서 하나를 선택하여 선택 기준 전압으로 출력하는 기준 전압 선택부, 선택 기준 전압, 픽셀 출력 전압, 램프 초기 전압 및 램프 전압을 비교하여 비교 결과 신호를 생성하는 멀티 입력 비교부, 및 비교 결과 신호 및 비교 모드 신호에 기초하여 선택 제어 신호를 생성하는 선택 제어 신호 생성부를 포함한다. 따라서, 아날로그 투 디지털 컨버터는 하나의 램프 전압을 이용하면서도 코스 비교 모드와 파인 비교 모드의 이중 모드로 아날로그 신호에 상응하는 디지털 신호를 생성할 수 있다. The analog-to-digital converter compares the selected reference voltage, the pixel output voltage, the lamp initial voltage, and the ramp voltage to select one of the reference voltages based on the selection control signal and output it as a selected reference voltage, And a selection control signal generator for generating a selection control signal based on the comparison result signal and the comparison mode signal. Accordingly, the analog-to-digital converter can generate a digital signal corresponding to an analog signal in a dual mode of the course comparison mode and the fine comparison mode, while using one lamp voltage.

Two stage a/d converter utilizing dual multiplexed converters with a common successive approximation control.

Convertisseur comprenant un convertisseur numérique/analogique pair et un convertisseur numérique/analogique impair pour convertir des signaux numériques provenant d'un convertisseur analogique/numérique ou d'un circuit d'approximation successive, et pour commander les convertisseurs impair et pair et le convertisseur analogique/numérique dans le but d'obtenir une conversion alternative par les convertisseurs pair et impair. Les convertisseurs impair et pair fonctionnent en opposition de phase de sorte que pendant que l'un est en phase d'acquisition, l'autre est en phase de conversion. Chacun des convertisseurs impair et pair comprend un convertisseur numérique/analogique approximatif séparé et un convertisseur numérique/analogique de précision commun. Le circuit de comande remet à l'état initial le convertisseur numérique/analogique de précision durant une partie initiale de la phase de conversion de chacun des convertisseurs numériques/analogiques approximatifs. Dans un convertisseur rapide à deux étages, le premier étage comprend un seul convertisseur analogique/numérique et le second étage comprend un seul convertisseur numérique/analogique ainsi que des convertisseurs analogiques/numériques à fonctionnement alternatif pair et impair. Converter comprising an even digital-to-analog converter and an odd digital-to-analog converter for converting digital signals from an analog-to-digital converter or a successive approximation circuit, and for controlling the odd and even converters and the analog converter /numeric in order to obtain an alternative conversion by the even and odd converters. The odd and even converters operate in phase opposition so that while one is in the acquisition phase, the other is in the conversion phase. Each of the odd and even converters includes a separate coarse D/A converter and a common precision D/A converter. The control circuit resets the precision digital-to-analog converter during an initial part ...

Analog-to-digital converter and sensor device comprising such a converter

Multistep analog-to-digital converter with error correction

A sub-ranging analog-to-digital converter includes, in cascade, a coarse converter, a digital-to-analog converter, a subtracter circuit and a fine converter. Errors of the coarse converter are detected in the fine converter by means of an overflow detector and an underflow detector which generate an overflow signal (OF) and an underflow signal (UF), respectively. The digital output (D A ) of the coarse converter is corrected by first subtracting one LBS in a decoder and then, in response to the overflow and underflow signal, adding thereto zero, one or two LBSs.

Analog-to-digital converter

Analog-to-Digital Converter (A/D converter) consisting of several continuously integrating charge balancing (CB) conversion stages. During each conversion interval, all CB capacitors are discharged by a reference current. In each stage, the end of the discharge of the CB capacitor is detected by a zero crossing detector. Time intervals between the zero crossing events and corresponding discharge termination events represent time equivalents of quantization errors. Each stage, other than the first, converts the time equivalents of quantization errors of the previous stage. Output of the entire multistage A/D converter is combined from the outputs of all stages in a way which provides compensation of a quantization error of any stage by the output of the next stage. Quantization noise (sequence of quantization errors) of the entire A/D converter becomes the same as the N-time differenced (N-number of stages) quantization noise of the last stage. The differencing shapes spectral density of quantization noise in such a way that the largest portion of the noise energy becomes shifted outside of the signal bandwidth. The larger the number of stages, the smaller the in-band portion of the quantization noise. The out-of-band portion of quantization noise can be filtered out in the post-conversion digital signal processing.

Semiconductor device and operating method thereof

A semiconductor device includes; a loop filter that receives a differential analog signal and generates a residue signal indicating an error between an analog input signal and an feedback signal, a first ADC that receives the residue signal and generates a first digital representation, a second ADC that receives the analog input signal and generates a second digital representation corresponding to the analog input signal, and a digital to analog converter (DAC) that receives a sum of the first digital representation and the second digital representation and generates the analog feedback signal. At least the first ADC is a multi-bit Successive Approximation Register ADC.

Three-step circulation-type analog-digital (A/D) converter, carries out third operational step for adjustment of group capacitors charge

A three-step analog-to-digital (A/D) circulation- type converter includes an A/D conversion circuit and a capacitor group-circuit comprised of a number of group capacitors (C1-C7) with each group capacitor having a group electrode which is connected to the group signal line (5). During the third, or subsequent step of the A/D converter, a charge adjustment of each of the group capacitors (C1-C7) takes place on the basis of the output voltage of an op.amp. (3) by closing the second switching network (S11) when the first switching network (S10) is open, followed by initialization the integration capacitor (CF) through an integration-initialization circuit.

Touch apparatus and analog-to-digital converting apparatus and method thereof

Analog-to-digital converter comprising a sigma-delta modulator

The invention relates to an analog-to-digital converter (ADC) comprising at least two quantization stages (stage 1, stage 2,..., stage N-1, SDM), wherein the final quantization stage (SDM) of said analog-to-digital converter (ADC) comprises a sigma-delta modulator (SDM).

analog-digital converting apparatus and converting method thereof

본 발명은 아날로그 신호를 디지털 신호로 변환 시 요구되는 변환 시간을 단축하여 좀 더 빠른 시간 내에 변환이 가능하도록 한 아날로그-디지털 변환 장치 및 변환 방법을 제공하기 위한 것으로, 이를 위해 본 발명의 아날로그-디지털 변환 장치는, 각각 두비트의 제1, 제2 및 제3 디지털 신호를 저장하는 제1, 제2 및 제3 특수 레지스터(SAR); 각기 상기 제1, 제2 및 제3 특수 레지스터(SAR)의 출력에 접속되어 상기 제1, 제2 및 제3 디지털 신호를 제1, 제2 및 제3 아날로그 기준신호로 변환하는 제1, 제2 및 제3 디지털-아날로그 변환기(DAC); 각각 제1, 제2 및 제3 디지털-아날로그 변환기(DAC)의 출력에 접속되어 제1, 제2 및 제3 아날로그 기준신호와 변환하고자 입력되는 아날로그 입력 신호를 비교하여 제1, 제2 및 제3 비교 결과 신호를 출력하는 제1, 제2 및 제3 비교기; 및 제1, 제2 및 제3 비교 결과 신호에 응답하여 한 사이클에 상기 제1, 제2 및 제3 특수레지스터에 저장된 디지털 신호의 두 비트 신호를 변환하는 변환 제어 수단을 포함하여, N비트의 아날로그신호를 N/2 사이클에서 변환하는 것을 특징으로 한다. The present invention is to provide an analog-to-digital conversion device and a conversion method for converting an analog signal into a digital signal required to shorten the conversion time in a faster time, the analog-digital of the present invention The conversion device comprises: first, second and third special registers SAR for storing two bits of first, second and third digital signals, respectively; First and second signals respectively connected to the outputs of the first, second and third special registers SAR to convert the first, second and third digital signals into first, second and third analog reference signals. Second and third digital-to-analog converters (DACs); The first, second and third analog reference signals respectively connected to the outputs of the first, second and third digital-to-analog converters (DACs) are compared with the analog input signals to be converted. First, second and third comparators for outputting a comparison result signal; And conversion control means for converting two bit signals of the digital signals stored in the first, second and third special registers in one cycle in response to the first, second and third comparison result signals. It converts the analog signal in N / 2 cycles.

Digitizer

High Speed High Resolution ADC Using Successive Approximation Technique

An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing various improvements. According to one aspect, another sub-ADC is used to resolve some of the bits in parallel. According to another aspect, the sub-ADC using SAP is implemented using a charge redistribution principle, while another sub-ADC does not rely on charge conservation. According to yet another aspect of the present invention, a same component operates as a comparator when the sub-ADC using SAP resolves the corresponding bits, and operates as an amplifier when the sub-ADC generates a residue signal.

ANALOG DIGITAL CONVERTER AND SUCH ANALOG DIGITAL CONVERTER USING CONTROL LOOP.

Analog to digital converter

An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.

Sensor system using multiple modes for analog to digital conversion

A device for converting analog to digital is disclosed. The device includes a dual mode converter and a control unit. The dual mode converter has a coarse mode and a fine mode. The dual mode converter is configured to receive an input signal and convert the input signal to a digital output having a selected resolution. The control unit is coupled to the dual mode converter and is configured to operate the converter in the coarse mode until a coarse approximation is obtained and to operate the converter in the fine mode until a fine approximation is obtained having the selected resolution. The fine mode includes multi-bit incremental tracking.

PARALLEL ANALOG / DIGITAL CONVERSION METHOD, DEVICE USING THE SAME, AND IMAGING DETECTOR COMPRISING SUCH A DEVICE

Digital to analog converter, image sensor having the same and method of driving image sensor

디지털 아날로그 변환기, 그를 포함하는 이미지 센싱 장치 및 이미지 센싱 장치의 구동방법에 관한 것으로, 예정된 전압레벨의 픽셀 신호를 출력하는 픽셀; 복수의 샘플링 단계에 따라 순차적으로 인에이블되며, 서로 다른 레벨만큼씩 상향 조절되거나 또는 하향 조절되는 기준전류를 생성하기 위한 복수의 전류원; 기준전류에 대응하는 램프전압을 생성하기 위한 램프전압 생성부; 및 램프전압과 픽셀 신호를 비교하기 위한 비교부를 포함하는 아날로그 디지털 변환기가 제공된다. A digital-to-analog converter, an image sensing device including the same, and a method of driving the image sensing device, the method comprising: a pixel for outputting a pixel signal having a predetermined voltage level; A plurality of current sources that are sequentially enabled according to a plurality of sampling steps and for generating a reference current that is adjusted up or down by different levels; A ramp voltage generator for generating a ramp voltage corresponding to a reference current; And a comparator for comparing the lamp voltage with the pixel signal.

Massively parallel three dimensional per pixel single slope analog to digital converter

An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through-silicon via.

High-speed high-resolution ADC for precision measurements

A measurement device such as a DMM may include four basic units—an analog circuit path, an analog to digital converter (ADC), a digital filter, and an RMS computation unit. The four basic units may be operable to multiplex or to process one or more of the plurality of channels at the same time. The analog circuit path may include the necessary circuitry for the plurality of channels to couple to one or more analog signals. The analog circuit path may couple to the ADC. The ADC may be operable to receive the one or more analog signals from the analog circuit path and convert it to one or more digital signals. The ADC may include a cascaded ADC, which may include a first ADC and a second ADC. The first and the second ADC and may be able to convert analog data to digital data during a cycle. In one embodiment, the first ADC may generate a conversion result and an error signal. The second ADC may be operable to receive the error signal, digitize the error signal, and process the error signal, thus performing noise cancellation. A summation operation may combine the data from the first ADC and the processed data from the second ADC. The cascaded ADC may consist of a continuous-time 1-bit sigma-delta modulator followed by a SAR ADC. Digital output from sigma-delta modulator may be weighted and summed with the output of the SAR ADC in an FPGA.

A hybrid analog-to-digital converter, an image sensor and a method for providing a plurality of ditigal signals

Single slope analog-to-digital converter

Flash-successive approximation analog-to-digital converter

This invention relates to a flash-successive approximation analog-to-digital converter combining the low speed, high resolution successive approximation method of conversion with the high speed, low resolution flash method of conversion, which provides the advantages of higher conversion speed with no increased conversion error.

Analog-digital converter

本实用新型涉及一种模数转换器，并且具体地，涉及基于时间残余的模数转换器。本实用新型所解决的技术问题是为信号转换提供增加的转换速率、改善的分辨率和改善的稳定时间，而无需与片上精度相符的电容器。所述ADC可利用两阶段转换过程将所述信号转换成粗位和精细位，从而将模拟信号转换为数字信号。所述ADC可生成时间残余信号并利用所述时间残余信号来确定所述精细位。本实用新型所实现的技术效果是为模数转换器提供改善的稳定时间、提高的分辨率和增加的转换速率。

Signal converting apparatus and related method

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.

Interleaving quantizer in continuous-time delta-sigma modulator for quantization level increment

The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.

SUBTRACTOR-AMPLIFIER CIRCUIT FOR CASCADE DIGITAL ANALOG CONVERTER

Dans un convertisseur analogique-numérique CAN à cascade, un premier CAN détermine les bits de poids supérieurs. Pour déterminer les bits de poids inférieurs, dans un deuxième CAN, il faut faire la différence entre le signal analogique d'entrée VE et sa partie déjà numérisée, reconvertie en analogique. Le soustracteur-amplificateur reçoit d'une part le signal d'entrée VE , qui est transformé en un courant iE , et d'autre part les bits de poids supérieurs S4 et S7 sur un convertisseur numérique-analogique. Ceci constitue une source modulable qui fournit un courant ic . Deux transistors en parallèle E et A font la différenciation entre le courant de la source modulable ic et le courant iE correspondant au signal d'entrée VE et l'amplifient. Application aux CAN à cascade.

Analog-to-digital converting system

A novel analog-to-digital converter (ADC) architecture using subranging successive approximation approach is disclosed. The ADC architecture is capable of achieving high sampling rate, low power consumption and low complexity. It is also able to advance the chip production yield and area utilization ratio. The new proposed ADC is formed by combining a flash converter having high sampling rate and low resolution with a successive approximation converter having low power consumption and low sampling rate.

Analog-to-digital converter

An analog-to-digital converter (300) in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom.

Circuit with a successive approximation analog to digital converter

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence.

A/D converter that is implemented using only digital circuit components and digital signal processing

A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion sampling interval, and a latch/encoder circuit detecting the total number of delay units traversed by the pulse signal by the end of the sampling interval, to obtain a numeric value expressing the input voltage level. To ensure uniformity of the delays of the delay units, these are formed using transistors of larger size than transistors of other circuits such as the latch/encoder circuit.

Circuit with a successive approximation analog to digital converter

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence.

Subranging analog-to-digital converter with integrating sample-and-hold

A subranging analog-to-digital converter (ADC) includes an integrating sample-and-hold circuit. The integrating sample-and-hold circuit is configured to sample an input voltage by charging at least one capacitor by coupling a current proportional to the input voltage to the at least one capacitor. A coarsely-quantizing ADC is configured to convert the voltage on the at least one capacitor to a digitized value. A digital-to-analog converter is configured to convert the digitized value to an analog voltage. A finely-quantizing ADC is configured to convert the difference between the analog voltage and the voltage on the charged at least one capacitor in the integrating sample-and-hold circuit to another digitized value.

Method and arrangement for digitising a voltage

Analog-digital-analog converter circuit

A converter circuit provides analog to digital and digital to analog functions on a single silicon device. A flash analog to digital converter produces digital outputs using comparators which each receive an input signal and which each have different reference voltages. A decoder receiving digital inputs activates switches to connect selected ones of the same voltage references used by the flash analog to digital converter to a buffer which produces an analog output. The converter circuit can be a single or multi-stage flash analog to digital converter operating in a single channel or multi-channel environment. Timing and control logic prevents switching from occurring at times when perturbations on the voltage references could affect the analog and digital outputs.

A/D converter, solid state image pickup device and driving method and electronic equipment

本技术涉及能够在减小电路尺寸的同时减少功率消耗的A/D转换器、固态成像装置及其驱动方法和电子设备。比较器将基准电压与输入电压相比较，该基准电压是RAMP波形以使得电压值随时间改变；较低位存储元件基于比较器的输出信号保存以预定计数模式的计数值；格雷码二进制转换电路将由较低位存储元件保存的以该计数模式的计数值转换为二进制数据；以及存储操作控制电路向较低位递增/递减计数器供应与由格雷码二进制转换电路转换的二进制数据对应的脉冲信号。本技术例如可应用于利用格雷码或相移码作为时钟信号在存储元件中保存计数值的图像传感器。

Robot, analog-to-digital converter, and solid-state imaging device

An analog-to-digital converter includes: a first to an (m+1)-th capacitive element each of which has a first end connected to a first terminal of a comparison circuit and have a predetermined capacitance ratio; and selection circuits which are connected to second ends of the capacitive elements, respectively. Each of the capacitive elements includes: a first electrode disposed in a semiconductor substrate and electrically connected to the second end; a third electrode disposed above the semiconductor substrate to oppose the first electrode and electrically connected to the second end; a second electrode disposed between the first electrode and the third electrode, above the semiconductor substrate, and electrically connected to the first end; a first insulation film disposed between the first and second electrodes; and a second insulation film disposed between the third and second electrodes.

Analog to digital converter with distortion correction

A system and method are disclosed for correcting for output distortion of an analog to digital converter, comprising: estimating the output distortion, providing an estimated distortion, and combining an output of the analog to digital converter with the estimated distortion to compensate for the output distortion. The compensating module for correcting output distortion of an analog to digital converter comprises a calibration module configured to estimate the output distortion and a combiner configured to combine an output of the analog to digital converter with the estimated distortion to compensate the output distortion.

Sub ranging a/d converter

내용 없음. No content.

Sub-range analog-to-digital converter with multiple clock cycles

Analog-to-digital converter and sensor device including such

PCT No. PCT/SE95/01287 Sec. 371 Date Apr. 30, 1997 Sec. 102(e) Date Apr. 30, 1997 PCT Filed Oct. 31, 1995 PCT Pub. No. WO96/13903 PCT Pub. Date May 9, 1996A periodically integrating analog-to-digital converter and a sensor device having such a converter. The analog-to-digital converter has a measured-value-to-pulse-amount converter, i.e., a sigma-delta converter of the first order that is reset to zero before each new period, and a digital counter for the number of feedback signals of known reference value in the measured-value-to-pulse-amount converter. This constitutes a rough measure of the input signal. The analog-to-digital converter also converts the residual value of the measured-value-to-pulse-amount converter at the end of the period to a digital value, and an adder which adds this value to the output signal from the digital counter, resulting in a more accurate measure of the input signal.

A subranging analog-to-digital converter

A subranging analog-to-digital converter is disclosed. A coarse analog-to-digital converter has an analog input terminal coupled to a source of analog signal, a digital output terminal, and a range indication output terminal. First and second fine analog-to-digital converters each have an analog input terminal coupled to the analog signal source, a range selection input terminal coupled to the range indication output terminal, and a digital output terminal. A combining circuit has input terminals coupled to the digital output terminals of the coarse and first and second fine analog-to-digital converters. The coarse analog-to-digital converter operates on every clock cycle, and the fine analog-to-digital converters operate alternately on every other clock cycle to produce a sequence of digital samples representing the analog signal, one for each clock cycle.

Multiplexing parallel analog-digital converter

A multiplexing parallel analog digital converter including two multiplexers, comparators, a demultiplexer, and a control unit. One multiplexer is provided the reference voltages resulting from a voltage division of inner resistors by a most significant bit reference ladder and a least significant bit reference ladder for the reference voltage of the next comparison. The other multiplexer is provided the reference voltages by accepting an analog input signal and the difference signal between an analog input signal and the output of a 4-bit digital analog converter. By using two multiplexers, only one analog digital converter is needed in this present device, so, the number of comparators is reduced. The multiplexer sends the digital signals compared with the most significant bit signal and the least significant bit signal, respectively, to a most significant output latch and a least significant output latch, respectively, so the 8-bit digital signal is obtained. The control unit is a logic circuit composed of flip-flops and gates, and provides clock signals for the sequential operation of the circuits, such as the operations of the multiplexers.

Data conversion methods and systems