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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 8711. Отображено 100.
05-01-2012 дата публикации

Digital Background Calibration System and Method for Successive Approximation (SAR) Analogue to Digital Converter

Номер: US20120001781A1
Автор: Anthony Gerard Scanlan
Принадлежит: University of Limerick

The invention provides a digital background calibration system and method for a successive approximation analog-to-digital converter comprising a digital to analog converter (DAC) having a plurality of weighted capacitors to be calibrated; means for splitting each of said weighted capacitors into a plurality of sub-capacitors and at least one redundant capacitor; means for multiplying the voltage level of at least one of the sub-capacitors with a PN sequence; and means for calibrating the weighted capacitor from the multiplied sub-capacitor and the redundant capacitor.

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Номер записи: 1
24-01-2018 дата публикации

Аналого-цифровой преобразователь

Номер: RU0000176659U1
Автор: Мария Сергеевна Жаворонкова, Сергей Николаевич Бондарь
Принадлежит: федеральное государственное бюджетное образовательное учреждение высшего образования "Ставропольский государственный аграрный университет"

Полезная модель относится к измерительной технике, в частности к аналого-цифровым преобразователям, и может быть использована в цифровых системах для измерения и контроля аналоговых величин. Технический результат, который может быть достигнут с помощью предлагаемой полезной модели, сводится к расширению функциональных возможностей, повышению точности или быстродействия или снижению сложности схемы. Расширение функциональных возможностей заключается в обеспечении возможности аналого-цифрового преобразования не только однополярных положительных, но также однополярных отрицательных и двуполярных сигналов. Устройство содержит схему сравнения, цифроаналоговый преобразователь, триггер, генератор импульсов, счетчик, регистр, постоянное запоминающее устройство, блок предсказания, блок определения знака и инвертирования отрицательных напряжений, в состав которого входят аналоговый инвертор, компаратор, два аналоговых ключа. 1 табл., 5 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 176 659 U1 (51) МПК H03M 1/38 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H03M 1/38 (2006.01); H03M 1/46 (2006.01) (21)(22) Заявка: 2017119127, 31.05.2017 (24) Дата начала отсчета срока действия патента: 24.01.2018 Приоритет(ы): (22) Дата подачи заявки: 31.05.2017 (45) Опубликовано: 24.01.2018 Бюл. № 3 1 7 6 6 5 9 R U (54) АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ (57) Реферат: Полезная модель относится к измерительной технике, в частности к аналого-цифровым преобразователям, и может быть использована в цифровых системах для измерения и контроля аналоговых величин. Технический результат, который может быть достигнут с помощью предлагаемой полезной модели, сводится к расширению функциональных возможностей, повышению точности или быстродействия или снижению сложности схемы. Расширение функциональных возможностей заключается в обеспечении возможности аналого-цифрового Стр.: 1 (56) Список документов, цитированных в отчете о поиске: RU 2205500 C1, ...

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Номер записи: 2
17-08-2020 дата публикации

Последовательный преобразователь двухполярного напряжения в двоичный код последовательного приближения

Номер: RU0000199113U1
Автор: Сергей Ильич Зиатдинов
Принадлежит: Федеральное государственное автономное образовательное учреждение высшего образования "Санкт-Петербургский государственный университет аэрокосмического приборостроения"

Полезная модель относится к вычислительной технике и может быть использована при цифровой обработке сигналов для преобразования двухполярного напряжения в цифровой двоичный код с увеличенным динамическим диапазоном преобразования. Последовательный преобразователь двухполярного напряжения в двоичный код последовательного приближения обеспечивает преобразование как положительного, так и отрицательного напряжения в двоичный код, а также увеличивает динамический диапазон преобразования в два раза, за счет того, что включает n-разрядный параллельный цифроаналоговый преобразователь, n разрядных триггеров, n двухвходовых дизъюнктора сброса разрядных триггеров, n двухвходовых конъюнкторов, n+1-разрядный сдвигающий регистр, двухвходовой дизъюнктор подачи тактовых импульсов, линию задержки, двухвходовой дизъюнктор окончания преобразования, триггер начала преобразования, генератор тактовых импульсов, двухвходовой конъюнктор подачи тактовых импульсов, двухвходовой логический сумматор по модулю два, знаковый компаратор, компаратор, логический инвертор, второй аналоговый ключ, первый аналоговый ключ, аналоговый сумматор и аналоговый инвертор. Преобразование двухполярного напряжения в двоичный код достигается за счет того, что в составе преобразователя имеется аналоговый инвертор и два аналоговых ключа, позволяющие сравнивать в компараторе положительное преобразуемое напряжение с положительным напряжением с выхода цифроаналогового преобразователя и при отрицательном преобразуемом напряжении - с отрицательным напряжением после инверсии выходного напряжения цифроаналогового преобразователя. 1 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 199 113 U1 (51) МПК H03M 1/38 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H03M 1/38 (2020.02) (21)(22) Заявка: 2020110478, 12.03.2020 (24) Дата начала отсчета срока действия патента: Дата регистрации: 17.08.2020 Приоритет(ы): (22) Дата подачи заявки: 12.03.2020 (45) Опубликовано: 17.08 ...

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Номер записи: 3
12-01-2012 дата публикации

Electronic circuit

Номер: US20120007438A1
Автор: Tadahiro Kuroda
Принадлежит: KEIO UNIVERSITY

A low-power high-speed asynchronous inductive-coupling transmission and reception technology is provided, in which a current signal of a single pulse is made to flow through a transmitting coil, and a voltage signal of a double pulse induced in an inductively-coupled receiving coil can be received asynchronously. A transmitting circuit for performing non-contact proximity communication adopts a configuration in which current flows through a first coil in a first direction for each change of a logical value of transmit data. A receiving circuit connected to a second coil coupled inductively to the first coil employs a comparator which determines an induced voltage of a double pulse induced in the second coil by current in the first direction and outputs a unipolar single pulse signal. Whenever the single pulse signal outputted by the comparator is inputted, the receiving circuit inverts the output in a sequential circuit and reproduces receive data.

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Номер записи: 4
26-01-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120019969A1
Автор: Masaru Iwabuchi
Принадлежит: Renesas Electronics Corp

In combining an analog terminal of an A/D converter with a digital terminal, the effect of the noise from the digital terminal is reduced. A semiconductor integrated circuit includes a high-speed external terminal, a low-speed external terminal, a high-speed analog switch, a low-speed analog switch, and an A/D converter. The high-speed external terminal is coupled to an input of the A/D converter via the high-speed analog switch, and the low-speed external terminal is coupled to the input of the A/D converter via the low-speed analog switch. A plurality of inputs of a plurality of low-speed digital input buffer circuits and a plurality of outputs of a plurality of low-speed digital output buffer circuits are coupled to a plurality of low-speed external terminals. The output of any digital output buffer circuit is not coupled to a plurality of high-speed external terminals, but a plurality of inputs of a plurality of high-speed digital input buffer circuits is coupled to a plurality of high-speed external terminals. Between a plurality of low-speed external terminals and the input of the A/D converter, a low-speed separating resistor with a high resistance value is coupled, respectively.

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Номер записи: 5
26-01-2012 дата публикации

Statistical Word Boundary Detection in Serialized Data Streams

Номер: US20120023059A1
Автор: James R. Fisher, Matthew A. Morgan
Принадлежит: Associated Universities Inc

Methods, systems, and devices using an algorithm that consists of scoring the bits in the data stream with a periodicity of N, where N is the word-length in bits, and then selecting as the most significant bit the one which receives the highest score after some large number of samples are disclosed. The condition under which bit b k receives a point depends on the binary format.

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Номер записи: 6
02-02-2012 дата публикации

A/d converter using isolation switches

Номер: US20120026027A1
Автор: Jesper Steensgaard-Madsen
Принадлежит: Linear Technology LLC

In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated.

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Номер записи: 7
02-02-2012 дата публикации

Demodulation circuit, digital microwave system and demodulation method

Номер: US20120027129A1
Автор: Guixue Zhao, Tianxiang Wang
Принадлежит: Huawei Technologies Co Ltd

A demodulation circuit, a digital microwave system including the demodulation circuit, and a signal demodulation method are provided. The demodulation circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit connected in turn. The fourth circuit includes a pulse counting unit and a data decision unit connected in turn. The signal demodulation method includes: performing bandpass filtering on input signals; increasing gains of the bandpass filtered signals; extracting pulse signals are extracted from the gain-increased signals; counting the extracted pulse signals; filtering the pulse signals having counting values falling outside of a predetermined range, and outputting the filtered pulse signals.

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Номер записи: 8
09-02-2012 дата публикации

Serial link voltage margin determination in mission mode

Номер: US20120033685A1
Автор: Dawei Huang, Deqiang Song, Drew G. Doblar
Принадлежит: Oracle International Corp

This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.

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Номер записи: 9
16-02-2012 дата публикации

Mode Dependent Driving of the Center Tap in Ethernet Communications

Номер: US20120038393A1
Автор: Christopher Ward, Erol Arslan, Frank van der GOES, Ovidiu Bajdechi
Принадлежит: Broadcom Corp

An output stage comprising a current mode line driver, a voltage mode line driver, and a center-tapped transformer for coupling data provided by the line drivers to a transmission line is provided herein. The output stage is configured to operate in a backwards compatible Ethernet communication device. For example, the Ethernet communication device is configured to support 10G Ethernet and legacy Ethernet modes of 10BASE-T, 100BASE-T, and 1000BASE-T. The current mode line driver can be utilized while operating in the 10G Ethernet mode to provide high linearity. The voltage mode line driver can be utilized while operating in legacy mode to conserve power. In order to accommodate the use of two different line drivers, a switch and/or a voltage regulator is used to couple/decouple a dc voltage to a center-tap of the transformer based on which of the two different line drivers is currently active.

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Номер записи: 10
16-02-2012 дата публикации

Receiver apparatus for receiving a multicarrier signal

Номер: US20120039379A1
Автор: Alessio Filippi, Phjm Van Voorthuisen, Sri Andari Husen
Принадлежит: NXP BV

In time varying OFDM systems, the effect of a non-ideal time synchronization may lead to a poor performance in terms of decoded average bit error rate versus the signal-to-noise ratio. The receiver apparatus ( 3 ) of the transmission system ( 1 ) estimates a subcarrier-dependent channel frequency response and determines an intercarrier interference spreading on the basis of a cyclic shift in symbols carried by the subcarriers. Therewith, an intercarrier interference included in an OFDM signal can be canceled, even in case of a non-ideal time synchronization.

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Номер записи: 11
15-03-2012 дата публикации

Network system and node

Номер: US20120066421A1
Автор: Atsushi Seita, Masaki Mitsui, Naoki Nagashima, Osamu Ueda, Takanori Aoki, Taro Inami
Принадлежит: Azbil Corp

A connector unit includes a communication line connecting a receiving port of a physical layer unit of a node to one adjacent node, and a communication line connecting a transmitting port of the physical layer unit to the one adjacent node via a capacitor, and a connector unit includes a communication line for connecting a receiving port of a physical layer unit of the node to the other adjacent node, and a communication line for connecting a transmitting port of the physical layer unit to the other adjacent node via a capacitor, wherein the connector unit is connected to a connector unit of the one adjacent node, so that the communication line of the node is connected to the communication line of the one adjacent node, and the communication line of the node is connected to the communication line of the one adjacent node.

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Номер записи: 12
19-04-2012 дата публикации

Analog to digital converter

Номер: US20120092202A1
Автор: John Kikidis, Michael Birbas, Nikolaos Petrellis
Принадлежит: ANALOGIES SA

An analog to digital converter for converting an initial analog signal into a digital signal comprising at least one electronic module with an input, a first output, and a second output, which module generates from an analog input signal: a first output signal, which first output signal in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the integer quotient of division of the input signal by a number or comprises a plurality of signals which if combined are substantially equal to the integer quotient of division of the input signal in terms of multiples of a predetermined amount of current or voltage, and a second output signal which in terms of multiples of a predetermined amount of current or voltage, such as 1 uA or 1 mV, is substantially equal to the remainder of the division, the analog to digital converter also comprising a further analog to digital converter for converting the second output signal into a digital signal, wherein the further analog to digital converter is connected the at least one module and the module is configured so that in use when the analog input signal connects through the input the first output signal connects through the first output, and the second output signal connects through the second output into the further analog to digital converter.

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Номер записи: 13
14-06-2012 дата публикации

Successive approximation register analog-to-digital converter and analog-to-digital conversion method using the same

Номер: US20120146822A1
Автор: Hyeong-won Kang
Принадлежит: LG Display Co Ltd

A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes a Sample-and-Hold Amplifier (SHA) for sampling and holding an externally input analog voltage, a comparator for comparing a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, an SAR logic circuit for sequentially generating a digital signal from a Most significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal, a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output register for holding the sequentially generated digital signal from the MSB to the LSB to generate an n-bit digital signal, wherein, upon externally receiving a start signal, the SAR logic circuit generates a digital signal of a MSB having a one-bit phase delay compared with the start signal.

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Номер записи: 14
12-07-2012 дата публикации

Semiconductor integrated device and operation method thereof

Номер: US20120176261A1
Автор: Takuji Aso, Toshiyuki Ishioka
Принадлежит: Renesas Electronics Corp

In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.

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Номер записи: 15
16-08-2012 дата публикации

Control of a loudspeaker output

Номер: US20120207314A1
Автор: Bram Hedebouw, Temujin Gautama
Принадлежит: NXP BV

A loudspeaker drive circuit comprises an input for receiving an audio signal and a signal processor for processing the audio signal before application to the loudspeaker. The signal processor processes the audio signal to derive a loudspeaker drive signal which results in the loudspeaker membrane reaching its maximum displacement in both directions of diaphragm displacement.

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Номер записи: 16
23-08-2012 дата публикации

Baseband Recovery in Wireless Networks, Base Transceiver Stations, and Wireless Networking Devices

Номер: US20120213257A1
Автор: Tim Kuechler
Принадлежит: Apple Inc

Baseband recovery in wireless networks, base transceiver stations, and wireless networking devices may be implemented to minimize the number of timing symbols while at the same time enabling wireless devices to use a relatively low per-symbol sampling rate, so that minimal processing is required to implement the timing recovery. In one embodiment, a relatively low number of samples is taken per expected symbol interval during the training sequence. A subset of the samples is selected and processed to determine error signals for each of the samples. The error signals are multiplied by the expected symbol and summed to form an error signal. The error signal is used to adjust the set of samples that will be used and processed in connection with subsequent symbols. The error signal is also used to interpolate between available samples to infinitesimally approach the point of maximum eye opening.

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Номер записи: 17
30-08-2012 дата публикации

Low-power area-efficient sar adc using dual capacitor arrays

Номер: US20120218137A1
Автор: Euisik Yoon, Sun-Il Chang
Принадлежит: University of Michigan

An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.

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Номер записи: 18
30-08-2012 дата публикации

Signal Processing Circuit and Method

Номер: US20120219088A1
Автор: Andreas Holm, Dirk Friedrich
Принадлежит: Intel Mobile Communications GmbH

A signal processing circuit for providing a modulated analog transmit signal on the basis of a digital transmit data signal is configured to vary a resolution in dependence on a detected or predefined parameter when providing the modulated analog transmit signal.

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Номер записи: 19
13-09-2012 дата публикации

Analog to digital converter circuit

Номер: US20120229313A1
Автор: Chi-Hang CHAN, Franco Maloberti, He-Gong Wei, Li Ding, Rui Paulo da Silva Martins, Sai-Weng Sin, Seng-Pan U, U-Fat CHIO, Yan Zhu
Принадлежит: UNIVERSITY OF MACAU

The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design

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Номер записи: 20
13-09-2012 дата публикации

Soft bit metric generation

Номер: US20120230379A1
Автор: Christian Rasmussen, Fan Mo, Mehmet Aydinlik, Sameep Dave
Принадлежит: Acacia Communications Inc

Soft bit metric generation computational complexity can be reduced by identifying and utilizing only the dominant terms in a reliability calculation such as a logarithmic likelihood ratio (LLR). The dominant terms are those terms for which the signs of the x and y components match those of channel outputs of the channel outputs. One technique for identifying the dominant terms is by determining the most likely transitions from two consecutive channel output samples Values for the dominant terms can be estimated by either the joint reliability of two consecutive samples of the in-phase component (x 1 ,x 2 ) or by the joint reliability of two consecutive samples of the quadrature components (y 1 ,y 2 ).

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Номер записи: 21
08-11-2012 дата публикации

Successive approximation register analog-to-digital converter

Номер: US20120280846A1
Автор: Jin-Fu Lin
Принадлежит: Himax Technologies Ltd

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

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Номер записи: 22
06-12-2012 дата публикации

Isolated resistive current sensor

Номер: US20120306657A1
Автор: Miguel Angel Acena, Youssef Ghabbour
Принадлежит: Lear Corp

An isolated current-sensing system for use with a resistive current sense element includes an analog front-end configured to receive a voltage from the resistive current sense element, and to provide an analog output. A processing circuit receives the analog output, and provides a measurement signal indicative of the sensed current. An isolation circuit provides an isolation barrier, and is configured to pass the measurement signal. A programmable over-current protection alarm may be included, and configured to generate an alarm signal when the analog output exceeds a programmable threshold. The processing circuit may include a voltage-to-PWM converter.

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Номер записи: 23
06-12-2012 дата публикации

Analog-to-digital conversion apparatus and signal processing system

Номер: US20120306673A1
Автор: Yosuke Ueno
Принадлежит: Sony Corp

An analog-to-digital conversion apparatus includes: a first analog-to-digital converter configured to convert an input analog signal into a digital signal; a second analog-to-digital converter configured to convert an analog signal generated by multiplying the input analog signal by α times with a coefficient α into a digital signal; a first non-linear compensation part configured to compensate a non-linear distortion of a first output signal of the first analog-to-digital converter; a second non-linear compensation part configured to compensate a non-linear distortion of a second output signal of the second analog-to-digital converter; and a non-linear detection part configured to estimate how much the non-linear distortions of the first and second analog-to-digital converters are compensated by the first and second non-linear compensation parts depending on first and second signals by the first and second non-linear compensation parts.

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Номер записи: 24
24-01-2013 дата публикации

Multiplexed amplifier with reduced glitching

Номер: US20130021188A1
Автор: Robert F. Payne
Принадлежит: Texas Instruments Inc

In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.

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Номер записи: 25
24-01-2013 дата публикации

Enhanced lattice reduction systems and methods

Номер: US20130022155A2
Автор: Qi Zhou, Xiaoli Ma
Принадлежит: Georgia Tech Research Corp

An exemplary embodiment of the present invention provides a lattice reduction method comprising obtaining a preliminary estimate of a transformation matrix, generating a covariance matrix based on the preliminary estimate of the transformation matrix, reducing diagonal elements of the covariance matrix to generate a unimodular transformation matrix, and using the unimodular transformation matrix to obtain an estimate of an input.

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Номер записи: 26
14-03-2013 дата публикации

Method and apparatus for decoding a repeated message

Номер: US20130064331A1
Автор: Miguel M. Lopez, Sajal Kumar Das
Принадлежит: Telefonaktiebolaget LM Ericsson AB

Techniques for decoding repeated messages sent from a transmitter are improved with information obtained from the decoding of the first transmission and by augmenting Chase combining techniques with a voting-based combining method. In an example method, first encoded bits corresponding to a first instance of the repeated message and demodulated to obtain first soft bits, which are decoded to obtain first decoded bits. Second encoded bits corresponding to a second instance of the repeated message are demodulated to obtain second soft bits. The first decoded bits are re-encoded to obtain re-encoded bits. Sign values for modified soft bits are determined from sign values for the first soft bits, the sign values for the second soft bits, and the sign values for the re-encoded bits. The modified soft bits are combined with the first soft bits and decoded.

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Номер записи: 27
28-03-2013 дата публикации

Methods and apparatus for mimo detection

Номер: US20130077721A1
Автор: Ankit Gupta, Chaiman Lim, Zhouyue Pi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmitted signal estimate based on signals received in a layer i within a multiple input, multiple output transmission system and based upon selected constellation points for other, previously processed layers is quantized to a nearest constellation point. A list of candidates headed by the nearest constellation point and with remaining candidates presorted by proximity to the head is selected, for each such quantized estimate based on constellation point selections for previously processed layers. To select K best candidates for the transmitted signal estimates of the current layer i, the proximity of the candidates at the head of each list to the signal estimate for the current layer are compared, and the closest candidate is selected. The list containing the selected candidate is advanced, and proximity of the transmitted signal estimate to all list heads is again evaluated and the closest candidate selected.

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Номер записи: 28
30-05-2013 дата публикации

Electronic Device and Method for Analog to Digital Conversion Using Successive Approximation

Номер: US20130135125A1
Автор: Renukamurthy Harinath, RUCK BERNHARD, Schreiner Joerg
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value. 1. An electronic device for analog-to-digital conversion using successive approximation , the device comprising:a successive approximation register storing a digital value;a digital-to-analog converter coupled to said successive approximation register, said digital-to-analog converter adapted to convert said digital value stored in said successive approximation register into an analog value and output said analog value;a comparator coupled to said digital-to-analog converter and receiving an analog input value, said comparator adapted to compare said analog value output from said digital-to-analog converter with said analog input value and generate a comparison signal; load a first digital value into said successive approximation register,', 'increase said digital value stored said successive approximation register if said comparison signal indicates said analog value output from said digital-to-analog converter is less than said analog input value, and', 'decrease said digital value stored said successive approximation register if said comparison signal indicates said analog value output from said digital-to-analog converter is greater than said analog input value., 'a control stage connected to said successive approximation register and said comparator, said control ...

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Номер записи: 29
30-05-2013 дата публикации

RECEPTION DEVICE

Номер: US20130136216A1
Автор: Sakamoto Takenori, Shirakata Naganori
Принадлежит: Panasonic Corporation

There are provided a correlation calculation unit that takes a cross-correlation between a signal from which a DC component of an analog baseband signal is removed, and to which a known fixed DC offset is added, and a known signal, an inter-correlation peak phase difference detection unit that estimates a carrier frequency offset from a peak of the calculated correlation vector, and a residual DC offset estimation unit that estimates a residual DC offset component from a mean value of the sidelobe of the calculated correlation vector. 1. A reception device configured to receive a single carrier signal , comprising:a filter configured to remove a DC component of a baseband signal of a received single carrier signal;a fixed DC offset addition unit configured to add, as a fixed DC offset, a DC component included in a known signal to a signal from which the DC component has been removed;a correlation calculation unit configured to calculate a cross-correlation between the signal to which the fixed DC offset has been added and the known signal;a carrier frequency offset estimation unit configured to estimate a carrier frequency offset according to a peak of the correlation vector calculated by the correlation calculation unit; anda frequency correction unit configured to correct a frequency of the baseband signal on the basis of the estimated carrier frequency offset.2. The reception device according to claim 1 , further comprising:a residual DC offset estimation unit configured to estimate a residual DC offset according to a mean value of a sidelobe of the correlation vector calculated in the correlation calculation unit; anda DC offset correction unit configured to correct the DC offset of the baseband signal on the basis of the estimated residual DC offset.3. The reception device according to claim 1 ,wherein the filter is configured to remove the DC component of an analog baseband signal,wherein the reception device further includes an AD converter configured to ...

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Номер записи: 30
06-06-2013 дата публикации

MAJORITY DETECTOR APPARATUS, SYSTEMS, AND METHODS

Номер: US20130142285A1
Автор: Dimitriu Dragos
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatus, methods, and systems are disclosed, including, for example,a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results. 1. An apparatus comprising:a receiver to receive a first voltage and a second voltage, and to provide an output based on a voltage difference between the first and second voltages, the output including a plurality of bits;a first counter to count a number of bits having a same state among the plurality of bits and provide a bit count;a second counter to count a number of clock cycles of a clock signal and provide a clock cycle count; anda comparator to compare the clock cycle count with a count derived from the bit count.2. The apparatus of claim 1 , further comprising a multiplier to multiply the bit count to provide the count derived from the bit count.3. The apparatus of claim 2 , wherein the comparator comprises comparator cells to compare the clock cycle count with the count derived from the bit count.4. The apparatus of claim 2 , wherein the comparator comprises comparator cells to compare the clock cycle count with the count derived from the bit count from a most significant bit to a least significant bit.5. The apparatus of claim 1 , further comprising a divider to divide the clock cycle count to provide a divided clock cycle count.6. The apparatus of claim 5 , wherein the comparator comprises comparator cells to compare the plurality of bits of the output count with the divided clock cycle count ...

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Номер записи: 31
27-06-2013 дата публикации

High-speed successive-approximation-register analog-to-digital converter and method thereof

Номер: US20130162454A1
Автор: Chia-Liang Lin
Принадлежит: Realtek Semiconductor Corp

In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data.

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Номер записи: 32
27-06-2013 дата публикации

Methods and Systems for Compressed Sensing Analog to Digital Conversion

Номер: US20130162457A1
Автор: Allstot David, Gangopadhyay Daibashish
Принадлежит: University of Washington through its Center for Communications

Disclosed herein are example methods, systems, and devices for compressed sensing analog to digital conversion. In an example embodiment, a multiplication circuit is configured to multiply an input signal with a measurement signal to produce a multiplied signal, where the measurement signal includes data from a column of a measurement matrix. The measurement matrix may be generated by a linear feedback shift register (LFSR)-based measurement-matrix generator. An integration circuit may be coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal. An analog to digital converter (ADC) circuit may be coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal. Among other benefits of the disclosure herein, a column-wise multiplication of the input signal with the measurement signal enables an efficient compressed-sensing analog-to-digital conversion architecture. 1. A circuit comprising:a multiplication circuit configured to multiply an input signal with a measurement signal to produce a multiplied signal, wherein the measurement signal comprises data from a column of a measurement matrix;an integration circuit coupled to the multiplication circuit and configured to integrate the multiplied signal for a predefined amount of time to produce an integrated signal; andan analog to digital converter (ADC) circuit coupled to the integration circuit and configured to (i) sample the integrated signal and (ii) produce an output signal comprising at least one sample of the integrated signal.2. The circuit of claim 1 , wherein the measurement matrix comprises a plurality of entries claim 1 , the circuit further comprising:a measurement-matrix generator coupled to the multiplication circuit and configured to generate a random coefficient for each entry in the measurement ...

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Номер записи: 33
01-08-2013 дата публикации

Method and Apparatus for Clockless Conversion of Voltage Value to Digital Word

Номер: US20130194123A1
Автор: Dariusz Koscielnik, Marek Miskowicz
Принадлежит: Dariusz Koscielnik, Marek Miskowicz

Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor.

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Номер записи: 34
08-08-2013 дата публикации

REFERENCE VOLTAGE GENERATION IN A SINGLE-ENDED RECEIVER

Номер: US20130202061A1
Автор: Chandrasekaran Srinivasaraman
Принадлежит: RAMBUS INC.

As single-ended signaling is implemented in higher-speed communications, accurate and consistent reading of the data signal becomes increasingly challenging. In particular, single-ended links can be limited by insufficient timing margins for sampling a received input signal. A single ended receiver provides for improved timing margins by adjusting a reference voltage used to sample the input signal. A calibration pattern is provided to the receiver as the input signal, and the reference voltage is adjusted toward a median value of the signal. As a result, the receiver provides for reading received single-ended data in a manner enabling accurate data transfer at higher speeds. 1. A method of calibrating a receiver for receiving a signal , comprising:sampling a input signal against a reference voltage to generate a sampled input signal;calculating a duty cycle of the sampled input signal; andadjusting the reference voltage based on the duty cycle.2. The method of claim 1 , wherein adjusting the reference voltage includes adjusting the reference voltage to move the reference voltage toward a median value of the input signal.3. The method of claim 1 , wherein adjusting the reference voltage includes:comparing the duty cycle against a duty cycle of 50%; anddetermining adjustment to the reference voltage such that the duty cycle is moved towards 50%.4. The method of claim 1 , wherein the input signal corresponds to a digital pattern having an equal number of high and low bits.5. The method of claim 4 , wherein the input signal is generated by an oscillator circuit.6. The method of claim 1 , wherein adjusting the reference voltage includes adjusting the reference voltage to match the median value of the input signal.7. The method of claim 6 , wherein adjusting the reference voltage includes:comparing the duty cycle against a duty cycle of 50%; anddetermining adjustment to the reference voltage such that the duty cycle is 50%.8. The method of claim 1 , further comprising ...

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Номер записи: 35
08-08-2013 дата публикации

Collision detection using a multiple symbol noncoherent soft output detector

Номер: US20130202062A1
Автор: Dariush Divsalar, Ramin Sadr
Принадлежит: Mojix Inc

Systems and methods for detecting collisions in radio frequency tags in accordance with embodiments of the invention are disclosed. In one embodiment, a receiver system includes a receiver configured to receive and sample a phase modulated input signal, and a multiple symbol noncoherent soft output detector configured to receive the sampled input signal and to generate a soft metric indicative of the reliability of a detected symbol based upon observations over multiple symbols, a collision detector configured to calculate a decision metric from a set of soft metrics generated by the multiple symbol noncoherent soft output detector and detect a collision when the decision metric satisfies a predetermined criterion.

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Номер записи: 36
22-08-2013 дата публикации

Device, System and Method for Analogue-to-Digital Conversion Using a Current Integrating Circuit

Номер: US20130214947A1
Автор: Craninckx Jan, Yamamoto Takaya
Принадлежит:

A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.

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Номер записи: 37
22-08-2013 дата публикации

APPARATUS AND METHOD FOR DETECTING COMMUNICATIONS FROM MULTIPLE SOURCES

Номер: US20130215955A1
Автор: Fitz Michael P., SITI Massimiliano
Принадлежит:

A method, apparatus, and computer program for detecting sequences of digitally modulated symbols transmitted by multiple sources are provided. A real-domain representation that separately treats in-phase and quadrature components of a received vector, channel gains, and a transmitted vector transmitted by the multiple sources is determined. The real-domain representation is processed to obtain a triangular matrix. In addition, at least one of the following is performed: (i) hard decision detection of a transmitted sequence and demapping of corresponding bits based on a reduced complexity search of a number of transmit sequences, and (ii) generation of bit soft-output values based on the reduced complexity search of the number of transmit sequences. The reduced complexity search is based on the triangular matrix. 1. A method for detecting sequences of digitally modulated symbols transmitted by multiple sources and received at a receiver , comprising:determining a real-domain representation that separately treats in-phase and quadrature components of a received vector, channel gains, and a transmitted vector transmitted by the multiple sources;processing the real-domain representation to obtain a triangular matrix; andperforming, at the receiver, at least one of: (i) hard decision detection of a transmitted sequence and demapping of corresponding bits based on a reduced complexity search of a number of transmit sequences, and (ii) generation of bit soft-output values based on the reduced complexity search of the number of transmit sequences, the reduced complexity search based on the triangular matrix.2. The method of claim 1 , wherein:channel state information and received observations are known at the receiver;the channel state information comprises a complex matrix, the complex matrix comprising entries representing complex gain channel paths between transmit and receive antennas; andthe received observations comprise a complex vector.3. The method of claim 1 , ...

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Номер записи: 38
29-08-2013 дата публикации

WIRELESS RECEIVER

Номер: US20130223569A1
Автор: HONMA Hiroki, ITO Katsuhiko, NITTA Yoshimi
Принадлежит: GOYO ELECTRONICS CO., LTD.

A direct-conversion type wireless receiver includes a pair of mixers for frequency-converting a radio signal received from an antenna into a base band signal by local signals having different phases; a first amplification circuit for amplifying the base band signal up to a demodulation level; a second amplification circuit provided between the mixer and the first amplification circuit; and a variable current circuit including a multi-stage current mirror to add a current 2n times as high as a reference current. The wireless receiver further includes a control unit configured to correct a DC offset of the mixer by allowing a current to flow into the second amplification circuit from the variable current circuit, based on an output of the first amplification circuit, and a capacitor connected between a gate and a source of a PchMOSFET which allows the reference current to flow therethrough. 1. A direct-conversion type wireless receiver , comprising:a pair of mixers configured to frequency-convert a radio signal received from an antenna into base band signals by local signals having different phases;a first amplification circuit configured to amplify a base band signal from one of the mixers up to a demodulation level;a second amplification circuit provided between said one of the mixers and the first amplification circuit;a variable current circuit including a multi-stage current mirror to add a current 2n times as high as a reference current;a control unit configured to correct a DC offset of said one of the mixers by allowing a current to flow into the second amplification circuit from the variable current circuit, based on an output of the first amplification circuit; anda capacitor connected between a gate and a source of a PchMOSFET which allows the reference current to flow therethrough.2. The wireless receiver of claim 1 , wherein the control unit includes a comparator configured to output a result of comparison between the output of the first amplification ...

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Номер записи: 39
29-08-2013 дата публикации

APPARATUS FOR REMOVING DC COMPONENTS INHERENT IN A RADIO FREQUENCY CHAIN

Номер: US20130223570A1
Автор: LE CORRE Pascal, PAQUELET Stéphane
Принадлежит: RENESAS MOBILE CORPORATION

Device for compensating a DC component inherent in any radio frequency chain in which from a single measurement, generally obtained from a digital stage, a set of multiple compensation values is determined by a compensation value vector generating module and which compensation values are applied to multiple compensation points of the analog chain. The compensation values are calculated by an iterative process converging toward cancellation of the DC component and avoid saturating amplification components and components of the analog-to-digital converter. The module includes compensation value calculation units each configured to calculate a respective compensation value and provide the calculated compensation value to the respective compensation point. 1. A radio frequency signal reception device , comprising:at least one analog stage into which a DC component in a signal passing through the analog stage is present, each of the at least one analog stage having compensation points at each of which a compensation DC signal is added from digital-to-analog conversion of a compensation value in order to cancel a DC component measured at an end of the at least one analog stage; anda module that produces the compensation DC signals that are added to the compensation points of the at least one analog stage; calculate an approximate gain vector with a number of components corresponding to the number of compensation points, each component being based on gain and attenuation values of analog components located downstream of the corresponding compensation point in the at least one analog stage;', 'calculate a corresponding unit gain vector by dividing the approximate gain vector by its Euclidean norm;', 'calculate a first term representing a value to be compensated divided by the gain vector norm and multiplying a product of this result with the unit gain vector;', 'calculate a new compensation vector by adding a second term to the first term, the second term being a current ...

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Номер записи: 40
26-09-2013 дата публикации

SUCCESSIVE APPROXIMATION A/D CONVERTER

Номер: US20130249728A1
Автор: IKEDA Shinichi, Ishii Hirotomo
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A successive-approximation A/D converter includes a reference voltage generator configured to generate a reference voltage, a comparator configured to receive an input analog signal and generate a voltage difference by comparing the input analog signal and the reference voltage, an error-correction circuit including a variable capacitor configured to correct the voltage difference based on a capacitance of the variable capacitor, an error-correction controller configured to retrieve from memory a correction amount and control the error-correction circuit to vary the capacitance of the variable capacitor according to the correction amount, and a successive approximation register logic circuit configured to generate an output digital signal based on the voltage difference from the comparator. 1. A successive approximation analog-to-digital (A/D) converter , comprising:a reference voltage generator configured to generate a reference voltage;a comparator configured to receive an input analog signal and generate a voltage difference by comparing the input analog signal and the reference voltage;an error-correction circuit including a variable capacitor configured to correct the voltage difference based on a capacitance of the variable capacitor; andan error-correction controller configured to retrieve from memory a correction amount and control the error-correction circuit to vary the capacitance of the variable capacitor according to the correction amount.2. The successive approximation A/D converter of claim 1 , wherein the error-correction circuit further includes a second variable capacitor configured to correct the voltage difference based on a capacitance of the second variable capacitor.3. The successive approximation A/D converter of claim 2 , wherein the error-correction controller is configured to retrieve from memory a second correction amount and control the error-correction circuit to vary the capacitance of the second variable capacitor according to the ...

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Номер записи: 41
26-09-2013 дата публикации

Multilevel amplitude modulation device, multilevel amplitude demodulation device, transmission system including these, multilevel amplitude modulation method, and multilevel amplitude demodulation method

Номер: US20130251060A1
Автор: Osamu Shibata, Tsuyoshi Ikushima
Принадлежит: Panasonic Corp

A multilevel amplitude modulation device for generating, from digital data, a multilevel amplitude modulation signal having four or more signal levels and outputting the generated signal, including: an average level calculator that selects one of a plurality of preliminarily prepared different candidates for a code word building method such that average level of a symbol array, obtained by adding a symbol for a code word of digital data to be transmitted to one or more already outputted symbols included in a multilevel amplitude modulation signal already outputted, is most approximate to voltage center of the four or more signal levels, and outputs a selection signal indicating the selected method; a signal converter that forms a codeword of the digital data in accordance with the method indicated by the selection signal; and a multilevel modulator that generates a multilevel amplitude modulation signal using the codeword and outputs the generated signal.

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Номер записи: 42
03-10-2013 дата публикации

Low Power Receiver

Номер: US20130259163A1
Автор: DARABI HOOMAN, Hadji-Abdolhamid Amir, Mikhemar Mohyee
Принадлежит: BROADCOM CORPORATION

According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an s output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TTA) implemented using a current mode to buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced. 120-. (canceled)21. A compact low-power receiver comprising:first and second analog circuits, said first analog circuit having a first direct-current (DC) offset and a first common mode voltage at an output, said second analog circuit having a second DC offset and a second common mode voltage at an input;an interface circuit connecting said output to said input;said interface circuit configured to match said first and second DC offsets.22. The compact low-power receiver of claim 21 , further comprising an analog-to-digital converter (ADC) coupled to an output of said second analog circuit.23. The compact low-power receiver of claim 22 , wherein said ADC is configured to provide control data for said interface circuit.24. The compact low-power receiver of claim 21 , wherein said interface circuit comprises a plurality of cross-coupled adjustable current source pairs.25. The compact low-power receiver of claim 24 , wherein said plurality of cross-coupled adjustable current source pairs are configured to tune at least one internal current of said interface circuit so as to match said first and second ...

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Номер записи: 43
03-10-2013 дата публикации

Enhanced metrics for demodulation and soft information generation in the presence of a non-constant envelope modulated interferer

Номер: US20130259164A1
Автор: Ali S. Khayrallah, Dennis Hui
Принадлежит: Telefonaktiebolaget LM Ericsson AB

Systems and methods utilize enhanced metrics for demodulation and/or soft bit information generation in the presence of a non-constant envelope modulated interfering signal. In one embodiment, a receiver includes a downconverter and a demodulator. The downconverter receives a radio frequency signal comprising a desired signal, noise, and a non-constant envelope modulated interfering signal, and downconverts the radio frequency signal to provide a downconverted signal. The demodulator demodulates the downconverted signal based on a demodulation metric that models the non-constant envelope modulated interfering signal as a stationary non-Gaussian random process with a probability distribution derived from a modulation constellation of a modulation used for the non-constant envelope modulated interfering signal. In one embodiment, the demodulator outputs demodulated symbols. In another embodiment, the demodulator outputs soft bit information.

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Номер записи: 44
10-10-2013 дата публикации

INTEGRATED CIRCUIT

Номер: US20130265180A1
Автор: Ito Masao, Matsumoto Osamu, MATSUMOTO Takashi, Suzuki Hiroto
Принадлежит:

A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period. 1. An integrated circuit including a successive approximation register A/D (analog/digital) converter which obtains a comparison result of N bits (N is a number greater than or equal to 1) , the integrated circuit comprising:a conversion operation controller that determines an interruption timing of a comparison operation in the successive approximation register A/D converter on the basis of an operation timing of a predetermined circuit that interferes with an operation of the successive approximation register A/D converter,wherein the successive approximation register A/D converter obtains the comparison result of N bits by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states (M is a number greater than or equal to 1) which follows the comparison period and in which a comparison of M bits can be performed, andan operation is interrupted in accordance with the determined interruption timing and a comparison operation of a bit where the comparison is not performed enough in the comparison period due to the interruption is performed in the ...

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Номер записи: 45
10-10-2013 дата публикации

Transmission system

Номер: US20130266055A1
Автор: Hirotaka Tamura, Tadahisa Matsumoto
Принадлежит: Fujitsu Ltd

A transmission system includes: a transmitter configured to transmit a first signal; a receiver configured to receiver a second signal from the transmitter; and a bias circuit configured to regulate a direct current bias level of an input terminal of the receiver, wherein the transmitter includes a first amplitude converter configured to convert the first signal to the second signal having a smaller amplitude than an amplitude of the first signal, wherein the receiver includes a second amplitude converter configured to convert the second signal to a third signal having a larger amplitude than the amplitude of the second signal, and wherein the first amplitude converter includes a first capacitance that restricts an amount of charge to be supplied to the receiver.

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Номер записи: 46
17-10-2013 дата публикации

High speed signaling system with adaptive transmit pre-emphasis

Номер: US20130272359A1
Автор: Andrew C. Ho, Anthony Bessios, Elad Alon, Fred F. Chen, Mark A. Horowitz, Vladimir M. Stojanovic
Принадлежит: RAMBUS INC

A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

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Номер записи: 47
24-10-2013 дата публикации

Analog-to-digital converter system and method

Номер: US20130278453A1
Автор: Jesper Steensgaard-Madsen
Принадлежит: Linear Technology LLC

An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

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Номер записи: 48
24-10-2013 дата публикации

Communication interface for galvanic isolation

Номер: US20130279549A1
Автор: Remco Van De Beek
Принадлежит: Individual

In one or more embodiments, a system is provided for communicating between different voltage domains using N+1 capacitive-coupled conductive lines to provide N communication channels. For instance, bi-directional communication (e.g., a first communication in a first direction and a second communication path in the opposite direction) may be provided using three capacitive-coupled signal paths. Two of the signal paths are used as single-ended (i.e., non-differential) signal paths. The third signal path is used to suppress voltage disturbances between two voltage domains.

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Номер записи: 49
24-10-2013 дата публикации

Capacitive isolated voltage domains

Номер: US20130279550A1
Автор: Hendrik Boezen, Martijn Bredius
Принадлежит: Individual

In one embodiment, a method of communicating data values over a three conductor interface is provided. Different data values are transmitted by generating and transmitting three respective signals to a receiver using three conductors. The first signal is maintained as a set voltage level. The second signal is alternated between a high voltage and a low voltage according to a carrier frequency. The third signal is alternated between the high and low voltages and is out of phased with the second signal. To transmit a first data value, the first signal is generated on a first conductor, the second signal is generated on a second conductor, and the third signal is generated on a third conductor. To transmit a second data value, the second signal is generated on the first conductor, the first signal is generated on the second conductor, and the third signal is generated on the third conductor.

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Номер записи: 50
14-11-2013 дата публикации

Passive Offset and Overshoot Cancellation for Sampled-Data Circuits

Номер: US20130300488A1
Автор: Hae-Seung Lee
Принадлежит: Maxim Integrated Products Inc

A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.

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Номер записи: 51
05-12-2013 дата публикации

AD CONVERTER CIRCUIT AND AD CONVERSION METHOD

Номер: US20130321189A1
Автор: Chen Yanfei, Ide Tatsuya, YOSHIOKA Masato
Принадлежит:

A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit. 1. An analog-to-digital converter circuit configured to convert an analog input signal voltage into a digital signal with a predetermined number of bits , comprising:a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage between the analog input signal voltage and an analog signal voltage corresponding to the digital signal with the number of higher-order bits;a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; andan encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital ...

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Номер записи: 52
26-12-2013 дата публикации

Decision feedback equalizer

Номер: US20130346811A1
Автор: Chan-Hong Chern, Chih-Chang Lin, Ming-Chieh Huang, Tao Wen CHUNG, Tsung-Ching HUANG, Yuwen Swei
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

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Номер записи: 53
09-01-2014 дата публикации

Hybrid analog-to-digital converter having multiple adc modes

Номер: US20140008515A1
Автор: Liping Deng, Rui Wang, Tiejun Dai
Принадлежит: Omnivision Technologies Inc

A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

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Номер записи: 54
16-01-2014 дата публикации

Mixed mode analog to digital converter and method of operating the same

Номер: US20140015702A1
Автор: Jaewon Nam
Принадлежит: Electronics and Telecommunications Research Institute ETRI

An analog to digital converter in accordance with the inventive concept may include a reference voltage generation circuit outputting first and second reference voltages; a decompression part decompressing amplitude of an analog input signal and the first and second reference voltages; a flash ADC converting the decompressed analog input signal into a first digital signal with reference to the decompressed first and second reference voltages; and a successive approximation ADC converting the analog input signal into a second digital signal according to a successive approximation operation with reference to the first digital signal and the first and second reference voltages.

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Номер записи: 55
23-01-2014 дата публикации

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE

Номер: US20140022105A1
Автор: Chan Kok Lim, Chen Xuefeng, Fogleman Eric, Ye Sheng
Принадлежит: MaxLinear, Inc.

A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns. 1. A method , comprising:detecting in a signal processing component meta-stability events; andwhen a meta-stability event is detected, handling the meta-stability event, wherein the handling comprises adjusting at least a portion of an output of the signal processing component based on detection of the meta-stability event.2. The method of claim 1 , comprising setting at least the portion of the output of the signal processing component claim 1 , when adjusting it based on detection of the meta-stability event claim 1 , to a predefined value.3. The method of claim 2 , comprising selecting the predefined value based on based on processing outcome in the signal processing component prior to or when the meta-stability event is detected.4. The method of claim 1 , wherein at least the portion of the output comprises a sequence of bits.5. The method of claim 4 , wherein sequence of bits correspond to remaining bits in a N-bit output claim 4 , starting with bit corresponding to occurrence of the meta-stability event.6. The method of claim 5 , wherein the value of N is determined claim 5 , when the signal processing component comprises an analog-to-digital convertor (ADC) ...

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Номер записи: 56
06-02-2014 дата публикации

Successive-Approximation-Register Analog-to-Digital Converter and Method Thereof

Номер: US20140035767A1
Автор: Lin Chia-Liang
Принадлежит: Realtek Semiconductor Corp.

A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data. 1. An analog-to-digital conversion apparatus , comprising:a first ADC (analog-to-digital converter) having a first resolution and a first conversion speed, for converting an analog input signal into a first digital signal, based in part on a value of a second digital signal; anda second ADC of a second resolution and a second conversion speed, for converting the analog input signal into the second digital signal;wherein the second resolution is lower than the first resolution and the second conversion speed is higher than the first conversion speed.2. The apparatus of claim 1 , wherein the first ADC comprises:a bootstrapped controller, for updating a digital code according to a decision signal and the second digital signal and generating the first digital signal based on a final value of the digital code at an end of the first process.3. The apparatus of claim 2 , wherein the first ADC comprises:a S/H (sample-and-hold) circuit configured to sample the analog input signal into a first voltage;a DAC (digital-to-analog converter) for converting a digital code into a second voltage;a summing circuit configured to generate a third voltage having a magnitude equal to a difference between the first voltage and the second voltage; anda comparator ...

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Номер записи: 57
06-02-2014 дата публикации

High Bandwidth Equalizer and Limiting Amplifier

Номер: US20140036982A1
Автор: Ali Nazemi, Namik Kocaman, Tamer Ali
Принадлежит: Broadcom Corp

Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.

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Номер записи: 58
13-02-2014 дата публикации

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS)

Номер: US20140043175A1
Автор: Chan Kok Lim, Chen Xuefeng, Fogleman Eric, Ye Sheng
Принадлежит: MaxLinear, Inc.

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision. 1. A method , comprising: generating an indication signal that indicates completion of each comparison step and indicates that an output decision for said each comparison step is valid;', 'initiating a timer based on said generated indication signal; and', 'generating a timeout signal that preempts said indication signal and forces a preemptive decision, wherein said preemptive decision sets one or more remaining bits up to, but not including, said one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value., 'in an asynchronous successive approximation register analog-to-digital converter that utilizes one or more overlapping redundant bits in each digital-to-analog converter code word2. The method according to claim 1 , comprising setting said one or more remaining bits up to claim 1 , but not including claim 1 , said one or more overlapping redundant bits in said corresponding digital-to-analog converter code word for said current comparison step to a value ...

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Номер записи: 59
13-02-2014 дата публикации

Reference Voltage Generator for Single-Ended Communication Systems

Номер: US20140044220A1
Автор: Hollis Timothy
Принадлежит: MICRON TECHNOLOGY, INC.

An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system. 1. A communication system comprising:a receiver for receiving input data from a communication channel and for receiving a reference voltage, wherein the receiver compares the input data to the reference voltage; anda generator for producing the reference voltage, wherein the generator comprises a series connection in order of a first transistor, a second transistor, and a resistor, and wherein the reference voltage is produced at a node between the second transistor and the resistor.2. The system of claim 1 , wherein a gate of the first transistor is adjustable.3. The system of claim 2 , wherein a gate of the second transistor is not adjustable.4. The system of claim 1 , wherein the first and second transistors comprise a cascoded current source.5. The system of claim 1 , wherein a first power supply voltage is coupled to the series connection at the first transistor claim 1 , and wherein a second power supply voltage is coupled to the series connection at the resistor claim 1 , and wherein the reference voltage depends on the second power supply voltage but not the first power supply voltage.6. The system of claim ...

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Номер записи: 60
06-03-2014 дата публикации

Successive equalizer for analog-to-digital converter (adc) error correction

Номер: US20140062738A1
Автор: Binning Chen, Chun-Ying Chen, Jiangfeng Wu, Lin He, Ramon Gomez, Randall Perlow, Tianwei Li, Wei-Ta Shih, Wenbo Liu
Принадлежит: Broadcom Corp

Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.

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Номер записи: 61
13-03-2014 дата публикации

Reducing the effect of elements mismatch in a sar adc

Номер: US20140070968A1
Автор: Minkle Eldho Paul, Seetharaman Janakiraman
Принадлежит: Texas Instruments Inc

An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.

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Номер записи: 62
20-03-2014 дата публикации

Receiver and receiving method

Номер: US20140079161A1
Автор: Hiroaki Arai, Shunji Miyazaki
Принадлежит: Fujitsu Ltd

A receiver including: a memory, and a processor configured to calculate a plurality of soft decision values based on a received symbol to which a plurality of bits are mapped, to select at least one first soft decision value of the plurality of soft decision values, to calculate at least one relative value of at least one second soft decision value of the plurality of soft decision values other than the at least one first soft decision value, based on the at least one first soft decision value, to store the at least one first soft decision value and the at least one relative value, in the memory, and to estimate the plurality of bits based on the at least one first soft decision value and the at least one relative value which are stored in the memory.

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Номер записи: 63
27-03-2014 дата публикации

Successive approximation register analog-to-digital converter

Номер: US20140085122A1
Автор: Jong-Kee Kwon, Tae Moon Roh, Young-Deuk Jeon
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

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Номер записи: 64
10-04-2014 дата публикации

Method for estimating capacitance weight errors and successive approximation analog to digital converter using the same

Номер: US20140097975A1
Автор: Hao-Chiao Hong, Tsung-Yin HSIEH
Принадлежит: National Chiao Tung University NCTU

A method for estimating capacitance weight errors of a digital-to-analog converter and a successive approximation (SA) analog-to-digital converter (ADC) using the same are disclosed, and the SA ADC includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC.

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Номер записи: 65
01-01-2015 дата публикации

ANALOG-TO-DIGITAL CONVERTER AND SELF-DIAGNOSIS METHOD FOR ANALOG-TO-DIGITAL CONVERTER

Номер: US20150002323A1
Автор: ARAI Kazuyuki, Sezaki Isao
Принадлежит:

An n-bit analog-to-digital converter includes a comparator that compares an analog input voltage with a comparison voltage; and a digital-to-analog converter that generates the comparison voltage in response to a result of the comparator, wherein the analog-to-digital converter outputs n-bit digital data corresponding to the analog input voltage, and wherein the analog-to-digital converter outputs a self-diagnosis result in such a way that the digital-to-analog converter generates a self-diagnosis voltage in response to the n-bit digital data and the comparator compares the analog input voltage with the self-diagnosis voltage. 1. An n-bit analog-to-digital converter comprising:a comparator that compares an analog input voltage with a comparison voltage; anda digital-to-analog converter that generates the comparison voltage in response to a result of the comparator,wherein the analog-to-digital converter outputs n-bit digital data corresponding to the analog input voltage, andwherein the analog-to-digital converter outputs a self-diagnosis result in such a way that the digital-to-analog converter generates a self-diagnosis voltage in response to the n-bit digital data and the comparator compares the analog input voltage with the self-diagnosis voltage.2. The n-bit analog-to-digital converter according to claim 1 ,wherein the self-diagnosis voltage is a higher voltage than a voltage corresponding to the n-bit digital data,wherein the self-diagnosis result indicates a failure of the n-bit analog-to-digital converter when the analog input voltage is higher than the self-diagnosis voltage.3. The n-bit analog-to-digital converter according to claim 1 ,wherein the self-diagnosis voltage is a lower voltage than voltage corresponding to the n-bit digital data,wherein the self-diagnosis result indicates a failure of the n-bit analog-to-digital converter when the analog input voltage is lower than the self-diagnosis voltage.4. The n-bit analog-to-digital converter according to ...

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Номер записи: 66
01-01-2015 дата публикации

PROCESS VARIABLE TRANSMITTER WITH VARIABLE FREQUENCY CLOCK CIRCUIT FOR REJECTION OF CLOCK SYNCHRONOUS NOISE

Номер: US20150003560A1
Автор: Flanagan Peter J., Korolev Eugene, Schulte John P., Tyson David G.
Принадлежит: Rosemount Inc.

In a process variable transmitter, a sensor signal is sampled, using a clock signal, at a sensor sampling frequency. Interference is also sampled at the sensor sampling frequency. A comparison is made to determine whether the interference at the sensor sampling frequency or harmonics of the sensor sampling frequency exceed a threshold level. If so, the clock signal is changed to adjust the sensor sampling frequency away from the frequency of the interference. 1. A process variable transmitter , comprising:a housing;a measurement circuit that receives a sampling clock signal at a first sampling frequency and samples an analog sensor signal, indicative of a sensed process variable, at the first sampling frequency, and converts the sampled analog sensor signal into a digital signal;a harmonic energy detector that receives the sampling clock signal and samples interference coupled to the housing at the first sampling frequency and generates a trigger signal if the interference meets a threshold interference value;a variable frequency clock circuit that receives the trigger signal and, in response to the trigger signal, changes the frequency of the sampling clock signal to an alternate sampling frequency, different from the first sampling frequency; anda processor that receives the digital signal and provides an output indicative of the sensed process variable.2. The process variable transmitter of wherein the variable frequency clock circuit is configured to change the frequency of the sampling clock signal to the alternate sampling frequency that is different from the first sampling frequency by a threshold frequency amount.3. The process variable transmitter of wherein the threshold frequency amount exceeds a narrow band of sensitivity corresponding to the first sampling frequency.4. The process variable transmitter of wherein the harmonic energy detector is configured to determine whether the sampled interference meets the threshold interference value at a frequency ...

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Номер записи: 67
05-01-2017 дата публикации

AD CONVERTER AND AD CONVERSION METHOD

Номер: US20170005668A1
Автор: TAKADA Hiroki, TANGODA Atsushi
Принадлежит:

A successive approximation ADC capable of reducing deterioration in AD conversion accuracy due to noise is provided. An AD converter according to an embodiment includes: a DA converter that generates a comparison voltage based on a sampling value obtained by sampling an analog signal, and a successive approximation control signal; a reference voltage generation circuit that generates a reference voltage used for the successive approximation process; a comparator that compares the comparison voltage with the reference voltage and outputs a successive approximation result; a successive approximation processing unit that generates the successive approximation control signal based on the successive approximation result; and a storage unit that stores an expected value of the AD conversion process. The reference voltage generation circuit generates the reference voltage based on the expected value stored in the storage unit. 1. An AD (Analog/Digital) converter of a successive approximation type configured to perform a sampling process and a successive approximation process on an analog signal , execute an AD conversion process , and output an AD conversion result , the AD converter comprising:a DA (Digital/Analog) converter configured to generate a comparison voltage based on a successive approximation control signal and a sampling value obtained by sampling the analog signal;a reference voltage generation circuit configured to generate a reference voltage used for the successive approximation process;a comparator configured to compare the comparison voltage with the reference voltage and output a successive approximation result;a successive approximation processing unit configured to generate the successive approximation control signal based on the successive approximation result, and to output the AD conversion result; andat least one storage unit configured to store an expected value of the AD conversion process based on the AD conversion result,wherein the reference ...

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Номер записи: 68
07-01-2016 дата публикации

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE

Номер: US20160006450A1
Автор: Chan Kok Lim, Chen Xuefeng, Fogleman Eric, Ye Sheng
Принадлежит:

Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels. 120-. (canceled)21. A method , comprising: searching through a plurality of quantization levels for a quantization level that matches an analog input; and', 'when said search for said matching quantization level fails within a particular amount of time, adjusting at least a portion of an output of said signal processing circuitry., 'in signal processing circuitry22. The method of claim 21 , wherein adjusting at least a portion of an output of said signal processing circuitry comprises setting at least said portion of said output of said signal processing circuitry to a predefined value.23. The method of claim 22 , comprising selecting said predefined value based on an outcome of processing in said signal processing circuitry prior to or when said search for said matching quantization level fails.24. The method of claim 21 , comprising selecting claim 21 , for adjusting at least a portion of an output of said signal processing circuitry claim 21 , between an output of a normal processing path and an output of a code generation path configured for handling search failures.25. The method of claim ...

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Номер записи: 69
02-01-2020 дата публикации

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with Switchable Reference Voltage

Номер: US20200007143A1
Автор: Aboudina Mohamed, ELWAN HASSAN, Emira Ahmed, Farid Ali
Принадлежит:

An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator. 1. A successive approximation register (SAR) analog to digital converter (ADC) , comprising:a SAR logic circuit configured to generate a digital input word;a DAC, configured to receive the digital input word and an analog input voltage, and to generate a first voltage based on the analog input voltage and the digital input word; a first input terminal configured to receive the first voltage, and', 'a second input terminal configured to receive a second voltage,', 'wherein the comparator is configured to generate a comparator output voltage based on the first and second voltages, wherein the comparator output voltage has a value corresponding with a sign of a difference between the first and second voltages; and, 'a comparator, comprisinga voltage reference generator, configured to generate the second voltage by selecting the second voltage from a plurality of discrete voltage options,wherein the SAR logic circuit is further configured to receive the comparator output voltage, and to generate the digital input word for the DAC based on one or more comparator output voltages received from the comparator.2. The SAR ADC of claim 1 , wherein the voltage reference ...

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Номер записи: 70
02-01-2020 дата публикации

METHOD AND SYSTEM FOR AN ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH WORD COMPLETION ALGORITHM

Номер: US20200007144A1
Автор: Zabroda Oleksiy
Принадлежит:

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated. 1. A method for communication , the method comprising: sampling input signals at inputs of the plurality of switched capacitors;', 'comparing, by the comparator, signals at outputs of the plurality of switched capacitors;', 'sensing whether a metastability condition exists for the comparator a using the timer and setting a metastability flag upon each metastability detection for each bit to be evaluated;', 'increasing a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal;', 'decreasing a value of the tunable timer time interval if no metastability flags are set;', 'using the metastability flags for a word completion in cases when not all bits have been evaluated; and', 'configuring an output value of the SAR ADC based on a final value of the successive approximation register and word completion., 'in a successive approximation register analog-to-digital converter (SAR ADC) comprising a plurality of switched capacitors, a comparator, a ...

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Номер записи: 71
14-01-2016 дата публикации

DUAL-COMPARATOR CIRCUIT WITH DYNAMIC VIO SHIFT PROTECTION

Номер: US20160011245A1
Автор: Gerber Johannes, KUHN RUEDIGER, QAIYUM ASIF, RUCK BERNHARD
Принадлежит:

A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin| Подробнее

Номер записи: 72
12-01-2017 дата публикации

ANALOG-TO-DIGITAL CONVERTERS FOR SUCCESSIVE APPROXIMATION INCORPORATING DELTA SIGMA ANALOG-TO-DIGITAL CONVERTERS AND HYBRID DIGITAL-TO-ANALOG CONVERTERS WITH CHARGE-SHARING AND CHARGE REDISTRIBUTION

Номер: US20170012633A1
Автор: Bosi Alessandro, Ghittori Nicola, Nani Claudio, Venca Alessandro
Принадлежит:

An A/D converter including a sample and hold circuit, first and second A/D converters and a combination circuit. The sample and hold circuit samples an analog input signal to generate bits. The first A/D converter generate a first digital signal based on the analog input signal and includes charge-sharing and charge-redistribution D/A converters that convert respectively a most-significant-bit and a first least significant bit. The first digital signal is generated based on outputs of the charge-sharing and charge redistribution D/A converters. The second A/D converter generates a second digital signal based on an output of the first A/D converter and includes a delta sigma D/A converter, which converts a second least significant bit. The second digital signal is generated based on an output of the delta sigma D/A converter. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. 1. An analog-to-digital converter comprising:a sample and hold circuit configured to sample an analog input signal to generate a plurality of bits; a charge-sharing digital-to-analog converter configured to convert a first most-significant-bit of the plurality of bits, and', 'a charge redistribution digital-to-analog converter configured to convert a first least significant bit of the plurality of bits,', 'wherein the first digital signal is generated based on an output of the charge-sharing digital-to-analog converter and an output of the charge redistribution digital-to-analog converter;, 'a first analog-to-digital converter configured to generate a first digital signal based on the analog input signal, comprising'}a second analog-to-digital converter configured to generate a second digital signal based on an output of the first analog-to-digital converter, wherein the second analog-to-digital converter comprises a delta sigma digital-to-analog converter, wherein the delta sigma digital-to-analog converter is configured to convert a second least ...

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Номер записи: 73
12-01-2017 дата публикации

METHOD AND A DEVICE FOR ANALOG-TO-DIGITAL CONVERSION OF SIGNALS, CORRESPONDING APPARATUS

Номер: US20170012635A1
Автор: Faravelli Roberto, Poli Salvatore, Quartiroli Matteo, Tripoli Giovanni Carlo
Принадлежит:

One or more first signals and one or more second signals, wherein the second signal(s) are slowly varying or low frequency signals in comparison with the first signals and are converted from analog to digital by sampling the first signals and the second signals to produce samples thereof for analog-to-digital conversion, subjecting the samples of the first signals to conversion to digital at a certain conversion rate, subjecting the samples of the second signal to conversion to digital by segments so that these segments are subjected to conversion to digital along with the samples of the first signals at the respective conversion rate, and reconstructing digital converted samples of the second signal from the segments subjected to conversion to digital. 1. A method , comprising:sampling a first signal at a sampling rate to generate analog samples of the first signal;sampling a second signal at the sampling rate to generate analog samples of the second signal, the second signal being a low frequency signal relative to the first signal;performing conversion of the analog samples of the first signal to digital values at a conversion rate; andperforming time-segmented conversion on the analog samples of the second signal at the conversion rate to sequentially generate bits of a digital value representing the second signal.2. The method of claim 1 , wherein performing time-segmented conversion on the analog samples of the second signal at the conversion rate to sequentially generate bits of a digital value representing the second signal comprises generating N-bit segments of the digital value representing the second signal each period defined by the conversion rate along with converting the analog samples of the first signal to digital values.3. The method of claim 2 , wherein generating the N-bit segments of the second signal comprises generating the N-bit segments from the most significant bit of the digital value representing the second signal to the least significant ...

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Номер записи: 74
12-01-2017 дата публикации

SUCCESSIVE APPROXIMATION SIGMA DELTA ANALOG-TO-DIGITAL CONVERTERS

Номер: US20170012637A1
Автор: Bosi Alessandro, Ghittori Nicola, Nani Claudio, Venca Alessandro
Принадлежит:

An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter. 1. An analog-to-digital converter comprising:a first analog-to-digital converter configured to receive an analog input signal and convert the analog input signal to a first digital signal, the first analog-to-digital converter comprising a successive approximation module, wherein the successive approximation module is configured to perform a successive approximation to generate the first digital signal; suppress noise which reduces amplification and power consumption requirements of the first analog-to-digital converter, and', 'perform a delta-sigma decimation process to generate the second digital signal based on the analog output of the first analog-to-digital converter; and, 'a second analog-to-digital converter configured to convert an analog output of the first-analog-to-digital converter to a second digital signal, wherein the analog output of the first analog-to-digital converter is generated based on the analog input signal, wherein the second analog-to-digital converter is a fine conversion ...

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Номер записи: 75
12-01-2017 дата публикации

Analog-to-digital converter, radiation detector and wireless receiver

Номер: US20170012638A1
Автор: Masanori Furuta, Tetsuro Itakura
Принадлежит: Toshiba Corp

According to an embodiment, an analog-to-digital converter includes a detection circuit, a first conversion circuit, a second comparator, a delay control circuit, a control circuit. A detection circuit detects a differential time signal corresponding to a delay time by using a comparison signal and a delay comparison signal. A first conversion circuit generates a differential voltage by performing time-to-voltage conversion on the differential time signal. A second comparator generates a digital delay determination signal by comparing the differential voltage and an adjustment target voltage. A delay control circuit generates a delay control signal controlling the delay time in accordance with a delay determination signal. A control circuit generates a control signal by using the delay comparison signal in an analog-to-digital conversion period.

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Номер записи: 76
12-01-2017 дата публикации

GAIN CALIBRATION FOR ADC WITH EXTERNAL REFERENCE

Номер: US20170012639A1
Автор: BOGNER Peter
Принадлежит:

Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation. 1. An analog-to-digital converter (ADC) , comprising:a passive sample and hold (SH) capacitance arranged to receive an analog input voltage;a digital-to-analog converter (DAC) capacitance coupled to the SH capacitance at a first node and switchably coupled to a reference voltage at another node of the DAC capacitor;a calibration capacitance coupled at the first node, the calibration capacitance adjustable to minimize a difference between a capacitance value of the SH capacitance and a capacitance value comprising a sum of the calibration capacitance and the DAC capacitance; and couple the SH capacitance to the reference voltage at another node of the SH capacitance;', 'couple the first node to a bias voltage;', 'couple the DAC capacitance to ground at the other node of the DAC capacitance;', 'disconnect the SH capacitance from the reference voltage and the DAC capacitance from ground and setting the first node to a high impedance state after charging the SH capacitance with the reference voltage;', 'couple the SH capacitance to ground at the other node of the SH capacitance;', 'couple the DAC capacitance to the reference voltage at the other node of the DAC capacitance;', 'compare an injected voltage from the SH capacitance to an injected voltage from the DAC capacitance at the first node;', 'place a comparator coupled to the first node on a trip point of the comparator when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are equal; and', 'detect a sign of a voltage magnitude deviation between ...

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Номер записи: 77
14-01-2016 дата публикации

SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER

Номер: US20160013803A1
Автор: Kinget Peter, KUPPAMBATTI Jayanth, Shen Junhua
Принадлежит:

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. 1. A system for providing a pipelined Analog-to-Digital Converter , comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal;', 'at least two reference capacitors that are charged to a reference voltage;', 'at least two sampling capacitors that are charged to a sampling voltage; and', 'a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage., 'a first multiplying Digital-to-Analog Converter (MDAC) stage comprising2. The system of claim 1 , wherein the first MDAC stage further comprises a first current source coupled to a first of the at least two reference capacitors and a ...

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Номер записи: 78
11-01-2018 дата публикации

FORWARD ISOLATION IN RADIO-FREQUENCY SWITCHES USING INTERNAL REGULATOR

Номер: US20180013420A1
Автор: HO Chu-hsiung
Принадлежит:

A radio-frequency switch includes a series field-effect transistor, a shunt field-effect transistor having a gate node, and shunt arm control circuitry configured to receive an internal regulator voltage and provide the internal regulator voltage to the gate node of the shunt field-effect transistor when the radio-frequency switch is in a stand-by mode of operation. 1. A radio-frequency switch comprising:a series field-effect transistor;a shunt field-effect transistor having a gate node; andshunt arm control circuitry configured to receive an internal regulator voltage and provide the internal regulator voltage to the gate node of the shunt field-effect transistor when the radio-frequency switch is in a stand-by mode of operation.2. The radio-frequency switch of wherein said providing the internal regulator voltage to the gate node of the shunt field-effect transistor causes the shunt field-effect transistor to be in an ON state.3. The radio-frequency switch of wherein the internal regulator voltage is between 1.0 and 1.5 V.4. The radio-frequency switch of wherein the shunt arm control circuitry is further configured to receive a voltage regulator voltage and provide the voltage regulator voltage to the gate node of the shunt field-effect transistor when the radio-frequency switch is in an active ON mode of operation.5. The radio-frequency switch of wherein the shunt arm control circuitry is further configured to provide the voltage regulator voltage to the gate node of the shunt field-effect transistor when the voltage regulator voltage is greater than the internal regulator voltage and to provide the internal regulator voltage to the gate node of the shunt field-effect transistor when the voltage regulator voltage is less than the internal regulator voltage.6. The radio-frequency switch of wherein the shunt arm control circuitry is further configured to receive a charge pump voltage and provide the charge pump voltage to the gate node of the shunt field-effect ...

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Номер записи: 79
11-01-2018 дата публикации

CIRCUIT DEVICE, PHYSICAL QUANTITY DETECTION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20180013441A1
Автор: Haneda Hideo
Принадлежит:

A circuit device includes a control circuit having a successive approximation register, a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register, and a comparison circuit adapted to compare an analog input signal and an output signal from the D/A conversion circuit with each other, the control circuit includes an upper limit value register and a lower limit value register adapted to respectively hold an upper limit value and a lower limit value of a conversion range, and increases the upper limit value or decreases the lower limit value in the case in which the same comparison result has been output by the comparison circuit a predetermined number of times or more. 1. A circuit device adapted to perform A/D conversion on an analog input signal , comprising:a control circuit having a successive approximation register adapted to hold successive approximation data;a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register; anda comparison circuit adapted to perform a comparison process between the analog input signal and an output signal from the D/A conversion circuit, includes an upper limit value register adapted to hold an upper limit value of a conversion range of A/D conversion result data obtained by the A/D conversion of the analog input signal, and a lower limit value register adapted to hold a lower limit value of the conversion range, and', 'performs at least one of an update of increasing the upper limit value and an update of decreasing the lower limit value in a case in which the comparison circuit has output a same comparison result a predetermined number of times or more in a successive approximation process., 'wherein the control circuit'}2. The circuit device according to claim 1 , whereinin a case in which the comparison circuit has output a same comparison result the predetermined number of times or more from a first comparison in ...

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Номер записи: 80
11-01-2018 дата публикации

ANALOG-TO-DIGITAL CONVERSION DEVICE

Номер: US20180013443A1
Автор: Chao Chieh-Yuan, KANG Wen-Juh, Wang Ting-Hao
Принадлежит:

An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of the rear SAR ADCs is electrically coupled to the front SAR ADC and is configured to receive the analog input signal and the corresponding group of higher bits in response to the different time periods. The rear SAR ADCs convert the analog input signal into a group of lower bits of the digital output signal corresponding to the time period of the group of higher bits. 1. An analog-to-digital conversion device comprising:a clock circuit configured to generate p multi-phase clocks;a front successive-approximation analog-to-digital converter (SAR ADC) electrically coupled to the clock circuit, and configured to convert an analog input signal into p groups of higher bits of a digital output signal in response to different time periods according to the p multi-phase clocks; anda plurality of rear SAR ADCs each electrically coupled to the clock circuit and the front SAR ADC, and configured to receive the analog input signal and one of p groups of higher bits corresponding to each other in response to the different time periods according to the p multi-phase clocks, wherein the number of the plurality of rear SAR ADCs equals the number of phases of the p multi-phase clocks, so that the plurality of rear SAR ADCs convert the analog input signal into p groups of lower bits of the digital output signal corresponding to the time period of the p groups of higher bits; anda combining circuit electrically coupled to the clock circuit, the front SAR ADC and the rear SAR ADCs, and configured to receive the p multi-phase clocks and combine the p groups of higher bits and the p groups of lower bits that correspond to the same time period according to the p multi-phase clocks, so as to generate the digital ...

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Номер записи: 81
14-01-2016 дата публикации

GALVANIC ISOLATION INTERFACE FOR HIGH-SPEED DATA LINK FOR SPACECRAFT ELECTRONICS, AND METHOD OF USING SAME

Номер: US20160013953A1
Автор: Boggan Garry H.
Принадлежит: The Aerospace Corporation

Under one aspect of the present invention, a structure for providing galvanically isolated communication between first and second spacecraft electronic components includes a semi-insulating substrate; an input port disposed on the substrate and configured to receive a signal from the first spacecraft electronic component; a coupling structure disposed on the substrate, coupled to the input port so as to receive the signal, and configured to provide an isolated replica of the received signal as an output; a signal conditioner disposed on the substrate, coupled to the coupling structure so as to receive the isolated replica of the received signal, and configured to condition the isolated replica; and an output port disposed on the substrate, coupled to the signal conditioner so as to receive the conditioned isolated replica, and configured to provide the conditioned isolated replica to the second spacecraft electronic component. 1. A structure for providing isolated digital communication between first and second electronic components , the structure comprising:a semi-insulating substrate;a first input port disposed on the substrate and configured to receive a digital signal from the first electronic component;a first coupling structure disposed on the substrate, coupled to the first input port so as to receive the digital signal from the first input port, and configured to output an isolated digital replica of the received digital signal;a first digital signal conditioner disposed on the substrate, coupled to the first coupling structure so as to receive the isolated digital replica of the received digital signal from the first coupling structure, and configured to output a conditioned isolated digital replica;a first microstrip element disposed on the substrate, coupled to the first digital signal conditioner so as to receive the conditioned isolated digital replica from the first signal conditioner, and configured to output the conditioned isolated digital replica;a ...

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Номер записи: 82
14-01-2016 дата публикации

On-Chip AC Coupled Receiver with Real-Time Linear Baseline-Wander Compensation

Номер: US20160013955A1
Автор: Dong Yikui Jen
Принадлежит:

An on-chip AC coupled receiver with baseline wander compensation. The receiver may be used for either single ended or differential signals. The receiver includes an input terminal to receive an input signal. AC coupling circuitry is between the input terminal and a node and couples the input signal into a coupled signal at the node. A control loop senses low frequency signal content at the node and uses a linear buffer in adjusting the coupled signal at the node based on the low frequency signal content. The operation of the control loop compensates for potential baseline wander in the coupled signal. An input stage to recovers data from the coupled signal at the node. 1. An on-chip AC coupled receiver with baseline wander compensation , the receiver comprising:a first input terminal to receive a first input signal;first AC coupling circuitry between the first input terminal and a first node, the first AC coupling circuitry coupling the first input signal into a first coupled signal at the first node;a data recovery stage to recover data from the first coupled signal at the first node; anda control loop to sense low frequency signal content at the first node and to use a linear buffer in adjusting the first coupled signal at the first node based on the low frequency signal content.2. The receiver of claim 1 , wherein the control loop comprises:a low pass filter to generate a signal indicative of the low frequency signal content at the first node based on the first coupled signal at the first node,wherein the control loop uses the linear buffer to adjust the first coupled signal based on the signal indicative of the low frequency signal.3. The receiver of claim 2 , wherein the low pass filter comprises:a first resistor coupled between the first node and an input of the first buffer; andan input capacitance of the linear buffer.4. The receiver of claim 3 , wherein the control loop comprises a second resistor coupled in series between an output of the linear buffer and ...

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Номер записи: 83
14-01-2016 дата публикации

DATA LINK POWER REDUCTION TECHNIQUE USING BIPOLAR PULSE AMPLITUDE MODULATION

Номер: US20160013958A1
Автор: Hollis Timothy Mowry, MISHRA Lalan Jee
Принадлежит:

High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the “floor voltage” that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver. Additionally, data inversion pre-coding may be concatenated with the floor voltage adjustment to further maximize power savings of the interface. 1. An apparatus comprising:a termination resistor configured to receive multi-level signaling and generate corresponding polarized voltages and currents according to an amplitude of received multi-level signaling;a biasing source communicatively coupled to the termination resistor and configured to selectively generate a biasing-voltage level on the termination resistor; anda multi-level decoder communicatively coupled across the termination resistor and configured to determine respective entries from a set of compound-index entries according to the polarized voltages and currents across the termination resistor and correspondingly retrieve an associated data symbol from an array of data symbols.2. The apparatus of claim 1 , wherein the termination resistor is configured to receive a plurality of voltage levels corresponding to the received multi-level signaling and generate the corresponding polarized voltages and currents according to the combination of ...

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Номер записи: 84
10-01-2019 дата публикации

DOUBLE DATA RATE TIME INTERPOLATING QUANTIZER WITH REDUCED KICKBACK NOISE

Номер: US20190013817A1
Автор: Koli Kimmo
Принадлежит:

A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core. 1. An apparatus comprising:a first double data rate comparator circuit configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the first double data rate comparator circuit;a second double data rate comparator circuit configured to determine a relative voltage of a second differential input signal during each of the rising edge and the falling edge in the single clock cycle of the comparator clock input to the second double data rate comparator circuit;a third double data rate comparator circuit configured to determine a relative voltage of a third differential input signal during each of a rising edge and a falling edge in the single clock cycle of an inverted comparator clock input to the third double data rate comparator circuit; anda first floating voltage reference circuit configured to shift a voltage of a differential comparator input signal by a first fixed amount, and produce the first differential input signal;a second floating voltage reference circuit configured to shift the differential comparator input signal by a second fixed amount and produce the second differential input signal; anda clock inverter circuit connected to the comparator ...

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Номер записи: 85
15-01-2015 дата публикации

Serializer/deserializer apparatus with loopback configuration and methods thereof

Номер: US20150016493A1
Автор: Michael S. Harwood, Parmanand Mishra
Принадлежит: Inphi Corp

The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

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Номер записи: 86
14-01-2021 дата публикации

EFFICIENT ALL-DIGITAL DOMAIN CALIBRATION ARCHITECTURE FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

Номер: US20210013898A1
Автор: CHOI Jeongki, KIM Ryunwoo, LEE Seungyun, Park Jonghoon, RYU Jaeyoung, SONG Changhun
Принадлежит: NEWRACOM, Inc.

A method is described that is performed by a calibration system. The method includes determining a set of perturbation values for configuring an analog-to-digital converter of the calibration system; generating a set of digital test values for determining the accuracy of the analog-to-digital converter; and applying the set of perturbation values to the set of digital test values to generate a set of modified test values, wherein the set of perturbation values are digital values that are applied to the set of digital test values in the digital domain. 1. A method performed by a calibration system , the method comprising:determining a set of perturbation values for configuring an analog-to-digital converter of the calibration system;generating a set of digital test values for determining the accuracy of the analog-to-digital converter; andapplying the set of perturbation values to the set of digital test values to generate a set of modified test values,wherein the set of perturbation values are digital values that are applied to the set of digital test values in the digital domain.2. The method of claim 1 , further comprising:converting, by a digital-to-analog converter of the calibration system, the set of modified test values to generate a set of analog test values;converting, by the analog-to-digital converter, the set of analog test values to a set of test result values; anddetermining the accuracy of the analog-to-digital converter based on the set of test result values.3. The method of claim 1 , wherein the analog-to-digital converter is a successive approximation register (SAR) analog-to-digital converter.4. The method of claim 1 , further comprising:determining an analog delay in the calibration system; andadding a guard interval, based on the analog delay, to each digital test value in the set of digital test values to account for the analog delay in the calibration system.5. The method of claim 4 , wherein a guard interval is added to a start of each ...

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Номер записи: 87
09-01-2020 дата публикации

Area Efficient Single-Ended Analog-to-Digital Converter

Номер: US20200014395A1
Автор: Gu-Yeon Wei, Simon Chaput
Принадлежит: Harvard College

A single ended n-bit hybrid digital-to-analog converter is configured to receive as an input an analog signal and produce an n-bit digital output. The converter includes a split main sub-digital-to-analog converter capacitor array, a most significant bit capacitor array, and a main capacitor array. A coupling capacitor couples the main array to the split main sub-digital-to-analog convert.

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Номер записи: 88
09-01-2020 дата публикации

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with Overlapping Reference Voltage Ranges

Номер: US20200014396A1
Автор: Aboudina Mohamed, ELWAN HASSAN, Emira Ahmed, Farid Ali
Принадлежит:

An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs. 1. A successive approximation register (SAR) analog to digital converter (ADC) configured to receive an analog input which changes , and to generate a digital output word representing the analog input , the SAR ADC comprising:a SAR logic circuit configured to generate a digital input word;a DAC, configured to receive the digital input word and the analog input, and to generate a first signal based on the analog input and the digital input word; and a first input terminal configured to receive the first signal, and', 'a second input terminal configured to receive a second signal,, 'a comparator, comprisingwherein the comparator is configured to generate a comparator output based on the first and second signals, wherein the comparator output has a value corresponding with a sign of a difference between the first and second signals,wherein, at a first time, the second signal is equal to a reference signal, the first signal is equal to the analog input having a first analog input value, and the comparator is configured to generate a first comparator output based on the first and second signals of the first time, andwherein, at a second time, the second signal is equal to the ...

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Номер записи: 89
14-01-2021 дата публикации

LOW VOLTAGE DRIVE CIRCUIT WITH DIGITAL TO DIGITAL CONVERSION AND METHODS FOR USE THEREWITH

Номер: US20210014101A1
Автор: JR. Richard Stuart, Markison Timothy W., Morrison Gerald Dale, Seger, Van Ostrand Daniel Keith
Принадлежит: SigmaSense, LLC.

A low voltage drive circuit (LVDC) includes a digital to digital converter that converts transmit digital data into a digital input signal, wherein the transmit digital data is synchronized to a clock rate of a host device and the digital input signal is synchronized to a clock rate of a bus to which the LVDC is coupled. An output limited digital to analog is converter converts the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit conveys the analog outbound data as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency. 1. A low voltage drive circuit (LVDC) comprises:a digital to digital converter configured to convert transmit digital data into a digital input signal;an output limited digital to analog converter configured to convert the digital input signal into analog outbound data by generating a DC component and converting the digital input signal into an oscillating component at a first frequency, wherein magnitude of the oscillating component is limited to a range that is less than a difference between magnitudes of power supply rails of the LVDS, and wherein the oscillating component and the DC component are combined to produce the analog outbound data;a receive analog to digital circuit configured to convert analog inbound data into received digital data; and convert the analog outbound data into an analog transmit signal;', 'drive the analog transmit signal onto a bus, wherein the analog outbound data is represented within the ...

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Номер записи: 90
09-01-2020 дата публикации

EHF Receiver Architecture with Dynamically Adjustable Discrimination Threshold

Номер: US20200014567A1
Автор: Kyles Ian A., Seitz Norbert
Принадлежит:

An EHF receiver that determines an initial slicing voltage level and dynamically adjusts the slicing voltage level and/or amplifier gain levels to account for characteristics of the received EHF electromagnetic data signal. The architecture includes an amplifier, detector, adaptive signal slicer, and controller. The detector includes a main detector and replica detector that convert the received EHF electromagnetic data signal into a baseband signal and a reference signal. The controller uses the baseband signal and reference signal to determine an initial slicing voltage level, and dynamically adjust the slicing voltage level and the gain settings of the amplifier to compensate for changing signal conditions. 1. A receiver device comprising:a detector circuit configured to receive an EHF electromagnetic signal and generate a baseband signal and an initial reference signal; and [ sample the initial reference signal to determine an initial reference signal setting value,', 'during a first time period, determine a difference between the initial reference signal setting value and a reference signal setting value, and', 'during a second time period, adjust the initial reference signal setting value when the determined difference is more than a reference signal threshold value;, 'a reference signal feedback loop configured to, sample the baseband signal,', 'compute an average baseband signal using a plurality of samples of the baseband signal to determine an average baseband value,', 'determine a difference between the average baseband value and the initial reference signal setting value, and', 'compute an initial discrimination threshold voltage level value using the determined difference; and, 'a baseband signal feedback loop configured to, 'an amplifier configured to apply the initial discrimination threshold voltage level value to the baseband signal., 'a voltage slicer circuit comprising2. A method comprising:generating a baseband signal and an initial reference ...

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Номер записи: 91
21-01-2016 дата публикации

METHOD AND DEVICE FOR USE IN ANALOG-TO-DIGITAL CONVERSION

Номер: US20160020778A1
Автор: BOGNER Peter, Fyvie Clifford, Suravarapu Niranjan Reddy, Wappis Herwig
Принадлежит:

Disclosed herein are embodiments of a precharge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when said sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a precharge sample-and-hold circuit and of methods to operate a precharge sample-and-hold circuit in an analog/digital converter are also disclosed.

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Номер записи: 92
19-01-2017 дата публикации

OFFSET CORRECTION FOR SENSE AMPLIFIER

Номер: US20170019119A1
Автор: FOREY Simon, MISHRA Parmanand
Принадлежит:

The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well. 1. An apparatus comprising:an equalizer module comprising a first Continuous Time Linear Equalizer (CTLE) and a second CTLE, an output of the first CTLE being connected to an input of the second CTLE, the second CTLE generating a first equalizer output signal from an input signal, the input signal being characterized by a first sampling frequency;a Digital to Analog Converter (DAC) generating an offset correction signal determined at an isolation mode of the equalizer module;a first sense amplifier generating data samples by sampling the equalizer output signal from the second CTLE at the first sampling frequency using the offset correction signal; the first CTLE is shut and the second CTLE operates in a common mode and generates a second equalizer output signal;', 'the first sense amplifier generates a predetermined number of samples at a second sampling frequency different from the first sampling frequency; and', 'the offset correction signal is determined using the predetermined number of samples., 'wherein during the isolation mode2. The apparatus of further comprising a second sense amplifier claim 1 , wherein the second sense amplifier is an edge sense amplifier.3. The apparatus of further comprising a Demultiplexor (DEMUX) for selecting the data samples from the first sense amplifier.4. The apparatus of wherein the equalizer module further comprises ...

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Номер записи: 93
03-02-2022 дата публикации

Current Operative Analog to Digital Converter (ADC)

Номер: US20220038109A1
Автор: HUYNH Phuong
Принадлежит: SigmaSense, LLC.

An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW). 1. An analog to digital converter (ADC) comprising:an operational amplifier operably coupled to a load, wherein, when enabled, the operational amplifier configured to produce a load voltage based on charging of a feedback capacitor that is operably coupled to an input of the operational amplifier and to an output of the operational amplifier, wherein the input of the operational amplifier is coupled to the load via a single line; receive the load voltage;', 'receive a reference voltage; and', 'compare the load voltage to the reference voltage and generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage;, 'an M-bit analog to digital converter (ADC), wherein when enabled, the M-bit ADC operably coupled and configured tomemory that stores operational instructions;one or more processing modules operably coupled to the M-bit ADC and the memory, wherein, when enabled, the one or more processing modules is configured to execute the operational instructions to process the first digital output signal to generate a second digital output signal that is representative of the ...

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Номер записи: 94
18-01-2018 дата публикации

Method And System For An Analog-To-Digital Converter With Near-Constant Common Mode Voltage

Номер: US20180019760A1
Автор: Liu Hao, Tang Yongjian
Принадлежит:

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V/128+V/256+V/512+V/1024 when m equals 4 and where Vis the full-scale voltage of the ADC. 1. A method for communication , the method comprising: sampling an input voltage by closing the first and second sampling switches;', 'opening the first and second sampling switches and comparing a voltage level between the input lines;', 'iteratively switching the N switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels; and', 'iteratively switching the M single switched capacitors between ground and different reference voltages., 'in an analog-to-digital converter (ADC) comprising a first sampling switch on a first input line to the ADC, a second sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on said first input line, and N switched capacitor pairs and M single switched capacitors on said second input line2. The method according to claim 1 , wherein the different reference voltages are equal to Vref/2where x ranges from 0 to M−1.3. The method according to claim 2 , wherein a magnitude of a common mode offset of the ADC is less than V/128+V/256+V/512+V/1024 when M equals 4 and ...

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Номер записи: 95
17-01-2019 дата публикации

CAPACITIVE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER

Номер: US20190020351A1
Автор: FAN Shuo
Принадлежит:

A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code. 1. A capacitive successive approximation analog-to-digital converter , comprising:a first capacitor array comprising N first capacitors, wherein N is a number of bits of a binary code output by the capacitive successive approximation analog-to-digital converter, and N is a positive integer greater than or equal to 3;a second capacitor array comprising N second capacitors;a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage, wherein the first voltage is determined according to the common mode voltage and the reference voltage, and the second voltage is determined according to the common mode voltage and a ground voltage;a first switch connected between the voltage generation circuit and upper plates of the N first capacitors;a second switch connected between the voltage generation circuit and upper plates of the N second capacitors;N third switches correspondingly connected to lower plates of the N first capacitors ...

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Номер записи: 96
17-01-2019 дата публикации

ENDOSCOPY ARRANGEMENT WITH GALVANIC ISOLATION AND ASSOCIATED METHOD

Номер: US20190020507A1
Автор: Hornbach Mathias, KÖHLER ALEXANDER
Принадлежит: Scholly Fiberoptic GMBH

So as to improve the quality of the transmission of a signal, in particular an image or video signal, from an image sensor () to a camera controller () of an endoscopy arrangement () by a cable () while maintaining electrical safety standards, a first circuitry arrangement that is used to transmit the signal within the cable () is embodied with galvanic isolation from a second circuitry arrangement () that is used to further process the signal within the camera controller (). The galvanic isolation () is formed to this end, preferably downstream of a proximal end () of the cable () in the signal direction, and the first circuitry arrangement has an impedance matching circuit (), preferably with a passive embodiment, for example arranged at the proximal end () of the cable () or in the camera controller (). This impedance matching circuit is configured to compensate signal distortions, which arise during the transmission of the signal that is produced by the image sensor () to the camera controller (), preferably in such a way that a frequency spectrum of the signal that is produced by the image sensor () can be reproduced. 11. An endoscopy arrangement () comprising:{'b': 2', '3, 'an endoscope (), which has an image sensor (),'}{'b': 5', '19, 'a camera controller () having signal processing circuitry (),'}{'b': 4', '3', '5, 'a cable (), which is configured to transmit a signal from the image sensor () to the camera controller (),'}{'b': 6', '2', '19', '5, 'a galvanic isolation () formed between the endoscope () and the signal processing circuitry () of the camera controller (), and'}{'b': 8', '8', '19', '5, 'an impedance matching circuit () configured to compensate changes in a signal form of a signal which arise due to signal transmission, the impedance matching circuit () is arranged upstream of the signal processing circuitry arrangement () of the camera controller () in the signal direction.'}216745. The endoscopy arrangement () as claimed in claim 1 , wherein ...

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Номер записи: 97
22-01-2015 дата публикации

VOLTAGE REGULATOR FOR A SERIALIZER/DESERIALIZER COMMUNICATION APPLICATION

Номер: US20150023398A1
Автор: GOPALAKRISHNAN Karthik S., Ren Guojun
Принадлежит:

The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source. The second gate is coupled to a fast node, and the second drain is coupled to the regulator output. 1. A system comprising:a memory device;a transmitter apparatus coupled to the memory device comprising:an incoming receiver device configured to receive a plurality of data streams, each of the data streams having a first data rate and characterized in a first format, the incoming receiver configured to transfer a second data stream having a second format;a serializer device coupled the incoming receiver device, the serializer device processes the second data stream to output a third data stream in a third format;a line driver comprising a power input, the line driver coupled to the serializer device to output a four data stream in a fourth format.a voltage regulator device coupled to supply power to the power input of the line driver, the voltage regulator device comprising:a wide band amplifier having an input reference voltage, Vref and an input feedback voltage ...

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Номер записи: 98
16-01-2020 дата публикации

INTEGRATED CIRCUIT AND REFERENCE VOLTAGE GENERATION CIRCUIT

Номер: US20200021303A1
Автор: SEO Young-Suk
Принадлежит:

An integrated circuit includes: a first differential buffer suitable for receiving a primary signal through a primary input terminal thereof, and receiving a secondary signal through a secondary input terminal thereof, wherein the secondary signal has a phase opposite to a phase of the primary signal; a second differential buffer suitable for receiving a first reference voltage through primary and secondary input terminals thereof; and an operational amplifier suitable for receiving a first common mode voltage of the primary and secondary output terminals of the first differential buffer and a second common mode voltage of the primary and secondary output terminals of the second differential buffer, to output the first reference voltage. 1. An integrated circuit comprising:a first differential buffer suitable for receiving a primary signal through a primary input terminal thereof, and receiving a secondary signal through a secondary input terminal thereof, wherein the secondary signal has a phase opposite to a phase of the primary signal;a second differential buffer suitable for receiving a first reference voltage through primary and secondary input terminals thereof; andan operational amplifier suitable for receiving a first common mode voltage of the primary and secondary output terminals of the first differential buffer and a second common mode voltage of the primary and secondary output terminals of the second differential buffer, to output the first reference voltage.2. The integrated circuit of claim 1 , further comprising:an analog-to-digital converter (ADC) suitable for analog-to-digital converting the first reference voltage to generate a digital code; anda digital-to-analog converter (DAC) suitable for digital-to-analog converting the digital code to generate a second reference voltage.3. The integrated circuit of claim 2 , further comprising a third differential buffer suitable for receiving an input signal based on the second reference voltage.4. The ...

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Номер записи: 99
16-01-2020 дата публикации

LATCHED COMPARATOR AND ANALOG-TO-DIGITAL CONVERTER MAKING USE THEREOF

Номер: US20200021304A1
Автор: Wegberg Roland Van
Принадлежит:

A latched comparator comprises a pre-amplifier stage with a positive input (V), a negative input (V); and a differential output (ΔV) comprising a first output (V) and a second output (V), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN) and a first cascode transistor (MN) connected at a first cascode node, the first amplifying transistor (MN) being controlled by the positive input (V) and the first cascode transistor (MN) being connected, opposite to the first cascode node, to the first output (V); a second cascode pair, comprising a second amplifying transistor (MN) and a second cascode transistor (MN) connected at a second cascode node, the second amplifying transistor (MN) being controlled by the negative input (V) and the second cascode transistor (MN) being connected, opposite to the second cascode node, to the second output (V); a first gain-boosting transistor (MN) connected between the first output (V) and the first cascode node; and a second gain-boosting transistor (MN) connected between the second output (V) and the second cascode node, wherein the first gain-boosting transistor (MN) and the second gain-boosting transistor (MN) are cross-coupled, so that the first gain-boosting transistor (MN) is controlled by the second output (V) and the second gain-boosting transistor (MN) is controlled by the first output (V). 1. A latched comparator comprising a pre-amplifier stage with:a positive input,a negative input; anda differential output comprising a first output and a second output,said pre-amplifier stage comprising:a first cascode pair, comprising a first amplifying transistor and a first cascode transistor connected at a first cascode node, said first amplifying transistor being controlled by said positive input and said first cascode transistor being connected, opposite to said first cascode node, to said first output;a second cascode pair, comprising a second amplifying transistor and a second ...

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Номер записи: 100