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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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16-07-2013 дата публикации

Shuffled LDPC decoding

Номер: US0008489962B2
Автор: John Dielissen, DIELISSEN JOHN
Принадлежит: ST-Ericsson SA, DIELISSEN JOHN, ST ERICSSON SA, ST-ERICSSON SA

An LDPC decoder iteratively decodes an LDPC code represented by a parity check matrix H consisting of a plurality of circulants based on a Log-Likelihood Ratio Belief-Propagation algorithm. First computation means (1010) compute for a next iteration symbol messages lambdakappam from a representation of a corresponding symbol value stored in a first memory 1005 and from check node messages Lambdamn from a previous iteration. A shuffler (1030) changes a sequence of the symbol message received from the first computation means (1010) in dependence on a position of the non-zero elements in a corresponding sub-matrix. Second computation means (DP-O, DP-I, DP-D-I) compute the check node messages in dependence on symbol messages received from the barrel shifter and store a representation of the computed check node message in a second memory (1015). Third computation means (1020) update the representation of the symbol values in the first memory in dependence on output of the first and second computing ...

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Номер записи: 1
09-02-2012 дата публикации

Techniques To Control Power Consumption In An Iterative Decoder By Control Of Node Configurations

Номер: US20120036410A1
Автор: David Rault, Olivier Souloumiac
Принадлежит: Silicon Laboratories Inc

A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include progressively enabling and disabling nodes of the iterative decoder to perform iterative decoding on a demodulated signal to provide a decoded signal with minimal variation of a supply voltage.

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Номер записи: 2
05-04-2012 дата публикации

Modified progressive edge-growth ldpc codes for ultra-high-speed serial optical transport

Номер: US20120084617A1
Автор: Ivan B. Djordjevic, Lei Xu, Ting Wang
Принадлежит: NEC Laboratories America Inc

Systems and methods enabling ultra-high-speed optical transport The systems and methods include receiving a modulated, encoded input stream. Channel impairments are removed using MAP equalization. Symbols are detected in the input stream to produce a stream of encoded data. The stream of encoded data is decoded with one or more low density parity check (LDPC) decoders that use an LDPC code built by modified progressive edge growth. The LDPC code is built by iteratively expanding trees from each variable node until all check nodes are connected to the respective variable node, while controlling both the local girth and the global girth of the code.

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Номер записи: 3
19-07-2012 дата публикации

MULTI-CSI (Cyclic Shifted Identity) SUB-MATRIX BASED LDPC (Low Density Parity Check) CODES

Номер: US20120185745A1
Автор: Ba-Zhong Shen, Tak K. Lee
Принадлежит: Broadcom Corp

Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

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Номер записи: 4
04-10-2012 дата публикации

Readdressing decoder for quasi-cyclic low-density parity-check and method thereof

Номер: US20120254685A1
Автор: Tai-Lai Tung, Tung-Sheng Lin, Yu-Hsien Ku
Принадлежит: MStar Semiconductor Inc Taiwan

A readdressing decoder for QC-LDPC decoding including a memory, a controller and parallel processors is provided. The memory stores a QC-LDPC matrix including sub-matrices respectively addressed with a corresponding address. The controller readdresses each of the sub-matrices into divided matrices and defines each of the divided matrices into a first address group and a second address group. The controller further respectively transmits the divided matrices of the first address group and the second address group to the parallel processors to perform correction algorithm.

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Номер записи: 5
18-10-2012 дата публикации

Method of error floor mitigation in low-density parity-check codes

Номер: US20120266040A1
Автор: Jon HAMKINS
Принадлежит: California Institute of Technology CalTech

A digital communication decoding method for low-density parity-check coded messages. The decoding method decodes the low-density parity-check coded messages within a bipartite graph having check nodes and variable nodes. Messages from check nodes are partially hard limited, so that every message which would otherwise have a magnitude at or above a certain level is re-assigned to a maximum magnitude.

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Номер записи: 6
27-12-2012 дата публикации

Systems and Methods for Error Correction Using Low Density Parity Check Codes Using Multiple Layer Check Equations

Номер: US20120331369A1
Автор: Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.

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Номер записи: 7
27-12-2012 дата публикации

Systems and Methods for Non-Binary Decoding

Номер: US20120331370A1
Автор: Changyou Xu, Chung-Li Wang, Shaohua Yang, Wu Chang, YANG Han, Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

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Номер записи: 8
28-02-2013 дата публикации

Two Low Complexity Decoding Algorithms for LDPC Codes

Номер: US20130055043A1
Автор: Attahiru Sule Alfa, Jun Cai, Telex Maglorie Ngatched
Принадлежит: Individual

In the present invention, two improved variants of the reliability-based iterative majority-logic decoding algorithm for regular low-density parity-check (LDPC) codes are presented. The new algorithms are obtained by introducing a different reliability measure for each check-sum of the parity-check matrix, and taking it into account in the computation of the extrinsic information that is used to update the reliability measure of each received bit in each iteration. In contrast to the first algorithm, the second algorithm includes check reliability that changes at each iteration. For the tested random and structured LDPC codes, both algorithms, while requiring very little additional computational complexities, achieve a considerable error performance gain over the standard one. More importantly, for short and medium block length LDPC codes of relatively large column weight, both algorithms outperform or perform just as well as the iterative decoding based on belief propagation (IDBP) with less decoding complexity.

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Номер записи: 9
30-05-2013 дата публикации

Variable Sector Size LDPC Decoder

Номер: US20130139022A1
Автор: Lei Chen, Shaohua Yang, YANG Han, Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding variably sized blocks of data in an LDPC decoder. For example, in one embodiment an apparatus includes a low density parity check decoder operable to perform decoding of a plurality of circulant sub-matrices from an H matrix, and a controller connected to the low density parity check decoder, operable to omit any of the plurality of circulant sub-matrices from the decoding if they do not contain user data.

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Номер записи: 10
04-07-2013 дата публикации

Non-binary qc-ldpc code decoding device and associated method

Номер: US20130173981A1
Автор: Chen-Yap Leong, Chung-Jay Yang, Kuo-Hsuan Liao, Yeong-Luh Ueng
Принадлежит: National Tsing Hua University NTHU

A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device comprises a first barrel-shifter, a routing network and a second barrel-shifter. The first barrel-shifter uses a constraint h′v′+h″v″=hv to shift q−1 elements of an input by j 0 positions to produce first temporary elements. The routing network connects to the first barrel-shifter, permutes the first temporary elements to produce second temporary elements if v′ of the constraint is not zero and designates the first temporary elements as the second temporary elements if v′ of the constraint is zero. The second barrel-shifter connects to the routing network and uses the constraint h′v′+h″v″=hv to shift q−1 elements of the second temporary elements by i 0 positions. A non-binary QC-LDPC decoding method is also disclosed.

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Номер записи: 11
11-07-2013 дата публикации

Error correct coding device, error correct coding method, and error correct coding program

Номер: US20130179757A1
Автор: Norifumi Kamiya
Принадлежит: NEC Corp

Disclosed are an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data for information data of length k×m bits (k, m and r are positive integers), and a cyclic addition apparatus including a k×m-bit shift register and exclusive OR. With information data of a length of k×m×L bits (L≦k), a length of (r×m×(L+1)+k×m) bits is calculated as redundant data by adding redundant data of a length of r×m×L bits calculated using the encoding apparatus L times, k×m-bit data calculated by inputting the information data of a length of k×m×L bits to the cyclic addition apparatus, and r×m-bit redundant data calculated by inputting the k×m-bit data to the encoding apparatus.

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Номер записи: 12
15-08-2013 дата публикации

Reduced complexity non-binary ldpc decoding algorithm

Номер: US20130212451A1
Автор: Majid NEMATI ANARAKI, Richard D. Barndt, Xinde Hu
Принадлежит: Stec Inc

A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

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Номер записи: 13
22-08-2013 дата публикации

Interleaving method and deinterleaving method

Номер: US20130216001A1
Автор: Mihail Petrov
Принадлежит: Panasonic Corp

An interleaving method performed by a transmitter for a communication system with quasi-cyclic low-density parity-check codes, spatial multiplexing, and T transmit antennas is used for applying permutation to N cyclic blocks of a codeword in order to map bits of the permutated cyclic blocks onto T constellation words constituting multiple spatial-multiplexing blocks from the codeword. Each cyclic block consists of Q bits.

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Номер записи: 14
26-09-2013 дата публикации

Encoder, decoder, transmitting apparatus, and receiving apparatus

Номер: US20130254638A1
Автор: Masayuki Orihashi, Shutai Okamura, Yutaka Murakami
Принадлежит: Panasonic Corp

There is provided an encoder that provides a termination sequence with a simple structure for LDPC-CC encoding and reduces an amount of the termination sequence transmitted to a transmission line. The LDPC-CC encoder connects a first encoder to a second encoder to perform encoding and thereby carry out LDPC-CC encoding, the first encoder performing encoding based on an partial parity check matrix for information bits obtained by extracting a sequence corresponding to the information bits in a parity check matrix and the second encoder performing encoding based on a partial parity check matrix for parity bits obtained by extracting a sequence corresponding to the parity bits in the parity check matrix. A termination sequence generator generates a termination sequence including the same number of bits as the memory length of the first encoder and provides the generated termination sequence as an input sequence.

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Номер записи: 15
31-10-2013 дата публикации

METHOD FOR SIGNALING INFORAMTION BY MODIFYING MODULATION CONSTELLATIONS

Номер: US20130290807A1
Автор: Sadowsky John S., Stephens Adrian P.
Принадлежит:

Methods and systems for communicating in a wireless network may distinguish different types of packet structures by modifying the phase of a modulation constellation, such as a binary phase shift keying (BPSK) constellation, in a signal field. Receiving devices may identify the type of packet structure associated with a transmission or whether the signal field is present by the phase of the modulation constellation used for mapping for the signal field. In one embodiment, the phase of the modulation constellation may be determined by examining the energy of the I and Q components after Fast Fourier Transform. Various specific embodiments and variations are also disclosed. 125-. (canceled)26. A method of decoding encoded information by a wireless communication device , comprising:receiving a data unit including encoded information comprising one or more variable length low density parity check (LDPC) codewords from a network device;decoding a length of the encoded information from a header of the data unit; determining, based at least in part on the decoded length, the length of each of the one or more LDPC codewords; anddecoding the one or more LDPC codewords.27. The method of claim 26 , wherein decoding the one or more LDPC codewords comprises claim 26 , for each of the one or more LDPC codewords:determining a plurality of variable node values; anddetermining a plurality of check node values, corresponding to parity check relationships, based on the variable node values and a parity check matrix.28. The method of claim 26 , wherein decoding the one or more LDPC codewords comprises using a Bahl claim 26 , Cocke claim 26 , Jelinek and Raviv (BCJR) algorithm.29. The method of claim 26 , wherein decoding the one or more LDPC codewords comprises using a min-sum algorithm.30. The method of claim 26 , wherein decoding the one or more LDPC codewords comprises using a plurality of decoding iterations.31. The method of claim 30 , wherein the plurality of decoding iterations ...

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Номер записи: 16
06-03-2014 дата публикации

SYMBOL FLIPPING DECODERS OF NON-BINARY LOW-DENSITY PARITY CHECK (LDPC) CODES

Номер: US20140068393A1
Автор: Chilappagari Shashi Kiran, Varnica Nedeljko
Принадлежит: MARVELL WORLD TRADE LTD.

Systems and methods are provided for decoding data. A decoder retrieves data related to a symbol and identifies a plurality of candidate values for the symbol. The decoder determines a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances, and the decoder determines whether to update a value of the symbol based at least in part on the plurality of distances. 1. A method for decoding data , the method comprising:retrieving data related to a symbol;identifying a plurality of candidate values for the symbol;determining a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances; anddetermining whether to update a value of the symbol based at least in part on the plurality of distances.2. The method of claim 1 , wherein the plurality of distances form a distance distribution claim 1 , wherein the distance distribution includes a number of check nodes associated with at least one distance in the plurality of distances.3. The method of claim 1 , wherein determining whether to update a value of the symbol is further based at least in part on a comparison between a threshold and a number of check nodes associated with a first distance in the plurality of distances.4. The method of claim 3 , further comprising modifying the threshold at a further iteration of the decoding.5. The method of claim 1 , wherein determining whether to update the value of the symbol comprises:identifying a plurality of thresholds, wherein each threshold in the plurality of thresholds corresponds to a distance in the plurality of distances, and wherein the threshold is modified as the corresponding distance is modified; andcomparing each threshold in the plurality of thresholds to the corresponding distance in the plurality of distances.6. The method of claim 1 , further comprising updating the value of the symbol when a number ...

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Номер записи: 17
13-03-2014 дата публикации

PARALLEL BIT INTERLEAVER

Номер: US20140075271A1
Автор: Petrov Mihail
Принадлежит:

A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word. 113-. (canceled)14. A bit interleaving method interleaving a codeword of quasi-cyclic low-density parity check codes , including repeat-accumulate quasi-cyclic low-density parity check codes , the bit interleaving method comprising:a permutation step of applying a permutation process to the codeword made up of N cyclic blocks each including Q cyclic block bits in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks; andan allocation step of allocating codeword bits of the codeword, after the-permutation process, to Q×N/M constellation words, each of the constellation words being made up of M constellation word bits, whereinF is a divisor of M and Q,N is not a multiple of M/F,N′ is equal to (M/F)×floor(N/(M/F)),each of N′ cyclic blocks among the N cyclic blocks is allocated to one among F×N'/M folding sections according to the cyclic block permutation rule, each of the folding sections including M/F of the cyclic blocks,(N-N′) of the cyclic blocks are excluded from the N′ cyclic blocks and include a parity section of the codeword,the cyclic block permutation rule defines allocation of the N′ cyclic blocks to the folding sections, andin the allocation step, the allocation process is applied such that the M bits include F cyclic block ...

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Номер записи: 18
27-03-2014 дата публикации

Apparatus and method for low density parity check (ldpc) encoding

Номер: US20140089766A1
Автор: Deock Gil Oh, In Ki LEE, Ji Won JUNG, Min Hyuk KIM
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Provided is a low density parity check (LDPC) encoding apparatus and method that may store M registers each including N bits, obtain N×M parity bits by performing a partial parallel operation an N×M number of times with respect to the M registers, and mutually invert subsequent N parity bits periodically, based on previous parity bits for each Nth parity bit of the N×M parity bits, respectively.

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Номер записи: 19
06-01-2022 дата публикации

Decoding Apparatus, Device, Method and Computer Program

Номер: US20220006471A1
Автор: PALANGAPPA Poovaiah
Принадлежит:

Examples relate to a decoding apparatus, a decoding device, a decoding method, a decoding computer program, and a communication device, a memory device and a storage device comprising such a decoding apparatus or decoding method. A decoding apparatus for performing iterative decoding on a codeword comprises processing circuitry comprising a plurality of processing units, and control circuitry configured to control the iterative decoding of the codeword. The iterative decoding is based on a parity-check matrix. The matrix is sub-divided into two or more partitions. The control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length. The control circuitry is configured to multiplex the utilization of the plurality of processing units across the two or more partitions of the matrix at least in the second mode of operation. 1. A decoding apparatus for performing iterative decoding on a codeword , the decoding apparatus comprising:processing circuitry comprising a plurality of processing units; andcontrol circuitry configured to control the iterative decoding of the codeword, the iterative decoding being based on a parity-check matrix, the parity-check matrix being sub-divided into two or more partitions,wherein the control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length,wherein the control circuitry is configured to multiplex utilization of the plurality of processing units across the two or more partitions of the parity-check matrix at least in the second mode of operation such that the plurality of processing units are applied to a different partition of the two or more partitions in each time slot of a plurality of time slots required for completing an iteration of the iterative ...

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Номер записи: 20
05-01-2017 дата публикации

CONTROLLER FOR A SOLID-STATE DRIVE, AND RELATED SOLID-STATE DRIVE

Номер: US20170004033A1
Автор: Maffeis Margherita
Принадлежит:

A controller for a solid state drive is proposed. The solid state drive comprises memory cells each one for storing a symbol among a plurality of possible symbols that the memory cell is designed to store. The controller comprises: 1. A controller for a solid state drive comprising memory cells each one for storing a symbol among a plurality of possible symbols that the memory cell is designed to store , wherein the controller comprises:an encoding unit for encoding information bits into encoded bits;a mapping unit for mapping the encoded bits into said symbols, wherein said symbols are determined based on a plurality of allowed symbols that the memory cells are allowed to store, said plurality of allowed symbols being a subset of the plurality of the possible symbols such that a plurality of forbidden symbols not allowed to be stored in the memory cells are defined among the plurality of the possible symbols,a demapping unit for demapping read symbols and for providing an indication of the reliability of the read symbols based on said plurality of forbidden symbols, anda soft decoding unit for soft decoding the read symbols according to said indication of the reliability of the read symbols thereby obtaining said information bits.2. The controller according to claim 1 , wherein said indication of the reliability of the read symbols comprises claim 1 , for each read symbol equal to a forbidden symbol of said plurality of forbidden symbols claim 1 , an indication that the read symbol read from a memory cell is different from an original symbol originally stored in that memory cell.3. The controller according to claim 2 , wherein said indication of the reliability of the read symbols further comprises claim 2 , for each read symbol equal to a forbidden symbol of said plurality of forbidden symbols claim 2 , an indication of the probability that the original symbol is one of the plurality of the allowed symbols.4. The controller according to claim 3 , wherein the ...

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Номер записи: 21
05-01-2017 дата публикации

DATA PROCESSING METHOD, PRECODING METHOD, AND COMMUNICATION DEVICE

Номер: US20170005749A1
Автор: Kimura Tomohiro, MURAKAMI Yutaka, Ouchi Mikihiro
Принадлежит:

An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s and a second complex signal s with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s, and Y indicates the number of bits used to generate the second complex signal s. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved. 1. A transmission device comprising:error correction encoding circuitry which, in operation, generates a first encoded data sequence from an input data sequence using a first coding rate and a first code length, and generates a second encoded data sequence from a control information sequence using a second coding rate and a second code length;mapping circuitry which, in operation, generates a first modulation symbol sequence by applying a first mapping pattern of a first modulation scheme to the first encoded data sequence, and generates a second modulation symbol sequence by applying a second mapping pattern of a second modulation scheme to the second encoded data sequence; andtransmitting circuitry which, in operation, transmits the first modulation symbol sequence and the second modulation symbol sequence, whereinthe first mapping pattern and the second mapping pattern are different from each other,the first code length and the second code length are different from each other,the first modulation scheme and the second modulation scheme are the same in the number of transmission bits per symbol, andthe first coding rate and the second coding rate are the same ...

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Номер записи: 22
04-01-2018 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20180006663A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 17280 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1800 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 45720.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 17280 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1800 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. patent application Ser. No. 14/496,654, filed on Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106180 and 10-2014-0120014, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.The present ...

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Номер записи: 23
07-01-2021 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20210006265A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. 1. A bit-interleaved coded modulation (BICM) reception method , comprising:performing demodulation corresponding to quadrature phase shift keying (QPSK);performing group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; andrestoring information bits by low-density parity check (LDPC) decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 3/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception method of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using a permutation order claim 1 , andthe permutation order corresponds to an interleaving sequence represented by the following interleaving sequence:{15 22 34 19 7 17 28 43 30 32 14 1 11 0 3 9 10 38 24 4 23 18 27 39 29 33 8 2 40 21 20 36 44 12 37 13 35 6 31 26 16 25 42 5 41}.3. The BICM reception method of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 values.5. An apparatus for transmitting a broadcast signal claim 2 , comprising:a low-density parity check (LDPC) encoder configured to encode a low-density parity check (LDPC ...

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Номер записи: 24
07-01-2021 дата публикации

INTEGRATED CIRCUIT FOR TRANSMISSION APPARATUS

Номер: US20210006266A1
Автор: MURAKAMI Yutaka, OKAMURA Shutai
Принадлежит:

Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit () searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) () switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code. 1. An integrated circuit for a transmission apparatus comprising:at least one input which, in operation, receives an input;control circuitry, which is coupled to the at least one input and which, in operation, controls:{'sub': b', 'b', 'b', 'b', 'b', 'b, 'generating a codeword sequence s having a first coding rate by performing a low density parity check (LDPC) encoding process on information bit sequence u to generate a parity bit sequence p, the codeword sequence s being made up of z×nbits, the information bit sequence u being made up of z×(n-m) bits, the parity bit sequence p being made up of z×mbits, z being an integer equal to or greater than 1, nbeing an integer equal to or greater than 1, mbeing an integer equal to or greater than 1, the codeword sequence s being a sequence having the parity bit sequence p concatenated at a latter part of the information bit sequence u, the codeword sequence s being decoded at a decoder of a communicating partner apparatus;'}{'sub': 'b', 'forming a codeword sequence sp having a second coding rate by removing one or more sets of consecutive y bits from the parity bit sequence p, by using a removing pattern indicating whether or not each set of bits from a first bit to a z×m-th bit of the parity bit ...

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Номер записи: 25
07-01-2021 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 5/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20210006268A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 4096-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 64800 and a code rate of 5/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={146 89 57 16 164 138 91 78 90 66 122 12 9 157 14 68 112 128 74 45 28 87 158 56 61 168 18 161 95 99 139 22 65 130 166 118 150 49 142 44 36 1 121 6 46 29 88 47 0 58 105 43 80 64 107 21 55 151 8 145 163 7 98 123 17 11 153 136 52 3 13 34 160 102 125 114 152 84 32 97 33 60 62 79 37 129 38 165 71 75 59 144 127 132 104 53 162 103 120 54 155 116 48 77 76 73 113 119 179 177 41 19 92 109 31 143 178 108 39 140 106 40 5 25 81 176 101 124 126 72 111 4 173 156 134 86 174 2 170 35 175 137 15 24 69 ...

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Номер записи: 26
03-01-2019 дата публикации

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

Номер: US20190007061A1
Автор: Shinohara Yuji, Yamamoto Makiko
Принадлежит: SATURN LICENSING LLC

A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology apparatus and method may be applied to LDPC encoding and LDPC decoding. 1an encoding unit configured to encode information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 24/30 on the basis of a parity check matrix of the LDPC code, whereinthe LDPC code includes information bits and parity bits,the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,the information matrix portion is represented by a parity check matrix initial value table, andthe parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including{'b': 1504', '2103', '2621', '2840', '3869', '4594', '5246', '6314', '7327', '7364', '10425', '11934', '12898', '12954}{'b': 27', '1903', '3923', '4513', '7812', '8098', '8428', '9789', '10519', '11345', '12032', '12157', '12573', '12930}{'b': 17', '191', '660', '2451', '2475', '2976', '3398', '3616', '5769', '6724', '8641', '10046', '11552', '12842}{'b': 13', '1366', '4993', '6468', '7689', '8563', '9131', '10012', '10914', '11574', '11837', ' ...

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Номер записи: 27
03-01-2019 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20190007065A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. 1. A BICM reception device , comprising:a demodulator configured to perform demodulation corresponding to 16-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 2/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={5 33 18 8 29 10 21 14 30 26 11 23 27 4 7 6 24 44 38 31 34 43 13 0 15 42 17 2 20 12 40 39 35 32 1 3 41 37 9 25 19 22 16 28 36}.'}, 'the permutation order corresponds to an interleaving sequence represented by the following'}3. The BICM reception device of claim 2 , wherein the 16-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 16 constellations.4. The BICM reception device of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 values.5. The BICM reception device of claim 4 ...

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Номер записи: 28
02-01-2020 дата публикации

Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same

Номер: US20200007166A1
Автор: Bo-Mi Lim, Heung-Mook Kim, Jae-Young Lee, Nam-Ho Hur, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

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Номер записи: 29
03-01-2019 дата публикации

OAM BASED PHYSICAL LAYER SECURITY USING HYBRID FREE-SPACE OPTICAL-TERAHERTZ TECHNOLOGY

Номер: US20190007137A1
Автор: DJORDJEVIC Ivan, Wang Ting, Zhang Shaoliang
Принадлежит:

Aspects of the present disclosure describe systems, methods, and structures for physical layer security using hybrid free-space optical and terahertz transmission technologies that advantageously overcome atmospheric characteristics that infirmed the prior art. 1. A communications system employing a hybrid free-space optical (FSO) terahertz (THz) physical layer security scheme comprising: a binary-to-nonbinary converter that converts an input binary sequence;', 'a non-binary LDPC encoder that encodes the nonbinary symbols and provides parity symbols to a mapper/modulator;', 'a multidimensional mapper that maps the nonbinary symbols; and', 'a free space optical and THz transmitter for transmitting the symbols via a FSO and THz channel(s) respectively;, 'a transmitter including a FSO and a THz receiver for receiving transmissions on the FSO and THz channel(s) respectively;', 'a nonbinary a posteriori probability (APP) demapper which receives any data from the FSO and THz receivers and the mapped/modulated parity symbols from the mapper/demodulator, said APP calculates symbol log-likelihood ratios (LLRs); and', 'a nonbinary LDPC decoder that receives the LLRs and outputs any corrected symbols transmitted., 'a receiver including2. The system of wherein the system employs N orbital angular momentum (OAM) modes in an optical domain and N OAM modes in a THz domain.3. The system of wherein nonbinary LDPC codes are chosen such that any information symbols remain intact while generalized parity-symbols are algebraically related to the information symbols.4. The system of wherein the information symbols are transmitted over the FSO and THz channels while the generalized parity symbols are transmitted over classical channel(s).5. The system of wherein multidimensional signaling is used exclusively over the FSO channels and THz channels.6. The system of wherein operating wavelength of the FSO is one selected from the group consisting of: 1550 nm claim 5 , 2 μm claim 5 , 3.85 μm ...

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Номер записи: 30
12-01-2017 дата публикации

Low density parity check encoder having length of 64800 and code rate of 5/15, and low density parity check encoding method using the same

Номер: US20170012646A1
Автор: Heung-Mook Kim, Nam-Ho Hur, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

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Номер записи: 31
12-01-2017 дата публикации

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

Номер: US20170012648A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит:

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 5400 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 720 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 10080.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 5400 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 720 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of U.S. application Ser. No. 14/496,432, filed Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106176 and 10-2014-0120011, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. Technical FieldThe present ...

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Номер записи: 32
12-01-2017 дата публикации

COMMUNICATION METHOD AND COMMUNICATION DEVICE

Номер: US20170012736A1
Автор: Herrmann Frank, Kimura Tomohiro, KLENNER Peter
Принадлежит:

A communication method includes executing a cyclic block permutation for a codeword generated based on a quasi-cyclic parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the cyclic block permutation is permutation of cyclic blocks within the codeword, and mapping each bit of the codeword for which the cyclic block permutation is executed to any one of constellation point of a non-uniform constellation. 2. The communication method according to claim 1 , wherein N is equal to 180 claim 1 , and Q is equal to 360.3. The communication method according to claim 1 , the quasi-cyclic parity-check code used for generation of the codeword is selected from a plurality of the determined quasi-cyclic parity-check codes having the code rates different from each other. 1. Technical FieldThe present disclosure relates to a digital communication field. More specifically, the present disclosure relates to bit interleavers and bit de-interleavers in a bit-interleaved coding and modulation (BICM) system using quasi-cyclic low-density parity-check codes (QC LDPC codes) and quadrature amplitude modulation (QAM).2. Description of the Related ArtIn these years, a lot of transmitters are proposed, and in the transmitters, bit interleavers are disposed between encoders that encode information bits and output codeword bits, and constellation mappers that map the codeword bits to constellations and that output modulation symbols (for example, refer to PTL1).In one general aspect, the techniques disclosed here feature a communication method including executing a cyclic block permutation for a codeword generated based on a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the codeword includes a sequence of N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks ...

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Номер записи: 33
11-01-2018 дата публикации

PARALLEL BIT INTERLEAVER

Номер: US20180013449A1
Автор: Petrov Mihail
Принадлежит:

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section. 1. A transmitting method for transmitting a codeword generated based on a quasi-cyclic low-density parity check coding scheme , the transmitting method comprising:a cyclic block permutation step of applying a cyclic block permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the cyclic blocks in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks;a bit permutation step of applying a bit permutation process to the codeword after the cyclic block permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits;a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits,a modulating step of mapping each constellation word to a modulated signal, anda transmitting step of transmitting a transmitting signal generated from the constellation words, whereinN is a multiple of M,the bit permutation rule defines the reordering of the bits of the codeword after the cyclic block permutation process, the reordering of the bit permutation rule being equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N cyclic blocks being written into a matrix row-by-row during the writing process, the written bits being ...

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Номер записи: 34
11-01-2018 дата публикации

APPARATUSES AND METHODS FOR LAYER-BY-LAYER ERROR CORRECTION

Номер: US20180013451A1
Автор: Kaynak Mustafa N., Khayat Patrick R., Parthasarathy Sivagnanam, Richardson Nicholas J.
Принадлежит:

One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit. 1. An apparatus , comprising: iteratively error correct a codeword on a layer-by-layer basis in a first mode;', 'determine on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors, wherein a layer comprises a fraction of an iteration and wherein the particular layer is a fraction other than a last fraction of a particular iteration;', 'transfer the codeword to a second error correction circuit coupled to the first error correction circuit in response to the number of parity errors in the particular layer being less than the threshold number of parity errors; and', 'iteratively error correct the codeword on the layer-by-layer basis in a second mode in response to completing a defined quantity of iterations in the first mode and in response to the number of parity errors being greater than or equal to the threshold number of parity errors for each layer of the defined quantity of iterations., 'a first error correction circuit configured to2. The apparatus of claim 1 , wherein the threshold number of parity errors is at least partially based on an adjustable ...

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Номер записи: 35
14-01-2016 дата публикации

DATA PROCESSING METHOD, PRECODING METHOD, AND COMMUNICATION DEVICE

Номер: US20160013841A1
Автор: Kimura Tomohiro, MURAKAMI Yutaka, Ouchi Mikihiro
Принадлежит:

An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s and a second complex signal s with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s, and Y indicates the number of bits used to generate the second complex signal s. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved. 1. A transmission device comprising:an error correction encoder configured to generate a first encoded data sequence from an input data sequence using a first coding rate and a first code length, and generate a second encoded data sequence using a second coding rate and a second code length;a mapper configured to generate a first modulation symbol sequence by applying a first mapping pattern of a first modulation scheme to the first encoded data sequence, and generate a second modulation symbol sequence by applying a second mapping pattern of a second modulation scheme to the second encoded data sequence; anda transmitter configured to transmit the first modulation symbol sequence and the second modulation symbol sequence, whereinthe mapper uses the first mapping pattern and the second mapping pattern that are different from each other for mapping, when (i) the first code length and the second code length are different from each other, (ii) the first modulation scheme and the second modulation scheme are the same in the number of transmission bits per symbol, and (iii) the first coding rate and the second coding rate are the same.2. A reception device ...

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Номер записи: 36
10-01-2019 дата публикации

METHOD AND APPARATUS FOR CONFIGURABLE MIMO PROCESSING IN WIRELESS COMMUNICATIONS

Номер: US20190013896A1
Автор: ANDONIEH Joseph, Cheng Gary, HANSEN Christopher James, Lynch Bradley Robert
Принадлежит:

A method in a transmitter station includes: generating payload data for transmission to a receiver station via a plurality of antennae of the transmitter station; selecting a number of transmit streams for transmission of the payload data; selecting respective modulation schemes for each of the transmit streams; according to the modulation schemes and to an active one of (i) a single-encoder mode and (ii) a per-stream encoder mode, generating the number of coded, modulated transmit streams; wherein each coded, modulated transmit stream contains a portion of the payload data; and providing the coded, modulated transmit streams to respective ones of the antennae for transmission to the receiver station. 1. A method in a transmitter station , comprising:generating payload data for transmission to a receiver station via a plurality of antennae of the transmitter station;selecting a number of transmit streams for transmission of the payload data;selecting respective modulation schemes for each of the transmit streams;according to the modulation schemes and to an active one of (i) a single-encoder mode and (ii) a per-stream encoding mode, generating the number of coded, modulated transmit streams; wherein each coded, modulated transmit stream contains a portion of the payload data; andproviding the coded, modulated transmit streams to respective ones of the antennae for transmission to the receiver station.2. The method of claim 1 , further comprising:prior to generating the coded, modulated transmit streams, selecting the active one of the encoding modes.3. The method of claim 2 , further comprising claim 2 , when the active one of the single-encoder mode and the per-stream encoding mode is the single-encoder mode:providing the payload data to a single encoder for generation of coded payload data;providing the coded payload data to a stream parser for generation of the number of coded transmit streams; andproviding the coded transmit streams to respective modulators for ...

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Номер записи: 37
14-01-2021 дата публикации

PROCESSING METHOD AND DEVICE FOR QUASI-CYCLIC LOW DENSITY PARITY CHECK CODING

Номер: US20210013901A1
Автор: Li Liguang, Xu Jin, Xu Jun
Принадлежит:

Provided are a processing method and device for quasi-cyclic low density parity check (LDPC) coding. The processing method for LDPC coding includes: determining, according to a data feature of an information bit sequence to be encoded, a processing strategy for the quasi-cyclic LDPC coding according to a data feature of an information bit sequence to be encoded; and performing, according to the processing strategy and based on a base matrix and a lifting size, the quasi-cyclic LDPC coding and rate matching output on the information bit sequence according to the processing strategy, a base matrix and a lifting value. This technical solution is able to improve adaptability and flexibility of the quasi-cyclic LDPC coding. 184-. (canceled)85. A processing method for quasi-cyclic low density parity check (LDPC) coding , comprising:determining, according to a data feature of an information bit sequence to be encoded, a processing strategy for the quasi-cyclic LDPC coding; andperforming, according to the processing strategy and based on a base matrix and a lifting size, the quasi-cyclic LDPC coding.86. The method of claim 85 , wherein the data feature comprises at least one of a length of the information bit sequence and a modulation and coding scheme (MCS) index of the information bit sequence.87. The method of claim 85 , wherein determining the processing strategy for the quasi-cyclic LDPC coding comprises determining at least one of a maximum number of systematic columns of the base matrix claim 85 , a maximum number of systematic columns of the quasi-cyclic LDPC coding claim 85 , a minimum code rate of the base matrix at a maximum length of the information bit sequence claim 85 , and a maximum information length supported by the quasi-cyclic LDPC coding.88. The method of claim 87 , wherein the maximum number of systematic columns of the base matrix is selected from at least two integer values greater than or equal to 2 and less than or equal to 32.89. The method of ...

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Номер записи: 38
09-01-2020 дата публикации

QC-LDPC DECODER, METHOD FOR PERFORMING LAYERED DECODING AND STORAGE DEVICE

Номер: US20200014402A1
Автор: Liu Yidi
Принадлежит:

A QC-LDPC decoder includes: a zero matrix monitoring circuit, configured to monitor whether a submatrix of a check matrix of QC-LDPC coding information is a zero matrix; a check node processing circuit, configured to calculate check message of the check node by using the check matrix according to variable message of a variable node if the submatrix is not a zero matrix; a variable node processing circuit, configured to update the variable message of the variable node according to the check message returned by the check node if the submatrix is not a zero matrix; and a check circuit, configured to determine whether the variable message satisfies a check standard or not. 1. A QC-LDPC decoder , comprising:a zero matrix monitoring circuit, configured to monitor whether a submatrix of a check matrix of QC-LDPC coding information is a zero matrix;a check node processing circuit, configured to calculate check message of the check node by using the check matrix according to variable message of a variable node if the submatrix is not a zero matrix;a variable node processing circuit, configured to update the variable message of the variable node according to the check message returned by the check node if the submatrix is not a zero matrix; anda check circuit, configured to determine the variable message as decoded information if the variable message satisfies a check standard, and determine that decoding fails if the number of updates of the variable message exceeds a predetermined threshold but the check standard is still not satisfied.2. The QC-LDPC decoder according to claim 1 , wherein the check matrix of the QC-LDPC coding information is divided into M layers claim 1 , M being a positive integer; and{'sup': 'th', 'the QC-LDPC decoder is configured to decode the QC-LDPC coding message from a first layer to an Mlayer.'}3. The QC-LDPC decoder according to claim 2 , further comprising a delay circuit; wherein{'sup': th', 'th, 'the delay circuit is arranged in a data ...

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Номер записи: 39
21-01-2016 дата публикации

Low Density Parity Check Decoder With Relative Indexing

Номер: US20160020783A1
Автор: Li Shu, LIU Dan, Yang Shaohua, Zuo Qi
Принадлежит:

An apparatus for low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to update variable node values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages based on the variable node to check node messages. The variable node processor and the check node processor comprise a quasi-cyclic decoder with relative indexes that refer to non-zero circulants.

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Номер записи: 40
19-01-2017 дата публикации

MULTI-ELEMENT CODE MODULATION MAPPING METHOD, DEVICE AND COMPUTER STORAGE MEDIUM

Номер: US20170019289A1
Автор: Duan Can, Tong Ningning, Xu Jin, Xu Jun, Yu Guanghui, Zhao Danfeng, Zhou Xiangchao
Принадлежит:

Disclosed is a multi-element code modulation mapping method and device, relating to communications and designed to improve communication reliability. The method includes that: multi-element domain coding is performed on a first sequence including K multi-element codes to obtain a second sequence including N multi-element codes; Kand Kare calculated according to a multi-element domain element number q and a modulation order M, wherein K*logq=K*logM, both Kand Kare integers not smaller than 2, and both q and M are power of 2; the second sequence is divided into z groups of multi-element codes with each group including Kmulti-element codes, wherein C=formula (I), and formula (II) represents rounding up; each group of multi-element codes is mapped to a constellation diagram to form KMth-order modulation symbols; and z groups of Mth-order modulation symbols are sequentially cascaded to form a modulation symbol to be sent. The present disclosure further discloses a computer storage medium. 1. A multi-element code modulation mapping method , comprising:performing multi-element domain coding on a first sequence comprising K multi-element codes to obtain a second sequence comprising N multi-element codes;{'sub': 1', '2', '1', '2', '2', '2', '1', '2, 'calculating Kand Kaccording to a multi-element domain element number q and a modulation order M, wherein K*logq=K*logM, Kand Kare both integers not smaller than 2, and q and M are both power of 2;'}{'sub': 1', '1, 'dividing the second sequence into z groups of multi-element codes with each group comprising Kmulti-element codes, wherein z=┌N/K┐, and ┌ ┐ represents rounding up;'}{'sub': '2', 'mapping each group of multi-element codes to a constellation diagram to form KMth-order modulation symbols, wherein each group of multi-element codes is mapped to at least two Mth-order modulation symbols; and'}sequentially cascading z groups of Mth-order modulation symbols to form a modulation symbol to be sent.2. The method according to ...

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Номер записи: 41
03-02-2022 дата публикации

METHOD AND APPARATUS FOR DATA PROCESSING WITH STRUCTURED LDPC CODES

Номер: US20220038115A1
Автор: Li Liguang, Xu Jin, Xu Jun
Принадлежит:

The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding. 1. A method for wireless communication , comprising:determining a code block size for Low Density Parity Check (LDPC) coding;determining a coding expansion factor Z from a set of coding expansion factors based on the code block size and a parameter kb associated with a basic check matrix, wherein the parameter kb is an integer larger than or equal to four and smaller than or equal to 64, and wherein the coding expansion factor Z is equal to a positive integer power of two minus one or a product of a positive integer power of two and a prime number; andencoding a data sequence based on the basic check matrix and the coding expansion factor Z.2. The method of claim 1 , wherein at least one value in the set of coding expansion factors is equal to a product of a positive integer power of two and a prime number.3. The method of claim 2 , wherein the prime number comprises one of: 3 claim 2 , 5 claim 2 , 7 claim 2 , 11 claim 2 , or 13.4. The method of claim 1 , wherein at least one value in the set of coding expansion factors is equal to a product of a positive integer power of two and an odd number.5. The method of claim 1 , wherein the set of coding expansion factors includes at least 6 claim 1 , 12 claim 1 , ...

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Номер записи: 42
18-01-2018 дата публикации

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

Номер: US20180019763A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, LOBETE Daniel Ansorregui, MOUHOUCHE Belkacem, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The method as claimed in claim 1 , wherein the interleaving comprises:splitting the codeword into a plurality of bit groups; andinterleaving the plurality of bit group.3. The method as claimed in claim 1 , wherein the mapping comprises:demultiplexing the bits of the interleaved codeword into parallel streams to generate cells; andmapping the cells onto the constellation points. This application is a Continuation of application Ser. No. 14/716,283 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is ...

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Номер записи: 43
18-01-2018 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20180019764A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andoutputting the interleaved codeword,wherein the interleaving is performed using the following equation using permutation order:{'sub': j', 'j, 'where Xis the j-th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}2. The bit interleaving method of claim 1 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={7 11 4 38 19 25 2 43 15 26 18 14 9 29 44 32 0 5 35 10 1 12 6 36 21 33 37 34 3 31 20 16 40 23 41 22 30 39 13 24 17 42 28 8 27},'}wherein the interleaving sequence is for a case where 64-symbol mapping is employed.3. The bit interleaving method of claim 2 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.4. The bit interleaving method of claim 3 , wherein the parallel factor is 360 claim 3 , and the bit group includes 360 bits.5. The bit interleaving method of claim 4 , wherein the LDPC codeword is represented by (u claim 4 , u claim 4 , . . . claim 4 , u) ( ...

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Номер записи: 44
21-01-2021 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF10/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20210019228A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 256-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 10/15, wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using permutation order claim 1 , and the permutation order corresponds to an interleaving sequence represented by the followinginterleaving sequence ={128 20 18 38 39 2 3 30 19 4 14 36 7 0 25 17 10 6 33 15 8 26 42 24 11 21 23 5 40 41 29 32 37 44 43 31 35 34 22 1 16 27 9 13 12}.3. The BICM reception device of claim 2 , wherein the 256-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 256 constellations.4. The BICM reception device of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 ...

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Номер записи: 45
17-01-2019 дата публикации

Transmitting method including bit group interleaving

Номер: US20190020355A1
Автор: Belkacem Mouhouche, Daniel Ansorregui Lobete, Hong-Sil Jeong, Kyung-Joong Kim, Se-Ho Myung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

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Номер записи: 46
16-01-2020 дата публикации

ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD

Номер: US20200021311A1
Автор: Ishii Kenji, Kubo Kazuo, SUGIHARA Kenya, Sugihara Takashi, Yoshida Hideo
Принадлежит: Mitsubishi Electric Corporation

Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems. 1. An error correction device , comprising at least one of:an encoder configured to encode a plurality of error correction code sequences; anda decoder configured to decode the plurality of error correction code sequences,wherein the encoder includes a predetermined plurality of encoders connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the predetermined plurality of encoders by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any one of a payload input in one system and payloads input in two or more systems, andwherein the decoder includes a predetermined plurality of decoders connected in parallel, and is configured to execute decoding processing for the plurality of error correction code sequences through use of all the predetermined plurality of decoders by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any one of a payload input in one system and payloads input in two or more systems.2. The error correction device according to claim 1 , wherein the plurality of error correction code sequences are subjected to interleaving in units of bit or symbol with respect to a transmission order among data buses to which the plurality of error correction code sequences are input.3. The ...

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Номер записи: 47
21-01-2021 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20210021284A9
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaver , comprising:a first memory configured to store a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15;a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda second memory configured to provide the interleaved codeword to a modulator for 64-symbol mapping.2. The bit interleaver of claim 1 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.3. The bit interleaver of claim 2 , wherein the parallel factor is 360 claim 2 , and the bit group includes 360 bits.6. The bit interleaver of claim 5 , wherein the permutation order corresponds to an interleaving sequence represented by the following equation:{'br': None, 'interleaving sequence={19 34 22 6 29 25 23 36 7 8 24 16 27 43 11 35 5 28 13 4 3 17 15 38 20 0 26 12 1 39 31 41 44 30 9 21 42 18 14 32 10 2 37 33 40}'} This application is a continuation of U.S. application Ser. No. 14/717,174, filed May 20, 2015, which claims the benefit of Korean Patent Application Nos. 10-2014-0061874 and 10-2015-0009141, filed May 22, 2014 and Jan. 20, 2015, which are hereby incorporated by reference herein in their entirety.The present disclosure relates generally to an interleaver and, ...

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Номер записи: 48
26-01-2017 дата публикации

ADAPTIVE DESATURATION IN MIN-SUM DECODING OF LDPC CODES

Номер: US20170026055A1
Автор: Wu Yingquan
Принадлежит:

A system implements adaptive desaturation for the min-sum decoding of LDPC codes. Specifically, when an-above threshold proportion of messages from check nodes to variable nodes (CN-to-VN messages) are saturated to a maximum fixed-precision value, all CN-to-VN messages are halved. This facilitates the saturation of correct messages and boosts error correction over small trapping sets. The adaptive desaturation approach reduces the error floor by orders of magnitudes with negligible add-on circuits. 1. A method comprising:receiving, by an electronic device, input data; andperforming, by the electronic device, min-sum decoding of the input data using a Tanner graph to generate decoded output data, the min-sum decoding including passing messages from variable nodes (VNs) to check nodes (CNs) in VN-to-CN messages and from CNs to VNs in CN-to-VN messages, each VN and CN having a value associated therewith, the values of the VNs being updated in response to CN-to-VN messages and the values of the CNs being updated in response to VN-to-CN messages; andduring performing min-sum decoding, in response to detecting that a proportion of the values of the CNs that exceed a maximum value meets a threshold condition, halving at least one of all of the CN-to-VN messages and all of the VN-to-CN messages.2. The method of claim 1 , wherein performing min-sum decoding of the input data to generate decoded output data comprises performing algorithm 3 of Table 3.3. The method of claim 1 , wherein performing min-sum decoding of the input data to generate decoded output data comprises performing algorithm 4 of Table 4.4. The method of claim 1 , wherein performing min-sum decoding of the input data to generate decoded output data comprises iteratively performing a plurality of iterations claim 1 , each iteration including passing of VN-to-CN messages followed by CN-to-VN messages claim 1 , wherein halving at least one of all of the CN-to-VN messages and all of the VN-to-CN messages is ...

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Номер записи: 49
26-01-2017 дата публикации

UNIFIED H-ENCODER FOR A CLASS OF MULTI-RATE LDPC CODES

Номер: US20170026056A1
Автор: Wu Yingquan
Принадлежит:

A quasi-cyclic LDPC encoding apparatus is disclosed wherein a matrix H of the form [0 T; D E] is used, where T is a triangular matrix and D and E are arbitrary matrices selected to improve encoding performance. T and E vary with the size of an encoded data word whereas D is maintained constant. T and E are sparse such that encoding operations performed on them are computationally simple. Likewise D and its inverse are constant and pre-computed further reducing computation. T, E, and D and the inverse of D may be constrained to be quasi-cyclic, which reduces storage required to represent them and enables the performance of encoding operations using shift registers. 3. (canceled)4. The method of claim 1 , wherein Dis pre-computed and is identical for each input data word u regardless of length.5. The method of claim 1 , wherein D claim 1 , D claim 1 , T claim 1 , E claim 1 , Hare all quasi-cyclic for all i.6. The method of claim 1 , wherein generating claim 1 , by the electronic device claim 1 , encoded data c for each input word u further comprises storing for each of D claim 1 , Dand for T claim 1 , Efor each i a first 1 in a first row for each circulant of D claim 1 , D claim 1 , T claim 1 , E.7. The method of claim 1 , wherein determining [s claim 1 , s] claim 1 , p claim 1 , and s′ claim 1 , each comprise performing barrel shifter and circulant-wise XOR operations combined into a single cycle.8. The method of claim 1 , wherein determining pcomprises using circular shift registers for calculation of each bit of p.9. The method of claim 1 , wherein D has the following properties:(i) D approaches maximum rank;(ii) D approaches maximum girth and does not contain small trapping sets;{'sup': '−1', '(iii) a pseudo inverse of D is in simple format such that the pseudo inverse Dis quasi cyclic when D is singular.'}10. The method of claim 1 , wherein Tis an identity matrix for all i.13. (canceled)14. The system of claim 11 , further comprising a memory storing D and D; ...

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Номер записи: 50
25-01-2018 дата публикации

METHOD AND APPARATUS FOR ENCODING AND DECODING LOW DENSITY PARITY CHECK CODES

Номер: US20180026660A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus includes: a low density parity check (LDPC) encoder configured to encode information bits to generate parity bits based on a parity check matrix according to a code rate of 8/15 and a code length of 64800; an interleaver configured to interleave an LDPC codeword including the information bits and parity bits; and a mapper configured to map the interleaved LDPC codeword onto constellation points, wherein the parity check matrix comprises an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits, and the information matrix part is defined by a specific table indicating indices of rows at which a value “1” is positioned in a 0-th column of an i-th column group in the parity check matrix. 2. The transmitting apparatus of claim 1 , wherein the table represents indices of rows at which a value “1” is are positioned in a 0-th column of an i-th column group in the parity check matrix used in the encoding claim 1 , where i is an integer greater than or equal to “0”. This is a continuation of U.S. application Ser. No. 14/716,053 filed May 19, 2015. The disclosures of which is incorporated herein in its entirety by reference.Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to encoding and decoding Low Density Parity Check (LDPC) codes, and more particularly, to encoding and decoding LDPC codes which perform LDPC encoding and decoding based on a parity-check matrix.In a communication/broadcasting system, link performance may considerably deteriorate due to various types of noises, a fading phenomenon, and inter-symbol interference (ISI) of a channel. Therefore, to implement high-speed digital communication/broadcasting systems requiring high data throughput and reliability like next-generation mobile communications, digital broadcasting, and portable Internet, it has been required to develop technologies to overcome the noises, the fading, ...

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Номер записи: 51
10-02-2022 дата публикации

METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN COMMUNICATION OR BROADCAST SYSTEM

Номер: US20220045785A1
Автор: AHN Seokki, JANG Min, JEONG Hongsil, KIM Jaeyoel, KIM Kyungjoong, MYUNG Seho
Принадлежит:

The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transfer rate beyond a 4G communication system, such as LTE. One embodiment of the present invention provides a method for channel encoding in a communication system, the method comprising: encoding second data, using an outer channel code; determining a value corresponding to first data; arranging the encoded second data in a block size unit corresponding to the second data, based on the determined value; and encoding the arranged second data, using an inner channel code. 1. A method of channel decoding performed by a receiver in a communication system , the method comprising:receiving a first signal and a second signal corresponding to input bits;identifying first values based on the first received signal and second values based on the second received signal;identifying groups of the first values and groups of the second values, each of the groups of the first values and the groups of the second values having a bit group size;performing quasi-cyclic shifting of the groups of the second values based on the bit group size and an integer;combining the groups of the first values and the quasi-cyclic shifted groups of the second values;performing inner decoding, based on an inner channel code, on the combined values;performing outer decoding, based on an outer channel code, on an output of the inner decoding; andidentifying the input bits that indicate first data from an output of the outer decoding,wherein the integer is identified as a difference between a first cyclic shift value applied to the groups of the first values and a second cyclic shift value applied to the groups of the second values, andwherein second data is identified based on the first cyclic shift value, in case that the outer decoding is successful.2. The method of claim 1 , wherein:the outer channel code includes at least one of cyclic redundancy check (CRC) code or Bose-Chaudhuri-Hocquenghem (BCH) ...

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Номер записи: 52
24-01-2019 дата публикации

LOW-COMPLEXITY LDPC ENCODER

Номер: US20190028117A1
Автор: Bhatia Aman, CAI Yu, Kumar Naveen, Prabhakar Abhiram, XIONG Chenrong, Zhang Fan
Принадлежит:

Techniques are described for encoding information data bits using a low-density parity-check matrix optimized for a Low-Density Parity-Check (LDPC) encoder. In an example, the parity-check matrix includes a first matrix and a second matrix. The second matrix is a square matrix, and is also a block diagonal matrix that includes a set of square submatrices located on the diagonal of the block diagonal matrix. An intermediate vector is generated based on the information data bits and the first matrix, and a parity vector of a codeword is generated based on the intermediate vector and the second matrix. 1. A computer-implemented method of encoding an information vector , the computer-implemented method comprising:receiving, by a computer system, the information vector to be encoded into a low-density parity-check (LDPC) codeword; the parity-check matrix includes a first matrix and a second matrix;', 'the second matrix includes a block diagonal matrix; and', 'the block diagonal matrix includes a set of square submatrices located on a diagonal of the block diagonal matrix;, 'accessing, by the computer system, a parity-check matrix, whereingenerating, by the computer system, an intermediate vector based on the information vector and the first matrix;generating a parity vector based on the intermediate vector and the second matrix; andgenerating, by the computer system, the LDPC codeword including the information vector and the parity vector.2. The computer-implemented method of claim 1 , further comprising:writing the LDPC codeword to a storage device; ortransmitting the LDPC codeword via a communication channel.3. The computer-implemented method of claim 1 , wherein generating the parity vector comprises:dividing, by the computer system, the intermediate vector into a set of intermediate sub-vectors, each intermediate sub-vector corresponding to a square submatrix of the set of square submatrices; and 'generating, by the computer system, a corresponding parity sub-vector ...

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Номер записи: 53
01-02-2018 дата публикации

TRANSMITTING APPARATUS AND NON-UNIFORM CONSTELLATION MAPPING METHOD THEREOF

Номер: US20180034586A1
Автор: Jeong Hong-Sil, LOBETE Daniel Ansorregui, MOUHOUCHE Belkacem
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The apparatus as claimed in claim 1 , wherein the constellation points as defined in the list comprises constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the list as a*, −a*, and −a, respectively, * indicating complex conjugation. This is a continuation of U.S. application Ser. No. 14/715,817 filed on May 19, 2015, the disclosures of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is translated into a complex number. M, ...

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Номер записи: 54
17-02-2022 дата публикации

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

Номер: US20220052708A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, LEE Jae-Young, LIM Bo-Mi, PARK Sung-Ik
Принадлежит:

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A method of transmitting a broadcast signal , comprising:storing a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword;performing 64-symbol mapping for generating a broadcast signal after generating the interleaved codeword; andtransmitting the broadcast signal over a physical channel, {'br': None, 'i': Y', '=X', 'j≤N, 'sub': j', 'π(j)', 'group, '0≤'}, 'wherein the interleaving is performed using the following equation using permutation order{'sub': π(j)', 'j', 'group, 'where Xis the π(j)th bit group, Yan interleaved j-th bit group, Nis the number of bit groups, and π(j) is a permutation order for bit group-based interleaving,'} {'br': None, 'interleaving sequence={19 34 22 6 29 25 23 36 7 8 24 16 27 43 11 35 5 28 13 4 3 17 15 38 20 0 26 12 1 39 31 41 44 30 9 21 42 18 14 32 10 2 37 33 40}.'}, 'wherein the permutation order corresponds to an interleaving sequence represented by the following'}2. The method of claim 1 , wherein the interleaving is performed by using the interleaving sequence before performing the 64-symbol mapping so as to distribute burst errors occurring in the broadcast signal transmitted over the physical channel.3. The method of claim 1 , wherein the ...

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Номер записи: 55
30-01-2020 дата публикации

DATA STORAGE DEVICE, OPERATION METHOD THEREOF AND STORAGE SYSTEM HAVING THE SAME

Номер: US20200036391A1
Автор: Kim Jang Hyun, KIM Jung Ae, PARK Sung Jin
Принадлежит:

A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged to with the storage based on a second parity check matrix extracted from the firmware during a second operation mode. 1. A data storage device comprising:a storage configured to store user data, firmware and a boot code; anda controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange,wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.2. The data storage device of claim 1 , wherein the first operation mode comprises an input and output mode for user data.3. The data storage device of claim 2 , wherein the second operation mode is decided among operation modes excluding the first operation mode.4. The data storage device of claim 1 , wherein the second operation mode comprises an update mode for the boot code.5. The data storage device of claim 1 , wherein the firmware comprises a set of parity check matrix codes for respective code rates of an ECC code used in the ECC engine.6. The data storage device of claim 5 , wherein the storage stores firmware which is updated as any of the parity check matrix codes is changed or another ...

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Номер записи: 56
30-01-2020 дата публикации

TRANSMISSION METHOD AND RECEPTION DEVICE

Номер: US20200036394A1
Автор: Shinohara Yuji, Yamamoto Makiko
Принадлежит:

The present technology relates to a transmission method and a reception device capable of ensuring good communication quality in data transmission by using an LDPC code. In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of bit groups of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code after the group-wise interleaving is returned to an original arrangement. The present technology can be applied, for example, to the case of performing data transmission by using an LDPC code or the like. The present technology relates to a transmission method and a reception device, and more particularly, to a transmission method and a reception device that can ensure good communication quality, for example, in data transmission using an LDPC code.Low density parity check (LDPC) codes have high error correction capability, and in recent years, have been widely adopted in transmission schemes such as digital broadcasting, for example, digital video broadcasting (DVB)-S.2, or DVB-T.2, DVB-C.2, in Europe or the like or advanced television systems committee (ATSC) 3.0 or the like in the United States or the like (refer to, for example, Non-Patent Document 1).With recent researches, it has been found that, similarly to turbo codes and the like, in LDPC codes, performance close to the Shannon limit is obtained as the code length is increased. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, features that a block error probability characteristic is good and so-called error floor phenomenon observed in a decoding characteristic of turbo code or the like hardly occurs are also mentioned as an advantage.In data transmission using an LDPC code, for example, the LDPC code becomes a symbol of quadrature modulation (digital modulation) such as quadrature phase shift keying (QPSK) (that is, the LDPC code is symbolized), and the symbol is mapped to a signal point of ...

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Номер записи: 57
09-02-2017 дата публикации

METHOD AND APPARATUS FOR REDUCING IDLE CYCLES DURING LDPC DECODING

Номер: US20170041024A1
Автор: CHANG Yuan-Mao, YEO Engling
Принадлежит:

There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel. 1. A method of decoding codewords in conjunction with a low-density parity-check (LDPC) code , the method comprising:receiving a first codeword and a second codeword over a data channel, wherein a first code matrix is configured to be used to decode the first codeword, and wherein a second code matrix is configured to be used to decode the second codeword; and during a first time period, reading a first layer of the first code matrix, and', 'during a second time period, (i) updating the first layer of the first code matrix and (ii) reading a first layer of the second code matrix,, 'decoding the first codeword and the second codeword, wherein decoding the first codeword and the second codeword comprises'}wherein the first layer of the first code matrix is updated at least in part simultaneously with reading the first layer of the second code matrix such that the first codeword and the second codeword are decoded at least in part in parallel.2. The method of claim 1 , further comprising:receiving a third codeword, wherein a third code matrix is configured to be used to decode the third codeword; and 'during a third time period, (i) updating the first layer of the second code matrix and (ii) reading a first layer of the third code matrix.', 'decoding the second codeword and the third codeword, wherein decoding the second codeword and the third codeword comprises'}3. The method of claim 2 , further comprising:receiving a fourth codeword, wherein a fourth code ...

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Номер записи: 58
09-02-2017 дата публикации

TRANSMITTER, RECEIVER, TRANSMISSION METHOD, AND RECEPTION METHOD

Номер: US20170041025A1
Автор: Kimura Tomohiro, MURAKAMI Yutaka, Ouchi Mikihiro
Принадлежит:

One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence. 1. A transmission method using a plurality of coding schemes , the transmission method comprising:selecting one coding scheme from the plurality of coding schemes, encoding an information sequence by using the selected coding scheme to obtain an encoded sequence;modulating the encoded sequence to obtain a first modulated signal and a second modulated signal; andapplying a phase change to at least one of the first modulated signal and the second modulated signal while regularly changing a degree of the phase change, and transmitting the at least one of the first modulated signal and the second modulated, whereinthe plurality of coding schemes include at least a first coding scheme and a second coding scheme,the first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix,the second coding scheme is a coding scheme with a second coding rate different from the first coding rate and obtained after ...

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Номер записи: 59
08-02-2018 дата публикации

Zero padding apparatus for encoding variable-length signaling information and zero padding method using same

Номер: US20180041226A1
Автор: Heung-Mook Kim, Jae-Young Lee, Sun-Hyoung Kwon, Sung-Ik Park
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

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Номер записи: 60
12-02-2015 дата публикации

ENCODING METHOD AND SYSTEM FOR QUASI-CYCLIC LOW-DENSITY PARITY-CHECK CODE

Номер: US20150046768A1
Автор: Hu Junqiang, Wang Ting
Принадлежит:

A method and system are provided. The method includes applying a quasi-cyclic matrix M to an input vector X of encoded data to generate a vector Y. The method further includes applying a matrix Q to the vector Y to generate a vector Z. The method also includes recursively generating, using a processor, parity check bits P for the encoded data from the vector Z and an identity matrix variant I. The encoded data includes quasi-cyclic low-density parity-check code. The identity matrix variant t is composed of Toeplitz sub-matrices. 1. A method , comprising:applying a quasi-cyclic matrix M to an input vector X of encoded data to generate a vector Y;applying a matrix Q to the vector Y to generate a vector Z; andrecursively generating, using a processor, parity check bits P for the encoded data from the vector Z and an identity matrix variant I*,wherein the encoded data comprises quasi-cyclic low-density parity-check code, and the identity matrix variant I* is composed of Toeplitz matrices.2. The method of claim 1 , further comprising combining the encoded data with the parity check bits to form one or more encoded output signals.3. The method of claim 1 , wherein said applying steps are performed using feedback shift registers.4. The method of claim 1 , further comprising receiving a parity check matrix H of quasi-cyclic low-density parity-check code claim 1 , wherein a rank r of the parity check matrix H is less than a number of rows of the parity check matrix H claim 1 , and wherein the quasi-cyclic matrix M is a subset of the parity check matrix H claim 1 , generated by removing at least some circulants from the parity check matrix H7. The method of claim 4 , further comprising generating a matrix D from the at least some circulants removed from the parity check matrix H claim 4 , wherein the at least some circulants that are removed from the parity check matrix H are determined for removal by finding a least number of columns of circulants in the parity check matrix ...

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Номер записи: 61
07-02-2019 дата публикации

SYSTEM AND METHOD FOR ERROR CORRECTION IN DATA COMMUNICATIONS

Номер: US20190044539A1
Автор: FARD Saeed Fouladi, Graumann Peter
Принадлежит:

A method and system are provided for error correction. In an implementation, after row encoding and column encoding, additional codeword data (ACD) and modified parity (P′) are concurrently created, for each of a plurality of modified column codewords (CCW), by multiplying initial calculated parity P by a generator matrix G. In an example implementation, each CCW′ includes an ACD portion and a P′ portion such that each bit in the P′ portion of a selected CCW is present in the ACD portion for one of the other CCW′. In contrast to known approaches, in an implementation the method and system described herein provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords generated according to the method and system described herein, each bit in the modified parity in one modified codeword is present in another codeword. 1. An encoder comprising:a processor;a parity memory in communication with the processor;a first encoder memory storing a generator matrix; and storing, in the parity memory in a first memory state, a plurality R of row codewords comprising R rows of raw data and created row parity, the plurality of row codewords defining initial column codeword data ICD arranged in N columns;', 'column encoding the initial column data ICD into a plurality N of initial column codewords, and storing, in the parity memory in a second memory state, the plurality N of initial column codewords, each of the plurality N of initial column codewords having a portion of the ICD and having a computed initial parity P;', 'concurrently creating for each of the N modified column codewords (CCW′), additional column codeword data (ACD) and modified parity (P′) by multiplying the initial parity P by a generator matrix G, each CCW′ including an ACD portion and a P′ portion such that each bit in the P′ portion for a selected CCW′ ...

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Номер записи: 62
06-02-2020 дата публикации

APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM

Номер: US20200044665A1
Автор: Liu Xiaojian, Ma Liang, Wei Yuejun, Zeng Xin, Zheng Chen
Принадлежит: Huawei Technologies CO.,Ltd.

This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z≥K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices. 3. The device according to claim 2 , wherein in obtaining the encoding matrix H by replacing each element of the LDPC base graph with a matrix of Z rows and Z columns claim 2 , the processor is configured to:replace each element of value 0 in the LDPC base graph with an all zero matrix of Z rows×Z columns; and{'sub': i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j', 'i,j, 'replace a {row index i, column index j} element of value 1 in the LDPC base graph by a circular permutation matrix I(P) of Z rows×Z columns, wherein the circular permutation matrix I(P) is obtained by circularly shifting an identity matrix of Z rows×Z columns to the right Ptimes, wherein P=mod (V, Z), Vis a shift value corresponding to a lifting factor set index of Z, Vis an integer, and V≥0.'}4. The device according to claim 1 , wherein K=22×Z.5. The device according to claim 1 , wherein the input sequence is c={c claim 1 ,c claim 1 ,c claim 1 , . . . claim 1 ,c} claim 1 , the encoded sequence is d={d claim 1 , d claim 1 , d claim 1 , . . . claim 1 , d} claim 1 , wherein c(i=0 claim 1 , 1 claim 1 , . . . K−1) are information bits claim 1 , d(j=0 claim 1 , 1 claim 1 , . . . N−1) are encoded bits claim 1 , N is a positive integer claim 1 , and N=66×Z.7. The ...

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Номер записи: 63
06-02-2020 дата публикации

SYSTEMS AND METHODS FOR DECODING LOW DENSITY PARITY CHECK ENCODED CODEWORDS

Номер: US20200044666A1
Автор: CHANG Yuan-Mao
Принадлежит: NYQUIST SEMICONDUCTOR LIMITED

The present disclosure relates to methods and systems for decoding a low density parity check (LDPC) encoded codeword. The methods may include receiving a codeword over a data channel. The codeword may be encoded with a preset number of data bits having one or more shortened data bits. The methods may also include obtaining a parity check matrix that defines relationships between a plurality of variable nodes and a plurality of check nodes. The methods may further include decoding the codeword by iteratively estimating values with respect to the codeword at the plurality of variable nodes and the plurality of check nodes. During each iteration, a same part of the plurality of variable nodes related to one or more shortened data bits are skipped from estimation. 1. A method for decoding a low density parity check (LDPC) encoded codeword , the method comprising:receiving a codeword over a data channel, the codeword being encoded with a preset number of data bits having one or more shortened data bits;obtaining a parity check matrix, the parity check matrix defining relationships between a plurality of variable nodes and a plurality of check nodes, each variable node corresponding to one of the preset number of data bits; anddecoding the codeword by iteratively estimating values with respect to the codeword at the plurality of variable nodes and the plurality of check nodes,wherein during each iteration, a same part of the plurality of variable nodes related to one or more shortened data bits are skipped from estimation.2. The method of claim 1 , wherein the parity check matrix includes a plurality of layers claim 1 , each corresponding to one or more of the plurality of check nodes and having a plurality of non-zero circulants.3. The method of claim 2 , further comprising:storing a first value indicating a first number of non-zero circulants in each layer of the parity check matrix in a scheduler for decoding the codeword; andstoring a second value indicating a second ...

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Номер записи: 64
06-02-2020 дата публикации

Method and Apparatus for Encoding Quasi-Cyclic Low-Density Parity Check Codes

Номер: US20200044667A1
Автор: Declercq David, Reynwar Benedict J., Vasic Bane
Принадлежит:

This disclosure presents a method and the corresponding hardware apparatus for encoding low-density parity check codes whose parity check matrices are composed of circulant blocks. The encoder operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput. 1. A encoding method comprising:receiving as input a set of information bits;computing a first set of temporary parity check bits using the set of information bits and a first submatrix of a first region of a parity check matrix of a quasi-cyclic, low-density parity check (LDPC) code, the first submatrix composed of columns of a first subset of the parity check matrix;computing a second set of temporary parity check bits and a first set of redundancy bits using the first set of temporary parity check bits and a second submatrix of a second region of the parity check matrix, the second submatrix composed of columns of a second subset of the parity check matrix;computing a second set of redundancy bits using the second set of temporary parity check bits from the second region and a third submatrix of a third region of the parity check matrix, the third submatrix composed of columns of a third subset of the parity check matrix;combining the set of information bits, the first set of redundancy bits and the second set of redundancy bits to form a codeword of the quasi-cyclic LDPC code; andoutputting said codeword.2. The encoding method of claim 1 , wherein the first submatrix of the first region is organized into generalized layers claim 1 , where a number of the generalized layers is at least equal to the maximum block-column degree of the parity check matrix claim 1 , the method further comprising:recursively accumulating the first set of temporary parity check bits and storing the first set of temporary bits in a number of separate memories, the number of separate memories equal to the number of generalized layers.3. The ...

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Номер записи: 65
06-02-2020 дата публикации

METHOD FOR LDPC DECODING, LDPC DECODER AND STORAGE DEVICE

Номер: US20200044668A1
Автор: Liu Yidi
Принадлежит:

A LDPC decoder includes: a coded information receiving circuit, configured to receive coded information and initialize bit information of a variable node; a check node processing circuit, configured to receive first reliability information, and perform check node processing and output second reliability information; a variable node processing circuit, configured to receive the second reliability information, and perform variable node processing to update the bit information of the variable node; a decoding decision circuit, configured to perform a decoding decision for the bit information of the variable node; and a scaling circuit configured to scale the first reliability information transmitted, the second reliability information and the bit information of the variable node. 1. A method for LPDC decoding , comprising:initializing,processing several loop iterations, wherein the loop iteration is consist of processing of a check node, processing of a variable node and decoding decision;scaling a first reliability information transmitted from the variable node to the check node and a second reliability information transmitted from the check node to the variable node and bit information of the variable node, in one or more loop iterations.2. The method according to claim 1 , scaling the first reliability information claim 1 , the second reliability information and the bit information in a shifting manner.3. The method according to claim 1 , further comprising:determining whether the loop iteration satisfies a predetermined execution condition; andscaling the first reliability information, the second reliability information and the bit information if the predetermined execution condition is satisfied.4. The method according to claim 3 , wherein the determining whether the loop iteration satisfies a predetermined execution condition comprises:determining whether the bit information of the variable information is less than a predetermined threshold;determining that the ...

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Номер записи: 66
16-02-2017 дата публикации

PARALLEL BIT INTERLEAVER

Номер: US20170047946A1
Автор: Petrov Mihail
Принадлежит:

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. 1. A bit interleaving method for interleaving bits of a codeword generated based on a quasi-cyclic low-density parity check coding scheme , including a repeat-accumulate quasi-cyclic low-density parity check coding scheme , the bit interleaving method comprising:a bit permutation step of applying a bit permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits; anda dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits, whereinN is not a multiple of M,the bit permutation rule includes a first rule and a second rule, the first rule being applied to N′=N−X cyclic blocks, the second rule being applied to X cyclic blocks, the first rule and the second rule differing from each other, where X is a remainder of N divided by M, andthe reordering of the first rule is equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N′ cyclic blocks being written into a matrix row-by-row during the writing process, the written bits being read out from the matrix column-by-column during the reading process, the matrix having M rows, the Q bits ...

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Номер записи: 67
15-02-2018 дата публикации

LOW DENSITY PARITY CHECK CODE FOR TERRESTRIAL CLOUD BROADCAST

Номер: US20180048330A1
Автор: HUR Nam Ho, KIM Heung Mook, PARK Sung Ik
Принадлежит: Electronics and Telecommunications Research Institute

Provided is an LDPC (Low Density Parity Check) code for terrestrial cloud broadcast. A method of encoding input information based on an LDPC (Low Density Parity Check) includes receiving information and encoding the input information with an LDPC codeword using a parity check matrix, wherein the parity check matrix may have a structure obtained by combining a first parity check matrix for an LDPC code having a higher code rate than a reference value with a second parity check matrix for an LDPC code having a lower code rate than the reference value. 1. A method of decoding an LDPC (Low Density Parity Check) code by an LDPC decoder , the method comprising:receiving an LDPC codeword; anddecoding the LDPC codeword corresponding to a parity check matrix, wherein the parity check matrix includes a dual diagonal matrix and an identity matrix.2. The method of claim 1 , wherein the LDPC codeword includes a systematic part corresponding to input information claim 1 , a first parity part corresponding to the dual diagonal matrix claim 1 , and a second parity part corresponding to the identity matrix.3. The method of claim 2 , wherein the LDPC codeword is generated by performing:obtaining the first parity part using accumulation corresponding to the dual diagonal matrix based on the input information; andobtaining the second parity part using the identity matrix based on the calculated first parity part.4. The method of claim 3 , wherein the LDPC codeword is generated by further performingpuncturing the LDPC codeword corresponding to predetermined locations of at least one of the first parity part and the second parity part for a target code rate.5. The method of claim 4 , wherein the puncturing corresponds to the identity matrix in the parity check matrix.6. An LDPC (Low Density Parity Check) decoder comprising:a receiving unit configured to receive an LDPC codeword; anda decoding unit configured to decode the LDPC codeword corresponding to a parity check matrix, wherein the ...

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Номер записи: 68
08-05-2014 дата публикации

PARALLEL BIT INTERLEAVER

Номер: US20140126674A1
Автор: Petrov Mihail
Принадлежит: Panasonic Corporation

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section. 117-. (canceled)18. A bit interleaving method interleaving a codeword of quasi-cyclic low-density parity check codes , including repeat-accumulate quasi-cyclic low-density parity check codes , the bit interleaving method comprising:a permutation step of applying a permutation process to the codeword made up of a plurality of cyclic blocks each including an equal number of cyclic block bits in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks; andan allocation step of allocating the cyclic block bits, after the permutation process, to a plurality of constellation words, each of the constellation words being made up of a plurality of constellation word bits, whereineach of the cyclic blocks is allocated to one among a plurality of sections according to the cyclic block permutation rule,the cyclic block permutation rule defines allocation of the cyclic blocks to the sections and an ordering of the cyclic blocks within each of the sections, andeach of the constellation words is only allocated cyclic block bits from the cyclic blocks allocated to a common section, and each of the cyclic block bits is arranged within one of the constellation words at a position determined according to the ordering of the cyclic blocks within the section.19. A bit interleaver interleaving a codeword of quasi-cyclic low-density parity check codes , including repeat-accumulate quasi-cyclic low- ...

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Номер записи: 69
03-03-2022 дата публикации

FORWARD ERROR CORRECTION USING NON-BINARY LOW DENSITY PARITY CHECK CODES

Номер: US20220069844A1
Автор: Abrams Stuart, Hadani Ronny, Namboodiri Vamadevan
Принадлежит:

Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink. 1. An apparatus for forward error correction , comprising:a processor-implemented encoder configured to encode information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries;a modulator configured to modulate, using an orthogonal time frequency space (OTFS) modulation scheme, the encoded information bits to generate a signal; anda transmitter configured to transmit the signal over a channel,wherein a parity matrix H for the NB-LDPC code is based on a binary H matrix, and 'add offsets to entries in a first column and entries in a first row of the binary H matrix such that the first column and the first row contain only identity elements.', 'wherein the binary H matrix is based on a computer search algorithm configured to2. The apparatus of claim 1 , wherein the computer search algorithm is configured to terminate upon a determination that no N-cycles are present in a Tanner graph representation of the binary H matrix claim 1 , and wherein N=4 or N=6.3. The apparatus of claim 1 , wherein the parity check matrix H is represented a H=[H claim 1 , H] claim 1 , where ...

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Номер записи: 70
08-05-2014 дата публикации

PARALLEL BIT INTERLEAVER

Номер: US20140129895A1
Автор: Petrov Mihail
Принадлежит: Panasonic Corporation

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. 114-. (canceled)15. A bit interleaving method interleaving a codeword of quasi-cyclic low-density parity check codes , including repeat-accumulate quasi-cyclic low-density parity check codes , the bit interleaving method comprising:an allocation step of allocating codeword bits of the codeword made up of N cyclic blocks each including Q cyclic block bits to Q×N/M constellation words, each of the constellation words being made up of M bits, whereinF is an integer greater than 1, and is a divisor of M and Q,N is not a multiple of M/F,N′ is equal to (M/F)×floor(N/(M/F)),in the allocation step, allocation process is applied such that the M bits-include F cyclic block bits from each of M/F different cyclic blocks in each of F×N′/M folding sections, each of the folding sections being made up of M/F of the cyclic blocks, and such that the M bits are allocated to each of Q/F of the constellation words.16. A bit interleaver interleaving a codeword of quasi-cyclic low-density parity check codes , including repeat-accumulate quasi-cyclic low-density parity check codes , the bit interleaver comprising:an allocation unit allocating codeword bits of the codeword made up of N cyclic blocks each including Q cyclic block bits to Q×N/M constellation words, each of the constellation words being made up of M bits, whereinF is an integer greater than 1, ...

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Номер записи: 71
14-02-2019 дата публикации

METHOD OF CHANNEL CODING FOR COMMUNICATION SYSTEMS AND APPARATUS USING THE SAME

Номер: US20190052287A1
Автор: HUR Nam-Ho, KIM Heung-Mook, KWON Sun-Hyoung, PARK Sung-Ik
Принадлежит: Electronics and Telecommunications Research Institute

Disclosed herein are a channel coding/decoding method in which a parity check matrix is transformed and an apparatus using the same. The channel-coding method includes loading a first exponent matrix, transforming the first exponent matrix into a second exponent matrix, creating a parity check matrix corresponding to a required block size using the second exponent matrix, and performing LDPC encoding using the parity check matrix. 1. A channel-coding method , comprising:loading a first exponent matrix;transforming the first exponent matrix into a second exponent matrix;creating a parity check matrix corresponding to a required block size using the second exponent matrix; andperforming low-density parity-check (LDPC) encoding using the parity check matrix.2. The channel-coding method of claim 1 , wherein transforming the first exponent matrix into the second exponent matrix comprises:performing a circular column permutation on one column of the first exponent matrix and thereby creating a column-permutated exponent matrix; andcreating conversion values for elements that are greater than 0 in the column-permutated exponent matrix and creating the second exponent matrix using the conversion values.3. The channel-coding method of claim 2 , wherein the one column is a (k+1)-th column of the first exponent matrix (where kis a natural number that is acquired by subtracting a number of rows in the first exponent matrix from a number of columns therein).4. The channel-coding method of claim 3 , wherein the first exponent matrix and the second exponent matrix are classified as two types claim 3 , which are a first type and a second type claim 3 , depending on first four elements in the (k+1)-th column of the first exponent matrix.5. The channel-coding method of claim 4 , wherein claim 4 , when the first four elements include a single natural number claim 4 , which is greater than 0 claim 4 , the exponent matrix is classified as the first type claim 4 , and when the first four ...

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Номер записи: 72
14-02-2019 дата публикации

Low Density Parity Check Decoder

Номер: US20190052288A1
Автор: Choi Gwan S., GUNNAM Kiran Kumar
Принадлежит: The Texas A&M University System

A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order. 1. A low density parity check (LDPC) code decoder , comprising: 'a control unit that controls processing by the decoding circuitry, the control unit configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order,', 'decoding circuitry configured to process blocks of an LDPC matrix, the decoding circuitry comprising an R new update substep that provides an R new message, wherein the R new message is produced for a block of a different layer of the matrix from a layer containing a block currently being processed;', 'an R old update substep that provides an R old message, wherein the R old message is produced for a layer of the matrix currently being processed;', 'a P message substep that generates updated P messages;', 'a Q message substep that computes variable node messages (Q messages); and', 'a check node partial state processing substep that updates partial state of the layer based on Q messages computed for the block., 'wherein the control unit is configured to cause the decoding circuitry to process each block of the LDPC matrix in processing substeps comprising2. The LDPC code decoder of claim 1 , wherein the decoding circuitry is configured to generate a Q message by combining an R message with a P message.3. The LDPC code decoder of claim 1 , wherein the decoding circuitry further comprises a permuter configured to permute a P message.4. The LDPC code decoder of claim 3 , wherein the permuter is configured to permute the P message by a difference of ...

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Номер записи: 73
14-02-2019 дата публикации

Transmitting apparatus and mapping method thereof

Номер: US20190052507A1
Автор: Belkacem Mouhouche, Daniel Ansorregui Lobete, Hong-Sil Jeong, Kyung-Joong Kim, Se-Ho Myung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

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Номер записи: 74
25-02-2021 дата публикации

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM

Номер: US20210058095A1
Автор: JIN Jie, Mazurenko Ivan Leonidovich, PETIUSHKO Aleksandr Aleksandrovich, ZHANG Chaolong
Принадлежит: Huawei Technologies CO.,Ltd.

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths. 2. The method according to claim 1 , further comprising:determining, by the communication apparatus, the lifting factor Z; anddetermining, by the communication apparatus, the base matrix according to a set index of the lifting factor Z.3. The method according to claim 1 , wherein lifting factor Z is one of 5 claim 1 , 10 claim 1 , 20 claim 1 , 40 claim 1 , 80 claim 1 , 160 claim 1 , or 320.4. The method according to claim 1 , wherein the base matrix comprises m rows and n columns claim 1 , where m and n are positive integers claim 1 , and n=m+10.5. The method according to claim 4 , wherein 7≤m≤42 claim 4 , and 17≤n≤52.6. The method according to claim 1 , wherein the matrix H is determined according to a transformed matrix of the base matrix claim 1 , and wherein the transformed matrix is obtained by performing one or more of row transformation or column transformation on the base matrix.7. The method according to claim 1 , further comprising:receiving a signal, the signal comprising information that is based on low density parity check (LDPC) encoding; andperforming demodulating, deinterleaving, and rate de-matching on the signal to obtain the input sequence.9. The apparatus according to claim 8 , wherein the at least one processor is further configured to: ...

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Номер записи: 75
25-02-2021 дата публикации

RECEIVER AND METHOD FOR PROCESSING A SIGNAL THEREOF

Номер: US20210058191A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal. 1. A receiver for receiving a superposition-coded signal , the receiver comprising:a first decoder configured to decode data of the superposition-coded signal to generate information bits corresponding to a first layer signal of the superposition-coded signal based on at least a part of a parity check matrix of a low density parity check (LDPC) code;an encoder configured to encode the information bits and first parity bits to generate second parity bits based on at least the part of the parity check matrix;an interleaver configured to interleave bits of a codeword comprising the information bits, the first parity bits and the second parity bits;a mapper configured to map the interleaved bits of the codeword to constellation points; anda second decoder configured to decode the data of the superposition-coded signal to generate bits corresponding to a second layer signal of the superposition-coded signal,wherein the second layer signal is obtained by removing a signal which is based on the constellation points, from the superposition-coded signal, andwherein the parity check matrix comprises a dual diagonal matrix corresponding to the first parity ...

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Номер записи: 76
25-02-2021 дата публикации

HIGH PERFORMANCE, FLEXIBLE, AND COMPACT LOW-DENSITY PARITY-CHECK (LDPC) CODE

Номер: US20210058192A1
Автор: Kudekar Shrinivas, Richardson Thomas Joseph
Принадлежит:

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity. 1. A method for wireless communication , comprising:determining a low-density parity-check (LDPC) code base graph associated with a plurality of LDPC codes for a plurality of code rates and blocklengths, the LDPC base graph having a number of base graph columns corresponding to a maximum number of base information bits;determining a lifting size value for generating a lifted LDPC parity check matrix (PCM);generating the lifted LDPC PCM based on the base graph and the lifting size value; andgenerating an LDPC code based on the lifted LDPC PCM and an all zero vector, wherein the LDPC code was shortened by either (i) removing one or more of the base graph columns or (ii) removing one or more lifted LDPC PCM columns, and wherein the shortening was based on at least one of: a desired code rate, lifting size value, or blocklength for a transmission.2. The method of claim 1 , wherein the step of determining the lifting size value for generating the lifted LDPC PCM determines the number of base graph columns or the lifted LDPC PCM columns that may be removed to shorten the LDPC code.3. The method of claim 1 , further comprising transmitting the LDPC code over a wireless channel.4. The method of claim 1 , wherein the plurality of LDPC codes are associated with different numbers of base graph columns claim 1 , equal to or less than the number of ...

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Номер записи: 77
13-02-2020 дата публикации

METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CHANNEL CODING IN WIRELESS COMMUNICATION SYSTEM

Номер: US20200052720A1
Автор: JIN Jie, Mazurenko Ivan Leonidovich, PETIUSHKO Aleksandr Aleksandrovich, ZHANG Chaolong
Принадлежит: Huawei Technologies CO.,Ltd.

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths. 2. The method according to claim 1 , wherein N is equal to 50×Z.3. The method according to claim 1 , wherein the input sequence c is represented as c={c claim 1 , c claim 1 , c claim 1 , . . . claim 1 , c} claim 1 , and the encoded sequence d is represented as d={d claim 1 , d claim 1 , d claim 1 , . . . claim 1 , d} claim 1 , wherein in encoding the input sequence c using the matrix H claim 1 , an element c(k=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , K−1) in the input sequence c and an element do (n=0 claim 1 , 1 claim 1 , 2 claim 1 , . . . claim 1 , N−1) in the encoded sequence d satisfy:for k=2Z to K−1,{'sub': k', 'k−2z', 'k, 'if cis not a filling bit, d=c; and'}{'sub': k', 'k', 'k−2Z, 'if cis a filling bit, c=0, and dis a filling bit.'}5. The method according to claim 4 , wherein the parity sequence w has N+2Z−K bits and the parity sequence w is represented as w={w claim 4 , w claim 4 , w claim 4 , . . . claim 4 , w}.6. The method according to claim 5 , wherein in encoding the input sequence c using the matrix H claim 5 , an element in the parity sequence w and an element in the encoded sequence d satisfy:for k=K to N+2Z−1,{'sub': k−2z', 'k−K, 'd=w.'}7. The method according to claim 1 , wherein Z is a minimum value that satisfies K×Z≥K claim 1 ...

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Номер записи: 78
13-02-2020 дата публикации

METHODS AND APPARATUS FOR COMPACTLY DESCRIBING LIFTED LOW-DENSITY PARITY-CHECK (LDPC) CODES

Номер: US20200052817A1
Автор: Kudekar Shrinivas, Richardson Thomas Joseph
Принадлежит:

Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word. 1. A method for wireless communications , comprising:determining a first set of cyclic lifting values associated with a set of lifting size values and a base parity check matrix (PCM) associated with a base graph;selecting a lifting size value from the set of lifting size values;determining a second set of cyclic lifting values by computing a modulo of each of the first set of cyclic lifting values with respect to the selected lifting size value;determining a lifted PCM for generating a lifting low density parity code (LDPC) code by applying the second set of cyclic lifting values to interconnect edges in copies of the base graph; andat least one of: encoding a set of information bits to produce one or more codewords for transmission or decoding one or more codewords to obtain a set of information bits.2. The method of claim 1 , wherein:computing the modulo of the second set of cyclic lifting values with respect to the selected lifting size value comprises, for each cyclic lifting value in the second set of cyclic lifting values, performing a modulo operation;the selected lifting size value is a divisor in the modulo operation; anda corresponding cyclic ...

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Номер записи: 79
21-02-2019 дата публикации

H MATRIX GENERATING CIRCUIT, OPERATING METHOD THEREOF AND ERROR CORRECTION CIRCUIT USING H MATRIX GENERATED BY THE SAME

Номер: US20190056988A1
Автор: CHAE Chol Su, Kim Jang Seob
Принадлежит:

An H matrix generating circuit for generating an H matrix of a QC-LDPC code may include: a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; and a shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively. 1. An H matrix generating circuit for generating an H matrix of a QC-LDDC (Quasi Cyclic Low Density Parity Check) code , comprising:a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; anda shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively.2. The H matrix generating circuit of claim 1 ,wherein the conversion value calculation unit calculates shift values as the conversion values corresponding to the respective column sections, andwherein the shift values are used for converting first circulant matrices of the column sections into identity matrices through a circular shift, respectively.3. The H matrix generating circuit of claim 1 , wherein the shift unit generates the advanced H matrix such that the first circulant matrices of the respective column sections of the advanced H matrix are identity matrices.4. The H matrix generating circuit of claim 1 , wherein the advanced H matrix is compressed into H matrix information that contains positions of the first circulant matrices of the respective column sections of the advanced H matrix and positions and shift values of the other circulant matrices of the advanced H matrix.5. An operating method of an H matrix generation circuit for generating an H matrix of a QC-LDDC code claim 1 , the operating method comprising: ...

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Номер записи: 80
21-02-2019 дата публикации

Transmitting apparatus and signal processing method thereof

Номер: US20190058492A1
Автор: Hong-Sil Jeong, Kyung-Joong Kim, Se-Ho Myung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

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Номер записи: 81
21-02-2019 дата публикации

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

Номер: US20190058546A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform by group-wise interleaving a plurality of bit groups configuring the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern. 1. A broadcasting signal transmitting apparatus which is operable in a mode among a plurality of modes , the broadcasting signal transmitting apparatus comprising:an encoder configured to encode information bits comprising input bits to generate parity bits based on a low density parity check (LDPC) code having a code rate of the mode being 3/15 and a code length of the mode being 16200 bits, wherein the input bits are based on signalling information about a broadcasting data;a parity permutator configured to split a codeword into a plurality of bit groups, the codeword comprising the information bits and the parity bits, and interleave bit groups including the parity bits among the plurality of bit groups based on a permutation order of the mode, to provide an interleaved codeword;a puncturer configured to calculate a number of parity bits to be punctured based on a number of the information bits, and puncture bits of the interleaved codeword based on the calculated number;a mapper configured to map the input bits and parity bits of the interleaved codeword remaining after the puncturing onto constellation points, wherein the constellation points are generated based on a quadrature phase shift keying (QPSK) ...

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Номер записи: 82
20-02-2020 дата публикации

DATA PROCESSING APPARATUS AND METHOD

Номер: US20200059251A1
Автор: IKEGAYA Ryoji, Loghin Muhammad Nabil Sven, Michael Lachlan, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

A data processing apparatus includes a group-wise interleaving unit that performs group-wise interleaving; and a block interleaving unit that performs block interleaving in such a manner that an LDPC code obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in the row direction. A type of the block interleaving includes a type A and a type B. A MODCOD which is a combination of the LDPC code and the modulation scheme includes a MODCOD-A which is a MODCOD based on the assumption that the block interleaving of the type A is performed, and a MDOCOD-B which is a MDOCOD based on the assumption that the block interleaving of the type B is performed. 1. A transmitting apparatus comprising:circuitry configured toperform group-wise interleaving which interleaves an LDPC code word to obtain a group-wise interleaved LDPC code word;perform block interleaving which interleaves the group-wise interleaved LDPC code word to obtain a block interleaved and group-wise interleaved LDPC code word in such a manner that the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving is written in m number of columns as storage regions arranged in a row direction, m bits are obtained by respectively reading the LDPC code word from m number of columns bit by bit,perform mapping the block interleaved and group-wise interleaved LDPC code word to any one of 2m number of signal points defined by a modulation scheme; andperform transmitting a digital broadcast signal including the mapped block interleaved and group-wise interleaved LDPC code word obtained by performing the group-wise interleaving, performing the block interleaving, and performing the mapping,wherein a type of the block interleaving includes a type A in which writing of the group-wise interleaved LDPC code word obtained by performing the group-wise interleaving in a column direction of the columns is iteratively performed on m number of ...

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Номер записи: 83
01-03-2018 дата публикации

ENCODING METHOD, DECODING METHOD

Номер: US20180062667A1
Автор: MURAKAMI Yutaka
Принадлежит:

An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check (LDPC) convolutional code using a plurality of parity check polynomials. The second parity check matrix is generated by performing at least one of row permutation and column permutation with respect to the first parity check matrix. An eth parity check polynomial that satisfies zero, of the LDPC convolutional code, is expressible by using a predetermined mathematical formula. This application is based on application No. 2011-164262 filed in Japan on Jul. 27, 2011, on application No. 2011-250402 filed in Japan on Nov. 16, 2011, and on application No. 2012-009455 filed in Japan on Jan. 19, 2012, the content of which is hereby incorporated by reference.The present invention relates to an encoding method, a decoding method, an encoder, and a decoder using low-density parity check convolutional codes (LDPC-CC) supporting a plurality of coding rates.In recent years, attention has been attracted to a low-density parity-check (LDPC) code as an error correction code that provides high error correction capability with a feasible circuit scale. Because of its high error correction capability and ease of implementation, an LDPC code has been adopted in an error correction coding scheme for IEEE802.11n high-speed wireless LAN systems, digital broadcasting systems, and so forth.An LDPC code is an error correction code defined by low-density parity check matrix H. Furthermore, the LDPC code is a block code having the same block length as the number of columns N of check matrix H (see Non-Patent Literature 1, Non-Patent Literature 2, Non-Patent Literature 3). For example, random LDPC code, QC-LDPC code (QC: Quasi-Cyclic) are proposed.However, a characteristic of many ...

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Номер записи: 84
04-03-2021 дата публикации

Transmitter, receiver, communication system, method for changing code rate, control circuit and non-transitory storage medium

Номер: US20210067174A1
Автор: Hideo Yoshida, Kazuo Kubo
Принадлежит: Mitsubishi Electric Corp

A transmitter according to the disclosure includes: an encoding unit that generates a code word by performing coding with a low-density parity-check code using a check matrix, the encoding unit being capable of switching the check matrix for use in generating the code word, between a first check matrix with a first code rate and a second check matrix with a second code rate smaller than the first code rate, the first check matrix containing a plurality of cyclic permutation matrices, the encoding unit generating the second check matrix by masking the cyclic permutation matrix at a predetermined position in the first check matrix and adding a row with a column weight equal to or less than a threshold; and a transmission unit that transmits the code word.

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Номер записи: 85
04-03-2021 дата публикации

Low density parity check decoder

Номер: US20210067175A1
Автор: Gwan S. CHOI, Kiran Kumar Gunnam
Принадлежит: TEXAS A&M UNIVERSITY SYSTEM

A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

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Номер записи: 86
17-03-2022 дата публикации

Method and Apparatus for Vertical Layered Decoding of Quasi-Cyclic Low-Density Parity Check Codes Using Predictive Magnitude Maps

Номер: US20220085828A1
Автор: Declercq David, Reynwar Benedict J., Yella Vamsi Krishna
Принадлежит:

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss. 1. A method for vertical layered decoding of quasi-cyclic low-density parity-check (LDPC) codes , the method comprising:receiving, as inputs, channel values belonging to a channel output alphabet;using the channel values for initializing and iteratively processing messages between variable nodes and check nodes within block-columns in an arbitrary order, and sequentially from a group of one or more block-columns to another group of one or more block-columns;initializing, during the initializing, check node states associated with the check nodes by computing syndrome bits and magnitudes of the check node states;computing, during the initializing, respective signs of variable-to-check messages;storing the check node states in a check node memory, with each check node state associated to a check node comprising a syndrome bit computed from the signs of the variable-to-check messages of the associated check node and a set of values comprising one or more smallest magnitudes of the variable-to-check messages of the associated check node, along with a same number of respective block-column indices;{'claim-text': ['computing new check-to-variable messages with inputs comprising the check node states and the signs of the variable-to-check messages as ...

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Номер записи: 87
17-03-2022 дата публикации

QUALITY-BASED DYNAMIC SCHEDULING LDPC DECODER

Номер: US20220085829A1
Автор: ASADI Meysam, Bhatia Aman, Zhang Fan
Принадлежит:

Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters. 1. A method for decoding a low-density parity-check code (LDPC) codeword , the method implemented on a computing device and comprising:determining a variable node to check node (V2C) message, wherein the V2C message corresponds to a variable node that is connected to a check node;determining a reliability of a set of V2C messages comprising the V2C message;selecting, based on the reliability, a check node processing mode from a plurality of different check node processing modes;determining a check node to variable node (C2V) message based on the check node processing mode; anddecoding the LDPC codeword based on the C2V message.2. The method of claim 1 , further comprising: determining a syndrome of the LDPC codeword;', 'increasing a decoding iteration number;', 'determining that the increased decoding iteration number does not exceed a maximum number; and', 'determining that the syndrome of the LDPC codeword is not zero., 'during a decoding iteration3. The method of claim 2 , further comprising: (a) updating the V2C message corresponding to the variable node;', '(b) determining that the variable node is associated with a “j” variable node circulant matrix;', '(c) determining that the ...

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Номер записи: 88
17-03-2022 дата публикации

APPARATUS AND METHOD FOR ENCODING AND DECODING CHANNEL IN COMMUNICATION OR BROADCASTING SYSTEM

Номер: US20220085912A1
Автор: JANG Min, JEONG Hongsil, KIM Kyungjoong, MYUNG Seho
Принадлежит:

The present invention related to a 5G or pre-5G communication system to be provided to support a higher data transmission rate since 4G communication systems like LTE. The present invention relates to a method and an apparatus for encoding a channel in a communication or broadcasting system supporting parity-check matrices having various sizes are provided. The method for encoding a channel includes determining a block size of the parity-check matrix; reading a sequence for generating the parity-check matrix, and transforming the sequence by applying a previously defined operation to the sequence based on the determined block size. 1. A method performed by an apparatus for processing a low-density parity-check (LDPC) code , the method comprising:identifying a parity check matrix;encoding a code block based on the parity check matrix; andtransmitting at least a part of the encoded code block,wherein the parity check matrix includes an information part and a parity part,wherein the parity part including:a first part (B) including a plurality of first permutation matrices,a second part (D) including a second permutation matrix,a third part (T) including a plurality of identity matrices arranged diagonally within the third part and a plurality of third permutation matrices arranged below the plurality of identity matrices, anda fourth part (E) including a fourth permutation matrix,wherein the third part (T) is in a form of a square matrix, and{'sup': '−1', 'wherein a matrix according to (E)(T)(B)+D corresponds to a circulant permutation matrix which is not an identity matrix.'}2. The method of claim 1 , wherein one of the first permutation matrices is arranged in the first block of the first part (B) claim 1 , andwherein the fourth permutation matrix is arranged in the last block of the fourth part (E).3. The method of claim 2 , wherein the one of the first permutation matrix claim 2 , the second permutation matrix claim 2 , the plurality of third permutation matrices ...

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Номер записи: 89
08-03-2018 дата публикации

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

Номер: US20180069571A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, LOBETE Daniel Ansorregui, MOUHOUCHE Belkacem, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The method of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The method of claim 1 , wherein the π(j) is determined based on at least one of the code length claim 1 , a modulation method of the mapping and the code rate. This application is a Continuation of application Ser. No. 14/715,941 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes data and transmits the data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions and portable multimedia player and portable broadcasting equipments are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods of digital broadcasting services.In order to meet such demand, standard groups are establishing various standards and are providing a variety of services to satisfy users' needs. Therefore, there is a need for a method for providing improved services to users with high decoding and receiving performance.Exemplary embodiments may overcome ...

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Номер записи: 90
28-02-2019 дата публикации

LOOK-AHEAD LDPC DECODER

Номер: US20190068223A1
Автор: Tseng Ko-Chung, YEO Engling
Принадлежит:

Look-ahead LDPC decoder. In an exemplary embodiment, a method includes generating a message (QA) to a first check node, the QA message is generated from a result (RA) from the first check node, and generating a message (QB) to a second check node, the QB message is generated from the result (RA) and is transmitted to avoid decoder stall. The method also includes receiving a result (R′A) from the first check node, computing a difference (R″A) between the result (R′A) and the result (RA), and receiving a result (R′B) from the second check node. The method also includes computing a bit value P(B) using the difference (R″A) and the result (R′B). 1. A method , comprising:generating a message (QA) to a first check node, wherein the QA message is generated from a result (RA) from the first check node;generating a message (QB) to a second check node, wherein the QB message is generated from the result (RA) and is transmitted before decoder stall;receiving a result (R′A) from the first check node;computing a difference (R″A) between the result (R′A) and the result (RA);receiving a result (R′B) from the second check node; andcomputing a bit value P(B) using the difference (R″A) and the result (R′B).2. The method of claim 1 , further comprising storing the result (RA).3. The method of claim 1 , wherein generating the message (QA) comprises generating the message (QA) from (QA=P−RA) claim 1 , wherein P is a previous bit value and RB is a previous result from the second check node.4. The method of claim 1 , wherein generating (QB) comprises determining (QB) from (QB=P−RB) claim 1 , wherein P is a previous bit value and RB is a previous result value from the second check node.5. The method of claim 1 , further comprising computing the difference (R″A) from (R′A−RA).6. The method of claim 1 , wherein computing the bit value P(B) comprises determining P(B) from (P(B)=QB+R′B+R″A).7. The method of claim 1 , further comprising performing the method to mitigate a read before write (RBW ...

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Номер записи: 91
28-02-2019 дата публикации

SYSTEMS AND METHODS FOR ADVANCED ITERATIVE DECODING AND CHANNEL ESTIMATION OF CONCATENATED CODING SYSTEMS

Номер: US20190068320A1
Автор: Dogan Hakan, Lee Wookwon, Shayegh Farnaz, Vojcic Branimir R.
Принадлежит:

Systems and methods for decoding block and concatenated codes are provided. These include advanced iterative decoding techniques based on belief propagation algorithms, with particular advantages when applied to codes having higher density parity check matrices such as iterative soft-input soft-output and list decoding of convolutional codes, Reed-Solomon codes and BCH codes. Improvements are also provided for performing channel state information estimation including the use of optimum filter lengths based on channel selectivity and adaptive decision-directed channel estimation. These improvements enhance the performance of various communication systems and consumer electronics. Particular improvements are also provided for decoding HD radio signals, satellite radio signals, digital audio broadcasting (DAB) signals, digital audio broadcasting plus (DAB+) signals, digital video broadcasting-handheld (DVB-H) signals, digital video broadcasting-terrestrial (DVB-T) signals, world space system signals, terrestrial-digital multimedia broadcasting (T-DMB) signals, and China mobile multimedia broadcasting (CMMB) signals. These and other improvements enhance the decoding of different digital signals. 1. A method for generating check-to-variable messages during an iteration in decoding of codes represented by a parity check matrix , the method comprising the following steps for at least one variable node:a. calculating a check-to-variable message Mcv(i,j) from check node i to variable node j;{'sub': 1', '2, 'b. identifying two smallest absolute values, Minand Min, in a set of variable-to-check messages Mvc(i, k), where k≠j, excluding the message from variable j to check node i, Mvc(i,j);'}{'sub': 1', '2, 'c. calculating a scaling factor α=1−β·Min/Min, where β is a non-negative number such that 0≤β≤1; and'}d. scaling the check-to-variable message Mcv(i,j) as Mcv(i,j)=α·Mcv(i,j).2. The method of wherein the check-to-variable message Mcv(i claim 1 ,j) from check node i to ...

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Номер записи: 92
07-03-2019 дата публикации

PERMUTATION NETWORK DESIGNING METHOD, AND PERMUTATION CIRCUIT OF QC-LDPC DECODER

Номер: US20190074850A1
Автор: Hsiao Yu-Hua
Принадлежит: Shenzhen EpoStar Electronics Limited CO.

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit. 1. A permutation network designing method for a permutation circuit of a quasi-cyclic low-density parity check (QC-LDPC) decoder corresponding to a rewritable non-volatile memory module , comprising:identifying a size of a physical page of the rewritable non-volatile memory module as a page size, wherein the physical page is configured to store a plurality of codewords;obtaining a length of each of the codewords as a codeword length according to the amount of the codewords and the page size;identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices, and the default dimension value is a quotient obtained by dividing the codeword length with N;calculating a first value according to the default dimension value, and identifying a first permutation network according to the first value, the default dimension value, and a shift type of the check matrix, wherein the first permutation network comprises a plurality of first permutation layers arranged ...

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Номер записи: 93
19-03-2015 дата публикации

Transmitter and signal processing method thereof

Номер: US20150082117A1
Автор: Hong-Sil Jeong, Kyung-Joong Kim, Se-Ho Myung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmitter, a receiver and methods of controlling the transmitter and the receiver are provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to generate an LDPC codeword by performing LDPC encoding on an L1 post signaling; a demux configured to demultiplex a plurality of bits constituting the L1 post signaling of the LDPC codeword; and a modulator configured to modulate the demultiplexed bits.

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Номер записи: 94
19-03-2015 дата публикации

Scoring variable nodes for low density parity check code decoding

Номер: US20150082126A1
Автор: Mark Vernon
Принадлежит: Fusion IO LLC

Apparatuses, systems, methods, and computer program products are disclosed for error correcting code (ECC) decoding. A score module is configured to assign a score to a variable node of low density parity check (LDPC) code decoder. The LDPC code decoder may include a plurality of variable nodes associated with a plurality of check nodes. The plurality of variable nodes may correspond to bits of a received code word. The score for the variable node may be based on a count of unsatisfied check nodes associated with the variable node. A variable node update module is configured to update the variable node based on the score. A check node update module is configured to update one or more of the check nodes based on the updated variable node.

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Номер записи: 95
15-03-2018 дата публикации

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

Номер: US20180076928A1
Автор: Jeong Hong-Sil, LOBETE Daniel Ansorregui, MOUHOUCHE Belkacem
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 1. A mapping method of a transmitting apparatus , comprising:encoding, using at least one hardware processor, input bits to generate parity bits based on a low density parity check (LDPC) code;interleaving, using at least one hardware processor, a codeword comprising the input bits and the parity bits; andmapping, using at least one hardware processor, bits of the interleaved codeword onto constellation points for 256-quadrature amplitude modulation (QAM),wherein the constellation points comprise constellation points as represented in a list below:0.0899+0.1337i0.0910+0.1377i0.0873+0.3862i0.0883+0.3873i0.1115+0.1442i0.1135+0.1472i0.2067+0.3591i0.1975+0.3621i0.1048+0.7533i0.1770+0.7412i0.1022+0.5904i0.1191+0.5890i0.4264+0.6230i0.3650+0.6689i0.3254+0.5153i0.2959+0.5302i0.3256+0.0768i0.3266+0.0870i0.4721+0.0994i0.4721+0.1206i0.2927+0.1267i0.2947+0.1296i0.3823+0.2592i0.3944+0.2521i0.7755+0.1118i0.7513+0.2154i0.6591+0.1033i0.6446+0.1737i0.5906+0.4930i0.6538+0.4155i0.4981+0.3921i0.5373+0.3586i0.1630+1.6621i0.4720+1.5898i0.1268+1.3488i0.3752+1.2961i1.0398+1.2991i0.7733+1.4772i0.8380+1.0552i0.6242+1.2081i0.1103+0.9397i0.2415+0.9155i0.1118+1.1163i0.3079+1.0866i0.5647+0.7638i0.4385+0.8433i0.6846+0.8841i0.5165+1.0034i1.6489+0.1630i1.5848+0.4983i1.3437+0.1389i1.2850+0.4025i1.2728+1.0661i1.4509+0.7925i1.0249+0.8794i1.1758+0.6545i0.9629+0.1113i0.9226+0.2849i1.1062+0.1118i1.0674+0.3393i0.7234+0.6223i0.8211+0.4860i0.8457+0.7260i0.9640+0.5518i2. The method as claimed in claim 1 , wherein the encoding encodes the input bits according to a code rate of ...

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Номер записи: 96
24-03-2022 дата публикации

EFFICIENT ENCODING FOR NON-BINARY ERROR CORRECTION CODES

Номер: US20220094372A1
Автор: Tocalli Claudio
Принадлежит:

A method for encoding information bits with a Q-ary linear error correction code defined over a binary-extension Galois field GF(2), and defined by a quasi-cyclic parity-check matrix comprising: 2. The method of claim 1 , wherein the information section of the parity-check matrix comprises a fifth and a sixth circulant sub-matrices claim 1 , said determining a first set of parity-check bits being further performed according to said fifth and a sixth circulant sub-matrices.3. The method of claim 2 , wherein said determining the first set of parity-check bits comprises determining the first set of parity-check bits according to an amount given by:the sum between the fifth circulant sub-matrix, the sixth circulant sub-matrix, and the third circulant sub-matrix multiplied by the inverse of the second circulant sub-matrix.4. The method of claim 3 , further comprising:periodically and/or aperiodically updating the fifth and sixth circulant sub-matrices and said amount according to the updated fifth and sixth circulant sub-matrices, anddetermining the first set of parity-check bits according to said updated amount.5. The method of claim 1 , wherein the information section of the parity-check matrix comprises a fifth circulant sub-matrix claim 1 , said determining a second set of parity-check bits being further performed according to said fifth circulant sub-matrix.6. The method of claim 1 , wherein the Q-ary linear error correction code is a Q-ary “Low-Density Parity-Check” (LDPC) code.8. The controller of claim 7 , wherein the information section of the parity-check matrix comprises a fifth and a sixth circulant sub-matrices claim 7 , the controller being configured to determine said first set of parity-check bits further according to said fifth and a sixth circulant sub-matrices.9. The controller of claim 8 , wherein the controller is configured to determine the first set of parity-check bits according to an amount given by:the sum between the fifth circulant sub-matrix, ...

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Номер записи: 97
18-03-2021 дата публикации

HARDWARE IMPLEMENTATIONS OF A QUASI-CYCLIC SYNDROME DECODER

Номер: US20210083686A1
Автор: ASADI Meysam, Chen Jianging, LU Xuanxuan, Zhang Fan
Принадлежит:

Disclosed are devices, systems and methods for providing hardware implementations of a quasi-cyclic syndrome decoder. An example method of reducing the complexity of a decoder includes receiving a noisy codeword that is a based on a transmitted codeword generated from a quasi-cyclic linear code; computing a plurality of syndromes based on the noisy codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address as a function of the first syndrome; reading, based on the memory cell address, a coset leader corresponding to the first syndrome; and determining, based on the noisy codeword and the coset leader, a candidate version of the transmitted codeword. 1. A method for reducing complexity of a decoder , comprising:receiving a noisy codeword that is a based on a transmitted codeword generated from a quasi-cyclic linear code;computing a plurality of syndromes based on the noisy codeword;selecting a first syndrome from the plurality of syndromes;generating a memory cell address as a function of the first syndrome;reading, based on the memory cell address, a coset leader corresponding to the first syndrome; anddetermining, based on the noisy codeword and the coset leader, a candidate version of the transmitted codeword.2. The method of claim 1 , wherein the plurality of syndromes are computed in parallel.3. The method of claim 1 , wherein the first syndrome is selected based on decimal representations of the plurality of syndromes claim 1 , and wherein the first syndrome has a minimum decimal representation associated with a shift.4. The method of claim 3 , further comprising:determining, based on the coset leader, an error pattern; andapplying the shift to error pattern to generate a shifted error pattern that is used to determine the candidate version of the transmitted codeword.5. The method of claim 1 , wherein generating the memory cell address is based on a hash function claim 1 , and wherein collisions of the hash function ...

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Номер записи: 98
18-03-2021 дата публикации

PARALLEL BIT INTERLEAVER

Номер: US20210083692A1
Автор: Petrov Mihail
Принадлежит:

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process. 1. A transmission method comprising:generating a codeword according to a low density parity check coding scheme such that the codeword includes N bit groups each consisting of Q bits, a parity check matrix of the low density parity check coding scheme having a quasi-cyclic structure;reordering bits in the codeword;dividing the codeword into constellation words each consisting of M bits after the bits in the codeword are reordered; andgenerating a transmission signal based on the constellation words,wherein a first part of the N bit groups is constituted by K bit groups and bits of the K bit groups are written into an M by Q matrix row-by-row and the written bits of the K bit groups are read from the M by Q matrix column-by-column in order to reorder the bits in the codeword, andwherein a second part of the N bit groups is constituted by L bit groups, and bits of the L bit groups are mapped onto the constellation words in a state where bits in the L bit groups are not reordered.2. A transmission device comprising:generating circuitry configured to generate a codeword according to a low density parity check coding scheme such that the codeword includes N bit groups each consisting of Q bits, a parity check matrix of the low density parity check coding scheme having a quasi-cyclic structure;reordering circuitry connected to the ...

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Номер записи: 99
26-03-2015 дата публикации

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

Номер: US20150089321A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns including a plurality of rows, respectively, and comprises: a block interleaver configured to divide each of the plurality of columns into a first part and a second part, and interleave a plurality of bit groups constituting the LDPC codeword, all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part, at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns constituting the second part. 1. A transmitting apparatus comprising:an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding;an interleaver configured to interleave the LDPC codeword; anda modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol,wherein the interleaver is formed of a plurality of columns including a plurality of rows, respectively, and comprises:a block interleaver configured to divide each of the plurality of columns into a first part and a second part, and interleave a plurality of bit groups constituting the LDPC codeword,wherein all bit groups interleaved by the first part are interleaved as bits included in a same bit group are written in a same column of the first part,wherein at least one bit group interleaved by the second part is interleaved as bits included in the at least one bit group are divided and written in at least two columns ...

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Номер записи: 100
12-03-2020 дата публикации

Apparatus and method for channel encoding/decoding in communication or broadcasting system

Номер: US20200083904A1
Автор: Hongsil JEONG, Kyungjoong KIM, Min Jang, Seho Myung, Seokki AHN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus and a method for channel encoding and decoding in a communication or broadcasting system is provided. According to the present disclosure, the method for channel encoding in a communication or broadcasting system includes determining a block size Z, and performing encoding based on the block size and a parity check matrix corresponding to the block size, in which the block size is included in any one of the plurality of block size groups and the parity check matrix is different for each block size group.

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Номер записи: 101