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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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20-04-2016 дата публикации

Генератор последовательностей импульсов

Номер: RU0000161479U1
Автор: Александр Алексеевич Алабин, Борис Викторович Добромыслов, Юрий Анатольевич Сорокин, Юрий Васильевич Слепов
Принадлежит: Акционерное общество "Научно-исследовательский институт Приборостроения имени В.В. Тихомирова"

Генератор последовательностей импульсов, содержащий первый счетчик, выход которого подключен ко входу первого постоянного запоминающего устройства, выход которого подключен ко входу данных D регистра, К выходов которого являются выходом устройства, при этом выход генератора частоты соединен со входом логической схемы НЕ, выход которой подключен ко входу С регистра, отличающийся тем, что введены второй счетчик, второе постоянное запоминающее устройство, компаратор кодов, логическая схема И, дешифратор и элемент задержки, при этом выход генератора частоты подключен к первому входу логической схемы И и счетному входу С второго счетчика, выход второго счетчика подключен к первому входу компаратора кодов, выход которого подключен ко второму входу логической схемы И, выход логической схемы И подключен к счетному входу С первого счетчика, выход первого счетчика подключен ко входу дешифратора и ко входу второго постоянного запоминающего устройства, выход которого подключен ко второму входу компаратора кодов, при этом выход дешифратора подключен ко входу элемента задержки, выход элемента задержки соединен с R входами первого и второго счетчиков. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (51) МПК H03K 3/84 (13) 161 479 U1 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ТИТУЛЬНЫЙ (21)(22) Заявка: ЛИСТ ОПИСАНИЯ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ 2015157219/08, 29.12.2015 (24) Дата начала отсчета срока действия патента: 29.12.2015 (45) Опубликовано: 20.04.2016 Бюл. № 11 1 6 1 4 7 9 R U (57) Формула полезной модели Генератор последовательностей импульсов, содержащий первый счетчик, выход которого подключен ко входу первого постоянного запоминающего устройства, выход которого подключен ко входу данных D регистра, К выходов которого являются выходом устройства, при этом выход генератора частоты соединен со входом логической схемы НЕ, выход которой подключен ко входу С регистра, отличающийся тем, что введены второй счетчик, второе постоянное запоминающее устройство, компаратор ...

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Номер записи: 1
13-09-2012 дата публикации

Sampling based data de-duplication

Номер: US20120233135A1
Автор: Jeffrey Vincent TOFANO
Принадлежит: Quantum Corp

Example apparatus, methods, and computers perform sampling based data de-duplication. One example method controls a data de-duplication computer to compute a sampling sequence for a sub-block of data and to use the sampling sequence to locate a stored sub-block known to the data de-duplication computer. Upon finding a stored sub-block to compare to, the method includes controlling the data de-duplication computer to determine a degree of similarity (e.g., duplicate, very similar, somewhat similar, very dissimilar, completely dissimilar, x % similar) between the sub-block and the stored sub-block and to control whether and how the sub-block is stored and/or transmitted based on the degree of similarity. The degree of similarity can also control whether and how the data de-duplication computer updates a dedupe data structure(s) that stores information for finding groups of similarity sampling sequence related sub-blocks.

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Номер записи: 2
20-09-2012 дата публикации

Method for controlling a basic parity node of a non-binary ldpc code decoder, and corresponding basic parity node processor

Номер: US20120240002A1
Автор: Emmanuel Boutillon, Laura Conde-Canencia
Принадлежит: UNIVERSITE DE BRETAGNE SUD

A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U 1 ,U 2 ) having n m elements sorted in ascending or descending order, n m being greater than 1, and gives an output list (U out ) of n m , elements sorted in said ascending or descending order, n m , being greater than 1, each element of the output list (U out ) being the result of a computing operation φ between an element of the first input list (U 1 ) and an element of the second input list (U 2 ). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.

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Номер записи: 3
18-04-2013 дата публикации

LDPC Decoder With Targeted Symbol Flipping

Номер: US20130097475A1
Автор: Chung-Li Wang, Shaohua Yang, Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for decoding data in a non-binary LDPC decoder with targeted symbol flipping. For example, a non-binary low density parity check data decoder is disclosed that comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.

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Номер записи: 4
02-05-2013 дата публикации

Encoding method, decoding method, encoding device, decoding device, program, and recording medium

Номер: US20130106626A1
Автор: Kimitaka Tsutsumi, Masahiro Fukui, Shigeaki Sasaki, Shoichi Koyama, Yusuke Hiwasaki
Принадлежит: Nippon Telegraph and Telephone Corp

A plurality of samples are vector-quantized to obtain a vector quantization index and quantized values; bits are assigned in a predetermined order of priority based on auditory perceptual characteristics to one or more sets of sample positions among a plurality of sets of sample positions, each set having a plurality of sample positions and being given an order of priority based on the auditory perceptual characteristics, the number of bits not being larger than the number of bits obtained by subtracting the number of bits used for a code corresponding to the vector quantization index from the number of bits assigned for the code corresponding to the vector quantization index; and index information indicating a group of coefficients that minimizes the sum of the error between the value of each sample included in each of the sets of sample positions to which the bits are assigned and the value obtained by multiplying the quantized value of each sample included in the set of sample positions by a coefficient corresponding to the position of the sample, of all the sample positions included in the set of sample positions, is output.

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Номер записи: 5
30-05-2013 дата публикации

Variable Sector Size LDPC Decoder

Номер: US20130139022A1
Автор: Lei Chen, Shaohua Yang, YANG Han, Zongwang Li
Принадлежит: LSI Corp

Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding variably sized blocks of data in an LDPC decoder. For example, in one embodiment an apparatus includes a low density parity check decoder operable to perform decoding of a plurality of circulant sub-matrices from an H matrix, and a controller connected to the low density parity check decoder, operable to omit any of the plurality of circulant sub-matrices from the decoding if they do not contain user data.

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Номер записи: 6
13-06-2013 дата публикации

TIME DETECTION CIRCUIT, AD CONVERTER, AND SOLID STATE IMAGE PICKUP DEVICE

Номер: US20130146751A1
Автор: Hagihara Yoshio
Принадлежит: OLYMPUS CORPORATION

A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing. 1. A time detection circuit comprising:a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse;a latch unit configured to latch logic states of the plurality of delay units;a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units;a count latch unit configured to latch a state of the count unit; anda latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.2. The time detection circuit according to claim 1 , wherein the delay unit is an annular delay circuit in which the plurality of delay units are connected in an annular shape.3. The time detection circuit according to claim 1 , further comprising:a comparison unit configured to receive an analog signal and a reference signal that increases or decreases with the passage of time and output a comparison signal when the reference signal has satisfied a predetermined ...

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Номер записи: 7
13-06-2013 дата публикации

METHODS OF CONTROLLING CLOCKS IN SYSTEM ON CHIP INCLUDING FUNCTION BLOCKS, SYSTEMS ON CHIPS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

Номер: US20130147526A1
Автор: HEO Jung Hun, KIM Dong Keun, KIM Si Young, KWON Sun Cheol, Lee Jae Gon
Принадлежит:

A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero. 1. A method of operating a system-on-chip including at least one function block , the method comprising:decreasing an operating frequency of the at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state, the decreased operating frequency being greater than zero.2. The method of claim 1 , wherein the decreasing of the operating frequency comprises:dividing a frequency of a reference clock for the system-on-chip according to a division factor associated with the idle state of the at least one function block; and wherein the operating frequency of the at least one function block is decreased to the divided frequency.3. The method of claim 1 , further comprising:setting the operating frequency of the at least one function block to an active mode operating frequency, the active mode operating frequency being a first clock frequency associated with the active state of the at least one function block; and whereinthe operating frequency of the at least one function block is decreased from the active mode operating frequency to an idle mode operating frequency, the idle mode operating frequency being a second clock frequency associated with the idle state of the at least one function block.4. The method of claim 1 , further comprising:increasing the operating frequency of the at least one function block in response to a change in the operating ...

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Номер записи: 8
20-06-2013 дата публикации

DECODING DEVICE AND CODING METHOD

Номер: US20130154857A1
Автор: KUSHIDA Sohei, TAKEMOTO Takashi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A decoding device has a buffer configured in memory to store N code streams and N decoders connected in series. Each of N decoders decodes a corresponding code steam and sequentially generates partial symbols of M bit width each unit cycle. Among the N decoders, i (i>=2) stage decoders stores multiple probabilistic models in the memory. In each unit cycle, the decoder receives an input of i−1 partial symbols which contains partial symbols generated by the i−1 stage decoder in the former unit cycle, selects one probabilistic model among the multiple probabilistic models based on i−1 partial symbols which are entered previously, generates one partial symbol using previously selected probabilistic models, and outputs the previously generated one partial symbol along with previously entered i−1 partial symbols. 1. A decoding device comprising:a buffer configured in memory to store N (N is a positive integer) code streams; andN decoders connected in series, each of the N decoders having a one-to-one correspondence with one of the N code streams, and being configured to decode the corresponding code stream and sequentially generate partial symbols of M bit width (M is a positive integer) per each unit cycle,wherein among the N decoders, i (2<=i<=N, i is a positive integer) stage decoders store multiple probabilistic models in the memory; andwherein, in each unit cycle, an i stage decoder receives an input of i−1 partial symbols which are partial symbols generated by an i−1 stage decoder in the former unit cycle, selects one probabilistic model among the multiple probabilistic models based on i−1 partial symbols which are entered previously, generates one partial symbol using previously selected probabilistic models, and outputs the previously generated one partial symbol along with the previously entered i−1 partial symbols.2. The decoding device according to claim 1 , wherein the i stage decoder connects the one partial symbol to the end of the i−1 partial symbols which ...

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Номер записи: 9
27-06-2013 дата публикации

SEMICONDUCTOR DEVICE THAT CAN ADJUST PROPAGATION TIME OF INTERNAL CLOCK SIGNAL

Номер: US20130162308A1
Автор: MATSUBARA Yasushi, MATSUI Yoshinori, Morishita Satoshi, SAKASHITA Mototada
Принадлежит: ELPIDA MEMORY, INC.

Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal. 1. A semiconductor device comprising:a measurement circuit measuring propagation time of an internal clock signal inside the semiconductor device;a delay adjustment circuit adjusting the propagation time of the internal clock signal; anda data output circuit outputting a data signal in response to the internal clock signal.2. The semiconductor device as claimed in claim 1 , wherein the measurement circuit includes a replica circuit of a propagation path of the internal clock signal claim 1 , the measurement circuit measuring the propagation time of the internal clock signal by measuring a time from when a test signal that is different from the internal clock signal is supplied to the replica circuit until when the test signal is output from the replica circuit.3. The semiconductor device as claimed in claim 2 , wherein the time from when the test signal is supplied to the replica circuit until when the test signal is output from the replica circuit is longer than the propagation time of the internal clock signal.4. The semiconductor device as claimed in claim 2 , wherein the measurement circuit further includes a latch circuit that latches the test signal output from the replica circuit at a time when the test signal supplied to the replica circuit is changed from a second logic level to a first logic level after the test signal is changed from the first logic level to the second logic level.5. The semiconductor device as claimed in claim 4 , wherein the measurement circuit further includes:a counter circuit outputting a different count value each time the test signal ...

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Номер записи: 10
04-07-2013 дата публикации

RAM Based Implementation for Scalable, Reliable High Speed Event Counters

Номер: US20130170605A1
Автор: Bender Carl Alfred, Hochschild Peter Heiner, MISRA Ashutosh, Swetz Richard
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter. 1. A system comprising:a main memory;said main memory comprising RAM;a plurality of preliminary counters each fed by a corresponding event source; anda sweeper which accesses preliminary counters and feeds values from preliminary counters to said RAM, wherein said sweeper accesses said preliminary counters in a predetermined order;said RAM acting to accumulate counting data relating to the event sources.2. The system according to claim 1 , wherein the sweeper acts to access each of 2M preliminary counters in sequential order in a clock cycle of length 2M.3. The system according to claim 2 , wherein said sweeper comprises a free running M-bit counter which facilitates sequential access of said sweeper to said preliminary counters.4. The system according to claim 3 , wherein each preliminary counter has a width of M+1 bits.5. The system according to claim 1 , wherein said sweeper comprises a state machine.6. The system according to claim 1 , wherein said sweeper further acts to clear each preliminary counter.7. The system according to claim 1 , wherein said sweeper acts to add an output value from a preliminary counter to a corresponding RAM location claim 1 , whereby a previous count value is incremented at said corresponding RAM location.8. The system according to claim 1 , ...

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Номер записи: 11
04-07-2013 дата публикации

Non-binary qc-ldpc code decoding device and associated method

Номер: US20130173981A1
Автор: Chen-Yap Leong, Chung-Jay Yang, Kuo-Hsuan Liao, Yeong-Luh Ueng
Принадлежит: National Tsing Hua University NTHU

A non-binary quasi-cyclic (QC) low-density parity-check (LDPC) code decoding device comprises a first barrel-shifter, a routing network and a second barrel-shifter. The first barrel-shifter uses a constraint h′v′+h″v″=hv to shift q−1 elements of an input by j 0 positions to produce first temporary elements. The routing network connects to the first barrel-shifter, permutes the first temporary elements to produce second temporary elements if v′ of the constraint is not zero and designates the first temporary elements as the second temporary elements if v′ of the constraint is zero. The second barrel-shifter connects to the routing network and uses the constraint h′v′+h″v″=hv to shift q−1 elements of the second temporary elements by i 0 positions. A non-binary QC-LDPC decoding method is also disclosed.

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Номер записи: 12
11-07-2013 дата публикации

ENCODING DEVICE AND ENCODING METHOD

Номер: US20130176150A1
Автор: Oshikiri Masahiro, Yamanashi Tomofumi
Принадлежит: Panasonic Corporation

An encoding device enables the amount of processing operations to be significantly reduced while minimizing deterioration in the quality of an output signal. This encoding device () encodes an input signal by determining the correlation between a first signal generated by using the input signal and a second signal generated by a predetermined method. An importance assessment unit () sets the importance of each of a plurality of processing units obtained by dividing the frames of the input signal. A CELP coder () performs sparse processing in which the amplitude value of a predetermined number of samples among multiple samples constituted by the first signal and/or the second signal in each processing unit is set to zero according to the importance that was set for each processing unit, and calculates the correlation between the first signal and the second signal, either of which was subjected to sparse processing. 1. A coding apparatus that codes an input signal to generate coded information , the coding apparatus comprising:a first signal generation section that generates a first signal using the input signal;a second signal generation section that generates a second signal through a predetermined method;a setting section that sets a significance for each of a plurality of processing units obtained by dividing a frame of the input signal; anda correlation computation section that sets, in accordance with the significance set for each of the processing units, amplitude values of a predetermined number of samples to zero, the predetermined number of samples being taken from a plurality of samples forming at least one of the first signal and the second signal of each processing unit, and that computes a correlation between the one signal, for which the amplitude values of the predetermined number of samples have been set to zero, and the other signal.2. The coding apparatus according to claim 1 , wherein the correlation computation section reduces the number of ...

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Номер записи: 13
18-07-2013 дата публикации

PARALLEL DIFFERENTIAL ENCODING CIRCUITS

Номер: US20130181853A1
Автор: Konishi Yoshiaki
Принадлежит: Mitsubishi Electric Corporation

A first differential encoding circuit is configured to perform a differential encoding on n-lines parallel input data to generate n-lines parallel output data. A second differential encoding circuit is configured to perform a differential encoding on n-lines parallel input data to generate n-lines parallel output data. A multiplexing circuit is configured to alternately multiplex the generated parallel output data from the first differential encoding circuit and the second differential encoding circuit, and configured to output the multiplexed data. 1. A parallel differential encoding circuit that performs a differential encoding on parallel input data to generate parallel output data , comprising:a first differential encoding circuit configured to perform a differential encoding on n-lines parallel input data (2≦n; n denotes an integer) to generate n-lines parallel output data (2≦n; n denotes an integer);a second differential encoding circuit configured to perform a differential encoding on n-lines parallel input data (2≦n; n denotes an integer) to generate n-lines parallel output data (2≦n; n denotes an integer); anda multiplexing circuit configured to alternately multiplex the generated parallel output data from the first differential encoding circuit and the second differential encoding circuit, and configured to output the multiplexed data.2. The parallel differential encoding circuit according to claim 1 , further comprising:a first selector circuit configured to select n-th line in the parallel output data either from the first differential encoding circuit or from the second differential encoding circuit; anda second selector circuit configured to select either n-th line in the parallel output data from the first differential encoding circuit or delayed n-th line in the parallel output data from the second differential encoding circuit,wherein the first differential encoding circuit delays an output of the first selector circuit, and performs a differential ...

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Номер записи: 14
01-08-2013 дата публикации

METHOD OF PROCESSING DATA SAMPLES AND CIRCUITS THEREFOR

Номер: US20130194112A1
Автор: Harwood Michael, Hearne Peter, Simpson Richard
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

The present invention relates to data manipulation and in particular incrementing, decrementing and comparing binary coded numbers, notably the manipulation of thermometer codes and the performance of arithmetic operations thereon. A method of processing data is provides which comprises receiving a series of data samples, each sample being represented as an N-bit thermometer code, wherein the most significant bit thereof represents the sign of the data sample value Y(n) and the remaining N−1 bits represent the magnitude of the data sample and executing a predetermined sequence of arithmetic operations directly on the series of N-bit thermometer code data samples to determine one of two values for each data sample, without any recoding of the thermometer code data samples. 1. A method of processing data comprisingreceiving a series of data samples (Y(1) Y(2) . . . Y(n), Y(n+1)), each sample being represented as an N-bit thermometer code, wherein the most significant bit thereof represents the sign of the data sample value Y(n) and the remaining N−1 bits represent the magnitude of the data sample; andexecuting a predetermined sequence of arithmetic operations directly on the series of N-bit thermometer code data samples to determine one of two values for each data sample, without any recoding of the thermometer code data samples.2. The method of claim 1 , wherein the step of executing a predetermined sequence of arithmetic operations comprises:for each data sample Y(n),comparing the magnitude of the next consecutive data sample Y(n+1) in the series of data samples to a first threshold (th1);if the magnitude of Y(n+1) is less than the first threshold (th1), setting an adjusted value (Y_adjust (n)) of data sample Y(n) to the value of data sample Y(n);if the magnitude of data sample Y (n+1) is not less than the threshold (th1), determining the sign of the data sample Y(n+1) from the MSB of Y(n+1);incrementing or decrementing the value of Y(n) in dependence on the sign of ...

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Номер записи: 15
08-08-2013 дата публикации

LOW-POWER PULSE WIDTH ENCODING SCHEME AND COUNTER-LESS SHIFT REGISTER THAT MAY BE EMPLOYED THEREWITH

Номер: US20130200152A1
Автор: Mickle Marlin H., Ogirala Ajay, Sai Vyasa
Принадлежит: UNIVERSITY OF PITTSBURGH-OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION

A method of decoding an encoded signal includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time Δ, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling. Also, a method of operating a shift register wherein the shift register has an initialization state wherein a first binary symbol is stored in a first position and a second binary symbol different than the first binary symbol is stored in each of one or more intermediate positions and a last position. The method includes determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position. 1. A method of decoding an encoded signal , comprising: receiving the encoded signal;creating a decoding signal by delaying the encoded signal by apredetermined amount of time Δ;sampling the encoded signal using the decoding signal; anddetermining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling.2. The method according to claim 1 , wherein the plurality of decoded bits represented by the encoded signal each comprise one of a first symbol and a second symbol claim 1 , wherein the encoded signal represents each first symbol using a first square wave and each second symbol using a second square wave.3. The method according to claim 2 , wherein the first square wave has a first period Pand a first duty cycle D claim 2 , wherein the second square wave has a second period Pand a second duty cycle D claim 2 , and wherein D<ΔDand P≧P.5. The method according to claim 4 , wherein Dis at least 10% greater than D.6. The method according to claim 5 , wherein Dis at least 20% greater than D.7. The method according to claim 6 , wherein ...

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Номер записи: 16
08-08-2013 дата публикации

DECODING DEVICE AND DECODING METHOD

Номер: US20130201040A1
Автор: TAKAYAMA TSUYOSHI
Принадлежит: Panasonic Corporation

A decoding device includes an interface unit, a readout unit that reads out a file and recording medium management information from an external recording medium, a decoding unit that analyzes a read out file, a storage unit that stores file analysis information and recording medium management information, a determination unit that determines whether or not the recording medium management information pieces are the same when the external recording medium is connected to the interface unit, and a matching confirmation unit that, when the recording medium management information pieces are determined as being the same, determines whether or not the file contents match. When the determination results in a mismatch, the decoding unit generates new file analysis information and performs file decoding using the generated file analysis information, and when the determination results in a match, the decoding unit performs file decoding using the file analysis information in the storage unit. 1. A decoding device comprising:an interface unit connectable to an external recording medium on which an encoded file and recording medium management information that indicates an attribute of the external recording medium are recorded;a readout unit configured to read out the file and the recording medium management information from the external recording medium when the external recording medium is connected to the interface unit;a decoding unit configured to generate file analysis information that indicates a content of the file read out by the readout unit, through analysis of the content of the file;a storage unit configured to store the file analysis information and the recording medium management information of the external recording medium connected to the interface unit before;a determination unit configured to determine whether or not new recording medium management information is the same as the recording medium management information stored in the storage unit, the new ...

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Номер записи: 17
24-10-2013 дата публикации

DATA DECODING METHOD AND APPARATUS

Номер: US20130278450A1
Автор: ZHANG Jiaji, Zhang Yafan
Принадлежит:

Embodiments of the present invention disclose a data decoding method and apparatus, relate to the field of wireless communications, and can improve a resource utilization rate in a decoding process, thereby improving decoding efficiency. The method of the present invention includes: dividing a to-be-decoded data transport block into N code blocks, where N is an integer greater than or equal to 2; and decoding the N code blocks in parallel according to a reverse direction of encoding. The present invention is applicable to data decoding. 1. A decoding method , for decoding channel encoded data , comprising:dividing a to-be-decoded data transport block into N code blocks, wherein N is an integer greater than or equal to 2; anddecoding the N code blocks in parallel according to a reverse direction of encoding.2. The decoding method according to claim 1 , wherein the step of decoding the N code blocks in parallel according to the reverse direction of encoding comprises:dividing a decoding process into at least two decoding units according to a reverse sequence of encoding, wherein decoding processing on at least one code block can be completed in each decoding unit; anddecoding the N code blocks in the at least two decoding units, whereinat a first decoding time, decoding a first code block in a first decoding unit;at a second decoding time, decoding a second code block in the first decoding unit, and decoding, the first code block in a second decoding unit; andat a third decoding time, decoding the second code block in the second decoding unit;till decoding of the N code blocks is completed in every decoding unit.3. The decoding method according to claim 2 , wherein in the step of dividing the decoding process into at least two decoding units according to the reverse sequence of encoding claim 2 , any decoding unit comprises one or more decoding steps claim 2 , and any decoding step is decoding in a reverse direction of an encoding step.4. The decoding method according ...

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Номер записи: 18
31-10-2013 дата публикации

TIMING MONITOR FOR PLL

Номер: US20130285721A1
Автор: KOERNER Heiko
Принадлежит:

Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions of the PLL device, a quantity or pattern of the pulses indicating an error of the PLL device. 1. An apparatus , comprising:an identification block arranged to receive at least two signals and to output an identity signal indicating that one of the at least two signals is logically true and another of the at least two signals is logically false;a counter block arranged to count a quantity of successive identity signals referencing the one of the at least two signals; anda comparison block arranged to output an alert signal based on a comparison of a count of the counter block to a preselected threshold value.2. The apparatus of claim 1 , wherein the counter block is arranged to output an up count or a down count based on a relative temporal position of the at least two signals.3. The apparatus of claim 2 , wherein the counter block is arranged to output an up count when the one of the at least two signals is logically true and the one of the at least two signals temporally leads the other of the at least two signals.4. The apparatus of claim 2 , wherein when the counter block outputs an up count claim 2 , the counter block resets the down count.5. The apparatus of claim 1 , wherein the at least two signals are outputs from a phase detector of a phase-locked loop (PLL) device.6. The apparatus of claim 1 , wherein the at least two signals are binary pulse signals.7. A system claim 1 , comprising:a phase-locked-loop (PLL) device, including:a phase detector arranged to compare a phase of a reference frequency with a phase of a modified frequency and output a control signal on at least one of two outputs based on the comparison, the modified frequency comprising an output frequency of the PLL divided by a divider value; anda charge pump arranged to adjust the output frequency of ...

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Номер записи: 19
31-10-2013 дата публикации

SYSTEMS, DEVICES, AND METHODS FOR CONTINUOUS TIME SIGNAL PROCESSING

Номер: US20130287136A1
Автор: MARTINEZ NUEVO Pablo, TSIVIDIS Yannis
Принадлежит: The Trustees of Columbia University in the City of New York

The present disclosure shows new mechanisms fir sampling an input signal. In particular, some embodiments of the present disclosure include a new type of a level-crossing sampling mechanism called a derivative level-crossing sampling (D-LCS). At a high level, D-LCS involves quantizing the derivative of an input signal when the derivative of the input signal crosses one of the quantization thresholds. For certain class of signals, the derivative of the input signal can vary at a slower speed compared to the amplitude of the input signal. Therefore, by sampling the derivative of the input signal, instead of the input signal itself, the number of samples per unit time can be reduced. 1. A circuit system comprising:a differentiator configured to receive an input signal and to provide a derivative of the input signal; anda quantizer coupled to the differentiator, configured to receive the derivative of the input signal and to sample the derivative of the input signal when the derivative of the input signal crosses one of a plurality of quantization thresholds to provide a quantized derivative of the input signal.2. The circuit system of claim 1 , wherein the quantizer is configured to represent the quantized derivative of the input signal using a per-level representation.3. The circuit system of claim 2 , wherein the quantizer comprises a flash analog-to-digital converter.4. The circuit system of claim 1 , wherein the quantizer is associated with a finite offset voltage claim 1 , and wherein the circuit system further comprises a feedback system configured to compensate for the finite offset voltage associated with the quantizer.5. The circuit system of claim 1 , further comprising:a continuous time digital signal processing block coupled to the quantizer, configured to receive the quantized derivative of the input signal and to process the quantized derivative of the input signal to provide a derivative of an output signal; andan integrator coupled to the continuous ...

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Номер записи: 20
07-11-2013 дата публикации

SEMICONDUCTOR APPARATUS

Номер: US20130293271A1
Автор: SONG Choung Ki
Принадлежит: SK HYNIX INC.

A semiconductor apparatus includes a clock frequency change block configured to output a plurality of internal clocks with different frequencies by dividing a frequency of an external clock in response to a mode register set signal and a setting command to enable the plurality of internal clocks to be outputted, and generate a flag signal to designate the completion of the output, and a command generation block configured to receive a command and generate the setting command in response to the flag signal and the mode register to set signal. 1. A semiconductor apparatus comprising:a clock frequency change block configured to output a plurality of internal clocks with different frequencies by dividing a frequency of an external clock in response to a mode register set signal and a setting command to enable the plurality of internal clocks to be outputted, and generate a flag signal to designate the completion of outputting the plurality of internal clocks; anda command generation block configured to receive a command and generate the setting command in response to the flag signal and the mode register set signal.2. The semiconductor apparatus according to claim 1 , wherein the clock frequency change block generates a first internal clock with the same frequency as the external clock and a second internal clock with a different frequency from the external clock when the setting command and the mode register set signal are activated.3. The semiconductor apparatus according to claim 2 , wherein the frequency of the second internal clock corresponds to ½ of the frequency of the first internal clock.4. The semiconductor apparatus according to claim 1 ,wherein the command generation block activates the setting command when the flag signal is in a deactivated state and the mode register set signal is in an activated state, andwherein the command generation block deactivates the setting command even though the mode register set signal is in the activated state, when the flag ...

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Номер записи: 21
07-11-2013 дата публикации

High Speed RF Divider

Номер: US20130293272A1
Автор: Frambach Johannes Petrus Antonius, Hesen Leonardus, Mateman Paul
Принадлежит:

High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring. 1. A Radio Frequency (RF) quadrature clock divider comprising:positive and negative differential RF clock inputs;four clocked inverter stages connected in a serial ring formation, each clocked inverter stage comprising a pair of stacked PMOS transistors connected to a pair of stacked NMOS transistors; andan inverter interposed between each clocked inverter stage;wherein one of the PMOS transistors of each clocked inverter stage is connected to a positive voltage supply node and one of the NMOS transistors is connected to a ground node;wherein the gates of one PMOS transistor and one NMOS transistor of each clocked inverter stage are connected together to form an inverter; andwherein the gate of one PMOS transistor and one NMOS transistor of each clocked inverter stage are each connected to a different input clock, such that the positive and negative inputs to the PMOS and NMOS transistors alternate at each successive clocked inverter circuit in the ring.2. The RF-divider of wherein the outputs of the clocked inverter circuits comprise first and second differential clock outputs claim 4 , each having half the frequency of the clock input claim 4 , and wherein the second clock output is phase ...

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Номер записи: 22
07-11-2013 дата публикации

PHASE-LOCKED LOOP AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME, AND TEST SYSTEM INCLUDING THE INTEGRATED CIRCUIT CHIP

Номер: US20130294186A1
Автор: CHO Joo-Hwan, Choi Hae-Rang, KIM Kwan-Dong, NA Kwang-Jin
Принадлежит: SK HYNIX INC.

A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock. 1. A phase-locked loop , comprising:a phase detection unit configured to compare a phase of a feedback clock with a phase of an input clock;a clock generation unit configured to adjust a frequency of a first clock based on a result of the comparison of the phase detection unit;a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode; anda second division unit configured to generate the feedback clock by dividing the output clock.2. The phase-locked loop of claim 1 , wherein the clock generation unit comprises:a charge pump configured to generate a charging discharging current based on a result of the comparison of the phase detection unit;loop filter charged/discharged in response to the charging/discharging current to generate a control voltage; anda voltage-controlled oscillator (VCO) configured to generate the first clock having a frequency controlled in response to the control voltage.3. The phase-locked loop of claim 1 , wherein the first division unit comprises a divider having the first or second division ratio in response to a test mode signal indicative of the test mode.4. The phase-locked loop of claim 1 , ...

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Номер записи: 23
28-11-2013 дата публикации

DATA PROCESSING APPARATUS THAT ENABLES IMPORT/EXPORT OF SETTING VALUE, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR

Номер: US20130314259A1
Автор: Okayama Noritsugu
Принадлежит: CANON KABUSHIKI KAISHA

A data processing apparatus that is capable of reducing the garbling of characters caused by the difference among the character codes when setting data are transferred to another apparatus by the import-export function. A storage unit stores setting data for the data processing apparatus. A receiving unit receives an instruction for exporting the setting data stored in the storage unit. A converting unit converts Unicode data included in the setting data into character code data of language, which is set to the data processing apparatus. An export unit exports the character code data converted by the converting unit and the Unicode data. 1. A data processing apparatus comprising:a storage unit configured to store setting data for the data processing apparatus;a receiving unit configured to receive an instruction for exporting the setting data stored in said storage unit;a converting unit configured to convert Unicode data included in the setting data into character code data of language, which is set to the data processing apparatus; andan export unit configured to export the character code data converted by said converting unit and the Unicode data.2. The data processing apparatus according to claim 1 , wherein said export unit exports the setting data and code information that shows the character code of the setting data concerned.3. The data processing apparatus according to claim 2 , wherein code information about the setting data and a conversion flag that shows whether the character code data should be converted by said converting unit are registered in said storage unit for every setting data registered claim 2 , andwherein said conversion unit converts the Unicode data when the code information shows Unicode and the conversion flag shows to convert.43. The data processing apparatus according to claim claim 2 , wherein said converting unit determines whether the setting data is converted into the character code data claim 2 , based on a user's instruction.5. ...

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Номер записи: 24
12-12-2013 дата публикации

DECODING METHOD AND DECODER FOR UNARY/Kth ORDER EXPONENTIAL GOLOMB CODES

Номер: US20130328705A1
Автор: Lin Yu-Chao, Wang Yao-Hsin
Принадлежит:

A decoding method for unary/korder exponential Golomb (UEGk) codes is provided. The first step is a receiving step: receiving N bits from an input stream and updating a bit count. If the N bits are all one, the receiving step is re-performed. If the N bits includes zero, a searching step is performed to find a first value based on the bit count. Subsequently, according to the bit count and a threshold value, a remaining bit number M is calculated. A second value is generated based on M remaining bits received from the input stream. Then, the first value and the second value are added, so as to generate an index. 1. A decoding method for a unary/korder exponential Golomb (UEGk) code , comprising:a) receiving an N number of bits from an input bitstream, and updating a bit count according to N, wherein N is a positive integer;b) repeating step (a) when all of the N number of bits are “1”;c) generating a first value through a look-up table search at least according to the bit count when not all of the N number of bits are “1”;d) determining a remaining bit count M according to the bit count and a threshold;e) generating a second value according to an M number of remaining bits received from the input bitstream; andf) adding the first value and the second value to generate an index.2. The decoding method according to claim 1 , wherein the positive N is equal to 1.3. The decoding method according to claim 1 , wherein the positive integer is greater than 1;wherein generating the first value through the look-up table search is done according to the N number of bits and the bit count when not all of the N number of bits are “1”;wherein determining the remaining bit count M is done according to the N number of bits, the bit count and the threshold.4. The decoding method according to claim 3 , wherein the look-up table search further comprises:selecting a target look-up table from the N number of look-up tables according to the N number of bits, wherein the N number of look-up ...

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Номер записи: 25
19-12-2013 дата публикации

DOWN CONVERTER AND CONTROL METHOD OF THE SAME

Номер: US20130335124A1
Автор: NAKAMURA Yoshiaki, Suzuki Shigeya, URAKAWA Tatsuya, WANG Jianqin
Принадлежит: RENESAS ELECTRONICS CORPORATION

A down converter has two down converter circuits. The one down converter circuit has a first mixer, a first ½ frequency-divider, and a first PLL. The other down converter circuit has a second mixer, a second ½ frequency-divider, and a second PLL. A difference frequency between a frequency of a local oscillation frequency signal of the second PLL and a frequency of a frequency-divided signal of the first ½ frequency-divider is higher than an upper limit of a receive frequency band of a tuner. 1. A down converter , comprising:an amplification unit including:a first amplifier to which a first polarized wave signal is supplied; anda second amplifier to which a second polarized wave signal is supplied;a first down converter circuit including:a first reference signal generation unit for generating a first reference signal;a first local oscillation unit for generating a first local oscillation frequency signal using the first reference signal;a first frequency-divider for generating a first frequency-divided signal obtained by frequency dividing the first local oscillation frequency signal; anda first frequency conversion unit for converting a signal amplified by the amplification unit into a first intermediate frequency signal using the first frequency-divided signal; anda second down converter circuit including:a second reference signal generation unit for generating a second reference signal;a second local oscillation unit for generating a second local oscillation frequency signal using the second reference signal;a second frequency-divider for generating a second frequency-divided signal obtained by frequency dividing the second local oscillation frequency signal; anda second frequency conversion unit for converting a signal amplified by the amplification unit into a second intermediate frequency signal using the second frequency-divided signal,wherein a difference frequency between a frequency of the second local oscillation frequency signal and a frequency of the ...

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Номер записи: 26
19-12-2013 дата публикации

Updating variable nodes associated with an iterative decoder

Номер: US20130339817A1
Автор: Zion S. Kwok
Принадлежит: Individual

Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for data decoding and/or error correction. In various embodiments, an iterative decoder may compute, from sign bits of log likelihood ratios associated with x bits of a plurality of bits of encoded data, a first combination of the x bits having a higher associated log density ratio than any other combination of the x bits. In various embodiments, the iterative decoder may further be configured to compute m combinations of the x bits having m highest associated log density ratios, based on reductions in log density ratios associated with one or more sub-combinations of the x bits and the computed first combination of the x bits. In various embodiments, a variable node associated with the iterative decoder may be updated with the m combinations of the x bits. Other embodiments may be described and/or claimed.

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Номер записи: 27
26-12-2013 дата публикации

Processing elementary check nodes of an iterative ed transmitter appar

Номер: US20130346833A1
Автор: Zion S. Kwok
Принадлежит: Intel Corp

Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative decoder in a manner that conserves computing resources. In various embodiments, first and second sets of m tuples may be received, e.g., as input for the elementary check node. Each tuple may include a symbol and a probability that the symbol is correct, and the first and second sets of m tuples may be sorted by their respective probabilities. In various embodiments, less than all combinations of the first and second sets of m tuples may be computed for consideration as output of the elementary check node, and some computed combinations may be eliminated from consideration as output. In various embodiments, the elementary check node may output a set of m output tuples with the highest probabilities. Other embodiments may be described and/or claimed.

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Номер записи: 28
02-01-2014 дата публикации

HYBRID-CODING FOR IMPROVING TRANSIENT SWITCH RESPONSE IN A MULTI-CELL PROGRAMMABLE APPARATUS

Номер: US20140002282A1
Автор: Bawell Shawn, Huang Feng-Jung, Mourant Jean-Marc
Принадлежит:

Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution. 1. A device comprising:a step device having a plurality of cells, each cell being selectable to provide one or more of a plurality of selectable steps in a first range at a first resolution,where at least one of the plurality of cells, a first cell, is a variable cell selectable to provide a plurality of the plurality of selectable steps, and greater than a ratio of the range to a largest selectable step value in a binary coded step device at the first resolution and the first range, and', 'less than a ratio of the range to a largest selectable step value in a thermometer coded step device at the first resolution and the first range., 'where a ratio of the first range to a largest selectable step value of the plurality of selectable steps at the first resolution is2. The device of claim 1 , wherein the step device is hybrid-coded or hybrid-codable.3. The device of claim 1 , the plurality of cells comprising a hybrid of fixed and variable step value cells claim 1 , the step device further comprising:a second cell of the plurality of cells, the second cell comprising a fixed cell selectable to provide only one of the plurality of selectable steps4. The device of claim 1 , wherein the first cell claim 1 , the variable cell claim 1 , comprises one bypass shared by the plurality of selectable steps in the first cell.5. The device of claim 4 , wherein each variable cell comprises a plurality of selectable unit cells or stages sharing a common bypass.6. The device of ...

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Номер записи: 29
09-01-2014 дата публикации

APPARATUS AND METHOD FOR CODING DATA BASED ON PHASOR DISPARITY

Номер: US20140009315A1
Автор: Falconer Maynard C., KESLING DAWSON W., SKINNER HARRY G., Slattery Kevin P.
Принадлежит:

A method for managing information includes receiving bits of data, determining phasors for bits at only one frequency of a transmission spectrum, combining the phasors of bits that form a phasor having a spectral energy that lies within a predetermined range, and forming a codeword from the bits of the combined phasors. 1. An apparatus , comprising:first logic to receive bits of data; andsecond logic to generate a codeword from a predetermined number of the bits by:determining phasors for bits at only one frequency of a transmission spectrum,combining the phasors of bits that form a phasor having a spectral energy that lies within a predetermined range, andforming the codeword from the bits of the combined phasors.2. The apparatus of claim 1 , wherein the second logic is to combine the phasors by:identifying a phasor of a first bit that has a first angle and first magnitude,selecting a phasor for a second bit that has a second angle and second magnitude, andforming the codeword to include the first and second bits, wherein the first angle is spaced substantially 180° from the second angle.3. The apparatus of claim 2 , wherein the first magnitude is at least substantially equal to the second magnitude.4. The apparatus of claim 1 , wherein the phasors of bits corresponding to the codeword are to be combined to form a phasor with a spectral energy of substantially zero.5. The apparatus of claim 4 , wherein the foamed phasor is to have a magnitude of substantially zero.6. The apparatus of claim 1 , wherein the predetermined range is between zero and a predetermined magnitude of the phasor formed from the combined phasors.7. The apparatus of claim 1 , wherein the processor is to:generate a data word for transmission based on the codeword.8. The apparatus of claim 7 , wherein the data word includes only one codeword.9. The apparatus of claim 7 , wherein the data word includes at least two codewords and wherein one of the codewords is the codeword generated from the bits ...

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Номер записи: 30
27-02-2014 дата публикации

Methods and Apparatus in Alternate Finite Field Based Coders and Decoders

Номер: US20140055290A1
Автор: Lablans Peter
Принадлежит:

Methods and apparatus for coding and decoding n-state symbols with n≧2 and n>2 and n>3 and n>4 are provided wherein at least one implementation of an addition over an alternate finite field GF(n) and an inverter defined by a multiplication over the alternate finite field GF(n) are provided. Encoders and decoders implementing a single n-state truth table that is a truth table of an addition over an alternate finite field GF(n) modified in accordance with at least one inverter defined by a multiplication over the alternate finite field GF(n) are also provided. Encoders include scramblers, Linear Feedback Shift Register (LFSR) based encoders, sequence generator based encoders, block coders, streaming cipher encoders, transposition encoders, hopping rule encoders, Feistel network based encoders, check symbol based encoders, Hamming coder, error correcting encoders, encipherment encoders, Elliptic Curve Coding encoders and all corresponding decoders. Systems applying encoders and decoders also are provided. 1. An apparatus for encoding a first plurality of n-state symbols with n equal to or greater than 3 , each symbol being represented by a signal , comprising:an input enabled to receive the first plurality of n-state symbols; a zero element which is a neutral element of the addition is not 0; and wherein', 'the apparatus is part of the group consisting of a communication system and a data storage system; and, 'a device implementing an n-state switching function that is an addition over an alternate finite field GF(n) modified with a multiplication over an alternate finite field GF(n), wherein the alternate finite field GF(n) is a finite field defined by the addition and the multiplication, wherein'}an output enabled to provide a second plurality of symbols based on the first plurality of symbols.2. The apparatus of claim 1 , wherein n>4.3. The apparatus of claim 1 , further comprising:an implementation of at least one n-state inverter defined by the multiplication over ...

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Номер записи: 31
03-04-2014 дата публикации

Non-volatile memory counter

Номер: US20140093026A1
Автор: Jean-Louis Modave, Michel Dawirs
Принадлежит: Proton World International NV

A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

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Номер записи: 32
04-01-2018 дата публикации

LEVEL SHIFTER, DIGITAL-TO-ANALOG CONVERTER, AND BUFFER AMPLIFIER, AND SOURCE DRIVER AND ELECTRONIC DEVICE INCLUDING THE SAME

Номер: US20180006660A1
Автор: KIM Hwi-Cheol
Принадлежит: INNOAXIS CO., LTD

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch. 126-. (canceled)27. A source driver that drives a display panel , comprising:a level shifter configured to receive digital bits and provide a level-shifted output signal;a digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; andan amplifier configured to amplify a signal provided by the digital-to-analog converter,wherein the lower limit voltage is provided to a body electrode of the NMOS switch.28. The source driver of claim 27 , wherein the level shifter is driven by a first voltage and a second voltage that is smaller than the first voltage claim 27 , and the level-shifted output signal swings between the first voltage and the second voltage.29. The source driver of claim 28 , wherein the first voltage is the ...

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Номер записи: 33
02-01-2020 дата публикации

PHASE ROTATOR NON-LINEARITY REDUCTION

Номер: US20200007137A1
Автор: DICLEMENTE Dominic, VAN IERSSEL Marcus
Принадлежит:

A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal. 1. An integrated circuit , comprising:a phase interpolator configured to receive two or more signals having different phases;current source bias circuitry connected to determine respective contributions the two or more signals have to a phase of an output signal, the current source bias circuitry comprising a plurality of switchable current limiting circuits controllable by a thermometer code; and,the plurality of switchable current limiting circuits to each be biased to limit respective currents through respective current limiting circuits to reduce a non-linearity in a relationship between the thermometer code and the phase of the output signal.2. The integrated circuit of claim 1 , wherein respective limited currents through respective current limiting circuits is determined by a dimensioning of a circuit element of the current limiting circuit.3. The integrated circuit of claim 1 , wherein a resistive ladder is used to provide a respective plurality of bias voltages to the respective current limiting circuits.4. The integrated circuit of claim 2 , wherein at least one selectable current is connected to the resistive ladder to adjust the plurality of bias voltages.5. The integrated circuit of claim 3 , wherein the resistive ladder is designed to provide ...

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Номер записи: 34
12-01-2017 дата публикации

METHOD FOR DECODING NON-BINARY CODES AND CORRESPONDING DECODING APPARATUS

Номер: US20170012642A1
Автор: Declercq David, Garcia Herrero Francisco Miguel, Li Erbao, Valls Coquillat Javier
Принадлежит:

An extension to the enhanced serial generalized bit-flipping decoding algorithm (ES-GBFDA) of non-binary LDPC codes by introducing soft information in the check node operation. The application not only considers the most reliable symbol in the syndrome computation, but also takes at least the second most reliable symbol of each incoming message into account. An extended information set is available for the parity-check node update and this allows introducing the concept of weak and strong votes performed by the check node unit. Each variable node can receive two kinds of votes, whose amplitudes can be tuned to the reliability of the syndrome that produces the vote. 1. A method for decoding a non-binary low density parity-check (NB-LDPC) code defined in a finite field of size q , which is a symbol flipping decoding method using multiple votes performed by the check node unit and transferred to the variable node unit ,{'sub': n', 'm', 't, 'claim-text': [{'sub': n', 'm', 'n', 'n', 'c, 'sup': 1(j)', 'th', 'p(j), 'each variable node V, connected to a check node C, is configured for determining (A1.1, A1.2) a most reliable symbol Qand at least one symbol which is at least a pmost reliable symbol Q, with p≧2 for obtaining a vector of dmost reliable symbols;'}, {'sub': 'm', 'claim-text': [{'sub': n', 'n', 'c, 'sup': 0(j)', '(j), '(A3.1) a first symbol to be voted R=Rbased on the vector of dmost reliable symbols passed by the variable nodes connected to him in the bipartite graph;'}, {'sub': n', 'c', 'c', 'n', 'c', 'c', 'n, 'sup': i(j)', 'th', 'p(j)', '1(j), '(A3.2) a list of i=1, . . . , L second symbols to be voted Rbased on a list of L+1 test vectors defined as a combination of dsymbols with a restriction according to which at most η of these dsymbols are a pmost reliable symbol Qwith p≧2, and at least d−η of these dsymbols are a most reliable symbol Q.'}], 'each check node Cis configured for determining], 'the code can be displayed in a bipartite graph comprising at ...

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Номер записи: 35
12-01-2017 дата публикации

TECHNOLOGIES FOR ENHANCING COMPUTER SECURITY

Номер: US20170012963A1
Автор: Penny Brian, Penny Desmond
Принадлежит:

A method includes providing a plurality of variables and a variable. The variables differ from each other. The variables differ from the variable. The further method includes providing a lookup table indexing a plurality of characters via a plurality of values based on a first numeral system, converting a message into a first sequence of values based on the table, converting the first sequence into a second sequence of values based on a second numeral system different from the first system and according to a preset format, combining the second sequence into a single sequence via removing the format, generating a first plurality of subsequences from the single sequence based on segmentation of the sequence via alternating the variables, converting the first subsequences into a second plurality of subsequences such that each of the second subsequences is sized according to the variable, and transmitting the second subsequences. 1. A method comprising: providing a plurality of variables and a variable, said variables differ from each other, said variables differ from said variable,', 'providing a lookup table indexing a plurality of characters via a plurality of values based on a first numeral system,', 'converting a message into a first sequence of values based on said table,', 'converting said first sequence into a second sequence of values based on a second numeral system different from said first system and according to a preset format,', 'combining said second sequence into a single sequence via removing said format,, 'via a computergenerating a first plurality of subsequences from said single sequence based on segmentation of said sequence via alternating said variables, 'transmitting said second subsequences.', 'converting said first subsequences into a second plurality of subsequences such that each of said second subsequences is sized according to said variable,'}2. The method of claim 1 , wherein said first subsequences are converted into said second ...

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Номер записи: 36
14-01-2016 дата публикации

Low power divide-by-seven divider

Номер: US20160013794A1
Автор: Chulkyu Lee, Le Zhang, Wenjun Su
Принадлежит: Qualcomm Inc

A divide-by-seven divider includes a first module clocked with a clock input, and a second module coupled to the first module and clocked with an output of the first module. The first and second modules are configured to divide the clock input by seven and to output the divided clock input. The first module may be configured to store a count between 0 and 3 in a count cycle. The divide-by-seven divider may further include a feedback module coupled between the first module and the second module that is configured to cause the first module to skip one count in the count between 0 and 3 once every other count cycle. Specifically, the first module may be configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.

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Номер записи: 37
15-01-2015 дата публикации

SYSTEMS AND METHODS FOR DERIVATIVE LEVEL-CROSSING SAMPLING

Номер: US20150015429A1
Автор: MARTINEZ NUEVO Pablo, PATIL Sharvil Pradeep, TSIVIDIS Yannis
Принадлежит:

Systems and methods for level-crossing sampling and reconstruction technique are disclosed. The derivative of the input signal is level-crossing-sampled, and the resulting samples are transmitted. At the receiver, these samples are fed to a zero-order hold followed by an integrator, which results in piecewise-linear reconstruction. The disclosed systems and methods are further refined to reduce the number of samples generated per unit of time, compared to methods based on zero-order-hold reconstruction, for a given signal-to-error ratio, without significant hardware overhead. 1. A system for reconstructing an input signal comprising:a first differentiator configured to receive the input signal and generate a first signal representing the first derivative of the input signal;a second differentiator configured to receive the first signal and generate a second signal representing the second derivative of the input signal;a controller configured to receive the second signal and generate a quantization step;a level-crossing sampling block configured to receive the first signal and the quantization step and generate level-crossed samples of the first signal;a zero-order holding block configured to receive the level-crossed samples and the quantization step and generate a quantized signal; andan integrator configured to receive the quantized signal and the quantization step and generate a third signal representing a reconstructed signal of the input signal.2. The system of claim 1 , wherein the first differentiator is further configured to scale the received input signal.3. The system of claim 1 , wherein the second differentiator is further configured to scale the received first input signal.4. The system of claim 1 , wherein the integrator is further configured to scale the received quantized signal.5. The system of claim 1 , wherein the quantizer is configured to generate a small quantization step claim 1 , when a magnitude of the second signal is small.6. The system of ...

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Номер записи: 38
11-01-2018 дата публикации

LEVEL SHIFTER, DIGITAL-TO-ANALOG CONVERTER, AND BUFFER AMPLIFIER, AND SOURCE DRIVER AND ELECTRONIC DEVICE INCLUDING THE SAME

Номер: US20180013444A1
Автор: KIM Hwi-Cheol
Принадлежит: INNOAXIS CO., LTD

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch. 1. A level shifter that converts a level of an input voltage and outputs a level-converted input voltage , comprising:a first level shifter module configured to receive an input signal and output a signal that swings between a middle voltage and a reference voltage; anda second level shifter module configured to output a signal that swings between an upper limit voltage and a lower limit voltage in response to the input signal,wherein the second level shifter module includes an N-type metal oxide semiconductor (NMOS) transistor, and the lower limit voltage is provided to a body electrode of the NMOS transistor.2. The level shifter of claim 1 , wherein the NMOS transistor is arranged in a P well included in a triple well structure claim 1 , and the lower limit voltage is provided to the P well.3120. The level shifter of claim 2 , wherein the second level shifter module further comprises a P-type MOS (PMOS) transistor having a drain electrode connected to a drain electrode of the NMOS transistor claim 2 , and the PMOS transistor is arranged in an N well included in the triple well structure.4. The level ...

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Номер записи: 39
10-01-2019 дата публикации

ENTROPY ENCODING AND DECODING SCHEME

Номер: US20190013822A1
Автор: MARPE Detlev, NGUYEN Tung, SCHWARZ Heiko, WIEGAND Thomas
Принадлежит:

Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols swith i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols syields z, and, if n>1, for all i=1 . . . n−1, the value of scorresponds to a range of the ipartition. 1. An apparatus for decoding comprising:a symbol decoder configured to obtain, based on codewords from a data stream, a first sequence of source symbols and a second sequence of source symbols, wherein source symbols of the first and second sequences are related to level values of transform coefficients of a transform coefficient block,wherein the level values of transform coefficients are encoded into the data stream according to a scan order leading through the transform coefficients of the transform coefficient block, and the symbol decoder is configured to obtain a first source symbol of the first sequence using a Rice code and a second source symbol of the first sequence using an Exp-Golomb code; anda composer configured to: obtaining a set of source symbols from the first and second sequences based on a portion of the plurality of disjoint portions associated with the syntax element, and', 'combining values of the source symbols of the set to determine the value of the syntax element; and, 'compose a sequence of syntax elements having a value ...

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Номер записи: 40
10-01-2019 дата публикации

COMPRESSION AND DECOMPRESSION ENGINES AND COMPRESSED DOMAIN PROCESSORS

Номер: US20190013823A1
Автор: Bruck Dan, Tamir Dan E.
Принадлежит:

Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided. 1. A compressed domain processor comprising:an unpack unit to unpack blocks of compressed data into at least a first compressed integer and a second compressed integer;an arithmetic logic unit to receive the first compressed integer and the second compressed integer and to generate a third compressed integer; anda pack unit to pack block of compressed data, at least one block including the third compressed integer.2. The compressed domain processor as recited in claim 1 , wherein the arithmetic logic unit is includes:a pre-arrangement-system, to receive the first compressed integer and the second compressed integer and to generate two operand ready for execution;an operation-execution-system to execute all the computations and operations to obtain the intermediate results to produce a third compressed integer; anda post-arrangement-system to receive the intermediate results from the operation-execution-system to produce the third compressed integer.3. The compressed domain processor as recited in claim 2 , wherein:the first compressed integer includes a first fixed length header and a first variable length code and the second compressed integer include a second fixed length header and a second variable length code; and a position subtraction component to receive the first fixed length header and the second fixed length header and to output a sign and a value;', receive the sign, the first and the second variable length code; and', 'select from the first variable length code and the second variable length code a long variable code and a short variable code based at least in part on the sign;, 'a swap unit configured to, 'a ...

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Номер записи: 41
15-01-2015 дата публикации

METHOD AND SYSTEM FOR TRANSMITTING DATA STREAM

Номер: US20150016343A1
Автор: YU Rongdao
Принадлежит:

Disclosed are a method and a system for transmitting a data stream, aiming at increasing system capacity. The method includes: transmitting, by a first sending end, a coded first data stream to a first receiving end, and transmitting, by a second sending end, a coded second data stream to a second receiving end on time-frequency resources occupied by transmission of the first data stream by the first sending end; decoding, by the first receiving end, a first received signal received to obtain a first decoded result, and transmitting at least one decoded result in the first decoded result to the second receiving end; and decoding, by the second receiving end, a second received signal received, by using the at least one decoded result in the first decoded result to obtain a second decoded result. 1. A method for transmitting a data stream , comprising:transmitting, by a first sending end, a coded first data stream to a first receiving end, and transmitting, by a second sending end, a coded second data stream to a second receiving end on time-frequency resources occupied by transmission of the first data stream by the first sending end, wherein when the second sending end codes the second data stream, interference of at least one data stream in the second data stream to the first receiving end is correspondingly aligned with at least one data stream in the first data stream according to number of antenna(s) configured for the first receiving end;decoding, by the first receiving end, a first received signal received to obtain a first decoded result, and transmitting at least one decoded result in the first decoded result to the second receiving end, wherein the first decoded result at least comprises sum data stream(s) of the above-mentioned correspondingly aligned data streams; anddecoding, by the second receiving end, a second received signal received, by using the at least one decoded result in the first decoded result to obtain a second decoded result, wherein the ...

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Номер записи: 42
03-02-2022 дата публикации

OFFSET VALUE DETERMINATION IN A CHECK NODE PROCESSING UNIT FOR MESSAGE-PASSING DECODING OF NON-BINARY CODES

Номер: US20220038116A1
Автор: Boutillon Emmanuel, HARB Hassan, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide an elementary check node processing unit () implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit () being linked to a variable node processing unit () and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit () comprises a calculation unit () which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit () also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit () also comprises a selection unit () which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit () then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (). 2. The elementary check node processing unit of claim 1 , wherein said decoding performance values comprise a bit error rate evaluated for a given signal-to-noise ratio.3. The elementary check node processing unit of claim 1 , wherein said first message comprises a first predefined number of components and said second message comprises a second predefined number of components claim 1 , each component of the first message and of the second message comprising a symbol and a reliability metrics associated with said symbol claim 1 , the calculation unit being configured to determine each auxiliary component among said ...

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Номер записи: 43
18-01-2018 дата публикации

ENTROPY ENCODING AND DECODING SCHEME

Номер: US20180019762A1
Автор: MARPE Detlev, NGUYEN Tung, SCHWARZ Heiko, WIEGAND Thomas
Принадлежит:

Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols swith i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols syields z, and, if n>1, for all i=1 . . . n−1, the value of scorresponds to a range of the ipartition. 1. A non-transitory computer-readable medium for storing video data , comprising:a data stream stored in the non-transitory computer-readable medium and comprising data associated with a first sequence of source symbols and a second sequence of source symbols, wherein the source symbols of the first and second sequences are obtained based on a sequence of syntax elements having a value range which is sub-divided into a sequence of N disjoint portions by executing operations using a processor, the operations including:{'sub': i', 'i', 'i, 'sup': 'th', 'converting the sequence of syntax elements into a sequence of source symbols by individually decomposing at least a subgroup of the syntax elements into a respective number n of source symbols swith i=1 . . . n, the respective number n of source symbols depending on as to which of the sequence of N disjoint portions a value z of the respective syntax elements falls into, such that a sum of values of the respective number of source symbols syields z, and, if n>1, for all i=1 . . . n−1, the value of ...

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Номер записи: 44
28-01-2016 дата публикации

System and Method for Circuit Card Insertion Tracking

Номер: US20160028404A1
Автор: Berke Stuart A., Farkas Sandor
Принадлежит: Dell Products, L.P.

Embodiments of systems and methods for circuit card insertion tracking are described. In an embodiment, a method may include detecting insertion of a pluggable circuit card into a socket connector, and incrementing a count of insertions in an insertion counter. 1. A method , comprising:detecting insertion of a pluggable circuit card into a socket connector; andincrementing a count of insertions in an insertion counter.2. The method of claim 1 , further comprising detecting insertion of the pluggable circuit card into the socket connector without external power being provided to either the pluggable circuit card or the socket connector.3. The method of claim 2 , wherein detecting insertion is performed by a mechanical detection device.4. The method of claim 2 , further comprising providing a dedicated power source for detecting insertion and incrementing the counter.5. The method of claim 4 , wherein the dedicated power source is a coin-cell battery.6. The method of claim 4 , wherein the dedicated power source is an electro-mechanical power source.7. The method of claim 1 , further comprising detecting that the socket connector is powered at the time that the pluggable circuit card is inserted into the socket connector.8. The method of claim 1 , further comprising recording an identifier of the pluggable circuit card inserted into the socket connector.9. The method of claim 1 , further comprising logging data associated with insertion of the pluggable circuit card into the socket connector in a system log.10. The method of claim 1 , further comprising communicating data associated with insertion of the pluggable circuit card into the socket connector to a third party.11. An Information Handling System (IHS) claim 1 , comprising:an insertion detector configured to detect insertion of a pluggable circuit card into a socket connector; andan insertion counter coupled to the insertion detector and configured to increment a count of insertions.12. The IHS of claim 11 , ...

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Номер записи: 45
04-02-2016 дата публикации

SORTING DECODER

Номер: US20160036461A1
Автор: Cronie Harm, Holden Brian
Принадлежит:

A sorting decoder captures the rank-order of a set of input analogue signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analogue-to-digital signal converters. The analogue signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components. 1. A sorting decoder comprising:a dynamic reference generator configured to generate a monotonic dynamic reference signal;a set of n comparators, each comparator configured to operate on (i) a respective input signal of a set of n input signals and (ii) the monotonic dynamic reference signal, the set of n comparators configured to form a set of n comparator outputs;a first logic circuit configured to detect when N comparator outputs of the set of n comparator outputs have a low state and n-N remaining comparator outputs have a high state and output a first latching signal, the N comparator outputs corresponding to a set of N most positive input signals, wherein 1≦N Подробнее

Номер записи: 46
01-02-2018 дата публикации

ENTROPY ENCODING AND DECODING SCHEME

Номер: US20180034472A1
Автор: MARPE Detlev, NGUYEN Tung, SCHWARZ Heiko, WIEGAND Thomas
Принадлежит:

Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols swith i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols syields z, and, if n>1, for all i=1 . . . n−1, the value of scorresponds to a range of the ipartition. 1. A non-transitory computer-readable medium for storing video data , comprising:a data stream stored in the non-transitory computer-readable medium and comprising data associated with a first sequence of source symbols and a second sequence of source symbols, wherein the source symbols of the first and second sequences are obtained based on a sequence of syntax elements having a value range which is sub-divided into a sequence of disjoint portions by executing operations using a processor, the operations including:converting the sequence of syntax elements into a sequence of source symbols by decomposing at least a subgroup of the syntax elements into a corresponding number of source symbols, based on a value of the respective syntax elements and a portion of the sequence of disjoint portions, such that a sum of values of the source symbols yields the value of the respective syntax element;subdividing the sequence of source symbols into a first sequence of source symbols and a second sequence of source symbols;encoding, into the data stream, the source ...

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Номер записи: 47
01-02-2018 дата публикации

Pad encoding and decoding

Номер: US20180034473A1
Автор: Frederic J. Bauchot, Marc Joel Herve Legroux
Принадлежит: International Business Machines Corp

A system, method and computer program product for encoding an input string of binary characters representing alphanumeric characters. A system includes: a character writing engine for writing a binary character to an empty cell of a multi-dimensional shape beginning with a starting empty cell; a next cell determination engine for determining a next empty cell by traversing neighboring cells in the multi-dimensional shape until an empty cell is located; a loop facilitator for looping back to the character writing engine and the next cell determining engine until no more data characters or a next empty cell is not determined; and a serialization engine for serializing the cells into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.

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Номер записи: 48
16-02-2017 дата публикации

DETECTION OF UNKNOWN CODE PAGE INDEXING TOKENS

Номер: US20170047943A1
Автор: Baessler Michael, Hampp-Bahnmueller Thomas A. P., Jiang Peng Hui
Принадлежит:

A method for determining an encoding used for a sequence of bytes may be provided. The method comprises providing a set of candidate code pages and transforming them into different groups of sequences of bytes, wherein each group of sequences of bytes corresponds to one of the candidate code pages. Thereby each code point is transformed by applying a transformation from one of the candidate code pages to a reference code point value relating to a reference encoding for each code point. The method comprises further separating each of the transformed sequences of bytes into groups of tokens, wherein each group of tokens relates to one candidate code page, and providing an index relating to a text corpus. Furthermore, the method comprises selecting a code page from the set of candidate code pages at least partially based on how many tokens are found in the index. 1. A method for determining an encoding used for a sequence of bytes , the method comprising:providing a set of candidate code pages adapted for decoding a sequence of bytes, wherein the sequence of bytes comprises one or more successions of digitally encoded characters;transforming the sequence of bytes into different groups of sequences of bytes based on the set of candidate code pages, wherein each code point within the sequences of bytes is transformed to a reference code point value relating to a reference encoding for each code point;separating each of the transformed sequences of bytes into groups of tokens, wherein the group of tokens relates to one candidate code page;providing an index relating to a text corpus, wherein the index comprises a set of tokens in the reference encoding; andselecting a code page within the set of candidate code pages at least partially based on a number of token relating to one of the set of candidate code pages is found in the index.2. The method of claim 1 , wherein the selecting a code page that code is based on a maximum number of matches between the group of tokens ...

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Номер записи: 49
03-03-2022 дата публикации

FORWARD ERROR CORRECTION USING NON-BINARY LOW DENSITY PARITY CHECK CODES

Номер: US20220069844A1
Автор: Abrams Stuart, Hadani Ronny, Namboodiri Vamadevan
Принадлежит:

Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink. 1. An apparatus for forward error correction , comprising:a processor-implemented encoder configured to encode information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries;a modulator configured to modulate, using an orthogonal time frequency space (OTFS) modulation scheme, the encoded information bits to generate a signal; anda transmitter configured to transmit the signal over a channel,wherein a parity matrix H for the NB-LDPC code is based on a binary H matrix, and 'add offsets to entries in a first column and entries in a first row of the binary H matrix such that the first column and the first row contain only identity elements.', 'wherein the binary H matrix is based on a computer search algorithm configured to2. The apparatus of claim 1 , wherein the computer search algorithm is configured to terminate upon a determination that no N-cycles are present in a Tanner graph representation of the binary H matrix claim 1 , and wherein N=4 or N=6.3. The apparatus of claim 1 , wherein the parity check matrix H is represented a H=[H claim 1 , H] claim 1 , where ...

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Номер записи: 50
22-02-2018 дата публикации

ALIGNMENT OF SAMPLES ACROSS DIFFERENT CLOCK DOMAINS

Номер: US20180054205A1
Автор: PETRICK BRUCE E.
Принадлежит:

Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes. 120-. (canceled)21. A synchronizer system for aligning power management data from multiple clock domains in measurement circuits , comprising:a first clock input clocked according to a first clock domain;a first power management characteristic (PMC) measurement input in the first clock domain;a first PMC output in the first clock domain, wherein the first PMC output comprises a first PMC sample of the first PMC measurement input associated with a code;a second clock input clocked according to a second clock domain;a second PMC measurement input in the second clock domain; anda second PMC output comprising a second PMC sample of the second PMC measurement input associated with the code, wherein the second PMC output is synchronized to the first clock domain as a function of being associated with the code.22. The synchronizer system of claim 21 , further comprising:a code synchronizer (CS) structure synchronized to the first clock domain, wherein the CS structure outputs the code corresponding to a first PMC sample time of the first PMC sample;a storage array coupled to the CS structure to receive the code ...

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Номер записи: 51
13-02-2020 дата публикации

ERROR CORRECTION CIRCUIT AND OPERATING METHOD THEREOF

Номер: US20200052716A1
Автор: KANG Soon Young, Kim Dae Sung
Принадлежит:

Provided herein may be an error correction circuit. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a NB-LDPC code may include a symbol configuration circuit for configuring an initial symbol to be assigned as a variable node value to a variable node, a reliability value initialization circuit for initializing first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node, and a symbol correction circuit updating the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and adjusting the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value. 1. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a Non-Binary Low Density Parity Check (NB-LDPC) code , comprising:a symbol configuration circuit configured to configure an initial symbol to be assigned as a variable node value to a variable node;a reliability value initialization circuit configured to initialize first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node; anda symbol correction circuit configured to update the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and configured to adjust the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value.2. The error correction circuit according to ...

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Номер записи: 52
22-05-2014 дата публикации

Fractional frequency divider with phase permutation

Номер: US20140139272A1
Автор: Stefan Tertinek
Принадлежит: Individual

Some embodiments of the present disclosure relate to a fractional divider for frequency generation. The fractional divider includes a permutation network including a plurality of phase input terminals and a plurality of permuted phase output terminals with a plurality of propagation paths extending therebetween. Multiple propagation paths extend between a phase input terminal and a permuted phase output terminal. A control unit switches an input signal on the phase input terminal through the multiple propagation paths in time to produce a permuted phase signal on the permuted phase output terminal. A phase selection element individually switches the permuted phase output terminals to an output terminal of the fractional divider in time to generate an output signal. The output signal has an output frequency that is a non-unity fraction of an input frequency of the input signal.

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Номер записи: 53
22-05-2014 дата публикации

DELAY-OPTIMIZED OVERLAP TRANSFORM, CODING/DECODING WEIGHTING WINDOWS

Номер: US20140139362A1
Автор: Faure Julien, Philippe Pierrick
Принадлежит: ORANGE

Coding/decoding of a digital signal, consisting of successive blocks of samples, the coding being of the transform with overlap type and comprising, upon analysis, the application of a weighting window to two blocks of M successive samples. In particular, this weighting window is asymmetric and comprises four distinct portions extending successively over the two aforesaid blocks, with: a first portion, increasing over a first interval of samples, a second portion, constant at a value of 1 over a second interval, a third portion, decreasing over a third interval, and a fourth portion, constant at a value of 0 over a fourth interval. 1. A method for coding a digital signal , said signal being made up of successive blocks of samples , the coding being of the transform with overlap type and comprising , upon analysis , the application of a weighting window over two successive blocks of M samples , a first portion, increasing over a first interval of samples,', 'a second portion, constant at a value of 1 over a second interval,', 'a third portion, decreasing over a third interval, and', 'a fourth portion, constant at a value of 0 over a fourth interval., 'wherein said weighting window is asymmetrical and comprises four distinct portions extending in succession over said two blocks, with2. The method as claimed in claim 1 , wherein the first claim 1 , second and third intervals are calculated at least as a function of the fourth interval.4. The method as claimed in claim 3 , wherein the term Cis between 3 and 5.6. The method as claimed in claim 5 , wherein the term Cis between 0.85 and 1.05.10. The method as claimed in claim 1 , wherein the first interval claim 1 , denoted R claim 1 , is of a duration given by:{'sub': 1', 'z', 'z, 'R=└M−M+1+0.5┘, in which M corresponds to the duration of a block, and Mcorresponds to the duration of the fourth interval.'}11. The method as claimed in claim 10 , wherein the third interval claim 10 , denoted R claim 10 , is of a duration ...

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Номер записи: 54
27-02-2020 дата публикации

ERROR CORRECTION DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME

Номер: US20200067538A1
Автор: JO Myung Jin, KANG Soon Young, Kim Dae Sung, SUNG Wan Je
Принадлежит:

An error correction device includes: a plurality of variable node units each configured to: receive a hard decision bit and a channel reliability value having a first bit-precision; and perform an iteration of a decoding operation on the hard decision bit based on the channel reliability value; a plurality of check node units each configured to: receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; and transmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto, wherein, during the iteration, each of the plurality of variable node units further: receives one or more first check reliability values from one or more check node units coupled thereto among the plurality of check node units; and updates the hard decision bit with reference to the channel reliability value and the one or more first check reliability values by upsizing the first bit-precision of the channel reliability value and the second bit-precision of the one or more first check reliability values. 1. An error correction device comprising:a plurality of variable node units each configured to:receive a hard decision bit and a channel reliability value having a first bit-precision; andperform an iteration of a decoding operation on the hard decision bit based on the channel reliability value;a plurality of check node units each configured to:receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; andtransmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto,wherein, ...

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Номер записи: 55
15-03-2018 дата публикации

ELEMENTARY CHECK NODE PROCESSING FOR SYNDROME COMPUTATION FOR NON-BINARY LDPC CODES DECODING

Номер: US20180076830A1
Автор: Boutillon Emmanuel, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a check node processing unit implemented in a decoder for decoding a signal, the check node processing unit being configured to receive at least three input messages and to generate at least one output message, wherein the check node processing unit comprises: 1. A check node processing unit implemented in a decoder for decoding a signal , the check node processing unit being configured to receive at least three input messages and to generate at least one output message , wherein the check node processing unit comprises:a syndrome calculator configured to determine a set of syndromes from said at least three input messages using at least two elementary check node processors, each syndrome comprising a symbol, a reliability metric associated with said symbol, and a binary vector;a decorrelation unit configured to determine, in association with at least an output message, a set of candidate components from said set of syndromes, each candidate component comprising a symbol and a reliability metric associated with said symbol, said set of candidate components comprising one or more pairs of components comprising a same symbol; anda selection unit configured to determine at least an output message by selecting components comprising distinct symbols from the set of candidate components associated with said at least an output message.2344. The check node processing unit of claim 1 , wherein at least one elementary check node processor is configured to determine an intermediary message from a first message and a second message claim 1 , said first message and second message being derived from said at least three input messages claim 1 , said intermediary message comprising one or more components and an intermediary binary vector associated with each component claim 1 , each component comprising a symbol and a reliability metric associated with said symbol claim 1 , said one or more components being sorted into a given order of the ...

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Номер записи: 56
24-03-2016 дата публикации

APPARATUS AND METHOD FOR MAPPING BINARY TO TERNARY AND ITS REVERSE

Номер: US20160087646A1
Автор: Kalavade Pranav, MOTWANI RAVI H.
Принадлежит:

Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

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Номер записи: 57
02-04-2015 дата публикации

EFFICIENT TWO-STAGE ASYNCHRONOUS SAMPLE-RATE CONVERTER

Номер: US20150091743A1
Автор: Lavacek Dave, Stewart David P., Whikehart J. Willliam
Принадлежит: VISTEON GLOBAL TECHNOLOGIES, INC.

Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter. 1. A sample-rate converter system , comprising:a simple asynchronous sample-rate converter having an input and an output; anda synchronous sample-rate converter having an input and an output, wherein the output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter.2. The system of claim 1 , wherein the synchronous sample-rate converter comprises a full synchronous sample-rate converter.3. The system of claim 1 , wherein the simple asynchronous sample-rate converter has an input sample-rate and an output sample-rate claim 1 , wherein the ratio of the input sample-rate over the output sample-rate is approximately equal to unity.4. The system of claim 1 , wherein the simple asynchronous sample-rate converter comprises a sample buffer and a controller.5. The system of claim 1 , wherein the synchronous sample-rate converter comprises a sample buffer and a controller/calculator.6. The system of claim 1 , wherein the simple asynchronous sample-rate converter comprises a packet buffer and a controller.7. The system of claim 1 , wherein the synchronous sample-rate converter comprises a packet buffer and a controller/calculator.8. A sample-rate converter system claim 1 , comprising:a synchronous sample-rate converter having an input and an output; anda simple asynchronous sample-rate converter having an input and an output, wherein the output of the ...

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Номер записи: 58
12-03-2020 дата публикации

Systems and methods for variable-length encoding and decoding for enhancing computer systems

Номер: US20200084200A1
Автор: Brian Penny, Desmond Penny
Принадлежит: Kara Partners LLC

A method for variable length decoding, the method including: receiving, in a default word length mode, at least one first data word having a default first word length; combining the received at least one first data word as a first portion of data; receiving, after the at least one first data word, a transition word indicative of transitioning to a variable word length mode; receiving, after the transition word, a first word length word indicative of a second word length; receiving, after the first word length word, at least one second data word having the second word length; and combining the received at least one second data word as a second portion of the data.

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Номер записи: 59
31-03-2016 дата публикации

Non-binary low density parity check (NB-LDPC) codes for communication systems

Номер: US20160094246A1
Автор: Shen Ba-Zhong, Vasista Srinivasan Ranganathan Sudarsan
Принадлежит: BROADCOM CORPORATION

A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. The device receives a non-binary low density parity check (NB-LDPC) coded signal. The device then decodes the NB-LDPC coded signal using a NB-LDPC matrix to generate estimates of information bits encoded therein. The NB-LDPC matrix is characterized by a base proto-matrix having elements that represent sub-matrices, and the elements are selected from a finite Galois field that includes symbols. In another example, the device encodes other information bits using a generator matrix to generate another NB-LDPC coded signal and then transmits this other NB-LDPC coded signal. 1. A communication device comprising: receive a non-binary low density parity check (NB-LDPC) coded signal; and', 'decode the NB-LDPC coded signal using a NB-LDPC matrix to generate estimates of information bits encoded therein, wherein the NB-LDPC matrix is characterized by a base proto-matrix having a plurality of elements that represent a plurality of sub-matrices, wherein the plurality of elements are selected from a finite Galois field that includes 2-bit symbols, wherein a plurality of edges specify connectivity between a plurality of check nodes and a plurality of variable nodes based on the NB-LDPC matrix, and wherein each edge of a subset of edges of the plurality of edges corresponding to a sub-matrix of the plurality of sub-matrices that is based on a non-zero-valued 2-bit symbol has a common weight., 'a processor configured to2. The communication device of claim 1 , wherein:a zero-valued 2-bit symbol within the base proto-matrix ...

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Номер записи: 60
09-04-2015 дата публикации

DEVICE AND METHOD FOR CONVERTING DATA RATE

Номер: US20150097708A1
Автор: Eo Ik Soo, Kim Sang-Kyun, PARK Mi Jeong
Принадлежит: Electronics and Telecommunications Research Institute

A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter. 1. A device that converts a rate of input data , the device comprising: an output clock counter that performs a counting operation based on the output clock according to a first enable signal;', 'a counter enable generator that generates a second enable signal using a counting value of the output clock counter and that generates a third enable signal by delaying the second enable signal based on the input clock; and', 'an input clock counter that generates the rate by performing the counting operation based on the input clock according to the first enable signal and the second enable signal;, 'a rate counter that calculates a rate representing a ratio of frequencies of an input clock and an output clock, wherein the rate counter comprisesa phase accumulator that generates a first parameter representing a memory address position to sample using the rate and a second parameter representing a phase value of an estimation time point;an asynchronous data sampler that records data that is input based on an input clock and that outputs continued data using the first parameter based on an output clock;a filter coefficient operation unit that calculates a plurality of first operation values using the continued data and a plurality of filter coefficients; anda phase operation unit that generates and outputs final data using the plurality of first operation values and the second parameter.2. (canceled)3. The device of claim 1 , wherein the phase accumulator comprises:a rate enable generator that generates a fifth enable ...

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Номер записи: 61
28-03-2019 дата публикации

ENTROPY ENCODING AND DECODING SCHEME

Номер: US20190097649A1
Автор: MARPE Detlev, NGUYEN Tung, SCHWARZ Heiko, WIEGAND Thomas
Принадлежит:

Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols swith i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols syields z, and, if n>1, for all i=1 . . . n−1, the value of scorresponds to a range of the ipartition. 1. An apparatus for decoding comprising:a symbol decoder configured to:obtain, based on codewords from a data stream, a first sequence of source symbols and a second sequence of source symbols, wherein source symbols of the first and second sequences are related to level values of transform coefficients of a transform coefficient block, wherein the symbol decoder is configured to obtain a source symbol of the first sequence using arithmetic context-based entropy coding and a source symbol of the second sequence using Exp-Golomb coding; anda composer configured to: obtaining a set of source symbols from the first and second sequences based on a portion of the plurality of disjoint portions associated with the syntax element, and', 'combining values of the source symbols of the set to determine the value of the syntax element., 'compose a sequence of syntax elements having a value range which is sub-divided into a plurality of disjoint portions by, for each syntax element2. The apparatus of claim 1 , wherein the symbol decoder comprises:a first decoder ...

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Номер записи: 62
03-07-2014 дата публикации

HIERARCHICAL ENTROPY ENCODING AND DECODING

Номер: US20140184430A1
Автор: Cai Kangying, Hu Ping, Jiang Wenfei
Принадлежит: THOMSON LICENSING

A particular implementation receives geometry data of a 3D mesh, and represents the geometry data with an octree. The particular implementation partitions the octree into three parts, wherein the symbols corresponding to the middle part of the octree are hierarchical entropy encoded. To partition the octree into three parts, different thresholds are used. Depending on whether a symbol associated with a node is an S1 symbol, the child node of the node is included in the middle part or the upper part of the octree. In hierarchical entropy encoding, a non-S1 symbol is first encoded as a pre-determined symbol ‘X’ using symbol set S2={S1, ‘X’} and the non-S1 symbol itself is then encoded using symbol set S0 (S2⊂S0), and an S1 symbol is encoded using symbol set S2. Another implementation defines corresponding hierarchical entropy decoding. A further implementation reconstructs the octree and restores the geometry data of a 3D mesh from the octree representation. 1. A method , comprising:determining that a symbol in a sequence of symbols does not belong to a first symbol set;encoding a pre-determined symbol to represent the determined symbol, using a statistical model for the first symbol set and the pre-determined symbol; andencoding the determined symbol, using a statistical model for a second symbol set.2. The method of claim 1 , wherein the second symbol set is a superset of the first symbol set and the pre-determined symbol does not belong to the second symbol set.3. The method of claim 1 , further comprising:encoding a second sequence of symbols using the statistical model for the second symbol set; andencoding a third sequence of symbols using a statistical model for a third symbol set.4. The method of claim 3 , wherein the third symbol set is the same as the first symbol set.5. The method of claim 3 , further comprising:receiving geometry data of a 3D mesh;representing the geometry data using a tree data structure; andpartitioning the tree data structure into three ...

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Номер записи: 63
08-04-2021 дата публикации

PHASE ROTATOR NON-LINEARITY REDUCTION

Номер: US20210105016A1
Автор: DICLEMENTE Dominic, VAN IERSSEL Marcus
Принадлежит:

A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal. 1. (canceled)2. An integrated circuit , comprising:a phase interpolator biased by a selectable current, the phase interpolator configured to receive two or more signals having different phases and to produces an output signal having a phase; and,digital code to analog current converter circuitry to determine the selectable current corresponding to the digital code, the selectable current provided for a given digital code using a resistive ladder network and to have a non-linear relationship that reduces a non-linearity in a relationship between the digital code and the phase of the output signal, the non-linear relationship to be adjustable by control circuitry that draws current from a midpoint node of the resistive ladder network.3. The integrated circuit of claim 2 , wherein the digital code is to be provided as a thermometer code.4. The integrated circuit of claim 3 , wherein the analog current converter circuitry comprises a set of current switching circuits responsive to the thermometer code to allow a respective current to flow and to substantially block current from flowing.5. The integrated circuit of claim 4 , wherein a set of current limiting circuits each include a respective field-effect transistor that is biased by the resistive ladder network to ...

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Номер записи: 64
30-04-2015 дата публикации

Method and Apparatus for Regular Expression Processing with Parallel Bit Streams

Номер: US20150116136A1
Автор: Cameron Robert D.
Принадлежит:

One embodiment of the present invention is a method for increasing the speed of a computer in identifying occurrences of strings in a character stream that match a string pattern involving repetitions of characters of a particular character class. The method uses a parallel bit stream processing module of the computer, which processing module includes a processor equipped with parallel processing instructions, to form a plurality of parallel property bit streams Pj. 1. A method for increasing the speed of a computer in identifying occurrences of strings in a character stream that match a string pattern involving repetitions of characters of a particular character class , the method comprises:in a parallel bit stream processing module of the computer, which processing module includes a processor equipped with parallel processing instructions, in response to the character stream, using the parallel processing instructions to form a plurality of parallel property bit streams Pj wherein each of the parallel property bit streams consists of a stream of bit values Pj(i) such that Pj(i) is a property associated with code unit C(i) of the character stream and each parallel processing instruction produces a plurality of bit values Pj (i), and segments the parallel property bit streams into blocks, each block consisting of bit values Pj (i) at a multiplicity of positions i;operating on the blocks with bitwise logic operations and/or shifting operations to form a character class bit stream to identify positions in the character stream that have members of the particular character class;obtaining a cursor bit stream identifying starting positions for simultaneous string matches;adding the cursor bit stream to the character class bit stream to produce a temporary bitstream; andapplying bitwise logic to the temporary bit stream and the character class bit stream to produce an output cursor stream whose one bits exclusively identify the end points following each string match.2. ...

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Номер записи: 65
20-04-2017 дата публикации

Method and system for extracting rule specific data from a computer word

Номер: US20170109632A1
Автор: Chiranjib BHANDARY
Принадлежит: Avanseus Holdings Pte Ltd

The invention provides method and system for extracting rule specific data from a computer word. The method comprises: calculating at least one decimal value based on a rule representation associated with a rule, the rule representation is a byte array, value of each bit of the byte array representing whether a corresponding bit position in the computer word has a data component; identifying at least one result byte array based on the calculated decimal value from a preset look-up table, which includes a plurality of mappings, each between a result byte array and a decimal value, the result byte array indicating a set of reference bit positions for determining a set of bit positions in the computer word in which data components related to the rule are stored, and a last byte of the result byte array representing a bit count value associated with the set of reference bit positions.

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Номер записи: 66
30-04-2015 дата публикации

DATA ENCODING WITH SIGN DATA HIDING

Номер: US20150120798A1
Автор: Jeong Yo Won, Jung Young Beom, Kwon Nyeong Kyu, Lim Yo Han
Принадлежит:

A method of encoding data includes selecting a line to define an adjustment target coefficient group in each of a plurality of coefficient groups included in a transform unit that has been transformed and quantized. Each of the coefficient groups comprises a plurality of coefficients. For each of the coefficient groups, a sum of the coefficients for the respective coefficient group is calculated. For each of the coefficient groups, a value of one adjustment target coefficient included in the adjustment target coefficient group is adjusted according to a result of the calculation of the sum of the coefficients for the respective coefficient group. 1. A method of encoding data comprising:selecting a line to define an adjustment target coefficient group in each of a plurality of coefficient groups included in a transform unit that has been transformed and quantized, each of the coefficient groups comprising a plurality of coefficients;calculating, for each of the coefficient groups, a sum of the coefficients for the respective coefficient group; andadjusting, for each of the coefficient groups, a value of one adjustment target coefficient included in the adjustment target coefficient group according to a result of the calculation of the sum of the coefficients for the respective coefficient group.2. The method of claim 1 , wherein the line is a column at a same position amongst a plurality of columns in each of the coefficient groups.3. The method of claim 2 , wherein the column is one of a rightmost or a leftmost column.4. The method of claim 1 , wherein the line is a row at a same position amongst a plurality of rows in each of the coefficient groups.5. The method of claim 4 , wherein the row is one of a topmost or a bottommost row.6. The method of claim 1 , wherein adjusting the value of one of the adjustment target coefficients comprises increasing or decreasing the value by one when the sum of the coefficients is an even number and a sign of a first non-zero ...

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Номер записи: 67
13-05-2021 дата публикации

SIMPLIFIED CHECK NODE PROCESSING IN NON-BINARY LDPC DECODER

Номер: US20210143838A1
Автор: Boutillon Emmanuel, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: 1. A decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages , wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes , each block of sub-check node being configured to:determine a set of sub-check node syndromes from at least one variable node message among said at least three variable node messages; anddetermine at least one check node message from at least one syndrome.2. The decoder of claim 1 , wherein it further comprises at least one message presorting unit configured to determine permuted variable node messages by applying one or more permutations to the at least three variable node messages claim 1 , each block of sub-check node being configured to determine said set of sub-check node syndromes from at least one permuted variable node message of said permuted variable node messages.3. The decoder of claim 1 , further comprising a block division unit configured to perform a division of at least one check node processing unit into at least two blocks of sub-check nodes using a set of block division parameters.4. The decoder of claim 1 , wherein at least one check node processing unit comprises at least two blocks of sub-check nodes claim 1 , at least one block of sub-check node implementing a syndrome sub-check node architecture and at least one block of sub-check node implementing a forward-backward architecture.5. The decoder of claim 3 , wherein the set ...

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Номер записи: 68
25-04-2019 дата публикации

GROUPS OF PHASE INVARIANT CODEWORDS

Номер: US20190123765A1
Автор: Gaubatz Matthew D., Simske Steven J., Ulichney Robert
Принадлежит:

Disclosed herein are a system, non-transitory computer-readable medium, and method for encoding and decoding information on a data bearing medium. A message comprising a bit string is read. A plurality of substrings in the message may be associated with a phase invariant codeword. 1. A method of encoding a message , comprising:reading a message comprising a bit string of a first length;dividing the message into a plurality of substrings, each substring having a second length shorter than the first length;determining a phase invariant codeword associated with each substring; and,generating a composite codeword comprising each phase invariant codeword.2. A method as in claim 1 , wherein determining a phase invariant codeword associated with each substring comprises:based on selection criteria, and where each of a number of groups of phase invariant codewords has a different property, selecting a group of phase invariant codewords having a particular property; and,selecting a phase invariant codeword associated with the substring from within the selected group of phase invariant codewords.3. A method as in claim 1 , wherein the particular property is a range of values defining the number of active bits in the phase invariant codeword of each group.4. A method as in claim 2 , wherein the selection criteria comprise a selection criterion chosen from phase invariant codewords being selected from a single group claim 2 , and phase invariant codewords being selected from any combination of the groups.5. A method as in claim 1 , wherein generating a composite codeword comprising each phase invariant codeword comprises:interspersing each symbol of each phase invariant codeword with respective symbols of each of the other phase invariant codewords.6. A method as in claim 1 , wherein determining a phase invariant codeword associated with each substring comprises:searching a LUT (look up table) that comprises stored associations between phase invariant codewords and bit strings ...

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Номер записи: 69
12-05-2016 дата публикации

DETERMINATION OF ENCODING BASED ON PERCEIVED CODE POINT CLASSES

Номер: US20160134303A1
Автор: Cox Benjamin D., Francis Stewart O. M.
Принадлежит:

A method, a computer program product, and a computer system for determination of encoding based on received code point classes are provided. The computer implemented method includes transferring data in a text form. The computer implemented method includes, in response to determining that decoding the data in text form passes, transferring some or all of the data in a binary form. The computer implemented method includes calculating code point class proportions for the data in the text form and the data in the binary form and determining a best form for transferring the data, based on comparison of the code point class proportions. 1. A method for determination of encoding based on received code point classes , the method comprising:transferring data in a text form;in response to determining that decoding the data in the text form is successful, transferring some or all of the data in a binary form;calculating code point class proportions for the data in the text form and the data in the binary form; anddetermining a best form for transferring the data, based on comparison of the code point class proportions, wherein the best form is chosen from the binary form and the text form, wherein the best form encodes the data correctly with greater confidence.2. The method of claim 1 , further comprising:in response to determining that the text form is the best form, using the data in the text form.3. The method of claim 1 , further comprising:in response to determining that the text form is not the best form, transferring the data in the binary form; andusing the data in the binary form.4. The method of claim 1 , further comprising:in response to determining that decoding the data in text form is not successful, transferring the data in the binary form; andusing the data in the binary form.512-. (canceled) The present invention relates generally to data encoding, and more particularly to determination of encoding based on received code point classes.Text data can be stored ...

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Номер записи: 70
21-05-2015 дата публикации

Generating an ICONV Module in Real Time

Номер: US20150138003A1
Автор: Liu Su, Qu Rong, Tinnakul Teerasit
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Provided are techniques for detecting a mapping, by a universal convertor, of a first character set to a second character set and of the second character set to a third character set; monitoring, logging, and analyzing code set conversion (CSC) operations; generating a updated character set conversion module from the first character set to the third character set in response to the detecting and a determination that the CSC operation exceed the predefined threshold; and storing the updated character set conversion module for utilization of subsequent processing of the first character set to the third character set. 1. A method , comprising:detecting a mapping, by a universal convertor, of a first character set to a second character set and of the second character set to a third character set;generating a updated character set conversion module from the first character set to the third character set in response to the detecting; andstoring the updated character set conversion module for utilization of subsequent processing of the first character set to the third character set.2. The method of claim 1 , wherein the updated character set conversion module is stored in conjunction with a default character set conversion table.3. The method of claim 1 , further comprising:monitoring, logging, and analyzing code set conversion (CSC) operations; anddetermining that the CSC operations corresponding to mapping exceed a predefined threshold;wherein the generating is in response to both the detecting of the mapping and the determining that the CSC operations exceed the threshold.4. The method of claim 1 , wherein the monitoring is performed at an operating system level.5. The method of claim 1 , wherein the updated character set conversion is employed by an operating system.6. The method of claim 1 , wherein the character set conversion module is configured as an iconv utility.7. The method of claim 1 , further comprising:bypassing the universal convertor during the subsequent ...

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Номер записи: 71
10-05-2018 дата публикации

METHOD FOR CONTROLLING A CHECK NODE OF A NB-LDPC DECODER AND CORRESPONDING CHECK NODE

Номер: US20180131395A1
Автор: Boutillon Emmanuel, LEHNIGK-EMDEN Timo, SCHLÄFER Philipp
Принадлежит:

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives dinput lists Uand delivers and delivers doutput lists V, with iϵ[1 . . . d]. Each input list and output list includes nelements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q>n. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of delements of input lists U. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list. 1. A method for controlling a check node of a decoder for decoding non-binary LDPC codes , the check node receiving dc input lists Ui of nm elements (Ui[j]) and delivering dc output lists Vi of n′m elements (Vi[j]) , with “iϵ[1 . . . ” “d”_“c” “]” , with dc>2 , each element of the input or output lists , called respectively input element and output , comprising a reliability value (LLR(Ui[j]) , LLR(Vi[j])) associated to a symbol (GF(Ui[j]) , GF(Vi[j])) of a Galois Field GF(q) with q>nm and q>n′m , the input elements and output elements being substantially sorted according to the reliability values respectively in the input list and output list , the method comprising:adding dc input elements of input lists Ui in order to generate a plurality of sums called syndromes, each of the input elements belonging to a distinctive input list among the dc input lists Ui and each syndrome comprising a reliability value which is the sum of the reliability values of the input elements and a symbol of the Galois field which is the sum of the symbols of the input elements in the Galois field,applying, for each output list Vi, a decorrelation to the syndromes by subtracting the input element of the input list Ui from the syndromes in order to generate decorrelated syndromes, andselecting, for each output ...

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Номер записи: 72
03-06-2021 дата публикации

DYNAMIC SELF-CORRECTION OF MESSAGE RELIABILITY IN LDPC CODES

Номер: US20210165712A1
Автор: Kwok Zion S., Mitra Debarnab, MOTWANI RAVI H.
Принадлежит: Intel Corporation

An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed. 1. An electronic apparatus , comprising:one or more substrates; and detect unreliable messages between check nodes and variable nodes in association with an error correction operation,', 'determine respective degrees of unreliability for the unreliable messages, and', 'reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability., 'logic coupled to the one or more substrates, the logic to2. The apparatus of claim 1 , wherein the logic is further to:increase a reliability factor of reliable messages sent from the check nodes to the variables nodes and keep unreliable messages sent from the check nodes to the variables nodes unchanged to reduce the influence of the unreliable messages sent from the check nodes to the variable nodes.3. The apparatus of claim 1 , wherein the logic is further to:reduce a reliability factor of unreliable messages sent from the variable nodes to the check nodes and keep the reliable messages sent from the variable nodes to the check nodes unchanged to reduce the influence of unreliable messages sent from the variable nodes to the check nodes.4. The apparatus of claim 1 , wherein the logic is further to:calculate a message to be sent from a check node to a ...

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Номер записи: 73
23-04-2020 дата публикации

Simplified, presorted, syndrome-based, extended min-sum (ems) decoding of non-binary ldpc codes

Номер: US20200127683A1
Автор: Cédric MARCHAND, Emmanuel Boutillon
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a check node processing unit ( 25 ) configured to determine at least one check node message to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units ( 24 ) configured to determine permuted variable node messages by applying one or more permutations to at least three variable node messages generated by one or more variable node processing units ( 23 ); a syndrome calculation unit ( 26 ) configured to determine a set of syndromes from the at least three permuted variable node messages, a syndrome comprising binary values; a decorrelation and permutation unit ( 27 ) configured, for each check node message of a given index, to: Determine a permuted index by applying to said given index the inverse of the one or more permutations; Select at least one valid syndrome in the set of syndromes, a valid syndrome comprising a binary value associated with said permuted index equal to a given value; Determine, at least one candidate check node component from said at least one valid syndrome; a selection unit ( 28 ) configured to determine at least one check node message from said at least one candidate check node component.

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Номер записи: 74
19-05-2016 дата публикации

FREQUENCY DIVISION CLOCK ALIGNMENT USING PATTERN SELECTION

Номер: US20160142067A1
Автор: Aiken Steve, Balasubramanian Suresh, Faldamis Georgios
Принадлежит:

Generating a clock signal includes: at a root node of a clock distribution network, receiving a first clock signal generated based on a reference clock signal; at a first leaf node, detecting a reference event associated with the reference clock signal and generating a synchronizing signal; passing the synchronizing signal from the first leaf node to the root node; at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal, and distributing the second clock signal to the leaf nodes. Generating the second clock signal includes selecting a repeating pattern of cycles of the first clock signal including fewer than all of the cycles of the first clock signal, and at least every cycle of the first clock signal that is shifted in time by a propagation delay with respect to a rising edge of the reference clock signal. 1. A method for generating a clock signal , comprising:at a root node of a clock distribution network, receiving a first clock signal generated based on a reference clock signal;at a first leaf node of a plurality of leaf nodes of the clock distribution network, detecting a reference event associated with the reference clock signal and generating a synchronizing signal based on the detection of the reference event;passing the synchronizing signal from the first leaf node to the root node;at the root node, generating a second clock signal from the first clock signal synchronized to the synchronizing signal received at the root node, and distributing the second clock signal to the leaf nodes of the clock distribution network, the generating of the second clock signal including selecting a repeating pattern of cycles of the first clock signal, wherein the repeating pattern includes fewer than all of the cycles of the first clock signal, and at least every cycle of the first clock signal that is shifted in time by a propagation delay with respect to a rising edge of the reference clock signal or every ...

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Номер записи: 75
03-06-2021 дата публикации

VARIABLE NODE PROCESSING METHODS AND DEVICES FOR MESSAGE-PASSING DECODING OF NON-BINARY CODES

Номер: US20210167799A1
Автор: Boutillon Emmanuel, HARB Hassan, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a variable node processing unit () for a non-binary error correcting code decoder, the variable node processing unit () being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit () comprises: 1. A variable node processing unit for a non-binary error correcting code decoder , the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics , and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics , the intrinsic reliability metrics being derived from a received signal , an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol , wherein the variable node processing unit comprises:a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.2. The variable node processing unit of claim 1 , wherein the variable node processing unit comprises a calculation unit configured to determine a first auxiliary message from the check node message and the intrinsic reliability metrics and a second auxiliary message from the intrinsic reliability metrics associated with a ...

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Номер записи: 76
03-06-2021 дата публикации

SYSTEMS AND METHODS FOR VARIABLE-LENGTH ENCODING AND DECODING FOR ENHANCING COMPUTER SYSTEMS

Номер: US20210168131A1
Автор: Penny Brian, Penny Desmond
Принадлежит:

A method for variable length decoding, the method including: receiving, in a default word length mode, at least one first data word having a default first word length; combining the received at least one first data word as a first portion of data; receiving, after the at least one first data word, a transition word indicative of transitioning to a variable word length mode; receiving, after the transition word, a first word length word indicative of a second word length; receiving, after the first word length word, at least one second data word having the second word length; and combining the received at least one second data word as a second portion of the data. 1. A system comprising:at least one processor; and receive a first sequence of values;', 'segment the first sequence of values into a plurality of subsequences each having respective lengths;', 'modify each of the plurality of subsequences by inserting one or more values into at least one of the plurality of subsequences to create a plurality of modified subsequences each having a same final length;', 'combine the plurality of modified subsequences to create a second sequence of values; and', 'output the second sequence of values., 'at least one memory, having stored thereon computer program code that, when executed by the at least one processor, controls the at least one processor to2. The system of claim 1 , wherein the computer program code claim 1 , when executed by the at least one processor claim 1 , further controls the at least one processor to output the second sequence of values for transmission to a destination device.3. The system of claim 2 , wherein the respective lengths of the plurality of subsequences and the final length are known by the destination device.4. The system of claim 1 , wherein the computer program code claim 1 , when executed by the at least one processor claim 1 , controls the at least one processor to output the second sequence of values for processing of the second ...

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Номер записи: 77
30-04-2020 дата публикации

PLEAT COUNTER

Номер: US20200132506A1
Автор: Williams Steve
Принадлежит: K&N Engineering, Inc

A pleat counter and methods are provided to accurately count the number of pleats in a corrugated sheet of material to be used for the production of air filters. The pleat counter comprises a pleat detector mounted underneath a mounting board for counting the pleats. The mounting board is configured to position the pleat detector adjacent to the corrugated sheet of filter material. The pleat detector includes one or more sensors configured to detect the presence of individual pleats comprising the corrugated sheet. The pleat counter includes an interface configured to enable coupling the pleat counter with a data processing system. The data processing system may comprise any of a desktop, a tablet, a server, a mobile phone, a media player, a personal digital assistant (PDA), a personal communicator, a network router or hub, a wireless access point (AP) or repeater, a set-top box, or a combination thereof. 1. A pleat counter , comprising:a mounting board for supporting one or more sensors;a pleat detector for counting a number of pleats comprising a corrugated sheet of filter material; andan interface for coupling the pleat counter with a data processing system.2. The pleat counter of claim 1 , wherein the pleat detector is mounted underneath the mounting board for the purpose of counting the number of pleats comprising the corrugated sheet of filter material.3. The pleat counter of claim 2 , wherein the mounting board is configured to position the pleat detector adjacent to the corrugated sheet of filter material.4. The pleat counter of claim 3 , wherein the pleat counter is configured to remain in a stationary disposition while the corrugated sheet of filter material is steadily translated nearby the pleat detector claim 3 , such that the pleats passing by the detector are detectable.5. The pleat counter of claim 1 , wherein the data processing system comprises any of a desktop claim 1 , a tablet claim 1 , a server claim 1 , a mobile phone claim 1 , a media player ...

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Номер записи: 78
14-08-2014 дата публикации

Systems and Methods for Shared Layer Data Decoding

Номер: US20140226229A1
Автор: Bolotov Anatoli, Wang Chung-Li, Wilson Bruce A., Yang Shaohua
Принадлежит: LSI Corporation

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. 1. A data processing system , the data processing system comprising: receive a data input that includes at least a first data set and a second data set;', 'encode the data set to yield a first encoded output and a second encoded output, wherein the first encoded output includes the first data set and a first encoded data, wherein the second encoded output includes the second data set and a second encoded data, and wherein the first encoded data and the second encoded data are generated from a combination of the first data set and the second data set;', 'encode the first encoded output to yield a first codeword, wherein the first codeword includes the first encoded output and a third encoded data unrelated to the second encoded output; and', 'encode the second encoded output to yield a second codeword, wherein the second codeword includes the second encoded output and a fourth encoded data unrelated to the first encoded output; and, 'a data encoder circuit operable to decode the first codeword to yield a third encoded output and a fifth encoded data;', 'decode the second codeword to yield a fourth encoded output and a sixth encoded data; and', generate a first feedback based at least in part upon the third encoded output and the fourth encoded output; and', 're-decode the first codeword using the first feedback as a guide., 'where the third encoded output is different from the first encoded output, the data decoder circuit is further operable to], 'a data decoder circuit operable to2. The data processing system of claim 1 , wherein the data processing system is implemented as part of a storage device claim 1 , and wherein the storage device comprises:a storage medium operable to store the first codeword and the second codeword.3. The data processing system of claim 1 , wherein the data processing system is ...

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Номер записи: 79
30-04-2020 дата публикации

Hybrid Comparison for Unicode Text Strings Consisting Primarily of ASCII Characters

Номер: US20200134254A1
Автор: Kemper Alfons, Leis Viktor, Neumann Thomas
Принадлежит:

A method compares text strings having Unicode encoding. The method receives a first string S=ss. . . sand a second string T=tt. . . t, where s, s, . . . , sand t, t, . . . , tare Unicode characters. The method computes a first string weight for the first string S according to a weight function ƒ. When S consists of ASCII characters, ƒ(S)=S. When S consists of ASCII characters and some accented ASCII characters that are replaceable by ASCII characters, ƒ(S)=g(s)g(s) . . . g(s), where g(s)=swhen sis an ASCII character and g(s)=s′when sis an accented ASCII character that is replaceable by the corresponding ASCII character s′. The method also computes a second string weight for the second text string T. Equality of the strings is tested using the string weights. 1. A method of comparing text strings having Unicode encoding , comprising:at a computer having one or more processors, and memory storing one or more programs configured for execution by the one or more processors:{'sub': 1', '2', 'n', '1', '2', 'm', '1', '2', 'n', '1', '2', 'm, 'receiving a first text string S=ss. . . s, having Unicode encoding and a second text string T=tt. . . thaving Unicode encoding, wherein n and m are positive integers, and s, s, . . . , sand t, t, . . . , tare Unicode characters;'} when it is determined that S consists entirely of ASCII characters, ƒ(S)=S; and', {'sub': 1', '2', 'n', 'i', 'i', 'i', 'i', 'i', 'i', 'i, 'when it is determined that S consists of ASCII characters and one or more accented ASCII characters that are replaceable by corresponding ASCII characters, ƒ(S)=g(s)g(s) . . . g(s), wherein g(s)=swhen sis an ASCII character and g(s)=s′when sis an accented ASCII character that is replaceable by the corresponding ASCII character s;'}], 'computing, for the first text string S, a first string weight ƒ(S) according to a weight function ƒ, computed according tocomputing, a second string weight ƒ(T), for the second text string T, according to the weight function ƒ; anddetermining ...

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Номер записи: 80
26-05-2016 дата публикации

EFFICIENT DECODER FOR CURRENT-STEERING DIGITAL-TO-ANALOG CONVERTER

Номер: US20160149587A1
Автор: MULDER Jan
Принадлежит:

A decoder for a current-steering digital-to-analog converter (DAC) is described herein. In an embodiment, the decoder is a dynamic element matching (DEM) row/column decoder that randomizes pairs of row control signals and column control signals that are provided to a matrix of current cells. The randomization is performed in a manner that ensures that the pairs of row control signals are randomized as pairs. In another embodiment, the decoder is an N-dimensional decoder, where N is any integer greater than two. The N-dimensional decoder comprises an N number of decoders that are each configured to provide respective control signals that are provided to current source(s) in current cell(s) in a respective dimension of an N-dimensional matrix of current cells for enabling current source(s) included therein. Such decoders advantageously allow for a simpler, more efficient design compared to a non-segmented, unary DAC due to the smaller area and lower power consumed. 1. An apparatus , comprising:a first decoder configured to decode a first plurality of input data bits to generate a first plurality of decoded bits;a first randomizer coupled to the first decoder, the first randomizer configured to randomize the first plurality of decoded bits to generate a first plurality of randomized bits, the first plurality of randomized bits being provided to one or more current cells in one or more rows of a matrix of current cells;a second decoder configured to decode a second plurality of input data bits to generate a second plurality of decoded bits; anda second randomizer coupled to the second decoder, the second decoder configured to randomize the second plurality of decoded bits to generate a second plurality of randomized bits, the second plurality of randomized bits being provided to one or more current cells in one or more columns of the matrix of current cells.2. (canceled)3. The apparatus of claim 2 , wherein the first decoder comprises a first binary-to-thermometer ...

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Номер записи: 81
24-05-2018 дата публикации

Sonic Boom: System For Reducing The Digital Footprint Of Data Streams Through Lossless Scalable Binary Substitution

Номер: US20180145701A1
Автор: Benavides Anthony Ben
Принадлежит:

Because all digital data streams are composed of randomly-distributed zeros (0s) and ones (1s) called bits, it can be posited that all arbitrary-length binary data sets having a finite magnitude can be distilled into numerically-precise integers that accurately represent the value of every individual bit within the set. Mathematically, once a data stream's bit structure has been analyzed, the exact combination of its uniquely-assembled bits, its “digital footprint”, can be perfectly replicated simply by calculating the numerical value of each consecutive bit to produce a decimal sum equal to the value of the entire stream. This universal data compression technique is called “SCALABLE BINARY SUBSTITUTION” because the functional objective of the scheme is to analyze the digital footprint of a source data stream, regardless of its magnitude, and substitute the entirety of its encoded information for a simple math expression: Absolutely lossless data compression through mathematically-precise substitution. 1. The invention claimed functions as a data substitution system by applying binary-to-decimal arithmetic to directly calculate the decimal value of each consecutive bit in any arbitrary-length binary source data set in order to produce an output decimal sum whose precise numerical value is substituted for the entire string of binary source bits.2. A data substitution system as claimed in claim 1 , in which the individual bits of a binary source data set are interpreted and/or directly calculated in a manner that produces an output decimal sum independently and exclusively respective of each bit's spatial values derived from their exact positions within the set.3. The invention claimed achieves a level of material data compression by converting the output decimal sum of the consecutively added bits of a binary source data set as produced in claim 1 , or claim 1 , into an interchangeable mathematical expression of equivalent numerical value specifically encoded claim 1 ...

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Номер записи: 82
16-05-2019 дата публикации

COMPUTATIONAL DEVICES USING THERMOMETER CODING AND SCALING NETWORKS ON UNARY ENCODED DATA

Номер: US20190149166A1
Автор: Bazargan Kiarash, Faraji Sayed Abdolrasoul, Mohajer Soheil, Wang Zhiheng
Принадлежит:

This disclosure describes techniques for performing computational operations on input unary bit streams using one or more scaling networks. In some examples, a device is configured to perform a digital computational operation, where the device includes a plurality of input wires and a plurality of output wires. Each input wire is configured to receive a respective input bit of an encoded input value, and each output wire is configured to output a respective output bit of an encoded output value. The device also includes scaling network circuitry configured to apply a function to the encoded input value by electrically routing at least one input wire of the plurality of input wires to at least two output wires of the plurality of output wires. The device can also include hybrid binary/unary computations. 1. A device configured to perform a digital computational operation , the device comprising:a plurality of input wires and a plurality of output wires, each input wire of the plurality of input wires configured to receive a respective input bit of an encoded input value, and each output wire of the plurality of output wires configured to output a respective output bit of an encoded output value, wherein the encoded input value includes a thermometer unary encoded input value or an edge encoded input value, and wherein the encoded output value includes a thermometer unary encoded output value or an edge encoded output value; andscaling network circuitry configured to apply a function to the encoded input value by electrically routing at least one input wire of the plurality of input wires to at least two output wires of the plurality of output wires.2. The device of claim 1 , further comprising voting circuitry configured to receive claim 1 , from the scaling network claim 1 , at least two input wires electrically routed by the scaling network for a single corresponding one of the output bits of the encoded output value claim 1 ,wherein the voting circuitry includes a ...

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Номер записи: 83
08-06-2017 дата публикации

REDUCING POWER NEEDED TO SEND SIGNALS OVER WIRES

Номер: US20170163282A1
Автор: Sadowski Greg
Принадлежит: Advanced Micro Devices, Inc.

Methods and apparatus are described. A method, implemented in a decoder, includes receiving two or more signals from an encoder over two or more respective wires. At least one of the two or more signals includes at least one code that was recoded by the encoder. The decoder receives a recoding table. The recoding table provides a mapping indicating the recoding for each code that was recoded by the encoder in the received two or more signals. The decoder decodes the two or more received signals using the received recoding table. 1. A method , implemented in a decoder , the method comprising:receiving two or more signals from an encoder over two or more respective wires, at least one of the two or more signals including at least one code that was recoded by the encoder;receiving a recoding table, the recoding table providing a mapping indicating the recoding for each code that was recoded by the encoder in the received two or more signals; anddecoding the two or more received signals using the received recoding table.2. The method of claim 1 , wherein at least one of the two or more signals includes at least one code that was recoded by the encoder based on an analysis of two or more previously received signals at the encoder over two or more clock cycles.3. A method claim 1 , implemented in a decoder claim 1 , the method comprising:receiving two or more signals from an encoder over two or more respective wires, at least one of the two or more signals including at least one code that was recoded by the encoder based on an analysis of two or more previously received signals at the encoder over two or more clock cycles;receiving an indication of the at least one code that was recoded by the encoder; anddecoding the two or more received signals based on the received indication. This application is a continuation of U.S. patent application Ser. No. 13/721,944, filed Dec. 20, 2012, which is incorporated by reference as if fully set forth.The disclosed embodiments are ...

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Номер записи: 84
04-09-2014 дата публикации

METHOD AND SYSTEM FOR DE-BINARIZATION

Номер: US20140247165A1
Автор: Chen Yi-Hau, Chou Han-Liang, Ju Chi-Cheng, LAI YEN-CHIEH, LEE Kun-Bin, Lin Ting-An
Принадлежит: MEDIATEK INC.

A method for generating a decoded value from a codeword which is binarized utilizing a concatenated unary/k-th order Exp-Golomb code includes: identifying a first portion of the codeword, a second portion of the codeword and a third portion of the codeword; generating an offset according to the second portion; decoding the third portion to generate an index value; and generating the decoded value by adding the offset and the index value. 1. A method for generating a decoded value from a codeword which is binarized utilizing a concatenated unary/k-th order Exp-Golomb code , the method comprising:identifying a first portion of the codeword, a second portion of the codeword and a third portion of the codeword;generating an offset according to the second portion only;decoding the third portion to generate an index value; andgenerating the decoded value by adding the offset and the index value.2. The method of claim 1 , wherein the third portion comprises a binary number claim 1 , and decoding the third portion comprises converting the binary number into the index value.3. The method of claim 1 , wherein the step of generating the offset comprises:deriving the number of successive bit ONES in the second portion; andusing the derived number as the input of a look-up table, wherein the offset is the output of the look-up table.4. The method of claim 3 , wherein the step of generating the offset comprises left shifting value 1 according to the number of successive bit ONES in the second portion and adding the left shifted resultant to a predetermined value.5. The method of claim 3 , wherein the step of generating the offset comprises left shifting value 1 according to the number of successive bit ONES in the second portion and the order of Exp-Golomb when the order is not zero; and adding the left shifted resultant to a predetermined value.6. The method of claim 4 , wherein the predetermined value is predetermined to indicate a value represented by the truncated unary ...

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Номер записи: 85
04-09-2014 дата публикации

ENCODER, DECODER AND METHOD

Номер: US20140247168A1
Автор: KALEVO Ossi Mikael
Принадлежит: GURULOGIC MICROSYSTEMS OY

There is provided an encoder and decoder for encoding and decoding input data (D1, D2 or D3) to generate corresponding encoded output data (D2 or D3, D5). The encoder includes a data processing arrangement, optionally for analyzing a range of values present in the input data (D1) to determine at least one pre- and/or post-pedestal value, optionally to translate the input data (D1) using the at least one pre- and/or post-pedestal value to generate translated data, and then to apply a form of ODelta coding to the data, optionally translated data, to generate processed data, and to combine the processed data and optionally the at least one pre- and/or post-pedestal value for generating the encoded output data (D2 or D3). The decoder includes a data processing arrangement for processing the encoded data (D2 or D3), optionally to extract therefrom at least one pre- and/or post-pedestal value. 11010. An encoder () for encoding input data (D1) to generate corresponding encoded output data (D2 or D3) , wherein the encoder () includes a data processing arrangement for analyzing values present in the input data (D1) , and for translating the input data (D1) using results of the analysis to generate translated data , and then to apply a form of ODelta coding to the translated data to generate processed data , and to combine the processed data with the results of the analysis for generating the encoded output data (D2 or D3).210. The encoder () as claimed in claim 1 , wherein the data processing arrangement is operable to analyze a range of values in the input data (D1) and to generate at least one pre- and/or post-pedestal value for use in generating the translated data claim 1 , and is operable to combine the processed data and the at least one pedestal value for generating the encoded output data (D2 or D3).31010. The encoder () as claimed in claim 1 , wherein the encoder () is operable to subdivide the input data (D1) into a plurality of sections of data which are ...

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Номер записи: 86
16-06-2016 дата публикации

LOW POWER DIGITAL SELF-GATED BINARY COUNTER

Номер: US20160173106A1
Автор: Agarwal Amol, Goyal Gaurav, Gupta Naman
Принадлежит:

An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output. 1. An n-bit counter circuit , comprising:a plurality of cascaded counter sub-modules including at least first and second cascaded counter sub-modules, the first counter sub-module being at least a lower-order counter sub-module relative to the second counter sub-module, the second counter sub-module being a higher-order counter sub-module relative to the first counter sub-module, as well as being a lower-order counter sub-module relative to subsequent cascaded counter sub-modules; and the control logic includes a clock-gating integrated cell (CGIC) that clocks at least the second counter sub-module dependent on a logical combination of outputs of at least the first counter sub-module, and provides a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules dependent on a logical combination of the outputs of at least the second counter sub-module; and', 'the control logic does not include any intervening memory device between the first counter sub-module and the CGIC for use in resolution of a logical combination of outputs., 'control logic coupled to the first counter sub-module, wherein2. The n-bit counter circuit of claim 1 , wherein at least the n-bit counter circuit is fabricated as part of an integrated circuit.3. The n ...

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Номер записи: 87
11-09-2014 дата публикации

DIVIDED CLOCK GENERATION DEVICE AND DIVIDED CLOCK GENERATION METHOD

Номер: US20140253188A1
Автор: CHOI Hun-Dae, SONG In-Dal
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals.

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Номер записи: 88
30-05-2019 дата публикации

INTERLEAVED SIGMA DELTA MODULATOR BASED SDR TRANSMITTER

Номер: US20190165820A1
Автор: Baringer Cynthia D., Hitko Donald A., KUAN Yen-Cheng, LI James Chingwei, Sharifi Hasan, XU ZHIWEI A.
Принадлежит:

A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions. 1. A transmitter comprising:a dynamic element matching (DEM) system having an output, wherein the DEM system is configured to receive bits of data and output a permutation of the bits of data at its output;at least two digital-to-analog converters (DACs) each having an input and output;a coupler, wherein the coupler comprises a crossbar switch grid to couple the input of at least one of the DACs of the at least two DACs to the output of the DEM system, and wherein the at least one of the DACs is configured to output an analog signal corresponding to the permutation of the bits of data.2. The transmitter of further comprising a summing circuit having inputs coupled to the outputs of the at least two DACs;wherein the bits of data comprises sets of bits of data; wherein the DEM system comprises more than one DEM encoder;wherein the number of DACs is at least equal to the number of DEM encoders;wherein the output of the DEM system comprises outputs of the DEM encoders such that each DEM encoder of the more than one DEM encoder has an output, and the more than one DEM encoder are configured to receive the sets of bits of data and output permutations of the sets of bits ...

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Номер записи: 89
23-06-2016 дата публикации

Systems and Methods for Decoder Scheduling With Overlap and/or Switch Limiting

Номер: US20160182083A1
Автор: Li Shu, Yang Shaohua
Принадлежит:

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for scheduling in a data decoder. 1. A system for decoding a data set , the system comprising:a data decoder circuit operable to apply a data decoding algorithm to a data input to yield a decoded output, wherein operation of the data decoder circuit is governed at least in part by a modified H-matrix; andwherein the modified H-matrix enforces a column processing order that eliminates dependencies between columns at the beginning of the column processing order and columns at the ending of the column processing order.2. The system of claim 1 , wherein a subsequent local iteration through the data decoder circuit begins before completion of a preceding local iteration through the data decoder circuit.3. The system of claim 2 , wherein the preceding local iteration is performing minimum calculations to yield minimums and minimum locations for a first set of elements while the succeeding local iteration is calculating check node to variable node messages based upon the minimums and minimum locations for a second set of locations.4. The system of claim 1 , wherein the modified H-matrix further enforces a processing order conforming to a Gray code pattern claim 1 , wherein the Gray code pattern is represented as the row dependencies in each of the columns.5. The system of claim 1 , wherein the system is implemented as part of a device selected from a group consisting of: a storage device claim 1 , and a communication device.6. The system of claim 1 , wherein the data decoder circuit implements a low density parity check decoding algorithm.7. The system of claim 1 , wherein the system is implemented as part of an integrated circuit.8. The system of claim 1 , wherein the modified H-matrix includes columns of circulants in an order that reduces switching between rows in the modified H-matrix.9. A system for decoding a data set claim 1 , the system ...

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Номер записи: 90
18-09-2014 дата публикации

METHODS AND APPARATUS FOR CONTEXT BASED LINE CODING

Номер: US20140266817A1
Автор: Whitby-Strevens Colin
Принадлежит:

Methods and apparatus intelligently switching between line coding schemes based on context. In one exemplary embodiment, an High Definition Multimedia Interface (HDMI) system is configured to transmit control and video data according to an 8B/10B line coding protocol, and data island data according to TERC4 (TMDS (Transition Minimized Differential Signaling) Error Reduction Coding 4-bit). Various elements of the disclosed HDMI devices are configured to determine when a context switch occurs, and thereafter seamlessly transition between the appropriate line code protocol. 1. A method for intelligently switching between line coding schemes based on context , comprising:receiving one or more symbols according to a first context, the first context characterized by a first line coding scheme;detecting when a context switch to a second context will occur based on the received one or more symbols, the second context characterized by a second line coding scheme; andwhen a context switch is detected, changing to the second context.2. The method of claim 1 , where the first context comprises at least one of: (i) control information claim 1 , (ii) preamble information claim 1 , (iii) guard band claim 1 , and (iv) video data.3. The method of claim 2 , where the first line coding scheme comprises an 8B10B encoding.4. The method of claim 1 , where the second context comprises at least data island data.5. The method of claim 4 , where the second line coding scheme comprises Transition Minimized Differential Signaling (TMDS) Error Reduction Coding 4-bit (TERC4).6. The method of claim 1 , where the detection of the context switch comprises detecting a preamble that occurs during a blanking period.7. The method of claim 6 , where the blanking period is determined at least in part by one or more media parameters.8. The method of claim 7 , where the one or more media parameters includes at least one or more of a fixed number of scan lines and a length of each scan line.9. The method of ...

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Номер записи: 91
18-09-2014 дата публикации

UNICODE CHARACTER CONVERSION

Номер: US20140266818A1
Автор: LAVIOLETTE Michel
Принадлежит:

Disclosed is a method to convert a Unicode character. The method includes intercepting a service call for a character conversion, determining if a character associated with the service call is a candidate for a first conversion service, if the character is a candidate for the first conversion service, converting the character using the first conversion service, if the character is not a candidate for the first conversion service, converting the character using a second conversion service, and returning the converted character. 1. A method to convert a character , the method comprising:intercepting a service call for a character conversion;determining if a character associated with the service call is a candidate for a first conversion service;if the character is a candidate for the first conversion service, converting the character using the first conversion service;if the character is not a candidate for the first conversion service, converting the character using a second conversion service; andreturning the converted character.2. The method of claim 1 , whereinthe service call is to an address for the first conversion service, andthe service call is redirected to an address for the second conversion service if the character is not a candidate for the first conversion service.3. The method of claim 1 , wherein the service call includes the character claim 1 , a character type associated with the character claim 1 , and a character type to convert the character to.4. The method of claim 1 , wherein determining if the character is a candidate for a first conversion service includes:determining a character length of the character, andif the character length equals zero, the character is not a candidate for a first conversion service.5. The method of claim 1 , wherein determining if the character is a candidate for a first conversion service includes:determining if the character is in a single byte character format;determining if a character conversion type is a ...

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Номер записи: 92
02-07-2015 дата публикации

METHOD AND APPARATUS FOR DECODING NON-BINARY PARITY CHECK CODE

Номер: US20150188568A1
Автор: KIM Kyung-Joong, MYUNG Seho, YANG Kyeong-Cheol
Принадлежит:

A method of decoding a non-binary Low Density Parity Check (LDPC) code is provided. The method includes a plurality of messages to perform hard decision for all messages except for one message, and combines the hard-decided values with the one message that is not hard-decided, to update a final output message. 1. A method of decoding a non-binary Low Density Parity Check (LDPC) code , the method comprising:receiving a plurality of messages and hard-deciding all messages except for one message; andcombining the hard-decided values with the one message that is not hard-decided, to update a final output message.2. The method of claim 1 , wherein the one message that is not hard-decided is determined to have a lowest reliability from a previously-defined reliability measurement vector.3. The method of claim 2 , wherein the reliability measurement vector has a different value for each codeword symbol and a size of the reliability measurement vector is equal to a number of non-binary symbols of a single codeword.4. The method of claim 2 , wherein claim 2 , when the codeword symbol are hard-decided claim 2 , values of the reliability measurement vector have a probability value that the codeword symbol is hard-decided for each of the non-binary symbols or a value corresponding thereto.5. The method of claim 2 , wherein claim 2 , when decoding fails claim 2 , the reliability measurement vector is updated according to a predetermined rule until a decoding counter reaches a predetermined maximum value claim 2 , and the hard decision is performed again.6. An apparatus for decoding a non-binary LDPC code claim 2 , the apparatus comprising:a hard decision unit configured to receive a plurality of messages and hard-decide all the messages except for one message; andan output unit configured to combine the hard-decided values with the one message that is not hard-decided and update a final output message.7. The apparatus of claim 6 , wherein the hard decision unit determines that ...

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Номер записи: 93
18-09-2014 дата публикации

FREQUENCY SCALING COUNTER

Номер: US20140270049A1
Автор: Gleason Joseph Daniel
Принадлежит: Hewlett-Packard Development Company, L.P.

A counter is provided, where, as the number of events that occur increases, the frequency in which the events are counted is scaled. 1. A method , comprising:initializing a counter value and an exponent value;repeatedly receiving an indication of an event;incrementing the counter value, at a frequency, upon receiving the repeated indications of the event until the counter value has reached a maximum value;upon receipt of the repeated indication of the event after the counter value has reached a maximum value, incrementing the exponent value and returning the counter value to zero; andscaling the frequency in which the counter value is incremented.2. The method of claim 1 , wherein scaling the frequency in which the counter is incremented includes:{'sup': 'EXP', 'where N is an integer and EXP is the exponent value, upon receiving the repeated indications of the event, incrementing the counter every N̂events until the counter value has reached the maximum value; and'}upon receipt of the repeated indication of the event after the counter value has reached the maximum value, incrementing the exponent value and returning the counter value to zero.3. The method of claim 2 , further comprising:outputting the exponent value and the counter value.4. The method of claim 1 , wherein the event is a clock cycle.5. The method of claim 1 , wherein the event is an external event.6. A counter claim 1 , comprising:a first counting portion, the first counting portion incremented upon a frequency of an event; anda second counting portion, the second counting portion incremented when the first counting portion reaches a maximum value, wherein when the second counting portion is incremented, the frequency in which the first counting portion is incremented is scaled.7. The counter of claim 6 , further comprising:an input clock signal, wherein the frequency of an event is based on the input clock signal.8. The counter of claim 6 , further comprising:an input external signal, wherein the ...

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Номер записи: 94
04-06-2020 дата публикации

HYBRID ARCHITECTURES FOR CHECK NODE PROCESSING OF EXTENDED MIN-SUM (EMS) DECODING OF NON-BINARY LDPC CODES

Номер: US20200177203A1
Автор: Boutillon Emmanuel, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

Embodiments of the invention provide a check node processing unit (-) configured to determine at least two check node messages in a decoder to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: 1. A check node processing unit configured to determine at least two check node messages in a decoder to decode a signal encoded using a NB-LDPC code , the check node processing unit comprising:a data link to one or more message presorting units configured to determine at least three permuted variable node messages by permuting at least three variable node messages generated by one or more variable node processing units each variable node message comprising components, a component comprising a symbol and a reliability metrics associated with said symbol;a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the at least three permuted variable node messages;a forward-backward sub-check node configured to determine permuted check node messages at least from one of said one or more intermediate messages;a switching unit configured to generate each check node message of a given index from the check node messages determined by the at least one syndrome sub-check node or from the permuted check node messages determined at the at least a forward-backward sub-check node depending on said given index.2. The check node processing unit of claim 1 , wherein the message presorting unit is configured to determine said permuted variable node messages by applying one or more permutations to the at least three variable node messages depending on the reliability metrics comprised in said at least three variable node messages claim 1 , each permutation being associated with components extracted from the variable node messages according to a permutation index and being applied to permute the variable node messages according to a ...

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Номер записи: 95
18-09-2014 дата публикации

Systems and Methods for Multi-Stage Encoding Of Concatenated Low Density Parity Check Codes

Номер: US20140281790A1
Автор: Chung-Li Wang, Shaohua Yang, Shu Li, Yu Kou, Zongwang Li
Принадлежит: Avago Technologies General IP Singapore Pte Ltd

Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for multi-stage encoding for concatenated low density parity check codes.

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Номер записи: 96
21-07-2016 дата публикации

METHOD AND APPARATUS FOR CONVERTING FROM FLOATING POINT TO INTEGER REPRESENTATION

Номер: US20160211862A1
Автор: HO Huong, Kafrouni Michel
Принадлежит:

Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format. 2. The apparatus of claim 1 , wherein the shift conditioning module is further configured to generate the shift control signal based on a scaling factor input added to the exponent.3. The apparatus of claim 1 , further comprising an overflow/underflow correction module claim 1 , wherein upon detection of an overflow condition or an underflow condition claim 1 , the overflow/underflow correction module is configured to receive the shift control signal and an output of the shift execution module and the overflow/undeflow correction module configured to provide the signed integer representation as a predetermined saturated value.4. The apparatus of claim 1 , wherein the exponent is expressed using E bits claim 1 , and wherein the shift conditioning module is further configured to generate the shift control signal based on a scaling factor input and an exponent bias value claim 1 , the exponent bias value equal to 2−1 claim 1 , the shift conditioning module comprising:an inverter configured to operate on a most significant bit of the exponent to provide a modified exponent value, the modified exponent value corresponding to ...

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Номер записи: 97
18-06-2020 дата публикации

PARALLEL-TO-SERIAL CONVERSION CIRCUIT

Номер: US20200195274A1
Автор: CHAE Joo-Hyung, Kim Suhwan
Принадлежит:

A parallel-to-serial conversion circuit may include first to fourth data lines; first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line, wherein two of the first to fourth drivers are simultaneously activated. 1. A parallel-to-serial conversion circuit comprising:first to fourth data lines;first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; andfirst to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line,wherein two of the first to fourth drivers are simultaneously activated.2. The parallel-to-serial conversion circuit of claim 1 , wherein the first parallel-to-serial converter parallel-to-serial converts data of the fourth data line and data of the first data line at a ratio of 2:1 claim 1 ,the second parallel-to-serial converter parallel-to-serial converts the data of the first data line and data of the second data line at a ratio of 2:1,the third parallel-to-serial converter parallel-to-serial converts the data of the second data line and data of the third data line at a ratio of 2:1, andthe fourth parallel-to-serial converter parallel-to-serial converts the data of the third data line and data of the fourth data line at a ratio of 2:1.3. The parallel-to-serial conversion circuit of claim 2 , wherein the fourth driver and the first driver are activated during a first period claim 2 ,the first driver and the second driver are activated during a second ...

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Номер записи: 98
28-07-2016 дата публикации

PAD ENCODING AND DECODING

Номер: US20160218736A1
Автор: Bauchot Frederic J., Legroux Marc Joel Herve
Принадлежит:

A system, method and computer program product for encoding an input string of binary characters representing alphanumeric characters. A system includes: a register for storing a multi-dimensional cellular shape definition including a starting empty cell; a character writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by traversing neighboring cells in the multi-dimensional shape until an empty cell is located; a loop facilitator for looping back to the character writing engine and the next cell determining engine until there are no more data characters or a next empty cell is not determined; and a serialization engine for serializing the multi-dimensional cells into a one dimensional binary string of characters representing an encoded string of alphanumeric characters. 1. An encoding system , comprising:a register for storing a multi-dimensional cellular shape definition including a starting empty cell;a character writing engine for writing a binary character to an empty cell beginning with the starting empty cell;a next cell determination engine for determining a next empty cell by traversing neighboring cells in the multi-dimensional shape until an empty cell is located;a loop facilitator for looping back to the character writing engine and the next cell determining engine until there are no more data characters or a next empty cell is not determined; anda serialization engine for serializing the cells into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.2. The system according to claim 1 , wherein traversing comprises moving from the current cell in a current direction to a new cell and wherein the new cell is the next cell if the new cell is an empty cell otherwise traversing again until an empty cell is located.3. The system according to claim 1 , further comprising changing a direction of ...

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Номер записи: 99
12-08-2021 дата публикации

CHECK NODE PROCESSING METHODS AND DEVICES WITH INSERTION SORT

Номер: US20210250047A1
Автор: Boutillon Emmanuel, HARB Hassan, MARCHAND Cédric
Принадлежит: UNIVERSITE DE BRETAGNE SUD

A sorting device for determining elementary check node components in an elementary check node processor () implemented in a non-binary error correcting code decoder by sorting auxiliary components. The auxiliary components are stored in a plurality of FIFO memories (-), each FIFO memory (-) being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory (-) comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory (-). The sorting device is configured to sort the auxiliary components by a plurality of multiplexers (-) arranged sequentially. Each multiplexers (-) is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the following steps: 1. A sorting device for determining elementary check node components in an elementary check node processor implemented in a non-binary error correcting code decoder by sorting auxiliary components , said auxiliary components being stored in a plurality of FIFO memories , each FIFO memory being assigned a FIFO number index , each auxiliary component stored in a given FIFO memory comprising an auxiliary symbol , an auxiliary reliability metrics representing the reliability of said auxiliary symbol , and the FIFO number index assigned to said given FIFO memory , the sorting device comprising a plurality of multiplexers arranged sequentially , the multiplexers being configured to initialize a set of candidate elementary check node components , each candidate elementary check node component being determined from one of the FIFO memories and corresponding to the auxiliary component which comprises the most reliable auxiliary symbol among the auxiliary components stored in said FIFO memory , said candidate elementary check ...

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Номер записи: 100