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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 1147. Отображено 100.
05-01-2012 дата публикации

Power Supply Circuit

Номер: US20120001740A1
Автор: Akiyoshi Kato, Kazuhiko Taira, Masahiko Mawatari, Takashi Doi
Принадлежит: Individual

According to one embodiment, a power supply circuit includes a source, a sink, and a connection unit. A first control circuit of the source is configured to send an inquiry about the presence/absence of a power supply function to a second control circuit of the sink using a first line, to turn on a changeover switch and turn off a power reception notification switch when a response indicating the presence of the power supply function is received, and to send a power supply request to the second control circuit using the first line, and the second control circuit is configured to turn on a power supply switch and turn off a power source direction notification switch when the power supply request is received from the first control circuit, and to continue power supply during a first level period of a potential of the second line.

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Номер записи: 1
02-02-2012 дата публикации

Assessment of on-chip circuit based on eye-pattern asymmetry

Номер: US20120025889A1
Автор: Jianghui Su
Принадлежит: Oracle International Corp

During an asymmetry testing mode of an integrated circuit, the asymmetry of an on-chip I/O circuit is tested. In particular, a transmitter circuit in the integrated circuit transmits electrical signals, which are associated with a predefined data pattern, to a receiver circuit in the integrated circuit via a communication channel (such as a differential pair of signal lines). Then the integrated circuit generates an eye pattern using the received electrical signals, and determines an asymmetry of the eye pattern about a common reference level of the received electrical signals. Furthermore, the integrated circuit performs remedial action based on the determined asymmetry. For example, the integrated circuit may compare the determined asymmetry with a predefined asymmetry criterion and, if the asymmetry exceeds the predefined asymmetry criterion, may output a result of the comparison that indicates a failure of the asymmetry test.

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Номер записи: 2
19-07-2012 дата публикации

System and Method for Termination Powered Differential Interface Periphery

Номер: US20120182480A1
Автор: Hongwu Chi
Принадлежит: Individual

An apparatus and method for supplying power to the peripheral circuits of a transmitter circuit, especially an HDMI transmitter circuit, is disclosed. In an HDMI transmitter, the termination resistors of the output driver are part of the receiver. DC power for the driver is supplied through these termination resistors. In prior art implementations, power supplied by the receiver circuit is wasted in the DC set-up circuit of the differential line driver. In various embodiments, this wasted power may be recovered from the remote termination to power selected peripheral circuits of the transmitter. The use of this wasted power may reduce the total system power consumption.

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Номер записи: 3
26-07-2012 дата публикации

Receiving circuit, semiconductor device including the same, and information processing system

Номер: US20120188013A1
Автор: Daisuke Hamano, Tatsunori Usugi, Yuji USHIO
Принадлежит: HITACHI LTD

In a receiving circuit, and in a semiconductor device and an information processing system including the receiving circuit, the receiving circuit is configured to amplify a high-speed signal by a greater gain than a low-speed signal with a low electric power consumption. The receiving circuit includes a first amplifier and a second amplifier having a cutoff frequency lower than a cutoff frequency of the first amplifier. A received signal is inputted to the first amplifier and the second amplifier, an output from the second amplifier is subtracted from an output from the first amplifier, and a result is outputted from the receiving circuit.

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Номер записи: 4
02-08-2012 дата публикации

Differential output buffer

Номер: US20120194225A1
Автор: Junichiro Shirai, Katsuki Matsudera
Принадлежит: Toshiba Corp

According to one embodiment, a main driver is configured to shift the level of a differential signal. A bypass circuit is configured to bypass current flowing through the main driver in such a manner as to contain the change amount of current running through the main driver flowing from a high power supply potential to a low power supply potential within a fixed range upon transition between an operating state and a standby state of the main driver.

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Номер записи: 5
07-03-2013 дата публикации

Method and circuit for precisely controlling amplitude of current-mode logic output driver for high-speed serial interface

Номер: US20130057319A1
Автор: Arvind Bomdica, Xin Liu
Принадлежит: Advanced Micro Devices Inc

A method is provided for selecting a reference voltage value at a data transmission device that comprises a bias circuit and an output driver circuit. The method also includes providing a first electrical current at the bias circuit and a second electrical current at the output driver circuit. The second electrical current amplitude is approximately a multiple of the first electrical current amplitude, and the first electrical current is based on the reference voltage value. The method further includes driving a differential output the second electrical current. A circuit is also provided that includes a data output driver portion and a bias circuit portion. The bias circuit portion is a replica of the data output driver portion. The circuit is configured to drive a data signal. A computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus is also provided.

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Номер записи: 6
25-04-2013 дата публикации

METHOD AND ASSEMBLY FOR TRANSMITTING SENSOR SIGNALS

Номер: US20130101065A1
Автор: Heim Jens
Принадлежит: SCHAEFFLER TECHNOLOGIES AG & CO. KG

The invention relates to a method for transmitting sensor signals, comprising the following steps: a first sensor (), in particular a rotational speed sensor, supplies an alternating signal, which is present in the form of a sequence of sensor pulses () and pulse pauses () of predetermined duration, wherein in the pulse pauses () additional data () is transmitted as a bit sequence and wherein the bit sequence contains at least one free bit (); a binary information sequence () comprising data from at least one further sensor () is generated, which has a transmission length of a plurality of bits; and the data of the first sensor () and of the at least one further sensor () is transmitted through a common data line () in that a processing unit () distributes the information sequence () to a plurality of chronologically sequential bit sequences and the at least one free bit () of the additional data () is assigned at least one bit of the information sequence (). The information sequence () is thus reliably transmitted, even when it contains more bits than there are free bits available in the additional data (). 1. A method for transmitting sensor signals , comprising:supplying an alternating signal which exists as a sequence of sensor pulses and pulse pauses of a pre-defined duration from a first sensor, wherein in the pulse pauses additional data are transmitted as a bit sequence and wherein the bit sequence contains at least one free bit,generating a binary information sequence comprising data from at least one further sensor, which has a transmission length of a plurality of bits, andtransmitting the data of the first sensor and of the at least one further sensor through a common data line, and distributing the information sequence to a plurality of chronologically sequential bit sequences and overlaying the at least one free bit of the additional data with at least one bit of the information sequence using a processing unit.2. A method according to claim 1 , ...

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Номер записи: 7
09-05-2013 дата публикации

METHODS AND APPARATUS FOR SIGNALING ON A DIFFERENTIAL LINK

Номер: US20130114747A1
Автор: Schoenborn Theodore
Принадлежит:

Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link. 1. An apparatus comprising: enter a reduced power state;', 'identify a differential signal transmitted over a differential, point-to-point serial data link;', 'interpret the signal as a wake signal; and', 'transition from the reduced power state to a normal power state based at least in part on the wake signal., 'a receiver to2. The apparatus of claim 1 , wherein the receiver is further configured to identify an idle condition on the data link in excess of a predetermined length of time and the receiver is to enter the reduced power state based on the identification of the idle condition.3. The apparatus of claim 2 , wherein the idle condition is to be interpreted as an in-band signal to enter the reduced power state.4. The apparatus of claim 1 , wherein the receiver does not receive data when in the reduced power state.5. The apparatus of claim 1 , wherein the reduced power state is a non-zero power state.6. The apparatus of claim 1 , wherein the signal comprises an in-band signal.7. The apparatus of claim 6 , wherein the signal comprises a direct current (DC) signal.8. The apparatus of claim 7 , wherein the signal comprises a predetermined differential voltage condition for at least a predetermined time period.9. The apparatus of claim 6 , wherein the signal comprises an alternating current (AC) switching signal.10. The apparatus of claim 9 , wherein the signal comprises dummy data.11. The apparatus of claim 1 , wherein the receiver comprises a plurality of sections and the signal comprises information that identifies a particular one of the plurality of sections to awake.12. An apparatus comprising: transmit an in-band power management signal to a receiver over a differential, point-to-point serial data link, wherein the signal comprises a wake signal to prompt the receiver to transition from a reduced ...

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Номер записи: 8
22-08-2013 дата публикации

THREE PHASE AND POLARITY ENCODED SERIAL INTERFACE

Номер: US20130215991A1
Автор: Wiley George Alan
Принадлежит: QUALCOMM INCORPORATED

A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval. 1. A method for encoding data , comprising: [ open-circuiting a first conductor, and', 'providing a voltage differential between a second conductor and a third conductor; and, 'during a first of two sequential time intervals,'}, open-circuiting the second conductor and providing the voltage differential between the first conductor and the third conductor when data to be encoded at a transition between the two sequential time intervals has a first value, and', 'open-circuiting the third conductor and providing the voltage differential between the first conductor and the second conductor when the data to be encoded at the transition between the two sequential time intervals has a second value., 'during a second of the two sequential time intervals,'}], 'transmitting a three-phase signal in each of a plurality of sequential time intervals, wherein transmitting the three-phase signal includes2. The method of claim 1 , wherein the second conductor is open-circuited when a first bit of the data to be ...

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Номер записи: 9
29-08-2013 дата публикации

Data tranmission driver, system and method

Номер: US20130223559A1
Автор: Liu Yonghua
Принадлежит:

A system and method are provided for transmission of data bits across a data bus. To reduce power usage, noise, or some combination of the two, the data bus utilizes differential transmission using a three level signal in which a reference signal signifies no difference between input bits. Before the signals are transmitted an analysis is made to choose which one of a set of predetermined polarity reversal combinations is advantageous to encode the data bits. The data bits are so encoded and a formatting value F associated with the chosen polarity reversal is differentially transmitted with the encoded bits over the data bus. The three level differential signal is received at the far end of the bus, the encoded bits are recovered and decoded with use of F. The system and method achieves up to N bits transmitted per N data lines. 1. A driver for differentially transmitting data over first and second data lines , the driver comprising:driver cells for receiving a first signal comprising a digital voltage, a first input signal, and a second input signal, the first input signal and the second input signal comprising data, the driver cells comprising:a first driver cell for receiving over a first input of the first driver cell the first signal and for receiving over a second input of the first driver cell the first input signal, and for generating over an output of the first driver cell a first 3-level transmission signal from a difference between the first signal and the first input signal; and,a second driver cell coupled to the first driver cell for receiving over a first input of the second driver cell the first input signal and for receiving over a second input of the second driver cell the second input signal, and for generating over an output of the second driver cell a second 3-level transmission signal from a difference between the first input signal and the second input signal.2. A driver according to wherein each of the first driver cell and the second driver ...

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Номер записи: 10
10-10-2013 дата публикации

Transmission system

Номер: US20130266055A1
Автор: Hirotaka Tamura, Tadahisa Matsumoto
Принадлежит: Fujitsu Ltd

A transmission system includes: a transmitter configured to transmit a first signal; a receiver configured to receiver a second signal from the transmitter; and a bias circuit configured to regulate a direct current bias level of an input terminal of the receiver, wherein the transmitter includes a first amplitude converter configured to convert the first signal to the second signal having a smaller amplitude than an amplitude of the first signal, wherein the receiver includes a second amplitude converter configured to convert the second signal to a third signal having a larger amplitude than the amplitude of the second signal, and wherein the first amplitude converter includes a first capacitance that restricts an amount of charge to be supplied to the receiver.

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Номер записи: 11
01-01-2015 дата публикации

TRANSITION TIME MEASUREMENT OF PAM4 TRANSMITTERS

Номер: US20150003505A1
Автор: Lusted Kent C., Ran Adee O.
Принадлежит:

Methods, apparatus and systems for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter. During a test procedure, a PAM4 transmitter is configured to repetitively transmit a PAM4 symbol test pattern, which is captured as a signal waveform. The test pattern includes at least one rising signal sequence having a PAM4 symbol pattern of at least three −1 PAM4 symbols followed by at least three +1 PAM4 symbols and at least one falling signal sequence having a PAM4 symbol pattern of at least three +1 PAM4 symbols followed by at least three −1 PAM4 symbols. A voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level is measured for at least one rising signal sequence and falling signal sequence to derive 20% and 80% VMA levels. A rise transition time is then determined by measuring the time interval between when a rising signal crosses the 20% and 80% VMA levels, and a fall transition time is determined by measuring the time interval between when a falling signal crosses the 80% and 20% VMA levels. 1. A method for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter , comprising:transmitting a test pattern with the PAM4 transmitter, the test pattern having at least one rising signal sequence having a PAM4 symbol pattern of at least three −1 PAM4 symbols followed by at least three +1 PAM4 symbols and at least one falling signal sequence having a PAM4 symbol pattern of at least three +1 PAM4 symbols followed by at least three −1 PAM4 symbols;capturing a waveform of the test pattern, the captured waveform at least including portions of the test pattern proximate to at least one rising sequence and at least one falling signal sequence;determining, using the captured waveform, a voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 symbol to determine a 0% and 100% VMA level;deriving a 20% VMA level and an 80% VMA level as a function of the VMA 0% and ...

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Номер записи: 12
01-01-2015 дата публикации

DIFFERENTIAL SIGNAL TRANSMISSION CABLE AND CABLE WITH CONNECTOR

Номер: US20150003540A1
Автор: OIKAWA Minoru, WATANABE Haruyuki
Принадлежит: HITACHI METALS, LTD.

A differential signal transmission cable includes: two signal conductors; an insulator for covering these signal conductors; and a shield tape wound around the insulator in longitudinal wrapping. In the differential signal transmission cable, both ends of the shield tape in a direction of the winding around the insulator have a first overlapping region and a second overlapping region which overlap each other, and the first overlapping region of the shield tape is covered with the second overlapping region. In a tangent line of two tangent lines of a first signal conductor which is orthogonal to a line passing through centers of the signal conductors, when the tangent line positioned at radially outside of the first signal conductor is set to be a first tangent line, an end of the first overlapping region is positioned at outside of the first tangent line. 1. A differential signal transmission cable comprising:two signal conductors;an insulator for covering the signal conductors; anda shield tape wound around the insulator in longitudinal wrapping,wherein the shield tape comprises a first overlapping region and a second overlapping region which overlap each other on both ends of the shield tape in a direction of the winding around the insulator, the first overlapping region is covered with the second overlapping region, and,in a tangent line of two tangent lines of a first signal conductor which is orthogonal to a line passing through centers of the two signal conductors, when the tangent line positioned at radially outside of the first signal conductor is set to be a first tangent line, an end of the first overlapping region is positioned at outside of the first tangent line.2. The differential signal transmission cable according to claim 1 ,wherein, in a tangent line of two tangent lines of a second signal conductor which is orthogonal to the line passing through the centers of the two signal conductors, when the tangent line positioned at radially outside of the ...

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Номер записи: 13
07-01-2016 дата публикации

DRIVING DATA OF MULTIPLE PROTOCOLS THROUGH A SINGLE SET OF PINS

Номер: US20160006584A1
Автор: Agrawal Vinayak, Chekka Nagaraj, Gondi Srikanth, Sharma Namrta
Принадлежит:

Embodiments of the invention are generally directed driving data of multiple protocols through a single set of pins. An embodiment of an apparatus includes a transmitter connected to two pads on an IC the transmitter including a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, each branch of the differential driver including a protection device connected to one of the pads; and a common mode driver to transmit a common mode signal, the common mode driver having a first branch and a second branch, each of the branches of the common mode driver including a protection device connected to one of the pads. The first and second switch devices are not turned on simultaneously, based on data to be transmitted, one of the switch devices being turned on and the other being turned off. The third and fourth switch devices are both turned on when the common mode signal is one of a logic HIGH or logic LOW and both turned off when the common mode signal is the other of a logic HIGH or logic LOW. 127-. (canceled)28. An apparatus comprising: a differential driver to transmit a differential signal, wherein the differential driver has a first branch and a second branch, wherein each branch of the differential driver includes a protection device connected to one of the pads, the first branch of the differential driver having a first protection device and the second branch of the differential driver having a second protection device, each of the first and second protection devices having at least two terminals; and', 'a common mode driver to transmit a common mode signal, wherein the common mode driver has a first branch and a second branch, each of the first and second branches of the common mode driver including a protection device connected to one of the pads, the first branch of the common mode driver including a third protection device and the second branch of the common mode driver including a fourth ...

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Номер записи: 14
07-01-2016 дата публикации

METHODS AND APPARATUS TO REDUCE SIGNALING POWER

Номер: US20160006587A1
Автор: Hollis Timothy Mowry
Принадлежит:

System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state. 1. A method performed at a receiving device , comprising:decoding a multi-level encoding indicator received from a communications link;selectively inverting, using an inverting circuit, a primary bit of data symbols data symbols received from the communications link when the multi-level encoding indicator has a first value;selectively inverting, using the inverting circuit, a secondary bit of the data symbols when the multi-level encoding indicator has a second value, andselectively inverting, using the inverting circuit, the primary bit of the data symbols and the secondary bit of the data symbols when the multi-level encoding indicator has a third value; andswapping the primary bit and the secondary of the data symbols using a swapping circuit based on information in the multi-level encoding indicator,wherein more power is required to transmit the primary bit or the secondary bit in a first logic state than in a second logic state.2. The method of claim 1 , wherein the inverting circuit is disabled when the multi-level encoding indicator has a fourth value.3. The method of claim 1 , wherein decoding the multi-level encoding indicator comprises:using a decoding circuit to generate a plurality of control signals from the multi-level encoding ...

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Номер записи: 15
02-01-2020 дата публикации

PULSE AMPLITUDE MODULATION-3 TRANSCEIVER AND OPERATION METHOD THEREOF

Номер: US20200007362A1
Автор: KIM Chulwoo, Park Hyunsu, SIM Jin Cheol
Принадлежит: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

According to an embodiment of the inventive concept, a device for PAM-3 signaling includes an encoder selecting one of first to ninth transitions in first and second unit intervals that are successive and mapping data of three bits by using a remaining eight transitions other than the one selected among the first to ninth transitions, and an output driver receiving an output signal of the encoder via an input and generating a multi-level signal having an output voltage of first to third levels. The data of three bits is transmitted to a receiver terminal through the multi-level signal having the output voltage of the first to third levels during the first and second unit intervals that are successive. The device for PAM-3 signaling according to an embodiment of the inventive concept may transmit three bits during two unit intervals and may allow a receiver terminal to detect a windowing phenomenon. 13. A Pulse Amplitude Modulation (PAM-3) signaling device , the device comprising:an encoder configured to select one of first to ninth transitions in first and second unit intervals that are successive and configured to map data of three bits by using a remaining eight transitions other than the one selected among the first to ninth transitions; andan output driver configured to receive an output signal of the encoder via an input and configured to generate a multi-level signal having an output voltage of first to third levels,wherein the data of three bits is transmitted to a receiver terminal through the multi-level signal having the output voltage of the first to third levels during the first and second unit intervals that are successive.2. The device of claim 1 , wherein the one selected among the first to ninth transitions is used to detect a windowing phenomenon at the receiver terminal receiving the multi-level signal.3. The device of claim 2 , wherein the encoder selects the one of the first to ninth transitions claim 2 , based on at least one of circuit ...

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Номер записи: 16
12-01-2017 дата публикации

CIRCUITS FOR EFFICIENT DETECTION OF VECTOR SIGNALING CODES FOR CHIP-TO-CHIP COMMUNICATION

Номер: US20170012804A1
Автор: Hunt Peter, Ulrich Roger
Принадлежит:

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer. 1. An apparatus comprising:a termination network configured to receive symbols of a balanced codeword via a multi-wire bus, the termination network comprising a plurality of termination impedances, each termination impedance coupled to a respective wire of the multi-wire bus and configured to receive a corresponding symbol of the balanced codeword, the termination network further comprising a common mode biasing source coupled to the plurality of termination impedances, the common mode biasing source configured to form a set of biased symbols by biasing the received symbols of the balanced codeword;a first pair of transistors arranged in a differential amplifier configuration, each transistor in the first pair configured to receive corresponding biased symbols of a first pair of biased symbols, the first pair of transistors configured to generate a first difference signal;a second pair of transistors arranged in a differential amplifier configuration, each transistor in the second pair configured to receive corresponding biased symbols of a second pair ...

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Номер записи: 17
15-01-2015 дата публикации

MULTILEVEL SIGNAL TRANSMISSION SYSTEM CAPABLE OF ACCURATELY DETERMINING VOLTAGE LEVELS OF TRANSMITTED MULTILEVEL DATA SIGNAL

Номер: US20150016562A1
Автор: SHIBATA Osamu
Принадлежит:

A multilevel signal transmitting apparatus transmits a multilevel data signal with M voltage levels, and a multilevel clock signal with (M−2) voltage levels, to a multilevel signal receiving apparatus, where M is an even number equal to or more than four. The voltage levels of the multilevel data signal include M/2 first voltage levels larger than a reference voltage level, and M/2 second voltage levels smaller than the reference voltage level. Between each pair of adjacent voltage levels among the first voltage levels, one voltage level of the multilevel clock signal is set. Between each pair of adjacent voltage levels among the second voltage levels, one voltage level of the multilevel clock signal is set. An average of the voltage levels of the multilevel clock signal has a value between a minimum of the first voltage levels, and a maximum of the second voltage levels. 1. A multilevel signal transmitting apparatus comprising: a first driver circuit configured to generate a multilevel data signal with a number M of voltage levels , and a second driver circuit configured to generate a multilevel clock signal with a number (M−2) of voltage levels , where M is an even number equal to or more than four ,wherein the number M of voltage levels of the multilevel data signal include a number M/2 of first voltage levels larger than a predetermined reference voltage level, and a number M/2 of second voltage levels smaller than the reference voltage level,wherein between each pair of adjacent voltage levels selected among the number M/2 of first voltage levels of the multilevel data signal, one of the number (M−2) of voltage levels of the multilevel clock signal is set,wherein between each pair of adjacent voltage levels selected among the number M/2 of second voltage levels of the multilevel data signal, one of the number (M−2) of voltage levels of the multilevel clock signal is set, andwherein an average of the voltage levels of the multilevel clock signal for a ...

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Номер записи: 18
14-01-2021 дата публикации

TRANSCEIVER DEVICE FOR A BUS SYSTEM AND OPERATING METHOD THEREFOR

Номер: US20210014083A1
Автор: Mutter Arthur, Walker Steffen
Принадлежит:

A transceiver device for a bus system. The transceiver device includes first and second bus terminals for connection to first and second signal line of the bus system, and a transmitting unit for outputting a bus transmission signal to the first and second bus terminals. The transceiver device includes an input connection for receiving a transmission input signal useable for controlling an operating state of the transmitting unit, and a detection device, which to detect the presence of a first predefinable condition and, if the first predefinable condition is present, to interconnect the first and second bus terminals via a predefinable electrical resistance for a predefinable first period of time. 111-. (canceled)12. A transceiver device for a bus system , comprising:a first bus terminal for connection to a first signal line of the bus system;a second bus terminal for connection to a second signal line of the bus system;a transmitting unit configured to output a bus transmission signal to the first bus terminal and the second bus terminal;an input terminal for receiving a transmission input signal usable for controlling an operating state of the transmitting unit; anda detection device configured to detect a presence of a first predefinable condition and, if the first predefinable condition is present, to interconnect the first bus terminal and the second bus terminals via a predefinable electrical resistance for a predefinable first period of time, the predefinable first condition including at least one of the following elements: a) a rising edge of the transmission input signal and/or of a signal derived from the transmission input signal, b) a state transition of the transmitting unit from an operating state in which the first bus terminal and the second bus terminal are driven, into an operating state in which the first bus terminal and the second bus terminal are not driven.13. The transceiver device as recited in claim 12 , wherein the detection device is ...

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Номер записи: 19
14-01-2021 дата публикации

METHOD AND APPARATUS FOR STORING DATA OF TRANSMISSION SIGNAL, AND COMPUTER READABLE STORAGE MEDIUM

Номер: US20210014086A1
Автор: WANG MINGLIANG
Принадлежит:

The present application discloses a method for storing data of a transmission signal, which includes: upon the reception of the transmission signal, analyzing a clock signal corresponding to the transmission signal to obtain a signal frequency of the clock signal; according to the signal frequency, acquiring zero-volt time points of a clock signal after signal superposition with the transmission signal; acquiring a preset time length, and according to the zero-volt time points and the preset time length, generating data storage time periods with each of the zero-volt time points as a central time point; and storing data of the transmission signal within each of the data storage time periods. The present application further provides an apparatus for storing data of a transmission signal and a computer readable storage medium. 1. A method for storing data of a transmission signal , comprising:upon the reception of the transmission signal, analyzing a clock signal corresponding to the transmission signal to obtain a signal frequency of the clock signal;according to the signal frequency, acquiring zero-volt time points of a clock signal after signal superposition with the transmission signal;acquiring a preset time length, and according to the zero-volt time points and the preset time length, generating data storage time periods with each of the zero-volt time points as a central time point; andstoring the data of the transmission signal within each of the data storage time periods.2. The method for storing the data of the transmission signal according to claim 1 , wherein the step of according to the signal frequency claim 1 , acquiring zero-volt time points of a clock signal after signal superposition with the transmission signal comprises:calculating time intervals between adjacent two zero-volt time points according to the signal frequency; andacquiring the zero-volt time points according to the time intervals.3. The method for storing the data of the transmission ...

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Номер записи: 20
09-01-2020 дата публикации

EHF Receiver Architecture with Dynamically Adjustable Discrimination Threshold

Номер: US20200014567A1
Автор: Kyles Ian A., Seitz Norbert
Принадлежит:

An EHF receiver that determines an initial slicing voltage level and dynamically adjusts the slicing voltage level and/or amplifier gain levels to account for characteristics of the received EHF electromagnetic data signal. The architecture includes an amplifier, detector, adaptive signal slicer, and controller. The detector includes a main detector and replica detector that convert the received EHF electromagnetic data signal into a baseband signal and a reference signal. The controller uses the baseband signal and reference signal to determine an initial slicing voltage level, and dynamically adjust the slicing voltage level and the gain settings of the amplifier to compensate for changing signal conditions. 1. A receiver device comprising:a detector circuit configured to receive an EHF electromagnetic signal and generate a baseband signal and an initial reference signal; and [ sample the initial reference signal to determine an initial reference signal setting value,', 'during a first time period, determine a difference between the initial reference signal setting value and a reference signal setting value, and', 'during a second time period, adjust the initial reference signal setting value when the determined difference is more than a reference signal threshold value;, 'a reference signal feedback loop configured to, sample the baseband signal,', 'compute an average baseband signal using a plurality of samples of the baseband signal to determine an average baseband value,', 'determine a difference between the average baseband value and the initial reference signal setting value, and', 'compute an initial discrimination threshold voltage level value using the determined difference; and, 'a baseband signal feedback loop configured to, 'an amplifier configured to apply the initial discrimination threshold voltage level value to the baseband signal., 'a voltage slicer circuit comprising2. A method comprising:generating a baseband signal and an initial reference ...

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Номер записи: 21
21-01-2016 дата публикации

SIGNAL TRANSMISSION SYSTEM

Номер: US20160020924A1
Автор: CHAIVIPAS Win
Принадлежит:

A signal transmission system includes a transmitter configured to encode a transmission signal to generate 2N (N: integer larger than or equal to two) binary signals among which a number of 0s and a number of 1s are equal to each other, and to transmit the 2N binary signals, 2N signal lines configured to transmit the 2N binary signals, respectively, and a receiver configured to detect a bit pattern among a plurality of possible bit patterns of the 2N binary signals in response to a plurality of differential components between 2N received signals received through the 2N signal lines, and to decode the detected bit pattern.

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Номер записи: 22
19-01-2017 дата публикации

INTERFACE CIRCUIT FOR HIGH SPEED COMMUNICATION AND SYSTEM INCLUDING THE SAME

Номер: US20170019277A1
Автор: SHIM Jong Joo, SONG Keun Soo
Принадлежит:

A system may include an interface circuit coupled to a wire bus. The interface circuit may receive a multi-level symbol according to a status of the wire bus. The interface circuit may include a clock recovery circuit configured to generate a recovered clock based on the multi-level symbol. The interface circuit may latch the multi-level symbol based on one of an external clock and the recovered clock according to an operation speed of the system. 1. An interface circuit comprising:a receiver configured to receive a multi-level symbol according to a status of a wire bus;a clock recovery circuit configured to generate a recovered clock based on the multi-level symbol, wherein whether or not the clock recovery circuit operates is determined based on a clock selection signal;a clock selection circuit configured to generate an internal clock from one of an external clock and the recovered clock according to the clock selection signal; anda latch and decoding circuit configured to latch the multi-level symbol based on the internal clock.2. The interface circuit of claim 1 , wherein the wire bus comprises first to third wires claim 1 , and the receiver comprises:a first reception buffer configured to output a first phase of the multi-level symbol by differentially amplifying statuses of the first and second wires;a second reception buffer configured to output a second phase of the multi-level symbol by differentially amplifying statuses of the second and third wires; anda third reception buffer configured to output a third phase of the multi-level symbol by differentially amplifying statuses of the third and first wires.3. The interface circuit of claim 1 , wherein the clock recovery circuit changes a level of the internal clock by detecting a phase transition of the multi-level symbol.4. (canceled)5. The interface circuit of claim 1 , wherein the recovered clock and the external clock have the same or substantially the same frequency as each other.6. The interface ...

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Номер записи: 23
21-01-2021 дата публикации

METHOD AND APPARATUS FOR A ONE BIT PER SYMBOL TIMING RECOVERY PHASE DETECTOR

Номер: US20210021401A1
Автор: Ivry Raanan
Принадлежит:

Embodiments are disclosed for timing recovery used in conjunction with a phase detector embedded in a receiver of a communication system. An example method includes receiving, via a receiver of a communication system, an input signal. The input signal encodes a plurality of bits in a number of amplitude levels. The method further includes using an analog to digital converter to generate a sampled signal based on the input signal. The method further includes using a first interpolation filter to filter the sampled signal. The method further includes using a second interpolation filter to filter the sampled signal. The method further includes using a first non-linear device to process an output of the first interpolation filter. The method further includes using a second non-linear device to process an output of the second interpolation filter. The method further includes performing a mathematical operation on an output of the first non-linear device with an output of the second non-linear device to generate phase information. 1. A method for timing recovery used in conjunction with a phase detector embedded in a receiver of a communication system , comprising:receiving, via a receiver of a communication system, an input signal, wherein the input signal encodes a plurality of bits in a number of amplitude levels;using an analog to digital converter to generate a sampled signal based on the input signal, wherein the analog to digital converter is configured to receive the input signal and a waveform from a numerical control oscillator;providing the sampled signal to at least a first interpolation filter and a second interpolation filter of a set of interpolation filters to restore the input signal in one or more sampling points to generate a restored signal, wherein a first configuration of the first interpolation filter is different from a second configuration of the second interpolation filter;determining phase information of the input signal by using a phase ...

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Номер записи: 24
26-01-2017 дата публикации

TRANSMISSION UNIT, RECEPTION UNIT, AND COMMUNICATION SYSTEM

Номер: US20170026204A1
Автор: Hayashi Hiroaki, MATSUMOTO Hideyuki, Sugioka Tatsuya, Takahashi Hiroo
Принадлежит:

A transmitter includes: a transmission control circuit that determines whether or not to perform an emphasis on a data signal, based on a transition pattern of the data signal; and a transmission driver that selectively performs the emphasis based on a result of the determination by the transmission control circuit, to generate at least one transmission signal. 1. A receiver comprising:a first reception circuit configured to receive at least one transmission signal and output a first output signal;an equalizer configured to perform an equalization on the at least one transmission signal;a second reception circuit configured to receive at least one equalized transmission signal from the equalizer and output a second output signal; anda selection control circuit configured to select between the first output signal and the second output signal based on a transition pattern of the at least one transmission signal.2. The receiver according to claim 1 , wherein the selection control circuit determines a sequence of voltage states in the at least one transmission signal claim 1 , compares two time-adjacent voltage states of the sequence of voltage states claim 1 , and selects between the first output signal and the second output signal based on a result of the comparison.3. The receiver according to claim 1 , wherein the selection control circuit includes a look-up table indicating a relationship a current symbol and the at least one equalized transmission signal claim 1 , and selects between the first output signal and the second output signal based on the look-up table.4. The receiver according to claim 3 , wherein the look-up table is programmable.5. The receiver according to claim 1 , wherein the equalizer is configured to perform equalization to increase a high-frequency component of the at least one transmission signal.6. The receiver according to claim 1 , wherein the at least one transmission signal is three transmission signals claim 1 , andrespective ones of the ...

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Номер записи: 25
10-02-2022 дата публикации

SYSTEM AND METHOD FOR DYNAMIC ELEMENT MATCHING FOR DELTA SIGMA CONVERTERS

Номер: US20220045693A1
Автор: BANDYOPADHYAY Abhishek, BIRDSONG Preston S., SPIRER Adam R.
Принадлежит: ANALOG DEVICES, INC.

Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided a for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other I-DACs. Techniques are disclosed for decreasing mismatch among multiple I-DACs while improving efficiency of rotational dynamic element matching. 1. A system for rotational dynamic element matching in a delta sigma converter , comprising:a rotational dynamic element matching (DEM) component configured to receive a data signal, wherein the rotational DEM component has a plurality of elements, a start pointer, and a current pointer;wherein the current pointer shifts in a first direction when the data signal is positive and wherein the current pointer shifts in an opposite direction when the data signal is negative.2. The system of claim 1 , wherein the rotational DEM component is a barrel shifter claim 1 , and wherein the current pointer shifts circularly.3. The system of claim 2 , wherein the first direction is clockwise and the opposite direction is counterclockwise.4. The system of claim 2 , wherein the first direction is counterclockwise and the opposite direction is clockwise.5. The system of claim 1 , wherein a last element used when the data signal is positive is a first element used when the data signal is negative.6. The system of claim 1 , wherein a last element used when the data signal is negative is a first element used when the data signal is positive.7. The system of claim 1 , further comprising a current digital to analog converter configured to convert a rotational DEM component output into an analog signal.8. The system of claim 7 , wherein the current digital to analog converter is one of a 2-level current mode digital to analog converter and a 3-level current mode digital to ...

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Номер записи: 26
23-01-2020 дата публикации

MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE

Номер: US20200028720A1
Автор: Balb Markus, Ebert Ralf, Hollis Timothy M.
Принадлежит:

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data. 1. (canceled)2. An apparatus , comprising:an array of memory cells;a controller configured to control operation of memory cells in the array of memory cells;an interposer formed of a first material and operatively coupled with the array of memory cells and the controller, wherein the interposer comprises a plurality of channels between the array of memory cells and the controller;a substrate coupled with the interposer and formed of a second material different than the first material; anda receiver configured to determine a logic state represented by a signal modulated using a first modulation scheme communicated across at least one channel of the interposer.3. The apparatus of claim 2 , further comprising:a driver configured to generate the signal to be transmitted across the at least one channel of the interposer based at least in part on a plurality of information bits.4. The apparatus of claim 2 , wherein the signal comprises a binary-level signal.5. The apparatus of claim 4 , wherein the first modulation scheme comprises a non-return-to-zero (NRZ) scheme claim 4 , a unipolar encoding scheme claim 4 , a bipolar encoding scheme claim 4 , a Manchester encoding scheme claim 4 , a two-level pulse amplitude modulation (PAM) scheme claim 4 , or a combination thereof.6. The apparatus of claim 2 , wherein the signal comprises a non-binary signal.7. The apparatus of claim 6 , wherein the first modulation scheme comprises a four-level pulse amplitude modulation (PAM ...

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Номер записи: 27
02-02-2017 дата публикации

COLLABORATIVE CLOCK AND DATA RECOVERY

Номер: US20170033918A1
Автор: Dong Yikui Jen, Hossain Masum, Nguyen Nhat, Zargaran-Yazd Arash
Принадлежит:

A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams. 1. A receiver circuit for generating a data signal and recovering a clock signal from an input signal , comprising:a plurality of data samplers configured to sample the input signal using a respective plurality of threshold voltages, the plurality of data samplers configured to sample the input signal according to a first edge of the clock signal;an edge sampler configured to sample the input signal using a second edge of the clock signal and a first threshold voltage;a phase detector to produce a first phase error signal, the phase detector to produce the first phase error signal based on selected samples produced by the edge sampler, the samples to be selected based on a plurality of samples produced by the data samplers; and,a clock data recovery circuit to produce the clock signal based on a combined phase error signal, the combined phase error signal based on the first phase error signal and at least one phase error signal received from another receiver circuit.2. The receiver circuit of claim 1 , wherein the at least one phase error signal and the first phase error ...

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Номер записи: 28
01-02-2018 дата публикации

SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS

Номер: US20180034465A1
Автор: Whetsel Lee D.
Принадлежит:

First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. 1. A LVDS input circuit comprising:(a) a serial data out input;(b) a first, serial data in, low voltage differential signal lead;(c) a second, serial data in, low voltage differential signal lead;(d) a serial data in output;(e) an inverter having an input connected to the serial data out input and having an output; i. a first comparator having a non-inverting input connected to the first low voltage differential signal lead, an inverting input connected to the second low voltage differential signal lead, and a first control output, the first comparator requiring a voltage on the non-inverting input to be greater than a certain offset from a voltage on the inverting input before producing a logic high on the first control output; and', 'ii. a second comparator having a non-inverting input connected to the second low voltage differential signal lead, an inverting input connected to the first low voltage differential signal lead, and a second control output, the second comparator requiring a voltage on the non-inverting input to be greater than a certain offset from a voltage on the inverting input before producing a logic high on the second control output;, '(f) a window comparator including(g) a multiplexer having a first input coupled to a fixed logic high, a second ...

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Номер записи: 29
12-02-2015 дата публикации

System and Method for Cooperative Precoding in Heterogenous Two-Tier Wireless Networks

Номер: US20150043436A1
Автор: Maaref Amine
Принадлежит: Futurewei Technologies, Inc.

Embodiments are provided for a cooperative cross-tier precoding (CTP) and intra-tier precoding (ITP) scheme for two-tier networks. The cooperative precoding scheme allows exploitation of extra transmit dimensions at the second-tier network, thereby increasing the achievable throughput at the second-tier network. The embodiments allow significant increase in throughput of the second-tier network due to both CTP between the second-tier network and the first-tier network, and efficient ITP between the second-tier network transmitters. The increase in transmit dimension allows for efficient linear inra-tier precoding, which significantly reduces the intra-tier interference. A processor coupled to the second-tier network transmitters is configured to perform CTP of transmit signals in the second-tier network for cancelling signal interference from the second-tier network transmitters to a first-tier network receiver, thereby generating CTP matrix information. The processor then performs, using the CTP matrix information, ITP for reducing intra-signal interference from the second-tier transmitters to corresponding second-tier receivers. 1. A method for reducing or avoiding signal interference in a first tier network from a second tier network and within the second tier network , the method comprising:performing, by a network device, cooperative cross-tier precoding (CTP) for transmit signals of transmitter devices in the second tier network;generating, by the network device, CTP matrix information in accordance with the performed cooperative CTP;performing, by the network device, intra-tier precoding (ITP) for the transmit signals in accordance with the CTP matrix information; andforwarding information about the cooperative CTP and ITP to the transmitter devices in the second tier network.2. The method of further comprising:receiving, by the network device from a user device in the first tier network, channel state information (CSI) of signals received by the user device ...

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Номер записи: 30
04-02-2021 дата публикации

USER STATION FOR A SERIAL BUS SYSTEM AND METHOD FOR TRANSMITTING A MESSAGE IN A SERIAL BUS SYSTEM

Номер: US20210036884A1
Автор: Mutter Arthur, Walker Steffen
Принадлежит:

A user station for a bus system and a method for transmitting a message at different bit rates in a bus system. The user station includes a transmitting stage for transmitting a message on a bus line of the bus system. The transmitting stage switches between a first operating mode and a second operating mode when transmitting different phases of a message. The transmitting stage, in the first operating mode, generates a first data state as a bus state having different bus levels for two bus wires of the bus line, and generates a second data state as a bus state having the same bus level for the two bus wires of the bus line. The transmitting stage, in the second operating mode, generates the first and second data state in each case as a bus state having different bus levels for the two bus wires of the bus line. 112-. (canceled)13. A user station for a serial bus system , comprising:a transmitting stage configured to transmit a message on a bus line of the bus system, the transmitting stage being configured to switch between a first operating mode and a second operating mode when transmitting different phases of the message, the transmitting stage, in the first operating mode, being configured to generate a first data state as a bus state having different bus levels for two bus wires of the bus line, and to generate a second data state as a bus state having the same bus level for the two bus wires of the bus line, and the transmitting stage, in the second operating mode, being configured to generate the first data state and second data state as a bus state having different bus levels for the two bus wires of the bus line.14. The user station as recited in claim 13 , wherein the transmitting stage is configured to switch into the first operating mode when data of a first phase of the message are to be transmitted claim 13 , which are to be transmitted at a first bit rate claim 13 , and to switch into the second operating mode when data of second phase of the message ...

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Номер записи: 31
11-02-2016 дата публикации

MULTI-LEVEL SIGNALING

Номер: US20160043885A1
Автор: Hollis Timothy M.
Принадлежит:

Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output. 1. (canceled)2. An electronic device comprising:a first integrated circuit die comprising a transmitter circuit, the transmitter circuit comprising an encoder configured to generate at least three control signals and a push-pull circuit configured to generate a multi-level signal having more than two signal levels, wherein each of the more than two signal levels corresponds to a different data input value provided to the encoder; anda second integrated circuit die stacked with the first integrated circuit die, the second integrated circuit die configured to receive the multi-level signal from the first integrated circuit die.3. The electronic device of claim 2 , wherein the multi-level signal has a voltage swing that is less than a rail-to-rail voltage in a channel between the first integrated circuit die and the second integrated circuit die.4. The electronic device of claim 2 , wherein the push-pull circuit comprises:a first voltage drop circuit configured to adjust a first reference ...

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Номер записи: 32
24-02-2022 дата публикации

Transmission device, reception device, and communication system

Номер: US20220060357A1
Автор: Hironobu Konishi, Takashi Yokokawa
Принадлежит: Sony Group Corp

A transmission device of the disclosure includes: a generator unit that generates, on the basis of a control signal, a transmission symbol signal that indicates a sequence of transmission symbols; an output control unit that generates an output control signal on the basis of the transmission symbol signal; and a driver unit that generates, on the basis of the output control signal, a first output signal, a second output signal, and a third output signal. The generator unit generates the transmission symbol signal on the basis of the control signal, to allow the first output signal, the second output signal, and the third output signal to exchange signal patterns with one another.

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Номер записи: 33
07-02-2019 дата публикации

MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE

Номер: US20190044764A1
Автор: Balb Markus, Ebert Ralf, Hollis Timothy M.
Принадлежит:

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data. 1. An electronic memory apparatus , comprising:an array of memory cells;a controller configured to control access to the array of memory cells;an interposer to operatively couple the array of memory cells with the controller, the interposer including a plurality of channels between the array of memory cells and the controller; anda receiver configured to decode a multi-level signal modulated using a first modulation scheme having at least three levels communicated across at least one channel of the interposer.2. The apparatus of claim 1 , further comprising:a driver configured to generate the multi-level signal to be transmitted across the at least one channel of the interposer based at least in part on a plurality of information bits.3. The apparatus of claim 1 , wherein the receiver further comprises:a plurality of comparators, each comparator configured to compare the multi-level signal to a voltage threshold.4. The apparatus of claim 3 , wherein the receiver further comprises:a decoder configured to determine a plurality of bits represented by the multi-level signal based at least in part on information received from a set of the plurality of comparators.5. The apparatus of claim 1 , wherein:a plurality of information bits are represented by an amplitude of the multi-level signal.6. The apparatus of claim 1 , wherein:the multi-level signal is encoded with information using a pulse-amplitude modulation (PAM) scheme.7. The apparatus of claim 1 , wherein:the ...

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Номер записи: 34
03-03-2022 дата публикации

SELECTABLE MODE TRANSMITTER DRIVER

Номер: US20220070029A1
Автор: CHONG Euhan
Принадлежит:

A circuit for a transmitter driver is disclosed. The transmitter driver circuit includes a main voltage-mode driver circuit configured to receive an input signal at the input port and to drive an output signal at the output port. The transmitter driver circuit also includes a secondary circuit connected to the input port and the output port in parallel with the main voltage-mode driver circuit. The secondary circuit includes: a secondary voltage-mode driver circuit; a current source connected to the secondary voltage-mode driver circuit and controllable to enable or disable a current boost to the output signal; and a switch connected to the secondary voltage-mode driver circuit and controllable to enable or disable the secondary voltage-mode driver circuit to drive the output signal in parallel with the main voltage-driver circuit.

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Номер записи: 35
14-02-2019 дата публикации

DIRECT SEQUENCE DETECTION AND EQUALIATION

Номер: US20190052490A1
Автор: Hossain Masum, Mohammad Maruf H.
Принадлежит: RAMBUS INC.

Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages. 118-. (canceled)19. An integrated circuit (IC) , comprising:a plurality of comparators, wherein each comparator has a respective reference voltage that is adjustable, wherein each comparator outputs a result signal based on comparing a received input from a communication channel with the comparator's reference voltage, wherein reference voltages for the plurality of comparators are computed based on a main cursor and at least one pre-cursor associated with the communication channel, and wherein each generated reference voltage corresponds to a particular sequence of symbols; anda sequence-selection circuit to select a sequence of symbols based on result signals outputted by the plurality of comparators.20. The IC of claim 19 , wherein each symbol in the sequence of symbols is transmitted over the communication channel at successive time instances claim 19 , and wherein the sequence of symbols is selected based on received input that is sampled at a single time instance.21. The IC of claim 19 , wherein the sequence-selection circuit comprises:{'sup': 'M', 'a sequence generation circuit to generate a set of 2possible sequences of symbols based on the result signals outputted by the plurality of comparators; and'}{'sup': 'M', 'a chain of M multiplexers, where each multiplexer in the chain of M multiplexers selects a progressively smaller subset of possible ...

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Номер записи: 36
02-03-2017 дата публикации

USER STATION FOR A BUS SYSTEM AND METHOD FOR REDUCING LINE-CONDUCTED EMISSIONS IN A BUS SYSTEM

Номер: US20170063571A1
Автор: Hartwich Florian, HEHEMANN Ingo, Walker Steffen
Принадлежит: ROBERT BOSCH GMBH

A user station for a bus system and a method for reducing line-conducted emissions in a bus system, in which the user station includes a transceiver for transmitting or receiving a message from at least one additional user station of the bus system via the bus system. In the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured. The transceiver includes an emission control device for controlling the properties of the transceiver to reduce line-conducted emissions in the bus system. The transceiver is also configured for switching the emission control device on or off as a function of the arbitration phase and the data area of the message. 110-. (canceled)11. A user station for a bus system , comprising:a transceiver to transmit or receive a message from at least one additional user station of the bus system via the bus system, wherein in the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured;wherein the transceiver includes an emission control device to control the properties of the transceiver to reduce line-conducted emissions in the bus system, andwherein the transceiver is configured to switch the emission control device on or off as a function of the arbitration phase and the data area of the message.12. The user station of claim 11 , further comprising:a communication control device to control the communication in the bus system, wherein the communication control device or the transceiver includes a detection device to detect a data area.13. The user station of claim 12 , wherein the transceiver includes a detection device configured to recognize the data area based on detection of a BRS bit at the end of an arbitration phase.14. The user station of claim 12 , wherein the transceiver is configured to recognize the data area based on a switching signal from the communication control device.15. The user station of claim 12 , ...

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Номер записи: 37
02-03-2017 дата публикации

TRANSMITTING DEVICE FOR HIGH SPEED COMMUNICATION, AND INTERFACE CIRCUIT AND SYSTEM INCLUDING THE SAME

Номер: US20170063582A1
Автор: SHIM Jong Joo
Принадлежит:

A transmitting device may include an encoder, a timing transmission controller, and a transmission driver. The encoder may generate transmission control signals according to control symbols. The timing transmission controller may generate driving control signals from the transmission control signals. The transmission driver may drive each of wires to one level among multiple levels, based on the driving control signals. The timing transmission controller may control generation timings of the driving control signals according to levels to which the wires are to be driven. 1. A transmitting device comprising:a logic circuit configured to generate control symbols;an encoder configured to change information of a wire state based on the control symbols, and generate transmission control signals;a timing transmission controller configured to generate driving control signals based on the transmission control signals, and control generation timings of the driving control signals by comparing previously inputted transmission control signals and currently inputted transmission control signals; anda transmission driver configured to drive each of a plurality of wires to one level among multiple levels, in response to the driving control signals.2. The transmitting device according to claim 1 ,wherein the control symbols include a hold information, a rotation and an inversion information, andwherein the encoder generates the transmission control signals according to the hold information, the rotation information and the inversion information.3. The transmitting device according to claim 2 , wherein the encoder comprises:a first encoder configured to change most significant bit (MSB) information of the wire state according to control symbols, and generate first transmission control signals; anda second encoder configured to change least significant bit (LSB) information of the wire state according to control symbols, and generate second transmission control signals.4. The ...

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Номер записи: 38
17-03-2022 дата публикации

MEMORY DEVICE, METHOD OF CALIBRATING SIGNAL LEVEL THEREOF, AND MEMORY SYSTEM HAVING THE SAME

Номер: US20220083244A1
Автор: Choi Junghwan, CHOI Youngdon, PARK JaeWoo, SON Younghoon, Um Youngdo
Принадлежит:

A method of calibrating a signal level of a memory device includes performing pull-up code and pull-down code calibrations, using a ZQ calibration for non-return-to-zero (NRZ) signaling, performing a most significant bit (MSB) code calibration, using an MSB additional driver for pulse amplitude modulation level-4 (PAM4) signaling, and performing a least significant bit (LSB) code calibration using an LSB additional driver for the PAM4 signaling. 1. A memory device comprising:a transceiver configured to transmit or receive data according to multilevel signaling; anda ratio of level separation mismatch (RLM) controller configured to adjust at least one gap between signal levels during a data transmission operation of the transceiver,wherein the RLM controller includes:a resistor connected between a first node and a ground terminal,a first comparator configured to output a first comparison voltage by comparing a first adjusted voltage of the first node to a first reference voltage,a second comparator configured to output a second comparison voltage by comparing a second adjusted voltage of a second node to a second reference voltage;a first code generator configured to generate a pull-up code, a most significant bit (MSB) additional code, or a least significant bit (LSB) additional code, corresponding to the first comparison voltage;a second code generator configured to generate a pull-down code corresponding to the second comparison voltage;a first MSB pull-up driver connected between a power supply terminal and the first node and configured to control driving capability for at least a first higher bit according to the pull-up code,a first LSB pull-up driver connected between the power supply terminal and the first node and configured to control driving capability for at least a first lower bit according to the pull-up code,a first MSB pull-down driver connected between the first node and the ground terminal and configured to control driving capability for at least a ...

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Номер записи: 39
12-03-2015 дата публикации

FILTERING HIGH SPEED SIGNALS

Номер: US20150071333A1
Автор: Chen Huabo, Mao Wenjie, Riat Mayan, Zhou Yaping
Принадлежит: NVIDIA CORPORATION

A method for filtering a data signal includes transmitting the data signal from a transmitter to a receiver across a conductor disposed in an interposer, which interconnects the receiver and the transmitter. The data signal is low-passed with a filter, which includes a passive resistive element disposed within the interposer and coupled in series electrically with a passive inductive element. In relation thereto, the interposer is disposed in a position within the interposer, or upon a surface thereof. The filter is coupled to the conductor in a shunt configuration with respect to ground. 1. A circuit for filtering a data signal , the circuit comprising:an interposer component, comprising a plurality of conductors disposed within a semiconductor substrate;a receiver component electrically coupled to a first end of at least one of the plurality of conductors;a transmitter component electrically coupled to a second end of the at least one of the plurality of conductors and interactively operable with the receiver component therewith for exchanging the data signal; anda filter component, comprising a passive inductive device coupled electrically in series with a passive resistive device, which is disposed within the interposer component, wherein the filter component is electrically coupled to the at least one of the plurality of conductors, in a shunt configuration with respect to a ground potential, and operable for low-passing the data signal.2. The circuit as recited in wherein filter component is coupled to the at least one conductor at a location thereof more proximately in relation to at least one of the first end claim 1 , the second end claim 1 , or a position between the first end and the second end.3. The circuit as recited in wherein the exchanging the data signal comprises a single ended transaction.4. The circuit as recited in wherein the plurality of conductors comprises a second conductor claim 1 , wherein the receiver component is further coupled to a ...

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Номер записи: 40
12-03-2015 дата публикации

METHOD OF GENERATING DRIVING SIGNAL FOR DRIVING DUAL MODE SUPPLY MODULATOR FOR POWER AMPLIFIER AND DEVICE THEREOF

Номер: US20150071371A1
Автор: JUNG Jae Ho, LEE Kwangchun, LEE Sung Jun
Принадлежит: Electronics and Telecommunications Research Institute

Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter. 1. A method of generating a driving signal for driving a dual mode supply modulator which provides dual supply voltages to a power amplifier , the method comprising:obtaining an envelope of a complex baseband signal to be transmitted;comparing the envelope of the complex signal with a preset threshold value;when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N (where N is zero or a positive integer) comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; andwhen the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter.2. The method of claim 1 , wherein the digital board output signal configured with the first and second logic levels is applied to ...

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Номер записи: 41
10-03-2016 дата публикации

Wideband transmitter with high-frequency signal peaking

Номер: US20160072645A1
Автор: Kenneth Luis Arcudia, Tao Jiang, Zhiqin Chen
Принадлежит: Qualcomm Inc

A transmitter is provided that includes a voltage-mode driver and a current-mode driver. The current-mode driver includes a plurality of transconductors biased by high-pass filtered versions of a differential output voltage from the voltage-mode driver.

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Номер записи: 42
28-02-2019 дата публикации

RECEIVERS WITH AUTOMATIC GAIN CONTROL

Номер: US20190068292A1
Автор: Florentino Marco, Li Cheng, Zhu Kehan
Принадлежит:

One example of a receiver includes a first stage, a second stage, a third stage, and an automatic gain controller. The first stage amplifies an input signal to provide a first signal. The second stage amplifies or attenuates the first signal to provide a second signal based on a tunable gain of the second stage. The tunable gain is adjusted in response to a differential signal. The third stage amplifies the second signal to provide an output signal. The automatic gain controller provides the differential signal based on a comparison between a peak voltage of the output signal and the sum of a common mode voltage of the output signal and an offset voltage. 1. A receiver comprising:a first stage to amplify an input signal to provide a first signal;a second stage to amplify or attenuate the first signal to provide a second signal based on a tunable gain of the second stage, the tunable gain adjusted in response to a differential signal;a third stage to amplify the second signal to provide an output signal; andan automatic gain controller to provide the differential signal based on a comparison between a peak voltage of the output signal and the sum of a common mode voltage of the output signal and an offset voltage.2. The receiver of claim 1 , wherein the automatic gain controller comprises:a peak detector to sense the peak voltage of the output signal, sense the common mode voltage of the output signal, and provide the offset voltage; anda fully differential comparator to compare the sensed peak voltage of the output signal with the sum of the common mode voltage of the output signal and the offset voltage to provide the differential signal.3. The receiver of claim 1 , wherein the second stage comprises an always on first transistor in parallel with a second transistor and an always on third transistor in parallel with a fourth transistor claim 1 , the second transistor and the fourth transistor controlled by the differential signal claim 1 , respectively claim 1 , to ...

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Номер записи: 43
09-03-2017 дата публикации

USER STATION FOR A BUS SYSTEM AND METHOD FOR IMPROVING THE TRANSMISSION QUALITY IN A BUS SYSTEM

Номер: US20170070366A1
Автор: Hartwich Florian, HEHEMANN Ingo, Walker Steffen
Принадлежит:

A user station for a bus system and a method for improving the transmission quality in a bus system are provided. The user station includes a transceiver for transmitting or receiving a message to/from at least one additional user station of the bus system via the bus system. In the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured. The transceiver includes a transmission signal processing device for transmission signal processing of a transmission signal to be transmitted by the transceiver. The transmission signal processing device is configured for setting a predetermined bit symmetry of bits of the transmission signal by generating an internal transmission signal for the message. In the internal transmission signal, the dominant phase of the bits is shortened and the recessive phase of the bits is lengthened. 110-. (canceled)11. A user station for a bus system , comprising:a transceiver for transmitting or receiving a message to or from at least one additional user station of the bus system) via the bus system, wherein in the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured;wherein the transceiver includes a transmission signal processing device for transmission signal processing of a transmission signal to be transmitted by the transceiver,wherein the transmission signal processing device is configured for setting a predetermined bit symmetry of bits of the transmission signal by generating an internal transmission signal for the message, andwherein in the internal transmission signal the dominant phase of the bits is shortened and the recessive phase of the bits is lengthened.12. The user station of claim 11 , wherein the transmission signal processing device is configured for delaying the falling edge of a bit in the internal transmission signal claim 11 , so that the dominant phase of the bits is shortened and the ...

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Номер записи: 44
11-03-2021 дата публикации

IO-Link Device

Номер: US20210075644A1
Автор: Bagalá Fabio, Mestieri Marco
Принадлежит:

An IO-link device () configured as slave for transmitting/receiving signal data with a master module (), the IO-link device comprising: a sensor or actuator () configured to produce output measurement signals; a first microcontroller () operatively coupled to the sensor or actuator and configured to receive the measurement signals and generate data based on the measurement signals, and a transceiving module () which comprises a physical layer transceiver () configured to receive/transmit signal data from/to the master module (), and a second microcontroller () operatively coupled and in bi-directional communication with the transceiver, wherein the transceiver () is configured to receive signal data associated with a request from the master module () and transmit signal data associated with the request to the second microcontroller () and the second microcontroller () is configured to receive the signal data from the transceiver and to execute a device IO-Link protocol stack, the second microcontroller being operatively coupled and in bi-directional communication with the first microcontroller () for the transmission of signal data associated with the request to the first microcontroller and to receive data based on measurement signals from the first controller. 110-. (canceled)11. An IO-link device configured as slave for transmitting or receiving signal data with a master module , the IO-link device comprising:a sensor or actuator configured to output measurement signals;a first microcontroller operatively coupled to the sensor or actuator and configured to receive the measurement signals and to generate data based on the measurement signals, anda transceiving module comprising a physical layer transceiver configured to receive or transmit signal data from or to the master module,the device comprising a second microcontroller operatively coupled to, and in bidirectional communication with, the physical layer transceiver,wherein the physical layer transceiver is ...

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Номер записи: 45
19-03-2015 дата публикации

COMMUNICATION SYSTEMS BASED ON HIGH-GAIN SIGNALING

Номер: US20150078475A1
Автор: Hairapetian Armond
Принадлежит: StarPort Communications, Inc.

Systems, methods and apparatus for transferring data at a high rate. Examples may provide transmitters and receivers that transfer data at a high rate by encoding the data to be transmitted such that the circuits of the transmitter and receiver operate in their high-gain states. The encoded signal may have an average value that is independent of the data that is conveyed by the transmitted signal. In other examples, the encoding may shape the data signal into a data signal having a high-pass characteristic. When the high-pass encoded signal is transmitted through a channel having a low-pass transfer function, the resulting output signal may have much lower ISI compared to a un-encoded input signal. Transmit and receive circuits, such as amplifiers, laser, and photo-diodes, are biased to operate in their high-gain regions when receiving the encoded data in order to provide high-bandwidth and shorter transition times. 1. A transmitter comprising:an encoder having at least one input adapted to receive a data signal, the encoder capable of encoding the data signal into an encoded multi-level data signal having substantially reduced DC and low-frequency components; andan output stage coupled to receive the encoded multi-level data signal and to transmit the encoded multi-level data signal,wherein the output stage is configured to have a transfer function that includes a high-gain linear region, and wherein the output stage is conditioned to operate at least substantially in the high-gain linear region when receiving and transmitting the encoded multi-level data signal.2. The transmitter of wherein the output stage is conditioned to operate near a center of the high-gain linear region and remains substantially in its high-gain linear region when transmitting the encoded multi-level data signal.3. The transmitter of wherein the encoding of the data signal substantially reduces DC and low-frequency components of the data signal whereby claim 1 , in frequency domain claim 1 ...

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Номер записи: 46
05-06-2014 дата публикации

USE OF MULTI-LEVEL MODULATION SIGNALING FOR SHORT REACH DATA COMMUNICATIONS

Номер: US20140153620A1
Автор: Longo Lorenzo, Telang Vivek
Принадлежит: BROADCOM CORPORATION

A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate. 1. A high speed communication system comprising:a high speed SERDES comprising a transceiver;a multi-level modulated data signal transmitted or received over a communications channel medium by the transceiver; andwherein the multi-level modulated data signal reduces a data signaling rate of the high speed communication system.2. A high speed communication system claim 1 , as per claim 1 , wherein the transceiver comprises at least a transmitter claim 1 , the transmitter comprising a transmission pre-emphasizer and driver.3. A high speed communication system claim 1 , as per claim 1 , wherein the transceiver comprises at least a receiver claim 1 , the receiver comprising a continuous time linear equalizer (CTLE) claim 1 , slicer and clock and data recovery circuit (CDR).4. A high speed communication system claim 3 , as per claim 3 , wherein the CTLE boosts high frequencies attenuated during transmission across the communications channel medium to constantly optimize performance claim 3 , the slicer slices data signals output from the CTLE into at least four levels and the CDR optimizes phase and instantaneous sampling.5. A high speed communication system claim 1 , as per claim 1 , wherein the high speed communication system is operative with the communications channel medium comprising any of claim 1 , or a combination of: short trace PCB claim 1 , backplane claim 1 , copper wire claim 1 , wireline and fiber.6. A high speed communication ...

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Номер записи: 47
05-06-2014 дата публикации

N-PHASE PHASE AND POLARITY ENCODED SERIAL INTERFACE

Номер: US20140153665A1
Автор: Lee Chulkyu, Raskin Glenn D., Wiley George Alan
Принадлежит: QUALCOMM INCORPORATED

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector. 1. A method for data communications , comprising:encoding data in multi-bit symbols; and mapping the multi-bit symbols to a sequence of states of the plurality of connectors, and', 'driving the connectors in accordance with the sequence of states, wherein timing of the sequence of states is determinable at a receiver at each transition between sequential states,, 'transmitting the multi-bit symbols on a plurality of connectors, wherein transmitting the multi-bit symbols includes'}wherein the state of each connector is defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.2. The method of claim 1 , wherein for each state in the sequence of states claim 1 , the multi-phase signal carried on each connector is phase-shifted with respect to the multi-phase signal carried on the other connectors.3. The method of claim 1 , wherein the state of at least one of the plurality of connectors changes at each transition between the sequence of states.4. The method of claim 1 , wherein the plurality of connectors include a plurality of wires claim 1 , and wherein transmitting the multi-bit symbols on the plurality of connectors includes: leaving a first wire undriven, and', ' ...

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Номер записи: 48
07-03-2019 дата публикации

Low power multilevel driver

Номер: US20190073332A1
Автор: Armin TAJALLI, Omid Talebi Amiri
Принадлежит: Kandou Labs SA

Methods and systems are described for receiving a set of input bits at a plurality of drivers and responsively generating an ensemble of signals, each respective signal of the ensemble of signals generated by receiving a subset of input bits at a respective driver connected to a respective wire of a multi-wire bus, the received subset of bits corresponding to sub-channels associated with the respective wire, generating a plurality of weighted analog signal components, each weighted analog signal component (i) having a corresponding weight and sign selected from a set of wire-specific sub-channel weights associated with the respective wire and (ii) modulated by a corresponding bit of the received subset of bits, and generating the respective signal by forming a summation of the plurality of weighted analog signal components at a common node connected to the respective wire for transmission over the respective wire of the multi-wire bus.

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Номер записи: 49
24-03-2022 дата публикации

SIGNAL TRANSMISSION SYSTEM, TRANSMITTER ENCODING APPARATUS AND RECEIVER DECODING APPARATUS

Номер: US20220094575A1
Автор: Sung Lien-Hsiang, Tung Hsu-Jung
Принадлежит:

A transmitter encoding apparatus includes a multiplexer and a first transmitter encoder. The multiplexer receives a first digital signal and a second signal and to generate an output, in which the output of the multiplexer includes M-bit code words of the first digital signal and M-bit code words of the second digital signal arranged in an interleaved manner. The first transmitter encoder receives the output of the multiplexer and generates N-bit code words, and N is not equal to M. The first transmitter encoder determines a current N-bit code word of the N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the N-bit code words. The first transmitter encoder transmits the N-bit code words to a receiver decoding apparatus including a demultiplexer and a first receiver decoder configured to decode the N-bit code words. 1. A signal transmission system , comprising: a multiplexer, configured to receive a first digital signal and a second digital signal and generate an output, wherein the output of the multiplexer comprises a plurality of M-bit code words of the first digital signal and a plurality of M-bit code words of the second digital signal, wherein the plurality of M-bit code words of the first digital signal and the plurality of M-bit code words of the second digital signal are arranged in an interleaved manner, and M is a positive integer; and', 'a first transmitter encoder, configured to encode the output of the multiplexer to generate a plurality of N-bit code words, wherein N is a positive integer and N is not equal to M, wherein the first transmitter encoder is configured to determine a current N-bit code word of the plurality of N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the plurality of N-bit code words; and, 'a transmitter encoding apparatus comprising a first receiver decoder, configured to decode the plurality of N-bit code words to ...

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Номер записи: 50
14-03-2019 дата публикации

METHOD AND APPARATUS FOR GENERATING A MULTI-LEVEL PSEUDO-RANDOM TEST SIGNAL

Номер: US20190081829A1
Автор: Kossel Marcel A.
Принадлежит:

The present invention relates to a method for generating multi-level PRBS patterns for testing purposes, wherein the method includes the steps of providing a binary PRBS signal with a binary bit pattern sequence and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output. 1. A method for generating multi-level PRBS patterns , comprising: mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output,', 'wherein one symbol of a list of symbols is output each time a state machine is triggered by a bit tester configured for triggering a first state machine using a first trigger signal for each of one or more clock cycles, and', 'wherein the multilevel output is synchronized to a clock signal and transmitted via a transmission channel., 'providing a binary PRBS signal with a binary bit pattern sequence; and'}2. The method according to claim 1 , wherein the symbol level is represented by a level of an electrical quantity claim 1 , particularly of a voltage.3. The method according to claim 2 , wherein a first state of the bits of the binary bit pattern sequence is associated to a first set of symbols and wherein a second state of the bits of the binary bit pattern sequence is associated to a second set of symbols.4. The method according to claim 3 , wherein the symbols of the first set of symbols are represented by levels of an electrical quantity having a first sign and the symbols of the second set of symbols are represented by levels of an electrical quantity having a second sign.5. The method according to claim 4 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.6. The method according to claim 4 , wherein the multilevel output is a N-PAM output claim 4 , wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols.7. The method according to claim 6 , wherein the symbols of the first and second set of symbols are ...

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Номер записи: 51
24-03-2016 дата публикации

MULTI-DROP CHANNELS INCLUDING REFLECTION ENHANCEMENT

Номер: US20160087782A1
Автор: Han Minghui
Принадлежит:

A clock channel to couple a transmitter to a plurality of receivers, the clock channel including: a transmission line to be coupled to an input of at least one receiver from among a plurality of receivers, the transmission line including: a reflection portion to reflect a clock signal propagating through the clock channel according to a clock frequency.

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Номер записи: 52
24-03-2016 дата публикации

RECEIVER WITH DUOBINARY MODE OF OPERATION

Номер: US20160087821A1
Автор: Chen E-Hung
Принадлежит:

An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path. 1 sampling circuitry to determine symbol state;', 'a duobinary decoder coupled to the sampling circuitry to convert the detected states to a PAM2 coded symbol stream; and', 'a decision-feedback equalizer (DFE) having inputs coupled to the sampling circuitry in parallel with the duobinary decoder, the DFE cooperating with the sampling circuitry to form a feedback path, wherein the duobinary decoder is external to the feedback path., 'a receiver circuit operable to receive duobinary data symbols from a first signaling lane, the receiver circuit including'}. An integrated circuit comprising: This application is a continuation of U.S. Ser. No. 14/073,003, filed Nov. 6, 2013, titled RECEIVER WITH DUOBINARY MODE OF OPERATION, which claims the benefit of priority under 35 U.S.C. §119(e) to Provisional Application Ser. No. 61/727,587, filed Nov. 16, 2012, titled RECEIVER WITH DUOBINARY MODE OF OPERATION, all of which are incorporated herein by reference in their entirety.The disclosure herein relates generally to communications, and more specifically to high speed electronic signaling within and between integrated circuit devices.Duobinary coding is a signaling scheme often employed in optical networks due to its data rate capabilities with a reduced spectrum. Generally, the coding involves summing each current bit with the most recent previously ...

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Номер записи: 53
24-03-2016 дата публикации

NON-RECIPROCAL COMPONENTS WITH BALANCED DISTRIBUTEDLY MODULATED CAPACITORS (DMC)

Номер: US20160087823A1
Автор: Wang Yuanxun Ethan
Принадлежит: The Regents of the University of California

A non-reciprocal radio frequency transceiver front end utilizing multiple time-varying transmission lines (TVTLs) implemented using distributed modulated capacitors (DMC) to exploit time-varying properties of transmission line structures to isolate the transmit and receive signals. The TVTLs are coupled at an input side to an antenna and ground through a first 90 degree coupler, and the outputs of the TVTLs are coupled through a second 90 degree coupler for connection to a receiver and transmit circuit, respectively. The apparatus allows simultaneously operating a transmitter and receiver sharing a single antenna (or single antenna array). 1. A non-reciprocal radio frequency transceiver front end apparatus , comprising:at least two time-varying transmission lines (TVTLs) connected between first and second 90 degree couplers in a balanced structure, with said first 90 degree coupler connected to antenna side ports, and said second 90 degree coupler connected to a transmitter port and a receiver port;wherein each of said TVTLs have first and second inputs and an output, and said TVTLs comprise distributed modulated capacitors (DMC) that perform upconversion in frequency, having upper and lower sidebands, in response to high frequency pumping from a carrier source;wherein the combination of said TVTLs and said couplers physically separate an upconverted received signal and transmitted signal into different ports for canceling upconverted transmitted signals at the receiver port while adding upconverted received signals at the receiver port so that a transmitter and receiver can share an antenna.2. A non-reciprocal radio frequency transceiver front end apparatus , comprising:at least a first and second time-varying transmission line (TVTL) providing two TVTL paths, each TVTL having first and second inputs and an output;wherein each TVTL comprises a transmission line of distributed modulated capacitors (DMC);wherein said second input is configured for connection to ...

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Номер записи: 54
23-03-2017 дата публикации

METHOD FOR AUTOMATICALLY FINDING THE OPTIMUM SAMPLING POINT IN AN EYE DIAGRAM

Номер: US20170085366A1
Автор: Poulo Richard J.
Принадлежит:

A system and method of multi-symbol communications from a transmitter to a receiver via a channel, including transmitting signals as a waveform representing a sequence of symbols, each symbol of unit-interval duration and each symbol associated with its own signal level. This method includes graphically representing the waveform as an eye diagram having a horizontal time axis and a vertical signal level axis arranged to form one or more eyes, and using a sampling point in each eye to determine which signal the waveform in any unit interval represents. Each sampling point has a phase and a decision threshold. The method further includes identifying the eyes in the eye diagram, finding a convex polygonal region fitting within each eye, finding a largest rectangle fitting the convex polygonal region of each eye, and positioning the sampling point in each eye at a center of the rectangle of that eye. 1. A communications system , comprising:a transmitter for transmitting a signal includes a sequence of symbols;a receiver for the sequence of symbols; anda channel coupling the transmitter to the receiver;the sequence of symbols including at least two different symbols which can be transmitted in one-unit interval and each symbol associated with its own signal level;the sequence of symbols defining an eye diagram for graphically representing in one or more eyes all possible unit-interval sized waveforms of a signal overlain in a graph one-unit interval wide;the eye diagram having a horizontal axis representing a time axis and a vertical axis representing the signal level;each eye forming a polygon having a horizontal axis representing a time axis and a vertical axis representing the signal level;a bounding box defining a region of each eye in the eye diagram bounded in time to a middle half of the unit interval and bounded in signal level by specific signal levels just below and just above the eye;a sampling point in the unit interval within each eye to determine which ...

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Номер записи: 55
02-04-2015 дата публикации

APPARATUS AND METHOD FOR MULTILEVEL CODING IN COMMUNICATION SYSTEMS

Номер: US20150092879A1
Автор: Jorgensen Lars, Mansour Mohamed F.
Принадлежит:

A method includes receiving input blocks each having multiple bits to be transmitted. The method also includes applying a first encoding scheme to a first subset of the bits in the input blocks to generate first encoded bits and applying a second encoding scheme to a second subset of the bits in the input blocks to generate second encoded bits. The second encoding scheme has lower overhead than the first encoding scheme. The method further includes generating symbols using the first and second encoded bits. The first encoded bits include two or more first bits per symbol of each output block, and the second encoded bits include one or more second bits per symbol of each output block. 1. A method comprising:receiving input blocks each having multiple bits to be transmitted;applying a first encoding scheme to a first subset of the bits in the input blocks to generate first encoded bits;applying a second encoding scheme to a second subset of the bits in the input blocks to generate second encoded bits, the second encoding scheme having lower overhead than the first encoding scheme; andgenerating symbols using the first and second encoded bits;wherein the first encoded bits include two or more first bits per symbol of each output block; andwherein the second encoded bits include one or more second bits per symbol of each output block.2. The method of claim 1 , wherein the first and second encoding schemes comprise different linear block coding schemes.3. The method of claim 2 , wherein:the first encoding scheme comprises a low-density parity check (LDPC) coding;the second encoding scheme comprises a Bose, Chaudhuri and Hocquenghem (BCH) coding;applying the first encoding scheme comprises generating LDPC codewords; and generating BCH codewords comprising a systematic part of the LDPC codewords; and', 'discarding portions of the BCH codewords associated with the first encoded bits., 'applying the second encoding scheme comprises4. The method of claim 1 , wherein ...

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Номер записи: 56
31-03-2022 дата публикации

DIRECT DIGITAL SEQUENCE DETECTION AND EQUALIZATION

Номер: US20220103404A1
Автор: Hossain Masum, Mohammad Maruf H.
Принадлежит: RAMBUS INC.

Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages. 118-. (canceled)19. An integrated circuit (IC) , comprising:a first circuit to generate a set of symbol sequences based on a first set of outputs, wherein the first set of outputs is generated by a first set of comparators based on an input signal and a first set of reference voltages;a second circuit to generate a set of probabilities based on a second set of outputs, wherein the second set of outputs is generated by a second set of comparators based on the input signal and a second set of reference voltages, wherein the second set of reference voltages are generated based on the first set of outputs and the first set of reference voltages; anda third circuit to select a symbol sequence from the set of symbol sequences based on the set of probabilities.20. The IC of claim 19 , wherein each probability in the set of probabilities corresponds to a respective symbol sequence in the set of symbol sequences.21. The IC of claim 19 , wherein each reference voltage in the second set of reference voltages corresponds to a respective symbol sequence in the set of symbol sequences.22. The IC of claim 21 , wherein the input signal is received over a communication channel.23. The IC of claim 22 , wherein the second set of reference voltages is based on a main cursor and at least one pre-cursor associated with the communication channel.24. The IC of claim 23 , wherein ...

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Номер записи: 57
25-03-2021 дата публикации

SIGNAL OUTPUT CIRCUIT, TRANSMISSION CIRCUIT AND INTEGRATED CIRCUIT

Номер: US20210091981A1
Автор: HIRAMATSU Taku, KAWAI Shigeaki
Принадлежит:

A signal output circuit includes: a driver circuit including a variable current source and configured to output a multilevel signal; a replica circuit having a circuit configuration equivalent to the driver circuit; and a control circuit configured to control a characteristic of the driver circuit, based on an output signal of the replica circuit, wherein the replica circuit includes: a first replica circuit part configured to output first output signals having signal levels of a first subset of a plurality of signal levels corresponding to the multilevel signal; and a second replica circuit part configured to output second output signals having signal levels of a second subset of the plurality of signal levels, and the control circuit is configured to control a characteristic of the variable current source, based the first output signals and the second output signals. 120-. (canceled)21. A signal output circuit comprising:a driver circuit including a variable current source and configured to output a multilevel signal;a first detection circuit configured to detect signal levels of a first subset of a plurality of signal levels corresponding to the multilevel signal outputted from the driver circuit;a second detection circuit configured to detect signal levels of a second subset of the plurality of signal levels corresponding to the multilevel signal outputted from the driver circuit; anda control circuit configured to control a characteristic of the driver circuit, based on the signal levels of the first subset and the signal levels of the second subset, whereinthe control circuit is configured to control a characteristic of the variable current source, based on the signal levels of the first subset and the signal levels of the second subset.22. The signal output circuit according to claim 21 , wherein:the driver circuit is configured to output a quaternary signal;the first detection circuit is configured to detect signal levels of a first subset of first to fourth ...

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Номер записи: 58
26-06-2014 дата публикации

Apparatuses and methods of communicating differential serial signals including charge injection

Номер: US20140176234A1
Автор: Gregory A. King
Принадлежит: Micron Technology Inc

Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed.

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Номер записи: 59
05-04-2018 дата публикации

METHOD AND APPARATUS FOR GENERATING A MULTI-LEVEL PSEUDO-RANDOM TEST SIGNAL

Номер: US20180097668A1
Автор: Kossel Marcel A.
Принадлежит:

The present invention relates to a method for generating multi-level PRBS patterns for testing purposes, wherein the method includes the steps of providing a binary PRBS signal with a binary bit pattern sequence and mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output. 1. A method for generating multi-level PRBS patterns , comprising: mapping each bit of the binary bit pattern sequence to a symbol of a multilevel output,', 'wherein one symbol of a list of symbols is sequentially output each time one or more state machines are triggered by a bit tester, and', 'wherein a multilevel output signal is synchronized to a clock signal and transmitted via a transmission channel, 'providing a binary PRBS signal with a binary bit pattern sequence; and'}2. The method according to claim 1 , wherein the symbol level is represented by a level of an electrical quantity claim 1 , particularly of a voltage.3. The method according to claim 2 , wherein a first state of the bits of the binary bit pattern sequence is associated to a first set of symbols and wherein a second state of the bits of the binary bit pattern sequence is associated to a second set of symbols.4. The method according to claim 3 , wherein the symbols of the first set of symbols are represented by levels of an electrical quantity having a first sign and the symbols of the second set of symbols are represented by levels of an electrical quantity having a second sign.5. The method according to claim 4 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.6. The method according to claim 4 , wherein the multilevel output is a N-PAM output claim 4 , wherein the first set of symbols has N/2 symbols and the second set of symbols has N/2 symbols.7. The method according to claim 6 , wherein the symbols of the first and second set of symbols are subsequently output in a pseudo random order.8. The method according to claim 3 , wherein the ...

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Номер записи: 60
01-04-2021 дата публикации

Self Referenced Single-Ended Chip to Chip Communication

Номер: US20210099252A1
Автор: Fang Emerson S., Leibowitz Brian S., Savoj Jafar, Singh Praveen R.
Принадлежит:

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes. 120-. (canceled)21. An apparatus comprising:an interface configured to receive a first plurality of signals; and determine a reference voltage based on an average voltage of signal levels of the first plurality of signals;', 'generate a second plurality of signals based on the first plurality of signals and the reference voltage; and', 'generate a sequence of bits based on the second plurality of signals, wherein sequence of bits represent bits used by a transmitter to generate the first plurality of signals., 'circuitry configured to22. The apparatus as recited in claim 21 , wherein the interface receives the first plurality of signals as a plurality of single-ended data signals on a plurality of transmission lines.23. The apparatus as recited in claim 22 , wherein a first voltage level representing a Boolean logic high value for the first plurality of signals is less than a second voltage level representing a Boolean logic high value for the second plurality of signals.24. The apparatus as recited in claim 23 , wherein the circuitry is further configured to determine whether a given signal of the first ...

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Номер записи: 61
28-03-2019 дата публикации

Simplified 3-phase mapping and coding

Номер: US20190097852A1
Автор: George Alan Wiley
Принадлежит: Qualcomm Inc

Systems, methods and apparatus are described that facilitate transmission of data between two devices within an electronic apparatus. An apparatus has a bus interface, a 3-phase encoder, and a processing circuit that can configure the 3-phase encoder for a first mode of operation in which data is encoded in a sequence of two-bit symbols, transmit a first three-phase signal representative of the sequence of two-bit symbols on each of the three wires. The processing circuit may be configured to configure the 3-phase encoder for a second mode of operation in which data is encoded in a sequence of three-bit symbols. Three-phase signal representative of the sequence of two-bit symbols or sequence of three-bit symbols on each of three wires, where a three-phase signal is in a different phase on each wire when transmitted, and a transition in signaling state occurs between transmission of each pair of symbols.

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Номер записи: 62
23-04-2015 дата публикации

SYSTEM AND METHOD FOR AMPLIFYING A SIGNAL

Номер: US20150110222A1
Автор: BOUVIER Jessica, COSTA Bruno, GUERN Pierre
Принадлежит:

An amplification system, connected to a modem delivering a signal to be amplified, includes at least one amplification device, at least one first determination device for determination of a first difference and at least one second determination device for determination of a variable gain. Moreover, the system is characterized in that the second determination device is capable of the determination of said variable gain on the basis of said signal to be amplified, said amplified signal and said first difference. 1. An amplification system , connected to a modem delivering a signal to be amplified , comprising:at least one amplification device in which an amplification gain is variable,at least one first determination device for determination of a first difference between an amplified signal and said signal to be amplified,at least one second determination device for determination of said variable gain,wherein said second determination device is capable of the determination of said variable gain on the basis of said signal to be amplified, said amplified signal and said first difference;said second device having:at least one third determination device for determination of a model, comprising a delay and a gain, of the perturbation of the first difference by the amplification device by means of a correlation between said signal to be amplified and said amplified signal,at least one fourth determination device for determination of perturbations of the first difference that are caused by said amplification device, on the basis of said model and said signal to be amplified,at least one fifth determination device for determination of a second difference between said first difference and said perturbations, anda controller that is capable of determining said variable gain on the basis of said second difference.2. The amplification system of claim 1 , having at least one extraction device claim 1 , for extraction of said amplified signal to said first determination device ...

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Номер записи: 63
02-04-2020 дата публикации

Methods and apparatus for an interface

Номер: US20200106644A1
Автор: Athar Ali Khan. P, Manish Kumar VISWKARMA
Принадлежит: Semiconductor Components Industries LLC

Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage, bi-directional channel redriver having a transmitter and a receiver that share input pads and output pads. The interface may provide for selective biasing of the transmitter and receiver using a switching circuit and a resistance circuit connected to the channel's input and output pads.

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Номер записи: 64
26-04-2018 дата публикации

ANALOG BEHAVIOR MODELING FOR 3-PHASE SIGNALING

Номер: US20180115637A1
Автор: Lee Chulkyu, Li Xiang, Midha Nakul, Radhakrishnan Varun
Принадлежит:

System, methods and apparatus are described that model analog behavior in a multi-wire, multi-phase communications link A digital signal representative of a physical connection in a communications link and a virtual signal characterizing a three-phase signal transmitted over the physical connection are generated. The virtual signal may be configured to model one or more analog characteristics of the physical connection. The analog characteristics may include voltage states defining the three-phase signal. The analog characteristics of the physical connection include at least three voltage states corresponding to signaling states of the three-phase signal. 1. An apparatus , comprising: a digital signal that represents logic states of the signal transmitted on the physical connection; and', 'a virtual signal that represents one or more analog characteristics of the physical connection, the analog characteristics including at least three valid voltage states, each voltage state corresponding to a voltage level associated with the physical connection,, 'at least one processing circuit configured to model a signal transmitted over a physical connection in a communication link, wherein the signal is modeled usingwherein the at least one processing circuit is configured to characterize the signal transmitted over the physical connection by the virtual signal selecting between at least three modes of operation of the physical connection, wherein the physical connection is in a high-impedance state or an undefined state when an inactive mode of operation is selected, andwherein the communication link carries a signal that has at least three phases.2. The apparatus of claim 1 , wherein three valid voltage states are defined for the signal.3. The apparatus of claim 2 , wherein one of the at least three valid voltage states is an undriven state claim 2 , wherein only one physical connection in the communication link is in the undriven state when the communication link is in an ...

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Номер записи: 65
27-04-2017 дата публикации

SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS

Номер: US20170117896A1
Автор: Whetsel Lee D.
Принадлежит:

First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. 1. An LVDS input circuit comprising:(a) a data input lead;(b) a first LVDS signal path;(c) a second LVDS signal path;(d) an inverter having an input connected to the data input lead and an inverting output;(e) an LVDS receiver having a non-inverting input connected to the first LVDS signal path, an inverting input connected to the second LVDS signal path, and an output; (i) a first comparator having a non-inverting input connected to the first LVDS signal path, an inverting input connected to the second LVDS signal path, and an output;', '(ii) a second comparator having a non-inverting input connected to the second LVDS signal path, an inverting input connected to the first LVDS signal path, and an output;', '(iii) an OR gate having one input connected to the output of the first comparator, another input connected to the output of the second comparator, and an output; and, '(f) window comparator circuitry including(g) a multiplexer having one input connected to the inverting output of the inverter, another input connected to the output of the LVDS receiver, a control input connected to the output of the window comparator, and an output.2. The LVDS input circuit of including an LVDS driver having a non-inverting output connected to the first LVDS signal path claim 1 , ...

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Номер записи: 66
05-05-2016 дата публикации

N-Wire Two-Level Digital Interface

Номер: US20160127158A1
Автор: Koli Kimmo
Принадлежит:

A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node. 1. A receiver for an N-wire digital interface , where N is any integer exceeding two , the receiver comprising:N input terminals;a common node; and a resistive element coupled between the common node and one of the N input terminals, respectively, and', 'a comparator having a first input coupled to the one of the N input terminals, a second input coupled to the common node,, 'N detection stages, each of the N detection stages includingwherein the resistive element of each of the detection stages has substantially a same resistance value.2. The receiver as claimed in claim 1 , further comprising:a decoder coupled to comparator outputs of the N detection stages and configured to determine a received symbol dependent on states of the comparator outputs.3. The receiver as claimed in claim 2 , wherein the decoder comprises a first look-up table for mapping the states of the comparator outputs to the received symbol.4. The receiver as claimed in claim 1 , wherein N is one of: three claim 1 , four and five.5. A signalling system comprising:a transmitter configured to generate N signalling voltages applied to wires of of an N-wire interface, respectively, each of the N signalling voltages being indicative of a different one of N bits to be transmitted, and having a value selected from two values; and a resistive element coupled between the common node and one of the N input terminals, respectively, and', 'a comparator having a first input coupled to the one of the N input terminals, a second input coupled to the common node,, 'a receiver having N input terminals, a ...

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Номер записи: 67
05-05-2016 дата публикации

Three-Wire Three-Level Digital Interface

Номер: US20160127159A1
Автор: Koli Kimmo
Принадлежит:

A receiver () for a three-wire digital interface, comprises a first resistive element (R) coupled between a first input terminal (A) and a first junction node (JA), a second resistive element (R) coupled between a second input terminal (B) and a second junction node (JB), and a third resistive element (R) coupled between a third input terminal (C) and a third junction node (JC). A network () comprising first second and third network terminals () is coupled to, respectively, first, second and third junction nodes (JA, JB, JC). The network has substantially the same impedance between all pairs of the first, second and third network terminals. A first comparator (C) has a non-inverting input () coupled to the first input terminal (A), an inverting input () coupled to the second junction node (JB), and an output () coupled to a first output terminal (AJ). A second comparator (C) has a non-inverting input () coupled to the AK first input terminal (A), an inverting input () coupled to the third junction node (JC), and an output () coupled to a second output terminal (AK). A third comparator (C) has a non-inverting input () coupled to the second input terminal (B), an inverting input () coupled to the third junction node (JC), and an output () coupled to a third output terminal (BJ). A fourth comparator (C) has a non-inverting input () coupled to the second input terminal (B), an inverting input () coupled to the first junction node (JA), and an output () coupled to a fourth output terminal (BK). A fifth comparator (C) has a non-inverting input (50) coupled to the third input terminal (C), an inverting input () coupled to the first junction node (JA), and an output () coupled to a fifth output terminal (CJ). A sixth comparator (C) has a non-inverting input () coupled to the third input terminal (C), an inverting input () coupled to the second junction node (JB), and an N output () coupled to a sixth output terminal (CK). 1. A receiver for a three-wire digital interface , ...

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Номер записи: 68
10-05-2018 дата публикации

RECEIVER TRAINING DURING A SATA OUT OF BAND SEQUENCE

Номер: US20180129627A1
Автор: Hildebrant Marc Stephen, Priborsky Anthony Leigh
Принадлежит:

Method and apparatus contemplating a storage device communicating with a host via a bus, the storage device comprising programming instructions stored in memory that are configured to transmit a training signal that is not a COMWAKE signal to the host in response to receiving a COMWAKE signal from the host, after transmitting the training signal to the host then to determine whether a training signal is received from the host within a predetermined time interval, and if the training signal is received from the host within the predetermined time interval then transmitting a COMWAKE signal to the host. 1. A storage device communicating with a host via a bus, the storage device comprising programming instructions stored in memory that are configured to transmit a training signal that is not a COMWAKE signal to the host in response to receiving a COMWAKE signal from the host, after transmitting the training signal to the host then to determine whether a training signal is received from the host within a predetermined time interval, and if the training signal is received from the host within the predetermined time interval then transmitting a COMWAKE signal to the host. The present application is a continuation of copending U.S. patent application Ser. No. 12/391,727 which issues as U.S. Pat. No. 9,753,887 on Sep. 5, 2017.The present embodiments relate to serial communications and more particularly but without limitation to controlling a transceiver in a serial link to perform with a desired physical layer quality during communication between devices connected via the serial link.Serial interfaces such as the Serial Advanced Technology Attachment (BATA) interface are used to connect data storage devices to a host device or host adapter. The data transfer rate of first-generation SATA (SATA-1) is 1.5 Gbps. Second and third generations cumulatively double that speed to 3 Gbps and 6 Gbps, respectively. SATA permits a first device to transmit data to a second device by ...

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Номер записи: 69
11-05-2017 дата публикации

METHOD AND DEVICE FOR RADIO FREQUENCY CONTROL OF MULTICHANNEL WIRELESS MODEM

Номер: US20170134195A1
Автор: Cheng Bo, HAN Wenlong
Принадлежит:

The present disclosure provides a method. and device for radio frequency control of a multichannel wireless modem. The multichannel wireless modem includes N wireless modems, and the method includes: sorting the N wireless modems; acquiring a registering frequency of the 1st wireless modem; for the nth wireless modem, calculating an interfering frequency of the nth wireless modem according to registering frequencies of the 1st to the (n−1)th wireless modems, and registering according to a frequency retrieved by the nth wireless modem to obtain the registering frequency of the nth wireless modem, wherein the registering frequency does not fall into frequency scope of the interfering frequency; starting to execute the step from n=2 and finishing till n=N. The present disclosure achieves that the registering frequencies of the N wireless modems are different, thus avoids co-channel interference and frequency doubling interference and improves sensitivity and transmission rate of the multichannel wireless modem. 1. A method for radio frequency control of a multichannel wireless modem , wherein said multichannel wireless modem comprises N wireless modems , and said method comprises:sorting the N wireless modems;acquiring a registering frequency of the 1st wireless modem; andfor the nth wireless modem, calculating an interfering frequency of the nth wireless modem according to registering frequencies of the 1st to the (n−1)th wireless modems, and registering according to a frequency retrieved by the nth wireless modem to obtain a registering frequency of the nth wireless modem, wherein said registering frequency does not fall into a frequency scope of said interfering frequency; starting to execute the step from n=2 and finishing till n=N.2. The method according to claim 1 , wherein said calculating an interfering frequency of the nth wireless modem according to registering frequencies of the 1st to the (n−1)th wireless modems further comprises:using an interfering ...

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Номер записи: 70
23-04-2020 дата публикации

TRANSMISSION DEVICE, RECEPTION DEVICE, COMMUNICATION SYSTEM, SIGNAL TRANSMISSION METHOD, SIGNAL RECEPTION METHOD, AND COMMUNICATION METHOD

Номер: US20200127805A1
Автор: Hayashi Hiroaki, Koshisaka Naohiro, MATSUMOTO Hideyuki, Takahashi Hiroo
Принадлежит:

A transmission device of the disclosure includes: a clock signal transmitting circuit that outputs a clock signal onto a clock signal line; a data signal transmitting circuit that outputs a data signal onto a data signal line; and a blanking controller that controls the clock signal transmitting circuit to output a predetermined blanking signal, in place of the clock signal, from the clock signal transmitting circuit to the clock signal line in synchronization with a blanking period of the data signal. 1. (canceled)2. A transmission device comprising:a clock signal transmitting circuit configured to output a clock signal onto a clock signal line;a data signal transmitting circuit configured to output a data signal onto a data signal line; anda transmission switching circuit configured to switch the clock signal transmitting circuit and the data signal transmitting circuit between a high speed differential signal mode and a low power signal mode.3. The transmission device according to claim 2 , wherein the clock signal transmitting circuit includes:a selector configured to output a selection signal;a parallel/serial conversion circuit configured to receive the selection signal and output a control signal; anda high speed driver configured to receive the control signal and, in a case where the clock signal transmitting circuit is in the high speed differential signal mode, to output the clock signal onto the clock line.4. The transmission device according to claim 3 , wherein the clock signal transmitting circuit includes a clock divider.5. The transmission device according to claim 3 , wherein the selection signal is one of a toggle signal claim 3 , a first predetermined signal claim 3 , or a second predetermined signal.6. The transmission device according to claim 2 , wherein the data signal transmitting circuit includes:a selector configured to output a selection signal;a parallel/serial conversion circuit configured to receive the selection signal and output a ...

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Номер записи: 71
28-05-2015 дата публикации

METHODS AND APPARATUS TO REDUCE SIGNALING POWER

Номер: US20150146816A1
Автор: Hollis Timothy Mowry
Принадлежит: QUALCOMM INCORPORATED

System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state. 1. A data communications method , comprising:determining a first fraction corresponding to a proportion of primary bits of a plurality of input data symbols that are in a first logic state and a second fraction corresponding to a proportion of secondary bits of the plurality of input data symbols that are in the first logic state, wherein more power is required to transmit a primary bit in the first logic state than to transmit a secondary bit in the first logic state;generating transmission symbols from the plurality of input data symbols, wherein primary bits of the transmission symbols are derived from the secondary bits of the plurality of input data symbols and secondary bits of the transmission symbols are derived from the primary bits of the plurality of input data symbols when the second fraction is greater than a half and greater than the first fraction; andproviding the transmission symbols to one or more multi-state encoders configured to encode the transmission symbols as multi-level transmission symbols for transmission on a communications link.2. The method of claim 1 , wherein generating transmission symbols from the plurality of input data symbols includes:inverting the primary bits of the input data symbols when the first ...

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Номер записи: 72
09-05-2019 дата публикации

Baseline wander correction

Номер: US20190140768A1
Автор: Reza Navid
Принадлежит: RAMBUS INC

A receiver frontend having a high-frequency AC-coupled path in parallel to a low-frequency feed-forward path for baseline correction. The low-frequency path blocks the DC common-mode voltage of the input differential signal pair, but passes low-frequency differential signal components (e.g., long strings of a single value, or disparities in the number of 1's and 0's over a long period of time.) The low-frequency path can include a passive network for level shifting and extending the range of acceptable common-mode input voltages. The low-frequency path can also include a differential (e.g., transconductance) amplifier to isolate the common-mode input voltage from the output of the baseline wander correction circuit.

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Номер записи: 73
11-06-2015 дата публикации

METHODS AND APPARATUS FOR SIGNALING ON A DIFFERENTIAL LINK

Номер: US20150163075A1
Автор: Schoenborn Zale T.
Принадлежит:

Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link. 112-. (canceled)13. A processor device comprising: enter a low power state;', 'send a differential signal to the other device over a differential, point-to-point serial data link for at least a predetermined length of time to initiate a transition from the low power state to a data transmitting state; and', 'transmit data to the other device within the data transmitting state., 'an interface to couple the processor device to another device, wherein the interface comprises interface logic, implemented at least in part in hardware, to14. The processor device of claim 13 , wherein the differential signal comprises an in-band signal.15. The processor device of claim 13 , wherein transmission of the data comprises a high speed data transmission.16. The processor device of claim 15 , wherein the data is to be transmitted at at least 2.5 Gbit per second.17. The processor device of claim 13 , wherein the interface logic comprises transmitter logic.18. The processor device of claim 17 , wherein the interface logic further comprises receiver logic.19. The processor device of claim 13 , wherein the low power state comprises a non-zero power state.20. The processor device of claim 19 , wherein power is to be applied to the processor device during the low power state.21. The processor device of claim 13 , wherein the differential signal is to comprise a constant voltage signal over the duration of time.22. The processor device of claim 21 , wherein the differential signal is to comprise a direct current (DC) signal of a threshold voltage.23. The processor device of claim 13 , wherein the link is to support a serial data link protocol.24. The processor device of claim 23 , wherein the link protocol comprises a general purpose input/output interconnect protocol.25. The processor device of claim 13 , wherein the duration ...

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Номер записи: 74
11-09-2014 дата публикации

HIGH-FREQUENCY SWITCH

Номер: US20140253260A1
Автор: Horimoto Yasuhiro, Masuda Takahiro, Morihara Daisuke
Принадлежит: Omron Corporation

A high-frequency switch configured to transmit differential signals including first and second signals, has first and second switches each comprising an input terminal configured to receive a signal and two output terminals configured to output the signal, and a substrate comprising a first surface mounted with the first and second switches. The input terminal is arranged between the two output terminals. The first and second switches are arranged on the substrate along a direction intersecting with a direction in which the input terminal and the two output terminals are placed side by side. One terminal of the first switch and one terminal of the second switch are placed side by side along the direction in which the first and second switches are arranged.

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Номер записи: 75
11-09-2014 дата публикации

Methods and Systems for High Bandwidth Chip-to-Chip Communications Interface

Номер: US20140254642A1
Автор: FOX JOHN, Holden Brian, Hormati Ali, Hunt Peter, Keay John D., Shokrollahi Amin, Simpson Richard, Singh Anant, Stewart Andrew Kevin John, Surace Giuseppe, Ulrich Roger
Принадлежит: Kandou Labs, SA

Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

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Номер записи: 76
18-09-2014 дата публикации

ELEMENTS TO COUNTER TRANSMITTER CIRCUIT PERFORMANCE LIMITATIONS

Номер: US20140266302A1
Автор: Agrawal Vinayak, Ramapuram Deepak, Sharma Namrta
Принадлежит:

Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit. 1. An apparatus for driving data on a differential channel including a first output terminal and a second output terminal , the apparatus comprising:a differential driver circuit; anda first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver;wherein each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit;wherein each sub-pre-driver circuit may output a logic ‘0’, a logic ‘1’, or a high-impedance state;wherein one or more of the sub-pre-driver circuits are operable to enter into the high-impedance state before a start of data communication and are prohibited from entering into the high-impedance state during data communication;wherein each sub-pre-driver circuit that is not in the high-impedance state outputs logic ‘1’ when the associated pre-driver is driving a logic ‘1’ and outputs logic ‘0’ when the ...

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Номер записи: 77
18-09-2014 дата публикации

POWER LINE COMMUNICATION SYSTEM

Номер: US20140269953A1
Автор: Borisov Vladimir, Chiummiento Philippe
Принадлежит: ITRON, INC.

A disclosed PLC system includes a PLC modem electrically connected to a transmission medium that transmits or carries medium or high voltage without electrical isolation. The PLC system further includes a voltage divider that draws power from the transmission medium to the PLC modem, thereby eliminating a need of a separate power source for operating the PLC modem. Since the PLC modem is electrically connected to the transmission, the PLC modem or communication connections of the PLC modem may be located at a same potential level as the transmission medium and thus the PLC modem does not see a surge during a surge event occurs in the transmission medium. Therefore, the disclosed PLC system eliminates the use of a line coupler and a surge protection component for providing high-voltage isolation and surge protection to the PLC modem. 1. A system comprising:a power line communication (PLC) modem electrically connected to a transmission medium configured to transmit a medium or high voltage,wherein the PLC modem is electrically connected to the transmission medium without a line coupler.2. The system as recited in claim 1 , wherein the PLC modem is electrically connected to the transmission medium without electrical isolation between the PLC modem and the transmission medium.3. The system as recited in claim 1 , wherein the PLC modem is ungrounded and is allowed to float at a voltage of the transmission medium.4. The system as recited in claim 1 , further comprising a voltage divider that delivers DC (direct current) power to the PLC modem.5. The system as recited in claim 4 , wherein the voltage divider comprises an AC/DC (alternating current/direct current) voltage divider claim 4 , a solid state distribution transformer claim 4 , a solid state power supply claim 4 , an offline power supply or a magnetic harvester.6. The system as recited in claim 5 , wherein the voltage divider draws medium or high voltage AC power from the transmission medium and delivers DC power ...

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Номер записи: 78
18-09-2014 дата публикации

Signal level decision device and method

Номер: US20140269974A1
Автор: CHUANG Sheng-Fu, Ho Hsuan-Ting, Huang Liang-Wei, SU Ching-Yao
Принадлежит: REALTEK SEMICONDUCTOR CORPORATION

The present invention discloses a signal level decision device to determine the level of a source signal. Said source signal comprises a plurality of source messages along a time axis; each source message corresponds to one of a plurality of normal levels; and each normal level is equivalent to at least one of a plurality of extension levels. The signal decision device comprises: a storage circuit to store the level information of the normal level(s) and the equivalent extension level(s) thereof in connection with some or all of the source messages; a transition parameter calculation circuit to calculate a plurality of transition parameters of the normal level and its equivalent extension level(s) in connection with each of the source messages according to the level information; and a decision circuit to determine the level of each of the source messages according to the plurality of transition parameters. 1. A signal level decision device to determine the level of a source signal which includes a plurality of source messages along a time axis while each source message corresponds to one of a plurality of normal levels and each of the normal levels is equivalent to at least one of a plurality of extension levels , comprising:a storage circuit to store the level information of the normal level(s) and the equivalent extension level(s) thereof in connection with some or all of the source messages;a transition parameter calculation circuit to calculate a plurality of transition parameters of the normal level and its equivalent extension level(s) in connection with each of the source messages according to the level information; anda decision circuit to determine the level of each of the source messages according to the plurality of transition parameters.2. The signal level decision device of claim 1 , wherein the number of the extension levels is 2 or more times the number of the normal levels (2M+1) while the M is a positive integer.3. The signal level decision device ...

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Номер записи: 79
08-07-2021 дата публикации

TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEIVING DEVICE, AND RECEIVING METHOD

Номер: US20210209053A1
Автор: Morita Hiroshi, TOBA Kazuaki, Yamamoto Kazuo, Yamamoto Masanari
Принадлежит:

To enable preferable signal transmission between a plurality of daisy-chained devices at low cost. A transmission device generates a plurality of signals having different voltage levels and outputs the signals to a communication line at different timings. For example, the plurality of signals having different voltage levels is generated by a plurality of drivers or one driver. A receiving side can immediately determine whether or not it is information to be passed to the subsequent stage on the basis of only a difference in voltage level without logically analyzing contents of a signal, and cost of components such as a memory, verification cost, or the like are unnecessary so that the cost can be reduced. 1. A transmission device comprising:a signal generation unit that generates a plurality of signals having different voltage levels; anda signal transmission unit that outputs the plurality of signals having different voltage levels to a communication line at different timings.2. The transmission device according to claim 1 ,wherein the signal generation unit generates the plurality of signals having different voltage levels by a plurality of drivers.3. The transmission device according to claim 1 ,wherein the signal generation unit generates the plurality of signals having different voltage levels by one driver.4. The transmission device according to claim 1 ,wherein the signal generation unit generates the plurality of signals having different voltage levels by current driving.5. The transmission device according to according to claim 1 ,further comprising a determination unit that determines whether or not the communication line is connected to a receiving device corresponding to the plurality of signals having different voltage levels.6. The transmission device according to claim 5 ,wherein the determination unit makes determination on a basis of a voltage level of the communication line when a predetermined current is drawn from the communication line.7. The ...

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Номер записи: 80
16-07-2015 дата публикации

DIFFERENTIAL SIGNAL TRANSMITTERS

Номер: US20150200791A1
Автор: HUANG Chun-Che
Принадлежит: VIA TECHNOLOGIES, INC.

A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state. 1. A differential signal transmitter circuit , comprising:an output driver circuit, configured to transmit a pair of differential signals according to a supply power; anda leakage current preventing circuit, coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.2. The differential signal transmitter circuit as claimed in claim 1 , wherein the leakage current preventing circuit comprises:a first switching element, coupled between the supply power and the output driver circuit;a second switching element, coupled to the first switching element at a connection node and a ground node; anda resistor, coupled between the output driver circuit and the connection node.3. The differential signal transmitter circuit as claimed in claim 2 , wherein the first switching element is a transistor comprising a first electrode coupled to the supply power claim 2 , a second electrode coupled to the output driver circuit and a control electrode coupled to the connection node claim 2 , and the second switching element is a transistor comprising a first electrode coupled to the ground node claim 2 , a second electrode coupled to the connection node and a control electrode coupled to a power signal claim 2 , wherein the power signal has a high voltage level in the power on state and a low voltage level in the power off state.4. The differential signal transmitter circuit as ...

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Номер записи: 81
06-07-2017 дата публикации

Passive Equalizers for Directional Couplers

Номер: US20170195146A1
Автор: Greene Jake, Solomko Valentyn
Принадлежит:

In accordance with an embodiment, a device includes a directional coupler having an input port, a transmitted port, a coupled port and an isolated port. The device also includes a first passive equalizer having a first terminal coupled to a first one of a coupled port and an isolated port of the directional coupler. The first passive equalizer includes a resonator having a first inductor and a first capacitor, the resonator coupled between the first terminal and a second terminal of the first passive equalizer. The first passive equalizer also includes a first resistor and a second resistor serially connected between the first and the second terminals of the first passive equalizer, the first resistor connected to the second resistor at a first node. The first equalizer further includes a shunt network coupled between a reference terminal and the first node. 1. A device comprising:a directional coupler having an input port, a transmitted port, a coupled port and an isolated port; and a resonator comprising a first inductor and a first capacitor, the resonator coupled between the first terminal and a second terminal of the first passive equalizer;', 'a first resistor and a second resistor serially connected between the first and the second terminals of the first passive equalizer, the first resistor connected to the second resistor at a first node; and', 'a shunt network coupled between a reference terminal and the first node., 'a first passive equalizer having a first terminal coupled to a first one of the coupled port or the isolated port of the directional coupler, the first passive equalizer comprising2. The device of claim 1 , further comprising a termination load coupled to a second one of the coupled port or the isolated port of the directional coupler.3. The device of claim 1 , further comprising a second passive equalizer coupled to a second one of the coupled port or the isolated port of the directional coupler.4. The device of claim 1 , further comprising ...

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Номер записи: 82
20-06-2019 дата публикации

RINGING SUPPRESSION CIRCUIT AND RINGING SUPPRESSION METHOD

Номер: US20190190516A1
Автор: HONDA Takuya, ISOMURA Hirofumi, Kishigami Tomohisa, Mori Hiroyuki
Принадлежит:

A ringing suppression circuit connected to a transmission line to suppress ringing caused by the transmission line transmitting a differential signal using a pair of signal lines, the differential signal varying between a high level and a low level, the pair of signal lines including a high potential signal line and a low potential signal line, the ringing suppression circuit including: an inter-line switching element that is connected between the pair of signal lines; a control portion that performs a ringing suppression operation in response to detecting a level change in the differential signal, wherein the ringing suppression operation turns on the inter-line switching element to decrease an impedance between the pair of signal lines; and a suppression operation prohibiting portion that prohibits the control portion from performing the ringing suppression operation in response to detecting a signal caused by a signal on the transmission line. 1. A ringing suppression circuit connected to a transmission line to suppress ringing caused by the transmission line transmitting a differential signal using a pair of signal lines , the differential signal varying between a high level and a low level , the pair of signal lines including a high potential signal line and a low potential signal line , the ringing suppression circuit comprising:an inter-line switching element that is connected between the pair of signal lines;a control portion that performs a ringing suppression operation in response to detecting a level change in the differential signal, wherein the ringing suppression operation turns on the inter-line switching element to decrease an impedance between the pair of signal lines; anda suppression operation prohibiting portion that prohibits the control portion from performing the ringing suppression operation in response to detecting a signal caused by a signal on the transmission line.2. The ringing suppression circuit according to claim 1 , whereinthe signal ...

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Номер записи: 83
29-07-2021 дата публикации

POSTAMBLE FOR MULTI-LEVEL SIGNAL MODULATION

Номер: US20210234732A1
Автор: Brox Martin, DIETRICH Stefan, Hein Thomas, Jovanovic Natalija, Richter Michael Dieter, Schneider Ronny
Принадлежит:

Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided. 1. A method , comprising:generating, at a first device, a first signal modulated using a modulation scheme having more than two levels for transmission to a second device over a channel, wherein the channel is terminated to a first level;generating a second signal comprising a level that is between the first level and one or more of the more than two levels based at least in part on generating the first signal; andtransmitting the first signal and the second signal to the second device over the channel.2. The method of claim 1 , further comprising:generating, at the first device, a third signal comprising the first level; andtransmitting the third signal after transmitting the second signal.3. The method of claim 2 , further comprising:releasing the channel after transmitting the third signal.4. The method of claim 1 , further comprising:transmitting the second signal to the second device for at least one symbol period after transmitting the first signal.5. The method of claim 1 , wherein the modulation scheme comprises the first level claim 1 , a second level claim 1 , a third level claim 1 , and a fourth level claim 1 , and wherein the first level comprises a highest level and the ...

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Номер записи: 84
28-07-2016 дата публикации

TRANSITION ENFORCING CODING RECEIVER FOR SAMPLING VECTOR SIGNALS WITHOUT USING CLOCK AND DATA RECOVERY

Номер: US20160218723A1
Автор: CHANG CHING-HSIANG
Принадлежит:

A transition enforcing coding (TEC) receiver includes a first delay line circuit, a transition detection circuit, and a data sampling circuit. The first delay line circuit delays a plurality of vector signals to generate a plurality of delayed vector signals, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing determined based on an output of the transition detection circuit. 1. A transition enforcing coding (TEC) receiver comprising:a first delay line circuit, arranged to delay a plurality of vector signals to generate a plurality of delayed vector signals, respectively;a transition detection circuit, arranged to detect a transition of at least one specific delayed vector signal among the delayed vector signals; anda data sampling circuit, arranged to sample the vector signals according to a sampling timing determined based on an output of the transition detection circuit.2. The TEC receiver of claim 1 , wherein the TEC receiver determines the sampling timing without using clock and data recovery (CDR).3. The TEC receiver of claim 1 , wherein the transition of the at least one specific delayed vector signal is a last transition detected between adjacent states of the delayed vector signals.4. The TEC receiver of claim 1 , further comprising:a second delay line circuit, arranged to generate a delayed signal according to the output of the transition detection circuit;wherein the sampling timing is determined based on the delayed signal.5. The TEC receiver of claim 4 , wherein the first delay line circuit is arranged to act as a de-skew circuit.6. The TEC receiver of claim 4 , further comprising:a frequency divider, arranged to perform frequency division upon the output of the transition detection circuit to generate a clock signal to the second delay line circuit; a plurality of first data ...

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Номер записи: 85
28-07-2016 дата публикации

DIRECT DIGITAL SEQUENCE DETECTOR AND EQUALIZER BASED ON ANALOG-TO-SEQUENCE CONVERSION

Номер: US20160218897A1
Автор: Hossain Masum, Mohammad Maruf H.
Принадлежит: 9011579 Canada Incorporée

Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages. 1. An integrated circuit (IC) , comprising:a sample-and-hold circuit to sample an input signal based on a clock signal, and to output a sampled voltage for at least a holding period, wherein the input signal is received over a communication channel;a plurality of adjustable comparators, wherein each adjustable comparator has a respective reference voltage that is adjustable, wherein each adjustable comparator outputs a result signal based on comparing the sampled voltage with the adjustable comparator's reference voltage, wherein reference voltages for the plurality of adjustable comparators are computed based on a main cursor and at least one pre-cursor associated with the communication channel, and wherein each generated reference voltage corresponds to a particular sequence of symbols; anda sequence-selection circuit to select a sequence of symbols based on the result signals outputted by the plurality of adjustable comparators.2. The IC of claim 1 , wherein each symbol in the sequence of symbols is transmitted by a transmitter at successive time instances claim 1 , and wherein the sequence of symbols is selected based on the sampled voltage that is sampled at a single time instance.3. The IC of claim 1 , wherein the sequence-selection circuit comprises:{'sup': 'M', 'a sequence generation circuit to generate a set of 2possible sequences based on the ...

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Номер записи: 86
06-08-2015 дата публикации

Method for Code Evaluation Using ISI Ratio

Номер: US20150222458A1
Автор: Hormati Ali, Shokrollahi Amin, Ulrich Roger
Принадлежит:

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity. 1. A method comprising:receiving a set of information bits;generating a reduced-alphabet codeword vector with an encoder by forming a weighted sum of sub-channel code vectors wherein a weighting of each sub-channel code vector is based in part on a corresponding antipodal weight determined by a corresponding information bit in the set of received bits, and wherein the sub-channel code vectors form a reduced-alphabet weight matrix, and are mutually orthogonal and orthogonal to a common mode vector; and,transmitting the reduced-alphabet codeword vector using a plurality of line drivers, wherein the reduced-alphabet codeword vector comprises a plurality of reduced-alphabet codeword vector elements, and each reduced-alphabet codeword vector element is transmitted on a wire of a multi-wire communication bus by a respective one of the plurality of line drivers.2. The method of wherein the encoder is an orthogonal encoding logic circuit claim 1 , and wherein generating a reduced-alphabet codeword vector comprises mapping the received set of information bits to a respective reduced-alphabet codeword vector and outputting a reduced-alphabet codeword vector selector signal.3. The method of wherein the reduced-alphabet codeword vector selector signal is provided to the plurality of line drivers claim 2 , and wherein each line driver of the plurality of line drivers uses a portion of the reduced-alphabet codeword vector selector signal to output a corresponding a current or voltage representing the reduced-alphabet codeword vector element.4. The method of wherein at least one ...

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Номер записи: 87
02-08-2018 дата публикации

DATA TRANSMISSION DEVICE FOR MODULATING AMPLITUDE OF PAM-4 SIGNAL USING TOGGLE SERIALIZER AND METHOD OF OPERATING THE SAME

Номер: US20180219706A1
Автор: CHOI Woo Young, Kwon Dae Hyun
Принадлежит: Industry-Academic Cooperation Foundation, Yonsei University

Disclosed are a data transmission device for modulating the amplitude of a PAM-4 signal using a toggle serializer and a method of operating the same. In accordance with an embodiment of the present disclosure, the data transmission device includes a toggle serializer configured to generate at least one toggle signal by detecting logic level change of first and second signals from a Pulse Amplitude Modulation (PAM) signal including the first and second signals; and a driver configured to modulate an amplitude of the PAM signal by combining the first signal, the second signal, and the at least one toggle signal. 1. A data transmission device , comprising:a toggle serializer configured to generate at least one toggle signal by detecting logic level change of first and second signals from a Pulse Amplitude Modulation (PAM) signal comprising the first and second signals; anda driver configured to modulate an amplitude of the PAM signal by combining the first signal, the second signal, and the at least one toggle signal.2. The data transmission device according to claim 1 , wherein the toggle serializer generates a first toggle signal of the at least one toggle signal when a logic level of the first signal rises claim 1 , generates a second toggle signal of the at least one toggle signal when the logic level of the first signal falls claim 1 , generates a third toggle signal of the at least one toggle signal when a logic level of the second signal rises claim 1 , and generates a fourth toggle signal of the at least one toggle signal when the logic level of the second signal falls.3. The data transmission device according to claim 2 , wherein the first signal comprises a Most Significant Byte (MSB) signal claim 2 , and the second signal comprises a Least Significant Byte (LSB) signal.4. The data transmission device according to claim 3 , wherein the first toggle signal comprises a toggle-rising signal related to the MSB signal claim 3 ,the second toggle signal comprises a ...

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Номер записи: 88
23-10-2014 дата публикации

MISMATCHED DIFFERENTIAL CIRCUIT

Номер: US20140314171A1
Автор: Amirkhany Amir, Hekmat Mohammad
Принадлежит: Samsung Display Co., Ltd.

A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator. 1. A differential amplifier comprising:a first amplifier leg comprising a first transistor; anda second amplifier leg comprising a second transistor,wherein the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor.2. The differential amplifier of claim 1 ,wherein the differential amplifier is configured to be at an input stage of a comparator,wherein the first amplifier leg and the second amplifier leg, together, are configured to differentially amplify a received differential input signal,wherein the differential amplifier is configured to have an input offset voltage, andwherein the input offset voltage corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor.3. The differential amplifier of claim 2 ,wherein the first transistor has a first device size and the second transistor has a second device size different from the first device size, andwherein the input offset voltage further corresponds to the difference between the first device size and the second device size.4. The differential amplifier of claim 3 , wherein the first device size corresponds to a channel width or length of the first transistor and the second device size corresponds to a ...

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Номер записи: 89
11-07-2019 дата публикации

MULTIDROP DATA TRANSFER

Номер: US20190215195A1
Автор: Hormati Ali, Shokrollahi Amin
Принадлежит:

Multi-drop communications channels can have significantly deep notches in their frequency response causing a corresponding limitation of the effective data transmission rate. A special time-ordered coding method is described which results in the emitted spectrum of the data stream transmitted into the channel having a notch at the same frequency as the notch in the channel frequency response, permitting channel receivers to successfully decode the transmitted data stream. The described coding method may be applied at various multiples of the channel notch frequency to support different throughput rates, and may be combined with other coding techniques such as group or vector signaling codes. 1. A method comprising:{'sub': 'notch', 'receiving a plurality of symbols, each symbol of the plurality of symbols received via a respective wire of a multi-wire bus, the plurality of symbols comprising channel-induced superpositions of symbols of a first transmitted codeword with corresponding symbols of a second transmitted codeword, the first and second transmitted codewords sent at a rate that is an even integer multiple of a notch frequency fassociated with the multi-wire bus; and'}decoding the plurality of symbols to form a set of output bits.2. The method of claim 1 , wherein the symbols of the first transmitted codeword are quiescent values.3. The method of claim 1 , wherein the symbols of the first transmitted codeword are a replicated copy of the symbols of the second transmitted codeword.4. The method of claim 1 , wherein the symbols of the first transmitted codeword are an inverted copy of the symbols of the second transmitted codeword.5. The method of claim 1 , wherein decoding the plurality of symbols comprises forming a set of corrected symbols according to a previously-determined set of output symbols claim 1 , the previously-determined set of output symbols representative of the symbols of the first transmitted codeword.6. The method of claim 5 , wherein forming ...

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Номер записи: 90
02-07-2020 дата публикации

HIGH SPEED RECEIVER

Номер: US20200213165A1
Автор: IYER Arvindh, JEONG Jaehun, Kocaman Namik, Singh Ullas, THASARI Kumar, ZHANG BO, Zhang Heng
Принадлежит:

Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal. 13-. (canceled)4. An apparatus comprising:a first set of slicers comprising input ports to receive a first input signal, the first set of slicers configured to generate a first slicer output signal comprising outputs of the first set of slicers, the first slicer output signal digitally indicating a level of the first input signal; a first set of multiplexers comprising input ports coupled to output ports of the first set of slicers, and', 'a first set of latches comprising input ports coupled to output ports of the first set of multiplexers;, 'a first speculative tap comprising input ports coupled to output ports of the first set of slicers, the first speculative tap configured to select outputs of a subset of the first set of slicers based on a second slicer output signal, wherein the first speculative tap comprisesa first decoder comprising input ports coupled to output ports of the first speculative tap, the first decoder configured to decode the selected outputs of the subset of the first set of slicers in a first digital representation into a second digital representation; input ports ...

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Номер записи: 91
27-08-2015 дата публикации

Circuitry and Method for Multi-Level Signals

Номер: US20150244547A1
Автор: De Keulenaer Timothy, DE PEUTER Geert, LI ZHISHENG, Sinsky Jeffrey, Torfs Guy
Принадлежит:

Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n−1) different reference values, and having N sets of (n−1) output terminals for outputting N sets of (n−1) output signals indicating whether the value of the multi-level signal is below or above the (n−1) reference values. The circuitry also includes N sets of (n−1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n−1) sample-and-hold circuits for generating at least one binary signal having a period N*T. 1. Circuitry for converting a multi-level signal into at least one binary signal , the multi-level signal having a period T and comprising n signal levels , n being equal to or greater than 3 , comprising:comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n−1) different reference values, and having N sets of (n−1) output terminals for outputting N sets of (n−1) output signals, each set of (n−1) output signals indicating whether the value of the multi-level signal is below or above the (n−1) reference values, wherein N is greater than or equal to 2;N sets of (n−1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, each set of the N sets being arranged for sampling-and-holding at moments in time that are shifted in time with respect to another set of the N sets, wherein each output terminal of a set of the N sets of (n−1) output terminals is connected to the input of a sample-and-hold circuit of a corresponding set of the N sets of (n−1) sample-and-hold circuits; andlogical circuitry ...

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Номер записи: 92
26-08-2021 дата публикации

OPERATION METHOD AND RECEIVER DEVICE

Номер: US20210266035A1
Автор: HSU Chi-Sheng, MAO Sung-Yen
Принадлежит:

An operation method is implemented by a receiver device. The operation method includes following steps: detecting a signal on a transmission line; performing a channel estimation to acquire a length of the transmission line; comparing the length with at least one length threshold value to generate a comparison result; and adjusting a depth of a FIFO process according to the comparison result. 1. An operation method implemented by a receiver device , wherein the operation method comprises:detecting a signal on a transmission line;performing a channel estimation to acquire a length of the transmission line;comparing the length with at least one length threshold value to generate a comparison result; andadjusting a depth of a first-in-first-out (FIFO) process according to the comparison result.2. The operation method of claim 1 , further comprising:performing an initialization process to preset the depth as a maximum depth.3. The operation method of claim 1 , wherein adjusting the depth of the FIFO process comprises:reducing the depth if the length of the transmission line is shorter than the at least one length threshold value.4. The operation method of claim 1 , wherein detecting the signal on the transmission line comprises:detecting signal energy on the transmission line;determining whether the signal energy is greater than an energy threshold value; andperforming the channel estimation if the signal energy is greater than the energy threshold value.5. The operation method of claim 4 , further comprising:continuing to detect the signal energy on the transmission line if the signal energy is lower than or equal to the energy threshold value.6. The operation method of claim 1 , wherein the transmission line is applied to an Ethernet system.7. A receiver device claim 1 , comprising:a decoder circuit;a first storage circuit configured to receive first input data and perform a FIFO process;a first equalizer coupled to the first storage circuit and the decoder circuit;a ...

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Номер записи: 93
26-08-2021 дата публикации

DIGITAL ISOLATOR

Номер: US20210266199A1
Автор: Oda Tatsuhiro, OHGURO Tatsuya, Ootsuka Kenichi
Принадлежит:

According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion. 1. A digital isolator , comprising:a first member including a metal and being electrically conductive;a second member separated from the first member, the second member including the metal and being electrically conductive; andan insulating layer provided on the first member and the second member, the insulating layer including silicon, carbon, and nitrogen.2. The isolator according to claim 1 , further comprising:an insulating portion provided between the first member and the second member;a first electrically conductive portion provided between the first member and the insulating portion, the first electrically conductive portion including tantalum; anda second electrically conductive portion provided between the second member and the insulating portion, the second electrically conductive portion including tantalum.3. The isolator according to claim 1 , further comprising a circuit electrically connected to the first member. This application is a continuation of application Ser. No. 16/815,419 filed Mar. 11, 2020 and is based upon and claims the benefit of priority from Japanese Patent ...

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Номер записи: 94
13-11-2014 дата публикации

CLOCK EMBEDDED OR SOURCE SYNCHRONOUS SEMICONDUCTOR TRANSMITTING AND RECEIVING APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING SAME

Номер: US20140334583A1
Автор: Lee Kyongsu
Принадлежит:

The present invention relates to a clock-embedded or source synchronous semiconductor transmitting and receiving apparatus and to a semiconductor system including same. The semiconductor apparatus according to one embodiment of the present invention includes: a data providing unit for providing differential data; a multi-phase clock generator for generating a first clock signal provided to the data providing unit, and a second clock signal having a different phase from the first clock signal; and a combining unit for receiving the differential data and the second clock signal and combining same to generate a combined signal, wherein the second clock signal is a single clock signal and has n (here, n is an integer of two or greater) times a symbol period of the differential data, the first and second clock signals have a 90 degree phase difference, and the combination signal is transmitted to the outside through differential transmission lines. 1. A semiconductor device , comprising:a data providing unit for providing differential data;a multi-phase clock generation unit for generating a first clock signal provided to the data providing unit and a second clock signal having a different phase from the first clock signal; anda signal combination unit for receiving the differential data and the second clock signal and generating a combination signal by combining the differential data and the second clock signal,wherein the second clock signal is a single clock signal and has n times a symbol period of the differential data (n is an integer of 2 or more), the first clock signal and the second clock signal has a difference in phases of 90 degrees, the second clock signal is combined with the differential data in common, the combination signal is a differential signal and has a cross-point voltage level, the cross-point voltage level varies depending on a level of the second clock signal, and the combination signal is externally transmitted through differential ...

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Номер записи: 95
23-08-2018 дата публикации

Multidrop data transfer

Номер: US20180241589A1
Автор: Ali Hormati, Amin Shokrollahi
Принадлежит: Kandou Labs SA

Multi-drop communications channels can have significantly deep notches in their frequency response causing a corresponding limitation of the effective data transmission rate. A special time-ordered coding method is described which results in the emitted spectrum of the data stream transmitted into the channel having a notch at the same frequency as the notch in the channel frequency response, permitting channel receivers to successfully decode the transmitted data stream. The described coding method may be applied at various multiples of the channel notch frequency to support different throughput rates, and may be combined with other coding techniques such as group or vector signaling codes.

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Номер записи: 96
08-08-2019 дата публикации

SIGNAL OUTPUT CIRCUIT, TRANSMISSION CIRCUIT AND INTEGRATED CIRCUIT

Номер: US20190245721A1
Автор: HIRAMATSU Taku, KAWAI Shigeaki
Принадлежит:

A signal output circuit includes: a driver circuit including a variable current source and configured to output a multilevel signal; a replica circuit having a circuit configuration equivalent to the driver circuit; and a control circuit configured to control a characteristic of the driver circuit, based on an output signal of the replica circuit, wherein the replica circuit includes: a first replica circuit part configured to output first output signals having signal levels of a first subset of a plurality of signal levels corresponding to the multilevel signal; and a second replica circuit part configured to output second output signals having signal levels of a second subset of the plurality of signal levels, and the control circuit is configured to control a characteristic of the variable current source, based the first output signals and the second output signals. 1. A signal output circuit comprising:a driver circuit including a variable current source and configured to output a multilevel signal;a replica circuit having a circuit configuration equivalent to the driver circuit; anda control circuit configured to control a characteristic of the driver circuit, based on an output signal of the replica circuit, wherein a first replica circuit part configured to output first output signals having signal levels of a first subset of a plurality of signal levels corresponding to the multilevel signal; and', 'a second replica circuit part configured to output second output signals having signal levels of a second subset of the plurality of signal levels, and, 'the replica circuit includesthe control circuit is configured to control a characteristic of the variable current source, based on the first output signals and the second output signals.2. The signal output circuit according to claim 1 , wherein:the driver circuit is configured to output a quaternary signal;the first replica circuit part is configured to output the first output signals having signal levels of a ...

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Номер записи: 97
27-11-2014 дата публикации

METHOD OF CONVERTING AN OPTICAL COMMUNICATIONS SIGNAL AND AN OPTICAL RECEIVER

Номер: US20140348514A1
Автор: Bogoni Antonella
Принадлежит: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)

A method of converting an optical communications signal having a differentially encoded multilevel modulation format into communications traffic bits, the multilevel modulation format having a plurality of constellation points, the method comprising: receiving a consecutive pair of symbol signals of said optical communications signal, the pair of symbol signals being arranged to differentially encode a plurality of communications traffic bits; and generating a plurality of optical binary signals in dependence on the symbol signals, each optical binary signal having a respective binary signal level, wherein the optical binary signals form optical versions of the encoded communications traffic bits. 1. A method of converting an optical communications signal having a differentially encoded multilevel modulation format into communications traffic bits , the multilevel modulation format having a plurality of constellation points , the method comprising:receiving a consecutive pair of symbol signals of said optical communications signal, the pair of symbol signals being arranged to differentially encode a plurality of communications traffic bits; andgenerating a plurality of optical binary signals in dependence on the symbol signals, each optical binary signal having a respective binary signal level, wherein the optical binary signals form optical versions of the encoded communications traffic bits.2. The method as claimed in claim 1 , wherein the generating the plurality of optical binary signals comprises:{'sub': i-1', 'i, 'receiving a first symbol signal, S, of the pair of symbol signals and receiving a second symbol signal, S, of the pair of symbol signals;'}{'sub': i', 'i, 'sup': 'π/2', 'forming a phase-rotated version of the second symbol signal, S, having a π/2 phase difference relative to the second symbol signal, S;'} [{'br': None, 'i': S', '+S, 'sub': i', 'i-1, ';'}, {'br': None, 'i': S', '−S, 'sub': i', 'i-1, ';'}, {'br': None, 'i': S', '+S, 'sub': i', 'i-1, ' ...

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Номер записи: 98
14-09-2017 дата публикации

INTELLIGENT EQUALIZATION FOR A THREE-TRANSMITTER MULTI-PHASE SYSTEM

Номер: US20170264471A1
Автор: CHOU Shih-Wei, Lee Chulkyu, Wiley George
Принадлежит:

An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter. 1. A three-transmitter system for transmitting successive multi-phase symbols , comprising:an encoder configured to encode data to provide commands corresponding to the successive multi-phase symbols;a plurality of three transmitters each configured to drive its output signal responsive to a current one of the commands to one of a plurality of signal levels for a current one of the successive multi-phase symbols; anda logic circuit configured to detect when a mid-level one of the three transmitters is commanded by the encoder to transition its output signal from a high-level to a mid-level for the current multi-phase symbol while a low-level one of the three transmitters is commanded by the encoder to transition its output signal from the mid-level to a low-level and to force the mid-level transmitter to instead transition its output signal to a reduced mid-level during an initial portion of the current multi-phase symbol and to force the low-level transmitter to instead transition its output signal to an increased low-level during the initial portion, wherein the high-level is greater than the mid-level, the mid-level is greater than the reduced mid-level, the reduced mid-level is greater than increased low-level, and the increased low-level is greater than the low-level.2. The three-transmitter system of claim 1 , wherein the output signal for each transmitter is a voltage output signal claim 1 , and wherein the high-level claim 1 , the mid-level claim 1 , the reduced mid-level claim 1 , the increased low-level claim 1 , and the low-level are all voltage levels.3. The three-transmitter system of claim 1 , wherein the output signal for each transmitter is a current output signal claim 1 , and wherein the high-level claim 1 , the mid-level claim 1 , the reduced mid-level ...

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Номер записи: 99
20-09-2018 дата публикации

THREE-VALUED SIGNAL GENERATION DEVICE AND THREE-VALUED SIGNAL GENERATION METHOD

Номер: US20180270090A1
Автор: YAMANE Kazuhiro
Принадлежит:

A three-valued signal generation device includes a first differential amplifier that outputs a differential signal, a second differential amplifier that outputs a differential signal and an inverted differential signal in accordance with a level based on a reference voltage of an inverted pseudo LFPS signal, which is obtained by inverting a logic level of the pseudo LFPS signal, a first signal synthesis unit that synthesizes the differential signal from the first differential amplifier and the inverted differential signal from the second differential amplifier to perform positive logic output of a three-valued LFPS signal, and a second signal synthesis unit that synthesizes the inverted differential signal from the first differential amplifier and the differential signal from the second differential amplifier to perform negative logic output of the three-valued LFPS signal. 1. A three-valued signal generation device that generates a three-valued Low Frequency Periodic Signaling (LFPS) signal by using a pseudo LFPS signal which is a two-valued Non Return to Zero (NRZ) signal and a two-valued enable signal corresponding to a burst section of the three-valued LFPS signal having voltage levels of a low level , a high level , and an intermediate level , the three-valued signal generation device comprising:a first differential amplifier that includes:a first enable terminal to which the enable signal is input,a first input terminal to which the pseudo LFPS signal is input,a first output terminal from which a first differential signal is output, anda first inverted output terminal from which a first inverted differential signal obtained by inverting a voltage level of the first differential signal is output,a logic of the first differential signal being same as a logic of the pseudo LFPS signal based on a reference voltage of the pseudo LFPS signal when the enable signal is at a disable logic level,and the logic of the first differential signal being at a positive logic ...

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Номер записи: 100