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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 10511. Отображено 100.

05-01-2012 дата публикации

Communication circuit of inter-integrated circuit device

Номер: US20120005385A1

Автор: Ming-Yuan Hsu

Принадлежит: Hon Hai Precision Industry Co Ltd

A communication circuit of an Inter-Integrated Circuit (I2C) includes a master device, a switch circuit, first and second groups of slave devices. Each slave device includes a data signal pin and a clock signal pin, which are connected to the switch circuit. The master device includes a data signal pin, a clock signal pin, and a general purpose input output (GPIO) pin, which are connected to the switch circuit. The GPIO pin of the master device outputs a control signal to the switch circuit, to allow communication between the first group of slave devices and the master device or communication between the second group of slave devices and the master device.

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Номер записи: 1

19-01-2012 дата публикации

Data transfer circuit and data transfer method

Номер: US20120017017A1

Автор: Masaru Nishiyashiki

Принадлежит: Fujitsu Ltd

A port A request queue is configured with a port AQ 0 to a port AQn for each of request types Q 0 to Qn connected with a requester resource busy flag controller Q 0 to a requester resource busy flag controller Qn, respectively. A port A resource checking unit of a port X arbiter unit gives instructions to the requester resource busy flag controller of the port AQ 0 to turn a busy flag on when it is determined that a data request from the port AQ 0 has difficulty in being output to a port X inter-port arbiter unit due to resources being busy as a result of referring to a resource information unit of a port X resource managing unit. The port AQ 0 inhibits output of a data request as long as the busy flag is on.

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Номер записи: 2

08-03-2012 дата публикации

Non-invasive direct-mapping usb switching device

Номер: US20120059969A1

Автор: Cheng-Sheng Chou, Chien-Fa Lin

Принадлежит: June On Technology Co Ltd

A non-invasive direct-mapping USB switching device includes a main-controlled microprocessing module connected to a high-impedance module, and the high-impedance module is provided for detecting and monitoring a functional instruction code of a USB device transmitted from a data transmission module, such that a USB connecting module can be used for transmitting the USB data and functional instruction code to detect and monitor the data transmission module when the USB device is connected to the USB switching device. If the data transmitted from the data transmission module is not the required functional code, the non-required functional code (such as the USB data) will be passed, so that the USB device can be connected and communicated with a plurality of computer devices through another USB connecting module and a switching module to achieve a plug-and-play function.

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Номер записи: 3

15-03-2012 дата публикации

Use of pci express for cpu-to-cpu communication

Номер: US20120066430A1

Автор: Braden Michael Cooper, Stephen Dale Cooper

Принадлежит: Individual

CPUs that generate PCIe auxiliary signals and changing clock signals nevertheless communicate with each other using PCIe owing to PCIe switch assemblies that are disposed in the communication paths to isolate and terminate the auxiliary signals from reaching other CPUs and to isolate changing clock signals, communicating with each other using a fixed clock derived from one of the changing clock signals. Also, the CPUs directly access the memories of CPUs to which they wish to write data so that data is directly written from one CPU memory to another without store-and-forward operations being needed in the network.

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Номер записи: 4

29-03-2012 дата публикации

Scalable and programmable processor comprising multiple cooperating processor units

Номер: US20120079236A1

Автор: Adriaan J. De Lind Van Wijngaarden, Dusan Suvakovic, Man Fai LAU

Принадлежит: Alcatel Lucent USA Inc

A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

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Номер записи: 5

26-04-2012 дата публикации

Solid State Drive Architecture

Номер: US20120102263A1

Автор: Ajoy Aswadhati

Принадлежит: FASTOR SYSTEMS Inc

Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.

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Номер записи: 6

26-04-2012 дата публикации

Stall propagation in a processing system with interspersed processors and communicaton elements

Номер: US20120102299A1

Автор: Craig M. Chase, David A. Gibson, Michael B. Doerr, William H. Hallidy

Принадлежит: Individual

A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.

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Номер записи: 7

26-04-2012 дата публикации

Virtual function boot in single-root and multi-root i/o virtualization environments

Номер: US20120102491A1

Автор: Parag R. Maharana

Принадлежит: LSI Corp

A method for virtual function boot in a system including a single-root I/O virtualization (SR-IOV) enabled server includes loading a PF driver of the PF of a storage adapter onto the server utilizing the virtual machine manager of the server; creating a plurality of virtual functions utilizing the PF driver, detecting each of the virtual functions on an interconnection bus, maintaining a boot list associated with the plurality of virtual functions, querying the storage adapter for the boot list utilizing a VMBIOS associated with the plurality of VMs, presenting the detected boot list to a VM boot manager of the VMM, and booting each of the plurality of virtual machines utilizing each of the virtual functions, wherein each VF of the plurality of VFs is assigned to a VM of the plurality of VMs via an interconnect passthrough between the VMM and the plurality of VMs.

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Номер записи: 8

12-07-2012 дата публикации

Electrical Circuit For Transmitting Signals Between Two Masters And One Or More Slaves

Номер: US20120179848A1

Автор: Volker Frese

Принадлежит: ROBERT BOSCH GMBH

An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch.

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Номер записи: 9

19-07-2012 дата публикации

Apparatus and method for compressing trace data

Номер: US20120185675A1

Автор: Chang-Moo Kim, Dong-hoon Yoo, Hee-Jun Shim, Jae-Young Kim, Yeon-gon Cho

Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid trace data.

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Номер записи: 10

26-07-2012 дата публикации

Expandable asymmetric-channel memory system

Номер: US20120191921A1

Автор: Arun Vaidyanath, Ian Shaeffer, Sanku Mukherjee

Принадлежит: RAMBUS INC

An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

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Номер записи: 11

23-08-2012 дата публикации

Supporting global input/output interconnect features on ports of a midpoint device

Номер: US20120215948A1

Автор: Jeffrey Michael Dodson

Принадлежит: PLX Technology Inc

In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.

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Номер записи: 12

11-10-2012 дата публикации

Electronic device with card interface

Номер: US20120260001A1

Автор: Akihisa Fujimoto, Hiroyuki Sakamoto, Kosei Okamoto, Masao Suga

Принадлежит: Toshiba Corp

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

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Номер записи: 13

11-10-2012 дата публикации

Kvm switcher with ability to extend universal serial bus (usb) host interface via serial peripherial interface (spi)

Номер: US20120260018A1

Автор: Chun Tse LIN

Принадлежит: OCT Technology Co Ltd

A multi-computer (KVM) switcher with ability to extend universal serial bus (USB) host interface via serial peripheral interface (SPI), characterized in that SPI master device interface of master control unit can switch the capability of controlling plural SPI slave devices via serial peripheral interface (SPI), and through installing SPI slave device interfaces on plural universal serial bus (USB) host interface control units to be extended, the object of extending peripheral device with USB interface via SPI interface is achieved.

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Номер записи: 14

18-10-2012 дата публикации

Crosspoint switch with separate voltage sources for input and output ports

Номер: US20120262219A1

Автор: Merrick Brownlee, Poupak Khodabandeh

Принадлежит: Mindspeed Technologies LLC

A crosspoint switch device has a plurality of input ports each connected to a respective voltage source and a plurality of output ports each connected to a respective voltage source. A switch array selectively provides signal paths between the input ports and the output ports. The voltage sources are separate from one another.

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Номер записи: 15

18-10-2012 дата публикации

Server Input/Output Failover Device Serving Highly Available Virtual Devices

Номер: US20120265910A1

Автор: Luca Cafiero, Michael B. Galles

Принадлежит: Cisco Technology Inc

A failover input/output device and corresponding method are provided to manage failover events of input/output controller devices that operate in accordance with a computer expansion card standard, such as the Peripheral Component Interconnect Express (PCIe) standard. The failover input/output device connects to redundant first and second virtualized input/output controller devices each comprising multiple virtual network interfaces that are in an active or standby state at any given time, and to a computing device that hosts one or more processes. The failover input/output device broadcasts transactions in accordance with the computer expansion card standard initiated from the computing device to the first and second virtualized input/output controller devices. The failover input/output device receives signals associated with upstream transaction completions in accordance with the computer expansion card standard for both active and standby virtual network interfaces on the first and second virtualized input/output controller devices. The failover input/output device forwards signals associated with upstream transaction completions for active virtual network interfaces on the first and second virtualized input/output controller devices to the computing device.

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Номер записи: 16

18-10-2012 дата публикации

Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

Номер: US20120265914A1

Автор: Eugene Hogenauer, Paul L. Master, Walter James Scheuermann

Принадлежит: QST Holdings LLC

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

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Номер записи: 17

01-11-2012 дата публикации

Disk subsystem

Номер: US20120278523A1

Автор: Kazuhisa Aruga

Принадлежит: HITACHI LTD

A protocol controller disposed between switches in a fiber channel fabric switch circuit and disk drive units for converting a protocol to enable one-to-one connectivity established between controllers and disk drive units.

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Номер записи: 18

08-11-2012 дата публикации

Zone group manager virtual phy

Номер: US20120284435A1

Автор: Balaji Natrajan, Michael G. Myrah, Sohail Hameed

Принадлежит: Hewlett Packard Development Co LP

A switch is provided. The switch includes an expander configured to couple a server to a set of storage drive bays. The switch also includes a zone manager coupled to the expander and configured to maintain a zoning configuration corresponding to the set of storage drive bays. The zone manager is coupled to the expander through a virtual PHY.

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Номер записи: 19

22-11-2012 дата публикации

Motherboard of computing device

Номер: US20120297132A1

Автор: Bo Tian, Guo-Yi Chen

Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

A motherboard of a computing device includes a dual inline memory module (DIMM), a processor socket, a platform controller hub (PCH), a switch, and a switch controller. The DIMM is connected to the processor socket or the PCH through the switch controller. The switch is connected to the switch controller, and generates a signal when the switch is operated. The switch controller controls the DIMM to connect either to the processor socket or to the PCH according to the signal, so that a solid state disk (SSD) or a memory that is connected to the DIMM can be supported appropriately by the motherboard.

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Номер записи: 20

06-12-2012 дата публикации

Implementing device physical location identification in serial attached scsi (sas) fabric using resource path groups

Номер: US20120311222A1

Автор: Brian L. Bowles, Laurel Scaife, Robert E. Galbraith

Принадлежит: International Business Machines Corp

A method and controller for implementing device physical location identification in a Serial Attached SCSI (SAS) fabric using resource path groups, and a design structure on which the subject controller circuit resides are provided. The device physical location identification includes a Resource Path Group (RPG). Each RPG provides a unique persistent physical locator of a storage device in the system. Each RPG including at least two Resource Paths (RPs) and each RP has a fixed size identifying a type and a series of egress ports. A persistent RPG is stored within the device metadata on the storage device.

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Номер записи: 21

13-12-2012 дата публикации

Parallel communication device and communication method thereof

Номер: US20120317320A1

Автор: Tae Bum Park

Принадлежит: LSIS Co Ltd

Provided are a parallel communication device and a communication method thereof. The parallel communication device includes: a first receiving terminal receiving communication data transmitted through a master device; a first transmitting terminal transmitting the communication data received through the first receiving terminal to a slave device; a switch managing a communication line disposed between the first transmitting terminal and a plurality of slave devise; and a control unit confirming a first slave device to which the communication data are to be transmitted by using destination information in the communication data, and transmitting the received communication data to the confirmed first slave device.

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Номер записи: 22

20-12-2012 дата публикации

Apparatus and method for sharing i/o device

Номер: US20120324078A1

Автор: Junji Yamamoto, Ken Sugimoto, Kenichi Watanabe

Принадлежит: HITACHI LTD

In a server apparatus in which a plurality of physical servers and an I/O device are connected via an I/O switch, when the plurality of physical servers share one I/O device, a tag included in a request packet transmitted from a first physical server to the I/O device is translated into a value that is not used in the I/O device in the I/O switch and thereafter the request packet is transferred to the I/O device, and then a tag included in a response packet which responds to the request packet and which is transmitted from the I/O device to the first physical server is restored to the original tag, so that conflict of tags when a plurality of physical servers share one I/O device is avoided.

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Номер записи: 23

28-02-2013 дата публикации

Integrating Intellectual Property (IP) Blocks Into A Processor

Номер: US20130054845A1

Автор: Aimee D. Wood, James A. Beavens, Jeff V. Tran, Lily P. Looi, Marcus W. Song, Prashanth Nimmala, Robert J. Greiner, Rupin H. Vakharwala

Принадлежит: Intel Corp

In one embodiment, the present invention includes apparatus that is formed on a single semiconductor die having one or more cores, a memory controller, and a hub coupled to the memory controller. The hub includes multiple fabrics each to communicate with a peripheral controller via a target interface and a master interface according to a first protocol, and where the fabrics are serially coupled via a first plurality of target interfaces in an upstream direction and a second plurality of target interfaces in a downstream direction. Other embodiments are described and claimed.

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Номер записи: 24

14-03-2013 дата публикации

Virtual Switch Extensibility

Номер: US20130067466A1

Автор: Alireza Dabagh, Luis M. Hernandez, Pankaj Garg, Robert C. Combs, Sambhrama M. Mundkur, Sandeep K. Singhal

Принадлежит: Microsoft Corp

An extensible virtual switch allows virtual machines to communicate with one another and optionally with other physical devices via a network. The extensible virtual switch includes an extensibility protocol binding, allowing different extensions to be added to the extensible virtual switch. The extensible virtual switch also includes a miniport driver on which the extensions are loaded, tying the lifetimes of the extensions to the lifetime of the extensible virtual switch.

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Номер записи: 25

21-03-2013 дата публикации

SYSTEMS AND METHODS FOR IMAGE STREAM PROCESSING

Номер: US20130073775A1

Автор: Brown Joel, Siewert Charles, Wade Jack

Принадлежит:

Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may provide vision systems and methods suitable for use in vehicles, particularly windowless vehicles, such as armored ground vehicles, submerged watercraft, and spacecraft. Some embodiments may enable sharing of image streams (e.g., with one or more other vehicles), generation of panoramic views (e.g., from various camera feeds), intelligent encoding of image streams, and implementation of security features based on image streams. 1. A system for image stream processing , comprising:an image stream input interface;an image stream output interface;a first image processing module configured to accept a plurality of image streams, stitch at least two image streams from the plurality of image streams into a contiguous image stream, and output the contiguous image stream, wherein the plurality of image streams comprises an image stream from the image stream input interface or from another image processing module;a second image processing module; and selectively map the image stream from the image stream input interface or from the second image processing module, to the first image processing module, and', 'selectively map the contiguous image stream from the first image processing module to the image stream output interface or to the second image processing module., 'a switching matrix in communication with the image stream input interface, the image stream output interface, the first image processing module, and the second image processing module, wherein the switching matrix is configured to2. The system of claim 1 , further comprising a plurality of image stream input interfaces claim 1 , the plurality of image stream input interfaces being in communication with the switching matrix and including the image stream input interface claim 1 , wherein at least two ...

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Номер записи: 26

04-04-2013 дата публикации

COMMUNICATION CONTROL SYSTEM, SWITCHING NODE, COMMUNICATION CONTROL METHOD AND COMMUNICATION CONTROL PROGRAM

Номер: US20130086295A1

Автор: Hayashi Masashi, Hidaka Youichi, Izawa Tetsu, Okamoto Tsugio, Phila Vongh Minaxay, Sato Shihomi, Takashima Masanori, Tsuchiya Koichi, Yokota Takashi

Принадлежит:

In a switching node, high-speed and advanced service protocol processing function is achieved by utilizing an external control server without affecting performance of conventional service protocol processing. Specifically, a forwarding engine has PCI express and an LAN interface. Depending on a type of an input packet, destination of the packet is switched to the PCI express side for conventional network service and to the LAN interface side for extended network service that cooperates with the external control server. A CPU having the PCI express and the LAN interface is provided ahead of the LAN interface. The CPU performs communication of service inquiry with the external control server at high speed via the LAN interface. After response from the control server is obtained, setting of the forwarding engine is performed through the PCI express. 1. A communication control system comprising:a switching node configured to execute conventional network service; anda control server configured to execute extended network service,wherein said switching node comprises:a first internal bus used for forwarding a frame for internal processing;a second internal bus for forwarding a frame for external transmission; anda forwarding engine configured to operate depending on a type of an input frame, to forward a frame regarding said conventional network service to said first internal bus for internal processing in said switching node, and to forward a frame regarding said extended network service to said second internal bus for utilizing said control server.2. The communication control system according to claim 1 ,wherein said switching node further comprises:a first processor configured to receive a frame from said forwarding engine through said first internal bus and to execute said conventional network service; anda second processor configured to receive a frame from said forwarding engine through said second internal bus, to perform processing related to said extended network ...

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Номер записи: 27

25-04-2013 дата публикации

System and Method for Providing PCIE over Displayport

Номер: US20130103876A1

Автор: Goodart Joseph Edgar, Wu Shuguang

Принадлежит:

An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed 120-. (canceled)21. An information handling system comprising:a processor configured to generate information;a video display subsystem interfaced with the processor and configured to process the information into video information for communication to a display;a host main link interfaced with video display subsystem and configured to couple to a display cable;a display configured to present the video information as visual images;a display main link interfaced with the display and configured to couple to the display cable;a display cable coupled at a first end to the host main link and at a second end to the display main link, the display cable configured to communicate the video information from the video display subsystem to the display across four serial links; anda peripheral coupled to the display and having associated peripheral information;wherein the display main link is further configured to communicate the peripheral information through the display cable to the host main link, the display main link and host main link cooperating to selectively assign some of the four serial links to communicate the peripheral information while the remaining of the four serial links communicate the video information.22. The information handling system of further comprising:a display receiver interfaced with the display main link and configured to receive the video information from the display cable;a peripheral transceiver interfaced with the display main link and configured to communicate peripheral information with the display cable; anda multiplexor disposed between the main link and the display receiver and the peripheral transceiver, the ...

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Номер записи: 28

25-04-2013 дата публикации

Multi-Processor Architecture Implementing A Serial Switch And Method Of Operating Same

Номер: US20130103881A1

Автор: Bansal Deepak, Cheung David, Devarapalli Sridhar, Hamadani Mehrdad, Kancheria Mani, Malli Steenivasulu, Moy Sam Htin

Принадлежит: BROCADE COMMUNICATIONS SYSTEMS, INC.

A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards. 1. A multi-processor architecture comprising:a plurality of blades, each including: a plurality of processors, a switch fabric that implements connections using point-to-point serial links, wherein the switch fabric is coupled to each of the plurality of processors, and packet processing logic coupled to the switch fabric; anda first external switch fabric that implements connections using point-to-point serial links, wherein the first external switch fabric is coupled to each switch fabric of the plurality of blades.2. The multi-processor architecture of claim 1 , further comprising a management processor coupled to the first external switch fabric.3. The multi-processor architecture of claim 2 , further comprising a processor accelerator coupled to the first external switch fabric.4. The multi-processor architecture of claim 1 , further comprising:one or more line cards that receive and transmit data packets; anda second external switch fabric coupling each of the one or more line cards to the packet processing logic of each of the plurality of blades.5. The multi-processor architecture of claim 4 , further comprising a third external switch fabric coupled to the first external switch fabric claim 4 , the one or more line cards and the second external switch fabric ...

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Номер записи: 29

09-05-2013 дата публикации

COMMUNICATING A MESSAGE REQUEST TRANSACTION TO A LOGICAL DEVICE

Номер: US20130117490A1

Автор: Harriman David

Принадлежит:

A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. 1. An apparatus comprising: assemble a completion header of a packet of a completion of a request, wherein the completion header is to include a routing identifier field to identify a device associated with the request; and', 'send the packet over an interconnect comprising one or more serial point-to-point links, wherein routing of the packet is based at least in part on values of the routing identifier field., 'an I/O module to2. The apparatus of claim 1 , wherein the header further is to include a completer identifier identifying a device that attempted to complete a request of the transaction.3. The apparatus of claim 2 , wherein the completer identifier is to include identification of a bus number claim 2 , a device number claim 2 , and a function number of the device.4. The apparatus of claim 1 , wherein the completer identifier comprises a field of at least sixteen ...

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Номер записи: 30

16-05-2013 дата публикации

Routing of enterprise resource planning messages

Номер: US20130123964A1

Автор: Brandon E. Henning, Crisler Moor, David Cooper, Keith Chambers, Kevin Chao, Richard Sze, Suryanarayana Murthy Bobba

Принадлежит: Rockwell Automation Technologies Inc

An Enterprise Resource Planning (ERP) gateway is provided for routing of ERP messages to Manufacturing Execution System (MES) applications. The gateway can receive a message from an ERP system via a manufacturing services bus specifying a business objective requiring action at a control level of an enterprise. The received message can be routed to a selected MES application capable of carrying out the business objective based on attributes within the message. Message routing can be based on location tags contained in the message. The message can also be routed to a selected subset of MES applications based on an analysis of respective capabilities and control contexts of the MES applications. Messages can be routed between the ERP system and the MES applications via the manufacturing services bus, which can manage protocol transformations for a heterogeneous set of applications.

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Номер записи: 31

16-05-2013 дата публикации

Graphics processing

Номер: US20130124772A1

Автор: Wenjie Zheng, Zhao SANG

Принадлежит: Nvidia Corp

In one embodiment, a computer system comprises two or more graphics cards, each graphics card comprising: a graphics processing unit and an interface. An interface of the first graphics card is coupled to an interface of the second graphics card for enabling communication between the first and second graphics cards. A cable couples the interface of the first graphics card with the interface of the second graphics card. The transmitting speed of data exchanging between graphics cards of the computer system is increased, and the arrangement of the PCB (printed circuit board) of the graphics card is simple and the cost thereof is low.

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Номер записи: 32

30-05-2013 дата публикации

USB CLASS PROTOCOL MODULES

Номер: US20130138860A1

Автор: Moore Terrill M.

Принадлежит: MCCI CORPORATION

A computer system includes USB class protocol-aware modules for USB devices as part of a xHCI host controller. The protocol-aware modules serve as accelerators by implementing critical portions of the device class protocols, which includes fetching higher level protocol data directly from client buffers for transmission and delivering decoded data to client buffers on receipt; and emulating a register-based interface for the benefit of system software on the host computer. 1. A USB class aware protocol module operating with an xHCI controller to transfer data to a device attached to a Superspeed Universal Serial Bus 3.0 (USB) , the protocol module comprising:a set of registers and buffers including one or more registers and one or more buffers, the set modeling an interface for data transfer over a register oriented bus to the device, the set of registers and buffers receiving commands associated with data transfers to the device and the data for transfer to the device; process the data contained in the set of registers and buffers in accordance with the commands contained in the set of registers and buffers and a USB class protocol corresponding to the device and produce processed data, and', 'optimize the processed data for transfer over the USB to the attached device by the xHCI controller; and, 'one or more processors configured to'}transfer rings for directing the optimized and processed data over the USB to the is device under the control of the xHCI controller.2. The protocol module of wherein the one or more processors optimize the processed data by formatting the data as messages for transfer over the USB in accordance with an xHC protocol.3. The protocol module of wherein the one or more processors operate with an xHC driver to format the data.4. The protocol module of whereinthe device is a video device, andthe one or more processors process the data and commands contained in the set of registers and buffers by emulating a video device controller ...

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Номер записи: 33

06-06-2013 дата публикации

Microcontroller resource sharing

Номер: US20130145063A1

Автор: Alain Vergnes, Franck Lunadier, Guillaume Pean

Принадлежит: Atmel Rousset SAS

A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

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Номер записи: 34

06-06-2013 дата публикации

Electronic device and method for switching modes of thunderbolt connector thereof

Номер: US20130145071A1

Автор: Chen-Yi Chu, Chih-Pang Hsu, Ching-Hang Chen

Принадлежит: ASUSTeK Computer Inc

An electronic device and a method for switching mode of a thunderbolt connector thereof are provided. The electronic device includes a core unit, a PCIE device, a thunderbolt control unit, a first switch circuit and a second switch circuit. The thunderbolt control unit has a host mode and an end-point device mode. A common terminal of the first switch circuit is coupled to a PCIE port of the PCIE device. A first selection terminal of the first switch circuit is coupled to a first PCIE port of the core unit. A common terminal of the second switch circuit is coupled to a PCIE port of the thunderbolt control unit. A first selection terminal of the second switch circuit is coupled to a second PCIE port of the core unit. A second selection terminal of the first switch circuit is coupled to a second selection terminal of the second switch circuit.

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Номер записи: 35

06-06-2013 дата публикации

High availability and I/O aggregation for server environments

Номер: US20130145072A1

Автор: DAVAR Jonathan, Dvorkin Mike, Jain Vipul, Shah Shreyas, Tang Cheng, VENKATARAGHAVAN Vikram, WONG Ming

Принадлежит:

Methods and apparatus are provided for virtualizing port adapter resources such as network interface cards (NICs) used to connect servers to packet based networks. Resources are offloaded from individual servers onto a resource virtualization switch. Servers connected to the resource virtualization switch using an I/O bus connection share access to NICs. Redundancy can be provided using multipathing mechanisms implemented at individual servers or high availability mechanisms implemented at the resource virtualization switch. Switchover can occur between ports on the same port adapter, between ports on separate adapters, or between ports on separate resource virtualization switches. 135-. (canceled)36. A resource virtualization switch , comprising:an I/O bus switch connected to a plurality of external servers through a plurality of I/O bus ports, each of the plurality of external servers comprising a separate memory address space, the plurality of external servers including a first server running a first application and a second server running a second application;a plurality of network interface cards (NICs) connected to the PCI-Express bus switch, wherein the plurality of NICs are accessible to the plurality of servers as virtual NICs (VNICs), wherein a plurality of VNICs are assigned to the first application to allow for path redundancy in the event a particular NIC fails;a processor subsystem configured to initialize an internet protocol (IP) network connection through a first NIC regardless of whether any of the plurality of external servers are connected to the resource virtualization switch.37. The resource virtualization switch of claim 36 , wherein the first application accesses a particular VNIC as though it is accessing a particular NIC included in the first server.38. The resource virtualization switch of claim 36 , wherein the first application is operable to access the plurality of VNICs for load sharing.39. The resource virtualization switch of claim ...

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Номер записи: 36

13-06-2013 дата публикации

APPARATUS FOR COUPLING TO A USB DEVICE AND A HOST AND METHOD THEREOF

Номер: US20130151749A1

Автор: Chiu Hao-Hsuan, LAI YI-LIN, Shih Terrance

Принадлежит: VIA TECHNOLOGIES, INC.

An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result. 1. An apparatus for coupling to a Universal Serial Bus (USB) device and a USB host , the apparatus comprising:a memory, storing one or more descriptor entries, said one or more descriptor entries; anda controller, coupled to said memory, configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result,wherein the controller enables or disables a link path between the USB host and the USB device according the comparing result.2. The apparatus as recited in claim 1 , wherein the controller enables the link path when the comparing result indicates that the descriptor matches to the specific descriptor entry.3. The apparatus as recited in claim 1 , wherein claim 1 , when the link path is enabled and the comparing result indicates that the USB device has remote wakeup capability claim 1 , the controller maintains the link path when the USB host is operated in a power saving mode.4. The apparatus as recited in claim 1 , wherein the controller further issues a reset command to be transmitted to the USB device after obtaining the descriptor claim 1 , thereby allowing for normal enumeration procedures by the said USB host.5. The apparatus as recited in claim 1 , wherein said controller disables the link path when the comparing result indicates that the descriptor does not match to any one of said one or more descriptor entries.6. The ...

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Номер записи: 37

13-06-2013 дата публикации

MULTI-ROOT INPUT OUTPUT VIRTUALIZATION AWARE SWITCH

Номер: US20130151750A1

Автор: Haider Shabbir, Kanakaraj Paulraj, Kanigicherla Balaji, Medeme Naga Murali, Pasumarthy Dhanumjai, Vaidya Tapan

Принадлежит:

A system having a multi protocol multi-root aware (MP-MRA) switch () configured to route data between multiple host processors () and multiple I/O devices () is described herein. In said embodiment, the MP-MRIOV aware switch includes a switch routing module (), at least one upstream adaptive module (), and at least one downstream adaptive module (). The upstream adaptive module () is configured to map information in a primary communication protocol to a intermediate communication protocol at which the switch routing module operates. Further, the downstream adaptive module () maps the intermediate communication protocol to a secondary communication protocol at which the I/O device () operates. 1. A method for translating information in a multi-host computing system comprising:receiving information, from a host processor, from amongst a plurality of host processors, in a primary protocol; wherein at least two host processors from amongst the plurality of host processors form different root complexes, and wherein the primary protocol for at least one host processor from amongst the plurality of host processors is non Peripheral Component Interconnect express (PCIe);translating the information from the primary protocol to an intermediate protocol, wherein the intermediate protocol is implemented by a multi-root aware switch; andtranslating further, the information from the intermediate protocol to a secondary protocol, wherein the secondary protocol is associated with an I/O device coupled to at least one of the plurality of host processors.2. The method as claimed in claim 1 , wherein the translation comprises mapping one or more of address spaces claim 1 , completion status claim 1 , traffic classes claim 1 , atomic operations claim 1 , and split completions from the primary protocol to the secondary protocol claim 1 , and wherein the secondary protocol is associated with the I/O device coupled to at least one of the plurality of host processors.3. The method as ...

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Номер записи: 38

13-06-2013 дата публикации

RECONFIGURABLE PROCESSOR AND MINI-CORE OF RECONFIGURABLE PROCESSOR

Номер: US20130151815A1

Автор: KIM Suk-Jin, KWON Ki-Seok, PARK Jae-Un, SUH Dong-kwan, YU Hyeong-Seok

Принадлежит:

A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected. 1. A reconfigurable processor comprising:at least one mini-core;wherein each mini-core of the at least one mini-core comprises at least two function units having different respective computing powers.2. The reconfigurable processor of claim 1 , wherein each of the function units comprises at least one operation element configured to perform an operation.3. The reconfigurable processor of claim 2 , wherein the computing power of each of the function units is defined according to a type of each of the at least one operation element included in each of the function units.4. The reconfigurable processor of claim 2 , wherein the operation elements of the function units comprise at least one operation element that is not included in all of the function units.5. The reconfigurable processing of claim 4 , wherein the operation elements of the function units further comprise at least one operation element that is included in at least two of the function units.6. The reconfigurable processor of claim 1 , wherein each mini-core of the at least one mini-core further comprises an internal network to which the function units are connected.7. The reconfigurable processor of claim 1 , wherein each mini-core of the at least one mini-core has a full computing power that is defined by a combination of respective partial computing powers of the function units.8. The reconfigurable processor of claim 1 , further comprising an external network to which each mini-core of the at least one mini-core is connected.9. The reconfigurable ...

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Номер записи: 39

20-06-2013 дата публикации

Negotiation Between Multiple Processing Units for Switch Mitigation

Номер: US20130159594A1

Автор: Bjegovic Nebojsa, Heppolette Vanessa Cristina

Принадлежит: Apple Inc.

A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus. 124.-. (canceled)25. A system , comprising:a graphical processing unit (GPU); anda microcontroller coupled to the GPU through a bus; receive a bus request from the GPU;', 'grant the bus request to the GPU;', 'receive a request for a switch from the GPU;', 'grant the request for the switch to the GPU., 'wherein the microcontroller is configured to26. The system of claim 25 , wherein the microcontroller includes a register.27. The system of claim 26 , wherein receive a bus request from the GPU comprises the GPU writing a value into a first bit of the register.28. The system of claim 25 , wherein grant the bus request to the GPU comprises completing any current transactions on the bus.29. The system of claim 26 , wherein grant the bus request to the GPU comprises the microcontroller writing a value into a second bit of the software register.30. A system claim 26 , comprising:a display device;a graphical processing unit (GPU);a switch coupled between the display device and the GPU, through a bus; and send data through the bus to the display device;', 'receive a request from the GPU for access to the bus;', 'complete pending transactions on the bus; and', 'closing the switch responsive to completing the pending transactions., 'a microcontroller coupled to the display device through the bus, wherein the microcontroller is configured to31. The system of claim 30 , wherein the bus comprises a clock line and a data line.32. The system of claim 30 , wherein send data through the bus comprises activating one or more field-effect transistors (FETs) coupled to the bus.33. The ...

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Номер записи: 40

20-06-2013 дата публикации

Serial Interface for FPGA Prototyping

Номер: US20130159595A1

Автор: Chee Hoe Chu, Po-Chien Chang, Wei Zhou

Принадлежит: MARVELL WORLD TRADE LTD

In aspects of serial interface for FPGA prototyping, an advanced crossbar interconnect (AXI) bridge structure enables serial data communication between field programmable gate arrays (FPGA) in a system-on-chip (SoC). The AXI bridge structure includes a parallel interface configured to receive AXI data signals from an AXI component implemented at a first FPGA. A transmit (TX) engine is configured to packetize the AXI data signals into an AXI data packet, and transmit the AXI data packet to a second FPGA via a serial link. The AXI bridge structure also includes a receive (RX) engine configured to receive an additional AXI data packet from the second FPGA via the serial link, and extract AXI data signals from the additional AXI data packet. The parallel interface is further configured to provide the additional AXI data signals to the AXI component.

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Номер записи: 41

04-07-2013 дата публикации

SWITCH APPARATUS SWITCHING BETWEEN BASIC INPUT OUTPUT SYSTEM CHIP AND DIAGNOSTIC CARD

Номер: US20130173833A1

Автор: CHEN CHUN-SHENG, ZOU HUA

Принадлежит:

A switch apparatus which can switch between two different booting chips includes a first connector, a platform controller hub (PCH) chip, a first basic input output system (BIOS) chip, a switch circuit, and a diagnostic card. The diagnostic card includes a second connector operable to be plugged into the first connector, and a second BIOS chip. When the switch circuit receives a high level control signal from the second BIOS chip, the switch circuit outputs a high level switch signal to first and second trapping pins of the PCH chip, to select the second BIOS chip to bootstrap the motherboard. When the switch circuit does not receive a high level control signal, the switch circuit outputs a low level signal to the first and second trapping pins of the PCH chip, to select the first BIOS chip to bootstrap the motherboard. 1. A switch apparatus , comprising:a first connector arranged on a motherboard;a platform controller hub (PCH) chip arranged on the motherboard and coupled to the first connector through a low pin count (LPC) bus, the PCH chip comprising a first trapping pin and a second trapping pin;a first basic input output system (BIOS) chip arranged on the motherboard, and coupled to the PCH chip through a serial peripheral interface (SPI) bus;a switch circuit arranged on the motherboard; and a second connector being detachably plugged into the first connector; and', 'a second BIOS chip coupled to the second connector, to output a high level control signal through the second connector;, 'a diagnostic card, comprisingwherein the switch circuit receives the high level control signal from the second BIOS chip through the first connector in response to the second connector being plugged into the first connector, the switch circuit outputs high level switch signals to the first and second trapping pins of the PCH chip, to select the second BIOS chip to bootstrap the motherboard; wherein the switch circuit does not receive the high level control signal in response to ...

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Номер записи: 42

11-07-2013 дата публикации

Dynamically Adjusting Power Of Non-Core Processor Circuitry

Номер: US20130179716A1

Автор: Dean Mulla, Ganapati Srinivasa, Jeffrey D. Gilbert, Krishnakanth Sistla, Mark Rowland, Suresh Doraiswamy, Vivek Garg

Принадлежит: Individual

In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

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Номер записи: 43

08-08-2013 дата публикации

MOTHERBOARD COMPRISING EXPANSION CONNECTOR

Номер: US20130205059A1

Автор: YANG MENG-LIANG

Принадлежит:

A motherboard includes a CPU, an expansion connector detachably connected to an expansion card, a controller, and a switch. The switch is electronically connected to the CPU, the expansion connector and the controller, the switch may be made to switch connections between the expansion connector and one of the CPU and the controller, according to a type of the expansion card which is installed. 1. A motherboard , comprising:a central processing unit (CPU);an expansion connector detachably connected to an expansion card;a controller; anda switch electronically connected to the CPU, the expansion connector and the controller, the switch receiving a first bus signal and a second bus signal from the CPU and the controller respectively, and selectively transmitting one of the first and second bus signals to the expansion card, according to a type of the expansion card.2. The motherboard of claim 1 , wherein the expansion connector is a PCIE connector that selectively connects to an expansion card of the PCIE type or the SAS type.3. The motherboard of claim 1 , further comprising a switching control unit claim 1 , wherein the switching control unit comprises a jumper and a jumper block electronically connected to the switch claim 1 , the jumper block comprises a plurality of jumper pins claim 1 , the jumper selectively constructs an electronic connection between different two jumper pins according to the type of the expansion card claim 1 , to control the switch to switch signal paths of the bus signals.4. The motherboard of claim 1 , wherein the first bus signal is a peripheral component interconnect-express (PCIE) signal claim 1 , and the second bus signal is a serial attached SCSI (SAS) signal.5. The motherboard of claim 4 , wherein the CPU transmits direct media interface (DMI) signal to the controller.6. The motherboard of claim 1 , wherein the controller is a platform controller hub (PCH).7. A motherboard claim 1 , comprising:a CPU;an expansion connector detachably ...

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Номер записи: 44

08-08-2013 дата публикации

System and method for using a multipath

Номер: US20130205061A1

Автор: Hiroyuki Miyoshi, Mitsutoshi Jinno, Yoshihiko Terashita

Принадлежит: International Business Machines Corp

In a path determination unit of a SAS expander connected to a SAS initiator and connected via first and second paths to a SAS target, an SSP controller receives an SSP command frame received from the SAS initiator; a requested-data-length manager stores a requested data length of the SSP command frame in a requested-data-length storage unit; and a data-transfer-amount manager selects one of the first and second paths having a smaller one of the data transfer amounts stored in a data-transfer-amount storage unit, and adds the requested data length to the data transfer amount of the selected path. The SSP command frame is transmitted to the SAS target via the selected path. Upon receipt of an SSP response frame responding thereto, the requested data length is deleted from the requested-data-length storage unit, and the requested data length is subtracted from the data transfer amount of the selected path.

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Номер записи: 45

15-08-2013 дата публикации

Memory mapped input/output bus address range translation

Номер: US20130212308A1

Автор: Curtis C. Wollbrink, David R. Engebretsen, Steven M. Thurber

Принадлежит: International Business Machines Corp

In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

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Номер записи: 46

22-08-2013 дата публикации

Multi-interface compatible bus over a common physical connection

Номер: US20130215911A1

Автор: David P. Chengson, Jaya Bandyopadhyay

Принадлежит: Juniper Networks Inc

A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

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Номер записи: 47

29-08-2013 дата публикации

STORAGE MEDIUM STORING INPUT/OUTPUT SETTING PROGRAM, STORAGE MEDIUM STORING OUTPUT SETTING PROGRAM, AND DATA PROCESSING APPARATUS

Номер: US20130227192A1

Автор: YASUI Ryo

Принадлежит: BROTHER KOGYO KABUSHIKI KAISHA

A non-transitory computer readable medium stores instructions that, when executed, cause a data processing apparatus, which includes a first input/output section and which is driven by a battery, to: judge whether the first input/output section is set as the input/output section; judge whether the remaining battery level of the battery is not less than a first reference remaining level; judge whether the data processing apparatus includes a second input/output section requiring a power consumption lower than that of the first input/output section; and switch or output a notification to switch the input/output section from the first input/output section to the second input/output section, in a case that the first input/output section is set as the input/output section; that the remaining battery level is less than the first reference remaining level; and that the data processing apparatus includes the second input/output section. 1. A non-transitory computer readable medium storing instructions that , when executed , cause a data processing apparatus , which includes a first input/output section for performing input/output of a data and which is driven by a battery , to:judge whether the first input/output section is set as the input/output section used for the input/output of the data;judge whether a remaining battery level of the battery is not less than a first reference remaining level;judge whether the data processing apparatus includes a second input/output section requiring a power consumption which is used for the input/output of the data and which is lower than that of the first input/output section, in a case that the data processing apparatus judges that the first input/output section is set as the input/output section used for the input/output of the data and that the remaining battery level is less than the first reference remaining level; andswitch the input/output section from the first input/output section to the second input/output section or output ...

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Номер записи: 48

05-09-2013 дата публикации

OUTPUT INPUT CONTROL APPARATUS AND CONTROL METHOD THEREOF

Номер: US20130232286A1

Автор: Li Kuo-Feng, Nain Yueh-Yao

Принадлежит: Nuvoton Technology Corporation

An output input (I/O) control apparatus and a control method thereof are provided. The I/O control apparatus includes an interface control unit, a read-only memory, a random access memory, a multiplexer and a micro-process unit. The interface control unit is coupled to a memory apparatus through a bus, and the memory apparatus is external to the I/O control apparatus. The read-only memory stores judgment codes. The multiplexer is controlled by the micro-process unit to switch to the interface control unit, the read-only memory or the random access memory. When the bus is not busy, the micro-process unit can read data from the memory apparatus. When the bus is occupied and busy, the micro-process unit can read and execute codes from the read-only memory or the random access memory so as to avoid computer system instability or thermal damage. 1. An output input (I/O) control apparatus , comprising:an interface control unit, externally coupled to a memory apparatus through a bus;a read-only memory, storing judgment codes;a random access memory;a multiplexer, configured to switch to the interface control unit, the read-only memory or the random access memory; anda micro-process unit, coupled to the interface control unit and the multiplexer, and the micro-process unit controlling where the multiplexer is switched to.2. The I/O control apparatus according to claim 1 , wherein when the I/O control apparatus is powered on claim 1 , the multiplexer is switched to the read-only memory by default claim 1 , the micro-process unit reads and executes the judgment codes so that the multiplexer is switched to the memory apparatus by the micro-process unit through the interface control unit claim 1 , and the micro-process unit reads a data stored in the memory apparatus.3. The I/O control apparatus according to claim 2 , wherein when the interface control unit is aware that an electronic apparatus from the external is about to occupy the bus claim 2 , the interface control unit ...

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Номер записи: 49

26-09-2013 дата публикации

COMPUTER SYSTEM, AND SWITCH AND PACKET TRANSFER CONTROL METHOD USED THEREIN

Номер: US20130254453A1

Автор: Sato Kazuki, TAKASE Ryo, Todaka Takashi

Принадлежит:

A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O devices to a computer via a PCIe switch. A switch with which a computer and I/O devices are connected includes: a first PCI-PCI bridge which is positioned on the computer side; a second PCI-PCI bridge which is positioned on the I/O device side; trapper units which trap packet data which is inputted into the switch; a packet routing unit which transfers packet data to the I/O devices; and a management processor which is connected to the trapper units and provides the computer a virtual PCI-PCI bridge and a virtual link by execution of a program. The trapper units adjudicate the destination of the packet data which is transferred from the computer. 1. A computer system that transfers packet data via switches connected to a computer and an I/O device ,wherein the switch is provided with a first PCI-PCI bridge arranged on the side of the computer, a second PCI-PCI bridge arranged on the side of the I/O device, a trapper unit that traps packet data input to the switch and a packet routing unit that transfers the packet data to the I/O device;the switch is further provided with a management processor which is connected to the trapper unit and which provides a virtual PCI-PCI bridge and a virtual link to the computer by the execution of a program;the PCI-PCI bridge included in the physical configuration of the computer system is distinguished as a physical PCI-PCI bridge;address space of such a PCI-PCI bridge that its virtual PCI-PCI bridge and its physical PCI-PCI bridge can be correlated by one to one is realized in that of the physical PCI-PCI bridge;address space of a virtual PCI-PCI bridge that cannot be correlated with the corresponding physical PCI-PCI bridge by one to one is secured in a memory;the trapper unit determines a destination of the packet data transferred from the computer;when the destination is the ...

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Номер записи: 50

03-10-2013 дата публикации

DATA PROCESSING APPARATUS, COMPUTATION DEVICE, CONTROL METHOD FOR DATA PROCESSING APPARATUS

Номер: US20130262735A1

Автор: IKEDA Yoshiro

Принадлежит: FUJITSU LIMITED

A data processing apparatus includes a plurality of computation devices connected to each other by a communication path. Each of the computation devices includes: a switching section provided to each of terminals and switchable between an upper layer use state in which communication is performed by a communication section between a given terminal of a plurality of terminals and a corresponding internal path and there is no connection performed by a bypass section between a corresponding pair of the plurality of the terminals, and an upper layer non-use state in which communication is not performed by a communication section between the given terminal of the plurality of the terminals and the corresponding internal path and connection is performed by the bypass section between the corresponding pair of the plurality of the terminals. 1. A data processing apparatus comprising:a plurality of computation devices connected to each other by a communication path; anda control device that controls the plurality of computation devices, wherein a plurality of terminals respectively connected to the communication path;', 'a communication section that performs communication with a more upper layer in a communication protocol than a physical layer through an internal path connectable to a given terminal out of the plurality of terminals;', 'a bypass section connectable between a pair of the plurality of the terminals;', 'a switching section provided to each of the terminals and switchable between an upper layer use state in which communication is performed by the communication section between a given terminal of the plurality of the terminals and the corresponding internal path and there is no connection performed by the bypass section between the corresponding pair of the plurality of the terminals, and an upper layer non-use state in which communication is not performed by the communication section between the given terminal of the plurality of the terminals and the ...

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Номер записи: 51

10-10-2013 дата публикации

Methods and systems for providing user selection of associations between information handling resources and information handling systems in an integrated chassis

Номер: US20130268697A1

Автор: Babu Chandrasekhar, Michael A. Brundridge, Timothy M. Lambert

Принадлежит: Dell Products LP

In accordance embodiments of the present disclosure a method may include receiving a user indication of a desired association between at least one of a plurality of modular information handling systems and at least one or one or more information handling resources. The method may also include communicating one or more control signals to one or more switching elements housed in a chassis configured to house the plurality of modular information handling systems and the one or more information handling resources, such that a selected modular information handling system is communicatively coupled to a selected information handling resource in accordance with the user indication of the desired association.

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Номер записи: 52

10-10-2013 дата публикации

Pcie switch apparatus and method of controlling connection thereof

Номер: US20130268713A1

Автор: Yong-Seok Choi

Принадлежит: Electronics and Telecommunications Research Institute ETRI

The present invention relates to a PCIe switch apparatus and a method of controlling the connection thereof. The PCIe switch apparatus includes a PCIe photoconversion unit for converting an electrical signal input from a local host into packet data and converting the converted packet data into an optical signal. A PCIe slot board unit reconverts the optical signal into the packet data, reconverts the packet data into the electrical signal, and outputs the electrical signal to a PCIe-based device. An optical cable connects the PCIe photoconversion unit and the PCIe slot board unit to each other. The PCIe switch apparatus controls a long-distance communication interface between the local host and the PCIe-based device.

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Номер записи: 53

07-11-2013 дата публикации

Router, method for controlling the router, and computer program

Номер: US20130294458A1

Автор: Atsushi Yoshida, Takao Yamaguchi, Tomoki Ishii

Принадлежит: Panasonic Corp

An exemplary router is provided for an integrated circuit that has distributed buses and is arranged on a transmission route that leads from a transmission node to a reception node on the distributed buses to relay data. The distributed buses include first and second routes, each leading from the router to the reception node. The router includes a notifying section which sends a data transfer permission request to a second router on the first route and a third router on the second route and which determines whether or not the request is approved before a predetermined standby period passes to see if there is any abnormality in the first and second routes.

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Номер записи: 54

07-11-2013 дата публикации

Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC)

Номер: US20130297846A1

Автор: Arvind Mandhani, Ken Shoemaker, Madhu Athreya, Mahesh Wagh, Shreekant S. Thakkar, Woojong Han

Принадлежит: Individual

In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

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Номер записи: 55

14-11-2013 дата публикации

Methods and structure for configuring a serial attached scsi domain via a universal serial bus interface of a serial attached scsi expander

Номер: US20130304952A1

Автор: Kaushalender Aggarwal, Mandar Joshi, Rakesh Verma, Saurabh B. Khanvilkar

Принадлежит: LSI Corp

Methods and structure are provided for managing a Serial Attached SCSI (SAS) domain via Universal Serial Bus (USB) communications. The system comprises a SAS expander. The SAS expander comprises a plurality of physical links, a USB interface, and a control unit. The control unit is operable to receive USB packets via the USB interface, to determine SAS management information based upon the received USB packets, and to alter a configuration of the SAS domain based upon the SAS management information determined from the USB packets.

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Номер записи: 56

05-12-2013 дата публикации

COARSE-GRAINED RECONFIGURABLE PROCESSOR AND CODE DECOMPRESSION METHOD THEREOF

Номер: US20130326190A1

Автор: Cho Yeon-Gon, Chung Moo-Kyoung, Ryu Soo-Jung

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit. 1. A coarse-grained reconfigurable processor comprising:a configuration memory configured to store reconfiguration information comprising a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing uncompressed codes;a decompressor configured to specify a code corresponding to each of the plurality of units based on the compression mode indicator and the compressed code within the header; anda reconfigurator comprising a plurality of processing elements (PEs) and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit.2. The coarse-grained reconfigurable processor of claim 1 , wherein the reconfiguration information further comprises:a kernel dictionary comprising at least one code frequently used in a kernel for each kernel of the reconfiguration information in the body.3. The coarse-grained reconfigurable processor of claim 2 , wherein the decompressor comprises:a kernel dictionary storage configured to store the kernel dictionary.4. The coarse-grained ...

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Номер записи: 57

12-12-2013 дата публикации

ELECTRONIC APPARATUSES AND RELATED CONTROLLING METHODS USING THE SAME

Номер: US20130332639A1

Автор: Jiang Shu-Yu, Lin Yung-Sen

Принадлежит: ACER INCORPORATED

Controlling methods for use in a module of an electronic apparatus are provided. The module can support at least a high-speed expansion bus interface and a low-speed expansion bus interface and is coupled to a platform controller hub (PCH) through the high-speed expansion bus interface and the low-speed expansion bus interface. First, one of the high-speed expansion bus interface and the low-speed expansion bus interface is assigned for data transmission with the PCH. Then, a detection result corresponding to the electronic apparatus or the module is obtained and the other one of the expansion bus interfaces is to be switched to for data transmission with the PCH according to the detection result. 1. A controlling method for use in a module of an electronic apparatus , wherein the module supports at least a high-speed expansion bus interface and a low-speed expansion bus interface and is coupled to a platform controller hub (PCH) through the high-speed expansion bus interface and the low-speed expansion bus interface , the method comprising:assigning one of the high-speed expansion bus interface and the low-speed expansion bus interface to perform a data transmission operation with the PCH;obtaining a detection result associated with the electronic apparatus or the module; andswitching to the other one of the high-speed expansion bus interface and the low-speed expansion bus interface to perform the data transmission operation with the PCH according to the detection result.2. The controlling method of claim 1 , wherein the switching step further comprises switching from the high-speed expansion bus interface to the low-speed expansion bus interface or switching from the low-speed expansion bus interface to the high-speed expansion bus interface according to the detection result.3. The controlling method of claim 1 , wherein the detection result is obtained by detecting a power source of the electronic apparatus and the switching step further comprises:when detecting ...

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Номер записи: 58

19-12-2013 дата публикации

METHOD TO CONTROL OPTICAL TRANSCEIVER IMPLEMENTED WITH A PLURALITY OF INNER SERIAL BUSES

Номер: US20130339559A1

Автор: Tanaka Hiromi

Принадлежит:

An optical transceiver implemented with a plurality of inner serial busses is disclosed. One of inner serial busses is the mother serial bus drawn out from the controller to the bus selector, while, the rest are daughter serial busses connecting the bus selector to respective circuit units. When some circuit units causes failures to hang the daughter serial bus connected thereto, the controller makes this daughter serial bus inactive by controlling the bus selector, and collects information and sets parameters to rest circuit units as activating other daughter serial busses. 1. A method to control an electronic apparatus that implements with a mother serial bus , a plurality of daughter serial buses each selectively coupled with the mother serial bus , and a plurality of circuit units each coupled with respective daughter serial buses , the method comprising steps of:selecting one of circuit units by providing power supply thereto;selecting one of daughter serial busses coupled with one of the circuit units; andcommunicating with one of the circuit units with the one of the daughter serial busses, the bus selector, and the mother serial bus.2. The method of claim 1 ,further including a step, after the communication with one of the circuit units, releasing the one of the daughter serial buses coupled with one of the circuit units.3. The method of claim 2 ,wherein at least two circuit units have a device address same to each other.4. The method of claim 1 ,further including a step, after the communication with one of the circuit units, selecting another of daughter serial busses coupled with another of the circuit units without releasing one of the daughter serial buses.5. The method of claim 4 ,wherein the one of the circuit units has a device address different from the another of circuit units selected after the communication with one of the circuit units.6. An optical transceiver coupled with a host system claim 4 , comprising:a plurality of circuit units;a bus ...

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Номер записи: 59

19-12-2013 дата публикации

INFORMATION PROCESSING DEVICE

Номер: US20130339566A1

Автор: KITAGO Keita, MATSUI Takao, SATO Kenta, UEKI Toshikazu

Принадлежит: FUJITSU LIMITED

An information processing device includes: a computing device having a first path for connecting between a computing unit configured to execute a computation process and a peripheral device, a second path for connecting between a computing unit that is included in another computing device and configured to execute a computation process and the peripheral device, and a switching unit configured to switch between the first path and the second path according to a switching signal; and a signal generation unit configured to generate a switching signal, and to output the generated signal to the switching unit. 1. An information processing device including a plurality of computing devices connecting to a peripheral device , wherein: a computing unit configured to execute a computation process,', 'a first path configured to connect between the computing unit and the peripheral device,', 'a second path configured to connect between a computing unit included in a different computing device and the peripheral device, and', 'a switching unit configured to switch between the first path and the second path; and, 'at least one of the plurality of computing devices comprises'} 'a signal generation unit configured to generate a switching signal for causing the switching unit to switch between the first path and the second path, and to output the generated signal to the switching unit.', 'the information processing device further comprises'}2. The information processing device according to claim 1 , whereinthe signal generation unit generates the switching signal for switching the switching unit to the second path upon detection of an error that occurs within the computing device.3. The information processing device according to claim 1 , whereinthe signal generation unit comprises selection means configured to select the first path or the second path, and generates a switching signal for switching the switching unit to the path selected by the selection unit.4. The information ...

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Номер записи: 60

19-12-2013 дата публикации

Cross-threaded memory system

Номер: US20130339631A1

Автор: Frederick A. Ware, Kishore Kasamsetty

Принадлежит: RAMBUS INC

In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

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Номер записи: 61

19-12-2013 дата публикации

System and Method for Providing a Processing Node with Input/Output Functionality Provided by an I/O Complex Switch

Номер: US20130339714A1

Автор: Booth Bradley J., Dube Shawn J., Hormuth Robert W., Lin Geng, PIKE JIMMY, Winter Robert L.

Принадлежит: DELL PRODUCTS, LP

A processing node of a server rack includes a processor to generate processing node management requests and to process responses to the node management requests, and a communication module to receive the processing node management requests, to transmit over a communication link to a management controller of the server rack external to the processing node a processing node management request, to receive over the communication link from the management controller processing node management information, and to transmit the processing node management information to the processor. 1. A processing node of a server rack , the processing node comprising:a processor to generate processing node management requests and to process responses to the node management requests; anda communication module to receive the processing node management requests, to transmit over a communication link to a management controller of the server rack external to the processing node a processing node management request, to receive over the communication link from the management controller processing node management information, and to transmit the processing node management information to the processor.2. The processing node of claim 1 , wherein the communication link comprises a Peripheral Component Interconnect-Express (PCIe) link.3. The processing node of claim 2 , wherein the management controller is accessed by the communication module via a PCIe endpoint.4. The processing node of claim 1 , wherein:the processor is further operable to generate network requests and to process responses to the network requests; andthe communication module is further operable to receive the network requests, to transmit over the communication link to a network interface controller of the server rack external to the processing node a network request, to receive over the communication link from the network interface controller network information associated with the network request, and to transmit the network ...

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Номер записи: 62

02-01-2014 дата публикации

COMPUTER SYSTEM AND ROUTING CONTROL METHOD

Номер: US20140006679A1

Автор: Eguchi Shuhei, Todaka Takashi, Yamagata Ryo

Принадлежит: Hitachi, Ltd.

The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port. 2. The computer system according to claim 1 ,wherein a set of SPAs specified by the SPA set setting means is in the range of SPAs to be destinations of packets that can pass through the external port from the inside of the switch to the outside, andwherein each of the external ports has a register for storing the SPA indicating that the own port is the external port.3. The computer system according to claim 1 , wherein the contents of the conversion means claim 1 , the SPA set setting means claim 1 , and the register are set in the initial setting by a management system connected by the plurality of PCIe switches.4. The computer system according to claim 1 ,wherein, a port (first port) of one switch (first switch) is connected to a port (second port) of another switch (second switch),wherein when a switch other than the first switch is connected to the second switch, a set of SPAs is set to the SPA set setting means of the first port, so as to include the SPA of the ports of the second switch and the next switch,wherein when a switch other than the first switch is not connected to the second switch, a set of SPAs is set to the SPA set setting means of the first port, so as ...

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Номер записи: 63

02-01-2014 дата публикации

Disk subsystem

Номер: US20140006680A1

Автор: Kazuhisa Aruga

Принадлежит: HITACHI LTD

A protocol controller disposed between switches in a fiber channel fabric switch circuit and disk drive units for converting a protocol to enable one-to-one connectivity established between controllers and disk drive units.

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Номер записи: 64

09-01-2014 дата публикации

INTERPOSER AND INTELLIGENT MULTIPLEXER TO PROVIDE A PLURALITY OF PERIPHERIAL BUSES

Номер: US20140013024A1

Автор: BARAKE Omar George Joseph, LAMM Mark Peter, SCHARKOV John Ivan

Принадлежит: RESEARCH IN MOTION LIMITED

A communication connector is described that provides an increase in the number and type of communication circuits available on an electronic device without increasing the number and type of physical connectors. The communication connector electrically includes a set of inputs to couple to both a USB 2.0 connector and a HDMI connector. A set of outputs from the communication connector provides a third connector with a pin out specification compatible with a USB 3.0 connector or a PCIe connector. 1. An electrical circuit connector , comprising:a first communication port with a first pin out specification compatible with an Universal Serial Bus (USB) version 2.0 interface, and the first pin out electrically coupled to a first set of conductors;a second communication port with a second pin out specification compatible with a High-Definition Multimedia Interface (HDMI) interface, and the second pin out electrically coupled to a second set of conductors; anda third communication port with a third pin out specification compatible with an Universal Serial Bus (USB) version 3.0 interface, and the third pin out electrically coupled to a third set of conductors, and the third set of conductors electrically coupled to at least a portion of both the first set of conductors and the second set of conductors.2. The electrical circuit connector of claim 1 , wherein the third set of conductors electrically coupled to the at least a portion of electrical conductors in both the first set of conductors and the second set of conductors are defined as SuperSpeed conductors in the USB 3.0 standard.3. The electrical circuit connector of claim 1 , wherein the third communication port is a Micro USB version 3.0 interface receptacle.4. The electrical circuit connector of claim 1 , wherein the first communication port is a Micro USB version 2.0 plug claim 1 , the second communication port is a Micro HDMI plug claim 1 , and the third communication port is a Micro USB version 3.0 receptacle.5. An ...

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Номер записи: 65

16-01-2014 дата публикации

Methods of providing access to i/o devices

Номер: US20140019649A1

Автор: Yves Constantin Tchapda

Принадлежит: Individual

A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. The method comprises, at a first control element receiving a data packet transmitted by one of said one or more computing devices, and determining whether said data packet comprises a command including a first logical identifier identifying one of said resources. If it is determined that said data packet comprises a command including a first logical identifier a second logical identifier is obtained, the second logical identifier being associated with said first logical identifier and identifying said one of said resources. A request including said second logical identifier is transmitted to a second control element, the second control element being arranged to identify a physical device associated with said second logical identifier and to forward said request to the identified physical device.

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Номер записи: 66

16-01-2014 дата публикации

METHOD FOR CONTROLLING I/O SWITCH, METHOD FOR CONTROLLING VIRTUAL COMPUTER, AND COMPUTER SYSTEM

Номер: US20140019667A1

Автор: Shimada Keita, Takamoto Yoshifumi, Tameshige Takashi, Uchida Tomohito

Принадлежит:

The present invention is provided with: computers provided with a processor, a memory, and an I/O interface; an I/O switch for connecting a plurality of the computers with an I/O adapter; a management computer for managing the I/O switch and the computers; and a first network for connecting the computers with the management computer. The I/O switch has a dedicated adaptor connected to the management computer. The management computer selects from the plurality of computers a computer for performing data transfer, commands the I/O switch to connect the I/O interface of the selected computer and the dedicated adaptor, transfers data between the selected computer, senses that data transfer with the selected computer has been completed, and commands the I/O switch to disconnect the dedicated adaptor from the I/O interface of the selected computer after completion of the data transfer with the selected computer has been sensed. 1. A method of controlling an I/O switch in a computer system , a computer including a processor, a memory, and an I/O interface;', 'the I/O switch for coupling the I/O interface of each of a plurality of the computers and an I/O adaptor to each other;', 'a management computer for managing the I/O switch and the plurality of the computers; and', 'a first network for coupling the plurality of the computers and the management computer to each other,, 'the computer system comprisingthe I/O switch transferring data between the management computer and the plurality of the computers,the I/O switch including a dedicated adaptor coupled to the management computer,the method comprising:a first step of selecting, by the management computer, the computer for transferring the data out of the plurality of the computers based on a predetermined condition;a second step of instructing, by the management computer, the I/O switch to couple the I/O interface of the selected computer and the dedicated adaptor to each other;a third step of transferring, by the ...

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Номер записи: 67

23-01-2014 дата публикации

INFORMATION APPARATUS, METHOD FOR SWITCHING SCREEN, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN SCREEN SWITCH PROGRAM

Номер: US20140025860A1

Автор: HARA Yasushi, OTSUKA Katsumi, Yasaki Masatomo

Принадлежит: FUJITSU LIMITED

The information apparatus runs a first operating system and a second operating system in parallel with each other thereon and includes a monitor, a memory, and a switch. The memory stores first screen data generated by a first application operating on the first operating system and second screen data generated by a second application operating on the second operating system in association with each other. The switch switches, when screen data to be displayed on the monitor is to be switched from screen data generated by the first application to screen data generated by the second application and when screen data having been displayed on the monitor before the switching is the first screen data, the first screen data to the second screen data stored in the memory in association with the first screen data. 1. An information apparatus that runs a first operating system and a second operating system in parallel with each other thereon , the apparatus comprising:a monitor;a memory that stores first screen data generated by a first application operating on the first operating system and second screen data generated by a second application operating on the second operating system in association with each other;a switch that switches, when screen data to be displayed on the monitor is to be switched from screen data generated by the first application to screen data generated by the second application and when screen data having been displayed on the monitor before the switching is the first screen data, the first screen data to the second screen data stored in the memory in association with the first screen data.2. The information apparatus according to claim 1 , wherein:the memory comprises a first region that stores the first screen data and the second screen data in association with each other, and a second region that stores screen data generated by each application operating on the first operating system and screen data generated by each application operating on the ...

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Номер записи: 68

23-01-2014 дата публикации

INPUT OUTPUT CONTROL DEVICE, INFORMATION PROCESSING SYSTEM, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN LOG COLLECTION PROGRAM

Номер: US20140025861A1

Автор: MIYAZAWA Kazuyoshi

Принадлежит: FUJITSU LIMITED

An input output (IO) control device connects a plurality of devices with each other, and includes a plurality of ports to which the plurality of devices are connected and a control unit that controls the plurality of ports with each other, and the control unit collects a log of a the collection target port designated by a log collection instruction among the plurality of ports when the log collection instruction is received from any one of the plurality of devices through a first port to which the corresponding device is connected among the plurality of ports. 1. An input output (IO) control device that connects a plurality of devices with each other , the IO control device comprising:a plurality of ports to which the plurality of devices are connected; anda control unit that controls the plurality of ports,wherein the control unit collects a log of a collection target port designated by a log collection instruction among the plurality of ports when the log collection instruction is received from any one of the plurality of devices through a first port to which the corresponding device is connected among the plurality of ports.2. The IO control device according to claim 1 ,wherein the collection target port rejects reception of a connection request from a port other than the collection target port to the collection target port during a log collection period of time in which the control unit collects a log.3. The IO control device according to claim 2 ,wherein the log collection instruction is transmitted by the device when a connection release process of the first port and a second port among the plurality of ports is performed in a state in which the first port is connected with the second port.4. The IO control device according to claim 3 ,wherein at least one of the first and second ports is included as the collection target port.5. The IO control device according to claim 3 ,wherein the log collection period of time is either a period of time until the control ...

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Номер записи: 69

06-02-2014 дата публикации

Methods and structure for reduced layout congestion in a serial attached scsi expander

Номер: US20140036699A1

Автор: Tejas Tayade

Принадлежит: LSI Corp

Methods and structure for reduced layout congestion in a switching device integrated circuit. A switching device such as a Serial Attached SCSI (SAS) expander comprises a switching circuit to couple any of a plurality (“N”) of physical links of the switching device with any other physical link of the switching device. The switching circuit comprises a first stage circuit adapted to couple any of the N physical links with a selected one of N/2 communication paths of the switching circuit and comprises a second stage circuit adapted to couple any of the N/2 communication paths with any of the N physical links. Since only N/2 communication paths may be active at any time in such a switching device, a control unit of the switching device tracks which of the N/2 communication paths are presently in use or unused so that an unused path may be selected for a new connection.

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Номер записи: 70

06-02-2014 дата публикации

Method and apparatus for enhancing universal serial bus applications

Номер: US20140040525A1

Автор: Jonas Ulenas

Принадлежит: Vetra Systems Corp

A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

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Номер записи: 71

06-02-2014 дата публикации

OPTIMIZED MULTI-ROOT INPUT OUTPUT VIRTUALIZATION AWARE SWITCH

Номер: US20140040527A1

Автор: Haider Shabbir, Kanakaraj Paulraj, Kanigicherla Balaji, Medeme Naga Murali, Pasumarthy Dhanumjai, Vaidya Tapan

Принадлежит: INEDA SYSTEMS PVT. LTD

In one implementation, an optimized multi-root input-output virtualization (MRIOV) aware switch configured to route data between multiple root complexes and I/O devices is described. The MRIOV aware switch may include two or more upstream ports and one or more downstream ports. Each of an upstream port and a downstream port may include a media access controller (MAC) configured to negotiate link width and link speed for exchange of data packets between the multiple root complexes and the I/O devices. Each of an upstream port and a downstream port may further include a clocking module configured to dynamically configure a clock rate of processing data packets based one or more negotiated link width and negotiated link speed, and a data link layer (DLL) coupled to the MAC configured to operate at the clock rate, wherein the clock rate is indicative of processing speed. 1102. An optimized multi-root input-output virtualization (MRIOV) aware switch () comprising:{'b': 108', '110', '108', '110, 'claim-text': [{'b': 118', '104', '106, 'a media access controller (MAC) () configured to negotiate a link width and a link speed for exchange of data packets between a plurality of root complexes () and a plurality of I/O devices ();'}, {'b': '116', 'a clocking module () configured to dynamically configure a clock rate of processing data packets based on one or more of the negotiated link width and the negotiated link speed; and'}, {'b': 114', '118, 'a data link layer (DLL) module () coupled to the MAC (), configured to operate at the clock rate, wherein the clock rate is indicative of a processing speed; and'}], 'a plurality of upstream ports () and a plurality of downstream ports (), each of the plurality of upstream ports () and each of the plurality of downstream ports () comprising{'b': 112', '108', '110', '104', '106, 'a MRIOV core switching module () coupled to the plurality of upstream ports () and the plurality of downstream ports (), configured to perform arbitration ...

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Номер записи: 72

13-02-2014 дата публикации

PARALLEL COMPUTER SYSTEM, CROSSBAR SWITCH, AND METHOD OF CONTROLLING PARALLEL COMPUTER SYSTEM

Номер: US20140047157A1

Автор: Ajima Yuichiro, ANDO Shun, Hiramoto Shinya, INOUE Tomohiro, Maeda Masahiro, Toyoda Yuta

Принадлежит:

A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors. 1. A parallel computer system , comprising:a plurality of processors including a first processor and a plurality of second processors; anda crossbar switch provided with a plurality of ports; whereinthe first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, andthe first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors.2. The parallel computer system according to claim 1 , whereineach of the plurality of processors is configured to:transmit an arbitration request, the arbitration request being a data transmission request, to a paired second port in a given state from among the plurality of ports, and in the case of receiving a transmit authorization from the second port, transmit the data to the second port, andtransmit the arbitration request to a third port different from the second port from among the plurality of ports, and in the case of receiving a transmit authorization from the third port, transmit the data to the third port.3. The parallel computer system according to claim 1 , ...

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Номер записи: 73

20-02-2014 дата публикации

PARALLEL COMPUTER SYSTEM, DATA TRANSFER DEVICE, AND METHOD FOR CONTROLLING PARALLEL COMPUTER SYSTEM

Номер: US20140052885A1

Автор: Ajima Yuichiro, ANDO Shun, Hiramoto Shinya, INOUE Tomohiro, Maeda Masahiro, Toyoda Yuta

Принадлежит:

A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases. 1. A parallel computer system comprising:a plurality of computation nodes each of which performs computation; anda data transfer device connected to the computation nodes, wherein a plurality of ports that include: an arbitration unit that selects a computation node to be paired when receiving an arbitration request from the computation node to be paired in a predetermined state, receives the arbitration request from any one or more of the computation nodes in the other cases, selects one of the computation nodes from which the arbitration request has been received, and returns transmission permission to the selected computation node; and a data transfer unit that receives data from the computation node selected by the arbitration unit and transfers the received data to another computation node; and', 'a combination determining unit that dynamically determines the computation node to be paired with each of the ports among the computation nodes, wherein, 'the data transfer device comprises a request transmission unit that transmits an arbitration request that is a request to ...

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Номер записи: 74

20-02-2014 дата публикации

MEMORY SYSTEM AND BUS SWITCH

Номер: US20140052903A1

Автор: NAGADOMI Yasushi

Принадлежит: KABUSHIKI KAISHA TOSHIBA

A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips. 110-. (canceled)11. A memory system comprising:a board;a package for a memory mounted on the board;a first nonvolatile memory in the package;a second nonvolatile memory in the package;a first signal line electrically connected to the first nonvolatile memory;a second signal line electrically connected to the second nonvolatile memory;an interface configured to communicate with a host;a first controller configured to control power applied to the memory system which includes the first nonvolatile memory and the second nonvolatile memory; anda second controller configured to control a load capacity of the first nonvolatile memory and the second nonvolatile memory according to a command from the host by controlling the first signal line and the second signal line, whereinthe second controller controls the load capacity of the first nonvolatile memory to be increased and the load capacity of the second nonvolatile memory to be reduced, when the first nonvolatile memory is accessed, while the power controlled by the first controller is applied, andthe second controller controls the load capacity of the first nonvolatile memory to be reduced and the load of the second nonvolatile memory to be increased, when the second nonvolatile memory is accessed while the power controlled by the first controller is applied.12. The memory system according to claim 11 , whereinthe second controller controls the load capacity of the first nonvolatile memory to be increased and the load capacity of the second ...

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Номер записи: 75

06-03-2014 дата публикации

SYSTEM AND METHOD FOR SIGNAL INPUT CONTROL AND VIDEO DEVICE THEREOF

Номер: US20140068136A1

Автор: Chen Chin-Huang, Hsu Shih-Shun

Принадлежит: AMTRAN TECHNOLOGY CO., LTD.

A system and method for signal input control and a video device thereof are provided, adapted for a control device controlling the signal input to the video device. The method includes the following steps: the control device provides a process information and a control command; the video device detects the control commands and receives the process information through a Display Data Channel (DDC); and the video device controls the switch unit to transmit the process information to the Extended Display Identification Data (EDID) ROM or the processor according to the control command. 1. A system for signal input control , adapted for a High Definition Multimedia Interface (HDMI) , the system comprising:a control device providing a process information and a control command; and a switch unit receiving the process information through a Display Data Channel (DDC);', 'an Extended Display Identification Data (EDID) ROM;', 'a processor; and', 'a detection circuit detecting the control command of the control device, the detection circuit controlling a connection mode of the switch unit in the video device according to the control command, the connection mode being respectively a normal mode and a specific mode, wherein the normal mode is for transmitting the process information to the EDID ROM through the switch unit, and the specific mode is for transmitting the process information to the processor through the switch unit., 'a video device connected to the control device through the HDMI, wherein the video device comprising2. The system for signal input control of claim 1 , wherein the control device comprises:a process unit providing the process information, the process information being transmitted to the switch unit of the video device through the DDC; anda control circuit providing the control command, the control command being a specific voltage, the specific voltage being an adjustable voltage, the switch unit being controlled by the detection circuit to transmit the ...

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Номер записи: 76

13-03-2014 дата публикации

INFORMATION PROCESSING DEVICE

Номер: US20140075064A1

Автор: MINEGISHI Kiyoshi

Принадлежит: RENESAS ELECTRONICS CORPORATION

An information processing device includes a first functional section having an external terminal, and a second functional section and a third functional section, which are commonly coupled to the external terminal of the first functional section. The first functional section includes a first internal circuit that is associated with the second functional section, a second internal circuit that is associated with the third functional section, a switch that can select the first internal circuit or the second internal circuit, and a switch control circuit that controls the operation of the switch. While the second functional section is enabled, the switch control circuit controls the switch so that the first internal circuit is coupled to the second functional section. While the third functional section is enabled, the switch control circuit controls the switch so that the second internal circuit is coupled to the third functional section. 1. An information processing device comprising:a first functional section having an external terminal; anda second functional section and a third functional section, which are commonly coupled to the external terminal of the first functional section,wherein the first functional section includes:a first internal circuit, which exerts a function associated with the second functional section;a second internal circuit, which exerts a function associated with the third functional section;a switch that can select the first internal circuit or the second internal circuit; anda switch control circuit that controls the operation of the switch,wherein, while the second functional section is enabled, the switch control circuit controls the switch so that the first internal circuit is coupled to the second functional section through the external terminal, and wherein, while the third functional section is enabled, the switch control circuit controls the switch so that the second internal circuit is coupled to the third functional section through ...

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Номер записи: 77

13-03-2014 дата публикации

Multi-core integrated circuit configurable to provide multiple logical domains

Номер: US20140075082A1

Автор: Durgesh Srivastava, Gerald Rogers, James A. COLEMAN, Scott M. OEHRLEIN

Принадлежит: Intel Corp

Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed.

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Номер записи: 78

13-03-2014 дата публикации

CONCURRENT REPAIR OF THE PCIE SWITCH UNITS IN A TIGHTLY-COUPLED, MULTI-SWITCH, MULTI-ADAPTER, MULTI-HOST DISTRIBUTED SYSTEM

Номер: US20140075083A1

Автор: Engebretsen David R., Holthaus Brian G., Kaus Jonathan L., Thiemann Eric G., Todd Robert W.

Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports. 1. A computer-implemented method to repair switch units in a distributed switch comprising a plurality of switch units , each switch unit of the plurality having at least one port for establishing connections according to a predefined interface , the method comprising: identifying a host connected to the first switch unit;', 'transmitting a first removal indication to the host to remove a connection between the host and the first switch unit; and', 'upon determining that: (i) the host is connected to the first switch unit through a downstream port of the first switch unit and (ii) the host has not acknowledged the first removal indication within a predefined amount of time, transmitting a second removal indication by operation of one or more computer processors, wherein the second removal indication emulates that the first switch unit is physically removed from the distributed switch, wherein the first switch unit is not physically removed from the distributed switch; and, 'responsive to receiving an indication to vary off a first switch unit of the plurality of switch units 'transmitting an add indication to the host to establish a connection between the host and the first switch unit.', 'responsive ...

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Номер записи: 79

13-03-2014 дата публикации

ASYNCHRONOUS CIRCUIT WITH SEQUENTIAL WRITE OPERATIONS

Номер: US20140075084A1

Автор: FONKOUA Alain, MONNET Yannick, RENAUDIN Marc, RJIMATI Yassine

Принадлежит:

The asynchronous circuit includes an input channel, a divergence operator connecting the input channel to a plurality of intermediate channels, a convergence operator gathering the intermediate channels into a single output channel, a main sequencer including a plurality of sequentially-activated control channels, each intermediate channel being associated to a control channel, and a switch arranged in a request path of one of the intermediate channels and connected to the last active control channel. The circuit further includes a memory circuit, arranged in each of the other intermediate channels, connected to the associated control channel and configured to transmit the request signal of the associated intermediate channel to the output channel and to modify an output state of the associated intermediate channel, by means of the main sequencer, without requiring any state change of the input channel. 1. An asynchronous circuit comprising a plurality of components connected by channels , each channel conveying a request signal and an acknowledgement signal , an input channel;', 'a divergence operator connecting the input channel to a plurality of intermediate channels;', 'a convergence operator gathering the intermediate channels in a single output channel;', 'a main sequencer comprising a plurality of sequentially-activated control channels, each intermediate channel being associated to a control channel;', 'a switch arranged in a request path of one of the intermediate channels, and connected to the last active control channel, whereby a transmission of the request signal of said intermediate channel to the output channel occurs last in the sequence; and', 'a memory circuit, arranged in each of the other intermediate channels, connected to the associated control channel and configured to transmit the request signal from the associated intermediate channel to the output channel; and, 'said asynchronous circuit further comprisingthe memory circuit being further ...

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Номер записи: 80

13-03-2014 дата публикации

METHOD AND APPARATUS FOR TRANSFERRING PACKETS BETWEEN INTERFACE CONTROL MODULES OF LINE CARDS

Номер: US20140075085A1

Автор: Froslev-Nielsen Lars, Hoyer Claus F., Korger Peter, Schroder Jacob J.

Принадлежит: MARVELL WORLD TRADE LTD.

An access system includes line cards. The line cards include first and second line cards. The first line card receives a first packet and includes a first interface control module that generates a first request signal to transfer the first packet. The first request signal includes an identifier of a second interface control module in the second line card. Crossbar modules are separate from the line cards and include first and second crossbar modules. The first crossbar module includes a first scheduler module. The second crossbar module transfers packets between a pair of the line cards. The packets include the first packet. The first scheduler module is separate from the line cards and, based on the first request signal, schedules the transfer of the packets from the first interface control module, through the second crossbar module, and to the second interface control module. 1. An access system comprising: a physical layer module configured to receive a first packet, and', 'a first interface control module configured to generate a first request signal to transfer the first packet, wherein the first request signal comprises an identifier of a second interface control module in the second line card; and, 'a plurality of line cards including a first line card and a second line card, wherein the first line card comprises'}a plurality of crossbar modules separate from the plurality of line cards, wherein the plurality of crossbar modules comprise a first crossbar module and a second crossbar module, wherein the first crossbar module comprises a first scheduler module, wherein the second crossbar module is configured to transfer a plurality of packets between a pair of the plurality of line cards, and wherein the plurality of packets includes the first packet,wherein the first scheduler module is separate from the plurality of line cards and the first scheduler module is configured to, based on the first request signal, schedule the transfer of the first packet or the ...

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Номер записи: 81

20-03-2014 дата публикации

PCI EXPRESS DEVICE AND LINK ENERGY MANAGEMENT METHOD AND DEVICE

Номер: US20140082251A1

Автор: Li Yansong

Принадлежит: Huawei Technologies Co., Ltd.

Embodiments of the present invention disclose a PCI express device, and a link energy management method and device. The method includes: obtaining, by a first device, adjustment information for performing adjustment processing on a current rate and/or bit width of a PCI express link; stopping, by the first device, data sending, and clearing a master enable bit of a configuration space command register of a second device at an opposite end of the link, so that the second device stops data sending after current data sending is finished; performing, by the first device, adjustment processing on the rate and/or bit width of the link according to the adjustment information; resuming, by the first device, the data sending, and resetting the master enable bit, so that the first device and the second device send and receive data again at a rate and/or bit width that is obtained after the adjustment processing. 1. A PCI express link energy management method , comprising:obtaining, by a first device, adjustment information for performing adjustment processing on a current rate and/or bit width of a PCI express link;stopping, by the first device, data sending, and clearing a master enable bit of a configuration space command register of a second device at an opposite end of the link, so that the second device stops data sending after current data sending is finished;performing, by the first device, adjustment processing on the rate and/or bit width of the link according to the adjustment information; andresuming, by the first device, the data sending, and resetting the master enable bit, so that the first device and the second device send and receive data again at a rate and/or bit width that is obtained after the adjustment processing.2. The method according to claim 1 , wherein the performing claim 1 , by the first device claim 1 , adjustment processing on the bit width of the link according to the adjustment information specifically is:performing, by the first device, the ...

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Номер записи: 82

03-04-2014 дата публикации

Back-Off Retry with Priority Routing

Номер: US20140095754A1

Автор: Christopher McCarty, Jeffrey J. Gauvin, Stephen B. Johnson, William K. Petty

Принадлежит: LSI Corp

A method for back-off retry with priority routing includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the SAS expander via at least one inter-expander link (IEL), the expander including a first SAS expander and at least one additional SAS expander. The method includes routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

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Номер записи: 83

03-04-2014 дата публикации

REPRODUCTION DEVICE AND REPRODUCTION SYSTEM

Номер: US20140095761A1

Автор: FUJIWARA Takanori, Hirose Junichi, SAKABE Yoshinori, Suzuki Atsuyuki

Принадлежит:

A reproduction device includes a reproduction unit, communication paths, and a communication-path control unit. The reproduction unit is configured to be able to alternatively reproduce content items supplied from sources. The communication paths respectively correspond to the sources. The reproduction unit is connected to the sources via the respective communication paths. The communication-path control unit invalidates, when receiving an instruction to switch to the source having content to be reproduced by the reproduction unit, communication via the communication path corresponding to the source before the switching among the communication paths. 1. A reproduction device comprising:a reproduction unit configured to be able to alternatively reproduce content items respectively supplied from sources;communication paths that respectively correspond to the sources, the reproduction unit being connected to the sources via the respective communication paths; anda communication-path control unit configured to invalidate, when receiving an instruction to switch to the source having content to be reproduced by the reproduction unit, communication via the communication path corresponding to the source before the switching among the communication paths.2. The reproduction device according to claim 1 , wherein the communication-path control unit uses the communication path of finally established communication among the communication paths more preferentially than the communication path of communication established before the finally established communication is established.3. The reproduction device according to claim 1 , wherein the communication-path control unit sets one of the communication paths as a communication path for which communication is not invalidated even when the communication-path control unit receives the instruction to switch to the source.4. The reproduction device according to claim 2 , wherein the communication-path control unit sets one of the ...

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Номер записи: 84

10-04-2014 дата публикации

MULTI-PROCESSOR DEVICE

Номер: US20140101353A1

Автор: ISHIMI Koichi

Принадлежит: RENESAS ELECTRONICS CORPORATION

The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip. 118-. (canceled)19. A semiconductor device comprising:a plurality of a first type of processors disposed in a first layout region of a single chip in plan view and being controlled using a first clock, the signal chip having a rectangular shape with four sides in plan view;a plurality of a second type of processors disposed separately from the plurality of the first type of processors in a second layout region of the single chip in plan view, each said second type of processor having a different architecture from said first type of processors and being controlled using a second clock which differs in frequency or phase from the first clock;a first bus provided over the single chip to which the plurality of the first type of processors are coupled;a second bus provided over the single chip to which the plurality of the second type of processors are coupled;a first external bus interface provided over the single chip, to which a first external bus provided external to the single chip is coupled; anda second external bus interface provided over the single chip, to which a second external bus provided external to ...

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Номер записи: 85

10-04-2014 дата публикации

METHOD AND PROTOCOL FOR HIGH-SPEED DATA CHANNEL DETECTION CONTROL

Номер: US20140101357A1

Автор: Stolitzka Dale, XIONG Wei

Принадлежит: Samsung Display Co., Ltd.

A system capable of bi-directional data transfer, the system including a host configured to send downstream data to a peripheral and to receive upstream data from the peripheral, a main link coupled to the host and configured to transfer the downstream data from the host to the peripheral, and an auxiliary link coupled to the host and including a first auxiliary link lane for transferring the upstream data from the peripheral to the host in a first mode, and for transferring the downstream data from the host to the peripheral in a second mode, wherein the host is configured to engage in one or more handshake processes with the peripheral to cause the auxiliary link to switch between the first and second modes. 1. A system capable of bi-directional data transfer , the system comprising:a host configured to send downstream data to a peripheral and to receive upstream data from the peripheral;a main link coupled to the host and configured to transfer the downstream data from the host to the peripheral; andan auxiliary link coupled to the host and comprising a first auxiliary link lane for transferring the upstream data from the peripheral to the host in a first mode, and for transferring the downstream data from the host to the peripheral in a second mode,wherein the host is configured to engage in one or more handshake processes with the peripheral to cause the auxiliary link to switch between the first and second modes.2. The system of claim 1 , wherein the main link comprises d main link lanes claim 1 ,wherein the auxiliary link comprises u auxiliary link lanes comprising the first auxiliary link lane, andwherein d and u are natural numbers.3. The system of claim 2 , wherein between 1 and u of the auxiliary link lanes are used for transferring the downstream data from the host to the peripheral during the second mode claim 2 , andwherein between 0 and (u−1) auxiliary link lanes are used for transferring the upstream data from the peripheral to the host during the ...

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Номер записи: 86

06-01-2022 дата публикации

Industrial control system having multi-layered control logic execution

Номер: US20220004156A1

Автор: Jason Thomas URSO, Jethro Francis Steinman, Joseph J Pane, Joseph Pradeep FELIX, Nagaraja Sundaresh, Paul Francis Mclaughlin, Ram Mohan Anugu

Принадлежит: Honeywell International Inc

A process control system includes a process controller level including at least one process controller, and an input/output (I/O) module level including at least one I/O module. The process controller level and the I/O module level are communicatively coupled. and each include control logic comprising control hardware or algorithm blocks. The control logic in the process controller level and the I/O module level are configured to execute and exchange data to perform process control for a process run by the process control system in a distributed fashion across the process controller level and the I/O module level.

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Номер записи: 87

06-01-2022 дата публикации

COMMANDS TO SELECT A PORT DESCRIPTOR OF A SPECIFIC VERSION

Номер: US20220004515A1

Автор: Guendert Stephen Robert, Riedy Dale F.

Принадлежит:

A port descriptor version of a port descriptor to be obtained is selected. An indication of the port descriptor version is provided in a command to be preceded before another command used to obtain the port descriptor. The other command uses the port descriptor version to obtain the port descriptor. The port descriptor is obtained, and the port descriptor includes information relating to a port to be used in communication within the computing environment. 1. A computer program product for facilitating communication within a computing environment , the computer program product comprising: selecting a port descriptor version of a port descriptor to be obtained;', 'providing an indication of the port descriptor version, the port descriptor version to be used by a command to obtain the port descriptor; and', 'obtaining the port descriptor, wherein the port descriptor includes information relating to a port to be used in communication within the computing environment., 'one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method comprising2. The computer program product of claim 1 , wherein the providing includes providing the indication of the port descriptor version in an identify command issued by an operating system of a processor of the computing environment to a communication component of the computing environment claim 1 , the identify command providing information including the port descriptor version to be used by the command.3. The computer program product of claim 2 , wherein the command comprises a read command to be used to obtain the port descriptor and provide the port descriptor to the operating system.4. The computer program product of claim 3 , wherein the read command is to provide the port descriptor of the port descriptor version being requested claim 3 , based on the communication component supporting the port descriptor version.5. The computer ...

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Номер записи: 88

05-01-2017 дата публикации

Connecting circuitry and computing system having the same

Номер: US20170003709A1

Автор: Ming-Chun Lee, Syu-Siang Lee, Zh-Wei Zhang

Принадлежит: Wistron Corp

A connecting circuitry is disclosed. The connecting circuitry is coupled to a storage device, a first motherboard and a second motherboard, and controlled by a first control signal and a second control signal to switch over to a first mode, to a second mode and to a third mode. The connecting circuitry includes a first exchanging unit; a second exchanging unit; and a first multiplexing unit, electrical connected to the first exchanging unit and the second exchanging unit; wherein the first mode is the storage device being only accessed by the first motherboard, the second mode is the storage device being only accessed by the second motherboard, and the third mode is the storage device being accessed by both the first motherboard and the second motherboard.

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Номер записи: 89

07-01-2016 дата публикации

MICROCONTROLLER WITH MULTIPLE POWER MODES

Номер: US20160004292A1

Автор: CULSHAW CARL, DEVINE ALAN, Pathak Akshay K., Robertson Alistair P., Sharda Garima

Принадлежит: Freescale Semiconductor, Inc.

A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode. 1. An integrated circuit (IC) operable in a high power mode and a low power unit (LPU) run mode , comprising: a first set of circuits;', 'a first set of cores having at least one core that operates when the IC is in the high power mode and is powered off when the IC is in the LPU run mode; and', 'a first cross-bar bus, connected between the first set of cores and the first set of circuits, that configures a connection between the first set of cores and the first set of circuits; and, 'a primary domain including second and third sets of circuits;', 'a second set of cores having at least one core that operates when the integrated circuit is in the high power and LPU run modes; and', 'a switching module, connected to the second set of cores, the first cross-bar bus, and the second and third sets of circuits, that connects the second set of cores to at least one of the first, second and third sets of circuits by way of the first cross-bar bus when the IC is in the high power mode, and connects the second set of cores directly to at least one of the second and third sets of circuits when the IC is in the LPU run mode., 'a LPU domain including2. The IC of ...

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Номер записи: 90

05-01-2017 дата публикации

LOW-POWER RECONFIGURABLE ARCHITECTURE FOR SIMULTANEOUS IMPLEMENTATION OF DISTINCT COMMUNICATION STANDARDS

Номер: US20170003986A1

Автор: Garon Gilad, Soloman Doron

Принадлежит:

A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms is disclosed. The chip architecture comprises a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; and a plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols. Preferably, at least some of the same megafunctions are used with algorithms of two or more protocols. 1. A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of algorithms , comprising:a plurality of megafunctions, each in the form of reusable, reconfigurable functional blocks for use in implementing different algorithms necessary for implementing the physical layer of each of the communication protocols; anda plurality of switches configured to respond to select control signals so as to interconnect the necessary megafunctions for processing the signals encoded with each of the protocols;wherein at least some of the same megafunctions are used with algorithms of two or more protocols.2. The chip architecture according to claim 1 , wherein at least some of the megafunctions are parameterized claim 1 , the parameters of at least some of the megafunctions are adapted to be dynamically changed depending on the communication protocol.3. The chip architecture according to claim 2 , further including buses interconnecting the megafunctions claim 2 , and wherein the size of at least some of the buses are adapted to be dynamically changed depending on the communication protocol.4. The chip architecture according to claim 2 , wherein the control signals for ...

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Номер записи: 91

05-01-2017 дата публикации

FLEXIBLE MOBILE DEVICE CONNECTIVITY TO AUTOMOTIVE SYSTEMS WITH UBS HUBS

Номер: US20170004103A1

Автор: Petku Craig Allan, Voto Robert M., Yeda Shyambabu

Принадлежит:

A system which is configured to enable a vehicle's embedded USB Host system to connect to multiple mobile devices through a USB Hub, regardless of whether the mobile devices are configured to act as USB Hosts or USB Devices, without the need to add or provide OTG controllers in the system or additional vehicle wiring, or inhibiting the functionality of any consumer devices operating in USB Device mode connected to a vehicle system Hub while another consumer device connected to the same Hub operates in USB Host mode. Preferably, the system is configured to provide that no additional cabling is required, and no hardware changes are required to be made to the HU. The system can be employed between a vehicle's embedded USB Host, USB Hub and at least one consumer accessible USB port. In the case where the consumer device is acting as a USB Host, signals between the consumer device and the vehicle's embedded USB Host are processed through a bridge, thereby rendering the consumer device compatible with the vehicle's embedded USB Host. 1. A Universal Serial Bus (USB) hub module , comprising:a first USB port configured to be connected to a USB host;a second USB port configured to be connected to a consumer device;a USB hub interconnected to the first USB port and the second USB port;a USB bridge interconnected to the USB hub; anda USB routing switch interconnected to the USB bridge, the USB hub, and the second USB port, wherein the USB routing switch is configured to connect the second USB port to the first USB port through the USB bridge, thereby supporting bidirectional initiation of communication between the USB host and the consumer device when the consumer device connected to the second USB port is in a USB host mode and wherein the USB routing switch is configured to connect the second USB port directly to the first USB port through the USB hub, thereby supporting only communication initiated by the USB Host when the consumer device connected to the second USB port is ...

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Номер записи: 92

05-01-2017 дата публикации

USB SWITCH AND CONTROL METHOD THEREOF

Номер: US20170004104A1

Автор: LEE Chihte, Meyers Chistopher M., Ni Jie

Принадлежит:

A universal serial bus (USB) switch includes an upstream port, first downstream ports, M second downstream ports, and a switch engine. The upstream port is configured to have a first bandwidth. Each of the first downstream ports is configured to have a second bandwidth. Each of the M second downstream ports is configured to have a third bandwidth, and M is an integer, and M=0−N, where N is a positive integer greater than or equal to 1. The switch engine is configured to route signals between the upstream port and the totality of first downstream ports, and alternatively to route the signals between the upstream port and one of the M second downstream ports. The third bandwidth is greater than the second bandwidth, and the first bandwidth is a multiple of the second bandwidth. 1. A universal serial bus (USB) switch , comprising:an upstream port configured to have a first bandwidth;a plurality of first downstream ports, wherein each of the first downstream ports is configured to have a second bandwidth;M second downstream ports, wherein each of the M second downstream ports is configured to have a third bandwidth, M is an integer, and M=0−N, where N is a positive integer greater than or equal to 1; anda switch engine configured to route a plurality of signals between the upstream port and the totality of first downstream ports, and alternatively to route the signals between the upstream port and one of the M second downstream ports,wherein the third bandwidth is greater than the second bandwidth, and the first bandwidth is a multiple of the second bandwidth.2. The USB switch of claim 1 , wherein the first downstream ports are configured to communicate with a plurality of USB 2.0 devices claim 1 , and the M second downstream ports are configured to communicate with M USB 3.0 devices.3. The USB switch of claim 1 , wherein the upstream port is configured to communicate with a host device via a USB 3.0 interface or a USB 3.1 interface without USB 2.0 connectivity.4. The ...

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Номер записи: 93

05-01-2017 дата публикации

Networking using PCI Express

Номер: US20170004107A1

Автор: George Susan, Madathilparambil George George, Thomas Mammen

Принадлежит:

Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system. 1. A method implemented in a first network apparatus used for forwarding network packets , wherein said first network apparatus is used for interconnecting network nodes in a network , wherein said first network apparatus uses PCI Express transactions for communicating to a PCI Express root bridge connected to it , wherein said first network apparatus behaves like a PCI Express end node , said method comprising:a) receiving a first address of a network packet;b) using said first address of said network packet for reading said network packet;c) receiving said network packet in a first PCI Express read completion; andd) writing said network packet to memory in a destination node of said network packet.2. The method of further comprising: receiving said first address of said network packet in a second PCI Express read completion.3. The method of further comprising: receiving a second destination address claim 1 , wherein said second destination address is used to write said network packet to memory in said destination node.4. The method of comprising: writing said network packet to memory in said destination node of said network packet using a ...

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Номер записи: 94

07-01-2016 дата публикации

AUTOMATIC TEST PATTERN GENERATION FOR A RECONFIGURABLE INSTRUCTION CELL ARRAY

Номер: US20160004617A1

Автор: Abdelmuti Ihab, Boynapalli Venugopal, Fang Joseph Weizhou, Khawam Sami, Macha Raju, Nousias Ioannis, Rao Hari Madhava

Принадлежит:

An instruction cell array is provided that comprises an array of tiles. Each tile includes a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels. In addition, each tile includes an instruction cell comprising a plurality of dedicated logic gates for producing an instruction cell output from selected ones of the tile's input channels. Each I/O port is configured to select from the tile's instruction cell output and from the input channels for the remaining I/O ports for the tile to form the I/O port's output channels. To prevent combinatorial loops during an automatic test pattern generation (ATPG) of the array, the instruction cell array disclosed herein is configured in the testing mode such at least a subset of the I/O ports for each tile prevent any of their output channels from being formed as combinatorial signals. 1. An array , comprising:a plurality of tiles, each tile including:a set of input/output (I/O) ports for switching between a plurality of input channels and a plurality of corresponding output channels; andan instruction cell comprising a plurality of logic gates for producing an instruction cell output from selected ones of the input channels;wherein each I/O port is configured to select from the instruction cell output and from the input channels for the remaining I/O ports to form the I/O port's output channels, and wherein a subset of the I/O ports are configured in a testing mode to prevent any of their output channels from being combinatorial signals.2. The array of claim 1 , wherein each I/O port includes:a plurality of first multiplexers corresponding to the I/O port's plurality of output channels; each first multiplexer being configured in a normal mode of operation to select from the I/O port's tile's instruction cell output and from the corresponding input channel from each of the remaining I/O ports in the I/O port's tile to form an output signala plurality ...

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Номер записи: 95

07-01-2016 дата публикации

Computer System and A Computer Device

Номер: US20160004652A1

Автор: Glickman Jonathan

Принадлежит:

A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system. 1. A computer system comprising:a first board having an I/O controller hub including a main communication chipset;a common bus; and a memory operative to host a Sibling operating system, and', 'at least one CPU coupled to said memory, said Sibling board configured without a Sibling chipset;, 'a plurality of Sibling boards coupled to said first board by said common bus, each of the Sibling boards comprising,'}wherein at least one of the plurality of Sibling boards functions as a processing unit of said first board, and at least one of said Sibling boards is coupled to and shares said I/O controller hub.2. The computer system of claim 1 , wherein said I/O controller hub includes a main network device; and wherein at least one of said Sibling boards is coupled to and shares said main network device.3. The computer system of claim 2 , wherein at least one of said Sibling boards is directly coupled to and shares said main network device claim 2 , and is without an external I/O circuit.4. The computer system of claim 1 , wherein said common bus physically and electrically connects the plurality of said Sibling boards to said first board.5. The computer system of claim 1 , wherein said common bus couples the plurality of ...

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Номер записи: 96

07-01-2016 дата публикации

BUS CONTROLLER, DATA FORWARDING SYSTEM, AND METHOD FOR CONTROLLING BUSES

Номер: US20160004659A1

Автор: Anbai Toshihisa, Otoshi Akiko

Принадлежит:

The first buffers forward data from the first device to the respective corresponding second devices through the respective buses while the second buffers forward data from the respective corresponding second devices to the first device through the respective buses. In response to a simultaneous data transmission request to simultaneously transmit data from the first device to the second devices, the switch controller switches the first buffer into a data-forwarding enable state, and switches the second buffer into a data-forwarding disable state, for simultaneous data transmission from the first device to the plurality of the second devices. The pseudo-response generator generates pseudo-response signals acting as a plurality of response signals that the second devices transmit to the first device as a result of the simultaneous data transmission, and transmits the plurality of the pseudo-response signals to the first device. This configuration achieves simultaneous access to multiple devices. 1. A bus controller for controlling a plurality of buses each forwarding data between a first device and one of a plurality of second devices , the bus controller comprising:a first buffer and a second buffer being disposed on each of the plurality of buses, the first buffer forwarding data from the first device to the corresponding second device through the bus, the second buffer forwarding data from the corresponding second device to the first device through the bus;a switch controller that, in response to a simultaneous data transmission request to simultaneously transmit data from the first device to the plurality of second devices, switches the first buffer into a data-forwarding enable state that allows data transmission from the first device to the corresponding second device, and switches the second buffer into a data-forwarding disable state that prohibits data transmission from the corresponding second device to the first device, for simultaneous data transmission ...

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Номер записи: 97

07-01-2016 дата публикации

WIRELESS TRANSMISSION AND VIDEO INTEGRATED APPARATUS

Номер: US20160004662A1

Автор: CHANG Nai-Chien

Принадлежит:

A wireless transmission and video integrated apparatus includes a hub module, a video module and a wireless module. The hub module includes a hub unit, a first expansion interface, a second expansion interface and a transmission interface. The video module includes a first connection interface, an image processing unit, an image acquisition unit and a microphone unit. The video module is electrically connected to the first expansion interface of the hub module through the first connection interface. The wireless module includes a second connection interface, a wireless communication unit and an antenna unit. The wireless module is electrically connected to the second expansion interface of the hub module through the second connection interface. The video module and the wireless module are integrated as a whole through the hub module, and then electrically connected to an electronic apparatus through the transmission interface to help with the assembly. 1. A wireless transmission and video integrated apparatus assembled to an electronic apparatus and electrically connected to a main board of the electronic apparatus , the wireless transmission and video integrated apparatus comprising:a video module having a first circuit board, an image acquisition unit, an image processing unit, a microphone unit and a first connection interface, the image acquisition unit electrically connected to the first circuit board and acquiring an image signal, the image processing unit electrically connected to the first circuit board and the image acquisition unit, the image processing unit processing the image signal with an analog-to-digital conversion, the microphone unit electrically connected to the first circuit board and acquiring an audio signal, the first connection interface electrically connected to the first circuit board, the image processing unit and the microphone unit, the first connection interface receiving and outputting the image signal and the audio signal;a wireless ...

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Номер записи: 98

04-01-2018 дата публикации

POWER ADAPTER

Номер: US20180004266A1

Автор: JHONG JIA-CIAO

Принадлежит:

A power adapter includes an universal serial bus (USB) interface, a control unit and a charging circuit. The universal serial bus (USB) interface connected to the electronic device, to receive level signals from the electronic device. The control unit electronically connected to the USB interface, to output a control signal according to the level signals received by the USB interface. The charging circuit electronically connected to the control unit and receiving the external power signal, to determine whether or not to output the external power signal to the electronic device according to the control signal outputted by the control unit. 1. A power adapter for charging an electronic device according to an external power signal , the power adapter comprising:an universal serial bus (USB) interface to be connected to the electronic device, to receive level signals from the electronic device;a control unit electronically connected to the USB interface, to output a control signal according to the level signals received by the USB interface; anda charging circuit electronically connected to the control unit and to receive the external power signal, to determine whether or not to output the external power signal to the electronic device according to the control signal outputted by the control unit.2. The power adapter of claim 1 , wherein the control unit comprises:a first port and a second port, the first port and the second port of the control unit electronically connected to the USB interface, to receive the level signals from the electronic device.3. The power adapter of claim 2 , wherein in response to the first port and the second port of the control unit being logic 1 signals claim 2 , the control unit controls that the charging circuit outputs the external power signal to the electronic device.4. The power adapter of claim 3 , further comprising:a first resistor, a second resistor and an auxiliary power port; whereinone end of the first resistor and one end of ...

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Номер записи: 99

04-01-2018 дата публикации

METHODS FOR INTELLIGENT LOAD BALANCING AND HIGH SPEED INTELLIGENT NETWORK RECORDERS

Номер: US20180004435A1

Автор: Allen Maxwell John, Coddington Anthony, Donnelly Stephen Frank, Earl David William

Принадлежит: Endace Technology Limited

A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device. 131-. (canceled)32. A high speed intelligent network recording system for recording a plurality of flows of network packets into a computer network , the high speed intelligent network recording system comprising: an enclosure,', 'a backplane printed board (PCB) mounted in the enclosure, and', 'a plurality of controller cards mounted in the enclosure coupled to the backplane PCB;', 'and, 'a controller unit having'} an enclosure,', 'a backplane printed board (PCB) mounted in the enclosure,', 'a plurality of drive trays mounted in the enclosure coupled to the backplane PCB, and', 'a plurality of pluggable storage drives coupled to each of the plurality of drive trays;, 'a storage unit coupled in communication to the controller unit, the storage unit including'}wherein each controller card in the controller unit includes a first microcomputer coupled in communication with a plurality of storage devices in the storage unit.33. The high speed intelligent network recording system of claim 32 , whereinthe enclosure of the controller unit us a 1U sized computer enclosure and the storage unit is inclusively between a 3U sized computer enclosure and a 6U sized computer enclosure.34. The high speed intelligent network recording system of claim 32 , further comprising:a high speed network switch coupled between the controller unit and the storage unit to couple the controller unit and the storage unit in communication together.35. The high speed ...

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Номер записи: 100