ПРИОСТАНОВКА И/ИЛИ РЕГУЛИРОВАНИЕ ПРОЦЕССОВ ДЛЯ РЕЖИМА ОЖИДАНИЯ С ПОДКЛЮЧЕНИЕМ

Изобретение относится к по меньшей мере одной системе и/или одному методу присваивания классификации управления питанием, по меньшей мере одному процессу, связанному с компьютерной средой, перевода компьютерной среды в режим ожидания с подключением на основании классификаций управления питанием, присвоенных процессам, и перевода компьютерной среды из режима ожидания с подключением в режим выполнения. Способ содержит этапы, на которых: идентифицируют процесс, которому должна быть присвоена классификации управления питанием. Присваивают классификацию управления питанием, например, привилегированный, регулируемый и/или приостанавливаемый, которая может быть присвоена процессам на основании различных факторов, например, таких как: обеспечивает ли процесс требуемые функции, и/или обеспечивает ли процесс функции, используемые для базового режима работы компьютерной среды. Таким образом, компьютерную среду можно переводить в маломощный режим ожидания с подключением, в котором возможно продолжение ...

СПОСОБ, УСТРОЙСТВО И СИСТЕМА УМЕНЬШЕНИЯ ВРЕМЕНИ ВОЗОБНОВЛЕНИЯ РАБОТЫ ДЛЯ КОРНЕВЫХ ПОРТОВ И КОНЕЧНЫХ ТОЧЕК, ИНТЕГРИРОВАННЫХ В КОРНЕВЫЕ ПОРТЫ

Группа изобретений относится к области вычислительной техники и может быть использована для возобновления работы для корневых портов и конечных точек, интегрированных в корневые порты. Техническим результатом является уменьшение времени перехода в рабочее состояние. Устройство содержит логику восстановления для: определения того, что устройство в состоянии низкой мощности; инициирования перехода устройства из состояния низкой мощности в активное состояние, при этом определено фиксированное минимальное время восстановления для переходов из состояния низкой мощности в активное состояние; идентификации возможности устройства, соответствующей переходу указанного устройства из состояния низкой мощности в активное состояние, и завершения перехода устройства из состояния низкой мощности в активное состояние по меньшей мере частично на основе указанной возможности, при этом переход подлежит завершению до истечения фиксированного минимального времени восстановления; при этом указанная возможность ...

РАВНОПРАВНОЕ РАЗДЕЛЕНИЕ СИСТЕМНЫХ РЕСУРСОВ В ИСПОЛНЕНИИ РАБОЧЕГО ПРОЦЕССА

Способ может быть применен на практике в распределенном вычислительном окружении, которое предоставляет вычислительные ресурсы множеству арендаторов. Технический результат заключается в предотвращении запуска рабочих нагрузок, превышающих некоторую продолжительность. Способ включает в себя действия для выделения ограниченного множества системных ресурсов арендаторам. Способ включает в себя идентификацию части ресурса. Способ дополнительно включает в себя идентификацию выполняющейся рабочей нагрузки арендатора. Характеристики контрольных точек идентифицируются для исполняющейся рабочей нагрузки арендатора. На основе характеристик контрольных точек и части ресурса идентифицируется событие вытеснения задачи. 3 н. и 17 з.п. ф-лы, 6 ил.

СПОСОБ И АППАРАТ ДЛЯ ПРОБУЖДЕНИЯ ЭЛЕКТРОННОГО УСТРОЙСТВА

Изобретение относится к области управления электронными устройствами, имеющими средства беспроводной связи, а именно к пробуждению электронного устройства, находящегося в режиме энергосбережения. Техническим результатом является обеспечение возможности быстрой удаленной активизации спящего электронного устройства за счет широковещательной передачи команды пробуждения, не требующей установления соединения с пробуждаемым устройством. Для этого осуществляют получение целевого электронного устройства в той же целевой локальной сети, что и пробуждаемое электронное устройство, и отправляют команду пробуждения целевому электронному устройству так, что целевое электронное устройство широковещательно передает в целевой локальной сети сообщение пробуждения для пробуждения пробуждаемого электронного устройства в соответствии с командой пробуждения. При этом определение целевой локальной сети, к которой обращается пробуждаемое электронное устройство, осуществляют в соответствии с предварительно утвержденным ...

СПОСОБ ЭКСПЛУАТАЦИИ ПОЛЬЗОВАТЕЛЬСКОГО ТЕРМИНАЛА СЕЛЬСКОХОЗЯЙСТВЕННОЙ МАШИНЫ И СЕЛЬСКОХОЗЯЙСТВЕННАЯ МАШИНА

ПРИОСТАНОВКА И/ИЛИ РЕГУЛИРОВАНИЕ ПРОЦЕССОВ ДЛЯ РЕЖИМА ОЖИДАНИЯ С ПОДКЛЮЧЕНИЕМ

... 1. Способ присваивания классификации управления питанием процессу, содержащий этапы, на которых:идентифицируют процесс, которому должна быть присвоена классификации управления питанием; иприсваивают классификацию управления питанием процессу, при этом присваивание содержит этапы, на которых:определяют, управляет ли жизненным циклом процесса, по меньшей мере, одно из процесса и компонента управления жизненным циклом, и тогда присваивают процессу классификацию привилегированного;определяют, можно ли процесс приостановить без отказа компьютерной системы, и не требуются ли ограниченные динамические функции, ассоциированные с процессом, и тогда присваивают процессу классификацию приостанавливаемого;определяют, можно ли процесс регулировать без отказа компьютерной системы и требуются ли ограниченные динамические функции, ассоциированные с процессом, и тогда присваивают процессу классификацию регулируемого; иопределяют, невозможно ли процесс приостановить или регулировать без отказа компьютерной ...

Hibernationssystem für Netzwerk

Informationsverarbeitungssystem und Verfahren

Tischcomputer-Anordnung mit Halt/Wiederaufnahmenfunktion

Tranfering appliccation state across devices with checkpoints

Inter-processor communication

System and method for improving the efficiency, comfort and/or reliability in operating systems.

Although MS Windows (in its various versions) is at present the most popular OS (Operating System) in personal computers, after years of consecutive improvements there are still various issues which need to be improved, which include for example issues of efficiency, comfort, and/or reliability. The present invention tries to solve the above problems in new ways that include considerable improvements over the prior art. Preferably the system allows for example a "Reset" function, which means that preferably an Image of the state of the OS (including all loaded software) is saved immediately after a successful boot on the disk or other non-volatile memory and is preferably automatically updated when new drivers and/or software that change the state after a boot are added, so that if the system gets stuck it can be instantly restarted as if it has been rebooted. Other features include for example solving the problem that the focus can be grabbed while the user is typing something, allowing ...

Method and apparatus for enhancing a hibernate and resume process using user space synchronization

Before hibernating a computing device (102), system software components (116) are notified of an upcoming hibernation process. The notifications are conveyed through an application program interface (API) (114). At least a portion of the system software components (116) can perform one or more pre-hibernation activities to place that system software component (116) in a ready-to-resume state. Each system software component indicates when it is ready for hibernation. Responsive to receiving the indication from each of the system software components (116), the hibernation process can complete. The completed hibernation process creates a snapshot (122) in nonvolatile memory. The snapshot (122) saves state information (124) for each of the system software components (116). The state information (124) is for the ready-to-resume state of the system software components (116). The computing device (102) can be restored after hibernation using a resume process (130), which reads the state (124) ...

Power management of processor cache during processor sleep

A control circuit 30 is configured to transmit a set of operations to a circuit block 18A, which is being powered up after being powered down, in order to reinitialize the circuit block. The circuit block may be a cache coupled to one or more processors 16, and the operations may be connected to configuration registers 56A-D within the cache. The operations may be stored in a memory 60 (e.g. a set of registers) to which the control circuit is coupled. The control circuit is also configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. This allows the circuit block to be powered up or powered down during times that the processors in the system are powered down (and thus software is not executable at the time), without requiring the waking of the processors for the power up/power down event, and therefore conserving power.

Hibernation based on page source

Activating an electronic device

An electronic device 101 comprising: a processor 103 having a motion activation mode and an operating mode; an orientation sensor 107 operable to detect the orientation of the device, and a clock 105 configured to, when the processor is in the motion activation mode, periodically power-up the processor; wherein the processor is configured to, when powered-up in its motion activation mode, obtain a measurement of the orientation of the device from the orientation sensor; store the obtained measurement; and process the obtained measurement in dependence on one or more stored measurements of the orientation of the device so as to determine whether the obtained measurement and the one or more stored measurements are indicative of a predetermined sequence of orientations of the device: the processor being configured to transition from its motion activation mode to its operating mode in response to determining that the obtained measurement and the one or more stored measurements are indicative ...

Power control circuitry for controlling power domains

Autonomous core perimeter for low power processor states

SLEEP CONDITION TRANSITION

Methods and apparatus for dynamic endpoint generators and dynamic remote object discovery and brokerage

The system and method disclosed herein is a dynamic endpoint generator that enables a client device or application to consume business objects. Business objects expose a single logical data structure and view of a business object as well as a single set of logical methods that are associated with the business object. The business object is a dynamic business object whose definition can be changed by either adding or removing data or actions without the need to involve technical or development resources to reconfigure or recompile the actual objects. The endpoint generator provides updated endpoint information automatically without the need for manual generation of endpoint or contract data. If a business object is modified or newly added, the endpoint generator is automatically notified and publishes information about the modified or newly added object. The client device that is accessing the business object is notified about the modified or newly added object. Or, an endpoint is generated ...

Methods and systems for providing a level of access to a computing device

CAPTURING AND LOADING OPERATING SYSTEM STATES

Operating system states capture and loading technique embodiments are presented that involve the capture and loading of baseline system states. This is accomplished, in one embodiment, by storing the states of a computer's operating system memory that it is desired to restore at a future time. No changes are permitted to the persisted storage associated with the computer. Instead, changes that would have been made to the persisted storage during an ensuing computing session, had they not been prevented, are stored in a separate computing session file. Whenever it is desired to return the operating system to its baseline condition, the stored baseline system memory states are loaded into the operating system memory, in lieu of the operating system memory's current states.

METHODS AND SYSTEMS FOR HANDLING SOFTWARE OPERATIONS ASSOCIATED WITH STARTUP AND SHUTDOWN OF HANDHELD DEVICES

Systems and methods for improving software operations on startup. A system and method can provide for the storage of volatile memory contents of an application upon shutdown of a mobile device, and restoration of the contents upon startup.

COMPLEMENTARY LINKS (CLS) FOR SMARTPHONES AND TABLETS

Complementary Links (CLs) are user defined, customized Quick Links (QLs) which can be invoked by a user and which can be activated as visible icons during a session on the device. This facilitates easy switching between the current application and another application which can be complementary to the current session or can be any user preferred destination. When the user exits the current session with a QL the current session is minimized as an Interrupt icon and when the user completes the complementary session they can get back into the main session by clicking on the Interrupt icon which then restores the original session.

INFORMATION PROCESSOR FOR WORK MACHINE, WORK MACHINE, AND INFORMATION PROCESSING METHOD FOR WORK MACHINE

A controller (10) for a work machine includes a main board (20) and a PC board (30). The main board (20) includes: a main controller (21) that runs on a built-in work machine operating system; a first activator that activates the main controller (20) when an activation signal for activating the controller (10) is inputted; and an activation commander (212) that outputs an activation-command signal to the PC board (30) when the main controller (20) becomes active. The PC board (30) includes: a PC controller (31) that runs on an operating system for PCs; a network terminal (C33); a network controller (33) that outputs the activation signal to the main board (20) when a specific signal for commanding activation is inputted; and a second activator that activates the PC controller (31) when the activation-command signal outputted from the activation commander (212) of the main board (20) is inputted.

COMPUTER SHUTDOWN DEVICE

A shutdown device is described for a computer controlled by an operating system having an interrogation function operative on program termination to issue user save-change requests and activate a save function upon receipt of an affirmative response from the user. The device comprises an arrangement for generating a control signal in response to a predetermined condition to initiate a shutdown sequence through the operating system, a first non-volatile memory for storing predetermined shutdown responses to save change requests, an arrangement for intercepting save-change requests from the operating system pursuant to receipt thereby of the control signal, an arrangement for sequentially activating the save-change function to store changed files with respective identifying data in a second non-volatile memory, an arrangement for generating a deactivation signal when all changed files have been stored in the second non-volatile memory with the respective identifying data, and an arrangement ...

SUSPEND/RESUME CAPABILITY FOR A PROTECTED MODE MICROPROCESSOR AND HARD DISK, AND IDLE MODE IMPLEMENTATION

... 2102421 9221081 PCTABS00017 A portable computer system includes a protected mode microprocessor (311) capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multitasking operating system where an application program is being executed in a restricted mode, certain types of processing can be carried out after the unrestricted mode is entered due to the predetermined condition, then the interrupted application can be resumed with the restricted mode back in effect. An idle mode feature can automatically decrease and increase the speed of the processor clock (387) when user activity stops and later starts again, to conserve power.

Fingerprint scanning method and apparatus used for mobile terminal

The calculation of the history of the context of the object

A METHOD FOR RESTORING the OPERATING SYSTEM Of an APPARATUS IN a WORKING MEMORY, AND APPARATUS FOR the IMPLEMENTATION OF the INVENTION

L'invention concerne un appareil électronique disposant d'une unité centrale et d'une mémoire de travail contenant un système d'exploitation. Lors de la mise sous tension, un code mémorisé dans l'appareil est testé afin de déterminer si le programme est directement exécutable en mémoire de travail, ou s'il doit être téléchargé d'une mémoire non volatile interne à l'appareil. Une commande extérieure reçue par l'appareil initialise la valeur dudit code. La commande peut être soit directement introduite par l'utilisateur, soit reçue d'un réseau. Selon un perfectionnement, même si la valeur du code spécifie qu'il n'y a pas de téléchargement à effectuer, au bout d'un certain nombre de cycle d'allumage et d'extinction de l'appareil, le programme est téléchargé de la mémoire non volatile. La présente invention concerne également un appareil mettant en oeuvre le procédé.

DEVICE FOR CONTROLLING ACCESS TO A COMPUTER FOR WAKING UP SAME AND ACTIVATING A COMMUNICATION INTERFACE

PROCEEDED OF TAKING INTO ACCOUNT OF PARAMETERS OF CONFIGURATION BY the SOFTWARE Of a CALCULATOR EMBARKS HAS EDGE Of a VEHICLE

L'invention concerne un procédé de prise en compte de paramètres de configuration par le logiciel d'un calculateur embarqué à bord d'un véhicule, selon lequel, après une phase d'initialisation du calculateur, lesdits paramètres sont inscrits dans une mémoire volatile et copiés dans une mémoire non volatile pendant une phase de power-latch qui suit la coupure de l'alimentation électrique du véhicule. Selon l'invention, après réception desdits paramètres de configuration par la mémoire volatile, une requête est envoyée au calculateur lui commandant de redémarrer en tenant compte desdits paramètres enregistrés dans sa mémoire volatile, et le calculateur tient compte desdits paramètres immédiatement après l'exécution de ladite requête.

DESKTOP COMPUTER SYSTEM HAVING SYSTEM SUSPEND

음성인식을 통한 단말기의 잠금 상태 해제 및 조작 방법 및 장치

... 상술한 과제를 달성하기 위하여, 본 발명의 일 실시 예에 따르는 단말기의 제어방법은 단말기가 락(Lock)되어 있는 상태에서 음성 입력을 받는 단계; 및 상기 음성 입력이 기 설정된 명령과 일치할 경우 상기 음성 입력에 해당하는 동작을 수행하는 단계를 포함하는 것을 특징으로 한다. 또한 본 발명의 일 측면에 따르는 음성입력을 통해서 제어할 수 있는 단말기는, 상기 단말기의 동작 상태를 표시하는 디스플레이부; 음성입력을 받을 수 있는 음성 입력부; 상기 단말기가 락(Lock)되어 있는 상태에서 상기 음성 입력부를 통해 입력된 음성 입력이 기 설정된 명령과 일치할 경우 상기 음성 입력에 해당하는 동작을 수행하는 제어부를 포함하는 것을 특징으로 한다. 본 발명의 일 실시 예에 따르면 별도의 조작 없이 음성 입력만으로 단말기를 제어하는 것이 가능해지고, 사용자가 음성 입력에 따른 명령어 집합을 설정할 수 있으므로 단말기에 대한 사용자 조작성이 향상되는 효과가 있다.

SUSPENSION AND/OR THROTTLING OF PROCESSES FOR CONNECTED STANDBY

ＭＣＵ를 웨이크업 시키기 위한 방법 및 디바이스

... 본 개시내용은 MCU를 웨이크업하기 위한 방법 및 디바이스를 제공하며, 이는 지능형 디바이스 기술 분야에 속한다. 상기 방법은: 제 1 MCU가 제 2 MCU로 데이터를 전송하는 통신 이벤트를 트리거링하는 경우, 상기 제 2 MCU가 딥 슬립 상태(deep sleep state)에 있는지 여부를 결정하는 단계; 및 상기 제 2 MCU가 상기 딥 슬립 상태에 있는 경우, 상기 제 1 MCU와 상기 제 2 MCU 사이에서 접속되는 웨이크업 핀(pin)을 통하여 상기 제 2 MCU로 인터럽트(interrupt) 웨이크업 신호를 송신하여 상기 제 2 MCU를 웨이크업시키는 단계를 포함한다. 제 1 MCU와 제 2 MCU 사이에서 접속되는 웨이크업 핀을 통하여 제 2 MCU로 인터럽트 웨이크업 신호를 송신함으로써, 딥 슬립 상태에 있는 MCU는 딥 슬립 상태 하에서 상기 MCU에서의 내부 인터럽트 이벤트를 기다리지 않고, 외부 인터럽트 이벤트를 트리거링하는 것을 통하여 다른 MCU들에 의해 웨이크업될 수 있어서, MCU들의 통신의 효율성이 개선될 수 있다.

Data Storage Device and Operation Method Thereof, Storage System Having the Same

METHODS TO COMMUNICATE A TIMESTAMP TO A STORAGE SYSTEM

Driving of a multifunction device

This method of connecting a multifunction device to a computer is characterized in that it comprises the following steps: - the transmission by said device of a device identifier to said computer; - the execution, by said computer, of a driver of the device associated with said device identifier; - the obtaining of a list of the functions of the device by said computer; - the triggering, by the driver of the device and on said computer, of the execution of drivers associated with said listed functions and; - the management, by said driver of the device, of the data streams between the various functions of the device and said corresponding function drivers.

Electronic device and device wake-up method

A device wake-up method suitable for an electronic device is provided. The method includes starting to perform a wake-up operation, loading an optimized frequency value, and substituting a preset frequency value of a counter by the optimized frequency value; starting to continuously accumulate a waiting count value having an initial value according to the optimized frequency value; in response to determining that the accumulated waiting count value is equal to a target count value, respectively performing a read test operation to one or more test physical addresses in a rewritable non-volatile memory module; and, in response to determining that all the one or more test physical addresses pass the corresponding read test operations, loading a plurality of initial information corresponding to the rewritable non-volatile memory module, so as to complete the wake-up operation.

CONTROL METHOD, CONTROL DEVICE AND COMPUTER SYSTEM

Provided are a control method and a control device applied in a computer system, and a computer system. The control method according to the embodiments of the present invention is applied in a computer system, wherein the computer system includes a system memory containing two divided storage areas with the two storage areas being respectively a first storage area and a second storage area. The control method includes: loading a first operating system into the first storage area; running the first operating system; and starting up a system memory access drive by the first operating system, so as to load into the second storage area the pre-stored memory mapping data of the second operating system by the system memory access drive.

METHOD AND SYSTEM FOR MANAGING SLEEP STATES OF INTERRUPT CONTROLLERS IN A PORTABLE COMPUTING DEVICE

A method and system for managing sleep states of one or more interrupt controllers of processors contained within a portable computing device are described. The method includes a processor defining wake-up interrupt settings in a storage device contained within the portable computing device. This storage device may comprise message random access memory ("RAM"). After wake-up settings have been established in message RAM, a processor may generate an alert that the wake-up settings in the message RAM have been defined. Next, a controller reviews the wake-up interrupt settings in the message RAM for a plurality of interrupt controllers that correspond with a plurality of processors contained within the portable computing device. The controller merges the wake-up settings in the message RAM and then sends the merged wake-up settings to an always-on power manager ("APM"). The APM is responsible for issuing signals to place interrupt controllers of processors into a sleep state.

SLEEP STATE TRANSITIONING

A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

System and method for pre-operating system memory map management to minimize operating system failures

A method includes booting an information handling system, providing by an EFI of the information handling system a memory segment for a first EFI type memory access, reserving a first portion of the segment from access by an operating system of the information handling system, determining a size of the first portion, determining a size of a second portion of the segment based upon the size of the first portion, allocating a third portion of the segment for the first EFI type memory access, the third portion including the first portion and the second portion, and passing a memory map to the operating system, the memory map including the third portion, wherein the third portion is reserved from access by the operating system.

Quick starting external programmer for implantable medical device

A system and method for restoring a microprocessor-based system to a previously booted target state in which an image of memory and the processor registers in the previously booted state is saved and stored in a storage device. A restore routine executing in ROM retrieves the image from the storage device and restores the system memory and processor registers to the target state. An operating system return routine then returns control of the system to the operating system software. In an exemplary implementation, a system in accordance with the invention is incorporated into a microprocessor-based external programmer for a cardiac rhythm management device in order to allow quick starting of the programmer from a powered down condition without going through a time consuming boot process.

Information processing apparatus with work suspend/resume function

An information processing apparatus having a work suspend/resume function which allows operator to use a main memory shared by different processings even when work suspension information is saved therein. A system for allowing a same operational environment as that set up in one information processing apparatus to be easily implemented in another information processing apparatus. A main memory used by a CPU for execution of processings has a function for storing information concerning the state of the information processing apparatus prevailing at a time point when execution of a given processing is suspended by a CPU for allowing the suspended processing to be performed in continuation later on. When the suspension state information has already been stored in the main memory by a former user, the suspension state information is transferred to a removable nonvolatile storage device so that the CPU can perform other processing than the suspended one by using the main memory. The transfer ...

METHODS, SYSTEMS AND APPARATUS TO INITIALIZE A PLATFORM

Methods, apparatus, systems and articles of manufacture are disclosed to initialize a platform. An example disclosed apparatus includes a boot loader manager to prevent operating system loading in response to detecting a power-on condition, a context manager to retrieve first context information associated with the platform, and a policy manager to identify a first operating system based on the first context information, the policy manager to authorize the boot loader manager to load the first operating system.

APPARATUS AND METHOD FOR DISPLAYING A LOCK SCREEN OF A TERMINAL EQUIPPED WITH A TOUCH SCREEN

An apparatus and method for displaying a lock screen including a character object having a motion effect in a terminal equipped with a touch screen. The method includes locking the touch screen and displaying the lock screen including the character object having the motion effect on a preset background image. Upon generation of a touch input, determining whether the touch input is for unlocking the touch screen, and if the touch input is for unlocking the touch screen, unlocking the touch screen and controlling the character object to perform a preset action indicating the unlocking of the touch screen.

INFORMATION PROCESSING APPARATUS AND DATA SAVING ACCELERATION METHOD OF THE INFORMATION PROCESSING APPARATUS

According to one embodiment, an information processing apparatus includes a first storage, a second storage, a data saving module, and a data saving acceleration module. The data saving module is configured to save data stored in the first storage to the second storage after compressing the data stored in the first storage. The data saving acceleration module is configured to reserve a storage area on the first storage and to write predetermined data to the reserved storage area in order to fill the reserved storage area with regular data with high compression efficiency, when the data saving module saves the data stored in the first storage to the second storage.

Motherboard supply circuit

A motherboard supply circuit includes a motherboard and a control circuit coupled to the motherboard. The motherboard is configured to couple to a power supply. The power supply is configured to supply power to a notebook computer and charge a battery. The power supply is also configured to supply power to the motherboard via the control circuit. The motherboard is configured to switch off the control circuit when detecting the notebook computer is in stand-by, thereby enabling the power supply not to supply power to the motherboard. The motherboard is also configured to switch on the control circuit upon detecting that the battery needs to be charged, thereby stopping the power supply from supplying power to the motherboard.

Apparatus, method and computer program for processing information

An information processing apparatus working in pause states containing at least both a suspension state and a hibernation state, may include a time counting unit for counting time elapsed in the suspension state from a transition to the suspension state, and a transitioning unit for transitioning to the hibernation state if the elapsed time has exceeded a predetermined period of time.

Distributed file system

A distributed file system for devices is described. In an embodiment, each data element stored on one of the devices has an associated location and availability attribute. The location attribute is stored co-located with the data element. The availability attribute and a copy of the location attribute are stored by a metadata service. When a client on a device needs to access a data element, it sends a request to the metadata service to find the location of the data element. If the data element is available, this information is provided to the client and this may involve waking a dormant device which holds the data element. Where the data element is not available, read only access may be granted to a cached copy of the data element. Where replication is used and one of the devices holding a replica is unavailable, the system may use write off-loading.

INFORMATION PROCESSING APPARATUS AND RECORDING MEDIUM

In accordance with one embodiment, an information processing apparatus comprises an operation section, a signal generation section and a control section. The operation section outputs an operation signal indicating that it is operated by a user. The signal generation section generates a first control signal and a second control signal based on the operation signal from the operation section. The control section starts a pre-determined program based on the first control signal and executes an interruption processing of the pre-determined program based on the second control signal. The interruption processing means temporarily stopping the pre-determined program being executed or releasing the temporary stop of the pre-determined program.

Distributed File System

A distributed file system for devices is described. In an embodiment, each data element stored on one of the devices has an associated location and availability attribute. The location attribute is stored co-located with the data element. The availability attribute and a copy of the location attribute are stored by a metadata service. When a client on a device needs to access a data element, it sends a request to the metadata service to find the location of the data element. If the data element is available, this information is provided to the client and this may involve waking a dormant device which holds the data element. Where the data element is not available, read only access may be granted to a cached copy of the data element. Where replication is used and one of the devices holding a replica is unavailable, the system may use write off-loading.

DISPLAY CABINET AND CONTROL METHOD OF THE SAME

The disclosure provides a display cabinet and a control method thereof. The display cabinet comprises a cabinet body which defines an exhibition space, the display cabinet further comprises: a rotatable tray arranged in the exhibition space, which is configured to place an exhibit; a first camera located in the exhibition space, which is configured to capture images of the exhibit at different angles to construct a 3D model of the exhibit; a transparent touch display constituting at least a portion of the cabinet body, which is configured to display the 3D model when the transparent touch display screen is in an awake state, and acquiring a touch operation and displaying a detailed information of the exhibit according to the touch operation.

DELAYED SHUT DOWN OF A COMPUTER

A computer-implemented computer shut-down method includes identifying that a computing device has been moved from an open configuration in which input and output mechanisms on the computing device are accessible to a user, to a closed configuration in which at least some of the input and output mechanisms are inaccessible to a user; starting a shut-down timer in response to identifying that the computing device has been moved from the open configuration to the closed configuration; waiting a predefined time period, as established by the shut-down timer, and determining from the shut-down timer that the computing device can be transitioned from an active state into a sleep state in which power consuming components of the computing device are powered down; and transitioning the computing device from the active state to the sleep state upon determining that the computing device can be transitioned.

ON-BOARD UPDATE DEVICE AND ON-BOARD UPDATE SYSTEM

An on-board update device and an on-board update system provided herein may prevent a decrease in the electric power charged in the battery caused by an update. An on-board update device has an update processing unit configured to update a program stored in a storage unit of a communication device. The on-board update device includes: an update information acquisition unit; a required electric power estimation unit; and a battery level acquisition unit acquires an amount of electric power charged in the battery. The update processing unit performs an update process in consideration of the amount of electric power estimated by the required electric power estimation unit, the amount of electric power acquired by the battery level acquisition unit, and a priority level of the update program or data acquired by the update information acquisition unit.

Information processing system, information processing method and readable-by-computer recording medium

An information processing system includes a volatile storage unit stored with save target information to be saved when transiting to a sleep state in which a consumption of electric power can be temporarily restrained, a nonvolatile storage unit of saving the save target information when transiting the sleep state, a nonvolatile storage medium of storing the save target information remaining unstorable in the nonvolatile storage unit, and a control unit of storing the nonvolatile storage unit with the save target information and division-storing the nonvolatile storage medium with the save target information exceeding a storage capacity of the nonvolatile storage unit.

PREEMPTION OF A CONTAINER IN A SECURE COMPUTATION ENVIRONMENT

A container corresponding to executable code may be received. The container may be executed in a secure computation environment by performing one or more operations specified by the executable code of the container. An instruction to terminate the executing of the container may be received from a high level operating system (HLOS) that is external to the secure computation environment. A determination may be made as to whether the container is associated with a preemption privilege and the executing of the container may be terminated after receiving the instruction from the HLOS based on the determination of whether the container is associated with the preemption privilege.

Method and Apparatus for a Zero Voltage Processor Sleep State

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.

PERSISTING DATA ACROSS WARM BOOTS

Techniques for persisting data stored in volatile memory across a warm boot. One or more portions (referred to as warm memory) of volatile memory of the system can be reserved and configured such that the data stored by these portions is not affected by a warm boot thereby resulting in the data stored being persisted across a warm boot.

RDMA completion and retransmit system and method

A system and method for maintaining ordering in completion and retransmit operations in an RDMA environment. A system is provided for handling a completion process in an remote data memory access (RDMA) environment having a RequestOut channel and a ResponseOut channel, comprising: a descriptor list for each channel, wherein each descriptor list includes a message descriptor for each message in the channel; an update mechanism for updating a message length field in the message descriptor with a sequence number of a last byte in the message whenever a channel swap occurs between the RequestOut channel and the ResponseOut channel; an acknowledgement (Ack) completion system that examines values in a completion context and compares a sequence number of a next to complete message with a last acknowledged sequence number to determine if the message should be completed; and a read request completion system that performs completion of a read request.

Wearable equipment and mode switching method using the same

A mode switching method of wearable equipment and the wearable equipment are disclosed. The method comprising: confirming a current mode being a sleep mode, detecting an accumulated time of a motion state, judging whether the accumulated time is greater than a first predetermined time period and switching to a fake sleep mode if it is; and detecting an accumulated footsteps and a sleep state, which by judging whether the accumulated footsteps in a second predetermined time period is greater than a threshold footsteps and switching to the motion state if it is; and judging whether the second predetermined time period is experienced in the sleep state and switching to the sleep mode if it is. The present invention can improve the accuracy, while reducing power consumption.

Switching CPU execution path during firmware execution using a system management mode

A computer system firmware is provided that includes functionality for using a system management mode (SMM) to efficiently boot to a secondary operating system prior to booting to a primary operating system. The SMM is utilized to store data describing the state of the computer system at a point just prior to booting the secondary operating system. This data is used following execution of the secondary operating system to restore the system to the same state that it was in prior to executing the secondary operating system. Execution can then be continued at a location just following the location at which the secondary operating system was booted in order to execute a primary operating system.

WAKE SOURCE COMMUNICATION ACCORDING TO 10SPE LOCAL AND REMOTE WAKE AND RELATED SYSTEMS, METHODS, AND DEVICES

One or more examples relate, generally, to an apparatus. Such an apparatus includes a digital interface, a wake detect logic, and a power management connection. The digital interface may define a physical layer transceiver side of a connection between a physical layer transceiver and a physical layer controller, respectively of a 10SPE physical layer. The wake detect logic may communicate a source of detected wake from the physical layer transceiver to the physical layer controller via the digital interface. The power management connection may operatively couple to an enable connection of a switched voltage regulator.

Digital device for performing booting process and control method therefor

The present specification discloses a digital device for performing a hibernation booting process and a control method therefor. Here, the digital device according to an embodiment of the present invention comprises: a first memory; a second memory storing a snapshot image generated on the basis of pieces of page data of the first memory; and a control unit for generating the snapshot image, wherein the control unit primarily deduplicates duplicated page data in the first memory and selectively secondarily deduplicates duplicated page data by comparing the duplicated page data with the snapshot image prestored in the second memory, wherein data fragmentation is minimized through the secondary deduplication step.

Timer for use in an asymmetric mutli-core system

An integrated circuit includes a first processing domain configured to run a first operating system and a second processing domain configured to run a second operating system that is different than the first operating system. The integrated circuit further includes a time stamp timer circuit in the first processing domain configured to provide a first time stamp value to the first processing domain and an adjusted second time stamp value to the second processing domain. The time stamp timer circuit includes a timer adjust circuit configured to synchronize the adjusted second time stamp value when a power up signal is received by the time stamp timer circuit from the second processing domain.

HIBERNATE EXIT TIME FOR UFS DEVICES

Rather than waiting on a squelch to detect the difference in the state from steady to floating, this disclosure suggests using the time from when a reference clock is turned on to begin the process to exit the hibernation state. The reference clock is turned off while a data storage device is in the hibernation state to save power. Once the host is ready for the device to exit the hibernation state, the reference clock is turned on. The reference clock is monitored for the change. Once the reference clock is on, the data storage device returns to a steady state. In the ready state, the data storage device has a shortened ready time. Once the ready time is complete, the data storage device may now exit the hibernation state without waiting on squelch detection or a hibernation exit request from the host.

SYSTEMS AND METHODS FOR MANAGING DATA IN A DEVICE FOR HIBERNATION STATES

Method and apparatus to support a self-refreshing display device coupled to a graphics controller

A method and apparatus for supporting a self-refreshing display device coupled to a graphics controller are disclosed. A technique for setting the operating state of the graphics controller during initialization from a deep sleep state is described. The graphics controller may set the operating state based on a signal that controls whether the graphics controller executes a warm-boot initialization procedure or a cold-boot initialization procedure. In the warm-boot initialization procedure, instructions and values stored in a non-volatile memory connected to the graphics controller may be used to set the operating state of the graphics controller. In one embodiment, the graphics controller may determine whether any changes have been made to the physical configuration of the computer system and, if the physical configuration has changed, the graphics controller may set the operating state based on values received from a software driver.

TABS IN SYSTEM TASK SWITCHERS

NODE INTERCONNECTION APPARATUS, RESOURCE CONTROL NODE, AND SERVER SYSTEM

БЫСТРЫЙ ЗАПУСК КОМПЬЮТЕРА

Изобретение относится к компьютерной технике. Технический результат заключается в обеспечении возможности быстрой готовности к работе компьютера в состоянии, которое согласуется с ожиданием пользователей за счет копирования содержимого энергозависимой памяти в другую энергонезависимую память, причем копируемое содержимое включает в себя сохраненное системное состояние, но не пользовательское состояние, которое больше не сохраняется. Технический результат достигается за счет того, что в целевом состоянии на вычислительном устройстве могут быть закрыты все сеансы пользователей, так что пользовательское состояние больше не сохраняется энергозависимую память. Тем не менее, операционная система все еще может выполняться. В ответ на команду запуска компьютера, данное целевое состояние может быть быстро повторно создано из записанной информации о целевом состоянии. Части последовательности запуска могут выполняться для завершения процесса запуска, включая создание пользовательского состояния.

СПОСОБ И УСТРОЙСТВО ДЛЯ ПРОБУЖДЕНИЯ MCU

Настоящее изобретение относится к средствам управления режимами питания микроконтроллеров. Технический результат заключается в расширении арсенала технических средств пробуждения блока микроконтроллера (MCU). Способ содержит этапы, на которых: определяют, находится ли второй MCU в состоянии глубокого сна, когда первый MCU инициирует коммуникационное событие передачи данных на второй MCU; и, если второй MCU находится в состоянии глубокого сна, отправляют сигнал пробуждения прерывания на второй MCU через штырьковый вывод пробуждения, соединенный между первым MCU и вторым MCU, для пробуждения второго MCU из состояния глубокого сна посредством инициирования события внешнего прерывания, не ожидая события внутреннего прерывания во втором MCU, находящемся в состоянии глубокого сна. 3 н. и 8 з.п. ф-лы, 7 ил.

ПОДДЕРЖКА НЕСКОЛЬКИХ ОПЕРАЦИОННЫХ СИСТЕМ В МУЛЬТИМЕДИЙНЫХ УСТРОЙСТВАХ

Изобретение относится к области воспроизведения цифровых мультимедийных данных. Техническим результатом является расширение функциональных возможностей воспроизведения цифровых мультимедийных данных за счет поддержки нескольких операционных систем в устройствах потребительской электроники. Способ воспроизведения различных цифровых мультимедийных данных, закодированных в различных мультимедийных форматах, заключается в том, что: принимают первые цифровые мультимедийные данные в цифровом медиапроигрывателе, имеющем в памяти первую операционную систему в первом состоянии ожидания и имеющем в памяти вторую операционную систему в активном состоянии, причем первые цифровые мультимедийные данные закодированы согласно первому мультимедийному формату; пробуждают первую операционную систему из первого состояния ожидания, при этом первая операционная система поддерживает воспроизведение мультимедиа для первого мультимедийного формата, и вторая операционная система поддерживает воспроизведение мультимедиа ...

СПОСОБ И УСТРОЙСТВО ДЛЯ УСТАНОВКИ СОСТОЯНИЯ ПРИКЛАДНОГО ПРИЛОЖЕНИЯ

СРЕДСТВО ДЛЯ УСТАНОВКИ КЛЮЧА БЕЗ ПЕРЕВОДА В ПАССИВНОЕ СОСТОЯНИЕ

... 1. Способ обеспечения обработки в вычислительной среде, включающий следующие шаги:получение процессором машинной команды на изменение ключа хранения, который соответствует определенной ячейке запоминающего устройства, доступен для множества процессоров и содержит компонент (402) управления доступом, используемый для согласования ключей, и компонент (404) защиты от выборки, используемый для того, чтобы указывать, применимо ли управление ключами к выборке данных, хранящихся в ячейке запоминающего устройства, которой соответствует ключ хранения, ивыполнение машинной команды, в которой содержится управляющий разряд (NQ) без перевода в пассивное состояние, который определяет, должна ли осуществляться операция перевода в пассивное состояние, ключ хранения и одно или несколько значений для установки ключа хранения, при этом выполнение машинной команды включает:если NQ имеет первое значение, указывающее, что должнавыполняться операция перевода в пассивное состояние, выполнение шагова)-в), включающих ...

ПРИОСТАНОВКА И/ИЛИ РЕГУЛИРОВАНИЕ ПРОЦЕССОВ ДЛЯ РЕЖИМА ОЖИДАНИЯ С ПОДКЛЮЧЕНИЕМ

... 1. Способ перехода в режим ожидания с подключением на основании классификаций управления питанием, присвоенных процессам, причем способ содержит этапы, на которых:обнаруживают запрос входа в ожидание с подключением, ассоциированный с компьютерной средой; ивыполняют переход компьютерной среды в режим ожидания с подключением, содержащий:для соответствующих приостанавливаемых процессов, которым присвоена классификация приостанавливаемых, переключают приостанавливаемый процесс в приостановленный режим невыполнения;для соответствующих регулируемых процессов, которым присвоена классификация регулируемых, присваивают график регулирования регулируемому процессу; идля соответствующих привилегированных процессов, которым присвоена классификация привилегированных, предоставляют привилегированному процессу возможность продолжать выполнение в режиме выполнения.2. Способ по п. 1, содержащий этап, на котором:при нахождении в режиме ожидания с подключением, применяют график регулирования к регулируемому ...

СПОСОБ РАБОТЫ ТЕРМИНАЛА ПОЛЬЗОВАТЕЛЯ СЕЛЬСКОХОЗЯЙСТВЕННОЙ МАШИНЫ И СЕЛЬСКОХОЗЯЙСТВЕННАЯ МАШИНА

Verfahren und Vorrichtung zum Automatisierung von Informatikprozeduren

System und Verfahren zum Ermöglichen schneller Betriebszeiten bei Verwendung eines großen Betriebssystems zur Steuerung eines Instrumentierungssystems

Ein Sofort-An-Instrumentensystem wird dadurch erzielt, dass man das Betriebssystem vollständig hochfahren bzw. booten lässt, wenn zuerst Leistung an das Instrumentensystem angelegt wird, das System jedoch noch in dem Aus-Modus ist. Das OS bringt das Instrumentensystem zu dem Punkt, an dem alle internen Überprüfungen erzielt wurden, schaltet jedoch mögliche extern erfassbare Funktionen, wie z. B. die Anzeige, die Anzeigehintergrundbeleuchtung und den Lüfter, nicht an. Sobald das OS hochgefahren hat, wird die Festplatte gestoppt, die Taktrate reduziert, eine Leistung von möglichen Mess-PC-Karten entfernt. An diesem Punkt ist das Instrumentensystem im Wesentlichen in einem "Schlaf"-Modus. Wenn ein Benutzer das Instrumentensystem anschaltet, wird die Taktrate aufgegriffen und alle anderen Funktionen werden für die Dauer des Testzyklus aktiv. Wenn der Benutzer das Instrumentensystem ausschaltet, fährt das System hoch und kehrt dann wieder in den Schlafmodus zurück. Aus der Perspektive des Benutzers ...

Verwalten einer Portalanwendung

Das Verwalten einer Portalanwendung enthält: in einer Einheit mit mindestens einem Prozessor, der eine Portalanwendung ausführt, Erstellen eines Auslösers für das Bewahren von Ressourcen in der Einheit; Feststellen in der Einheit, dass der Auslöser aufgetreten ist; und Anhalten des Betriebs eines Portlet-Moduls innerhalb der Portalanwendung, die durch die Einheit ausgeführt wird.

FAHRZEUGSTEUEREINRICHTUNG

Es ist eine Fahrzeugsteuereinrichtung vorgesehen, welche die Verlängerung der Hochfahrzeit durch eine Erhöhung der Anzahl der sich auf die Kommunikation beziehenden Funktionsteile unterdrücken kann. Die Erfindung weist eine Stromversorgungseinheit 3, die einem Mikrocomputer 2, der mit anderen elektronischen Steuereinheiten durch CAN-Kanäle (CAN1, CAN2) kommuniziert, Betriebsstrom zuführen kann oder den Betriebsstrom für diesen unterbrechen kann, und Kommunikationssteuereinrichtungen 4 und 6, die jeweils in den mehreren CAN-Kanälen (CAN 1, CAN 2) bereitgestellt sind, die für die Kommunikation des Mikrocomputers 2 verwendet werden, auf. Wenn die Kommunikationssteuereinrichtung 4 durch den sich auf die Kommunikationssteuereinrichtung 4 beziehenden CAN-Kanal (CAN1) ein Steuerungseinleit-Befehlssignal empfängt, das die Aktivierung des Mikrocomputers 2 vorschreibt, schaltet die Kommunikationssteuereinrichtung 4 den Zustand der Kommunikationssteuereinrichtung 4 von einem Bereitschaftszustand mit ...

Hibernating a processing apparatus for processing secure data

Time-limited access to configuration settings

A method and apparatus to implement a time-limited configuration settings hierarchy where prioritized temporary access to a configuration setting of a subordinate device in a network of electronic devices is controlled. A data access control list (ACL) is established 104 that has a prior setting 106, permission is then granted to a configuration control interface device to override the prior setting for a limited time period by adding a time-limited override parameter to the ACL 112. Configuration control interface device is permitted to override 114 said prior setting and modify said configuration setting of at least one subordinate device during the time period. Once the time period expires the time-limited override parameter is removed and reverted to said prior setting 120. This allows temporary users of IoT devices to have much higher levels of privilege over configuration settings, as an automatic revocation of the permission and reversion to the previous settings is guaranteed on ...

Non-quiescing key setting facility

A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception.

Power control circuitry for controlling power domains

A data processing apparatus 2 includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry 22 includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus 2. The mapping parameters may be fixed or software programmable. The mapping parameters may be accessible as memory mapped values within a memory address space of a data processing apparatus.

Securely saving a state of a processor during hibernation

A data processing apparatus comprises processing circuitry including several state retention cells for holding a current state of the processing circuitry, at least some of the state retention cells being arranged in series. In response to a hibernate signal, the processing apparatus switches from an operational mode to a low power or sleep mode in which the processing circuitry is powered down. Prior to powering down the processing circuitry its current state is output from the state retention cells and encrypted, and the encrypted state is then stored (fig. 3a). Upon detection of a wake signal, the processing apparatus switches from the low power mode to the operational mode and the stored encrypted state data is decrypted and used to restore the state of the processing circuitry (fig. 3b). The state retention cells may take the form of one or more scan chains and provide an output in the form of one or more serial data streams. This is a convenient form for subsequent encryption by hardware ...

Method and system for providing hybrid-shutdown and fast startup processes

Collaborative processor and system performance and power management

PROCEDURE AND DEVICE FOR SNAPPING THE RESUMPTION

Desktop computer system having multi-level power management

Method and apparatus for controlling lock/unlock state of terminal through voice recognition

A method for controlling a terminal through a voice input is provided. The method includes receiving a voice input when the terminal is in a state in which the terminal is locked and performing an operation corresponding to the voice input if the voice input corresponds to a preset command.

SUPPORTING MULTIPLE OPERATING SYSTEMS IN MEDIA DEVICES

Techniques and tools for supporting multiple operating systems in consume r electronic devices. For example, techniques and tools are described that a llow quickly switching between operating systems in video disc players that support different media types while reducing wait time and mitigating possib le negative impacts to user experience.

SUSPENSION AND/OR THROTTLING OF PROCESSES FOR CONNECTED STANDBY

One or more techniques and/or systems are provided for assigning power management classifications to a process, transitioning a computing environment into a connected standby state based upon power management classifications assigned to processes, and transitioning the computing environment from the connected standby state to an execution state. That is, power management classifications, such as exempt, throttle, and/or suspend, may be assigned to processes based upon various factors, such as whether a process provides desired functionality and/or whether the process provides functionality relied upon for basic operation of the computing environment. In this way, the computing environment may be transitioned into a low power connected standby state that may continue executing desired functionality, while reducing power consumption by suspending and/or throttling other functionality. Because some functionality may still execute, the computing environment may transition into the execution ...

INFORMATION PROCESSING SYSTEM

In the process of returning to a series of processes for returning to a normal operation mode, an I/O address showing a change line status register of the FDC is set to a stored register of the trap logic. When the process returns to the normal operation mode and then an access to the first status register is trapped, a change line status flag value is rewritten. The faked OS/driver invalidates the floppy disk allocation information in the main memory.

Fast computer startup

Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information.

Information processing apparatus and method of controlling the same

A first nonvolatile storage device has a higher access speed in a continuous access than a random access and a second nonvolatile storage device has a higher access speed in the random access than the continuous access. The information processing apparatus selects a first storage method in which an amount of continuous data is larger than an amount of random data if data stored in a volatile storage device is saved in the first nonvolatile storage device, and selects a second storage method in which an amount of random data is larger than an amount of continuous data if the data stored in the volatile storage device is saved in the second nonvolatile storage device, and saves the data stored in the volatile storage device into the specified nonvolatile storage device using the selected storage method when a predetermined condition is satisfied.

Program, control method, and control device

Provided are a program, a control method, and a control device by which an activation time can be shortened. In a computer system which is equipped with a Memory Management Unit (MMU), with respect to a table of the MMU, page table entries are rewritten so that page faults occur at each page necessary for operation of software. At the time of activating, stored memory images are read page by page for the page faults which occurred in the RAM to be accessed. By reading as described above, reading of unnecessary pages is not performed, and thus, the activation time can be shortened. The present invention can be applied to a personal computer and an electronic device provided with an embedded computer.

Re-programming programmable hardware devices without system downtime

Programmable hardware devices are re-programmed without system downtime. To re-program the device, the device is quiesced, state associated with the device is saved, updates are loaded, the state is restored and operations are resumed, all transparent to the system, except for a possible delay in the system.

Information processing apparatus, information processing method, and storage medium

The hibernation start-up by the kernel function takes a long time due to a processing time required for a normal boot sequence. When starting an operating system, the information processing apparatus according to the present invention determines whether to perform the hibernation start-up processing before initialization of a memory management mechanism. When the hibernation start-up processing is performed, a size of the memory management mechanism is reduced to a minimum size necessary for initializing the kernel and a hibernation image is read in parallel with initialization of hardware. The limited memory management area can be restored to a state free from a limitation by reading the hibernation image.

Server with remote reboot and wake-up function

A server includes a number of first and second network cards, a buffer, a restart circuit, an AND gate, and a south bridge. Each of the first network cards includes a first signal pin to transmit a wake-up signal and a restart signal. Each of the second network cards includes a second signal pin to transmit a wake-up signal. The restart circuit is connected to each of the first signal pins through the buffer to receive the restart signal, and reboots the server according to the restart signal. The south bridge is connected to each of the first and second signal pins through the AND gate to receive the wake-up signal, and wakes up the server according to the wake-up signal.

Computing platform interface with memory management

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Information processing apparatus and method of controlling virtual machine

According to one embodiment, an apparatus includes a controller. The controller is configured to control an operation environment of a virtual machine which runs on a hypervisor. The controller includes a change module configured to change the virtual machine from an operating state to a sleep state, in response to a logout request for an operating system in the virtual machine, a storing module configured to store first image data indicating contents of a memory in a storage as an operation environment, a restoration module configured to restore the contents of the memory to contents based on second image data, and a return module configured to return the virtual machine to the operating state after the contents of the memory is restored to the contents based on the second image data.

Non-transitory recording medium storing information processing program, information processing apparatus, information processing system, and information processing method

An example information processing apparatus includes a duration acquisition unit to acquire a duration of a dormant state, and a processing unit to change a state of a predetermined program to be advantageous to a user when the duration of the dormant state is longer than a first time length. For example, the predetermined program is a game program and when the duration of the dormant state is longer than the first time length, the processing unit changes a parameter of the game program to be advantageous to the user.

System wakeup on wireless network messages

While an information handling device is in a reduced power state, the information handling device transitions from the reduced power state to a higher power state in response to receiving a message over an established wireless network connection that maintains a presence on a wireless network. In turn, the information handling device processes the message accordingly in the higher power state.

Collaborative processor and system performance and power management

The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

Collaborative processor and system performance and power management

The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

FAST COMPUTER STARTUP

Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information. 1. A method performed on a computing device , the method comprising:detecting, in response to starting up the computing device, a hibernation file that was recorded as part of a preceding shutdown process;determining that a hardware configuration of the computing device remains compatible with that reflected in the recorded hibernation file;determining that the hibernation file is consistent with a storage device on which the hibernation file is stored; andrestoring, in response to the determinings, an operating state of the computing device from the recorded hibernation file.2. The method of where the hibernation file is determined to be consistent with the storage device is based on a sequence number maintained by a file system managing the storage device.3. The method of where the hibernation file comprises system state of the computing device claim 1 , but not user state of the computing device.4. The method of where the determining that a hardware configuration of the computing device remains compatible comprises checking a hardware inventory of the computing device. ...

IMAGE FORMING APPARATUS, METHOD FOR CONTROLLING IMAGE FORMING APPARATUS, AND STORAGE MEDIUM

An image forming apparatus, which is configured to perform image processing while managing a resource of a system, includes a memory, a detection unit configured to detect a brightness level around a main body of the image forming apparatus, and a control unit configured to reboot the resource of the system, check a state in which the system should be rebooted to determine which level this state has shifted to, reserve reboot processing according to the determined level, and control whether the reboot processing should be performed by the reboot unit according to the detected brightness level and a level of the reserved reboot processing. 1. An image forming apparatus configured to perform image processing while managing a resource of a system , the image forming apparatus comprising:a detection unit configured to detect a brightness level around a main body of the image forming apparatus; anda control unit configured to:reboot the resource of the system;check a state in which the system should be rebooted to determine which level the state has shifted to;reserve reboot processing according to the determined level; andcontrol whether the reboot processing should be performed according to the detected brightness level and a level of the reserved reboot processing.2. The image forming apparatus according to claim 1 , wherein the detection unit detects at least three stages of brightness levels.3. The image forming apparatus according to claim 1 , wherein the resource of the system includes a volatile memory.4. The image forming apparatus according to claim 3 , wherein the volatile memory is managed with memory blocks of a plurality of capacities assigned to a single block.5. The image forming apparatus according to claim 1 , wherein the control unit determines that the level of the reboot processing is a high level in a case where a predetermined available capacity cannot be secured in a volatile memory.6. The image forming apparatus according to claim 1 , wherein the ...

Mobile client device, operation method, and recording medium

An information processing apparatus including a touch panel and a near field communication interface. The information processing apparatus detects that an input received at the touch panel corresponds to a predetermined input when the information processing apparatus is in a suspended state; and controls the information processing apparatus execute a predetermined function via the near field communication interface and awake from the suspended state upon detecting that the input corresponds to the predetermined input.

Method for controlling schedule of executing application in terminal device and terminal device implementing the method

A method may include associating, with a timer-B, a second application in a terminal device; setting the terminal device in a standby mode; and executing the second application when a processor in the terminal device wakes up after the timer-B measures a second amount of elapsed time. The timer-B may not initiate wake-up of the processor. The method may further include determining whether the second application is associated with the timer-B or a timer-A when the terminal device receives a command of setting the terminal device in the standby mode; and when the second application is determined as being associated with the timer-A, unassociating the second application with the timer-A. The timer-A may initiate wake-up of the processor when the timer-A measures another second amount of elapsed time while the terminal device is the standby mode. A timer associated with a first application may initiate wakeup of the processor.

METHOD AND APPARATUS FOR PERFORMING TIMED FUNCTIONS IN A WIRELESS ELECTRONIC DEVICE

Methods and apparatus for performing timed functions in battery-powered, wireless electronic devices, such as sensors or control modules. Such electronic devices comprise a main processor and a co-processor. When the main processor enters a quiescent state in order to preserve battery life, one or more timed functions are transferred from the main processor to the co-processor just before the main processor enters the quiescent state. When the co-processor determines that it is time to perform the timed function, the co-processor wakes the main processor in order for the main processor to perform the timed function. 1. A battery-powered , electronic device , comprising:a first memory for storing main processor-executable instructions;a second memory for storing co-processor-executable instructions;a main processor coupled to the first memory for executing the main processor-executable instructions; and determine that the main processor has entered a quiescent state;', 'start a timer in response to determining that the main processor has entered the quiescent state; and', 'upon expiration of the timer, wake the main processor from the quiescent state and send an identification of a timed function to the main processor, the timed function comprising a function performed by the main processor that is dependent on time;, 'a co-processor coupled to the main processor and the second memory for executing the co-processor-executable instructions that causes the co-processor towherein the main processor performs the timed function after receiving the identification from the co-processor.2. The electronic device of claim 1 , wherein the co-processor instructions that causes the co-processor to determine that the main processor has entered a quiescent state comprises instructions that causes the co-processor to:receive a message from the main processor, the message comprising an indication that the main processor is entering the quiescent state and a parameter associated with ...

SINGLE-CORE WAKEUP MULTI-CORE SYNCHRONIZATION MECHANISM

A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep. 1. A method for enabling most cores of a multi-core microprocessor to sleep while a designated one of the cores services non-directed wakeup events that are not directed to any specific core , the method comprising:putting all of the cores to sleep and blocking wakeup events for all but a designated one of the cores, wherein said putting all of the cores to sleep comprises refraining from providing a clock signal and a power source to all of the cores;in response to detecting a wakeup event, waking up the designated core to handle the detected wakeup event;unblocking the wakeup events for the cores other than the designated core, regardless of whether there is any non-designated core to which a pending wakeup event is directed, so that in an event that a directed wakeup event is directed to a non-designated core, the non-designated core is enabled to respond to the directed wakeup event, and in an event that no directed wakeup event is directed to a non-designated event, all of the non-designated cores remain asleep;putting the designated core back to sleep after the designated core services the wakeup ...

Method and device for waking up a controller

A method and a device are provided for waking up a MCU. The method includes: determining whether a second MCU is in a deep sleep state, when a first MCU triggers a communication event of transmitting data to the second MCU; and when the second MCU is in the deep sleep state, sending an interrupt wakeup signal to the second MCU via a wakeup pin connected between the first MCU and the second MCU, so as to wake up the second MCU.

VEHICLE MOUNT COMPUTER WITH CONFIGURABLE IGNITION SWITCH BEHAVIOR

A vehicle mount computer having a configurable behavior controlled by a vehicle's ignition switch. A user can configure the computer to perform an action, switch modes, or execute a software application in response to the ignition switch being pressed or the position of the ignition switch being adjusted. For example, the computer can be configured to switch to a standby mode or hibernation mode, shutdown, prompt the user to select an action, or do nothing in response to the ignition switch being placed in an off position. The ignition switch can be electrically coupled to an input of the computer so that the computer's operating system or another application can monitor the status of the ignition switch. The operating system or application can cause the computer to perform the configured response upon detecting a change in the ignition switch's position or an actuation of the ignition switch. 1. A method , comprising:receiving input identifying an action for a computer to perform automatically in response to an ignition switch of a vehicle switching from a position for activating the vehicle to a position for deactivating the vehicle;receiving, with the computer, a signal indicating that the ignition switch has switched from the position for activating the vehicle to the position for deactivating the vehicle; andin response to receiving the signal, performing the identified action;wherein the computer operates in a wireless networked environment using logical connections to one or more remote external computers.2. The method of claim 1 , wherein the identified action comprises:switching the computer to a standby mode;switching the computer to a hibernation mode; and/orremoving power from one or more components of the computer.3. The method of claim 1 , wherein the identified action comprises:prompting a user to select from a plurality of actions; and/orexecuting an application.4. The method of claim 1 , wherein the identified action is based on a current mode for ...

RUNTIME DATA STORAGE AND/OR RETRIEVAL

A data storage device includes a memory and a controller. The controller is configured to, in response to a transition from a low power state to an active state, load runtime data to a volatile memory of the controller from a memory of a device coupled to the controller via an interface and, concurrently with loading the runtime data from the memory of the device to the volatile memory of the controller, load other data from the non-volatile memory to the volatile memory of the controller. 1. A data storage device comprising:a non-volatile memory; anda controller coupled to the non-volatile memory, the controller configured to, in response to a transition from a low power state to an active state, load runtime data to a volatile memory of the controller from a memory of a device that is coupled to the controller via an interface, and concurrently load other data from the non-volatile memory to the volatile memory of the controller.2. The data storage device of claim 1 , wherein the other data includes firmware associated with the controller.3. The data storage device of claim 1 , wherein the other data includes second runtime data.4. The data storage device of claim 1 , wherein the runtime data includes one or more flash translation layer (FTL) mapping tables.5. The data storage device of claim 1 , wherein the runtime data includes firmware state data associated with firmware of the controller.6. The data storage device of claim 1 , wherein the controller receives a power supply voltage from the device via the interface.7. The data storage device of claim 1 , wherein the low power state comprises a sleep state and the transition from the low power state to the active state is responsive to a command from the device.8. The data storage device of claim 1 , wherein the low power state comprises a power off state and the transition from the low power state to the active state is responsive to boot up of the device.9. The data storage device of claim 1 , wherein the ...

Operation method of portable terminal

An operation method of a portable terminal according to an embodiment of the present invention comprises the steps of: entering a window screen movement mode in which a window screen of a foreground task is displayed uppermost and one or more window screens are stacked in multiple layers under the window screen of the foreground task; selecting a window screen from a plurality of window screens according to a user's movement command; changing the transparency of at least a part of areas of window screens stacked on the selected window screen; and displaying the selected window screen as a foreground screen and terminating the window screen movement mode when an input determining the selected window screen is received. Therefore, it is possible to switch screens and tasks more swiftly and conveniently, thereby improving user convenience.

POWER CONTROL CIRCUITRY FOR CONTROLLING POWER DOMAINS

A data processing apparatus includes a plurality of power domains controlled by respective power control signals PCS. Power control circuitry includes mapping circuitry which maps a plurality of power status signals PSS indicative of the power status of respective power domains, and received from those power domains, to form the power control signals which are then supplied power domains. The mapping circuitry may be controlled by mapping parameters stored within a memory mapped array. The mapping parameters may specify that a given power control signal is either sensitive or insensitive to the power status of a particular other power domain within the data processing apparatus . The mapping parameters may be fixed or software programmable. 1. Power control circuitry for controlling power supplied to a plurality of power domains within a processing apparatus , said power control circuitry comprising:mapping circuitry to map a plurality of power status signals indicative of power status of respective power domains within said plurality of power domains to a plurality of power control signals to control power status of respective power domains within said plurality of power domains.2. Power control circuitry as claimed in claim 1 , wherein said mapping circuitry is responsive to a plurality of mapping parameters specifying relationships between said plurality of power status signals and said plurality of power control signals.3. Power control circuitry as claimed in claim 2 , wherein said relationships specified by respective values of said mapping parameters specify one or more of:a given power control signal is independent of a given power status signal;said given power control signal has a given control signal value when said given power status signal has a given status signal value; andsaid given power control signal has a given control value dependent upon a limit of values among a given plurality of said power status signals.4. Power control circuitry as claimed ...

INTEGRATED CIRCUIT DEVICE INCLUDING WAKE-UP CONTROL CIRCUIT AND ELECTRONIC DEVICE INCLUDING THE SAME

An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal. 1. An integrated circuit device comprising:a central processing unit (CPU) configured to operate in one of a plurality of modes; and a clock generator configured to generate an internal clock signal,', 'a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and', 'a controller configured to control the CPU and the clock generator based on the external signal., 'a wake-up control circuit configured to control the CPU, the wake-up control circuit comprising2. The integrated circuit device of claim 1 , wherein the controller is configured to function as a finite state machine (FSM) and count edges of the external signal.3. The integrated circuit device of claim 1 , wherein the controller is configured to count edges of the external signal and generate a clock enable signal to activate the clock generator when a count value of the controller reaches a first reference value claim 1 , andwherein the clock generator is configured to generate the internal clock signal based on the clock enable signal and output the internal clock signal to the multiplexer.4. The integrated circuit device of claim 3 , wherein the controller is further configured to output a wake-up signal to the CPU when the count value of the controller reaches a second ...

ELECTRONIC DEVICE AND HALF-SUSPEND CONTROLLING METHOD APPLIED THEREIN

An electronic device includes a display and a processor. The display displays a present application program in a first brightness. When the electronic device in normal-use status receives no user input for a predetermined idle time period, the processor determines whether the present application program is in a half-suspend list. If yes, the processor controls the electronic device to enter a half-suspend status and keep the present application program running, but controls the display to display the present application program in a second brightness, which is less bright than the first brightness. A half-suspend controlling method of the electronic device is also provided. 1. An electronic device capable of running several application programs , the electronic device comprising:a plurality of electronic elements activated when the electronic device is in a normal-use status;a display configured to display a present application program in a first brightness; anda processor configured to establish a half-suspend list, the half-suspend list comprising at least one application program;wherein when the electronic device in the normal-use status receives no user input for a predetermined idle time period, the processor determines whether the present application program is in the half-suspend list;wherein if the present application program is in the half-suspend list, the processor controls the electronic device to enter a half-suspend status and keep running the present application program, and the display displays the present application program in a second brightness; andwherein the second brightness is less bright than the first brightness, and the electronic elements are partially kept activated in the half-suspend status.2. The electronic device as claimed in claim 1 , wherein the second brightness is a lowest brightness of the display.3. The electronic device as claimed in claim 1 , wherein when the electronic device is in the half-suspend status claim 1 , a group ...

DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES

Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system. 1. A System-on-a-Chip (SoC) comprising:a plurality of Input/Output (I/O) controllers;a plurality of lanes;a lane mapping module to multiplex at least one of said I/O controllers to at least one of said lanes based on a configuration;a first processor to detect a change request, said change request to modify said configuration from an existing configuration to a new configuration; anda second processor to: verify that said new configuration is valid based on a stock keeping unit (SKU) associated with said SoC; and, if said verification is successful, store said new configuration in non-volatile memory and reset said SoC.2. The system of claim 1 , wherein said configuration comprises an I/O controller to lane mapping claim 1 , a lane enablement selection or a lane width.3. The system of claim 1 , wherein said I/O controllers load said new configuration from said non-volatile memory claim 1 , after said reset.4. The system of claim 1 , wherein said verification of said new configuration further comprises verifying an I/O controller to lane mapping claim 1 , verifying a lane enablement selection and verifying a ...

Method of UEFI Shell for Supporting Power Saving Mode and Computer System thereof

A method of computer processor execution of an UEFI shell in a computer system for entering into a power saving mode, the UEFI shell is located in a memory, the memory is connected to the processor, the method comprising: executing, by the processor, the UEFI shell; when executing the UEFI shell: initiating a call to a power saving library; retrieving corresponding power configuration data; retrieving and storing hardware registers data to memory; and enabling system control interrupt and configuring power-saving control registers with the power configuration data. 1. A method of computer processor execution of an UEFI shell in a computer system for entering into a power saving mode , the UEFI shell located in a memory , the memory is connected to the processor , the method comprising:executing, by the processor, the UEFI shell; [{'b': '1', '(S) initiating a call to a power saving library;'}, {'b': '2', '(S) retrieving corresponding power configuration data;'}, {'b': '3', '(S) retrieving and storing hardware registers data to memory; and'}, {'b': '4', '(S) enabling system control interrupt, initiating flushing of CPU internal caches, and configuring power-saving control registers with the power configuration data.'}], 'when executing the UEFI shell2. The method of claim 1 , wherein before the step of initiating the call to the power saving library claim 1 , further comprising:{'b': '3', 'executing an application running with the power saving library, wherein the power saving library is a Shell S library corresponding to the Advanced Configuration and Power Interface (ACPI) Standard.'}3. The method of claim 1 , wherein the step of retrieving corresponding power configuration data further comprising:{'b': '3', 'retrieving relative Advanced Configuration and Power Interface (ACPI) data via standard ACPI tables and storing into an S data object.'}4. The method of claim 1 , wherein the step of retrieving and storing hardware registers data to memory further comprising: ...

TECHNOLOGIES FOR OPTIMIZING RESUME TIME FOR MEDIA AGNOSTIC USB

A method for operating a media agnostic universal serial bus (MAUSB) device includes a compute device having a link connection manager, a USB manager, and a state manager. The compute device establishes a link with a MAUSB device and a session with the MAUSB device. Subsequently to receipt of a sleep command for the compute device, the compute device transitions to a sleep state and terminates the link with the MAUSB device while keeping intact the session with the MAUSB device. The compute device transitions back to an active state in response to receipt of a wake command for the compute device. The compute device sends a wake request to the MAUSB device. If the MAUSB device responds to the wake request with an acceptance, then the compute device reestablishes the previous session with the MAUSB device. If instead an error is received, the compute device terminates the session. 1. A compute device for operating a media agnostic universal serial bus (MAUSB) device , the compute device comprising:a link connection manager to establish a link with the MAUSB device;a universal serial bus (USB) manager to establish an MAUSB session with the MAUSB device;an enumeration manager to perform an enumeration the MAUSB device; anda state manager to receive a sleep command for the compute device,wherein the USB manager is further to send, in response to receipt of the sleep command, a sleep request to the MAUSB device,wherein the link connection manager is further to terminate the link with the MAUSB device in response to receipt of the sleep command,wherein the USB manager is further to maintain the MAUSB session after termination of the link with the MAUSB device, wherein to maintain the MAUSB session comprises to maintain the enumeration of the MAUSB device,wherein the state manager is further to (i) transition, in response to receipt of the sleep command, the compute device into a sleep state; (ii) receive a wake command for the compute device, and (iii) transition, in ...

SELECTIVE TEMPORARY DATA STORAGE

One embodiment provides host device. The host device includes a host processor circuitry; a host memory circuitry, and a host storage logic to determine whether a data to be stored is temporary or persistent and to provide a write (Write) command associated with the data to a storage device, if the data is persistent data, or to provide a volatile write (vWrite) command associated with the data to the storage device, if the data is temporary data. 1. A host device comprising:a host processor circuitry;a host memory circuitry, anda host storage logic to determine whether a data to be stored is temporary or persistent and to provide a write (Write) command associated with the data to a storage device, if the data is persistent data, or to provide a volatile write (vWrite) command associated with the data to the storage device, if the data is temporary data.2. The host device of claim 1 , wherein the host storage logic is to determine whether a new system power state corresponds to at least one of standby and/or hibernate (standby/hibernate) or at least one of shutdown and/or restart (shutdown/restart) and to provide a shutdown (Shutdown) command to the storage device if the new system power state is standby/hibernate or a discard volatile shutdown (dvShutdown) command to the storage device claim 1 , if the new system power state is shutdown/restart.3. The host device of claim 1 , wherein the vWrite command is to indicate to the storage device that the associated data is temporary.4. The host device of claim 2 , wherein the dvShutdown command is to instruct the storage device to store the persistent data to a nonvolatile memory circuitry and to invalidate the temporary data.5. The host device of claim 2 , wherein the Shutdown command is to instruct the storage device to store the persistent data and the temporary data to a nonvolatile memory circuitry.6. A method comprising:determining, by a host storage logic, whether a data to be stored is temporary or persistent; ...

Memory Mapping for Hibernation

A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory. 1. An apparatus comprising:volatile memory;non-volatile memory; and receive a request from a first process associated with a first memory region of the volatile memory;', 'use the first memory region to store first data, wherein the first data is generated during execution of the first process;', 'associate a respective flag to memory regions of the volatile memory, the respective flag identifying each memory region for copying or not copying, wherein a first flag is associated to the first memory region;', 'detect an event associated with the volatile memory;', 'in response to detecting the event, determine that the first memory region is associated to the first flag; and', 'in response to determining that the first memory region is associated to the first flag, copy the first data stored in the first memory region to the non-volatile memory., 'at least one processing device configured to2. The apparatus of claim 1 , wherein the event is an impending loss of power to the volatile memory.3. The apparatus of claim 1 , wherein the event is initiation of a hibernation process.4. The apparatus of claim 1 , wherein the request includes a memory characterization claim 1 , and the first flag is associated to the first memory region based on the memory characterization.5. The apparatus of claim 1 , wherein the first flag is associated to the first memory region based on usage of the first memory region by the first process.6. The apparatus of claim 1 , wherein ...

OUT-OF-BAND POINT OF SALE ACTIVATION FOR ELECTRONIC POWER TOOL DEVICES

An electronic power tool device includes an electronic processor, a communication interface in communication with the electronic processor, and a wake-up sensor configured to generate a wake signal for activating the communication interface and the electronic processor responsive to a stimulus. The communication interface is configured to receive a first electronic message that includes an activation state and transmit the first received electronic message to the electronic processor. The electronic processor is configured to control the activation state of the electronic power tool device to allow or prevent operation of the electronic power tool device based on the first received electronic message. 1. A method for controlling an activation state of an electronic power tool device , the method comprising:waking the electronic power tool device by providing a stimulus to a wake-up sensor of the electronic power tool device;receiving, by an activation device, information associated with the electronic power tool device;generating, by the activation device, an activation state code based on the received information;transmitting, by the activation device, the activation state code to the electronic power tool device, wherein the activation state code is configured to control the activation state of the electronic power tool device upon being received at the electronic power tool device, and the activation state includes an unlock state or a lock state.2. The method of claim 1 , wherein the stimulus at the wake-up sensor is out-of-band with respect to the transmitting of the activation state code.3. The method of claim 1 , wherein the wake-up sensor includes an identification tag claim 1 , the stimulus includes a transaction being conducted with the identification tag claim 1 , the wake-up sensor is configured to generate a wake signal responsive to the transaction being conducted with the identification tag claim 1 , and the method further comprises:initiating, by the ...

OPERATION CONTROL DEVICE FOR ELECTRONIC APPARATUS

An operation control device for an electronic apparatus is provided. An operation control device for an electronic apparatus according to an embodiment of the present disclosure, which is connected to an electronic apparatus and can transmit and receive signals to and from the electronic apparatus and a control device for remotely controlling use of power in the electronic apparatus, comprises: a measuring unit for calculating the amount of power supplied to the electronic apparatus; and a communicating unit for receiving identification information of the electronic apparatus and state information of the electronic apparatus from the electronic apparatus, transmitting information regarding the amount of power, the identification information of the electronic apparatus, and the state information of the electronic apparatus to the control device, and receiving a first control signal for controlling operation of the electronic apparatus from the control device and then transmitting the first control signal to the electronic apparatus, thereby switching the electronic apparatus to an off mode or a sleep mode. 1. An operation control device for an electronic apparatus , which is to be connected to the electronic apparatus and transmits and to receive signals to and from a control device for remotely controlling the power usage of the electronic apparatus and the electronic apparatus , the operation control device for the electronic apparatus comprising:a measuring unit that calculates an amount of power supplied to the electronic apparatus; anda communicating unit that receives identification information of the electronic apparatus and state information of the electronic apparatus from the electronic apparatus, transmits information regarding the amount of power, the identification information of the electronic apparatus, and the state information of the electronic apparatus to the control device, receives a first control signal for controlling the operation of the ...

INTERCONNECT WAKE RESPONSE CIRCUIT AND METHOD

In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background. 1. A chip , comprising: a transmitter driver to be powered off during a reduced power mode; and', 'at least one data path register coupled to the driver, the at least one data path register to be powered during the reduced power mode and to be stored with resume data to respond to a wake event detected from the data bus to drive the stored data onto the bus in response to the wake event., 'an interface having a PHY and a data bus to be coupled to an external device, the PHY including2. The chip of claim 1 , in which the at least one data path registers comprise more than one register.3. The chip of claim 1 , in which the at least one register is a flop.4. The chip of claim 1 , in which the data path comprises multiple registers sequentially coupled together.5. The chip of claim 1 , in which the data path is part of a full speed transmitter data path for a USB capable interconnect.6. The chip of claim 1 , further comprising a wake detect circuit to be at least partially powered on during the reduced power mode to monitor data bus line state.7. The chip of claim 6 , in which the wake detect circuit is to provide indication of the wake event to a PMU external to the PHY to wake up the PHY.8. The chip of claim 6 , in which the wake detect circuit is to provide indication of the wake event to power domain control logic within the PHY to wake up the PHY.9. The chip of claim 1 , comprising a retention register to be powered on during the reduced power mode to store configuration information for the ...

CHIPSET RECONFIGURATION BASED ON DEVICE DETECTION

Example implementations relate to chipset reconfiguration based on device detection. For example, a method includes detecting, by a computing system, that a storage device is connected to an input/output (I/O) interface of the computing system, and reconfiguring a chipset of the computing system based on the detected storage device. The method also includes performing a power cycle on chipset standby power to trigger a chipset configuration reload. 1. A method , comprising:detecting, by a computing system, that a storage device is connected to an input/output (I/O) interface of the computing system;reconfiguring, by the computing system, a chipset of the computing system based on the detected storage device; andperforming, by the computing system, a power cycle on chipset standby power to trigger a chipset configuration reload.2. The method of claim 1 , wherein performing the power cycle on chipset standby power comprises updating I/O interface mappings upon occurrence of a subsequent power-on sequence of the computing system.3. The method of claim 1 , wherein reconfiguring the chipset comprises reconfiguring firmware configuration bits of the chipset.4. The method of claim 1 , wherein detecting that the storage device is connected to the I/O interface comprises determining a type of the storage device connected to the I/O interface.5. The method of claim 4 , wherein determining the type of the storage device includes using inter-integrated circuit (I2C) buses for determining the type of storage device connected to the I/O interface.6. The method of claim 5 , wherein determining the type of storage device is performed during a standby mode or a running mode of the computing system.7. The method of claim 5 , wherein the storage device is communicatively coupled to the computing system directly or via a field replaceable unit (FRU).8. The method of claim 1 , wherein the I/O interface is selected from the group consisting of at least a serial ATA (SATA) claim 1 , ...

Fast computer startup

Fast computer startup is provided by, upon receipt of a shutdown command, recording state information representing a target state. In this target state, the computing device may have closed all user sessions, such that no user state information is included in the target state. However, the operating system may still be executing. In response to a command to startup the computer, this target state may be quickly reestablished from the recorded target state information. Portions of a startup sequence may be performed to complete the startup process, including establishing user state. To protect user expectations despite changes in response to a shutdown command, creation and use of the file holding the recorded state information may be conditional on dynamically determined events. Also, user and programmatic interfaces may provide options to override creation or use of the recorded state information.

DEVICE SUCH AS A CONNECTED OBJECT PROVIDED WITH MEANS FOR CHECKING THE EXECUTION OF A PROGRAM EXECUTED BY THE DEVICE

The present invention relates to a device () such as a connected object comprising a first electronic circuit () comprising: 21. A device () according to claim 1 , wherein the steps implemented automatically and autonomously by the second processing unit further comprise a program suspension command claim 1 , the integrity check and/or compliance step being implemented while the program is suspended.31. A device () according to claim 2 , wherein the suspension command comprises the placement of a stop point at a predetermined location in the program claim 2 , so as to suspend the program at the predetermined location claim 2 , or the placement of an observation point on a variable of the program claim 2 , so as to suspend the program when the variable is modified.4121. A device according to claim 3 , wherein the steps implemented automatically and autonomously by the second processing unit () comprise a step consisting of verifying whether a condition independent of the way in which the program is being executed has been met claim 3 , such as verifying whether a predetermined period of time has elapsed since a previous start of the program claim 3 , a previous resumption of the program claim 3 , or a previous powering-on of the device () claim 3 , the suspension command step being implemented when the condition is met.51126. A device () according to claim 1 , wherein the steps implemented automatically and autonomously by the second processing unit () comprise the command for the first processing unit () to resume the program when the program or the data manipulated by the program is revealed not to have been compromised during the check step claim 1 , and where this command is not implemented when the program or the data manipulated by the program is revealed to have been compromised during the check step.61226. A device according to claim 1 , implemented automatically and autonomously by the second processing unit () comprising a command for a definitive program ...

APPARATUS, METHOD, AND SYSTEM FOR EARLY DEEP SLEEP STATE EXIT OF A PROCESSING ELEMENT

An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread. 118.-. (canceled)19. A hardware processor comprising:a decoder to decode an instruction into a decoded instruction; and 'generate a wake indication for a second thread that is to be spawned from a first thread to cause a power control circuit to transition a processing element that is to execute the second thread from a first power state to a second power state within an amount of time to transition the processing element from the first power state to the second power state before the spawn, wherein the first power state and the second power state are lower power consumption states than an active power state.', 'an execution unit to execute the decoded instruction to20. The hardware processor of claim 19 , wherein the execution unit is to execute the decoded instruction to store the wake indication in a control register.21. The hardware processor of claim 19 , wherein the wake indication includes a processing element identifier to identify the processing element from a plurality of processing elements.22. The hardware processor of claim 19 , wherein the first thread is a main thread and the second thread is a helper thread to return data from the ...

Method And Apparatus For A Zero Voltage Processor Sleep State

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. 1. A system comprising:at least one processor comprising a first core and a second core;voltage regulation circuitry to regulate an operational voltage of the first core and the second core;an interconnect to couple one of the at least one processor to one or more system components; anda system memory coupled to one of the at least one processor, the first core to execute sequences of instructions;', 'the second core to execute sequences of instructions;', 'a shared cache accessible by both the first core and the second core;', 'power management logic to cause the first core to be powered down while the second core remains in an active state;', 'wherein power to the shared cache is to be maintained to enable access by the second core; and', 'wherein data associated with the first core is to be preserved when the first core is powered down., 'one of the at least one processor comprising2. The system of claim 1 , wherein at least one instruction of the sequences of instructions is a sleep instruction.3. The system of claim 2 , wherein the sleep instruction is to cause certain portions of the at least one processor to be powered down.4. The system of claim 2 , wherein the sleep instruction is to cause certain clocks to be gated.5. The system of claim 1 , wherein the system memory comprises a random access memory.6. The system of claim 1 , further comprising:at least one communication device coupled to the at least one processor.7. The ...

MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND OPERATION METHOD OF THE MEMORY SYSTEM

A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit a no the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode. 110-. (canceled)11. A memory device , comprising:an internal voltage generation circuit suitable for generating an internal voltage whose drivability is controllable according to a mode of operation of the memory device; anda mode control circuit suitable for controlling the internal voltage generation circuit in a mode of operation selected among a standby mode, a weak active mode, and a strong active mode based on a chip enable signal and a logical unit number (LUN) address.12. The memory device of claim 11 ,wherein the mode control circuit controls the internal voltage generation circuit in a standby mode when the chip enable signal is disabled,wherein the mode control circuit controls the internal voltage generation circuit in the weak active mode when the chip enable signal is enabled and the LUN address represents non-selection of the memory device, andwherein the mode control circuit controls the internal voltage generation circuit in the strong active mode when the chip enable signal is enabled and the LUN address represents selection of the memory device.13. The memory device of claim 11 ,wherein the internal voltage generation circuit includes a plurality of internal voltage generators for generating the internal voltage,wherein a first number internal voltage ...

SECURITY DESIGN FOR A WAKE UP FRAME

Methods and systems for waking up an electronic device having a wake-up receiver circuit. A signal is transmitted, carrying a wake-up frame (WUF) including a protocol data unit (PDU). A wake-up sequence is inserted in a portion ahead of the PDU. The wake-up sequence is used by the electronic device for detection of the WUF and identification of the intended recipient. The WUF also includes a wake-up identifier (WUID) that is used by the electronic device to authenticate the WUF. 1. A method of waking up a electronic device (ED) having a wake-up receiver circuit , the method comprising:transmitting a signal comprising a wake-up frame (WUF) within a physical protocol data unit (PPDU);wherein the WUF includes a wake-up sequence inserted in a portion within the PPDU, the wake-up sequence encoding information for detection of the WUF and identification of at least one intended recipient device; andwherein the WUF further includes a wake-up identifier (WUID) in a data portion following the wake-up sequence, the WUID encoding information for authenticating the WUF.2. The method of claim 1 , wherein the WUF includes a physical layer preamble (PHY preamble) claim 1 , and the wake-up sequence is inserted in the PHY preamble.3. The method of claim 1 , wherein the WUF includes a physical layer preamble (PHY preamble) and a physical layer header (PHY header) claim 1 , and the wake-up sequence is inserted between the PHY preamble and the PHY header.4. The method of wherein the information encoded in the WUID further is for identifying the at least one intended recipient device.5. The method of further comprising:generating the wake-up sequence using at least a portion of a device identifier of the intended recipient device as input for a sequence generation algorithm, the sequence generation algorithm being selected to generate sequences having good autocorrelation properties.6. The method of wherein the sequence generation algorithm is for generation of a Gold sequence.7. The ...

UPDATE MEMORY MANAGEMENT INFORMATION TO BOOT AN ELECTRONIC DEVICE FROM A REDUCED POWER MODE

Examples disclosed herein relate to updating memory management information to boot an electronic device from a reduced power mode. In one implementation, prior to entering a reduced power mode, an electronic device creates a snapshot of instructions in a logically volatile partition of a partitioned persistent memory and manage the snapshot as a logically persistent partition. Prior to entering a resume mode, the electronic device updates memory management information to remap a portion of the partitioned memory resource including the snapshot to be managed as a logically volatile partition. The electronic device may resume execution from the snapshot. 1. A computing system comprising:a persistent partitioned memory resource including a logically volatile partition and a logically persistent partition; [ create a snapshot of instructions in the logically volatile partition; and', copying the snapshot to a logically persistent partition; and', 'updating memory management information to remap the logically volatile partition as a logically persistent partition; and, 'manage the snapshot as a logically persistent partition by at least one of], 'prior to entering a reduced power mode,'}, 'prior to entering a resume mode, update memory management information to remap a portion of the partitioned memory resource including the snapshot to be managed as a logically volatile partition;, 'a memory management module to 'resume execution from the snapshot.', 'a processing resource to2. The computing system of claim 1 , wherein the logically persistent partition includes used and available portions.3. The computing system of claim 1 , wherein updating memory management information comprises executing operating system instructions.4. The computing system of claim 1 , wherein the reduced power ode comprises at least one of: a sleep claim 1 , hibernate claim 1 , and standby mode.5. The computing system of claim 1 , wherein creating the snapshot comprises creating the snapshot in ...

Power Saving Mode Control Method and Device for Multiple Operating Systems, and Terminal

A power saving mode control method and device for multiple operating systems include: setting corresponding power saving modes for each of the multiple operating systems in advance; and determining an operating system of which a power saving mode is triggered, and causing the operating system of which the power saving mode is triggered to enter the corresponding power saving mode. 1. A method of power saving mode control for multiple operating systems , comprising:setting corresponding power saving modes for each of the multiple operating systems in advance; anddetermining an operating system of which a power saving mode is triggered, and causing the operating system of which the power saving mode is triggered to enter the corresponding power saving mode.2. The method of claim 1 , whereinsetting the corresponding power saving modes for each of the multiple operating systems in advance comprises:setting the power saving modes of multiple levels for each of the multiple operating systems in advance; anddetermining the operating system of which the power saving mode is triggered, and causing the operating system of which the power saving mode is triggered to enter the corresponding power saving mode comprises:determining the operating system of which the power saving mode is triggered and the level of the triggered power saving mode; andcausing the operating system of which the power saving mode is triggered to enter the power saving mode of the level.3. The method of claim 2 , wherein the multiple levels of the power saving modes include a first level claim 2 , a second level and a third level claim 2 ,the power saving mode of the first level performs a power saving setting of at least one of hardware and software which are used for the operating system,the power saving mode of the second level causes the operating system to enter a standby mode and merely reserving designated functions as wake-up sources of the operating system, andthe power saving mode of the third ...

METHOD AND ASSOCIATED APPARATUS FOR PERFORMING WAKE-UP MANAGEMENT ON NETWORK DEVICES

A method for performing wake-up management and an associated apparatus are provided, where the method is applied to at least one portion of a network system, and the network system includes a local area network (LAN). The method includes: utilizing a wake-on-LAN (WOL) agent device to receive device information of a network device, where the WOL agent device and the network device are positioned in the LAN, and the network device broadcasts the device information according to a predetermined communications protocol; utilizing the WOL agent device to update a wake-up management list in the WOL agent device according to the device information, where the wake-up management list includes the device information; and utilizing the WOL agent device to perform a WOL operation on the network device according to the wake-up management list. 1. A method for performing wake-up management , the method being applied to at least one portion of a network system , the network system comprising a local area network (LAN) , the method comprising:utilizing a wake-on-LAN (WOL) agent device to receive device information of a network device, wherein the WOL agent device and the network device are positioned in the LAN, and the network device broadcasts the device information of the network device according to a predetermined communications protocol;utilizing the WOL agent device to refer to the device information of the network device to update a wake-up management list in the WOL agent device, wherein the wake-up management list comprises the device information of the network device; andutilizing the WOL agent device to perform a WOL operation regarding the network device according to the wake-up management list.2. The method of claim 1 , wherein the network device refers to the predetermined communications protocol to perform at least one broadcast operation claim 1 , to allow the WOL agent device to determine a state transition of the network device; and the method further comprises:in ...

SOFTWARE OPERATION METHOD FOR MANAGING POWER SUPPLY AND APPARATUS USING THE SAME

A software operation method for managing power supply and an electronic apparatus using the same are provided. The electronic apparatus includes a controller configured to convert a state into a sleep state, to convert the sleep state into a wake-up state for every first interval and to execute the first software. The controller is configured to convert the wake-up state into the sleep state, if an execution of the first software ends. The controller is configured to convert the sleep state into the wake-up state for every second interval and to execute the second software. The controller is configured to convert the wake-up state into the sleep state, if an execution of the second software ends. A classification into the first software and the second software is made based on an execution period. 1. An electronic apparatus for managing power supply , comprising:a first memory configured to store information necessary for maintaining connection with a network;a second memory configured to store a first software and a second software;a transceiver configured to transmit or receive a data;a timer configured to check an execution period of the first software and the second software; and convert a state into a sleep state;', 'convert the sleep state into a wake-up state for every first interval and execute the first software;', 'covert the wake-up state into the sleep state, if an execution of the first software ends;', 'convert the sleep state into the wake-up state for every second interval and execute the second software; and', 'convert the wake-up state into the sleep state, if an execution of the second software ends, wherein a classification into the first software and the second software is made based on an execution period., 'a controller configured to2. The electronic apparatus as claimed in claim 1 , wherein the classification into the first software and the second software is further made based on a function to be performed.3. The electronic apparatus as ...

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING A SCHEDULER AND WORKLOAD MANAGER WITH SNAPSHOT AND RESUME FUNCTIONALITY

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a stateless, deterministic scheduler and work discovery system with interruption recovery. For instance, according to one embodiment, there is disclosed a system to implement a stateless scheduler service, in which the system includes: a processor and a memory to execute instructions at the system; a compute resource discovery engine to identify one or more computing resources available to execute workload tasks; a workload discovery engine to identify a plurality of workload tasks to be scheduled for execution; a cache to store information on behalf of the compute resource discovery engine and the workload discovery engine; a scheduler to request information from the cache specifying the one or more computing resources available to execute workload tasks and the plurality of workload tasks to be scheduled for execution; and further in which the scheduler is to schedule at least a portion of the plurality of workload tasks for execution via the one or more computing resources based on the information requested. Other related embodiments are disclosed. 1. A method performed by a system having at least a processor and a memory therein , wherein the method comprises:allocating a cache within the memory of the system to store information on behalf of a compute resource discovery engine and a workload discovery engine and a scheduler;identifying, via the compute resource discovery engine, a plurality of computing resources available to execute workload tasks and updating the cache specifying the identified computing resources;identifying, via the workload discovery engine, pending workload tasks to be scheduled for execution from one or more workload queues and updating the cache with the identified workload tasks; andexecuting a scheduler via the processor of the system, wherein the scheduler performs at least the following operations:retrieving information ...

WAKE-UP AND SCHEDULING OF FUNCTIONS WITH CONTEXT HINTS

Examples are described that relate to waking up or invoking a function such as a processor-executed application or a hardware device. The application or a hardware device can specify which sources can cause wake-ups and which sources are not to cause wake-ups. A device or processor-executed software can monitor reads from or writes to a region of memory and cause the application or a hardware device to wake-up unless the wake-up is specified as inhibited. The updated region of memory can be precisely specified to allow a pinpoint retrieval of updated content instead of scanning a memory range for changes. In some cases, a write to a region of memory can include various parameters that are to be used by the woken-up application or a hardware device. Parameters can include a source of a wake-up, a timer to cap execution time, or any other information. 1. An apparatus comprising:a memory device comprising at least one memory region anda function scheduler to monitor for an access to at least one memory region, wherein in response to an access to the least one memory region, the function scheduler is to write an identification of the accessed memory region into one or more registers and a target function associated with the at least one memory region is to read merely an accessed portion of the least one memory region based on the identification of the accessed portion in the one or more registers.2. The apparatus of claim 1 , wherein the function scheduler is to identify a source that requested a function wake-up and job-related information from a memory region to the one or more registers and comprising a processor claim 1 , whereinthe processor is to execute a monitoring application,the function scheduler is to awaken the monitoring application, andthe target function is to access the identification of the source and the job-related information from the one or more registers.3. The apparatus of claim 1 , wherein the function scheduler is to copy information about a ...

Methods and apparatus for boot time reduction in a processor and programmable logic device enviroment

Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.

MEMORY DEVICE AND A METHOD OF OPERATING THE SAME

A memory device in accordance with a described method of operation includes a read only memory (ROM) address controller and a suspend signal generator. The ROM address controller is configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and to suspend output of the plurality of operation ROM addresses in response to a suspend signal. The suspend signal generator is configured to generate the suspend signal that is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output. The suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored. 1. A memory device , comprising:a read only memory (ROM) address controller configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and configured to suspend output of the plurality of operation ROM addresses in response to a suspend signal; and wherein the suspend signal is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output, and', 'wherein the suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored., 'a suspend signal generator configured to generate the suspend signal,'}2. The memory device according to claim 1 , further comprising:a register configured to, in response to a test command, store a time code indicating the preset period and store a ROM address code indicating the suspend ROM address; anda ROM address decoder configured to provide the suspend ROM address obtained by decoding the ROM address code to the suspend signal generator.3. ...

Control method, control device and computer system

A control method and a control device applied in a computer system, and a computer system are described. The control method according to the embodiments of the present invention is applied in a computer system, wherein the computer system includes a system memory containing two divided storage areas with the two storage areas being respectively a first storage area and a second storage area. The control method includes loading a first operating system into the first storage area; running the first operating system; and starting up a system memory access drive by the first operating system, so as to load into the second storage area the pre-stored memory mapping data of the second operating system by the system memory access drive.

Method and device for advanced configuration and power interface (acpi) sleep-state support using cpu-only reset

A mechanism for firmware to gain control from the operating system of an Advanced Configuration and Power Interface (ACPI)-compliant computing device during sleep-state transitions even if the computing device lacks a dedicated means for such a change to occur is discussed. Embodiments of the present invention report a CPU-only reset register in place of a sleep control register for an ACPI-compliant computing device in which an operating system is attempting a sleep-state transition. A CPU reset value is substituted for a sleep type value in a sleep-state object and written to the CPU-only reset register that was reported instead of the sleep control register thereby triggering a CPU-only reset. Firmware code operating at a known CPU reset vector may perform specified processing and then authorize a transition to the originally requested sleep-state.

HIBERNATION BASED ON PAGE SOURCE

In some examples, a computing device includes a non-volatile memory, a volatile memory to store a page that is also stored in the non-volatile memory. As part of a hibernation process of the computing device, it is determined whether the page is sourced from a first type of non-volatile memory or a second type of non-volatile memory different from the first type of non-volatile memory. In response to determining that the page is sourced from the first type of non-volatile memory, cause storage of the page to the non-volatile memory, and in response to determining that the page is sourced from the second type of non-volatile memory, decline to store the page to the non-volatile memory. 1. A computing device comprising:a non-volatile memory;a volatile memory to store a page that is also stored in the non-volatile memory;a processor; and determine whether the page is sourced from a first type of non-volatile memory or a second type of non-volatile memory different from the first type of non-volatile memory,', 'in response to determining that the page is sourced from the first type of non-volatile memory, cause storage of the page from the volatile memory to the non-volatile memory, and', 'in response to determining that the page is sourced from the second type of non-volatile memory, decline to store the page from the volatile memory to the non-volatile memory., 'hibernation instructions executable on the processor to, as part of a hibernation process of the computing device2. The computing device of claim 1 , further comprising instructions executable on the processor to maintain a page table that tracks a plurality of pages claim 1 , wherein the page table includes information for each respective page of the plurality of pages that indicates which of a plurality of different types of non-volatile memory the respective page is sourced from claim 1 , the plurality of different types of non-volatile memory comprising the first type of non-volatile memory and the second ...

Storage Device, Memory Card, And Communicating Method Of Storage Device

A storage device includes a host interface configured to communicate with a host device according to a first protocol through an input terminal, an output terminal, and a clock terminal. The input terminal is configured to receive an input signal from the host device according to the first protocol. The output terminal is configured to output an output signal to the host device according to the first protocol. The clock terminal configured to receive a clock signal from the host device according to the first protocol. The host interface is configured to communicate with the host device according to a second protocol through the clock terminal, the second protocol being different from the first protocol. 1. A storage device , comprising: an input terminal configured to receive an input signal from the host device according to the first protocol,', 'an output terminal configured to output an output signal to the host device according to the first protocol, and', 'a clock terminal configured to receive a clock signal from the host device according to the first protocol,, 'a host interface configured to communicate with a host device according to a first protocol through,'}wherein the host interface is configured to communicate with the host device according to a second protocol through the clock terminal, the second protocol being different from the first protocol.2. The storage device of claim 1 , wherein the first protocol is a Universal Flash Storage (UFS) protocol.3. The storage device of claim 1 , wherein the host interface is configured to communicate with the host device according to the first protocol in a first mode claim 1 , andcommunicate with the host device according to the second protocol in a second mode.4. The storage device of claim 3 , wherein the input terminal is deactivated in the second mode.5. The storage device of claim 3 , wherein in the second mode claim 3 , the clock signal is based on the second protocol claim 3 , and the host interface is ...

Multiple Hardware-Separated Computer Operating Systems within a Single Processor Computer System to Prevent Cross-Contamination between Systems

Using a single processor, separate and independent hardware-enforced operating systems (OS's) are created in a computer, each OS inaccessible by another OS so that malware introduced in one OS cannot access and contaminate another. With a trusted switching mechanism, only one OS is active at any time yet switching between OS's occurs quickly by user action, without need to save open data and/or close the active OS, and/or reboot the inactive OS, yet on activation, the previously inactive OS resumes back where it was left off and no OS rebooting is required. 1. A method of switching and isolating a plurality of OS's on a computer system providing a separate hardware-protected domain for performing switching , but not having a virtual machine hypervisor , the method comprising:Starting the plurality of OS's when the computer system boots, accepting a boot command to identify a first OS that will continue to run in an active state, and placing the remaining second OS's in a suspended state;User initiating switch from the first OS to a second operating system;Suspending the first operating system, assigning the first operating system's memory resources to secure status so the computer hardware will prevent the second OS from accessing the first operating system's memory resources, resetting internal devices, assigning the second operating system's memory resources to normal status, and returning control to the second OS so it will run with full access to the computer's resources;Second OS resuming from the point of previous suspension.2. The method of claim 1 , further comprising suspending first OS by resetting or cutting power of internal computer system devices and putting CPU and RAM into a minimum power state just sufficient to retain its data.3. The method of claim 1 , wherein the computer system is a personal computer claim 1 , laptop claim 1 , mobile communication device claim 1 , smartphone or tablet.4. The method of claim 1 , wherein the protected hardware ...

Protection against unintended content change in dram during standby mode

Systems, methods, and apparatus related to protecting data stored in volatile memory of a computing system during a standby mode. In one approach, a first signature is generated for data stored in volatile memory. In some cases, the stored data may include sensor data obtained from one or more sensors of a vehicle, mobile device or other electronic device. The first signature is stored in a non-volatile memory device, and then the computing system enters the standby mode. Subsequently, after exiting the standby mode, a second signature is generated for the data stored in the volatile memory. The first signature is read from the non-volatile memory device and compared to the second signature. A signature mismatch indicates that an unintended change has occurred in the stored data during the standby mode. One or more remedial actions are performed by the computing system in response to this signature mismatch.

Method for calculating power-on hours of an electronic device and electronic device utilizing the same

An electronic device includes a processor, a timer and a memory device. The memory device stores a value for power-on hour(s). During the process of booting the electronic device, the processor triggers the timer to start counting down. When the timer expires, the processor updates the value of power-on hour(s).

CONTROL METHOD BASED ON SCREEN-OFF GESTURES, AND STORAGE MEDIUM AND MOBILE TERMINAL THEREOF

A control method based on screen-off gestures, storage medium and a mobile terminal thereof are disclosed. A first screen-off gesture can be acquired when a display screen is in a screen-off state, and a corresponding first target application can be determined according to the first screen-off gesture. When it is detected that a split-screen event is triggered, a second screen-off gesture can be acquired, and a corresponding second target application can be determined according to the second screen-off gesture. The display screen can be waked up, and the first target application and the second target application can be opened in a split-screen mode. 1. A control method based on screen-off gestures , comprising:acquiring a first screen-off gesture when a display screen is in a screen-off state, and determining a corresponding first target application according to the first screen-off gesture;detecting that a split-screen event is triggered, acquiring a second screen-off gesture, and determining a corresponding second target application according to the second screen-off gesture; andwaking up the display screen and opening the first target application and the second target application in a split-screen mode.2. The method of to claim 1 , wherein detecting that a split-screen event is triggered and acquiring a second screen-off gesture comprises:detecting whether a split-screen event is triggered within a first preset duration; andacquiring a second screen-off gesture if it is detected that e split-screen event is triggered.3. The method of claim 2 , wherein after detecting whether the split-screen event is triggered within a first preset duration claim 2 , the method further comprises:waking up the display screen and opening the first target application in the full-screen mode if it is not detected that the split-screen event is triggered.4. The method of claim 1 , wherein detecting that a split-screen event triggered and acquiring a second screen-off gesture comprises ...

SOLID-STATE DRIVE WITH NON-VOLATILE RANDOM ACCESS MEMORY

A solid-state drive includes a flash memory device, a power loss protection circuit, a dynamic random access memory (RAM) coupled to the power loss protection circuit, and a controller configured to direct I/O requests to either the flash memory drive or the RAM. Because the controller can direct I/O request to the RAM, the RAM is revealed as a separate mass storage device to a host. Consequently, the RAM provides additional and significantly higher performance storage capacity to the solid-state drive. 1. A data storage device of a host device , comprising:a flash memory device;a volatile random access memory (RAM) that comprises a first and a second region and is coupled to a power loss protection circuit; and store in the first region of the RAM a mapping table that maps a first portion of logical block addresses (LBAs) to respective physical locations in the flash memory device and a second portion of the LBAs to respective physical locations in the second region of the RAM, and', 'perform read and write operations using the mapping table stored in the first region of the RAM in response to commands from the host device, which reference either the first or the second portion of the LBAs., 'a controller configured to2. The data storage device of claim 1 , wherein the controller claim 1 , in response to a write command from the host device claim 1 , consults the mapping table to determine a target physical location to which an LBA referenced in the write command is mapped claim 1 , and stores write data associated with the write command in the target physical location.3. The data storage device of claim 1 , wherein the controller is further configured to claim 1 , in response to receiving a power loss indication from the power loss protection circuit claim 1 , copy data that are associated with the second portion of the LBAs and stored in respective physical locations in the second region to a reserved region of the flash memory device.4. The data storage device ...

SYSTEM AND METHODS FOR AN IN-VEHICLE COMPUTING SYSTEM

Embodiments are disclosed for controlling power modes of a computing system. In some embodiments, a method for an in-vehicle computing system includes, while the vehicle is shut down, operating the system in a suspend mode with volatile memory on standby, and determining whether a reboot may be completed before a next anticipated vehicle start. The method may further include, if it is determined that a reboot may be completed before the next anticipated vehicle start, performing a reboot of the system. 1. A method for an in-vehicle computing system , comprising: operating the system in a suspend mode with volatile memory on standby;', 'determining whether a reboot may be completed before a next anticipated vehicle start; and', 'if it is determined that a reboot may be completed before the next anticipated vehicle start, performing a reboot of the system., 'while the vehicle is shut down,'}2. The method of claim 1 , further comprising claim 1 , if it is determined that a reboot may not be completed before the next anticipated vehicle start claim 1 , continuing to operate the system in the suspend mode claim 1 , wherein the system transitions from a running mode to the suspend mode responsive to a vehicle shut down operation.3. The method of claim 1 , wherein the determination of whether a reboot may be completed before a next anticipated vehicle start comprises determining whether a predetermined duration has elapsed since vehicle shut down claim 1 , and wherein the reboot is performed without any user input only if it is determined that the reboot may be completed before the next anticipated vehicle start.4. The method of claim 1 , wherein the determination of whether a reboot may be completed before a next anticipated vehicle start is based on whether a current time matches a scheduled time.5. The method of claim 1 , wherein the determination of whether a reboot may be completed before a next anticipated vehicle start is based on detection of absence of users from ...

PROCESSING UNIT, PROCESSOR, PROCESSING SYSTEM, ELECTRONIC DEVICE AND PROCESSING METHOD

The present application discloses a method, electronic device, processing unit, processing system, and system for processing operations. The method includes reading instruction information from an instruction tightly-coupled memory, reading data information from a data tightly-coupled memory, and executing one or more operations corresponding to one or more instructions, the one or more instructions being executed based at least in part on the instruction information and the data information. 1. A processing unit , comprising:an instruction tightly-coupled memory that is configured to store instruction information and not data information;a data tightly-coupled memory that is configured to store data information and not instruction information; anda processor core, the processor core being configured to execute one or more instructions, wherein in connection with executing the one or more instructions, the processor core reads instruction information from the instruction tightly-coupled memory, and reads data information from the data tightly-coupled memory.2. The processing unit of claim 1 , wherein the instruction tightly-coupled memory stores only the instruction information claim 1 , and the data tightly-coupled memory stores only the data information.3. The processing unit of claim 2 , wherein the instruction information indicates one or more operations to be executed claim 2 , and the data information indicates one or more operands corresponding to the one or more operations indicated by the instruction information.4. The processing unit of claim 1 , wherein a capacity of the instruction tightly-coupled memory is less than a capacity of the data tightly-coupled memory.5. The processing unit of claim 4 , wherein the capacity of the instruction tightly-coupled memory is 64 kb claim 4 , and the capacity of the data tightly-coupled memory is 128 kb.6. The processing unit of claim 1 , wherein:the instruction tightly-coupled memory stores instruction information of ...

BUILDING A RESILIENT OPERATING SYSTEM BASED ON DURABLE SERVICES WITH KERNEL SUPPORT

In one embodiment, a method includes generating a handle that references a checkpoint for a service, sending the handle to the service, wherein the handle is configured to be used by the service to store one or more states of the service in the checkpoint, determining that the service needs to be restarted, restarting the service, accessing the handle for the checkpoint, and sending the handle for the checkpoint to the restarted service, wherein the handle for the checkpoint is configured to be used by the restarted service to restore the one or more states. 1. A method comprising , by an operating system executing on a computing device:generating, for a first service, a handle that references a checkpoint;sending the handle to the first service, wherein the handle is configured to be used by the first service to store one or more states of the first service in the checkpoint;determining that the first service needs to be restarted;restarting the first service;accessing the handle for the checkpoint; andsending the handle for the checkpoint to the restarted first service, wherein the handle for the checkpoint is configured to be used by the restarted first service to restore the one or more states.2. The method of claim 1 , wherein the first service is associated with a monitor claim 1 , and wherein determining that the first service needs to be restarted is based on the monitor.3. The method of claim 1 , further comprising generating a first key for the checkpoint claim 1 , wherein accessing the handle for the checkpoint is based on the first key.4. The method of claim 1 , wherein the first service is a component of the operating system.5. The method of claim 1 , wherein determining that the first service needs to be restarted is based on an indication that the first service is nonresponsive.6. The method of claim 1 , wherein accessing the handle comprises accessing a service-key index comprising a plurality of entries corresponding to a plurality of services claim ...

INTER-PROCESSOR COMMUNICATION

A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor. 1. An integrated circuit device comprising:a first processing subsystem comprising:a first local bus;a first processor connected to the first local bus;a first set of one or more local peripherals connected to the first local bus; anda first bridge unit connected to the first local bus;a second processing subsystem comprising:a second local bus;a second processor connected to the second local bus;a second set of one or more local peripherals connected to the second local bus;a local-event line, between the second bridge unit and a peripheral of the second set of peripherals, for sending a local event signal from the second bridge unit to said peripheral; anda second bridge unit connected to the second local bus; and the first processing subsystem, the second processing subsystem, and the electrical interconnect are integrated on a common semiconductor substrate;', 'the first bridge unit comprises a task register, accessible over the first local bus;', detect a write to the task register; and', 'respond to the write by sending an event signal over the electrical interconnect to the second bridge unit, and', 'the second bridge unit is configured, or is configurable, to:', 'receive the event signal from the first bridge unit;', 'send an interrupt signal to the second processor in response to receiving the event signal; and', 'send a local ...

MEMORY CONTROLLER AND OPERATING METHOD THEREOF

A memory controller capable of detecting a code having an error among codes stored in a Read Only Memory (ROM) controls a memory device. The memory controller includes: a code memory for storing codes used to perform an operation; a code executor for executing the codes stored in the code memory to perform the operation; a debug controller for setting a suspend code address for suspending the execution of the codes used to perform the operation; an initialization controller for controlling an initialization operation of at least one of the debug controller and the code executor; and an interfacing component for receiving a suspend code setting request corresponding to an operation of setting the suspend code address and providing the received suspend code setting request to the debug controller. 1. A memory controller comprising:a code memory configured to store codes used to perform an operation;a code executor configured to execute the codes stored in the code memory to perform the operation;a debug controller configured to set a suspend code address for suspending the execution of the codes used to perform the operation;an initialization controller configured to control an initialization operation of at least one of the debug controller and the code executor; andan interfacing component configured to receive a suspend code setting request corresponding to an operation of setting the suspend code address and provide the received suspend code setting request to the debug controller.2. The memory controller of claim 1 , wherein a processor including the debug controller and the code executor and the initialization controller is selectively coupled to a debugger for detecting an operation error of the memory controller claim 1 , which is caused by codes performed after the suspend code claim 1 , through the interfacing component claim 1 ,wherein the processor or the initialization controller is coupled to the debugger through the interfacing component, based on ...

Autonomous Sleep Mode

A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely transparent to host software. When the device is in a sleep mode and incoming data is detected, the device begins a wake-up procedure and data is routed to a first, transitional memory. The size of the transitional memory is selected such that it is capable of buffering data received during time required for the system memory to stabilize from wake-up. Once a second, extended memory is stabilized, the data is buffered from the transitional memory to the extended memory. The device resumes normal operation when its processor has initialized and can read data from the extended memory. 1. A device , comprising:an input buffer coupled to an input from a host device;a transitional memory coupled to the input buffer, the transitional memory configured to operate while the device is in a sleep-mode power state; andan extended memory coupled to the transitional memory, the extended memory configured to receive data from the transitional memory after waking up from a sleep-mode.2. The device of claim 1 , wherein a transitional memory size is selected based upon a maximum amount of data that can be received from the host while the extended memory is waking up from the sleep mode.3. The device of claim 1 , wherein the extended memory begins receiving data from the transitional memory when a low dropout (LDO) regulator stabilizes during a wake-up process.4. The device of claim 1 , wherein an extended memory size is selected based upon a maximum amount of data that can be received from the transitional memory while a device processor is waking up from the sleep mode.5. The device of claim 1 , further comprising:a system clock coupled to the input buffer, the transitional memory, and the extended memory; anda host clock signal interface coupled to the input buffer, the transitional memory, and the extended memory.6. The device of ...

METHOD AND APPARATUS FOR REDUCING CONSUMPTION OF STANDBY POWER THROUGH DETECTION OF IDLE STATE OF SYSTEM

A method and apparatus for reducing the consumption of standby power through the detection of the idle state of a system are disclosed herein. The apparatus includes a task information acquisition unit, an idle state detection unit, a power reduction determination unit, and a power reduction performance unit. The task information acquisition unit acquires task information from a scheduler. The idle state detection unit detects whether at least one apparatus enters an idle state based on the task information. The power reduction determination unit determines whether to perform the reduction of power consumption of the at least one apparatus based on at least one of an idle counter and the time elapsed after occurrence. The power reduction performance unit performs low-power mode using an apparatus manager corresponding to the at least one apparatus if it is determined that the reduction of power consumption is to be performed. 1. An apparatus for reducing consumption of standby power through detection of an idle state of a system , comprising:a task information acquisition unit configured to acquire task information from a scheduler that manages processing of one or more tasks;an idle state detection unit configured to detect whether at least one apparatus enters an idle state, in which there is no task to be processed, based on the task information;a power reduction determination unit configured to determine whether to perform reduction of power consumption of the at least one apparatus based on at least one of an idle counter and time elapsed after occurrence; anda power reduction performance unit configured to perform low-power mode for reducing consumption of standby power of the at least one apparatus using an apparatus manager corresponding to the at least one apparatus if it is determined that the reduction of power consumption is to be performed.2. The apparatus of claim 1 , wherein the power reduction determination unit determines that the reduction of power ...

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING METHOD

An information processing apparatus capable of communicating with machines configured to operate in a first operation mode and in a second operation mode in which energy consumption is lower than the first operation mode via a network is provided. The information processing apparatus includes a processor configured to obtain from the machines data sets including a use time information item generated when the machines are used; and generate time information used for transitioning from the first operation mode to the second operation mode by calculating differences between the use time information items of the data sets for each of the machines. 1. An information processing apparatus capable of communicating with machines configured to operate in a first operation mode and in a second operation mode in which energy consumption is lower than the first operation mode via a network , the information processing apparatus comprising:a processor configured toobtain from the machines data sets including a use time information item generated every time the machines are used; andgenerate time information used for transitioning from the first operation mode to the second operation mode by calculating differences between the use time information items of the data sets for each of the machines.2. The information processing apparatus according to claim 1 , the processor further configured totransmit the generated time information to a second machine different from a first machine that has transmitted the data sets, or to the first machine.3. The information processing apparatus according to claim 2 , the processor further configured toobtain extract condition information used for extracting the data sets used for the time information calculation from a terminal apparatus connected to the information processing apparatus via the network or from the first machine, whereinthe processor generates the time information by using the data sets extracted according to the obtained extract ...

SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM

A method of implementing a multi-threaded device driver for a computer system is disclosed. According to one embodiment, a polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread. 1. A method of partitioning a polling device driver into a plurality of driver threads for controlling a device of a computer system , the method comprising:checking a first device state of the device, the first device state having an unscouted state and a scouted state;determining that the first device state of the device is in the unscouted state;changing the first state of the device to the scouted state;checking a second device state of the device, the second device state having an inactive state and an active state;determining that the second device state of the device is in the inactive state;changing the second state of the device to the active state;executing an operation on the device during a pre-determined time slot configured for a first driver thread of the plurality of driver threads; andchanging the first state of the device to the unscouted state after the pre-determined time slot expires.2. The method of claim 1 , wherein the device is in one of four device states claim 1 , wherein the four device states comprise an unscouted/inactive state claim 1 , an unscouted/active state ...

PATTERN COALESCING FOR REMOTE WAKE-ENABLED APPLICATIONS

In various embodiments, methods and systems for managing wake-enabled transport connections of wake-enabled applications is provided. A set of ports is designated as a wake-enabled port set. An operating system (OS) of a computing device running applications plumbs the multiport wake pattern to the one or more network interface controllers (NIC) of the computing device. A wake-enabled application acquires a port from the wake-enabled port set. The OS makes a determination that the application is wake-enabled and as such, assigns a port, from the wake-enable port set, to the wake-enabled application. Upon receiving a packet at the NIC, a determination is made whether the packet corresponds to a wake-enabled transport connection based on comparing the packet to the multiport wake pattern. Upon matching the packet to the multiport wake pattern, the NIC communicates with the OS to wake a portion of the wake-enabled application associated with the wake-enabled transport connection. 1. One or more computer storage media storing computer-readable instructions that , when used by one or more computing devices , cause the one or more computing devices to perform operations for managing wake-enabled applications , the operations comprising:receiving a packet;determining that the packet corresponds to a wake-enabled transport connection of a wake-enabled application, based on comparing the packet to a multiport wake pattern to identify that a port in the packet matches a port in a wake-enabled port set associated with the multiport wake pattern, wherein the multiport wake pattern is a wild card pattern corresponding to the wake-enabled port set comprising a plurality of ports, and the plurality of ports are assigned to wake-enabled applications to support wake functionality; andwaking at least a portion of the wake-enabled application associated with the wake-enabled transport connection based at least in part on the identified port.2. The media of claim 1 , wherein the packet ...

DEVICE POWER SAVING DURING EXERCISE

A method includes: supporting a normal operation mode, during which functionalities of a portable apparatus are available through an operating system of the apparatus, wherein the operating system includes a plurality of layers including a kernel and library functions layer; supporting a limited operation mode during which the apparatus is configured to execute a physical activity algorithm based on physical activity data corresponding to a physical activity session performed by a user of the apparatus, wherein the physical activity algorithm applies a direct low-level hardware access bypassing at least the layers above the kernel and the library functions-layer; and switching between the normal operation mode and the limited operation mode 1. A smartwatch comprising:a motion sensor configured to measure a motion;a positioning unit configured to obtain a location;an optical heart activity sensor configured to optically measure a heart activity;a display configured to act as a user interface;a touch controller configured to make the display touch sensitive;a wireless interface configured to receive data;one or more memories including computer program code; and supporting a normal operating system operation mode during which the smartwatch is configured to run an operating system, control functionality of the display and the touch controller, display notifications regarding incoming calls, messages and social media updates received via the wireless interface, and measure physical activity using data obtained from the motion sensor, data obtained from the positioning unit and data obtained from the optical heart activity sensor;', 'supporting a limited exercise operation mode during which the smartwatch is configured to control functionality of the display, switch off the touch controller, enable the wireless interface to establish a wireless link with an external physiology exercise sensor, suppress reception of notifications related to incoming calls, messages and ...

SYSTEM ON CHIP FOR REDUCING WAKE-UP TIME, METHOD OF OPERATING SAME, AND COMPUTER SYSTEM INCLUDING SAME

A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader. 1. A method of operating a system on chip (SoC) , the method comprising:executing a first boot loader stored in an internal read-only memory (ROM) based on a reset signal;selecting one of non-volatile memories as a booting device using the first boot loader;loading a second boot loader from the booting device into a first internal static random access memory (SRAM) and loading a third boot loader from the booting device into a second internal SRAM; andloading an operating system (OS) from the booting device into a main memory as the second boot loader is executed.2. The method of claim 1 , further comprising:executing the second boot loader, wherein the second boot loader is executed after the third boot loader loaded into the second internal SRAM passes integrity checking.3. The method of claim 1 , wherein the non-volatile memories are flash-based memories.4. The method of claim 1 , further comprising:causing the SoC to enter a power-down mode;cutting off a power supply to the internal ROM and the first internal SRAM during the power-down mode; andcontinuing supplying power to the second internal SRAM in the power-down mode.5. The method of claim 4 , further comprising:executing the first boot loader based on a wake-up interrupt signal;executing, using ...

LOW LATENCY BOOT FROM ZERO-POWER STATE

An embodiment of a semiconductor package apparatus may include technology to determine if a wake event corresponds to a zero-power state of a computer operating system, determine if a run-time state is valid to wake the operating system from the zero-power state, and wake the operating system from the zero-power state to the run-time state if the run-time state is determined to be valid. Other embodiments are disclosed and claimed. 1. An electronic processing system , comprising:a processor;memory communicatively coupled to the processor; and determine if a wake event corresponds to a wake from a zero-power state of an operating system (OS) of the electronic processing system,', 'determine if a run-time state is valid to wake the OS from the zero-power state, and', 'wake the OS from the zero-power state to the run-time state if the run-time state is determined to be valid., 'logic communicatively coupled to the processor to2. The system of claim 1 , wherein the logic is further to:determine if a wake vector is available, the wake vector including information related to a transition of the OS to the zero-power state; andwake the OS from the zero-power state based on the wake vector, if the wake vector is determined to be available.3. The system of claim 2 , wherein the logic is further to:replay an initialization sequence from the zero-power state, if the wake vector is determined to be available.4. The system of claim 2 , wherein the logic is further to:determine if the memory includes a multi-level memory with at least one level of non-volatile memory.5. The system of claim 4 , wherein the logic is further to:receive an indication of a transition to a zero-power state; andcreate the wake vector, if the memory is determined to include the multi-level memory with at least one level of non-volatile memory.6. The system of claim 5 , wherein the logic is further to:initiate a flush of volatile memory to the non-volatile of the multi-level memory based on the received ...

Preventing Computing Device from Timing Out

A computer-implemented method for controlling time out of a device is disclosed according to an aspect of the subject technology. The method comprises determining whether at least one content-viewing criterion is satisfied; if the at least one content-viewing criterion is satisfied, then preventing the device from timing out upon expiration of a time-out period; and if the at least one content-viewing criterion is not satisfied, then timing out the device upon expiration of the time-out period. 120-. (canceled)21. A method for controlling time-out operations of a computing device , the method comprising:outputting, on a display of the computing device, content;initially recognizing, using a front-facing camera adjacent to the display, a face of a user of the computing device;determining whether a time-out period of the computing device is or is about to expire since recognizing the face of the user;responsive to determining the time-out period is or is about to expire, determining, from subsequently recognizing the face of the user, whether the user is viewing the content on the display at an initial time after the time-out period is or is about to expire;responsive to determining that the user is viewing the content on the display at the initial time after the time-out period is or is about to expire, continuing the outputting the content for display;determining, from thirdly recognizing the face of the user or not seeing the face of the user at all, that the user is no longer viewing the content on the display at a subsequent time after the initial time and after the time-out period is or is about to expire; andresponsive to determining that the user is no longer viewing the content on the display at the subsequent time after the initial time and after the time-out period is or is about to expire, controlling the display to conserve battery life of the computing device.22. The method of claim 21 , wherein controlling the display to conserve battery life of the ...

Information processing apparatus and method thereof

Data representing the storage state of the main memory of an information processing device is saved in a secondary storage device. The data saved in the secondary storage device is transferred to the main memory in reactivation of the information processing device to restore the storage state of the main memory. A cache allocated in the main memory is deallocated before generating data to be saved.

RESUMING A SYSTEM USING STATE INFORMATION

A non-volatile main memory stores state information of at least one program executing in the system, and metadata indicating whether a system is to be resumed to a prior state on a next start. As part of restarting the system from a mode in which power is removed from the system, the system is resumed to the prior state using the state information stored in the non-volatile main memory, in response to the metadata indicating that the system is to be resumed to the prior state. 1. A system comprising:a non-volatile main memory to store state information of at least one program executing in the system, and metadata indicating whether the system is to be resumed to a prior state or to be booted on a next start and 'as part of restarting the system from a mode in which power is removed from the system, resume the system to the prior state using the state information stored in the non-volatile main memory, in response to the metadata indicating that the system is to be resumed to the prior state.', 'at least one processor to2. The system of claim 1 , wherein the at least one processor is to resume the system as part of the restarting of the system in response to the metadata containing a first indication.3. The system of claim 2 , wherein the at least one processor is to boot the system as part of the restarting of the system in response to the metadata containing a second indication.4. The system of claim 1 , wherein the at least one processor includes a volatile memory to store volatile data claim 1 , and wherein the resuming includes restoring the volatile data to the volatile memory using the state information.5. The system of claim 1 , wherein the at least one program includes an operating system claim 1 , wherein the resuming includes continuing execution of the operating system starting from the prior state using the state information.6. The system of claim 1 , wherein the system is without a volatile main memory.7. The system of claim 1 , wherein the system is ...

OPERATION METHOD OF STORAGE SYSTEM AND HOST

A storage system shares a system memory of a host. An operation method of the storage system may include receiving a command including information about a shared memory from the host, receiving a stream command having no timeout from the host, and transmitting a first packet associated with the stream command to the host in response to the received stream command. The first packet includes information for accessing the shared memory. 1. An operation method executed by a storage system that shares a system memory of a host , the method comprising:receiving a command including information about a shared memory from the host;receiving a stream command having no timeout from the host; andtransmitting a first packet associated with the stream command to the host in response to the received stream command, whereinthe first packet comprises information for accessing the shared memory.2. The operation method of claim 1 , wherein the first packet is one of a response packet claim 1 , a data-in packet claim 1 , and a ready to transfer packet associated with the stream command3. The operation method of claim 2 , wherein the first packet is the data-in packet and comprises write data to be written in the shared memory and buffer offset information about a shared memory area in which the write data is to be written.4. The operation method of claim 2 , wherein:the first packet is the ready to transfer packet and comprises information about a buffer offset and a buffer length with respect to read data stored in the shared memory, andthe method further comprises receiving a data-out packet including the read data from the host after transmitting the first packet to the host.5. The operation method of claim 2 , wherein the first packet is the response packet and further comprises control information for controlling the shared memory.6. The operation method of claim 5 , wherein the control information corresponds to at least one of operations of copying claim 5 , moving claim 5 , and ...

METHOD AND SYSTEM FOR PROVIDING HYBRID-SHUTDOWN AND FAST STARTUP PROCESSES

In an example, in a method for providing a shutdown process for a computer system including an operating system (OS), basic input/output system (BIOS) firmware may capture a request from the OS to hardware of the computer system to enter into a hibernate state. In addition, the BIOS firmware may determine whether a hybrid-shutdown process is in process and in response to a determination that the hybrid-shutdown process is in process, may turn off the computer system instead of entering the computer system into the hibernate state. 1. A method for providing a shutdown process for a computer system , the computer system including an operating system (OS) , the method comprising:capturing, by basic input/output system (BIOS) firmware, a request from the OS to hardware of the computer system to enter the computer system into a hibernate state;determining, by the BIOS firmware, whether a hybrid-shutdown process is in process; andin response to a determination that the hybrid-shutdown process is in process, turning off the computer system instead of entering the computer system into the hibernate state.2. The method of claim 1 , further comprising:in response to a determination that the hybrid-shutdown process is not in process, entering the computer system into the hibernate state.3. The method of claim 1 , wherein determining whether a hybrid-shutdown process is in process further comprises determining that the hybrid-shutdown process is in process in response to an instruction to start the hybrid-shutdown process being received in the computer system and an instruction to start the hybrid-shutdown process being passed to an application that starts the hybrid-shutdown process.4. The method of claim 3 , wherein claim 3 , following receipt of the instruction to start the hybrid-shutdown process claim 3 , the OS is requested to prepare for the hibernate state by saving a current system state as a last system state claim 3 , said method further comprising:upon a next power- ...

Energy Efficient Sensor

A sensor is discloses that uses very little power by entering a sleep state, waking up, finding a sensor or other device to report to, then going back to sleep for the next sleep cycle. The sensor may need to add itself onto its network. To do so, keys are exchanged with the network provisioner, the sensor informs the network of its capabilities, and/or characteristics, etc, and the network determines which other sensors and other places in the network the sensor may talk with.

DIGITAL DEVICE FOR PERFORMING BOOTING PROCESS AND CONTROL METHOD THEREFOR

The present specification discloses a digital device for performing a hibernation booting process and a control method therefor. Here, the digital device according to an embodiment of the present invention comprises: a first memory; a second memory storing a snapshot image generated on the basis of pieces of page data of the first memory; and a control unit for generating the snapshot image, wherein the control unit primarily deduplicates duplicated page data in the first memory and selectively secondarily deduplicates duplicated page data by comparing the duplicated page data with the snapshot image prestored in the second memory, wherein data fragmentation is minimized through the secondary deduplication step. 1. A method for controlling a digital device for performing a booting process , the method comprising:removing duplicate page data from among page data stored in a first memory;comparing page data remaining after the removing with page data pre-stored in a second memory;selectively removing the duplicate page data depending on whether the duplicate page data is located in a hot cluster of the second memory as a result of the comparison; andgenerating a snapshot image based on page data remaining after the selective removing.2. The method of claim 1 , wherein the first memory includes a random access memory (RAM) claim 1 , andwherein the second memory includes a flash memory.3. The method of claim 1 , wherein the removing of the duplicate page data from among the page data stored in the first memory comprises:calculating a hash value on a page-by-page basis for the page data stored in the first memory; anddetermining whether the calculated hash value is duplicate,wherein, for page data having a duplicate hash value, only location information about the duplicate page data is stored in a mapping table.4. The method of claim 3 , wherein a mapping relationship between logical addresses of the page data stored in the first memory and physical addresses of page ...

HARDWARE DIRECTED CORE PARKING BASED ON PERFORMANCE AND ENERGY EFFICIENCY CAPABILITIES OF PROCESSING UNITS AND RUNTIME SYSTEM CHARACTERISTICS

Systems, apparatuses and methods may provide for technology that automatically determines a runtime performance of a plurality of heterogeneous processing units based on system-level thread characteristics, wherein the runtime performance is determined on a per performance class basis. The technology may also automatically determine a runtime energy efficiency of the heterogeneous processing units, wherein the runtime energy efficiency is determined on a per efficiency class basis. In one example, technology selectively unparks one or more of the heterogeneous processing units based on the runtime performance and the runtime energy efficiency.

Shadow Node With Cold And Warm Server Standby

An apparatus includes an operating environment including a motherboard and a processor, and a baseboard management controller (BMC) including circuitry configured to determine that another server is in a standby mode. The other server includes its own BMC and operating environment, and, in the standby mode, the second operating environment is powered down and the second BMC is powered only through a connection to the BMC of the apparatus. The BMC of the apparatus is further configured to determine that additional resources for execution by a system including the apparatus are to be activated. The BMC is further configured to send a control signal to the other BMC, wherein the control signal is configured to issue a wake-up signal to the other BMC to wake at least a portion of the other BMC's operating environment, and to provision the other BMC's operating environment.

Centralized Server Management For Shadow Nodes

An apparatus includes a communications interface and a management server. The management server is configured to access servers through the interface, determine that additional resources are needed for execution by a system, and determine that one of the servers is in a standby mode. In the standby mode, the server is powered down and a baseboard management controller (BMC) therein is only powered through a connection from the apparatus or another server of the network. The management server is configured to determine that additional resources for execution by the system from the server are to be activated and cause a wake-up signal to be sent to the BMC, wherein the wake-up signal is configured to cause the BMC to wake and provision the operating environment of the server.

Green NAND Device (GND) Driver with DRAM Data Persistence For Enhanced Flash Endurance and Performance

A Green NAND Device (GND) driver application queries AC line and battery status and then stores an image of processor states and caches and a resume routine to DRAM when power failure occurs. A DRAM image is then stored to flash memory for a persistent mode when battery power is available. The image in DRAM may be a partial image that includes entries, flushed caches, processor contexts, ramdisks, write caches, and a resume context. Endurance of flash memory is increased by a Super Enhanced Endurance Device (SEED) SSD. In a power down mode, the GND driver limits DRAM use and only caches in DRAM data that can be deleted on power down. Host accesses to flash are intercepted by the GND driver and categorized by data type. Paging files and temporary files cached in DRAM are optionally written to flash.

INFORMATION PROCESSING DEVICE, PERIPHERAL DEVICE CONTROL METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING FILTER DRIVER

In an information processing device, if the power state of a peripheral device changed by a class driver is the low-power state, in which the peripheral device consumes less power than in its normal state but its operation is limited, a filter driver below the class driver suspends controlling the peripheral device in accordance with a control request from an application program without passing through the class driver until the power state of the peripheral device returns to the normal state. 1. An information processing device comprising:a first application program configured to transmit a control request for a peripheral device;a second application program configured to run on an operating system on which the first application program runs and to transmit a control request for the peripheral device;a class driver configured to relay the control request from the first application program; anda filter driver sitting below the class driver and configured to control the peripheral device in accordance with the control request from the first application program through the class driver and to control the peripheral device in accordance with the control request from the second application program without passing through the class driver, wherein a power state management unit configured to change a power state of the peripheral device in accordance with a change request of the power state of the peripheral device from the class driver and to recognize the changed power state of the peripheral device; and', 'a control unit configured to control the peripheral device in accordance with the control request from the first application program and second application program, and, 'the filter driver comprisesif the power state of the peripheral device recognized by the power state management unit is a low-power state, the control unit suspends controlling the peripheral device in accordance with the control request from the second application program until the power state of ...

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT

According to an embodiment, an information processing device is connectable to a peripheral device and includes a buffer, a first operating system, a second operating system, and a monitor. The monitor is configured to enable the first operating system or the second operating system to execute in a switching manner. The monitor includes a switching controller that, when the second operating system issues an access request to the peripheral device, saves a state of the second operating system and suspends its execution as well as restores a state of the first operating system and restarts its execution. The first operating system includes a request input-output controller that reads the access request from the buffer, that divides the read access request into instructions in receivable units for the peripheral device, and that issues each instruction. The first operating system includes an access controller that accesses the peripheral device according to the instructions. 1. An information processing device connectable to a peripheral device , comprising:a buffer;a first operating system configured to control the information processing device;a second operating system configured to control the information processing device; anda monitor configured to execute either the first operating system or the second operating system to execute in a switching manner,the monitor includes a switching controller that, when the second operating system issues an access request with respect to the peripheral device, saves a state of the second operating system and suspends execution of the second operating system as well as restores a state of the firsL operating system and restarts execution of the first operating system, and [ reads, from the buffer, the access request written by the second operating system with respect to the peripheral device,', 'divides the read access request into instructions in receivable units for the peripheral device, and', 'issues each of the divided ...

Memory mapping for hibernation

A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory.

MEMORY SYSTEM AND OPERATION METHOD THEREOF

A memory system may include: a memory device that operates using a first voltage received from a host and suitable for storing a value of operation information, and waking up from a sleep state in response to a request of the host; and a controller that operates using a second voltage received from the host, and suitable for selectively resetting the memory device according to a result obtained by checking a value of operation information of the memory device, when waking up the memory device in a sleep state according to a request of the host. 1. A memory system comprising:a memory device that operates using a first voltage received from a host, wherein memory device is suitable for storing a value of operation information, and waking up from a sleep state in response to a request of the host; anda controller that operates using a second voltage received from the host,wherein the controller is suitable for checking the value of operation information and selectively resetting the memory device according to the value of operation information when the memory device wakes up from the sleep state.2. The memory system of claim 1 ,wherein the operation information is stored in a first storage region of the memory device and transmitted to a second storage region of the memory device when the memory device wakes up, andwherein the controller cannot access the first storage region and can access the second storage region.3. The memory system of claim 2 ,wherein the first voltage is selectively supplied to the memory device according to operation of the host when the memory device is in the sleep state.4. The memory system of claim 3 ,wherein the operation information stored in the first storage region is retained while the first voltage is not supplied to memory device, andwherein the operation information stored in the second storage region is reset when the first voltage is not supplied to the memory device.5. The memory system of claim 4 ,wherein the controller reads the ...

Equitable Sharing of System Resources in Workflow Execution

A method may be practiced in a distributed computing environment that provides computing resources to a plurality tenants. The method includes acts for allocating a limited set of system resources to the tenants. The method includes identifying a resource slice. The method further includes identifying an executing tenant workload. Checkpoint characteristics are identified for the executing tenant workload. Based on the checkpoint characteristics and the resource slice, a task eviction event is identified.

ELECTRONIC DEVICE AND OPERATING METHOD THEREOF, AND NETWORK SYSTEM

An operating method of an electronic device including controllers includes updating, by a first-level controller of the controllers, a first-level firmware of the the first-level controller, writing, by the first-level controller, a second-level firmware to one of second-level controllers of the controllers having a lower level than the first-level controller, booting, by the one of the second-level controllers, by performing a reset operation, verifying, by the first-level controller or the booted second-level controller, whether there is a target second-level controller with out-of-date firmware, and writing, by the first-level controller or the booted second-level controller in response to a result of the verifying, the second-level firmware to the target second-level controller. 1. An operating method of an electronic device including controllers , the operating method comprising:updating, by a first-level controller of the controllers, a first-level firmware of the the first-level controller;writing, by the first-level controller, a second-level firmware to one of second-level controllers of the controllers having a lower level than the first-level controller;booting, by the one of the second-level controllers, by performing a reset operation;verifying, by the first-level controller or the booted second-level controller, whether there is a target second-level controller with out-of-date firmware; andwriting, by the first-level controller or the booted second-level controller in response to a result of the verifying, the second-level firmware to the target second-level controller.2. The operating method of claim 1 , wherein the writing of claim 1 , by the first-level controller claim 1 , the second-level firmware to the one of the second-level controllers comprises writing claim 1 , by the first-level controller claim 1 , the second-level firmware stored in an external memory to the one of the second-level controllers.3. The operating method of claim 1 , further ...

IDENTITY VERIFICATION METHOD AND APPARATUS

A system detects that a target service program is being executed by a computing device. The target service program is one of a plurality of pre-defined service programs to be suspended to complete an identity verification of a user using the target service program. Execution of the target service program is suspended on the computing device. An identity verification program is executed on the computing device. The identity verification program is configured to perform the identity verification of the user to obtain an identity verification result indicating whether an identity of the user is verified. The identity verification program is independent from the target service program. 1. A computer-implemented method , comprising:detecting that a target service program is being executed by a computing device, the target service program being one of a plurality of pre-defined service programs to be suspended to complete an identity verification of a user using the target service program;suspending execution of the target service program on the computing device; andexecuting an identity verification program on the computing device, the identity verification program configured to perform the identity verification of the user to obtain an identity verification result indicating whether an identity of the user is verified, wherein the identity verification program is independent from the target service program.2. The computer-implemented method of claim 1 , wherein detecting that the target service program is executing comprises:detecting that the target service program is executing a target process associated with a service interface; anddetermining that the target process is one of a plurality of pre-defined target processes to be used to identify target service programs to be suspended.3. The computer-implemented method of claim 2 , wherein the target process calls a target function used to display the service interface claim 2 , and wherein the target function is one of ...

DEVICE POWER SAVING DURING EXERCISE

A method includes: supporting a normal operation mode during which functionalities of a portable apparatus are available through an operating system of the apparatus, wherein the operating system includes a plurality of layers including a kernel and library functions-layer; supporting a limited operation mode during which the apparatus is configured to execute a physical activity algorithm based on physical activity data corresponding to a physical activity session performed by a user of the apparatus, wherein the physical activity algorithm applies a direct low-level hardware access bypassing at least the layers above the kernel and the library functions-layer; and switching between the normal operation mode and the limited operation mode 120-. (canceled)21. A smartwatch comprising:a motion sensor configured to measure a motion;a GPS receiver configured to receive a GPS signal;an optical heart activity sensor configured to optically measure a heart activity;a touch sensitive color display configured to act as a user interface;a high-power processing unit configured to, during a normal operation mode, run an operating system, control functionality of the touch sensitive color display, and measure physical activity using data obtained from the motion sensor, data obtained from the GPS receiver and the data obtained from the optical heart activity sensor; and during a watch operation mode, run a watch configured to keep track of the time, run a physical activity algorithm, and measure physical activity using data obtained from the motion sensor, and', 'during a limited operation mode, measure physical activity using data obtained from the motion sensor, data obtained from the GPS receiver and the data obtained from the optical heart activity sensor,, 'a low power processing unit configured to,'}wherein the low power processing unit has a lower power consumption in performing a given task than the high-power processing unit.22. The smartwatch of claim 21 , wherein ...

INFORMATION PROCESSING APPARATUS INCLUDING MAIN SYSTEM AND SUBSYSTEM

An information processing apparatus according to an exemplary embodiment of the present invention includes a main system and a subsystem. The main system includes a first control unit configured to, before the information processing apparatus shifts to a power-saving state, develop a boot image to be executed by the subsystem in a memory of the subsystem. The subsystem includes a second control unit configured to, in a case where the information processing apparatus returns from the power-saving state, issue an instruction to execute the boot image developed in the memory. The subsystem further includes a third control unit configured to execute the boot image developed in the memory according to the instruction issued by the second control unit. 1. An information processing apparatus comprising:a main system; anda subsystem,wherein the main system includes a first control unit configured to, before the information processing apparatus shifts to a power-saving state, develop a boot image to be executed by the subsystem in a memory of the subsystem, andwherein the subsystem includes a second control unit configured to, in a case where the information processing apparatus returns from the power-saving state, issue an instruction to execute the boot image developed in the memory, and a third control unit configured to execute the boot image developed in the memory according to the instruction issued by the second control unit.2. The information processing apparatus according to claim 1 , wherein the subsystem further includes a storage unit configured to store a boot program to be executed by the second control unit in a case where the information processing apparatus returns from the power-saving state claim 1 , andwherein, in a case where the information processing apparatus returns from the power-saving state, the second control unit instructs the third control unit to execute the boot image by executing the boot program stored in the storage unit.3. The information ...

Processor To Pre-Empt Voltage Ramps For Exit Latency Reductions

In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed. 1. A processor comprising:a plurality of cores; anda power controller including a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state.2. The processor of claim 1 , wherein the voltage ramp logic is claim 1 , responsive to a voltage increase request for the second voltage claim 1 , to issue a plurality of commands to the voltage regulator to cause the voltage regulator to ramp from the first voltage to the second voltage in a plurality of steps.3. The processor of claim 2 , wherein the voltage ramp logic is to calculate a voltage increase value for one of the plurality of steps based on a current voltage value and a step value and issue one of the plurality of commands including the voltage increase value to the voltage regulator.4. The processor of claim 3 , further comprising a configuration storage to store the step value claim 3 , the step value comprising a programmable step voltage.5. The processor of claim 2 , wherein the power controller further comprises a second logic to send a freeze signal to the voltage ramp logic responsive to the request for the second core to exit the low power state when the voltage regulator is in the voltage ramp from the first voltage to the second voltage.6. The processor of claim 5 , wherein the voltage ramp logic is to suspend issuance of the plurality of commands to the voltage regulator responsive to the freeze signal.7. The processor of claim 5 , wherein the second logic is to determine a third voltage claim 5 , wherein the third voltage is less than ...

Short-Circuiting Normal Grace-Period Computations In The Presence Of Expedited Grace Periods

A technique for short-circuiting normal read-copy update (RCU) grace period computations in the presence of expedited RCU grace periods. The technique may include determining during normal RCU grace period processing whether at least one expedited RCU grace period elapsed during a normal RCU grace period. If so, the normal RCU grace period is ended. If not, the normal RCU grace period processing is continued. Expedited RCU grace periods may be implemented by expedited RCU grace period processing that periodically awakens a kernel thread that implements the normal RCU grace period processing. The expedited RCU grace period processing may conditionally throttle wakeups to the kernel thread based on CPU utilization.

METHOD AND APPARATUS FOR AWAKENING ELECTRONIC DEVICE

A method and an apparatus for awakening an electronic device are provided. The method includes: receiving a user instruction for awakening an electronic device from its hibernation state and determining an intermediate device. The intermediate device is a device running in a normal operation mode and accessing a same target local area network as the electronic device. The method further includes: sending an awakening instruction to the intermediate device, such that the intermediate device broadcasts in the target local area network an awakening message for awakening the electronic device. 1. A method for awakening an electronic device , comprising:receiving a user instruction for awakening an electronic device from its hibernation state;determining an intermediate device, the intermediate device being a device running in a normal operation mode and accessing a same target local area network as the electronic device; andsending an awakening instruction to the intermediate device, such that the intermediate device broadcasts in the target local area network an awakening message for awakening the electronic device.2. The method according to claim 1 , wherein the user instruction is received when a user selects an awakening button for awakening the electronic device.3. The method according to claim 2 , wherein the awakening button is a virtual button for controlling an interface of the electronic device.4. The method according to claim 1 , wherein the user instruction is received when a user touches an icon for awakening the electronic device.5. The method according to claim 4 , wherein the icon is a virtual slider icon for controlling an interface of the electronic device.6. The method according to claim 1 , wherein determining the intermediate device comprises:determining the target local area network accessed by the electronic device according to a preset correspondence relationship between a local area network and at least one device accessing the local area ...

Method for Managing Sleep Mode at a Data Storage Device and System Therefor

A method includes issuing a suspend command to a data storage device at an information handling system. In response to receiving the suspend command, the data storage device generates a one-time password that is stored at the data storage device. The one-time password is provided to a process executing at the information handling system that stores the one-time password at a memory device at the information handling system. Operation of the data storage device is transitioned to an energy saving state. 1. A method comprising:issuing a suspend command to a data storage device at an information handling system;generating a one-time password at the data storage device;storing the one-time password at the data storage device;providing the one-time password to a process executing at the information handling system;storing the provided one-time password at a memory device at the information handling system; andtransitioning operation of the data storage device to an energy saving state.2. The method of claim 1 , further comprising:issuing a resume command to the data storage device, the resume command including the one-time password stored at the memory device; invalidating the one-time password stored at the data storage device; and', 'transitioning operation of the data storage device from the energy saving state to a normal operating state; and, 'in response to successfully authenticating the one-time password at the data storage devicein response to unsuccessfully authenticating the one-time password at the data storage device, denying access to data stored at the data storage device.3. The method of claim 2 , wherein the successful authenticating comprises determining that the one-time password accompanying the resume command matches the one-time password stored at the data storage device.4. The method of claim 2 , wherein the unsuccessful authenticating comprises determining that the one-time password accompanying the resume command does not match the one-time ...

HYPERVISOR HIBERNATION

Upon receiving a request to hibernate a hypervisor of a virtualization system running on a first computer, acts are carried out to capture a state of the hypervisor, where the state of the hypervisor comprises hypervisor logical resource parameters and an execution state of the hypervisor. After hibernating the hypervisor by quiescing the hypervisor and storing the state of the hypervisor into a data structure, the data structure is moved to a different location. At a later moment in time, the data structure is loaded onto a second computing machine and restored. The restore operation restores the hypervisor and all of its state, including all of the virtual machines of the hypervisor as well as all of the virtual disks and other virtual devices of the virtual machines. Differences between the first computing machine and the second computing machine are reconciled before execution of the hypervisor on the second machine. 1. A non-transitory computer readable medium having stored thereon a sequence of instructions which , when stored in memory and executed by a processor cause the processor to perform acts for hibernating a virtualization system the acts comprising:receiving a request to hibernate a hypervisor of the virtualization system running on a computer;capturing a state of the hypervisor, the state of the hypervisor comprising at least a first value of a hypervisor logical resource parameter and a second value of an execution state of the hypervisor; andhibernating the hypervisor by quiescing the hypervisor and storing the state of the hypervisor.2. The non-transitory computer readable medium of claim 1 , further comprising instructions which claim 1 , when stored in memory and executed by the processor cause the processor to perform further acts of moving the state of the hypervisor to a different computing platform.3. The non-transitory computer readable medium of claim 1 , further comprising instructions which claim 1 , when stored in memory and executed ...

Multi-core synchronization mechanism with interrupts on sync condition

A microprocessor includes a plurality of processing cores, each comprising a respective interrupt request input and a control unit configured to receive a respective synchronization request from each of the plurality of processing cores. The control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores.

Computer system and data recovery method thereof

A computer system and a data recovery method are provided. The computer system includes an embedded controller (EC). The data recovery method includes following steps. When the computer system stores data into the EC through a basic input/output system (BIOS), the data is backed up into a non-volatile random access memory (NVRAM) by the BIOS. The EC enters a power-off mode. The data is obtained from the NVRAM and is stored back to the EC after the EC leaves the power-off mode. Accordingly, the EC recovers from the power-off mode.

ADDING CYCLE NOISE TO ENCLAVED EXECUTION ENVIRONMENT

A method comprises receiving an instruction to resume operations of an enclave in a cloud computing environment and generating a pseud-random time delay before resuming operations of the enclave in the cloud computing environment. 1. A computer-implemented method , comprising:receiving an instruction to resume operations of an enclave in a cloud computing environment; andgenerating a pseudo-random time delay before resuming operations of the enclave in the cloud computing environment.2. The method of claim 1 , further comprising:appending a pseudo-random number of no-operation clock cycles to the instruction to resume operations.3. The method of claim 2 , wherein the pseudo-random number is chosen randomly from an arbitrary distribution.4. The method of claim 3 , wherein the number of no-operation clock cycles falls between a lower bound and an upper bound.5. The method of claim 4 , wherein the upper bound is an integer value fixed by a hardware element.6. The method of claim 4 , wherein the upper bound is an integer value which may be configured as a parameter.7. The method of claim 6 , wherein the upper bound is configured to vary in response to one or more operating conditions of the enclave in the cloud computing environment.8. An apparatus comprising:a processor; and{'claim-text': ['receive an instruction to resume operations of an enclave in a cloud computing environment; and', 'generate a pseud-random time delay before resuming operations of the enclave in the cloud computing environment.'], '#text': 'a computer readable memory comprising instructions which, when executed by the processor, cause the processor to:'}9. The apparatus of claim 8 , comprising instructions which claim 8 , when executed by the processor claim 8 , cause the processor to:append a pseudo-random number of no-operation clock cycles to the instruction to resume operations.10. The apparatus of claim 9 , wherein the pseudo-random number is chosen randomly from an arbitrary distribution.11. ...

COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface. 121-. (canceled)22. An apparatus , comprising:a memory power node; anda computer platform having firmware including Advanced Configuration and Power Interface (ACPI) components to build a table for an ACPI interface,wherein the table is to store a flag which is to indicate whether the memory power node is to be power managed.23. The apparatus of claim 22 , wherein the memory power node is a first memory power node claim 22 , wherein the table is a first table claim 22 , wherein the flag is a first flag claim 22 , and wherein the apparatus comprises:a second memory power node,wherein the ACPI components is to build a second table for the ACPI interface,wherein the first flag of the first table is to indicate that the first memory power node is to be power managed;wherein the second table is to store a second flag to indicate that the second memory power node is to be not power managed; andwherein the apparatus comprises a power management logic that is to: selectively cause the first memory power node to transition to a low power state, refrain from attempting to cause the second memory power node to transition to the low power state.24. The apparatus of claim 22 , wherein the memory power node is a first memory power node claim 22 , wherein the table is a first table claim 22 , wherein the flag is a first flag claim 22 , and wherein the apparatus comprises:a second memory power node,wherein the ACPI components are to build a second table for the ACPI interface,wherein the first flag of the first table is to indicate that the first memory power node is to be power managed;wherein the second table is to store a second flag to indicate that the second memory power node is to be not ...

SYSTEMS, METHODS AND DEVICES FOR WORK PLACEMENT ON PROCESSOR CORES

Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state). 1. A computer-readable storage medium that stores instructions for execution by a processing resource to perform operations of a power control unit within a processor , the operations , when executed by the processing resource , to perform a method , the method comprising:report fewer processing cores to an operating system than are present within the processor;assign a first identifier to a first processing core within the processor and a second identifier to a second processing core within the processor;detect a migration trigger that indicates detection of an instruction that would use a broken arithmetic unit on the first core;determine to sequester the first processing core from use by the operating system and migrate a thread from the first processing core to the second processing core;transmit a sleep transition message to the first processing core and the second processing core, the message requesting a transition to a low-power state, the low-power state causing the first processing core to save the first context in the first processor context storage;copy the first context from the ...