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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 5685. Отображено 100.
12-01-2012 дата публикации

Digital-to-analog converter (dac) calibration system

Номер: US20120007757A1
Автор: Munkyo Seo, Myung-Jun Choe
Принадлежит: Teledyne Scientific and Imaging LLC

The present invention relates generally to a digital-to-analog converter (DAC) calibration. The present invention may be implemented by a DAC calibration system including a first current source, a first switch coupled to the first current source, a second current source, a second switch coupled to the second current source, an output node coupled to the first switch and the second switch, a first calibration module coupled to the output node, an average current measurement module coupled to the first calibration module, and a second calibration module coupled to the average current measurement module.

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Номер записи: 1
19-01-2012 дата публикации

Programmable linearity correction circuit for digital-to- analog converter

Номер: US20120013492A1
Автор: Michael Coln, Roderick McLachlan
Принадлежит: Analog Devices Inc

The invention provides a systematic error correction network coupled to a converter. The converter may display a systematic non-linearity error, and the systematic error correction network shapes a correction transform function that acts like counter distortion function for the non-linearity error. The systematic error correction network then scales the correction transform function according to a reference variable, where the magnitude of non-linearity error is related to the reference variable. The scaled correction transform function is then applied to the converter path in order to generate a corrected analog output signal.

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Номер записи: 2
09-02-2012 дата публикации

Digital-to-analog converter with code independent output capacitance

Номер: US20120032829A1
Автор: Paul Talmage Watkins, Ryan James Kier, Yusuf Aminul Haque
Принадлежит: SiFlare Inc

A Digital-to-Analog Converter (DAC) with code independent output capacitance includes circuitry configured to convert a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal. A method for converting a digital signal to an analog signal with a DAC includes converting a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal.

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Номер записи: 3
08-03-2012 дата публикации

Digital/analog converter

Номер: US20120056768A1
Автор: Shigeo Imai
Принадлежит: Toshiba Corp

A digital/analog converter converts an input digital signal to an analog signal and outputs the analog signal. The digital/analog converter has first and second transistors that are complementarily switched by a first digital signal included in the digital signal. The digital/analog converter has a first current source having a first end connected to a first potential, and having a second end connected to a first end of the first transistor and a first end of the second transistor, to output a constant current. The digital/analog converter has a third transistor having a first end connected to a second end of the first transistor. The digital/analog converter has a fourth transistor having a first end connected to a second end of the second transistor. The digital/analog converter has a first output terminal connected to a second end of the third transistor to output a first analog signal. The digital/analog converter has a control circuit that controls gate voltages of the third transistor and the fourth transistor according to the digital signal such that the third transistor and the fourth transistor operate in a saturation region.

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Номер записи: 4
22-03-2012 дата публикации

Fast data weighted average circuit and method

Номер: US20120068865A1
Автор: Gabor C. Temes, Jeongseok Chae
Принадлежит: Asahi Kasei Microdevices Corp

A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.

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Номер записи: 5
21-06-2012 дата публикации

Apparatus of driving light emitting diode using erasable programmable logic device chip

Номер: US20120153862A1
Автор: Chang Sub Lee, Jin Ho Park, Ki Young Kim, Min Su Kim, Sang Gon Lee, Sang Hun Lee, Te O Jung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is an apparatus that drives a light emitting device using an erasable programmable logic device (EPLD) chip. The apparatus may include the light emitting device, and a driving unit to use the EPLD chip storing programming information corresponding to the light emitting device, and to drive the light emitting device based on the stored programming information. The EPLD chip may receive the programming information inputted from an external terminal, and may store the programming information in a predetermined storage space.

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Номер записи: 6
12-07-2012 дата публикации

Calibration Circuit and Method for Calibrating Capacitive Compensation in Digital-to-Analog Converters

Номер: US20120176258A1
Автор: Franz Kuttner
Принадлежит: INFINEON TECHNOLOGIES AG

A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

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Номер записи: 7
12-07-2012 дата публикации

Semiconductor integrated device and operation method thereof

Номер: US20120176261A1
Автор: Takuji Aso, Toshiyuki Ishioka
Принадлежит: Renesas Electronics Corp

In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.

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Номер записи: 8
19-07-2012 дата публикации

Distortion and aliasing reduction for digital to analog conversion

Номер: US20120183110A1
Автор: Bruce J. Currivan, Ramon A. Gomez, Thomas J. Kolze
Принадлежит: Broadcom Corp

Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion.

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Номер записи: 9
02-08-2012 дата публикации

Device and method for driving digital-to-analog converter

Номер: US20120194373A1
Автор: Gunter Steinbach
Принадлежит: AGILENT TECHNOLOGIES INC

A device for driving a switch in a digital-to-analog converter (DAC) includes first and second latches, and a logic gate. The first latch is configured to store a digital input data signal according to a clock signal, and to output a first latch signal corresponding to the stored digital input data signal. The second latch is configured to store the first latch signal output by the first latch according to a logical inverse of the clock signal, and to output a second latch signal corresponding to the stored first latch signal. The logic gate is configured to perform an OR logic operation on the first latch signal and the second latch signal, the logic gate outputting a drive signal for driving a switch in the DAC connected to a current source.

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Номер записи: 10
16-08-2012 дата публикации

Minimum differential non-linearity trim DAC

Номер: US20120206283A1
Автор: Hans Martin Von Staudt
Принадлежит: Dialog Semiconductor GmbH

A trim DAC wherein the digital input bits to the trim DAC are controlled by a state machine to produce an analog output that is within a least significant bit of the digital input bits. An undersize factor between digital input bits is used to assist in finding a trim solution for major transitions of the digital input bits. Trim solutions are stored in a nonvolatile memory associated with the state machine to be used in creating an accurate analog output.

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Номер записи: 11
30-08-2012 дата публикации

Transmission circuit, ultrasonic probe and ultrasonic image display apparatus

Номер: US20120218135A1
Автор: Bruno Haider, Krishnakumar Sundaresan, Naresh Kesavan Rao, Shinichi Amemiya, Thomas Halvorsrod
Принадлежит: Individual

A transmission circuit for use with an ultrasonic probe including an ultrasonic transducer is provided. The transmission circuit includes a high voltage current DAC configured to output a drive current of an ultrasonic transducer to transmit and receive ultrasound, and a waveform generator configured to output a control signal from the high voltage current DAC to the high voltage current DAC with a predetermined timing. The control signal configured to output the drive current with a desired magnitude.

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Номер записи: 12
13-09-2012 дата публикации

Analog to digital converter circuit

Номер: US20120229313A1
Автор: Chi-Hang CHAN, Franco Maloberti, He-Gong Wei, Li Ding, Rui Paulo da Silva Martins, Sai-Weng Sin, Seng-Pan U, U-Fat CHIO, Yan Zhu
Принадлежит: UNIVERSITY OF MACAU

The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design

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Номер записи: 13
04-10-2012 дата публикации

Pipelined adc having error correction

Номер: US20120249348A1
Автор: Eric John SIRAGUSA
Принадлежит: Analog Devices Inc

A pipeline stage of a pipelined analog-to-digital converter (ADC) circuit can include an ADC to convert an analog input to a digital output, a first plurality of digital-to-analog converters (DACs) sufficient in number to produce an analog output corresponding to the digital output, and a second plurality of DACs configured to have their output added into the analog output, where a succeeding pipeline portion can convert the amplified analog residue to at least one second digital output and a digitized residue. A mapping circuit can selectively exchange inputs between a selected one of the first plurality of DACs and one of the second plurality of DACs, and a calibration signal circuit can provide first and second calibration signals to inputs of the selected one of the first plurality of DACs and another of the second plurality of DACs. The calibration signals can be correlated to each other, but uncorrelated to the analog input and digital output of the first pipeline stage, and have unequal effects on the amplified analog residue or the digitized residue. A correction circuit can correct the digital output of the pipeline stage for circuit path errors in circuit paths including the first plurality and second plurality of DACs based on the results of a correlation between the calibration signals and the second digital output or digitized residue. The effects, on the amplified analog residue or the digitized residue, of the first and second calibration signals, upon travelling through the selected one of the first plurality of DACs and the other of the second plurality of DACs, can at least partially offset each other.

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Номер записи: 14
25-10-2012 дата публикации

Analog-digital converter and signal processing system

Номер: US20120268302A1
Автор: Kouhei Kudou, Shinichirou Etou, Yasuhide Shimizu, Yukitoshi Yamashita
Принадлежит: Sony Corp

An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.

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Номер записи: 15
10-01-2013 дата публикации

Biological analog-to-digital and digital-to-analog converters

Номер: US20130009799A1
Автор: James J. Collins, Timothy Kuan-Ta Lu
Принадлежит: Boston University, Massachusetts Institute of Technology

Described herein are novel biological converter switches that utilize modular components, such as genetic toggle switches and single invertase memory modules (SIMMs), for converting analog inputs to digital outputs, and digital inputs to analog outputs, in cells and cellular systems. Flexibility in these biological converter switches is provided by combining individual modular components, i.e., SIMMs and genetic toggle switches, together. These biological converter switches can be combined in a variety of network topologies to create circuits that act, for example, as switchboards, and regulate the production of an output product(s) based on the combination and nature of input signals received.

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Номер записи: 16
24-01-2013 дата публикации

Circuitry and method for digital to analog current signal conversion with phase interpolation

Номер: US20130021186A1
Автор: Arlo J. Aude, Steven E. Finn
Принадлежит: National Semiconductor Corp

Circuitry and method for digital-to-analog current signal conversion with phase interpolation. For an n-bit digital-to-analog converter (DAC), the number 2 n control bits normally required can be reduced to 2 (n-1) by jointly controlling pairs of the current sources with one of the 2 (n-1) current control bits and inverses of two other ones of the 2 (n-1) current control bits.

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Номер записи: 17
31-01-2013 дата публикации

Modified Dynamic Element Matching For Reduced Latency In A Pipeline Analog To Digital Converter

Номер: US20130027231A1
Автор: Andrea Panigada, Daniel MEACHAM, Jorge GRILO
Принадлежит: Microchip Technology Inc

A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

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Номер записи: 18
31-01-2013 дата публикации

Analog digital converter

Номер: US20130027233A1
Автор: Takeshi Nozaki
Принадлежит: Fujitsu Semiconductor Ltd

An ADC which samples an analog input signal at a sampling frequency and converts the analog input signal to a digital output signal, has N analog digital converter (ADC) channels which convert the analog input signal into the digital output signal by time interleaving, a channel synthesizer which synthesizes channel digital signals output respectively by the ADC channels to generate the digital output signal, an adaptive filter provided at at least one output of the ADC channels, and a correction circuit which generates a coefficient of the adaptive filter in accordance with the digital output signal. The correction circuit calculates a DC component of an image signal component, from among an analog input signal component and the image signal component corresponding to error, both being included in the digital output signal, and calculates the coefficient such that the DC component is suppressed on the basis of the DC component.

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Номер записи: 19
07-03-2013 дата публикации

Digital-to-analog converter

Номер: US20130057420A1
Автор: Hideki Oku
Принадлежит: Fujitsu Ltd

There is provided a digital-to-analog converter including: a mirror circuit including a first transistor to copy a reference current at a predetermined mirror ratio, and a second transistor cascade coupled with the first transistor; and an analog switch coupled with a gate of the second transistor, the analog switch being configured to be controlled, by a digital signal input from outside, so as to be turned on or off.

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Номер записи: 20
28-03-2013 дата публикации

Analogue to digital converter and signal processing system

Номер: US20130076544A1
Автор: Junya Matsuno, Masanori Furuta, Naoya Waki, Takafumi Yamaji
Принадлежит: Toshiba Corp

According to one embodiment, an analogue to digital converter converts an analogue input signal to a digital output signal. The converter includes an analogue to digital converting unit, a multiplexer, a pseudo-alias signal generator, a gain controller, and an alias signal compensator. The analogue to digital converting unit converts the analogue input signal to a plurality of digital signals. The multiplexer sequentially selects one of the digital signals and outputs the selected digital signal as a multiplexer output. The pseudo-alias signal generator generates a plurality of pseudo-alias signals from the digital signals. The pseudo-alias signal simulates an alias signal component in the multiplexer output. The gain controller generates a plurality of gain control signals by using the pseudo-alias signals. The gain control signal controls gain of the digital output signal. The alias signal compensator compensates the alias signal component by using the gain control signals.

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Номер записи: 21
06-06-2013 дата публикации

ANALOG-TO-DIGITAL CONVERSION STAGE AND PHASE SYNCHRONIZATION METHOD FOR DIGITIZING TWO OR MORE ANALOG SIGNALS

Номер: US20130141262A1
Автор: Hays Paul J., McAnally Craig B.
Принадлежит: Micro Motion, Inc.

An analog-to-digital conversion stage () includes three or more ADCs () that receive two or more analog signals, generate a first digitized signal from a first analog signal, generate at least a second digitized signal from at least a second analog signal to create two or more digitized signals, and generate one or more redundant digitized signals from the two or more analog signals. The one or more redundant digitized signals are generated substantially in parallel with the two or more digitized signals. A processing device () generates a phase drift value from a phase difference between a redundant digitized signal of the one or more redundant digitized signals and a corresponding digitized signal of the two or more digitized signals and compensates the corresponding digitized signal using the one or more phase drift values. 1300300. An analog-to-digital conversion (ADC) stage () for digitizing two or more analog signals , the ADC stage () comprising:{'b': 303', '305', '307, 'three or more ADCs (, , ) configured to receive the two or more analog signals, generate a first digitized signal from a first analog signal of the two or more analog signals, generate at least a second digitized signal from at least a second analog signal of the two or more analog signals to create two or more digitized signals, and generate one or more redundant digitized signals from the two or more analog signals, with the one or more redundant digitized signals being generated substantially in parallel with the two or more digitized signals;'}{'b': 330', '303', '305', '307', '330, 'a processing device () coupled to the three or more ADCs (, , ), with the processing device () configured to generate a phase drift value from a phase difference between a redundant digitized signal of the one or more redundant digitized signals and a corresponding digitized signal of the two or more digitized signals and compensate the corresponding digitized signal using the one or more phase drift values.'} ...

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Номер записи: 22
27-06-2013 дата публикации

High-speed successive-approximation-register analog-to-digital converter and method thereof

Номер: US20130162454A1
Автор: Chia-Liang Lin
Принадлежит: Realtek Semiconductor Corp

In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data.

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Номер записи: 23
11-07-2013 дата публикации

SIGNAL CONVERTING APPARATUS OF POWER METERING SYSTEM, POWER METERING SYSTEM AND METHOD FOR SIGNAL-CONVERTING IN POWER METERING SYSTEM

Номер: US20130176016A1
Автор: KANG Shin Jae
Принадлежит:

The present invention relates to a signal converting apparatus of a power metering system, a power metering system and a method for signal-converting in a power metering system. In accordance with one embodiment of the present invention, there is proposed to a signal converting apparatus of a power metering system including a frequency shift unit for shifting a frequency(s) of at least one signal of sensed current and voltage signals by a shift frequency(s) so that the current and voltage signals have different frequency bandwidths, a signal coupling unit for coupling the current and voltage signals having different frequency bandwidths into one signal and an analog-digital convert unit for converting an analog signal coupled as said one signal into a digital signal(s). And also, a power metering system including the same and a method for converting a signal of the power metering system are proposed. 1. A signal converting apparatus of a power metering system comprising: a signal coupling unit for coupling the current and voltage signals having different frequency bandwidths into one signal; and', 'an analog-digital convert unit for converting an analog signal coupled as said one signal into a digital signal(s)., 'a frequency shift unit for shifting a frequency(s) of at least one signal of sensed current and voltage signals by a shift frequency(s) so that the current and voltage signals have different frequency bandwidths;'}2. The signal converting apparatus of a power metering system according to claim 1 , wherein the frequency shift unit shifts each of the sensed current and voltage signals by each of different shift frequencies.3. The signal converting apparatus of a power metering system according to claim 1 , wherein the current and voltage signals are 3-phase signals.4. The signal converting apparatus of a power metering system according to claim 1 , wherein the frequency shift unit consists of frequency synthesizers to generate frequency-shifted intermediate ...

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Номер записи: 24
11-07-2013 дата публикации

SYSTEM AND METHOD OF ANALOG-TO-DIGITAL CONVERTERS

Номер: US20130176152A1
Автор: ALI Ahmed Mohamed Abdelatty
Принадлежит: ANALOG DEVICES, INC.

An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system. 115-. (canceled)16. An analog-to-digital converter (ADC) system for converting an input , comprising:a pipeline including successively-cascaded signal converter stages, each signal converter stage including an analog-to-digital converter (ADC) for converting a portion of the input into digital codes and a multiplying digital-to-analog converter (MDAC) for outputting a residual portion of the input to a following signal converter stage, the MDAC including an amplifier having a summing node and operating alternatively in a first circuit configuration and a second circuit configuration, for a present signal converter stage, a summing node error is capacitively extracted under the first configuration of the MDAC of the present signal converter stage,', 'the extracted summing node error is amplified by the amplifier in a succeeding second configuration of the MDAC of the present signal converter stage to output an amplified error to a following signal converter stage,', 'the amplified error is amplified in a second configuration of following signal converter stages, and', 'an error estimator is coupled to the pipeline to receive the amplified error and to adjust a gain of the amplifier based on the amplified error., 'wherein17. The ADC system of claim 16 , wherein the amplified error is one of an analog error and a digital error.18. The ADC system of claim 16 , further comprising:a code aligner/corrector that temporally aligns and corrects the ...

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Номер записи: 25
25-07-2013 дата публикации

GAIN AND DITHER CAPACITOR CALIBRATION IN PIPELINE ANALOG-TO-DIGITAL CONVERTER STAGES

Номер: US20130187801A1
Автор: de Figueiredo Pedro Miguel Ferreira, dos Santos Fachada Carlos Pedro, Tordo Minderico Gonçalo Manuel
Принадлежит: Synopsys, Inc.

A switching scheme is used during a calibration mode for determining calibration coefficients of each calibrated stage of a pipeline analog-to-digital converter (ADC). A calibrated stage of the pipeline ADC includes an amplifier for amplifying a residue voltage of the stage and a sampling capacitor comprising a plurality of sub-capacitors. The plurality of sub-capacitors have a first terminal connected to an input of amplifier and a second terminal connected to one or more switches that selectively couple the second terminal to the input terminal of the stage, a first reference voltage or a second reference voltage lower than the first reference voltage. During foreground calibration, a number of measurements are taken at an output of the amplifier to determine the calibration coefficient of the calibrated stage. 1. A pipeline analog-to-digital converter comprising: an amplifier generating an output representing an amplified difference between a first voltage at an input of the amplifier and a second voltage at another input of the amplifier; and', 'a sampling capacitor comprising a plurality of sub-capacitors, each of the plurality of sub-capacitors having a first terminal coupled to the input of the amplifier and a second terminal selectively coupled to a first reference voltage or a second reference voltage higher than the first reference voltage in a calibration mode or an input voltage of each of the plurality of stages in an operational mode subsequent to the calibration mode; and, 'a plurality of calibrated stages, each of the plurality of calibrated stages comprising receive a plurality of measurements of the output of the amplifier performed in calibration mode, during each of the plurality of measurements, the second terminal of at least one of the plurality of sub-capacitors coupled to the first reference voltage;', 'determine a calibration coefficient for the calibrated stage based on the received plurality of measurements; and', 'compensate, in ...

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Номер записи: 26
22-08-2013 дата публикации

A/D Converter and Method for Calibrating the Same

Номер: US20130214946A1
Автор: Craninckx Jan, IRIGUCHI Masao, Verbruggen Bob
Принадлежит:

An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analogue non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal. 1. An analogue-to-digital converter for converting an input voltage signal into a digital output signal representing the input voltage signal , the analogue-to-digital converter , comprising:sampling means for sampling the input voltage signal;one or more comparators arranged for receiving the sampled input voltage signal;a digital-to-analogue converter (DAC) including circuitry adapted for generating a calibration signal and a search signal approximating the input voltage signal, the calibration signal and search signal to be applied to a comparator of the one or more comparators;a search logic block arranged for receiving a comparator output signal from the one or more comparators, for providing input to the DAC for generating the search signal, and for producing a digital output signal;a calibration logic block adapted for producing a control signal to control the circuitry of the DAC and including processing means for observing the digital output signal, for comparing the digital output signal with a desired output, and for compensating ...

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Номер записи: 27
22-08-2013 дата публикации

Interleaved analog to digital converter with reduced number of multipliers for digital equalization

Номер: US20130214958A1
Автор: Anatoli B. Stein, Semen P. Volfbeyn, Valeriy Serebryanskiy
Принадлежит: Guzik Technical Enterprises Inc

A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.

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Номер записи: 28
29-08-2013 дата публикации

Tree structured supply and bias distribution layout

Номер: US20130222167A1
Автор: Mansour Keramat, Yuan-Ju Chao
Принадлежит: Integrated Device Technology Inc

Systems and methods are disclosed for performing data conversion by matching current sources using a thin oxide device; and minimizing voltage stress on the thin oxide device during operation or power down.

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Номер записи: 29
29-08-2013 дата публикации

D/A CONVERTER

Номер: US20130222169A1
Автор: SUZUKI Hisao
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A digital-to-analog (D/A) converter includes D/A conversion circuits and an amplifier circuit coupled between the D/A conversion circuits. Each D/A conversion circuit includes an R-2R ladder type resistor network, first transistors coupled between the resistor network and a first wiring at a first voltage level, and second transistors coupled between the resistor network and a second wiring at a second voltage level. The sizes of the first transistors are set at a ratio of powers of 2. The sizes of second transistors are set at a ratio of powers of 2. The second transistors are respectively turned on and off complementarily to the first transistors according to the digital input signal. 1. A digital-to-analog (D/A) converter generating an analog signal corresponding to a digital input signal , the D/A converter comprising:a plurality of D/A conversion circuits; andan amplifier circuit coupled between the plurality of D/A conversion circuits in a negative feedback manner;wherein:the plurality of D/A conversion circuits include a first-stage D/A conversion circuit configured to receive a multi-bit digital input signal including a least significant bit of the digital input signal, and another D/A conversion circuit configured to receive a higher-order bit than a bit of a digital input signal received by a previous-stage D/A conversion circuit thereof, and an R-2R ladder type resistor network corresponding to the digital input signal received by the D/A conversion circuit,', 'a plurality of first transistors which are coupled between the resistor network and a first wiring at a first voltage level and the sizes of which are set at a ratio of powers of 2, and', 'a plurality of second transistors which are coupled between the resistor network and a second wiring at a second voltage level, the sizes of which are set at a ratio of powers of 2 and which are respectively turned on and off complementarily to the plurality of first transistors according to the digital input ...

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Номер записи: 30
26-09-2013 дата публикации

SCHEME FOR BALANCING SKEW BETWEEN LANES OF HIGH-SPEED SERIAL DIGITAL INTERFACE

Номер: US20130249719A1
Автор: Ryan Ivan R.
Принадлежит:

A device that supports communication over parallel serial lanes may include an analog circuit domain, a digital circuit domain, a buffer between the analog domain and the digital domain, and an alignment circuit. The buffer may receive data from the digital domain according to a write clock and send out the received data to the analog domain according to a read clock. The alignment circuit may generate control signals to initiate reading from the buffer when the read clock and write clocks are aligned. In one embodiment, the device may be an analog-to-digital converter (ADC) integrated circuit (IC) chip and the buffer may be a FIFO. 1. A method of aligning a pair of clock signals whose frequencies differ by a factor M/N , where M and N are integers , comprising:dividing a first clock signal by a predetermined factor to generate a divided down clock,on each cycle of the second clock, determine whether a transition of the divided down clock has occurred,when a transition of the divided down clock is detected, reading the divided down clock on a predetermined transition of the second clock,determining whether another transition of the divided down clock has occurred on the predetermined transition, andif not, repeating the reading and determining until a transition of the divided down clock is detected,wherein, the first and second clock signals are determined to be aligned when a transition of the divided down clock is detected on the predetermined transition of the first clock.2. The method of claim 1 , wherein the first clock signal is a write signal to a buffer memory and the second clock signal is a read signal from the buffer memory.3. The method of claim 1 , wherein the first and second clocks both are derived within an integrated circuit from a common clock source provided to the integrated circuit.4. The method of claim 1 , further comprising performing a second instance of the method in an integrated circuit separate from an integrated circuit which a first ...

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Номер записи: 31
26-09-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Номер: US20130249720A1
Автор: Kasahara Masumi, KIMURA Keisuke, MATSUURA Tatsuji, NAKANE Hideo, Takashi Oshima, Ujiie Ryuichi
Принадлежит: RENESAS ELECTRONICS CORPORATION

A semiconductor integrated circuit device having A/D converters for converting, by means of digital correction processing, analog input signals into digital signals is reduced in area. The semiconductor integrated circuit device has a first A/D converter and a second A/D converter. In a first mode, a first test signal is inputted to both the first and second A/D converters, and a first correction coefficient for the first A/D converter and a second correction coefficient for the second A/D converter are calculated. In a second mode, the first A/D converter converts a first analog signal into a first digital signal by subjecting the first analog signal to a first digital correction processing and the second A/D converter converts a second analog signal into a second digital signal by subjecting the second analog signal to a second digital correction processing. 1. A semiconductor integrated circuit device comprising:a first analog circuit which outputs a first analog signal and a second analog signal differing in phase from the first analog signal;a first A/D converter which receives the first analog signal from the first analog circuit and outputs a first digital signal;a second A/D converter which receives the second analog signal from the first analog circuit and outputs a second digital signal;a digital processing circuit which receives the first and second digital signals from the first and second A/D converters and digitally processes the first and second digital signals received;a mode setting information storing circuit for storing mode information; anda correction coefficient storing circuit which stores correction coefficients for the first and second A/D converters,wherein, when a first mode is set in the mode setting information storing circuit, a first correction coefficient for a first digital correction processing and a second correction coefficient for a second digital correction processing are calculated by having a first test signal inputted to both ...

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Номер записи: 32
26-09-2013 дата публикации

INPUT CONVERTER FOR A HEARING AID AND SIGNAL CONVERSION METHOD

Номер: US20130249726A1
Автор: KNUDSEN Niels Ole
Принадлежит: WIDEX A/S

In order to minimize noise and current consumption in a hearing aid, an input converter including a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage includes an amplifier (Q) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (C, C, C, C). The invention further provides a method of converting an analog signal. 1. A sigma-delta converter converting an analog signal into a digital signal , and comprising:an input transformer receiving an input voltage and outputting a transformed voltage to a summation point;an integrator integrating a voltage present in the summation point;a comparator comparing an output from the integrator with a predetermined threshold and outputting a logical level in accordance with the comparison; anda feedback loop coupling a feedback signal back to the summation point;wherein said input transformer includes a switchable capacitor configuration.2. The converter according to claim 1 , wherein the input transformer includes at least two capacitors claim 1 , a plurality of switching elements and control logic claim 1 , and wherein the control logic switches the input transformer between a first and a second phase of operation.3. The converter according to claim 2 , wherein said plurality of switching elements and control logic is configured to arrange said ...

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Номер записи: 33
17-10-2013 дата публикации

RESISTOR-BASED SIGMA-DELTA DAC

Номер: US20130271305A1
Автор: Kim Hyung Seok, Lakdawala Hasnain, Li Yee W., Ravi Ashoke
Принадлежит:

An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal. 1. A digital-to-analog converter , comprising an inverter-driven resistor-ladder network comprising a resistor for each bit signal of a multi-bit input signal , the multi-bit input signal comprising a plurality of bits , each resistor of the resistor-ladder network comprising an input end and an output end , the input end of each resistor being coupled to a corresponding bit signal of the multi-bit input signal , and the output end of each resistor being coupled to an output node of the resistor-ladder network , the digital-to-analog converter to generate an output voltage at the output node being based on the multi-bit input signal.2. The digital-to-analog converter according to claim 1 , wherein resistance values of the resistors of the resistor-ladder network are related by a binary weighting.3. The digital-to-analog converter according to claim 1 , wherein resistance values of the resistors of the resistor-ladder network are substantially equal.4. The digital-to-analog converter according to claim 1 , wherein the multi-bit input signal is a ...

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Номер записи: 34
31-10-2013 дата публикации

Power system data acquisition systems

Номер: US20130285716A1
Автор: Richard T. Dickens
Принадлежит: Mehta Tech Inc

A system comprising an interface configured to condition a signal associated with a power system; a clock module configured to generate a synchronization signal; and a module coupled to the interface and configured to digitize the signal from the interface; filter the digitized signal; and generate a time-shifted, digitized signal in response to the filtering and the synchronization signal.

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Номер записи: 35
07-11-2013 дата публикации

SEGMENTED DIGITAL-TO-ANALOG CONVERTER HAVING WEIGHTED CURRENT SOURCES

Номер: US20130293405A1
Автор: Medina Sánchez-Castro Italo Carlos
Принадлежит: ANALOG DEVICES TECHNOLOGY

A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.

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Номер записи: 36
28-11-2013 дата публикации

Digital Correction Techniques for Data Converters

Номер: US20130314261A1
Автор: CURRIVAN Bruce, GOMEZ Ramon, He Lin, JAFFE Steven, Kolze Thomas, TAN Loke
Принадлежит: BROADCOM CORPORATION

A method and apparatus is disclosed to compensate for impairments within a data converter such that its output is a more accurate representation of its input. The data converter includes a main data converter, a reference data converter, and a correction module. The main data converter may be characterized as having the impairments. As a result, the output of the main data converter is not the most accurate representation of its input. The reference data converter is designed such that the impairments are not present. The correction module estimates the impairments present within the main data converter using its output and the reference data converter to generate corrections coefficients. The correction module adjusts the output of the main data converter using the corrections coefficients to improve the performance of the data converter. 1. (canceled)2. A composite analog-to-digital converter (ADC) for converting an analog input to a digital output , comprising:a main data converter configured to convert the analog input to provide main digital samples, the main data converter having an impairment;a reference data converter configured to convert the analog input to provide reference digital samples, the reference data converter not being impaired by the impairment; anda correction module configured to estimate the impairment based upon the reference digital samples and to adjust the main digital samples to compensate for the impairment to provide the digital output.3. The composite ADC of claim 2 , wherein the reference data converter has a second impairment that is different from the first impairment.4. The composite ADC of claim 2 , wherein the reference data converter is further configured to sample the analog input at a different sampling rate or resolution than at which the main data converter samples the analog input.5. The composite ADC of claim 4 , wherein the compensation module is further configured to align the main digital samples and the reference ...

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Номер записи: 37
28-11-2013 дата публикации

Digital-to-Analog-Converter with Resistor Ladder

Номер: US20130314263A1
Автор: Dix Gregory
Принадлежит: MICROCHIP TECHNOLOGY INCORPORATED

A digital-to analog-converter (DAC) has a MSB resistor ladder with a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential, a LSB resistor ladder with a plurality of series connected resistors, and a plurality of switching units for connecting one of the series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit has a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on. 1. A digital-to analog-converter (DAC) comprising:a MSB resistor ladder comprising a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential;a LSB resistor ladder comprising a plurality of series connected resistors; anda plurality of switching units for connecting one of said series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit comprises a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on.2. The digital-to analog-converter according to claim 1 , further comprising a decoder for controlling one of the switching units to connect an associated resistor of the MSB resistor ladder with the LSB resistor ladder and for selecting one of a plurality of tapping nodes of the LSB ...

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Номер записи: 38
05-12-2013 дата публикации

ANALOG-TO-DIGITAL CONVERTER AND ELECTRONIC APPARATUS

Номер: US20130321187A1
Автор: Chen Yanfei, Tsukamoto Sanroku
Принадлежит: FUJITSU LIMITED

An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level. 1. An analog-to-digital converter comprising:a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal;a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level; anda second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.2. The analog-to-digital converter as claimed in claim 1 , whereinthe sub-comparator includes:a first sub-comparator having a negative offset less than the quantization unit of the DA converting part with respect to the main-comparator; anda second sub-comparator having a positive offset less than the quantization unit of the DA converting part with respect to the ...

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Номер записи: 39
02-01-2014 дата публикации

Circuit and Method

Номер: US20140002287A1
Автор: Boos Zdravko, Klepser Bernd-Ulrich, Mayer Thomas, Scholz Markus
Принадлежит:

Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input. 126-. (canceled)27. A circuit , comprising:a digital-to-time converter comprising a high-frequency input configured to receive a high-frequency signal, a digital input configured to receive a first digital signal, and a high-frequency output configured to provide a chronologically delayed version of the high-frequency signal; andan oscillator arrangement configured to provide the high-frequency signal having a phase-locked loop configured to provide a frequency of the high-frequency signal; andwherein the digital-to-time converter is configured to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.28. The circuit according to claim 27 , wherein the oscillator arrangement is further configured to vary a phase of the high-frequency signal based on an additional digital signal.29. The circuit according to claim 27 , further comprising:a polar coordinate provider configured to provide a first phase signal that determines a phase modification or a phase of the delayed version of the high-frequency signal; andwherein the first phase signal includes the first digital signal or is the first digital signal.30. The circuit according to :wherein the polar coordinate provider is configured to provide the first phase signal in such a manner that it includes ...

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Номер записи: 40
02-01-2014 дата публикации

Method and Apparatus for Detecting the Presence of a Signal in a Frequency Band Using Non-Uniform Sampling

Номер: US20140003556A1
Автор: Ajay K. Luthra
Принадлежит: MOTOROLA MOBILITY LLC

A method and apparatus for detecting the presence of a signal in a frequency band using non-uniform sampling includes an analog to digital converter (ADC) ( 110 ) for sampling an analog input signal ( 105 ) to create discrete signal samples ( 115 ), an ADC exciter ( 120 ) for exciting the ADC to sample at non-uniform time periods, a digital filter ( 130 ) for converting the discrete signal samples into an energy versus frequency spectrum ( 300 ), and an energy comparator ( 140 ) coupled to an output of the digital filter. The energy comparator ( 140 ) detects the presence of any frequency bands exceeding an energy setpoint.

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Номер записи: 41
16-01-2014 дата публикации

System and Method for Analog to Digital (A/D) Conversion

Номер: US20140015699A1
Автор: Zhang Yuxing, Zhao Jian Hua
Принадлежит: STMicroelectronics R&D (Shanghai) Co. Ltd.

In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels. 1. An analog-to-digital (A/D) converter comprising:an amplifier;a capacitor array coupled to the amplifier, wherein first ends of capacitors of the capacitor array are coupled to an input of the amplifier;a switching array coupled to second ends of the capacitors of the capacitor array and to an input terminal of the A/D converter;a first sub-A/D coupled to an output of the amplifier; anda controller configured to cause the switching array to perform a plurality of successive approximation steps to track a signal at the input terminal of the A/D converter, wherein the controller is configured to compensate for a correctable residue error made by the first sub-A/D in one of the plurality of successive approximation steps by applying an opposite error detected by the first sub-A/D in a subsequent successive approximation step.2. The A/D converter of claim 1 , wherein the amplifier comprises an adjustable open-loop gain.3. The A/D converter of claim 2 , wherein the controller is further configured to decrease the open loop gain of the amplifier during the subsequent successive approximation step.4. The A/D converter of claim 1 , wherein the first sub-A/ ...

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Номер записи: 42
13-02-2014 дата публикации

Interpolative digital-to-analog converter

Номер: US20140043178A1
Автор: Chih-Kang Deng, Sung-Yau Yeh
Принадлежит: ILI Techonology Corp

An interpolative digital-to-analog (D/A) converter is adapted to convert a N-bit digital signal into an analog signal, where N is a positive integer greater than 1. The interpolative D/A converter includes a router unit that outputs first and second router voltages based on the first and second bits of the digital signal, and an interpolation unit that receives the first and second router voltages from the router unit, and that performs interpolation operation on the first and second router voltages according to the first bit of the digital signal, so as to generate the analog signal having a voltage magnitude ranging from the first router voltage to the second router voltage.

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Номер записи: 43
06-03-2014 дата публикации

Successive equalizer for analog-to-digital converter (adc) error correction

Номер: US20140062738A1
Автор: Binning Chen, Chun-Ying Chen, Jiangfeng Wu, Lin He, Ramon Gomez, Randall Perlow, Tianwei Li, Wei-Ta Shih, Wenbo Liu
Принадлежит: Broadcom Corp

Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.

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Номер записи: 44
06-03-2014 дата публикации

BUFFER OFFSET MODULATION

Номер: US20140062739A1
Автор: CHUANG MEI-CHEN, Hsu Ying-Chih, HUANG Jui-Cheng, Tai Chia Liang
Принадлежит: Taiwan Semiconductor Manufacturing Company Limited

One or more techniques for buffer offset modulation or buffer offset cancelling are provided herein. In an embodiment, an output for a sigma-delta analog digital converter (ADC) is provided using an output of a first chop-able buffer (FB) and an output of a second chop-able buffer (SB). For example, the output of the FB is associated with a first offset, the output of the SB is associated with a second offset, and the output of the ADC includes an ADC offset associated with the first offset and the second offset. In an embodiment, buffer offset modulation is provided by modulating the ADC offset using an offset rotation. In an example, the offset rotation is based at least in part on a reference clock and the output of the ADC. The buffer offset modulation mitigates the first offset or the second offset, where such offsets are generally undesired. 1. A method for buffer offset modulation , comprising:sending an output of a first chop-able buffer (FB) to a first input for a sigma-delta analog digital converter (ADC);sending an output of a second chop-able buffer (SB) to a second input for the ADC;determining an offset rotation for at least one of the FB or the SB based at least in part on at least one of an output of the ADC or a reference clock; andproviding a modulated ADC offset based at least in part on the output of the FB and the output of the SB, the modulated ADC offset associated with a first offset and a second offset, the output of the ADC comprising the modulated ADC offset.2. The method of claim 1 , the output of the FB comprising the first offset.3. The method of claim 1 , the output of the SB comprising the second offset.4. The method of claim 1 , comprising filtering the modulated ADC offset from the output of the ADC.5. The method of claim 1 , comprising:filtering the modulated ADC offset from the output of the ADC using a filter associated with a first frequency; anddetermining the offset rotation based at least in part on a reference clock ...

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Номер записи: 45
06-03-2014 дата публикации

ANALOG TO DIGITAL CONVERTER WITH NOISE REDUCING FEEDBACK PATH

Номер: US20140062740A1
Автор: Castello Rinaldo, Colonna Vittorio, Gandolfi Gabriele, Liscidini Antonio, Sosio Marco
Принадлежит: MARVELL WORLD TRADE LTD.

An analog to digital converter including a low pass filter element, a quantizer, and a digital to analog converter provide in a feedback path. The low pass filter element is configured to filter an analog input signal. The quantizer is configured to receive an analog output signal that is based on the filtered analog input signal and convert the analog output signal to a digital output signal. The digital to analog converter is configured to generate an analog feedback signal based on the digital output signal and selectively inject or absorb current associated with the feedback path to reduce noise associated with the digital to analog converter. The analog feedback signal is combined with the analog input signal at an input of the low pass filter element. 1. An analog to digital converter , comprising:a low pass filter element configured to filter an analog input signal;a quantizer configured to (i) receive an analog output signal that is based on the filtered analog input signal, and (ii) convert the analog output signal to a digital output signal; anda digital to analog converter configured to generate an analog feedback signal based on the digital output signal, wherein (i) the digital to analog converter is provided in a feedback path between an output of the quantizer and an input of the quantizer, (ii) the digital to analog converter is configured to selectively inject or absorb current associated with the feedback path to reduce noise associated with the digital to analog converter, and (iv) the analog feedback signal is combined with the analog input signal at an input of the low pass filter element.2. The analog to digital converter of claim 1 , whereinthe digital to analog converter includes a plurality of cells, andthe digital to analog converter is configured to individually activate or deactivate, based on the digital output signal, selected ones of the plurality of cells to inject or absorb, respectively, the current associated with the feedback path ...

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Номер записи: 46
06-03-2014 дата публикации

Sampling circuit, a/d converter, d/a converter, and codec

Номер: US20140062742A1
Автор: Junya Nakanishi, Seiko Nakamoto, Yutaka Nakanishi
Принадлежит: Asahi Kasei Microdevices Corp

An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.

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Номер записи: 47
13-03-2014 дата публикации

Reducing the effect of elements mismatch in a sar adc

Номер: US20140070968A1
Автор: Minkle Eldho Paul, Seetharaman Janakiraman
Принадлежит: Texas Instruments Inc

An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.

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Номер записи: 48
13-03-2014 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT AND IMAGE SENSOR

Номер: US20140070975A1
Автор: Deguchi Jun
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator. 1. A semiconductor integrated circuit configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal , the semiconductor integrated circuit comprising:m (m is an integer greater than or equal to 2) first capacitors, each of which comprises a first electrode and a second electrode, the first electrodes being connected to each other;m second capacitors, each of which comprises a third electrode and a fourth electrode, the third electrodes being connected to each other;a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; anda logic circuit configured to generate the digital signal based on a comparison result of the comparator,wherein the first analog voltage is inputted into the first electrode,the second analog voltage is inputted into the third electrode, andone of a ground voltage and substantially ½ of a voltage of an input voltage range of the semiconductor integrated circuit is inputted into each second electrode and each fourth electrode.2. The circuit of claim 1 , whereinonly two switches are connected to each second electrode ...

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Номер записи: 49
20-03-2014 дата публикации

Arrangement for reading out an analogue voltage signal with self-calibration

Номер: US20140077980A1
Автор: Joris PASCAL, Stephane Isler
Принадлежит: ABB TECHNOLOGY AG

An arrangement for reading out an analog voltage input signal includes an input applying the input signal thereto, and a reference unit generating an analog reference voltage. To perform online self-calibration, the arrangement includes a superposition unit generating a combined analog signal by superimposing the analog reference voltage onto the input signal, a converting unit converting the combined analog signal into a one-bit serial data stream at a conversion sampling rate, and a decomposition unit, which includes at least two digital filters configured to generate from the serial data stream two corresponding digital signals at different data rates, which can be less than the conversion sampling rate. Two data processing units calculate from the corresponding digital signal a digital input voltage representing the input signal and a digital reference voltage representing the analog reference voltage or a disturbance voltage signal representing parasitic voltage components introduced by the superposition unit, respectively.

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Номер записи: 50
27-03-2014 дата публикации

Successive approximation register analog-to-digital converter

Номер: US20140085122A1
Автор: Jong-Kee Kwon, Tae Moon Roh, Young-Deuk Jeon
Принадлежит: Electronics and Telecommunications Research Institute ETRI

A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

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Номер записи: 51
27-03-2014 дата публикации

TIME DIFFERENCE ADDERS, TIME DIFFERENCE ACCUMULATORS, SIGMA-DELTA TIME-TO-DIGITAL CONVERTERS, DIGITAL PHASE LOCKED LOOPS AND TEMPERATURE SENSORS

Номер: US20140086275A1
Автор: Kim Ji-Hyun, KIM Sung-jin
Принадлежит:

A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference. 1. A sigma-delta time-to-digital converter , comprising:a time difference adder configured to receive first and second input signals having a first time difference, the time difference adder being further configured to subtract a second time difference between first and second feedback signals from the first time difference to generate first and second addition signals having a third time difference corresponding to the first time difference minus the second time difference;a time difference accumulator configured to accumulate the third time difference between the first and second addition signals to generate first and second accumulation signals;a time domain quantizer configured to convert a time difference between the first and second accumulation signals into a digital output signal; anda digital-to-time converter configured to convert the digital output signal into the first and second feedback signals.2. A sigma-delta time-to-digital converter , comprising:a time difference adjusting unit configured to receive a first input signal, a second input signal and a digital output signal, the time difference adjusting unit being further configured to delay at least one of the first input signal and the second input signal by a delay time determined according to the digital output signal to generate first and second ...

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Номер записи: 52
01-01-2015 дата публикации

Integrating A/D Converter

Номер: US20150002327A1
Автор: FELDOTTE Heinrich, HOLST Heyko
Принадлежит:

In an integrating A/D converter, first and second reference voltage inputs () alternatingly connect through a reference voltage switch () via a first reference resistor (R) to an inverting input () of an integrator (). A comparator () connected downstream of the integrator () compares a test voltage applied to its test voltage input () with a comparator reference voltage applied to its reference voltage input (). This input () is connected to the output () of the integrator (). A control device () actuates the first reference voltage switch () in a pulsed manner and measures the time intervals between the individual switching processes. An inverter () inverting a measuring voltage (U) and a first heating resistor (R) coupled thermally with a measuring resistor (R), are connected in series between the measuring voltage input () and the output of the first reference voltage switch (). 1. An integrating analog-to-digital (A/D) converter , comprising:a measuring voltage input for an analog measuring voltage, which is connected via a measuring resistor to an inverting input of an integrator,a first reference voltage input for a first reference voltage and a second reference voltage input for a second reference voltage,a first reference voltage switch configured to alternatively connect the first and the second reference voltage inputs via a first reference resistor to the inverting input of the integrator,a comparator connected downstream of the integrator and configured to compare a test voltage applied to a test voltage input of the comparator with a comparator reference voltage applied to a reference voltage input of the comparator, wherein the comparator test voltage input is connected to an output of the integrator,a control device configured to actuate the first reference voltage switch in a clocked manner and to measure time intervals between individual switching processes, andan inverter configured to invert the measuring voltage and a first heating resistor ...

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Номер записи: 53
05-01-2017 дата публикации

LOW POWER ANALOG TO DIGITAL CONVERTER

Номер: US20170005670A1
Автор: Ayers James S., Douglas Jonathan P., Duarte David E., Geannopoulos George L., Hodgson J. Keith, Kornfeld Avner, Oshita Takao
Принадлежит:

Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal. 1. An apparatus comprising:a reference generator to provide a reference voltage;a sigma-delta modulator coupled to the reference generator, wherein the sigma-delta modulator is to receive an analog signal; anda finite state machine (FSM) coupled to an output of the sigma-delta modulator, wherein the FSM is to provide a digital code representing the analog signal.2. The apparatus of claim 1 , wherein the sigma-delta modulator comprises an amplifier and a circuit for performing auto zero correction of the amplifier.3. The apparatus of claim 2 , wherein the sigma-delta modulator comprises a chopper which is operable to cancel common-mode noise from the amplifier.4. The apparatus of claim 2 , wherein the amplifier and the circuit are part of an integrator.5. The apparatus of claim 2 , wherein the amplifier comprises an inverter.6. The apparatus of comprises a first multiplexer coupled to the reference generator.7. The apparatus of claim 6 , wherein the first multiplexer is controlled by an input of the FSM.8. The apparatus of claim 6 , wherein the first multiplexer is to selectively provide one of the reference voltage or a digital bit to a first switch.9. The apparatus of claim 8 , comprises a first capacitive device coupled to the first switch and the amplifier.10. The apparatus of claim 9 , comprises a second switch to receive the analog signal claim 9 , wherein the second switch is coupled to the first capacitive device.11. The apparatus of comprises a third switch coupled to an output of the amplifier and the second switch.12. The apparatus of comprises:a fourth switch coupled to the second switch; anda second capacitive device coupled in ...

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Номер записи: 54
07-01-2016 дата публикации

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE

Номер: US20160006450A1
Автор: Chan Kok Lim, Chen Xuefeng, Fogleman Eric, Ye Sheng
Принадлежит:

Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels. 120-. (canceled)21. A method , comprising: searching through a plurality of quantization levels for a quantization level that matches an analog input; and', 'when said search for said matching quantization level fails within a particular amount of time, adjusting at least a portion of an output of said signal processing circuitry., 'in signal processing circuitry22. The method of claim 21 , wherein adjusting at least a portion of an output of said signal processing circuitry comprises setting at least said portion of said output of said signal processing circuitry to a predefined value.23. The method of claim 22 , comprising selecting said predefined value based on an outcome of processing in said signal processing circuitry prior to or when said search for said matching quantization level fails.24. The method of claim 21 , comprising selecting claim 21 , for adjusting at least a portion of an output of said signal processing circuitry claim 21 , between an output of a normal processing path and an output of a code generation path configured for handling search failures.25. The method of claim ...

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Номер записи: 55
04-01-2018 дата публикации

DIGITAL TIME CONVERTER SYSTEMS AND METHODS

Номер: US20180006658A1
Автор: Banin Rotem, Madoglio Paolo, Palaskas Georgios Yorgos, PREYLER Peter
Принадлежит:

A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal. 120-. (canceled)21. A digital to time converter (DTC) comprising:a divider coarse delay component configured to generate a plurality of divider signals from an oscillator signal based on one or more corrections based on an input signal;a thermometric array configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections; anda switched capacitor array configured to generate a delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits.22. The converter of claim 21 , further comprising a lookup table configured to generate the one or more corrections based on the middle bits of the input signal claim 21 , wherein the lookup table includes a first table configured to generate a thermometric correction based on the thermometric bits and wherein the divider and the thermometric array utilize the thermometric correction and the thermometric bits include the middle bits.23. The converter of claim 22 , wherein the lookup table further includes a second table configured to generate an inverse binary delay correction based on the thermometric bits and the switched capacitor array is configured to utilize the inverse binary delay correction ...

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Номер записи: 56
03-01-2019 дата публикации

ERROR CORRECTING ANALOG-TO-DIGITAL CONVERTERS

Номер: US20190007071A1
Автор: NAGARAJAN Viswanathan, NARU Srinivas Kumar Reddy, RAJAGOPAL Narasimhan
Принадлежит:

A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment. 1. An error correcting analog-to-digital converter (ADC) , comprising:a first ADC segment;a second ADC segment coupled to the first ADC segment; and a digital correction circuit coupled to the first ADC segment and the second ADC segment;', a gain error estimation circuit; and', 'a memory error estimation circuit comprising:, 'an error estimation circuit coupled to the digital correction circuit and comprising], 'a digital backend coupled to the first ADC segment and the second ADC segment and comprising2. The error correcting ADC of claim 1 , wherein the first ADC segment comprises:a flash ADC having an input coupled to an input of the first ADC segment and output coupled to the digital correction circuit;a digital-to-analog converter (DAC) having an input coupled to the output of the flash ADC;a subtractor having a first input coupled to the input of the first ADC segment and a second input coupled to an output of the DAC;an adder having a first input coupled to the digital correction circuit and a second input coupled to an output of the subtractor; andan amplifier having an input coupled to an output of the adder ...

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Номер записи: 57
02-01-2020 дата публикации

DIGITAL-TO-ANALOG CONVERTERS HAVING MULTIPLE-GATE TRANSISTOR-LIKE STRUCTURE

Номер: US20200007135A1
Автор: KUO CHARLES, Pillarisetty Ravi, Rachmady Willy, SHARMA Abhishek A.
Принадлежит: Intel Corporation

Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples. 1. An integrated circuit comprising:a body including semiconductor material;a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material;a first gate electrode at least above the body, the first gate electrode including one or more metals; anda second gate electrode at least above the body, the second gate electrode including one or more metals, the second gate electrode distinct from the first gate electrode, the second gate electrode within 20 nanometers (nm) of the first gate electrode.2. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes indium.3. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes gallium.4. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes one of arsenic claim 1 , phosphorous claim 1 , or antimony.5. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes ...

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Номер записи: 58
02-01-2020 дата публикации

PHASE ROTATOR NON-LINEARITY REDUCTION

Номер: US20200007137A1
Автор: DICLEMENTE Dominic, VAN IERSSEL Marcus
Принадлежит:

A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal. 1. An integrated circuit , comprising:a phase interpolator configured to receive two or more signals having different phases;current source bias circuitry connected to determine respective contributions the two or more signals have to a phase of an output signal, the current source bias circuitry comprising a plurality of switchable current limiting circuits controllable by a thermometer code; and,the plurality of switchable current limiting circuits to each be biased to limit respective currents through respective current limiting circuits to reduce a non-linearity in a relationship between the thermometer code and the phase of the output signal.2. The integrated circuit of claim 1 , wherein respective limited currents through respective current limiting circuits is determined by a dimensioning of a circuit element of the current limiting circuit.3. The integrated circuit of claim 1 , wherein a resistive ladder is used to provide a respective plurality of bias voltages to the respective current limiting circuits.4. The integrated circuit of claim 2 , wherein at least one selectable current is connected to the resistive ladder to adjust the plurality of bias voltages.5. The integrated circuit of claim 3 , wherein the resistive ladder is designed to provide ...

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Номер записи: 59
02-01-2020 дата публикации

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with Switchable Reference Voltage

Номер: US20200007143A1
Автор: Aboudina Mohamed, ELWAN HASSAN, Emira Ahmed, Farid Ali
Принадлежит:

An ADC is disclosed. The ADC includes a SAR logic circuit, a DAC, a comparator, and a voltage generator. The voltage generator includes a first switch connected to the comparator configured to selectively connect a second input terminal of the comparator to a reference voltage, a capacitor connected to the second input terminal of the comparator, and a second switch connected to the capacitor and selectively connected to either of a ground voltage and the reference voltage. The second switch is configured to selectively connect the capacitor to either of the ground voltage and the reference voltage, and the SAR logic circuit is further configured to receive the comparator output voltage, and to generate a digital input word for the DAC based on one or more comparator output voltages received from the comparator. 1. A successive approximation register (SAR) analog to digital converter (ADC) , comprising:a SAR logic circuit configured to generate a digital input word;a DAC, configured to receive the digital input word and an analog input voltage, and to generate a first voltage based on the analog input voltage and the digital input word; a first input terminal configured to receive the first voltage, and', 'a second input terminal configured to receive a second voltage,', 'wherein the comparator is configured to generate a comparator output voltage based on the first and second voltages, wherein the comparator output voltage has a value corresponding with a sign of a difference between the first and second voltages; and, 'a comparator, comprisinga voltage reference generator, configured to generate the second voltage by selecting the second voltage from a plurality of discrete voltage options,wherein the SAR logic circuit is further configured to receive the comparator output voltage, and to generate the digital input word for the DAC based on one or more comparator output voltages received from the comparator.2. The SAR ADC of claim 1 , wherein the voltage reference ...

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Номер записи: 60
08-01-2015 дата публикации

DRIVING CIRCUIT AND DATA TRANSMITTING METHOD

Номер: US20150009057A1
Автор: Chen Chien-Ming, Chou Kuan-Hung, Lo Yu-Lung
Принадлежит:

A driving circuit includes channels, a positive converting unit, a negative converting unit, an input switch, and an operational amplifier. A first digital data and a second digital data are alternatively transmitted in a first channel and a second channel. The positive converting unit and negative converting unit are respectively disposed in first channel and second channel and convert first digital data and second digital data into a positive analog data and a negative analog data. A first input terminal and a second input terminal of operational amplifier are respectively in first channel and second channel. After input switch respectively transmits positive analog data and negative analog data to first input terminal and second input terminal or to second input terminal and first input terminal, positive analog data and negative analog data are transmitted in a channel of the channels corresponding to entering operational amplifier. 1. A driving circuit , comprising:a plurality of channels, comprising a first channel and a second channel, wherein a first digital data and a second digital data are alternatively transmitted in the first channel and the second channel;a positive converting unit, disposed in the first channel, for converting the first digital data into a positive analog data;a negative converting unit, disposed in the second channel, for converting the second digital data into a negative analog data;an input switch, coupled to the positive converting unit and the negative converting unit; andan operational amplifying module, coupled to the input switch, wherein a first input terminal and a second input terminal of the operational amplifying module are disposed in the first channel and the second channel respectively;wherein the input switch transmits the positive analog data and the negative analog data to the first input terminal and the second input terminal respectively or to the second input terminal and the first input terminal respectively ...

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Номер записи: 61
20-01-2022 дата публикации

Signal converting apparatus and related method

Номер: US20220021396A1
Автор: Chun-Chieh Peng, Ta-Shun Chu, Yu-Jiu Wang
Принадлежит: Tron Future Tech Inc

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.

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Номер записи: 62
20-01-2022 дата публикации

BINARY WEIGHTED CURRENT SOURCE AND DIGITAL-TO-ANALOG CONVERTER

Номер: US20220021397A1
Автор: Akdikmen Alper, DAI BIN, Liu Sen, MALOBERTI Franco, SHI Linsen
Принадлежит: Microtera Semiconductor (Guangzhou) Co., Ltd.

The present disclosure provides a binary weighted current source and a digital-to-analog converter, which include: a driving voltage generating circuit, generating a driving voltage based on a preset current; a current dividing circuit, connected to an output terminal of the driving voltage generating circuit; a current steering circuit, connected to the current dividing circuit. The current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor. Currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current. 1. A binary weighted current source , comprising:a driving voltage generating circuit, generating a driving voltage based on a preset current; wherein the current dividing circuit divides the driving voltage through resistors in series, and drives each of a plurality of current output transistors to output a current in response to a voltage across the current output transistor,', 'wherein currents output by the plurality of current output transistor are binary weighted currents, each two of the binary weighted currents have a binary relationship, and the binary weighted currents are produced by successive binary divisions of the preset current,', 'wherein each of the binary weighted currents and a voltage cross the corresponding current output transistor have an exponential relationship between them;, 'a current dividing circuit, connected to an output terminal of the driving voltage generating circuit,'}a current steering circuit, connected to the current dividing circuit and used to control currents passed by the resistors in series,a plurality of current dividing circuits, wherein the plurality of current ...

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Номер записи: 63
14-01-2016 дата публикации

SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER

Номер: US20160013803A1
Автор: Kinget Peter, KUPPAMBATTI Jayanth, Shen Junhua
Принадлежит:

Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. 1. A system for providing a pipelined Analog-to-Digital Converter , comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal;', 'at least two reference capacitors that are charged to a reference voltage;', 'at least two sampling capacitors that are charged to a sampling voltage; and', 'a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage., 'a first multiplying Digital-to-Analog Converter (MDAC) stage comprising2. The system of claim 1 , wherein the first MDAC stage further comprises a first current source coupled to a first of the at least two reference capacitors and a ...

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Номер записи: 64
11-01-2018 дата публикации

CIRCUIT DEVICE, PHYSICAL QUANTITY DETECTION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

Номер: US20180013441A1
Автор: Haneda Hideo
Принадлежит:

A circuit device includes a control circuit having a successive approximation register, a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register, and a comparison circuit adapted to compare an analog input signal and an output signal from the D/A conversion circuit with each other, the control circuit includes an upper limit value register and a lower limit value register adapted to respectively hold an upper limit value and a lower limit value of a conversion range, and increases the upper limit value or decreases the lower limit value in the case in which the same comparison result has been output by the comparison circuit a predetermined number of times or more. 1. A circuit device adapted to perform A/D conversion on an analog input signal , comprising:a control circuit having a successive approximation register adapted to hold successive approximation data;a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register; anda comparison circuit adapted to perform a comparison process between the analog input signal and an output signal from the D/A conversion circuit, includes an upper limit value register adapted to hold an upper limit value of a conversion range of A/D conversion result data obtained by the A/D conversion of the analog input signal, and a lower limit value register adapted to hold a lower limit value of the conversion range, and', 'performs at least one of an update of increasing the upper limit value and an update of decreasing the lower limit value in a case in which the comparison circuit has output a same comparison result a predetermined number of times or more in a successive approximation process., 'wherein the control circuit'}2. The circuit device according to claim 1 , whereinin a case in which the comparison circuit has output a same comparison result the predetermined number of times or more from a first comparison in ...

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Номер записи: 65
10-01-2019 дата публикации

DOUBLE DATA RATE TIME INTERPOLATING QUANTIZER WITH REDUCED KICKBACK NOISE

Номер: US20190013817A1
Автор: Koli Kimmo
Принадлежит:

A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core. 1. An apparatus comprising:a first double data rate comparator circuit configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the first double data rate comparator circuit;a second double data rate comparator circuit configured to determine a relative voltage of a second differential input signal during each of the rising edge and the falling edge in the single clock cycle of the comparator clock input to the second double data rate comparator circuit;a third double data rate comparator circuit configured to determine a relative voltage of a third differential input signal during each of a rising edge and a falling edge in the single clock cycle of an inverted comparator clock input to the third double data rate comparator circuit; anda first floating voltage reference circuit configured to shift a voltage of a differential comparator input signal by a first fixed amount, and produce the first differential input signal;a second floating voltage reference circuit configured to shift the differential comparator input signal by a second fixed amount and produce the second differential input signal; anda clock inverter circuit connected to the comparator ...

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Номер записи: 66
21-01-2016 дата публикации

METHOD AND DEVICE FOR USE IN ANALOG-TO-DIGITAL CONVERSION

Номер: US20160020778A1
Автор: BOGNER Peter, Fyvie Clifford, Suravarapu Niranjan Reddy, Wappis Herwig
Принадлежит:

Disclosed herein are embodiments of a precharge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when said sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a precharge sample-and-hold circuit and of methods to operate a precharge sample-and-hold circuit in an analog/digital converter are also disclosed.

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Номер записи: 67
21-01-2016 дата публикации

Method And System For A Low Input Voltage Low Impedance Termination Stage For Current Inputs

Номер: US20160020780A1
Автор: Gaurav CHANDRA, Rajesh Zele
Принадлежит: Maxlinear Inc

A low input voltage low impedance termination stage for current inputs is disclosed and may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors, wherein a source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor. The input cascode transistors, the feedback transistor, and the stacked output transistors may include complementary metal-oxide semiconductor (CMOS) transistors.

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Номер записи: 68
19-01-2017 дата публикации

DIGITAL-TO-ANALOG CONVERTER

Номер: US20170019122A1
Автор: ONISHI Akinobu
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

A digital-to-analog converter (DAC) circuit includes a first DAC that produces a first analog output signal based upon a received multi-bit digital data and upon a received clock. A second DAC that produces a second analog output signal based upon the received multi-bit digital data and upon the received clock, wherein the first and second DACs are connected in parallel and process the same input signal comprising the multi-bit digital data. In one embodiment, the DACs produce differential signals. A low pass filter connected to receive the first and second analog outputs is configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal. An amplifier connected to receive the ingoing analog signal to produce an amplified ingoing analog signal. 1. A digital-to-analog converter (DAC) circuit , comprising:a first DAC that produces a first analog output signal based upon a received multi-bit digital data and upon a received clock;a second DAC that produces a second analog output signal based upon the received multi-bit digital data and upon the received clock, wherein the first and second DACs are connected in parallel and process the same input signal comprising the multi-bit digital data;a low pass filter connected to receive the first and second analog outputs and configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal; andan amplifier connected to receive the ingoing analog signal to produce an amplified ingoing analog signal.2. The DAC circuit of wherein the first and second DACs each produce differential first and second analog output signals claim 1 , respectively.3. The DAC circuit of wherein the low pass filter is configured to receive the differential first and second analog output signals sum and filter the differential first and second analog output signals to produce a differential ...

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Номер записи: 69
03-02-2022 дата публикации

Duty-cycled analog-to-digital converter system with programmable foreground calibration

Номер: US20220038110A1
Автор: James Edward Bales
Принадлежит: Omni Design Technologies Inc

An analog-to-digital conversion (ADC) system is operated with a duty cycle. During the ON period, the ADC circuits perform analog-to-digital conversions of an analog input signal. During the Standby period, the ADC system is in either a standby state or a foreground calibration state. The ADC system operates in a reduced-power mode in the standby state. In the foreground calibration state, the ADC system performs a portion of a foreground calibration cycle during a calibration time slot. The foreground calibration cycle is performed over multiple calibration time slots. The foreground calibration cycle and the calibration time slots are configurable by changing the values of control registers that represent calibration parameters.

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Номер записи: 70
18-01-2018 дата публикации

Method And System For An Analog-To-Digital Converter With Near-Constant Common Mode Voltage

Номер: US20180019760A1
Автор: Liu Hao, Tang Yongjian
Принадлежит:

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2where x ranges from 0 to m−1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V/128+V/256+V/512+V/1024 when m equals 4 and where Vis the full-scale voltage of the ADC. 1. A method for communication , the method comprising: sampling an input voltage by closing the first and second sampling switches;', 'opening the first and second sampling switches and comparing a voltage level between the input lines;', 'iteratively switching the N switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels; and', 'iteratively switching the M single switched capacitors between ground and different reference voltages., 'in an analog-to-digital converter (ADC) comprising a first sampling switch on a first input line to the ADC, a second sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on said first input line, and N switched capacitor pairs and M single switched capacitors on said second input line2. The method according to claim 1 , wherein the different reference voltages are equal to Vref/2where x ranges from 0 to M−1.3. The method according to claim 2 , wherein a magnitude of a common mode offset of the ADC is less than V/128+V/256+V/512+V/1024 when M equals 4 and ...

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Номер записи: 71
22-01-2015 дата публикации

High-order and nested redundancies in time-interleaved adcs

Номер: US20150022385A1
Автор: Craig Allison Hornbuckle, Krishna Shivaram, Sandeep Louis D'Souza
Принадлежит: Semtech Corp

Examples are provided for time-interleaved analog-to-digital conversion with redundancy. The redundancy may include high-order and nested redundancies. An apparatus may include multiple analog-to-digital converter (ADC) blocks coupled to one another to form a time-interleaved ADC. Each ADC block may include multiple ADC slices, wherein a count of the ADC blocks is M and some of the ADC slices may be redundant slices. A clock circuit may be configured to provide multiple clock signals. A portion N of M ADC blocks may be configured to be active, in a normal mode of operation, where N and M are integer numbers and N is smaller than M. A remaining portion of the M ADC blocks may be redundant ADC blocks, one or more of which may be selectively active, in a healing mode of operation, and be swapped for one or more failed ADC blocks using the plurality of clock signals.

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Номер записи: 72
21-01-2021 дата публикации

METHODS AND APPARATUS FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER

Номер: US20210021276A1
Автор: BENJARAM Rajashekar, SURYADEVARA Maheedhar
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output. 1. A calibration circuit configured to connect to a set of analog-to-digital converters (ADCs) and receive an ADC output code from each ADC , comprising: a logic circuit configured to initiate the first calibration in response to a start signal;', 'a first control circuit in communication with the logic circuit and configured to generate a subtracted code according to a switching point code and the ADC output code;', 'a counter in communication with the logic circuit and configured to determine a code count based on the subtracted code;', 'a missing code generator in communication with the logic circuit and configured to determine a missing_code_count based on the code count and an average code count; and', 'a weight generator in communication with the logic circuit and configured to assign a weight to the missing_code_count and correct the ADC output code according to the assigned weight; and, 'a first calibration sub-circuit configured to perform a first calibration that compensates for a first error type that is shared among each ADC output code and comprisinga second calibration sub-circuit connected to the first calibration sub-circuit and configured to perform a second calibration that compensates for a second error type that occurs among different ADC output codes.2. The calibration circuit according to claim 1 , wherein the logic circuit is further configured to generate a plurality of operation signals claim 1 , wherein the plurality of operation signals comprise:an enable signal generated in response to receiving the ...

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Номер записи: 73
21-01-2021 дата публикации

TIME-INTERLEAVED DIGITAL-TO-ANALOG CONVERTER WITH TIME-DOMAIN DYNAMIC ELEMENT MATCHING AND ASSOCIATED METHOD

Номер: US20210021279A1
Автор: Tseng Wei-Hsin
Принадлежит:

A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs. 1. A time-interleaved digital-to-analog converter (DAC) for converting a digital signal into an analog signal , comprising:a digital processing circuit, arranged to generate a plurality of data sequences according to the digital signal of the time-interleaved DAC, wherein said plurality of data sequences comprise a first data sequence and a second data sequence;a time-domain dynamic element matching (TDEM) circuit, arranged to swap a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence, wherein the first adjusted data sequence comprises first bits of the first data sequence and first bits of the second data sequence, and the second adjusted data sequence comprises second bits of the first data sequence and second bits of the second data sequence;a plurality of DACs, each having at least one DAC cell, wherein said plurality of DACs comprise a first DAC and a second DAC, the first DAC comprises a first DAC cell that operates in response to the first adjusted data sequence, and the second DAC comprises a ...

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Номер записи: 74
26-01-2017 дата публикации

SEMICONDUCTOR DEVICE PERFORMING COMMON MODE VOLTAGE COMPENSATION USING ANALOG-TO-DIGITAL CONVERTER

Номер: US20170026051A1
Автор: CHO Thomas Byung-Hak, LEE Jong-Woo
Принадлежит:

A semiconductor device is provided that includes a first chip that generates a single signal by connecting a first signal line and a second signal line, to which differential signals are respectively provided, and outputs the single signal to a third signal line. The first chip is driven by a first power supply voltage. The semiconductor device also includes a second chip comprising an analog-to-digital converter (ADC) that receives the single signal through the third signal line, compares the single signal with a reference voltage, and outputs a digital signal based on the comparison. The semiconductor device also includes a controller that monitors the digital signal and adjusts the reference voltage to be approximately equivalent to the first power supply voltage. 1. A semiconductor device comprising:a first chip that generates a single signal by connecting a first signal line and a second signal line, to which differential signals are respectively provided, and outputs the single signal to a third signal line, the first chip being driven by a first power supply voltage;a second chip comprising an analog-to-digital converter (ADC) that receives the single signal through the third signal line, compares the single signal with a reference voltage, and outputs a digital signal based on the comparison; anda controller that monitors the digital signal and adjusts the reference voltage to be approximately equivalent to the first power supply voltage.2. The semiconductor device of claim 1 , wherein the second chip further comprises a variable current source claim 1 , the reference voltage is proportional to an amount of current output from the variable current source claim 1 , and the controller adjusts the amount of current output from the variable current source based on monitoring of the digital signal.3. The semiconductor device of claim 1 , wherein the second chip further comprises a voltage divider that comprises a variable resistor claim 1 , the reference voltage ...

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Номер записи: 75
28-01-2016 дата публикации

PIPELINED ANALOG-TO-DIGITAL CONVERTER

Номер: US20160028412A1
Автор: Liu Song, WU Ke, YANG Feiqin
Принадлежит:

The invention provides a pipelined analog-digital converter (ADC) and pertains to the technical field of integrated circuit (IC) design. The pipelined ADC at least comprises: a sampling holder, n multiplier digital-analog converters that are connected stage by stage, a clock generator, a reference generator and a digital encoder, wherein at least the sampling holder and n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection. The pipelined ADC has an excellent performance and is in particular applicable to high speed/high accuracy application. 1. A pipelined analog-digital converter (ADC) , at least comprising:n multiplier digital-analog converters that are connected stage by stage,a clock generator,a reference generator, anda digital encoder;characterized in that at least n multiplier digital-analog converters are substantially arranged in a loop so as to form an intermediate area in an encircling manner; the clock generator and the reference generator are disposed in the intermediate area so that the clock generator and the reference generator respectively provide corresponding signal inputs to the surrounding n multiplier digital-analog converters in a star connection;wherein n is an integer larger than or equal to 2.2. The pipelined ADC according to claim 1 , characterized in that the pipelined ADC further comprises a power bus for supplying power claim 1 , wherein the power bus is arranged substantially in a loop so as to surround therein the sampling holder and n multiplier digital-analog converters connected stage by stage.3. The pipelined ADC according to claim 2 , characterized in that the power bus is arranged in ...

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Номер записи: 76
24-04-2014 дата публикации

Apparatus, method and system for cancelling an input-referred offset in a pipeline adc

Номер: US20140111361A1
Автор: Kalyan Ghatak
Принадлежит: LSI Corp

An apparatus, method and system for offset compensation in a pipeline analog-to-digital converter. A group of capacitors includes one or more sampling capacitors and one or more feedback capacitors, wherein an input to the pipeline analog-to-digital converter circuit is connected to group of capacitors. An amplifier includes a non-inverting input terminal connected to a ground and an inverting input connected to the group of capacitors. The sampling and feedback capacitors are both partitioned in the same ratio to form partitioned capacitors such that a smaller of the partitioned capacitors is employed for offset compensation with respect to the pipeline analog-to-digital converter.

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Номер записи: 77
25-01-2018 дата публикации

Data handoff between randomized clock domain to fixed clock domain

Номер: US20180026781A1
Автор: Eric Otte
Принадлежит: Analog Devices Inc

A time-interleaved analog-to-digital converter (ADC) having M ADCs can increase the sampling speed several times compared to the sampling speed of just one ADC. Some time-interleaved ADCs randomize the order of the M ADCs sampling the analog input signal to improve dynamic performance. Randomization causes the output data of the M ADCs to be valid at randomized time instants. When the output data is sampled using a rising edge of a fixed clock, the output data can be valid just before, valid right at, or only valid for a short period of time after, the rising edge. Therefore, the setup or hold time can be very short. To address this issue, information regarding the randomized selection of an ADC is used to control the sampling occurring in the fixed clock domain and avoid the short setup or hold time.

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Номер записи: 78
24-01-2019 дата публикации

Digital amplifier

Номер: US20190028069A1
Автор: Shinichi Watanabe
Принадлежит: Panasonic Intellectual Property Management Co Ltd

A digital amplifier includes a digital PWM generator, a first amplifier circuit, a first low-pass filter, a second amplifier circuit, a second low-pass filter, an attenuator, an error extractor, an adder, and a voltage supply unit. The first amplifier circuit amplifies a digital PWM signal at a second voltage. The first low-pass filter extracts a low-frequency band voltage signal from the amplified digital PWM signal, and outputs the extracted voltage signal to a load. The second amplifier circuit amplifies the generated digital PWM signal at a third voltage. The error extractor extracts an error signal. The adder adds a digital error signal whose feedback gain is adjusted to a digital audio signal. The voltage supply unit generates the third voltage that has a voltage value of a predetermined ratio to a voltage value of the second voltage, and supplies the third voltage to the second amplifier circuit.

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Номер записи: 79
23-01-2020 дата публикации

High linearity digital-to-analog converter with isi-suppressing method

Номер: US20200028519A1
Автор: Chuan-Hung Hsiao, Kuan-Ta Chen, Sung-Han Wen
Принадлежит: MediaTek Inc

A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.

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Номер записи: 80
04-02-2016 дата публикации

SELECTION DEVICE

Номер: US20160036459A1
Автор: Okamura Jun-ichi, YASUDA Akira
Принадлежит:

Provided is a selection device including an acquisition section for acquiring digital selection signals, and an output section for outputting selection signals to respective unit cells, each unit cell capable of being commanded to output the value zero. The selection device is characterized in that: each selection signal is for commanding the unit cell to output a value corresponding to that selection signal; the sum of the values to be output as commanded by the respective selection signals, which are output to the respective unit cells, is a value determined in association with the digital selection signal; and if the output corresponding to the digital selection signal is the value zero, then selection signals each commanding to output a non-zero value (N) are output to some of the unit cells. 1. A selection device receiving a digital signals and outputting a total value of outputs of a plurality of unit cells , each of unit cells outputting a plus value and a minus value , comprising:a circuit outputting a signal representing a number of unit cells outputting a plus value among the plurality of unit cells, and a signal representing a number of unit cells outputting a minus value among the plurality of unit cells;a selection circuit of a plus side selecting a unit cell outputting a plus value among the plurality of unit cells based on a frequency of selection of the unit cell and the signal representing a number of unit cells outputting a plus value among the plurality of unit cells,a selection circuit of a minus side selecting a unit cell outputting a minus value from the plurality of unit cells based on a frequency of selection of the unit cell and the signal representing a number of unit cells outputting a minus value among the plurality of unit cells,wherein, a value of average time of the total value of outputs of a unit cell outputting a plus value selected by the selection circuit of a plus side and a unit cell outputting a minus value selected by the ...

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Номер записи: 81
31-01-2019 дата публикации

ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING ANALOG-TO-DIGITAL CONVERTER

Номер: US20190036538A1
Автор: TANAKA SACHIYA
Принадлежит:

To reduce power consumption of a sequential comparison analog-to-digital converter. An analog-to-digital converter includes a sequential conversion unit, a determination unit, and a stop control unit. The sequential conversion unit is configured to sequentially generate a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input. The determination unit is configured to determine whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated. The stop control unit is configured to stop the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range. 1. An analog-to-digital converter comprising:a sequential conversion unit configured to sequentially generate a predetermined number of bits of a value corresponding to an analog signal when the analog signal is input;a determination unit configured to determine whether a value of a digital signal including the predetermined number of bits is within a predetermined range whenever the bits are generated; anda stop control unit configured to stop the sequential conversion unit in a case in which the value of the digital signal is not within the predetermined range.2. The analog-to-digital converter according to claim 1 , a comparator configured to compare the analog signal to a reference signal and generate the bits on a basis of a result of the comparison, and', 'a reference signal control unit configured to update a value of the reference signal whenever the bits are generated., 'wherein the sequential conversion unit includes'}3. The analog-to-digital converter according to claim 1 , further comprising:an output control unit configured to output a determination result obtained by determining whether the value of the digital signal is within the predetermined range.4. The analog-to-digital converter according to claim 3 ,wherein the output ...

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Номер записи: 82
31-01-2019 дата публикации

HYBRID DIGITAL-TO-ANALOG CONVERSION SYSTEMS

Номер: US20190036541A1
Автор: ALEXANDER Richard Dennis, WONG Ark-Chew
Принадлежит:

A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal. 1. A hybrid digital-to-analog converter (DAC) driver circuit , the circuit comprising: a current-mode DAC driver configured to receive a first set of bits of a digital input signal and to generate a first analog signal;a voltage-mode DAC driver configured to receive a second set of bits of the digital input signal and to generate a second analog signal; anda combination circuit configured to combine the first analog signal and the second analog signal and to generate an analog output signal,wherein:resistor values of the voltage-mode DAC driver are adjustable to provide termination of the DAC driver circuit,the current-mode DAC driver and the voltage-mode DAC driver comprise differential drivers, andthe current-mode DAC driver and the voltage-mode DAC driver are configured to operate with a single clock signal.2. The circuit of claim 1 , wherein the current-mode DAC driver and the voltage-mode DAC driver are configured to operate using one of binary coded or thermometer coded digital signals claim 1 , and wherein the first set of bits comprises least significant bits (LSBs) of the digital input signal and the second set of bits comprises most ...

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Номер записи: 83
12-02-2015 дата публикации

Communication device and method capable of power calibration

Номер: US20150042497A1
Автор: Chung-Yao Chang, Tsung-Hsuan LEE, Yu-Cheng Chen
Принадлежит: Realtek Semiconductor Corp

The present invention discloses a communication device and a communication method capable of power calibration. Said communication device comprises: a digital circuit to provide a digital output signal; a detection circuit to perform a predetermined detection and generate a detection result; a control circuit to generate a digital-end and an analog-end gain adjustment signals according to the detection result; a digital-end gain adjustment circuit to adjust the gain of the digital output signal according to the digital-end gain adjustment signal and generate a digital gain-adjusted output signal; a digital-to-analog converter to generate an analog output signal according to the digital gain-adjusted output signal; and an analog circuit to adjust the gain of the analog output signal according to the analog-end gain adjustment signal and generate an analog gain-adjusted output signal, wherein the detection circuit is operable to detect the influence caused by a peripheral factor to the analog circuit.

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Номер записи: 84
12-02-2015 дата публикации

CONTINUOUS-TIME OVERSAMPLING PIPELINE ANALOG-TO-DIGITAL CONVERTER

Номер: US20150042501A1
Автор: SHIBATA Hajime
Принадлежит: ANALOG DEVICES TECHNOLOGY

A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. 120-. (canceled)21. A pipelined analog-to-digital converter (ADC) , comprising: a delay unit to generate an analog input current signal representing a delayed version of an analog input voltage signal;', 'an encoder circuit including a plurality of encoders to generate a plurality of digital output signals based on the analog input voltage signal and a plurality of interleaved clock signals;', 'a decoder circuit including a plurality of decoders to generate a plurality of analog output current signals based on the digital output signals and the plurality of interleaved clock signals; and', 'a subtraction circuit to generate a residue signal based on the analog input current signal and at least one of the plurality of analog output current signals., 'at least one pipeline stage including22. The pipelined ADC of claim 21 , wherein the analog input current signal is delayed from the analog input voltage signal by a predetermined period of time.23. The pipelined ADC of claim 22 , wherein the predetermined period of time is based on a period of the plurality of interleaved clock signals.24. The pipelined ADC of claim 21 , wherein the analog input current signal is delayed from the analog input voltage signal by 1.5 times a period of the plurality of interleaved clock signals.25. The pipelined ADC of claim 21 , wherein each of the plurality of encoders generates a respective one of the plurality of digital output signals at a different time based on a respective different one ...

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Номер записи: 85
11-02-2016 дата публикации

LINEARIZED OPTICAL DIGITAL-TO-ANALOG MODULATOR

Номер: US20160043732A1
Автор: Amrani Ofer, Ehrlichman Yossef, RUSCHIN Shlomo
Принадлежит: Ramot at Tel-Aviv University Ltd.

A modulator device for converting digital data into modulation of an optical signal includes an electronic input for receiving an input data word of N bits and an electrically controllable modulator for modulating the intensity of an optical signal, the modulator including M actuating electrodes where M≧N. An electrode actuating device, most preferably a digital-to-digital converter, operates actuating electrodes so that at least one electrode is actuated as a function of values of more than one bit of the input data word. According to an alternative, or supplementary, aspect of the invention, the set of electrodes includes at least one electrode having an effective area which is not interrelated to others of the set by factors of two. In one preferred implementation, a Mach-Zehnder modulator also provides phase modulation to give QAM functionality. Another implementation employs a semiconductor laser. 1. A system for converting digital data into a modulated optical signal , comprising:(a) an electrically controllable device having M actuating electrodes for actuating said device, the device providing an optical signal that is modulated in response to binary voltages applied to the actuating electrodes; and(b) an electrode actuating device having an electronic input for receiving digital input data words having a plurality of bits, and at least one digital-to-digital converter being enabled to provide a mapping of the input data words to binary actuation vectors of M bits and supplying the binary actuation vectors as M bits of binary actuation voltages to the M actuating electrodes, where M>N, N representing a number of bits in each input data word;{'sup': 'M', 'wherein the at least one digital-to-digital converter is enabled to map each digital input data word to a binary actuation vector of M bits by selecting a binary actuation vector from a subset of a total 2possible binary actuation vectors of M bits available to represent each of the received input data words ...

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Номер записи: 86
09-02-2017 дата публикации

CALIBRATION TECHNIQUE FOR CURRENT STEERING DAC

Номер: US20170041014A1
Автор: Dusad Shagun, JOSHI Supreet, KAVILADATH Jafar Sadique, Pentakota Visvesvaraya, SHRIVASTAVA Neeraj, Varshney Himanshu
Принадлежит:

The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal. 1. A current steering digital to analog converter (DAC) comprising: a fixed current source coupled to a primary node of the DAC element through a first estimation switch;', 'a digital code generator coupled to the primary node, and configured to generate a first digital code corresponding to a primary voltage generated at the primary node, the digital code generator configured to generate a second digital code; and', 'a correction DAC coupled to the digital code generator and configured to generate a bias voltage based on the second digital code, the bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal., 'a plurality of DAC elements, at least one DAC element of the plurality of DAC elements coupled to a calibration circuit, the calibration circuit comprising2. The current steering DAC of claim 1 , wherein each DAC element of the plurality of DAC element comprises:a first resistor and a second resistor coupled to a power source;a first switch coupled to the first resistor, and a second switch coupled to the second resistor, the first switch and the second switch ...

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Номер записи: 87
09-02-2017 дата публикации

Successive approximation method with a nonlinear characteristic

Номер: US20170041015A1
Автор: Alexander Kahl, Daniel Lopez-Diaz, Steffen Tratmann, Thomas Niederfriniger
Принадлежит: Lantiq Beteiligungs GmbH and Co KG

A circuit comprises a successive approximation analog-to-digital converter that comprises a feedback path and is operated for example in accordance with the successive approximation method. The feedback path is configured to translate a digital signal in accordance with a prescribed function and to furthermore convert the translated digital signal into an analog feedback signal. For example, the prescribed function can be an exponential function. As such, it can be possible to convert an input signal into an output signal by means of a nonlinear characteristic.

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Номер записи: 88
09-02-2017 дата публикации

Digital to analog converter with output impedance compensation

Номер: US20170041018A1
Автор: Hung-Yi Huang, Tai-Haur Kuo, Wei-Cheng HONG
Принадлежит: National Cheng Kung University NCKU

A digital to analog converter with output impedance compensation has an encoding unit, a current cell array, a summing unit and a compensation unit. The compensation unit is connected to output terminals of the DAC and provides a nonlinear impedance to compensate an original output impedance of the DAC. With the compensated output impedance, the SFDR performance and the linearity of the DAC are improved to obtain a superior input-to-output transfer curve.

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Номер записи: 89
24-02-2022 дата публикации

Ratiometric analog-to-digital conversion circuit

Номер: US20220060194A1
Автор: Jang Hyun Yoon
Принадлежит: Silicon Works Co Ltd

A ratiometric analog-to-digital conversion circuit includes a first voltage range operation circuit configured to use a first power supply voltage of a first voltage range, and output an analog signal corresponding to an external input signal; and a second voltage range operation circuit configured to use a second power supply voltage of a second voltage range, generate a digital value by analog-to-digital converting the analog signal, feed back the digital value for analog-to-digital conversion, and output a digital signal corresponding to the digital value and proportional to the input signal.

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Номер записи: 90
19-02-2015 дата публикации

LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS)

Номер: US20150048959A1
Автор: Zhu Jianyu
Принадлежит:

Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC. 1. A method , comprising: selecting one or more of a plurality of DAC elements in the DAC;', 'forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversion of an input to the DAC; and', 'scrambling remaining one or more of the plurality of DAC elements when generating an output of the DAC that corresponds to the input to the DAC., 'applying adaptive dynamic element matching, in a digital-to-analog converter (DAC), during digital-to-analog conversion, by2. The method of claim 1 , comprising scrambling the remaining one or more of the plurality of DAC elements such that a mismatch error caused thereby does not lead to nonlinear distortion.3. The method of claim 1 , comprising applying the adaptive dynamic element matching when the DAC input is backed off from full-scale.4. The method of claim 1 , comprising controlling the plurality of DAC elements claim 1 , during adaptive dynamic element matching claim 1 , via a switching arrangement comprising one or more switching elements configured for controlling switching of the plurality of DAC elements.5. The ...

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Номер записи: 91
19-02-2015 дата публикации

HIGH OUTPUT POWER DIGITAL-TO-ANALOG CONVERTER SYSTEM

Номер: US20150048961A1
Автор: SCHAFFERER BERND, Zhao Bing
Принадлежит: ANALOG DEVICES, INC.

The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more). 1. A digital to analog converter (DAC) , the DAC comprising: M is an integer greater or equal to 4;', 'each DAC core converts a digital input signal to an analog output signal; and', 'the same input digital word is provided as the digital input signal to the plurality of parallel DAC cores; and, 'M parallel DAC cores, whereina cascode stage directly connected to the outputs of the M parallel DAC cores for combining the outputs of the M parallel DAC cores to provide an aggregate analog output.2. The DAC of claim 1 , wherein M is greater or equal to 8.3. The DAC of claim 1 , wherein:the M parallel DAC cores are built using any one or more of the following: complementary metal-oxide-semiconductor (CMOS) technology, bipolar-complementary metal-oxide-semiconductor (BiCMOS), and silicon-on-insulator (SOI); andthe cascode stage comprises Gallium Arsenide (GaAs) cascodes and/or Gallium Nitride (GaN) cascodes.4. The DAC of claim 1 , wherein:the cascode stage comprises a M cascodes each connected to a corresponding parallel DAC cores directly ...

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Номер записи: 92
18-02-2021 дата публикации

Digital-to-Analog Conversion Circuit

Номер: US20210050862A1
Автор: Henrik FREDRIKSSON, Henrik Sjöland, Martin Anderson
Принадлежит: Telefonaktiebolaget LM Ericsson AB

A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

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Номер записи: 93
18-02-2016 дата публикации

Multi-zone data converters

Номер: US20160049948A1
Автор: Curtis Ling
Принадлежит: Maxlinear Inc

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

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Номер записи: 94
16-02-2017 дата публикации

ANALOG-TO-DIGITAL CONVERSION WITH NOISE INJECTION VIA WAVEFRONT MULTIPLEXING TECHNIQUES

Номер: US20170047935A1
Автор: Chang Donald C.D., Lin Tzer-Hso, Liu Yuanchang
Принадлежит:

An analog-to-digital conversion system comprises a first processor, a bank of N analog-to-digital converters, and a second processor. The first processor is configured to receive M input signal streams, perform a wave-front multiplexing transform in analog domain on the M input signal streams and output concurrently N mixed signal streams, M and N being integers and N≧M>1. The wave-front multiplexing transform comprises a first set of wave-front vectors. The bank of N analog-to-digital converters is coupled to the first processor. The N analog-to-digital converters convert the N mixed signal streams from analog format to digital format and output concurrently N digital data streams. The second processor is coupled to the bank of N analog-to-digital converters. The second processor is configured to receive the N digital data streams, perform a wave-front de-multiplexing transform in digital domain on the N digital data streams and output concurrently N output data streams such that the N output data streams comprise M output data streams that correspond respectively to the M input signal streams. The wave-front de-multiplexing transform comprises a second set of wave-front vectors. 1. An analog-to-digital conversion system comprising:a first processor configured to receive M input signal streams, perform a wave-front multiplexing transform in analog domain on the M input signal streams and output concurrently N mixed signal streams, M and N being integers and N≧M>1, the wave-front multiplexing transform comprising first wave-front vectors;a bank of N analog-to-digital converters coupled to the first processor, the N analog-to-digital converters converting the N mixed signal streams from analog format to digital format and outputting concurrently N digital data streams; anda second processor coupled to the bank of N analog-to-digital converters, the second processor being configured to receive the N digital data streams, perform a wave-front de-multiplexing transform ...

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Номер записи: 95
15-02-2018 дата публикации

METHOD AND APPARATUS FOR ANALOG TO DIGITAL ERROR CONVERSION WITH MULTIPLE SYMMETRIC TRANSFER FUNCTIONS

Номер: US20180048324A1
Автор: BIRKNER John, Cheung Herman, CROTTY Patrick J., Samad Maheen, SHANKAR Kapil
Принадлежит:

An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values. 1. An analog-to-digital conversion (ADC) block comprising:an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal;a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; anda ...

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Номер записи: 96
26-02-2015 дата публикации

Switched Capacitance Converter

Номер: US20150054668A1
Автор: van der Goes Frank Maria Leonardus
Принадлежит: BROADCOM CORPORATION

A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit. 1. A system , comprising:a first capacitor group to facilitate determination of a first bit;a second capacitor group to, in combination with the first capacitor group, facilitate determination of a second bit; anda delayed clock switch to engage the second capacitor group after determination of the first bit.2. The system of claim 1 , where the first bit comprises a most significant bit.3. The system of claim 1 , where the second bit comprises a least significant bit.4. The system of claim 1 , where the first capacitor group comprises a first capacitor paired with a second capacitor in the second capacitor group.5. The system of claim 4 , where the first capacitor has less capacitance than the second capacitor.6. The system of claim 4 , where the first capacitor is situated in parallel with the second capacitor.7. The system of claim 4 , further comprising a latch to drive the first and second capacitors.8. The system of claim 4 , where the first capacitor comprises a set of unitary capacitors situated in parallel.9. The system of where a first ratio of the capacitance of the first capacitor to the capacitance of the first capacitor group is similar to a second ratio of the capacitance of the first and second capacitors to the capacitance of the first and second capacitor groups.10. The system of claim 4 , further comprising a split-capacitance analog-to-digital converter; andwhere the first capacitor group further comprises a third capacitor with a capacitance equal to a capacitance of the first capacitor;where the first capacitor is configured to initialize in a logical high state; andwhere the third capacitor is configured to initialize ...

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Номер записи: 97
25-02-2016 дата публикации

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND SENSING METHOD

Номер: US20160056828A1
Автор: UEKI Hiroshi
Принадлежит:

In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit. 1. A semiconductor device comprising:a timer circuit for generating a piece of time information and a first activation signal which is flowing periodically;a determination circuit for determining whether the value of an analog input signal exists within a predetermined range, in response to the first activation signal;a first conversion circuit for converting the analog input signal to a digital signal, in response to a second activation signal; anda processing circuit for processing the digital signal converted by the first conversion circuit, in response to a third activation signal,wherein, when the analog input signal does not exist within the predetermine range, the determination circuit generates the second activation signal and the third activation signal,wherein the processing circuit stores a piece of digital information corresponding to the digital signal, as well as the piece of time information from the timer circuit, into a storage circuit.2. A semiconductor device according to claim 1 ,wherein the determination circuit is supplied with its operation voltage in response to the first activation signal,wherein the second activation signal and the third activation signal are used as a common ...

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Номер записи: 98
25-02-2016 дата публикации

REDUCING SIGNAL DEPENDENCE FOR CDAC REFERENCE VOLTAGE

Номер: US20160056833A1
Автор: Alladi Dinesh Jagannath, Chen Weihua, Ensafdaran Masoud, Mirhaj Seyed Arash, Wadhwa Sameer, Wen Xiaoke, Yamamoto Kentaro
Принадлежит:

Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step. 1. A method for reducing signal dependence for a reference voltage of a CDAC , the method comprising:selectively isolating at least one of a plurality of capacitors including a first capacitor and a second capacitor from a sampling buffer coupled to the reference voltage,the plurality of capacitors represented as a decoupling capacitor, wherein each capacitor of the plurality of capacitors is smaller in size than a size of the decoupling capacitor,wherein selectively isolating at least one of a plurality of capacitors comprises coupling the first capacitor to the sampling buffer and isolating the second capacitor from the sampling buffer using an isolation switch during a conversion phase; andsupplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of each conversion step.2. The method of claim 1 , wherein the size of each capacitor of the plurality of capacitors is substantially similar.3. The method of claim 1 , wherein the size of each capacitor of the plurality of capacitors is substantially different.45-. (canceled)6. The method of claim 1 , wherein the isolation switch is closed during ...

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Номер записи: 99
25-02-2016 дата публикации

MULTI-LEVEL LADDER DAC WITH DUAL-SWITCH INTERCONNECT TO LADDER NODES

Номер: US20160056834A1
Автор: Frank Aaron L.
Принадлежит:

A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors. 1. A DAC (digital to analog converter) circuit , comprisinga first-first level resistor ladder including multiple series-connected resistors, including a resistor N connected to a previous resistor N−1 at a respective top ladder node NT, and to a next resistor N+1 at a respective bottom ladder node NB;a second-level resistor ladder including multiple series-connected resistors, starting with a top resistor RT and ending with a bottom resistor RB, and with tap nodes between each second-level resistor, each tap node connected to a tap switch operable to select the tap node as a respective tap point; and dual (first and second) interconnect switches selectively connectable to the NT ladder node; and', 'dual (third and fourth) interconnect switches selectively connectable to the NB ladder node;', the first interconnect switch is operable to connect the NT node to a top tap switch operable to select the NT node as a top tap point, and', 'the fourth interconnect switch is operable to connect the NB node to a bottom tap switch ...

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Номер записи: 100