Continuous-phase frequency-shift keying digital demodulation device and demodulation method implemented by same

1. A continuous phase frequency shift keying digital demodulation device, characterized in that comprises a comparator device and a field programmable gate array device, a field programmable gate array device internal circuit includes a clock unit, sampling unit, a counting unit, the buffer unit and reconstruction unit, the clock unit and the sampling unit, a counting unit, the buffer unit and reconstruction unit is connected; said comparator device is connected with the sampling unit; sampling unit are connected with the counting unit; counting unit is connected with the buffer unit; the buffer unit connection reconstruction unit.

2. A the continuous phase frequency shift keying demodulation method of digital demodulation device according to Claim 1, characterized in that the clock unit, according to the continuous phase frequency shift keying signal carrier frequency and modulation degree determining system operating clock frequency value, generated by the external clock frequency of the clock of system work source frequency division , if the external clock source frequency and the working clock frequency ratio is n, then the maximum minute frequency meter value to (n/2)-1, the clock unit working clock signal of the initial state as the low level, the frequency division counter value for 0, clock unit in each of the external clock source rising edge of the frequency division counter value is judged, if the value is less than the maximum minute frequency meter , frequency meter with the value of 1, otherwise turning working clock signals, and a frequency division counter value is reset.

3. A continuous phase frequency shift keying demodulation method of digital demodulation device according to Claim 1, characterized in that the sampling unit at every clock rising edge of the continuous time b value to judge the signal level, if two consecutive signal level to the high level or low level, the low level is output; if the continuous two signal level is not the same, then the output is the high level; the output signal is a zero-cross pulse signal.

4. A continuous phase frequency shift keying demodulation method of digital demodulation device according to Claim 1, characterized in that the counting unit at every clock rising edge of the zero-crossing is judged whether the pulse signal is the high level, if the zero-crossing pulse signal is high level, from the 0 begins counting process, if there are no zero-cross pulse signal, or even a zero-cross pulse signal, however, the count value is less than a minimum count limit value, the count value plus 1, the counting process of the count value exceeding the minimum count limit value of a 1st after over-zero pulse signal arrives, the maximum counting value or idea end beyond the limiting value, counting the end of the process output count value, and output the count complete flag high-level, counting complete flag high-level sustainable a working clock cycle, after counting complete flag bit recovery low level.

5. A continuous phase frequency shift keying demodulation method of digital demodulation device according to Claim 1, characterized in that the buffer unit at every clock rising edge of the finish judging whether the mark bit is the high level, and if it is a high level, reading count value, the counting value is stored to the cycle according to the address order in data storage space a, and updates the current memory space occupancy, during the operation when the system is just starting, the buffer unit accumulated count value data to the circulating data storage space is occupied by half, the data valid flag bit to output a high level lasting one operating clock cycle, and from cycle data storage space according to the address order in extracting a count value output; thereafter continued system operation, at every clock rising edge, the reconstruction of complete flag is judged whether it is a high level, if the high level from the cycle data storage space according to the address order in extracting a count value output.

6. A continuous phase frequency shift keying demodulation method of digital demodulation device according to Claim 1, characterized in that in each working reconstruction unit clock rising edge is judged whether data effective flag bit is the high level, and if it is a high level, then enter the reconstruction state, reading a count value, the counting value is compared with a preset threshold value, if the count value is greater than a threshold, a demodulation output signal is the high level, otherwise demodulated output signal is low-level; thereafter in order to count value to maximum value carries out reverse counting, for each of the clock rising edge if the countdown value is not 0, the demodulated output signal unchanged, countdown the value reduces 1, or else, rebuilding the complete flag bit to output a high level lasting one operating clock cycle, the next renewal process, re-reading of the new count value, is compared with a threshold, output the new demodulation signal, count down again.