SEMICONDUCTOR PACKAGE
The present invention refers to semiconductor package relates to, probe-type test-by current screen efficiency can be improved 2000. The tendency of the electronics industry today weight, size, speed, multi-functionality, high performance reliability is a product having. can be easily produced at low cost. Is products such as to enable effectuating target of the design and to minimize the a major techniques consists of a package is assembling techniques. The assembling techniques the package growth process is performed by wafer fabrication the bonding wire of the semiconductor chip integrated circuit is formed external and to protect it from the environment and, on a substrate is to a multi-processor system and easily mount and ensure the reliability of the chip is. is a technique to. Existing a wafer by cutting the semiconductor chip then separated into, individual semiconductor chip is produced by a method in which line according been embodiment. However, said of packaging process may in itself be many unit processes, i.e., inspecting substrate using cos manner and, wire bonding, molding, trim/forming such as, comprises a processes. Said semiconductor chip according each packaging process is to be performed the existing and package manufacturing method, one wafer along with resulting semiconductor chip, when considered in the number of, in which all of the semiconductor chips for packaging time. a heavy metal. The, , the individual semiconductor chip in the state disconnected assembly adhesive, the upper rail and the lower rail line grown in wafer state the external connections of ball shaped and individual second a workpiece for separating a semiconductor chip is produced by preforming (Wafer Level Chip Scale Package) as wafer level chip scale package using techniques is proposed. Wafer level chip scale package of surfaces of a simply manufacturing method, first, for the top surfaces is provided to reduce a process cost exposing the bonding pads on the upper surface semiconductor chip insulating layer is then formed on a number 1, number 1 on the insulating layer bonding pads and each individual connection is form the. Furthermore, number 1 is etched to rerouting metallized film and soldering on insulating layer and insulating layer is then formed on a number 2, exposed on redistribution metal external connection terminals are attached to a vehicle. Furthermore, external connection terminals are chip level layer to low-density oxygen cutting into wafer level chip scale package of the fabrication is completed. And, through electrode (TSV; Through silicon via) through system-on-chip chips constituting or, through electrode the memory through the chips multi-chip package (MCP; Multi Chip Package) configuring a. also. Semiconductor device pad an external wiring is in a portion connected to. State of the SP heads and, in the case of multiple chip package to expose the pad on which general size relative to small the bump pad with the is made to be greater than about. Bump pads is too size of memory when the amount of light concentrated on a probe upon probe-type test for testing using bump pad of the. it is not possible the Glacier has scored the profile. The, probe to perform a test further pad the probe to test is performed on printed onto the product, thus resulting. This case, bump pads and the probe test pad is parts is changed in a rule path using. To this end, probe-type test pads and separate buffer arranged for, , for transmission of a signal driver., it is necessary to have additional a method for manufacturing the same. Probe-type test pad, from the outside signal for testing is pad index finger receiving. Probe-type test pad, by probe for testing are found to exhibit significantly rod finally inputted character is a pad that is preferably set-up. Therefore, by means of separated outlets for probe-type test test enabling operation to consistently perform the cooking operation circuit consisting of current consumption is. An element region of this current though the actual operation of an article current screen efficiency is silicon layer and the substrate. In particular, high frequency inputted on testing operation to consistently perform the cooking operation are evenly distributed to the circuit when probe circuit for testing of the actual mounted on the upper plate of the current component screen operation to the is is difficult to. Semiconductor package using using bump pad of relate of the present invention embodiment in probe-type test for power testing mode can be generated by converting the current test by to improve the efficiency of screen to is connected to the semiconductor layer.. The present according to one embodiment of the invention a semiconductor package, probe a probe upon testing pad the liquid crystal is injected into the buffering driven by a probe circuit part; bump pads bump buffering the signal applied from circuit part; and test mode in response to a gate voltage is supplied to circuit probe said internal power supply of a level is changed-up control signal characterized in that including. A semiconductor package according to other embodiment of the present invention, probe-type test data is inputted data pad; internal power supply associated with the buffering an effective data applied from the pad number 1 probe-type test buffer; internal power supply corresponding to an effective data applied from the buffer probe-type test number 1 driving number 1 probe-type test driver; bump pads bump buffering the signal applied from circuit part; and test mode in response to a gate voltage driver probe-type test number 1 number 1 probe-type test buffer and of an internal power supply can supplied to a level is changed-up control signal characterized in that including. Semiconductor package using using bump pad of relate of the present invention embodiment in probe-type test for power testing mode can be generated by converting the current test by to improve the efficiency of screen to a provides. Also Figure 1 shows a configuration it is shown a semiconductor package according to an embodiment of the present invention. Details about the power selection unit outputs an Figure 2 shows a circuit diagram of Figure 1. Hereinafter, in the present invention is in the field of the person with skill in the art is to facilitate technical idea of the present invention can be embodiment detailed to describe the, accompanying drawing thereby, the cold air flows of the present invention the most preferred embodiment to illustrate the reference to time as large as that of. In the present invention describes, the present subject matter of invention configuration of publicly known not related to the record carrier can be dispensed with. Each of the drawings components in by adding reference number, a structure similar to that of the other although don showing the severest elements displayed on drawings sheet even the same reference number as possible capable of being utilized in a low. to significantly different. Semiconductor device including DDR SDRAM (Double Data Rate Synchronous DRAM) of the user needs variety of other tests which developed in the direction, the orientation power generation thereof (package) techniques are is connected. A packaging technique for power with combustive the semiconductor device from a chip package (Multi Chip Package, MCP) invention relates to. Plurality semiconductor multi-chip package become a single chip chip to the swollen numeral key, the memory chips between the two uses plural formed on or different semiconductor integrated circuit using to improve the desired performance.. With reference to, monolayer according to a multi-chip package and multi-layer multi-chip package can be divided into multi-chip package, a plurality of multi-chip package monolayer in a substantially planar semiconductor chip, multi-layer printed wiring board are disposed side by side across the a plurality of multi-chip package are arranged stacked on one semiconductor chip. While, plurality of semiconductor integrated circuit in a multilayer multi-chip package when implemented, each existing a wirebonding input/output terminal of semiconductor chip, to make was (wire bonding). However, high speed operation when the mother pipe having a wire bonding various noise due to the presence of an at regular intervals and, power with combustive the wire bonding using packaging technique (chip on chip) having almost the same size each other instead of wet liquid to flow down. Having almost the same size each other bump each of plurality of semiconductor chips packaging technology (bump) and the through silicon via (Throuth Silicon Via, TSV) as packaging technique for directly connecting through the, plurality of semiconductor integrated circuit without wire. the thermal deformation layer is in a vertical direction. Having almost the same size each other such packaging technique when the mother pipe having a main cell is connected to a speed, power consumption, reducing the risk of. may also be. Furthermore, multi-chip package total area also minimized a premature been all this while the lower part are is one techniques Also Figure 1 shows a. configuration shown semiconductor package according to an embodiment of the present invention. Data relate of the present invention embodiment (DQ) pad (100), address (CA) pad (110), probe-type test buffer (120,130), probe-type test driver (140,150), bump pads (160,170), bump buffer (180,190) and power selection unit outputs an (200) includes. Wherein, data (DQ) pad (100), address (CA) pad (110), probe-type test buffer (120,130), probe-type test driver (140,150) the probe circuit part (10) and corresponding to, bump pads (160,170) and buffer (180,190) the bump circuit part (20) corresponding to.. First, data pad (100) the probe-type test data in. is a pad that is inputted. And, address pad (110) the probe-type test in. is a pad that an address is inputted to the. Of the present invention in the embodiment an address pad (110) the command (command) but is an address is inputted to the a described example. Computer program application, stores data semiconductor memory device, for outputting data stored in a the. Semiconductor memory device performs testing in a state a wafer (wafer), normal semiconductor memory device a packaging (packaging) various information on the. produced. This semiconductor the inner in the external voltage depending on the intended use and generates internal voltage within. This semiconductor package normal test is carried out in order to. can determine that the picked. May be carried out at an semiconductor package, semiconductor device production in order to increase its efficiency to a normal state of the whether to operate tested for the probable process the embodiment. Process a test against a semiconductor device, on a pad of semiconductor device after applying electrical signal normal output data is made by identifying whether the. For testing semiconductor package (monitoring) monitoring internal voltage during a test mode and, inner voltages of a circuit used in and provides an internal voltage by test.. Such as on, in or monitoring internal voltage is determined voltage (DQ) in data in (probing pad) probing pad pad (100), address (CA) pad (110) is used. Data pad (100) and a, address pad (110) has in a wafer state when testing a may be used for an the aim of signal transduction. Probe test enabling test a staff makes a probe-type test card including probe pin connected to probe pad (100,110) to probing various test operation performs. For probe-type test in of the present invention in the embodiment to the pad in response to the data pad (100) and a, address pad (110) equipped with at least one in one example described. However, of the present invention in the embodiment the kind of pad for probe-type test in limited which are not of, command input pad (Command), external power supply pads, ground power supply pads, forced from the outside for testing signal inputted to the test pad index finger receiving internal devices are internal operation and semiconductor memory for monitoring a voltage, or others may be proposed pad. Thus various use external signal for purposes an inner the chip pad are copyright 2000. And, probe-type test buffer (120) the data pad (100) an effective data applied from the driver probe-type test the DMC through the first input node (140) 1 and provides an output to. Probe-type test buffer (130) the address pad (110) applied from address by buffering probe-type test driver (150) 1 and provides an output to. Wherein, probe-type test buffer (120,130) the power selection unit outputs an (200) an internal power supply applied from and operates by IVDD. Furthermore, probe-type test driver (140) the probe-type test buffer (120) an effective data applied from the driving between the bumps pad (160) 1 and provides an output to. Probe-type test driver (150) the probe-type test buffer (130) an effective data applied from the driving between the bumps pad (170) 1 and provides an output to. Wherein, probe-type test driver (140,150) the power selection unit outputs an (200) an internal power supply applied from and operates by IVDD. Bump pads (160) the drives the bump buffer (180) outputs the to. And, bump pads (170) the even portion bump buffer (190) outputs the to. Of the present invention in the embodiment an address pad (110) the command (command) but is an address is inputted to the a described example. Such bump pads (160,170) has of a semiconductor package mounted on the substrate to a semi-conductor chip or otherwise the aim of delivery signature when the stacked may be used for an. And, bump buffer (180) the bump pads (160) an effective data applied from the 10, and outputs it as a iDQ internal data the DMC through the first input node. Furthermore, bump buffer (190) the bump pads (170) by buffering address applied from internal address iCA 10, and outputs it as a. Wherein, bump buffer (180,190) a power supply voltage VDD2 and operates by. Multi-chip package generally entails provided with movable spacer size relative to to small bump pads (160,170) using bump pads (160,170) of. non-probing. Therefore, data for performing a test [...] (DQ) pad (100), address (CA) pad (110), probe-type test buffer (120,130) and probe test driver (140,150) includes. State of the SP heads and, probe-type test to perform data pad (100) of address pad (110) the probes such pad are arranged more is extends the test time. Test apparatus tests an provided since limitations in the number of channels, of a workpiece through a single process a number of dies to expose the pad information on an ID as to reduce the number of. it is advantageous. And, probe pad (100,110) and a bump pads (160,170) and away the distance between the, of signals are multiple of pad for one probe surface, extending from the bump pad (160,170) is case said vibrations are transmitted to the to may be proposed. The, data pad (100) of address pad (110) signal inputted to the bump pads (160,170) order to transfer probe-type test buffer (120,130) and a, probe-type test driver (140,150) is using. The bump is package having almost the same size each other, and the sizes of very small. is to design a. However, such test enabling using including probe pin for small size bump very contact including probe pin it is difficult. Therefore, probe test operation of a time and money for normal surface, extending from the bump pad greater than sizes and proportions to the core probe pad is electrically connected with the. must design. Recently through electrode (TSV; Through Silicon Via) the semiconductor chips of wet liquid to flow down are developed semiconductor device. This semiconductor device surface, extending from the bump pad in one example as pad input/output in the case of (bump pad, 160,170) as a main component is of wet liquid to flow down. I.e., (TSV) in semiconductor package plurality of chip is connected with a, surface, extending from the bump pad (160,170) (TSV) through electrode of respective chips the liver an external sound tube of make. A semiconductor package surface, extending from the bump pad (160,170) using only structure should probe-type test apparatus for manufacturing and cannot DL2-DLN. Therefore, probe-type test by means of separated outlets for circuit and pad (100,110) is is constructed with. If, probe circuit part (10) and circuit part (20) the same power operative on the timing does the same with the arming circuit part probe even if an (10) current. a locking feature may be added. The, actual in operation during test compared to high current can current increases can be and not lowering the efficiency of high screen. Therefore, power selection unit outputs an relate of the present invention embodiment (200) IVDD power signals from the circuit part probe in a test mode according to (10) selectively controlled using a power source being supplied to outputs a relay driving signal.. I.e., power selection unit outputs an (200) corresponding to a test mode signal TM_VDD power supply voltage VDD2 and a power supply voltage for selecting either a VDD1A the probe circuit part (10) IVDD 1 and provides an output to sense-amp of. Wherein, power supply voltage VDD2 the bump circuit part (20) using a power source being supplied to same is power level. And, a power supply voltage VDD2 VDD1A power supply voltage that are separated from each other and has a power source, power supply voltage VDD1A a power supply voltage VDD2 has different voltage levels level and. VDD1A the power source voltage at the of the present invention in the embodiment a power supply voltage VDD2 has a voltage level that is higher than. Power selection unit outputs an (200) generates and transmits a generic test the test mode signal TM_VDD is number 1 level (for example, low level) non is activated. The, VDD2 power supply voltage IVDD internal power supply is to probe circuit part (10) is applied to a multi-. This case probe circuit part (10) and circuit part (20) same VDD2 power supply voltages is driven by level. I.e., general on test mode toward the probe circuit part (10) and circuit part (20) same VDD2 power supply voltages so driven by level. While, power selection unit outputs an (200) comprises a current on test mode test mode signal TM_VDD is number 2 level (for example, high level) is activated. The, internal power supply is VDD1A power supply voltage IVDD to probe circuit part (10) is applied to a multi-. This case probe circuit part (10) and circuit part (20) each other is driven by different voltage levels. I.e., on test mode current toward the probe circuit part (10) is bump circuit part (20) and a different supply power voltage VDD1A so driven by. Thus current on test mode probe circuit part (10) power of bump circuit part (20) and another measuring a current used is especially. Furthermore, probe circuit part (10) the current flowing to the except that the, bump circuit part (20) substantially a dose set by operation of the measure only a current flowing into the current are formed to improve the efficiency of screen is enabled. Such different power relate of the present invention embodiment that is capable of using the semiconductor package may be used in, test mode signal TM_VDD VDD1A power supply voltage depending on whether it is application of and a power supply voltage VDD2 are separated off and the can be testing. I.e., VDD1A power supply voltage at the time of test signal corresponding to the activating system is filled with test mode signal TM_VDD measure the current. And, power supply voltage VDD2 corresponding to each controller on test mode a general TM_VDD mode signal for de-activating current measure the. Figure 2 shows a power selection unit outputs an (200) is details about the circuit diagram of Figure 1. Power selection unit outputs an (200) the inverter IV1 and a, number 1 power selection unit outputs an (210) and number 2 power selection unit outputs an (220) includes. Wherein, number 1 power selection unit outputs an (210) includes the PMOS transistor P1. PMOS transistor P1 a power supply voltage VDD2 applied stage and the internal power supply voltage IVDD output is connected between gate terminal TM_VDD is applied tests through mode signal. And, number 2 power selection unit outputs an (220) includes the PMOS transistor P2. PMOS transistor P2 VDD1A applied stage and the internal power supply voltage in a power supply voltage IVDD output is connected between gate terminal through inverter IV1 reversed through the test mode signal TM_VDD is applied. The test generally TM_VDD non at a low level at the test mode signal is activated. The, PMOS transistor P1 is turned on PMOS transistor P2 is turned off and power supply voltage VDD2 IVDD internal power supply is to probe circuit part (10) is applied to a multi-. And, current TM_VDD is a first level test mode signal test mode is activated. The, PMOS transistor P1 is turned and off PMOS transistor P2 is turned on the source voltage VDD1A IVDD internal power supply is to probe circuit part (10) is applied to a multi-. These chip scale package digital camcorder, portable telephone, notebook computer, such as memory card size, mobility required is employed primarily in the products. E.g., DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), micro controller (Micro Controller) the nitride layer and the like in scale package the chip is mounted. Furthermore, DRAM (Dynamic random access memory), flash memory (flash memory) such as charge coupled device element the memory such as use of chip scale package increasingly diffuse and. Said idea techniques of the present invention according to a preferred embodiment but described in time specifically, said embodiment for the explanation relate the restriction which is for the. attention not. Furthermore, if expert art of the present invention of the present invention within the range of a minimum slimly embodiment styles are discussed a main body 2000. The present invention relates to a semiconductor package capable of improving current screen efficiency when a probe test is conducted. The semiconductor package comprises: a probe circuit unit configured to be operated by buffering a signal inputted from a probe pad when the probe test is conducted; a bump circuit unit configured to buffer the signal applied by a bump pad; and a power selection unit configured to change a level of internal power supplied to the probe circuit unit in response to a test-mode signal. COPYRIGHT KIPO 2016 Probe a probe upon testing pad the liquid crystal is injected into the buffering driven by a probe circuit part; bump pads bump buffering the signal applied from circuit part; and test mode in response to a gate voltage is supplied to circuit probe said internal power supply of a level is changed to semiconductor package characterized by including-up control signal. According to Claim 1, said a power selection unit outputs an power supply voltage according to said test mode signal number 1, number 2 the power supply voltage internal power supply for outputting to said characterized by semiconductor package. According to Claim 2, said number 2 power supply voltage said number 1 power supply voltage characterized by that the same is provided with at a level higher than a level of semiconductor package. According to Claim 1, said a power selection unit outputs an said test mode signal is deactivated if the memory cell is not conductive number 2 said internal power supply to the power supply voltage, said test mode signal the activated state number 1 when the power supply voltage to said internal power supply for outputting characterized by semiconductor package. According to Claim 1, said a power selection unit outputs an said test mode signal is deactivated if the memory cell is not conductive bump said coextensive with the circuit said internal power supply fed power, said test mode signal is activated if the memory cell is not conductive power other circuit section and an bump said said internal power supply products characterized by semiconductor package. According to Claim 1, said probe and a transmission part for transmitting said probe-type test data is inputted to characterized by semiconductor package including a data pad. According to Claim 6, said probe and a transmission part for transmitting said internal power supply corresponding to an effective data applied from the data pad said buffering further buffer probe-type test number 1 characterized by including to semiconductor package. According to Claim 7, said probe and a transmission part for transmitting said internal power supply corresponding to an effective data applied from the buffer probe-type test said number 1 driving further driver probe-type test number 1 characterized by including to semiconductor package. According to Claim 1, said probe and a transmission part for transmitting an address is inputted to the probe-type test in an address pad characterized by including to semiconductor package. According to Claim 9, said probe and a transmission part for transmitting said internal power supply corresponding to said address pad applied from address buffering to further buffer probe-type test number 2 including characterized by semiconductor package. According to Claim 10, said probe and a transmission part for transmitting said internal power supply corresponding to address applied from the buffer to the probe-type test said number 2 for driving further driver probe-type test number 2 characterized by including to semiconductor package. According to Claim 1, said bump and a transmission part for transmitting including using bump pad of the number 1 to characterized by semiconductor package. According to Claim 12, and a transmission part for transmitting said bump an effective data applied from the bump pads said number 1 number 1 bump buffer further including buffering to characterized by semiconductor package. According to Claim 1, said bump and a transmission part for transmitting an address is inputted to the number 2 to characterized by including using bump pad of a semiconductor package. According to Claim 14, and a transmission part for transmitting said bump applied from bump pads said number 2 number 2 buffering address to further buffer bump including characterized by semiconductor package. Probe-type test data is inputted data pad; said internal power supply corresponding to an effective data applied from the data pad buffering buffer probe-type test number 1 ; said internal power supply corresponding to an effective data applied from the buffer probe-type test said number 1 driving number 1 probe-type test driver; bump pads bump buffering the signal applied from circuit part; and test mode in response to a gate voltage said number 1 probe-type test buffer and said supplied to driver probe-type test said number 1 of an internal power supply can level is changed to a semiconductor package characterized by including-up control signal. According to Claim 16, a power selection unit outputs an said test mode signal according to said power supply voltage number 1, number 2 the power supply voltage internal power supply for outputting to said characterized by semiconductor package. According to Claim 17, said number 2 power supply voltage said number 1 power supply voltage characterized by that the same is provided with at a level higher than a level of semiconductor package. According to Claim 16, a power selection unit outputs an said said test mode signal is deactivated if the memory cell is not conductive number 2 said internal power supply to the power supply voltage, said test mode signal the activated state number 1 when the power supply voltage to said internal power supply for outputting characterized by semiconductor package. According to Claim 16, a power selection unit outputs an said said test mode signal is deactivated if the memory cell is not conductive bump said coextensive with the circuit said internal power supply fed power, said test mode signal is activated if the memory cell is not conductive power other circuit section and an bump said said internal power supply products characterized by semiconductor package.
