SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

The disclosure of the present invention general outline according to embodiment or application to a particular specification for the examples of the present invention general outline according to embodiment example structural functional disclosure that only to account for the purpose of example, embodiment examples of the present invention general outline according to embodiment in various forms can be the specification described embodiment examples are not limited to an application or interpreted.

Various modification examples of the present invention general outline according to embodiment can apply an embodiment may have specific examples and drawing in various forms since the example detailed specification or application to a broadcast receiver. However, this example of the present invention general outline according to embodiment specific disclosure but is to be defined with respect to form, all changing range of idea and techniques of the present invention, including the water to replacement should understood to evenly.

Various components such as number 1 or number 2 and/describes the term can be used but, in terms of said components are defined by said back like. Components are mounted to one of said terms object only distinguished from other components, for example of the present invention general outline according to those that are required from separating from the scope of the invention, components can be termed component number 2 number 1, number 2 components can be similarly designated as number 1 component.

Any component and other components "connected" or folder "connected" when referred to that, or the other components connected directly or may be connected, other components might lead to intermediate is present it will will be. While, any component and other components referred to as "directly connected" or folder that when "directly connected to", should be understood to does not exist in the middle of other components will. Other representations describing a relationship between the components, i.e. "- between" on "between immediately -" or "- of the adjacent" and "directly - neighboring" should likewise be interpreted like.

A term used in a particular embodiment to account for example specification only is used, the present invention intending to be define is endured. It is apparent that a single representation of the differently in order not providing language translators, comprising plurality of representation. In the specification, the term "comprising" or "having disclosed" such as described features, numbers, steps, operation, component, piece or specify a combination not present included, another aspect of one or more moveable number, step, operation, component, piece or a combination of pre-times the number should not understood to presence or additional possibility.

Not defined differently, scientific or technical terms so that all terms in the present invention thus is provided to the person with skill in the art will generally have the meanings etc. by same. Generally dictionary used for providing language translators such as defined terms have the meanings associated technology must be consistent semantics and having interprets, the specification defined manifest in not, or overly formal sense interpreted not ideal.

In the present invention embodiment example is provided to describe the present invention outside the field is a known technique for the content description and be directly related to free omit other. This is formed by the subject matter of invention without unnecessary description by more clearly for delivering a haze are disclosed.

Hereinafter, a preferred embodiment of the present invention example by describing objects with reference to the drawing, the present invention is described therein that are directionally. Hereinafter, with reference to the attached drawing example of the present invention embodiment detailed as follows.

Figure 1 shows a configuration of the memory system indicating block also are disclosed.

Memory system (50) a semiconductor memory device (100) and controller (200) having a predetermined wavelength.

Semiconductor memory device (100) includes a NAND flash memory (NAND flash memory), (Vertical NAND) vertical NAND flash memory, nor flash memory (NOR flash memory), ram (resistive random access memory: RRAM) resistance, phase change memory (phase-a change memory: PRAM), magnetoresistive memory (magnetoresistive random access memory: MRAM), ferroelectric memory (ferroelectric random access memory: FRAM), magnetization inversion can be injected into the memory (spin transfer torque random access memory: STT provided RAM) is red. In addition, semiconductor memory device of the present invention (100) includes a 3 dimensional array structure (three non-dimensional array structure) can be implemented. The present invention refers to charge storage layer is composed of conductive floating gate (floating gate; FG) as well as a flash memory device, charge storage layer insulation films charge trap flash (charge trap flash; CTF) can be applied.

Semiconductor memory device (100) the memory cell array (110) and a memory cell array (110) for driving peripheral circuitry (120) having a predetermined wavelength. Memory cell array (110) comprises a plurality of non-volatile memory cells includes the.

Memory cell array (110) and has a plurality of memory blocks, according to a plurality of memory blocks is composed of a bottom and user system block can be there are.

In one embodiment, memory cell array (110) includes a cam (Content Addressable Memory, CAM) region (111) comprises. Cam region (111) has at least one memory block can be a reading unit memory cells. Cam region (111) can be cam block corresponding to the memory block. The memory block has cam block may have is the same in structure. Cam region (111) is semiconductor memory device (100) can be stored in the setting of an.

Specifically cam region (111) predetermined conditions related to the operation of the status or other information can be stored. In one embodiment, cam region (111) (P/E Cycle) number is read/write embodiment, defective column address, a defective block address information can be stored. In one embodiment, cam area (111) is semiconductor memory device (100) in order to operate is options information, e.g. program voltage information, read voltage information, erase voltage information or cell gate oxide thickness information can be stored. In one embodiment, cam region (111) can be the repair information is stored. Semiconductor memory device (100) is energized, cam region (111) information stored in a circumferential circuit (120) is read by, peripheral circuit (120) is set according to the condition and outputting data read information memory cells to perform memory cell array (110) [e[e] it will do be a number.

According to the example of the present invention embodiment, cam area (111) is semiconductor memory device is a read operation required for discharging a plurality of lines (tref1) reference time number 1 and number 2 (tref2) reference time information can be stored.

A semiconductor memory device number 1 reference time (tref1) selected word line voltage reaches the time be a pass voltage (Vpass).

A semiconductor memory device number 2 (tref2) reference time of memory cell array of select lines (DSL, SSL) is be a discharge time. Select lines (DSL, SSL) reaches the ground voltage (GND) voltage can be time.

Peripheral circuit (120) includes a controller (200) in response to an opposite side of number and operate. Peripheral circuit (120) includes a controller (200) in response to an opposite side of number, memory cell array (110) can program data. Peripheral circuit (120) memory cell array (110) reading data from an memory cell array (110) operable to erasing data of a can.

In various embodiment, semiconductor memory device (100) the page read operation of and program operations can be performed. Semiconductor memory device (100) erase operations can be performed in the plurality of memory blocks.

Program operation, peripheral circuit (120) includes a controller (200) exhibit from a command, physical block address (PBA) (physical address, PA) and write data can be. Peripheral circuit (120) through a physical block address (PBA) according to a selected pages included in one memory block and the corresponding memory block, selected page programs data write can be.

Engine, peripheral circuit (120) includes a controller (200) command (hereinafter, read command) for reading from exhibit, physical block address (PBA) can be receiving. Peripheral circuit (120) through a physical block address (PBA) by a selected one of a memory block and its included in one page reading data from an, from a read data (hereinafter, page data) controller (200) can be outputs.

Erase operation, peripheral circuit (120) includes a controller (200) and physical block address (PBA) exhibit erased from command can be receiving. Physical block address (PBA) identifying the one or more memory blocks are disclosed. Peripheral circuit (120) through a physical block address (PBA) data of a memory block corresponding to the erased are disclosed.

Controller (200) for defect device (100) is enclosed by a protective operation number etched. Controller (200) in response to requests from external host semiconductor memory device (100) can access the disclosed. Controller (200) in response to requests from external host semiconductor memory device (100) decodes a command.

Example embodiment, controller (200) includes a program operation, read operation or erase operation to perform semiconductor memory device (100) [e[e] it will do a number are disclosed. Program operation, controller (200) includes a program command, address and data through a channel semiconductor memory device (100) to under public affairs number will. Engine, controller (200) includes a read command and address through a channel semiconductor memory device (100) to under public affairs number will. Erase operation, controller (200) is erase command and address through a channel semiconductor memory device (100) to under public affairs number will.

Controller (200) includes a ram (210), memory number control unit (220) and error correction circuit (230) can be comprising.

Ram (random access memory; RAM) (210) memory number control unit (220) number of opposite side operable pursuant, work memory (work memory), buffer memory (buffer memory), cache memory (cache memory) or the like can be used. Ram (210) is used as a work memory, memory number control unit (220) is treated with a data can be temporarily stored. Ram (210) is used as a buffer memories, host (not shown) in semiconductor memory device (100) or semiconductor memory device (100) (not shown) host in buffering data that can be sent can be used.

Memory number control unit (220) device for defect (100) read operation of, program operation, erase operations, and the background (background) to number consists of operation under [e. Memory number control unit (220) for defect device (100) consists of a number for the firmware (firmware) to drive.

Memory number control unit (220) includes a physical page number (FTL) host via a physical block address (physical block address, PBA) is the performance of a logical block address (logical block address, LBA) can be converted into. Specifically, the physical page (FTL) using logical block address (LBA) from the mapping table, physical block address (PBA) can be transformed into. Physical block address of a memory cell array (110) that defines page number be a particular word line. Various physical page address mapping method is mapping unit according flow tides. A representative address mapping method is page mapping method (Page mapping method), block mapping method (Block mapping method), and the pin is mixed mapping method (Hybrid mapping method).

Error correction code circuit (230) is in parity error correction code for data to be program (Error Correction Code; ECC) produce. In addition engine, error correction code circuit (230) is read page data using parity error correction can be. Error correction code circuit (230) LDPC (low density parity check) is code, BCH (Bose, Chaudhri, Hocquenghem) Code, turbo code, lead - Solomon code (Reed a-Solomon code), convolution code, RSC (recursive systematic code), TCM (trellis-a coded modulation), BCM (Block coded modulation), such as Hamming code (hamming code) can be correcting errors using coordinate set (coded modulation) modulation.

Read operation, error correction code circuit (230) is for error correcting page data can be read. Corrected read page data exceeds the number of bits which can be failed when decoding error bit are included. Error bit are included in a number of possible bit correction to page data when decoding can be less than or equal to succeed.

The success of the pass (pass) exhibits corresponding read command has been decoded. Of a decoder failure (fail) is changed to a corresponding read command fails by a goniophotometer. Success are decoded when controller (200) errors corrected page data is output to the host.

Even thought it does not drawing is shown, controller (200) for defect device (100) to communicate with a further comprises memory can be. Memory interface includes a semiconductor memory device (100) comprising a protocol to communicate with. For example, NAND memory interface (NAND) interface, such as interface nor (NOR) comprising at least one flash interfaces can.

In addition, controller (200) host and controller (200) for performing data exchanges between the host can be further comprises. The host interface and controller (200) comprises a protocol for communicating between. Illustratively, controller (200) includes a USB (Universal Serial Bus) protocol, MMC (multimedia card) protocol, PCI (peripheral component interconnection) protocol, PCI-a E (PCI-a express) protocol, ATA (Advanced Technology Attachment) protocol, Serial-a ATA protocol, Parallel provided ATA protocol, SCSI (smallcomputer small interface) protocol, ESDI (enhanced small disk interface) protocol, and IDE (Integrated Drive Electronics) protocol such as communicates with outside through at least one of various interface protocol (host) to consists of.

Figure 2 shows a example of the present invention embodiment according to semiconductor memory device 06 block also are disclosed.

Figure 3 shows a memory cell array (110) indicating the structure of Figure 2 also are disclosed.

The reference 2 also, semiconductor memory device (100) the memory cell array (110) and a peripheral circuit (120, peripheral circuit) having a predetermined wavelength.

Memory cell array (110) comprises a plurality of memory blocks comprise (BLK1 provided BLKz). Plurality of memory blocks (BLK1 provided BLKz) (RL) row lines through address decoder (121) connected, through bit lines (BL1 provided BLm) read and write circuit (123) is connected thereto. Each of the plurality of memory blocks includes the plurality of memory cells (BLK1 provided BLKz). In one example embodiment, a plurality of memory cells are non-volatile (nonvolatile) memory cell oxide inclusion content.

Memory cell array (110) according to a plurality of memory cells included in these divided into a plurality of blocks can be used.

In one embodiment, memory cell array (110) of Figure 1 is cam (Content Addressable Memory, CAM) region (111) can be comprising. Cam region (111) has at least one memory block can be a reading unit memory cells. Cam region (111) can be cam block corresponding to the memory block. Cam block includes a memory blocks at least one of block (BLK1 provided BLKz) can be. Cam block includes a memory blocks and may have is the same in structure. Cam region (111) is semiconductor memory device (100) can be stored in the setting of an. Specifically cam region (111) predetermined conditions related to the operation of the status or other information can be stored. In one embodiment, cam region (111) (P/E Cycle) number is read/write embodiment, defective column address, a defective block address information can be stored. In one embodiment, cam area (111) is semiconductor memory device (100) in order to operate is options information, e.g. program voltage information, read voltage information, erase voltage information or cell gate oxide thickness information can be stored. In one embodiment, cam region (111) can be the repair information is stored.

According to the example of the present invention embodiment, cam area (111) is semiconductor memory device is a read operation required for discharging a plurality of lines (tref1) reference time number 1 and number 2 (tref2) reference time information can be stored.

A semiconductor memory device number 1 reference time (tref1) selected word line voltage reaches the time be a pass voltage (Vpass).

The memory cell array of a semiconductor memory device number 2 reference time (tref2) select line (DSL, SSL) is be a discharge time. I.e., select line (DSL, SSL) reaches the ground voltage (GND) voltage can be time.

Number 1 to number z memory blocks the number 1 to number m bit lines (BL1 provided BLm) (BLK1 provided BLKz) common connected thereto. Number 1 to number z memory blocks (BLK1 provided BLKz) comprising the plurality of cell strings. A plurality of cell strings each number 1 to number m bit lines (BL1 provided BLm) coupled with each other.

In Figure 3, descriptions and to receive the plurality of memory blocks included in one memory block number 1 (BLK1 provided BLKz) (BLK1) elements are shown, the remaining memory blocks included in each dispensed elements (BLK2 provided BLKz) are disclosed. (BLK2 provided BLKz) remaining memory blocks each memory block number 1 (BLK1) is made from a will as well as it will.

(BLK1) memory block comprises a plurality of cell strings (CS11 - CS1m, CS21 - CS2m). Number 1 to number m number 1 to number m bit lines (BL1 provided BLm) each cell strings (CS11 - CS1m) coupled with each other.

Number 1 to number m cell strings (CS11 - CS1m) each selectively (DST), and the source select transistor (SST) is connected in series to a plurality of memory cells (MC1 provided MCn) without using a tool. Selectively (DST) is selectively line (DSL1) coupled with each other. Number 1 to number n memory cells (MC1 provided MCn) number 1 to number n word lines (WL1 provided WLn) respectively coupled with each other. The source select transistor (SST) (SSL1) comprises a source selection line is connected thereto. Selectively (DST) at the drain side of corresponding bit line is connected thereto. Number 1 to number m cell strings (CS11 - CS1m) number 1 to number m bit lines (BL1 provided BLm) of each of the selectively coupled with each other. The source select transistor (SST) common source line (CSL) source side of coupled with each other. As an example embodiment, the common source line (CSL) number 1 to number z memory blocks are connected commonly (BLK1 provided BLKz) can be.

Selectively line (DSL1), number 1 to number n word lines (WL1 provided WLn), and the source select line (SSL1) of Figure 1 to the row lines (RL) multiple myelomas are included. Selectively line (DSL1), number 1 to number n word lines (WL1 provided WLn), and the source select line (SSL1) an address decoder (121) encoded by the number. The common source line (CSL) is logic number (125) encoded by the number. Number 1 to number m bit lines (BL1 provided BLm) includes a read and write circuit (123) encoded by the number.

The reference 2 also again, peripheral circuit (120) decoder addresses (121), voltage generator (122), read and write circuit (123), test control circuit (124) and the logic number (125) comprises. Address decoder (121) rows and lines (RL) memory through the cell array (110) is connected thereto. Address decoder (121) is the logic number (125) number of response to operate consists of an opposite side. Address decoder (121) is the logic number (125) address (ADDR) through receives a.

Example embodiment, semiconductor memory device (100) are provided to a program operation and reading operation is carried out. Program operation and reading operation, address (ADDR) is block address and the row address are disclosed.

Address decoder (121) of received address (ADDR) consists of one block address decode. Address decoder (121) is decoded block address for memory blocks (BLK1 provided BLKz) selects one of the memory blocks.

Address decoder (121) of received address (ADDR) consists of one row address decode. Address decoder (121) is decoded row address according to the voltage generator (122) number ball it received from selected memory block row lines by applying voltages (RL) selects word line.

Program operation, address decoder (121) program applies a voltage to the selected word line selecting word lines are disclosed apply the pass voltage lower than the program voltage. During a program verify operation, address decoder (121) applies a voltage to the selected word line selecting word lines verifying verification pass capable of applying a voltage higher than verify voltages are disclosed.

Engine, address decoder (121) the read voltages are applied to the selected word line, the read voltages higher than one pass capable of applying a voltage selecting word lines are disclosed.

Example embodiment, semiconductor memory device (100) erase operations carried out in the plurality of memory blocks. Address (ADDR) erase operation of a block address without using a tool. Address decoder (121) which decodes the address block, according to one decoded block address selects the memory blocks.

Example embodiment, address decoder (121) block decoder, address buffer can be word line decoder and the like.

Voltage generator (122) for defect device (100) consists of a plurality of voltage to generate a voltage supplied to an external power supply. Voltage generator (122) is the logic number (125) in response to an opposite side of number and operate.

Embodiment example, voltage generator (122) comprises an outer power supply voltage can be regulated by internal power supply voltage. Voltage generator (122) internal power supply voltage generated in a semiconductor memory device (100) are used as the operating voltage of the.

Embodiment example, voltage generator (122) port of external power supply voltage or plurality of voltages can be generated. For example, voltage generator (122) for receiving a plurality of pumping capacitors and inner power supply voltage, the logic number (125) in response to a number of opposite pumping capacitors selectively activating voltages and a plurality of voltages are disclosed. Generates voltages are address decoder (121) are applied to selected by the word line.

Read and write circuit (123) is number 1 to number m page buffers comprises (PB1 provided PBm). Number 1 to number m page buffers each number 1 to number m bit lines (BL1 provided BLm) (PB1 provided PBm) through memory cell array (110) is connected thereto. Number 1 to number m page buffers (PB1 provided PBm) number is the logic (125) in response to an opposite side of number and operate.

The number 1 to number m page buffers (PB1 provided PBm) test control circuit (124) data and communication to each other. When program, the number 1 to number m page buffers (PB1 provided PBm) test control circuit (124) and data lines (DL) data (DATA) via receives a.

Program operation, number 1 to number m page buffers (PB1 provided PBm) program pulse is applied to a selected word line, data include data input output circuit (DATA) (124) (DATA) through bit lines (BL1 provided BLm) the received data through the memory cells is determined to be disclosed. (DATA) selected according to the transferred data to a page of memory cells are programmed. Program voltage tolerant (for example, ground voltage) applied bit line connected to the memory cell threshold voltage have raised are disclosed. Program inhibit voltage (for example, power supply voltage) is applied to a bit line of the memory cell threshold voltage is maintained will. During a program verify operation, number 1 to number m page buffers selected from memory cells (PB1 provided PBm) bit lines (BL1 provided BLm) read through page data.

Read operation, read and write circuit (123) from a page of memory cells selected as the bit lines (BL) (DATA) data via a reading or writing, from a read data input circuit (DATA) (124) output to the.

Erase operation, read and write circuit (123) (floating) floating bit lines (BL) is capable of.

Test control circuit (124) causes the lines (DL) number 1 to number m (PB1 provided PBm) through page buffers coupled with each other. Test control circuit (124) is the logic number (125) in response to an opposite side of number and operate. When program, test control circuit (124) comprises an outer controller (not shown) data from storage (DATA) receives a.

Test control circuit (124) is read operation, read and write circuit (123) number 1 to number m page buffers included in an output to the external controller transferred data from (PB1 provided PBm).

The logic number (125) an address decoder (121), voltage generator (122), read and write circuit (123) and circuit (124) coupled with each other. The logic number (125) a semiconductor memory device (100) number [e[e] it will do be enclosed by a protective operation. The logic number (125) command from the external controller (CMD) and address (ADDR) receives a. The logic number (125) address decoder in response to the command (CMD) (121), voltage generator (122), read and write circuit (123) and circuit (124) to a number consists of under [e. The logic number (125) address decoder address (ADDR) (121) delivers to.

According to the example of the present invention embodiment, the logic number (125) a semiconductor memory device (100) is energized, cam region (111) stored information weep-off gate.

In one embodiment of the present invention embodiment, the logic number (125) includes a read word lines during operation selected lines cam region (111) read from number 1 and number 2 (tref2) reference time (tref1) reference time according can be discharging.

The logic number (125) includes a read operation selected word line pass voltage (Vpass) discharge section adapted for applying voltage generator (122) of address decoder (121) is a number etched.

The logic number (125) after applying a selected word line pass voltage (Vpass) reference time (tref1) number 1 key, select line (DSL, SSL) can be discharging. The logic number (125) (tref1) reference time the number 1 key, select line (DSL, SSL) ground voltage to a voltage generator (122) of address decoder (121) [e[e] it will do be a number.

The logic number (125) selected lines (DSL, SSL) cross wall of a reference time (tref2) number 2 key, memory cell array (110) of word lines can be discharging. The logic number (125) is, number 2 (tref2) reference time from another, word lines word lines for discharging the ground voltage to a voltage generator (122) of address decoder (121) [e[e] it will do be a number.

The logic number (125) (tref1) reference time the number 1 and number 2 (tref2) reference time lapse of at least one counter circuit for can be determined.

Again, the reference also 3, memory cell array (110) comprises a plurality of memory blocks comprise (BLK1 provided BLKz). In Figure 3, for facilitating recognition number 1 (BLK1) are shown in the configuration of the memory block, the remaining memory blocks (BLK2 provided BLKz) internals dispensed in the nanometer range. (BLK1) number 1 to number 2 number z memory blocks (BLK2 provided BLKz) will also is made from a memory block as well as it will.

The reference number 1 memory block 3 also includes a plurality of cell strings (CS11 - CS1m, CS21 - CS2m) (BLK1) comprises. Example embodiment, each of the plurality of cell strings (CS11 - CS1m, CS21 - CS2m) 'U' can be of the upper portion. Number 1 in memory block (BLK1), m is the row direction (i.e. + X direction) of cell strings are prevented. In Figure 3, 2 (i.e. + Y direction) of cell strings arranged in row direction is found is also shown. For facilitating description but provided 3 column direction which produces one or more cell strings can be arranged it will will.

A plurality of cell strings (CS11 - CS1m, CS21 - CS2m) are at least one the source select transistor (SST), number 1 to number n memory cells (MC1 provided MCn), pipe transistor (PT), and at least one selectively comprises (DST).

(SST, DST) selectively and memory cells (MC1 provided MCn) may have each device comprises a similar structure. Example embodiment, each channel layer selectively (SST, DST) and memory cells (MC1 provided MCn), tunneling insulation layer, and a blocked charge storage can be insulating. Embodiment example, pillar (pillar) number under public affairs channel layer for each cell strings to 1308. ball number (each cell string). Example embodiment, channel layer, the tunneling insulation layer, and at least one charge storage isolation layer number for each cell string under public affairs pillar is 1308. ball number.

A common source line (CSL) and each cell string the source select transistor (SST) between memory cells (MC1 provided MCp) coupled with each other.

Example embodiment, arranged cell strings of the source select transistor are the same row source selection line connected to the column direction, different row arranged cell strings of the source select transistor at different source select lines coupled with each other. In Figure 3, number 1 row of cell strings (CS11 - CS1m) number 1 source selection line (SSL1) of the source select transistor are connected to disclosed. Number 2 row cell strings (CS21 - CS2m) number 2 source selection line (SSL2) of the source select transistor are connected to disclosed.

In another embodiment example, cell strings (CS11 - CS1m, CS21 - CS2m) of the source select transistor are mounted to one of the source select line can be the driver.

Each cell string number 1 to number n memory cells (MC1 provided MCn) (SST) (DST) on selectively between the source select transistor is connected thereto.

The number 1 to number p number 1 to number n memory cells (MC1 provided MCn) memory cells (MC1 provided MCp) and number p + 1 to number n memory cells can be divided into (MCp + 1 provided MCn). Number 1 to number p memory cells (MC1 provided MCp) sequentially arranged in the opposite direction to the + Z, the source select transistor (SST) between the pipe transistor (PT) series connected thereto. The number p + 1 to + Z direction arranged in a sequential number n memory cells (MCp + 1 provided MCn), pipe transistor (PT) (DST) on selectively between series connected thereto. Number 1 to number p memory cells (MC1 provided MCp) and number p + 1 to number n memory cells connected thereto through pipe transistor (PT) (MCp + 1 provided MCn). Each cell string number 1 to number n number 1 to number n memory cells (MC1 provided MCn) gates each word lines (WL1 provided WLn) coupled with each other.

Example embodiment, at least one of the number 1 to number n memory cells (MC1 provided MCn) can be used as dummy memory cells. Dummy memory cell when the ball number, the number of the voltage or current corresponding cell strings stably can be disclosed. , the reliability of data stored in the memory block (BLK1) is improved.

Each cell string pipe transistor the gate of the pipeline (PL) (PT) coupled with each other.

Each cell string selectively (DST) between corresponding bit line memory cells (MCp + 1 provided MCn) coupled with each other. Row cell strings arranged in row directions extended in the direction of the drain select line coupled with each other. The drain select line number 1 row of cell strings (CS11 - CS1m) number 1 (DSL1) of selectively coupled with each other. The drain select line number 2 number 2 row cell strings (CS21 - CS2m) (DSL2) of selectively coupled with each other.

In the column direction bit line extended in the direction of cell strings can heat-coupled with each other. In Figure 4, the bit line (BL1) number 1 number 1 row of cell strings (CS11, CS21) connected to disclosed. The number m bit line (BLm) number m of rows of cell strings (CS1m, CS2m) connected to disclosed.

Identical in cell strings arranged in row directions word lines connected to memory cells one fixed substrate. For example, number 1 row of cell strings (CS11 - CS1m) number 1 (WL1) word line connected to the memory cells are one of fixed substrate. Number 2 row cell strings (CS21 - CS2m) number 1 of the other memory cells are connected to word line (WL1) is fixed substrate. Selectively lines (DSL1, DSL2) is selected either by one row of selected cell strings as a sheet are disclosed. Word lines (WL1 provided WLn) selected by either is selected cell one of the selected page are disclosed.

Figure 4 shows a memory cell array (110) other embodiment showing the example of Figure 2 also are disclosed.

The reference also 4, memory cell array (110) comprises a plurality of memory blocks comprise (BLK1 '- BLKz'). In Figure 4, for facilitating recognition number 1 (BLK1 ') are shown in the configuration of the memory block, the remaining memory blocks (BLK2' - BLKz ') internals dispensed in the nanometer range. Number 1 to number 2 number z memory blocks (BLK2 '- BLKz') as well as memory block (BLK1 ') will also is made from a will.

(BLK1 ') number 1 memory block comprises a plurality of cell strings (CS11' - CS1m ', CS21' - CS2m '). A plurality of cell strings (CS11 '- CS1m', CS21 '- CS2m') extends along each of the + Z direction with each other. Number 1 in memory block (BLK1 '), m + X direction of the cell strings are prevented. In Figure 4, 2 + Y direction of cell strings arranged in is also shown. For facilitating description but provided 3 column direction which produces one or more cell strings can be arranged it will will.

Each of the plurality of cell strings (CS11 '- CS1m', CS21 '- CS2m'), at least one the source select transistor (SST), number 1 to number n memory cells (MC1 provided MCn), and at least one selectively (DST) without using a tool.

A common source line (CSL) and each cell string the source select transistor (SST) between memory cells (MC1 provided MCn) coupled with each other. Arranged cell strings of the source select transistor may be on the same row source selection line is connected thereto. Row number 1 arranged cell strings (CS11 '- CS1m') number 1 source selection line (SSL1) of the source select transistor are coupled with each other. Row number 2 arranged cell strings (CS21 '- CS2m') of the source select transistor source select line (SSL2) number 2 are coupled with each other. In another embodiment example, cell strings (CS11 '- CS1m', CS21 '- CS2m') of the source select transistor are mounted to one of the source select line can be the driver.

Each cell string number 1 to number n memory cells (MC1 provided MCn) (SST) and selectively between the source select transistor (DST) series connected thereto. Number 1 to number n memory cells (MC1 provided MCn) number 1 to number n word lines (WL1 provided WLn) gates each coupled with each other.

Example embodiment, at least one of the number 1 to number n memory cells (MC1 provided MCn) can be used as dummy memory cells. Dummy memory cell when the ball number, the number of the voltage or current corresponding cell strings stably can be disclosed. The reliability of data stored in the memory block (BLK1 ') is improved.

Each cell string selectively (DST) which receives between bit line memory cells (MC1 provided MCn) coupled with each other. These rows of cell strings arranged in row directions selectively extended in the direction of the drain select line coupled with each other. Number 1 row of cell strings (CS11 '- CS1m') of selectively drain selection line (DSL1) number 1 are coupled with each other. Number 2 row cell strings (CS21 '- CS2m') of selectively drain selection line (DSL2) number 2 are coupled with each other.

As a result, it was outside the number is a number of Figure 4 each cell string pipe transistor (PT) (BLK1 ') of Figure 3 is similar under the outside memory block memory block (BLK1) has an equivalent.

Figure 5 shows a voltage applied to each line indicating the engine also are disclosed.

Figure 6 shows a phenomenon that when the voltage is applied to explain agent of of Figure 5 are disclosed.

Read operation of semiconductor memory device access attempt to memory cell state (status) of the memory cell address (accessing) sensing behavior. Read operation program memory cells whether erase (erasure) whether, when a program state of the programmed state of any level (level) sensing whether behavior. Program and erase operations program verify (verification) and the erase verification (verification) of a read operation due to all electromagnetic wave is disclosed. The, each example of the present invention embodiment according to verify operation includes a program verify operation on an erase verification operation and may be used to specify other.

The reference also 5, read operation of semiconductor memory device preferably the precharge interval (P1), (P2) and discharging section (P3) can be divided into read section.

The memory cell array in a semiconductor memory device (P1) precharge section connected for each line read applies predetermined voltages.

Precharge interval selected source selection line (SSLsel) (P1) (DSLsel) (Vssl) is selected selectively line source selection voltage drain selection voltage (Vdsl) is applied. The drain selection voltage source select voltage (Vssl) (Vdsl) each selected memory string included in the source select transistor and selectively turn on the base.

Word line setting voltage is selected word line (SELWL) (Vset) can be applied to the disclosed. The word line setting voltage applied to non-selected word lines (Vset) (UNSELWL) such as be a pass voltage (Vpass) voltage level. In various embodiment, word line setting voltage selected word line (SELWL) (Vset) capable of floating. (Vset) word line setting voltage to a selected word line voltage (SELWL) set to read operation are disclosed. The present invention according to operation of the semiconductor memory device according to various word line setting voltage can be applied to the disclosed (variable).

(UNSELWL) is provided with a non-selected word line pass voltage (Vpass) is applied. A memory coupled to the non-selected word line pass voltage (Vpass) (UNSELWL) a voltage to turn on cells are disclosed.

Bit line (BL) is provided with a bit line voltage (VBL) can be applied to the disclosed. Bit line voltage (VBL) includes a read operation of precharging the bit line (BL) can be.

This bell type a [syen page buffer (PB) after the precharge operation or memory cell bit line (BL) through bit line current sensing operations of the present invention description is level or the specific key feature in the description corresponding to supply dispensed to each other.

In semiconductor memory device read section (P2) the read voltage (Vread) is applied to the selected word line (SELWL) coupled to a selected word line of the memory cells (SELWL) reads out the data stored.

During the source select line and the drain select line read section (P2) (SSLsel) (DSLsel) (UNSELWL) is provided with a precharge interval selected and applied in the word line voltage (P1) being maintained.

The read voltage (Vread) is applied to the selected word line (SELWL).

The potential of the bit line (BL) memory cells connected to the selected word line (SELWL) mode is set in its programmed state (high), low (low) or floating (floating) state may have value.

Discharging section (P3) in semiconductor memory device connected to the memory cell array each line discharging the other.

The reference also 5, semiconductor memory device by applying a pass voltage to the selected word line (SELWL) (Vpass), all of the word lines (equalizing) can be set to the same voltage level. In one embodiment, word line voltage level different values disk disapproval.

T1 point in time, semiconductor memory device includes a reaction chamber discharging the word lines.

6 also reference surface, one memory string is the source select line (SSL) connected to the source select transistors, the source select transistor coupled in series with the and dummy memory cells, dummy memory cells each include a dummy word line (DWL) coupled with each other. Dummy memory cell connected to word lines connected to a plurality of memory cells each xx number 0 (WL00 provided WLXX) can be. A memory coupled to the word line in Figure 6 is for facilitating description number 0 (WL00) cells erased state (PV0) and, a memory coupled to cell number 7 to number 1 word line (WL01) performs the programmed state (PV7) assuming each other. Word lines connected to memory cells are each number 2 to number XX (WL02 provided WLXX) of given program state thereof can reference cells are programmed.

Discharging section (P3) in the field of view occupied discharge t1 of word lines are arranged. At this time, source selection line is the source select voltage applied be a performs the source select transistor is turn-on state. Selectively line is provided with a selectively performs the applied voltage, the transistor selectively be a turning on state. During discharge section (P3) common source line, bit lines and selectively ground voltage is applied. For all word lines begins then scan voltage, the voltage of the ground voltage (GND) word lines in the pass voltage (Vpass) reduces.

Discharging section (P3) word lines in a memory coupled to each word line according to the difference between the threshold voltages (ON)/off (OFF) state amplitude and a s402.

I.e., the threshold voltage of a memory cell connected to word line number 0 (WL00) number 1 (WL01) when less than the threshold voltage of memory cells connected to the word line, a memory coupled to word line number 1 (WL01) channel is first before reaching the off (OFF) state. High threshold voltage memory cells channel having low threshold voltage memory cells may be delivered off the channel (OFF) state is achieved, high threshold voltage of memory cells having a low threshold voltage boundary present in memory cells be a discharge channel is in operation floating (floating) state. The off state (OFF) local boosting (Local Boosting) can be delamination occurs between channels.

The local boosting (Local Boosting) States, depending on the difference between the ground voltage (GND) bit line or source line number 2 with number 0 in word line (WL0) word line (WL02) hot carrier injection (HCI) towards channel channel can be delamination occurs. The, number 0 word line (WL0) connected to the memory cell erased state (PV0) despite that would yield a threshold voltage can be increased. This read disturb (read disturbance) to the sense amplifier circuit cannot assure the reliability of device memory to be coated.

In Figure 6 comprises a source selection transistor, selectively (not shown) and a dummy memory cell included in the memory string 1 shown but each one by one, embodiment embodiment the source select transistor, a dummy memory cell and selectively each comprising a plurality (not shown) can be.

Figure 7 shows a method of the present invention embodiment operation of the semiconductor memory device according to example to explain surface also are disclosed.

Embodiment of Figure 7 embodiment, precharge interval (P1) (P2) in the operations of the operation of the semiconductor memory device and read section in Figure 6 are the same.

According to the example of the present invention embodiment, semiconductor memory device discharging section (P3) is selected lines (SSL, DSL) than after discharging the first word line, word lines discharging substrate.

Discharging section (P3) in semiconductor memory device by applying a pass voltage to the selected word line (SELWL) (Vpass), all of the word lines is set to the same substrate (equalizing) voltage level. In various embodiment of semiconductor memory device in a semiconductor memory device can be disk weight parts.

(SELWL) (Vpass) passed to the selected word line voltage applied behind, reference time (tref1) number 1 key (t3), semiconductor memory device the selected lines (SSLsel, DSLsel) discharging the other. Semiconductor memory device for discharging the selected lines (SSLsel, DSLsel) capable of applying voltages to the select line (SSLsel, DSLsel) 2000.

Number 1 (tref1) reference time selected word line voltage (SELWL) reaches the paper to be a pass voltage (Vpass).

In various embodiment, select line (SSLsel, DSLsel) without simultaneously discharging, the source select line (SSL) or drain selection line (DSL) can be first discharging either. The selected word line voltage (SELWL) or semiconductor memory device changing a pass voltage (Vpass) without performing an equalizing operation, discharging section (P3) can be discharging directly select line (SSLsel, DSLsel).

Semiconductor memory device for discharging the selected lines after startup, number 2 (tref2) reference time key (t4), word lines can be discharging. Semiconductor memory device includes a word lines for discharging the selected word line (SELWL) and the non-selected word line (UNSELWL) be capable of applying a voltage to ground.

Number 2 (tref2) reference time is selected lines (SSLsel, DSLsel) be a discharge time. I.e., selectively (SST, DST) is turned off it would be a time.

In various embodiment, word lines while not start of discharging, with reference to the bit line or source line sequentially from the discharging either can be located distally of the word lines. Or a plurality of word lines is divided into at least one word line group, either sequentially from the bit line or source line adjacent word line group can be discharging.

Number 1 and number 2 (tref2) reference time (tref1) reference time information about cam (CAM) stored in a selected memory cell array can be disclosed. Semiconductor memory device includes a power source is supplied, from a reference time (tref1) number 1 and number 2 cam (tref2) reads out the reference time according to the example of Figure 7 embodiment can be discharge operation.

Figure 8 shows a example of the present invention embodiment of semiconductor memory device according to an order for operation also are disclosed.

The reference also 8, step S810, semiconductor memory device selected as the word line read voltage (Vread) and the amount, selecting word line pass voltage (Vpass) may apply. S810 semiconductor memory device via a plurality of memory cells connected to the selected word line read process for performing.

S820 step, semiconductor memory device in a semiconductor memory device and selection line discharge operation for a plurality of hierarchies. S820 step discharging operation through 9 also subjected to the corresponding business are provided as follows.

Figure 9 shows a discharging order of Figure 8 exhibit also are disclosed.

The reference also 9, semiconductor memory device is in S910, selected word line pass voltage (Vpass) capable of applying disclosed. S910 word line voltage level is supplied to all the semiconductor memory device pass voltage (Vpass) control substrate. In various embodiment, S910 of equalizing step can be avoided. S910 if performed without omission of step S920, S930 step can be performed immediately.

S920 step, semiconductor memory device includes a reference time can be the publisher number 1. A semiconductor memory device number 1 reference time selected word line voltage reaches the time be a pass voltage (Vpass).

S920 result in reference number 1 key, processing continues to a step S930.

S930 step, semiconductor memory device the selected lines discharging the other. The source select line (SSL) select line and the drain select line (DSL) implementation being. Semiconductor memory device for discharging the selected lines selected ground lines be capable of applying a voltage. In various embodiment, select line simultaneously without discharging, the source select line (SSL) or drain selection line (DSL) can be first discharging either.

S940 step, semiconductor memory device reference number 2 can determine whether the time period has lapsed. The memory cell array of a semiconductor memory device number 2 reference time select line (DSL, SSL) is be a discharge time. Select line (DSL, SSL) be a ground voltage (GND) voltage reaching time.

S940 processes result in reference number 2, processing continues to a step S950.

S950 the semiconductor memory device the selected word line and the non-selected word lines discharging substrate.

In various embodiment, step S950 without simultaneously in the discharge of the word lines, with reference to the bit line or source line either can be sequentially from discharging located distally of the word lines. Or a plurality of word lines is divided into at least one word line group, either sequentially from the bit line or source line adjacent word line group can be discharging.

According to the example of the present invention embodiment, locking device read operation or a verify operation command word lines can be selected lines prior to discharging. According to the example of the present invention embodiment, the programmed state is a melody memory cells prevent partial local boosting, preventing disturbance can be read through.

Figure 10 shows a semiconductor memory device including memory system of Figure 2 is shown a block also are disclosed.

The reference also 10, memory system (1000) a semiconductor memory device (1300) and controller (1200) having a predetermined wavelength.

Semiconductor memory device (1300) is described with reference to the semiconductor memory device also 1 (100) in the same manner as on which, can be operating. Hereinafter, redundant description dispensed with each other.

Controller (1200) host (Host) and semiconductor memory device (1300) is connected thereto. In response to a request from host (Host), controller (1200) device for defect (1300) consists of to access. For example, controller (1200) device for defect (1300) of lead, program, erase, and the background (background) to number consists of operation under [e. Controller (1200) device for defect (1300) and host (Host) number to interface between under public affairs consists of. Controller (1200) device for defect (1300) to drive consists of a number for the firmware (firmware).

Controller (1200) includes a ram (1210, Random Access Memory), processing unit (1220, processing unit), host interface (1230, host interface), memory interface (1240, memory interface) and error correction block (1250) comprises.

Ram (1210) processing unit (1220) operation of memory, semiconductor memory device (1300) and host (Host) between the cache memory, the semiconductor memory device (1300) and host (Host) used as at least one of buffer memory between 2000.

Processing unit (1220) includes the controller (1200) decodes the number of semi operation number.

Processing unit (1220) to mentioned acquires consists of data received from host (Host). For example, processing unit (1220) rendering the crystallization seed (seed) acquires the e will do the [cu using data received from the host (Host) are disclosed. The e became the [cu the data rendering data (DATA, also 1 reference) as semiconductor memory device (1300) to ball number to memory cell array (110, also reference 1) is programmed to.

Processing unit (1220) a lead operation semiconductor memory device (1300) to d LAN compared to E [cu[cu] consists of data received from. For example, processing unit (1220) d lan compared to e ising seed using the semiconductor memory device (1300) d LAN compared to the E will do the [cu[cu] data received from are disclosed. D lan compared to the e became the [cu data are output to the (Host) are disclosed.

Example embodiment, processing unit (1220) software (software) or firmware (firmware) and d lan compared to e [cu driving the mentioned rendering can be performed.

Host interface (1230) host (Host) and controller (1200) for performing data exchanges between the protocol comprises. In an exemplary embodiment example, controller (1200) is USB (Universal Serial Bus) protocol, MMC (multimedia card) protocol, PCI (peripheral component interconnection) protocol, PCI-a E (PCI-a express) protocol, ATA (Advanced Technology Attachment) protocol, Serial-a ATA protocol, Parallel provided ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, and IDE (Integrated Drive Electronics) protocol, such as two parallel metallic plates (private) protocol communicates with the host via at least one of various interface protocol (Host) to consists of.

Memory interface (1240) device for defect (1300) interfacing and etched. For example, the memory interface comprising NAND interface or nor interface.

Error correction block (1250) semiconductor memory device using an error correction code (ECC, Error Correcting Code) (1300) apparatus for detecting error of data received from, consists of correct.

Controller (1200) and semiconductor memory device (1300) can be integrated into one semiconductor device. In an exemplary embodiment example, controller (1200) and semiconductor memory device (1300) to be integrated into one semiconductor device, the memory card can be disclosed. For example, controller (1200) and semiconductor memory device (1300) is one semiconductor device to be integrated into the PC card (PCMCIA, personal computer memory card international association), compact flash card (CF), smart media card (SM, SMC), memory stick, multimedia card (MMC, RS-a MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), universal flash memory device such as memory card (UFS) configure a disclosed.

Controller (1200) and semiconductor memory device (1300) constituting the one semiconductor device can be integrated into the semiconductor drive (SSD, Solid State Drive). Semiconductor drive (SSD) storage device configured to store data for defect without using a tool. Memory system (1000) when used as semiconductor drive (SSD), memory system (1000) host apparatus connected to the operation of a refinery (Host) rejections.

As another example, memory system (1000) computer, UMPC (Ultra Mobile PC), workstation, net book (net-a book), PDA (Personal Digital Assistants), portable (portable) computer, web tablet (web tablet), wireless telephone (wireless phone), mobile phone (mobile phone), smart phone (smart phone), e - book (e-a book), PMP (portable multimedia player), portable game machine, navigation device (navigation), black box (black box), digital camera (digital camera), said be 3 dimensional (3 a-dimensional television), digital voice recorder (digital audio recorder), (digital audio player) digital voice player, digital video recorder (digital picture recorder), (digital picture player) digital video player, digital moving picture recorder (digital video recorder), digital moving picture player (digital video player), the device can receive information in a wireless environment, constituting one of the home electronic device, electronic device constituting the one computer network, constituting one of the telematics network electronic device, RFID device, or computing system constituting the one electronic device components such as various configurations of elements encoded number one ball.

In an exemplary embodiment example, semiconductor memory device (1300) or memory system (1000) in various forms of package may be mounted disclosed. For example, semiconductor memory device (1300) or memory system (1000) is PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline integrated circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi-a Chip Package (MCP), Wafer-a level Fabricated Package (WFP), (WSP) Wafer provided Level Processed Stack Package manner such as packaged may be mounted disclosed.

Figure 11 shows a memory system (1000) of applications (2000) 06 block of Figure 10 also are disclosed.

The reference also 11, memory system (2000) a semiconductor memory device (2100) and controller (2200) without using a tool. Semiconductor memory device (2100) comprises a plurality of semiconductor memory chip includes the. A plurality of semiconductor memory chips are grouped into a plurality of divided.

In Figure 11, each of which comprises a plurality of groups of number 1 to number k channels (CH1 provided CHk) through controller (2200) is illustrated communicates over. Each semiconductor memory chip has also 1 described with reference to semiconductor memory device (100) is made up of a similar one, operation will.

Each group one via the common channel controller (2200) to communicates with consists of. Controller (2200) 10 is also described with reference to controller (1200) in the same manner as on consisting of, semiconductor memory device through a plurality of channels (CH1 provided CHk) (2100) to number under [e consists of a plurality of memory chips.

In Figure 11, one channel is provided with a plurality of semiconductor memory chips been demonstrated. However, one channel one semiconductor memory chip to be joined and memory system (2000) deforms it will will viscoelastic materials.

Figure 12 shows a memory system described with reference to also also 11 (2000) including a computing system (3000) is shown block are disclosed.

The reference also 12, computing system (3000) includes a central processing device (3100), ram (3200, RAM, Random Access Memory), user interface (3300), power (3400), system bus (3500), the memory system (2000) comprises.

Memory system (2000) system bus (3500) through, central processing device (3100), ram (3200), user interface (3300), and a power source (3400) electrically connected thereto. User interface (3300) number through ball or, central processing device (3100) processing by the data memory system (2000) overnight.

In Figure 12, semiconductor memory device (2100) weight factor (2200) through system bus (3500) is connected to an shown in the nanometer range. However, semiconductor memory device (2100) has a bus (3500) can be configured to be coupled directly. The, controller (2200) the function of the central processing device (3100) and ram (3200) performed by will.

In Figure 12, also 11 described with reference to memory system (2000) where ball number is shown disclosed. However, memory system (2000) also 11 described with reference to the memory system (1000) can be replaced. Example embodiment, computing system (3000) 10 and 11 also is also described with reference to memory systems (1000, 2000) can be configured to include both.

Although the present invention refers to defined on one embodiment than described by the drawing but, limited to embodiment of the present invention refers to said example has the, from the substrate in the present invention if the person with skill in the art various modifications and flawless deformable disclosed.

Therefore, of the present invention does not require any limited in range described embodiment example and not, as well as the carry evenly defined by claim claim on others should.

Examples include the above-described embodiment, all steps to be selectively performed or omitted can be subjected to. In addition steps must occur in each embodiment and need not order, can be 2q2p. On the other hand, the specification to specification on the drawing disclosure of the embodiment examples with the instant specification specification technique to aid in the understanding of a particular instance of an alarm of the SFC may timing number is received, or limit the scope of the specification that is even endured. I.e. the specification technical idea that are based on another version of this is in the art plan examples embodiment belongs to reduced specification person with skill in the art are disclosed.

On the other hand, the specification of the present invention in a preferred embodiment for example is on when the drawing disclosure, although specific terms are used but, this technique of the present invention to aid in the understanding of the invention and are described only an alarm is employed for the generic sense not, or limit the scope of the present invention that is even endured. Example embodiment of the present invention that are based on the disclosure herein in addition another version the technical idea is provided to the person with skill in the art in enabling the present invention to reduced examples embodiment are disclosed.