ПРОГРАММИРУЕМОЕ ПОСТОЯННОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО С УЛУЧШЕННЫМ ВРЕМЕНЕМ ВЫБОРКИ

Изобретение относится к программируемым постоянным запоминающим устройствам типа электрически стираемого ПЗУ (ЭСППЗУ). Техническим результатом является создание ЭСППЗУ с быстрым стиранием, причем, используя данное ЭСППЗУ при любом времени выборки, возможно однозначное считывание из него данных. Устройство содержит запоминающий транзистор, транзистор выбора, разрядную шину, шину слов, средство (FSU), предназначенное для формирования напряжения считывания в зависимости от частоты тактового сигнала. 3 з.п.ф-лы, 4 ил.

МЕМРИСТОРНЫЙ ЭЛЕМЕНТ ПАМЯТИ

Изобретение относится к микроэлектронике. Мемристорный элемент памяти содержит подложку с расположенным на ее рабочей поверхности проводящим электродом. На указанном проводящем электроде выполнен активный слой из диэлектрика. Второй проводящий электрод расположен на активном слое. Проводящий электрод, расположенный на рабочей поверхности, и/или второй проводящий электрод выполнены из металла. В качестве диэлектрика активного слоя взят оксид металла, из которого выполнен соответственно проводящий электрод, расположенный на рабочей поверхности, и/или второй проводящий электрод. В результате обеспечивается снижение напряжения перепрограммирования, а также снижение потребляемой на перепрограммирование мощности. 13 з.п. ф-лы, 1 ил.

ФЛЭШ-НАКОПИТЕЛЬ, ХАРАКТЕРИЗУЮЩИЙСЯ ФОРМОЙ, ПОЗВОЛЯЮЩЕЙ ИСПОЛЬЗОВАТЬ ПРОСТРАНСТВО ПОЗАДИ МОБИЛЬНОГО УСТРОЙСТВА

Prüfverfahren für programmierbare nicht flüchtige Halbleiterspeichervorrichtung

Nichtflüchtiger Halbleiterspeicher mit elektrisch und gemeinsam löschbaren Eigenschaften

Schaltungsanordnung zum Messen der Schwellenspannungaufteilung von nicht-flüchtigen Speicherzellen

LESEVERSTÄRKER FÜR NICHT-FLÜCHTIGEN HALBLEITERSPEICHER

VERBESSERTES LÖSCHVERFAHREN FÜR EINE DOPPELBIT-SPEICHERZELLE

Verfahren zum Programmieren einer Doppelzellenspeichereinrichtung zur Speicherung von Mehrfach-Datenzuständen pro Zelle

Verfahren zum Programmieren einer dielektrischen Ladungsträgereinfangspeichereinrichtung (6) mit einer ersten Ladungsspeicherzelle (38, 40) benachbart zu einem ersten leitenden Gebiet (16) und einer zweiten Ladungsspeicherzelle (38, 40) benachbart zu einem zweiten leitenden Gebiet (16), mit: Programmieren der ersten Ladungsspeicherzelle, um eine erste Ladungsmenge zu speichern, wobei die erste Ladungsmenge einem ersten Zellendatenzustand entspricht, der ausgewählt ist aus einem leeren Programmierpegel oder einem van mehreren geladenen Programmierpegeln; und Programmieren der zweiten Ladungsspeicherzelle, um eine zweite Ladungsmenge zu speichern, wobei die zweite Ladungsmenge einem zweiten Zellendatenzustand entspricht, der ausgewählt ist aus dem leeren Programmierpegel oder einem der mehreren geladenen Programmierpegeln.

Speicherbauelement, Speichersystem und Löschverfahren

Die Erfindung bezieht sich auf ein Speicherbauelement, vorzugsweise ein nicht-flüchtiges Speicherbauelement, ein Speichersystem, das ein derartiges Speicherbauelement beinhaltet, sowie ein zugehöriges Löschverfahren. Ein Speicherbauelement der Erfindung beinhaltet ein Speicherzellenfeld (110) mit einer Mehrzahl von Zellenstrings auf einem Substrat, wobei sich wenigstens einer der Zellenstrings in einer Richtung weg von dem Substrat erstreckt und eine Mehrzahl von Zellentransistoren beinhaltet, die benachbart zueinander sind, einem Adressendekoder (120), der mit den Zellenstrings verbunden ist, einer Masseauswahlleitung (GSL), Wortleitungen (WL) und Stringauswahlleitungen (SSL), die konfiguriert sind, den Adressendekoder mit den Zellenstrings zu verbinden, einem Lese-/Schreibschaltkreis (130), der mit den Zellenstrings verbunden ist und konfiguriert ist, Daten mit einem externen Bauelement auszutauschen, und einem Spannungserzeugungsschaltkreis (140), der konfiguriert ist, in einem Löschvorgang ...

SPEICHERBLOCKAUSWAHL UNTER VERWENDUNG VON MEHREREN WORTLEITUNGEN ZUR ADRESSIERUNG EINER EINZIGEN SPEICHERZELLENZEILE

Electronic memory circuit

Electronic memory circuit for storing information, in particular switching control information for the optional switching of circuit elements of monolithically integrated semiconductor circuits, having two series connections each comprising an EPROM transistor (E1, E2) and an MOS transistor (M1, M2) connected between the two poles (VDD, GND) of a voltage supply source, the control gates of the two EPROM transistors (E1, E2) being connected jointly to a reference voltage source (REF) and the gates of the two MOS transistors (M1, M2) being connected to the point of connection of the EPROM transistor (E1, E2) and of the MOS transistor (M1, M2) of the other series connection, respectively. ...

Semiconductor device and writing method

A semiconductor device comprising a memory cell array including multi-valued memory cells each having a plurality of different threshold values; a first latch circuit for latching information in input information of multi-words; a second latch circuit for latching write information obtained by converting the information in the input information of the multi-words to information that are in accordance with the levels of the multi-valued memory cells; a write circuit for writing the information into the multi-valued memory cells for each group corresponding to the number of memory cells into which the information can be simultaneously written; and a control circuit for controlling the writing into the memory cell array. Thus, information are simultaneously written for each of the groups into which the input information of the multi-words are divided, so that the write time per unit word can be substantially shortened. In this way, during the writing into the multi-valued memory cells, even ...

Non-volatile memory error mitigation

DEVICE FOR TESTING MEMORY CELLS

A comparator has two inputs, one controlled by a circuit branch including a written cell being examined and one controlled by another circuit branch including a virgin cell. In parallel with the latter is placed another reference cell controlled in an adjustable manner in such a way as to raise the threshold of the written cell which the device is able to discriminate and accept.

Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PROGRAM INPUT EQUIPMENT

READ AMPLIFIER FOR NON VOLATILE INTEGRATED MULTI-LEVEL MEMORY MODULES

PROGRAMMING WITH STRENGTHENED ONE SUBSTRAT/TUB FOR FLASH MEMORY

MULTI-LEVEL PROGRAMMING DURING A NON VOLATILE MEMORY DEVICE

DOUBLE BIT MONOS MEMORY CELL USE FOR WIDTH PROGRAMBANDBREITE

PROCEDURE FOR THE CONTROL NON VOLATILE LOAD INTERFACIAL TRAP MEMORY ARRANGEMENTS AND PROCEDURES FOR THE DETERMINATION OF PROGRAMMING /L ÖSCHPARAMETER

PROCEDURE FOR IDENTIFYING NON VOLATILE MEMORY ELEMENTS WITH WORSE SUBSCHWELLENSTEIGUNG OR WEAK ONES TRANSKONDUKTANZ

PROCEDURE AND SYSTEM FOR PROGRAMMING AND CLOSING FROM NON VOLATILE MEMORY CELLS WITH SEVERAL LEVELS

PROGRAMM-EINGABEGERAET

DEMARCATION LINE ATTITUDE REGARDING DEFECTS IN NON VOLATILE MEMORY

SELECTIVE ENTERPRISE OF A NON VOLATILE MULTI-CONDITION MEMORY SYSTEM IN A COMPRESSED CARD MODE

SEMICONDUCTOR MEMORY CIRCUIT WITH A STRUCTURE OF LOGICAL CIRCUIT FOR EXAMINATION

Flashlaufwerk zur Nutzung des Raums hinter einem Mobilgerät

A flash drive that can utilize space behind a mobile device is disclosed. In some embodiments, a body of the flash drive has three portions, a front portion, a back portion, and an intermediate portion that runs from the front portion to the back portion. A mobile device connector extends from a first end of the front portion, and a second connector extends from a second end of the back portion. The intermediate portion is configured to cause, when the mobile device connector is connected to the mobile device, the second connector and part of the back portion of the body to be located behind and, in some embodiments, adjacent to the back of the mobile device. This can enable part of the body to fit in a gap that can form between the back of the mobile device and a user's palm when the user holds the mobile device.

SPACE ADMINISTRATION IN A NON VOLATILE MEMORY WITH HIGH CAPACITY

PERMANENT MEMORY AND PROCEDURE FOR THE CONTROL OF THE SAME

PROGRAMMABLE NON VOLATILE ZWEIWEGSCHALTER FOR PROGRAMMABLE LOGIC

PROGRAMMING PROCEDURE FOR A NON VOLATILE SEMICONDUCTOR MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

REDUNDANT EEPROM

PROGRAMMABLE MEMORY CELL AND ARRAY

PROGRAMMING NON-VOLATILE MEMORY DEVICES

USING MULTIPLE STATUS BITS PER CELL FOR HANDLING POWER FAILURES DURING WRITE OPERATIONS

PROGRAM INPUT SYSTEM USING A MEMORY CASSETTE

EAROM CELL MATRIX AND LOGIC ARRAYS WITH COMMON MEMORY GATE

EAROM CELL MATRIX AND LOGIC ARRAYS WITH COMMON MEMORY GATE A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line. The logic state stored in the cell is defined by the presence or absence ...

PROGRAMMABLE ACCESS PROTECTION IN A FLASH MEMORY DEVICE

A memory device (100) comprises a memory array (102) having corresponding first access control bits (202, 204) to control access thereto. A second set of access control bits (104) is provided to control write access to the first access control bits. The memory array is divided into memory blocks, each block having a corresponding access control bit. At least one such block (BLK0) is further subdivided into pages, each page having a corresponding control bit.

BISTABILE TRIGGER STAGE WITH FIXABLE SWITCHING STATUS.

Electrically erasable and programmable non-volatile memory cell

The non-volatile memory cell uses field-effect emission for the reading and/or for writing. It consists of a MOS transistor with a floating gate (8), coupled capacitively to a control electrode (9). On the drain (5) side, the floating gate is situated above a well (51) and, on the source (6) side, it is placed above the substrate (1). The regions (3) and (3'), at the silicon-oxide interface below the gate (8), are textured so that the effectiveness of the field-effect mechanism is greatly enhanced. ...

非易失性存储器微机芯片及其测试方法

... 为了提供一种非易失性存储器微机，其中可以省略掉使用逻辑测试器对微机单元进行测试的步骤，因此降低了测试成本。存储器测试器向非易失性存储器微机提供测试数据和期望数据，并且非易失性存储器微机将它们存储到非易失性存储器中。接着，在收到地址信号时，非易失性存储器根据对应于地址信号的测试数据和期望数据输出测试信号和期望信号。测试信号被提供给微机单元中的电路块，用于驱动该电路块。电路块返回测试结果信号，该信号同期望信号一块被输出该存储器测试器。存储器测试器对测试结果信号和期望信号进行比较，以判断微机单元运行是否正常。 ...

Fastening arrangement for replaceable voltage source for electronic price label

Semiconductor nonvolatile memory

In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.

CIRCUIT OF TEST OF CELLS EEPROM

TEST LOOP OF RELIABILITY OF PROGRAMMABLE READ-ONLY MEMORY ERASABLE

Test circuit with several identical cells on a silicon wafer with each cell having an elementary capacity with given characteristics, for use in testing EEPROM cell collections on a single chip

L'invention concerne un circuit de test réalisé sur une plaquette de silicium comprenant une pluralité de cellules identiques (10) dont chacune comporte une capacité élémentaire (C2), de caractéristiques données, qui comprend une capacité de test (C2') de mêmes caractéristiques que chaque capacité élémentaire et de surface au moins égale à la somme des surfaces des capacités élémentaires.

Logic controller for controlling starting of internal combustion engine of motor vehicle, has consultation interface consulting operating parameter writing execution state and accessible from exterior of controller

L'invention concerne un calculateur de contrôle moteur (1) comprenant une mémoire non volatile (15). Le calculateur est apte à exécuter une activation prolongée durant laquelle le calculateur est maintenu alimenté. Le calculateur écrit des paramètres de fonctionnement dans sa mémoire non volatile (15) durant cette activation prolongée. La mémoire non volatile comprend une zone de mémorisation (17) de l'état d'exécution d'écriture des paramètres. À la fin de l'écriture des paramètres dans la mémoire non volatile, le calculateur (1) inscrit un état de fin d'écriture dans la zone de mémorisation. Le calculateur comprend de plus une interface de consultation de l'état d'exécution accessible depuis l'extérieur du calculateur.

PROCESS AND CIRCUIT OF TEST FOR MEMORY IN INTEGRATED CIRCUIT

PROCESS AND CIRCUIT OF TEST FOR MEMORY IN INTEGRATED CIRCUIT

PROCESS AND CIRCUIT OF TEST FOR MEMORY IN INTEGRATED CIRCUIT

PROCESS AND CIRCUIT OF TEST FOR MEMORY IN INTEGRATED CIRCUIT

FLASH MEMORY DEVICE

SEMICONDUCTOR MEMORY DEVICE AND FAIL BIT TEST METHOD THEREOF

분리형 게이트 플래시 메모리 셀들의 프로그래밍 동안 외란을 감소시키기 위한 시스템 및 방법

... 플래시 메모리 셀들의 프로그래밍 동안 외란을 감소시키기 위한 개선된 제어 게이트 디코딩 설계가 개시된다. 일 실시예에서, 제어 게이트 라인 디코더는 제1 섹터 내의 소정 로우의 플래시 메모리 셀들과 연관된 제1 제어 게이트 라인, 및 제2 섹터 내의 소정 로우의 플래시 메모리 셀들과 연관된 제2 제어 게이트 라인에 커플링된다.

비휘발성 메모리 장치 및 이를 포함하는 메모리 시스템

... 비휘발성 메모리 장치는 전압 공급 컨트롤러, 전압 레귤레이터, 로우 디코더 및 메모리 셀 어레이를 포함한다. 전압 공급 컨트롤러는 전원 전압의 레벨을 검출하여 검출 신호를 발생하고, 검출 신호 및 외부 고전압에 기초하여 전원 전압의 공급이 중단되는지 여부에 따라 가변되는 제1 내부 전압을 발생한다. 전압 레귤레이터는 제1 내부 전압에 기초하여 복수의 제2 내부 전압들을 발생한다. 로우 디코더는 복수의 워드 라인들에 복수의 제2 내부 전압들을 제공한다. 메모리 셀 어레이는 복수의 워드 라인들 및 복수의 비트 라인들에 연결되는 복수의 메모리 셀들을 구비한다.

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

ENCODING METHOD AND MEMORY APPARATUS

UNUSABLE BLOCK MANAGEMENT WITHIN A NON-VOLATILE MEMORY SYSTEM

FLASH MEMORY DEVICE FOR IMPROVING RELIABLITY OF REPAIR DATA AND REPAIR METHOD THEREOF

MEMORY DEVICE AND A MEMORY SYSTEM INCLUDING OF THE SAME, CAPABLE OF SECURING A CONTACT AREA OF BIT LINE AND A BUTTER UNIT

PURPOSE: A memory device and a memory system including of the same are provided to connect a bit line and a page buffer unit through a sub-line by forming the sub-line at a connection part between the cell array and the page buffer unit. CONSTITUTION: A memory device(100) comprises a memory cell connected to a bit line, page buffer units(131,133), and a connection unit. The connection unit is located between the memory cell and the page buffer. The connection unit connected to a bit line comprises a sub-line connecting the memory cell and page buffer unit. The memory device comprises first contacts which are formed between the memory cell and the bit line and also includes second contacts(51-56) which are formed between the bit line and the subs line. COPYRIGHT KIPO 2010 ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a memory block including drain select transistors that are connected to bit lines, source select transistors that are connected to a common source line, and memory cells that are connected between the drain select transistors and the source select transistors, and an operation circuit configured to repeat a program operation and a program verifying operation to increase threshold voltages of the drain select transistors to a target level. The operation circuit applies a verification voltage that is applied to the drain select transistor first at a level that is lower than a normal level, for a program verifying operation, and increases the verification voltage to the normal level whenever the program verifying operation is repeated. An embodiment of the present invention provides a semiconductor device that can improve the reliability of an operation. COPYRIGHT KIPO 2016 (AA) Start (BB) End (C1,C2,C3) Yes (D1,D2,D3) No (S310,S350) DST program operation (S320 ...

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

The present technology includes a semiconductor device which includes: memory blocks which include a plurality of strings to which memory cells are connected, between select transistors; a peripheral circuit which is configured to program or erase the memory cells and the select transistors included in the selected memory block, among the memory blocks; and a control circuit which erases the memory cells and the select transistors, increases the threshold voltages of the select transistors within an erasure level, and controls the peripheral circuit to increase the threshold voltages of the select transistors up to a program level, and an operating method thereof. Accordingly, the present invention can suppress a leakage current in the strings to improve the reliability of the semiconductor device. COPYRIGHT KIPO 2016 (AA) Start (BB) End (S101) Erasing selected memory blocks (S102) Sub soft program (S103) Main soft program (S104) Select transistors and dummy cells program ...

FUSE ARRAY CIRCUIT CONSISTING OF FLASH CELLS, CAPABLE OF REDUCING AREA OF FUSE CELL ARRAY BY SHARING BIT LINES AND FUSE SENSE AMPLIFIER CONNECTED TO EACH BIT LINE, WITH FUSE CELL ARRAY

PURPOSE: A fuse array circuit embodied with a flash cell is provided to test a flash memory through repetitive program and erase operation of the flash cell by constituting a protection circuit, a first peripheral circuit and a second peripheral circuit with flash cells. CONSTITUTION: A flash cell array(20) consists of a number of flash memory cells. A protection circuit(40) shares bit lines with the flash cell array, consists of flash cells, and controls the connection between the flash cell array and an external logic circuit. A first peripheral circuit(50) consisting of flash cells, shares bit lines and changes an address of a defective cell into an address of a redundancy cell. A second peripheral circuit(60) consisting of flash cells, shares bit lines and controls a DC level for adjusting a reference value during the fabrication of the flash memory device. A fuse sense amplifier part(30) reads data from the bit lines in connection with the bit lines. © KIPO 2006 ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING THE INFLUENCE OF NOISES DUE TO A CAPACITIVE COUPLING BETWEEN BIT LINES

PURPOSE: A nonvolatile semiconductor memory device is provided to reduce necessary time of a writing operation by suppressing an over program. CONSTITUTION: A bit line is electrically connected to one end of a current path of a memory cell. A source line is electrically connected to the other end of the current path of the memory cell. A sense amplifier circuit(13) is electrically connected to the bit line and reads data from the memory cell. A row decoder(11) applies read voltage to a word line to make the memory cell on. A controller determines whether the memory cell is degraded or not by measuring a cell current flowing in the memory cell of an on state. COPYRIGHT KIPO 2011 ...

Techniques for updating trim parameters in non-volatile memory

METHOD FOR MONITORING SOURCE CONTACT OF FLASH MEMORY

PURPOSE: A method for monitoring source contact of flash memory is provided to improve the yield and the reliability of the flash memory by monitoring the contact condition of the source contact in the case that the flash memory is formed by the local interconnection method of a source line. CONSTITUTION: A plurality of word lines are connected to a common VG terminal(400), the first drain contact(27) is connected to a VD terminal(500), and the other drain contacts(27) are floated. The last common source contact(28) is connected to a VSS terminal(700), and the other common source contacts(28) are connected to a VS terminal(600). If the neighboring drain contacts(27) are separated, the drain contacts(27) are connected via a metal wire(300), so that current can be flowed from the VD terminal(500) to the VSS terminal(700). COPYRIGHT 2001 KIPO ...

3D 메모리에서의 서브-블록 디코딩

... 일부 실시예들은 메모리 셀들의 블록들과 연관된 장치들 및 방법들에 관한 것이다. 메모리 셀들의 블록들은 메모리 셀들의 2개 이상의 서브-블록들을 포함할 수 있다. 서브-블록들은 소스 선택 트랜지스터 및 드레인 선택 트랜지스터를 포함하는 메모리 셀들의 수직 스트링을 포함할 수 있다. 장치는 2개 이상의 드레인 선택 라인들을 포함할 수 있으며, 2개 이상의 드레인 선택 라인들 중 제 1 드레인 선택 라인은 제 1 블록의 제 1 서브-블록의 드레인 선택 트랜지스터 및 제 2 블록의 제 1 서브-블록의 드레인 선택 트랜지스터에 커플링된다. 장치의 제 2 드레인 선택 라인은 제 1 블록의 제 2 서브-블록의 드레인 선택 트랜지스터 및 제 2 블록의 제 2 서브-블록의 드레인 선택 트랜지스터에 커플링될 수 있다. 다른 장치들 및 방법들이 설명된다.

METHOD FOR OPERATING SONOS MEMORY DEVICE CAPABLE OF MINIMIZING DECREASE OF ON-CELL CURRENT

PURPOSE: A method for operating an SONOS(Silicon Oxide Nitride Oxide Silicon) memory device is provided to improve the efficiency of writing and erasing processes and to prevent the malfunction of the device by minimizing the decrease of an on-cell current. CONSTITUTION: An SONOS memory device comprises a substrate(10), first and second doped regions(12,14) spaced apart from each other in the substrate, a gate oxide layer between the first and the second doped region on the substrate, a first trap layer on the gate oxide layer, an insulating layer on the first trap layer, and a gate electrode(22) on the insulating layer. While a data writing process is performed on the SONOS memory device, the first doped region, the second doped region, and the gate electrode are applied with a first voltage, a second voltage and a gate voltage, respectively. © KIPO 2007 ...

System in package structure, electroplating module thereof and memory storage device

A system in package (SIP) structure, an electroplating module thereof and a memory storage device are provided. The SIP structure includes a first layout layer, a second layout layer and a rewritable non-volatile memory module. The first layout layer includes a first pad and a wire. The first pad is close to a first side of the first layout layer, and the first pad is configured to couple to a grounding voltage. One terminal of the wire is coupled to the first pad, and another terminal of the wire is coupled to an opening of the SIP structure, wherein the opening is located at a second side of the first layout layer opposite to the first side, and the opening is configured to couple to an external voltage.

Semiconductor storage device

As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

High temperature methods for enhancing retention characteristics of memory devices

Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells, and a reprogramming process to program the memory device once again by programming memory cells in a 0-state to a high Vt state. The baking step of placing the memory device in a high temperature environment causes a charge loss by expelling shallow trapped charges, resulting in the improvement of retention reliability.

Flash memory

The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.

Programming management data for NAND memories

Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combining a block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combining the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.

Non-volatile memory and method for compensation for variations along a word line

Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.

Access line dependent biasing schemes

The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.

Using multiple status bits per cell for handling power failures during write operations

A multi-level cell memory (30) may include at least two status bits. The status bits may be examined to determine whether or not a write operation was successful after a power loss occurs.

Memory cell and memory array

Inter-cell interference cancellation

Electron blocking layers for electronic devices

Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.

Nonvolatile memory devices with test data buffers and methods for testing same

A memory device includes a non-volatile memory core that includes a memory cell array and a page buffer configured to store data to be programmed in the memory cell array. The device also includes a test data input buffer configured to receive test data from an external source, and control circuit that controls the non-volatile memory core and the test data input buffer. The control circuit is configured to load test data from the test data buffer to the page buffer, to program the loaded test data in the page buffer in the memory cell array, and to retain the test data in the page buffer for subsequent programming of the memory cell array. The device may further include a test data output buffer configured to receive data read from the memory cell array, and the control circuit may be operative to convey the read data from the test data output buffer to an external recipient.

Embedded architecture with serial interface for testing flash memories

A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.

Semiconductor device

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

Cell deterioration warning apparatus and method

Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Warning of cell deterioration can be performed using reference cells programmed in accordance with a known pattern such as to approximate deterioration of non-volatile memory cells of the device.

Memory Bit Redundant Vias

An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the original data groups. The semiconductor memory device also includes data decoding logic for generating the original data groups from the converted data groups and the inverted flag data. A peripheral circuit may be enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells. A control logic may be enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit.

Semiconductor device

A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (t a /t b )×(ε ra /ε rb )<0.1, where t a represents the thickness of the gate insulating layer, t b represents the thickness of the insulating layer, ε ra represents the dielectric constant of the gate insulating layer, and ε rb represents the dielectric constant of the insulating layer.

Semiconductor device

A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.

Nonvolatile Semiconductor Memory

A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

Low power, single poly EEPROM cell with voltage divider

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8 ) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch ( 806 ) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider ( 804 ) is coupled in series with the switch. A sense transistor ( 152 ) has a sense control terminal ( 156 ) and a current path coupled between an output terminal ( 108 ) and a reference terminal ( 110 ). A first capacitor ( 154 ) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor ( 716 ) has a control terminal coupled to receive a read signal ( 721 ), and a current path coupled between the output terminal and a bit line ( 718 ).

Flash memory device and a method of programming the same

A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line voltage control signal is not affected by a change in a power voltage of the flash memory device.

Non-volatile memory with dynamic multi-mode operation

A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.

Method of operating semiconductor memory device

According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

Method of forming a non-volatile electron storage memory and the resulting device

The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

Semiconductor device and method for driving semiconductor device

It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a transistor including a first semiconductor material, a transistor including a second semiconductor material that is different from the first semiconductor material, and a capacitor, and a potential switching circuit having a function of supplying a power supply potential to a source line in a writing period. Thus, power consumption of the semiconductor device can be sufficiently suppressed.

Programming non-volatile memory with high resolution variable initial programming pulse

Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results.

Method for driving semiconductor memory device

A method for driving a semiconductor memory device including a transistor with low leakage current between a source and a drain in an off state and capable of storing data for a long time is provided. In a matrix including a plurality of memory cells in each of which a drain of a write transistor, a gate of an element transistor, and one electrode of a capacitor are connected, a gate of the write transistor is connected to a write word line, and the other electrode of the capacitor is connected to a read word line. The amount of charge stored in the capacitor is checked by changing the potential of the read word line, and if the amount of charge has decreased beyond a predetermined amount, the memory cell is refreshed.

Nonvolatile Memory Devices, Channel Boosting Methods Thereof, Programming Methods Thereof, And Memory Systems Including The Same

Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

Nonvolatile semiconductor memory device and driving method thereof

A nonvolatile semiconductor memory device has a first select transistor having a gate electrode connected to a first select word line, a source connected to a first sub bit line, and a drain connected to a first main bit line, and a second select transistor having a gate electrode connected to a second select word line, a source connected to a second sub bit line, and a drain connected to a second main bit line. The first sub bit lines are controlled by the first select transistor so as to be electrically isolated from each other between memory cell groups each formed by the memory cells to be erased simultaneously. On the other hand, the second sub bit lines are connected in common to the memory cells of memory cell groups to be erased separately, by the second select transistor.

NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS flash memory array

A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

Driving method of semiconductor device

A semiconductor device with a novel structure and a driving method thereof are provided. A semiconductor device includes a non-volatile memory cell including a writing transistor including an oxide semiconductor, a reading p-channel transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of electric charge is held in the node. In a holding period, the memory cell is brought into a selected state and a source electrode and a drain electrode of the reading transistor are set to the same potential, whereby the electric charge stored in the node is held.

Memory device having three-dimensional gate structure

Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.

Semiconductor memory device capable of memorizing multivalued data

In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2 k threshold voltages (k is a natural number equal to 3 or more) in each memory cell in the memory cell array. A control circuit refreshes data by moving the data in one of the plurality of dynamic latch circuits to the static latch circuit and further moving the data in the static latch circuit to one of the plurality of dynamic latch circuits.

System and method for adjusting read voltage thresholds in memories

A system and method for adjusting read threshold voltage values, for example, in a read circuit internal to a memory device. The quality of an associated read result may be estimated for each read threshold voltage value used to read memory cells. Only read results estimated to have sufficient quality may be allowed to pass to storage. The read threshold voltage value may be adjusted for subsequent read operations, for example, if the associated read result is estimated to have insufficient quality. The read threshold voltage value may be iteratively adjusted, for example, until a read result is estimated to have sufficient quality.

Pre-charge sensing scheme for non-volatile memory (nvm)

The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.

Systems and methods for averaging error rates in non-volatile devices and storage systems

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

EEPROM-based, data-oriented combo NVM design

A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines each connected to nonvolatile memory cells; and a control circuit. When executing the data reading operation, the control circuit applies to a selected word line connected to a selected memory cell a first voltage obtained by adding a first adjusting voltage to an intermediate voltage between adjoining two of the threshold voltage distributions; applies to first non-selected word lines adjoining the selected word line a second voltage obtained by subtracting a second adjusting voltage from a reading pass voltage; applies to second non-selected word lines adjoining the first non-selected word lines a third voltage obtained by adding the second adjusting voltage to the reading pass voltage; and applies to third non-selected word lines, the third non-selected word lines being non-selected word lines except the first and second non-selected word lines, the reading pass voltage.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.

Nonvolatile semiconductor memory device

A control circuit during an erase operation sets a voltage of a first line connected to a selected cell unit to a voltage larger than a voltage of a gate of a first transistor included in the selected cell unit by an amount of a first voltage, sets a voltage difference between a voltage of a first line connected to an unselected cell unit and a voltage of a gate of a first transistor included in the unselected cell unit to a second voltage which differs from the first voltage, applies in the selected cell unit and the unselected cell unit a third voltage to a gate of at least one of dummy memory transistors in a dummy memory string, and applies a fourth voltage to a gate of another one of the dummy memory transistors in the dummy memory string, the fourth voltage being lower than the third voltage.

Nonvolatile semiconductor memory device

A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

Flash memory system and word line interleaving method thereof

Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.

Semiconductor device

According to one embodiment, a semiconductor storage device includes a transistor, a first node, a first capacitor, a first switch, and a second switch. One end of the transistor is connected to a first voltage source supplying a first voltage. The first node is charged to the first voltage by the transistor. One of electrodes of the first capacitor is connected to the first node, and the other of the electrodes of the first capacitor is supplied with a first clock signal having a second voltage. One end of the first switch is connected to the first node. The first switch outputs a potential of the first node at a first time at which the first switch is turned on. One end of the second switch is connected to the first node. The second switch outputs the potential of the first node at a second time.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.

Multi-gate bandgap engineered memory

Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.

Nonvolatile semiconductor memory device, method of fabricating the nonvolatile semiconductor memory device and process of writing data on the nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Nonvolatile semiconductor memory device with advanced multi-page program operation

A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

Memory system and programming method thereof

Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.

E/p durability by using a sub-range of a full programming range

A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits.

Semiconductor memory device and method of operating the same

A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code.

Method of providing an operating voltage in a memory device and a memory controller for the memory device

A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Nonvolatile Memory Devices, Erasing Methods Thereof and Memory Systems Including the Same

Disclosed are erase methods for a memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the plurality of cell strings; applying a ground voltage to string selection lines connected with selection transistors of the plurality of cell strings; applying a word line erase voltage to word lines connected with memory cells of the plurality of cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.

Non-volatile memory and manufacturing method thereof and operating method of memory cell

A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell.

Retention in nvm with top or bottom injection

Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.

Non-volatile memory device, method of operating the same, and electronic device having the same

In one embodiment, the method includes receiving an operation command, detecting a noise level of a common source line, and adjusting a number of times to perform an operation on a memory cell in response to the operation command based on the detected noise level.

Memory instruction including parameter to affect operating condition of memory

Subject matter disclosed herein relates to techniques to operate memory.

Nonvolatile semiconductor memory device

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Method and memory controller for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory

An exemplary method for reading data stored in a flash memory includes: controlling the flash memory to perform a plurality of read operations upon each of a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from each of the memory cells as one of the bit sequences by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Non-volatile memory device and method for fabricating the same

A method of fabricating a non-volatile memory device is provided. The method includes sequentially forming a tunnel insulation layer and a first polysilicon layer on a substrate, patterning the first polysilicon layer and the tunnel insulation layer, forming a dielectric layer to cover the patterned first polysilicon layer and the patterned tunnel insulation layer, forming a gate insulation layer on the substrate where the substrate is exposed, forming a second polysilicon layer to cover the dielectric layer, and forming a first floating gate and a second floating gate a fixed distance apart from each other, the forming of the first and second floating gates including etching middle portions of the second polysilicon layer, the dielectric layer, the patterned first polysilicon layer, and the patterned tunnel insulation layer, and separating the etched layers into two parts.

Non-volatile storage system with shared bit lines connected to single selection device

A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line.

Biasing system and method

Embodiments are provided that include a memory system that includes a memory system, having an access device coupled between a global line and a local line and a voltage source coupled to the global line and configured to output a bias voltage on the global line when the memory system is in a non-operation state. The access device is selected when the memory system is in the non-operation state, and the access device is deselected when the memory system is in an other state. Further embodiments provide, for example, a method that includes coupling a global access line to a local access line, biasing the local access line to a voltage other than a negative supply voltage while a memory device is in a first state and uncoupling the global access line from the local access line while the memory device is in an other state.

Non-volatile memory device and method of manufacturing the same

A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.

Use of Alternative Value in Cell Detection

A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.

Single check memory devices and methods

Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.

Method for writing data in semiconductor storage device and semiconductor storage device

A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other.

Nonvolatile semiconductor memory device and method for controlling the same

During data read process, a control circuit gives a read voltage to a selected word line connected to a selected memory cell, and gives read pass voltages, for turning on memory cells, to unselected word lines connected to unselected memory cells. The control circuit respectively gives a first read pass voltage, a second read pass voltage, and a third read pass voltage to a first unselected word line adjacent to the selected word line at a side of at least one of a bit line and a source line, a second unselected word line adjacent to the first unselected word line at a side opposite to the selected word line, and a third unselected word line adjacent to the second unselected word line at a side opposite to the selected word line. The second read pass voltage is higher than the third read pass voltage.

Nonvolatile memory devices

A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

Nonvolatile memory device and nonvolatile memory system employing same

A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.

Nonvolatile semiconductor memory having a word line bent towards a select gate line side

A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Architecture for a 3d memory array

Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines.

Memory Device, Manufacturing Method and Operating Method of the Same

A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

One-Die Flotox-Based Combo Non-Volatile Memory

A memory access apparatus that controls access to at least one memory array has an array of programmable comparison cells that retain a programmed pass code and compare it with an access pass code. When there is a match between the access pass code and the programmed pass code, the memory access apparatus generates a match signal for allowing access to the at least one memory array. If there is no match, the data within the at least one memory array may be corrupted or destroyed. Each nonvolatile comparison cell has a pair of series connected charge retaining transistors. The programmed pass code is stored in the charge retaining transistors. Primary and complementary query pass codes are applied to the charge retaining transistors and are logically compared with the stored pass code and based on the programmed threshold voltage levels determine if the query pass code is correct.

Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory

A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

Cell operation monitoring

Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Atypical cell, block, string, column, row, etc. . . . operation is monitored and locations and type of atypical operation stored. Adjustment of operation is performed based upon the atypical cell operation.

Nonvolatile semiconductor memory device and method for driving the same

According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure, a semiconductor pillar, a storage layer, an inner insulating film, an outer insulating film, a memory cell transistor. The control unit performs control of setting the thresholds of the memory transistor to either positive or negative, and performs control so that, with one of the thresholds most distant from 0 volts being defined as n-th threshold, width of distribution of m-th threshold (m being an integer of 1 or more smaller than n) having a sign being same as the n-th threshold is set narrower than width of distribution of the n-th threshold.

Non-volatile semiconductor memory device

A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

Semiconductor memory device in which capacitance between bit lines is reduced, and method of manufacturing the same

According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a plurality of memory cells, and a plurality of bit lines for selecting a plurality of memory cells. Of the plurality of bit lines, first bit lines and second bit lines are arranged in different layers.

Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device

A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack

A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge.

Non-volatile memory device and memory system including the same

A non-volatile memory device and a read method thereof are disclosed. The read method includes providing a memory block having memory cells connected to word lines and connected in serial to a bit line, sensing potential of the bit line by applying a first read voltage to a selected word line of the word lines and providing a first pass voltage to an unselected word line adjacent to the selected word line, sensing potential of the bit line by applying a second read voltage higher than the first read voltage to the selected word line and providing a second pass voltage lower than the first pass voltage to the unselected word line adjacent to the selected word line, and sensing potential of the bit line by applying a third read voltage higher than the second read voltage to the selected word line and providing a third pass voltage lower than the second pass voltage to the unselected word line adjacent to the selected word line.

Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors

A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned.

Nonvolatile Memory Device And Operating Method Thereof

According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.

Memory device with multiple planes

Disclosed herein is a device that comprises at least one selection/non-selection voltage receiving line, at least one word line operatively coupled to the selection/non-selection voltage receiving line, and a plurality of memory cells coupled to the word line; a selection voltage source line; and a selection voltage supply circuit comprising a first switch circuit and a first driver circuit driving the first switch circuit to be turned ON or OFF, the first switch circuit including a first node coupled to the selection voltage source line, a second node coupled to the selection/non-selection voltage receiving line of the first memory plane and a third node coupled to the selection/non-selection voltage receiving line of the second memory plane, and the first driver circuit being provided in common to the first and second memory planes.

Nonvolatile memory device, driving method thereof, and memory system having the same

A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and a ground voltage is applied to the well of the transistor. And, during a second time a second high voltage level is applied to the channel of the transistor, and within the second time interval a first negative voltage is applied to the well of the transistor. The first high voltage level is higher than the second high voltage level, and a voltage applied on the selected wordline is negative within the second time interval.

Sense operation in a stacked memory array device

Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers).

Circuit and Method for a Three Dimensional Non-Volatile Memory

An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment cell is disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non-volatile arrays formed of the SONOS cells rely on conventional semiconductor processing. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.

Logic-Based Multiple Time Programming Memory Cell

A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

Non-volatile memory cell

The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.

Electrically addressed non-volatile memory maintentance

An electrically addressed non-volatile memory is maintained by measuring a voltage threshold for each selected memory cell in the electrically addressed non-volatile memory. The voltage threshold is a voltage around which a controllable voltage signal applied to a control gate of a selected memory cell produces a change in value read from the selected memory cell. A measured voltage threshold distribution of the measured voltage thresholds is generated for the selected memory cells. The voltage threshold distribution is analyzed to identify memory cells having greater probabilities of read errors, for example. In response to the analysis, an operating parameter that affects the memory cells identified as having greater probabilities of read errors is selectively changed.

Non-Sequential Encoding Scheme for Multi-Level Cell (MLC) Memory Cells

Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.

Memory system

According to one embodiment, there is provided memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device. The changing unit changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value. The writing process is a process in which a writing operation and a verification operation are alternately repeated.

Nonvolatile programmable logic switch

An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

Semiconductor memory and semiconductor memory control method

According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.

Non-volatile memory device and program method thereof

A method for programming a non-volatile memory device including a plurality of memory cells includes verifying whether the memory cells are programmed or not by applying a program verification bias voltage, which is calculated and stored during an initialization operation preformed before the programming of the memory cells, after a program voltage is applied to word lines of the memory cells.

Internal wordline current leakage self-detection method, detection system and computer-readable storage medium for nor-type flash memory device

A wordline internal current leakage self-detection method, system and a computer-readable storage medium thereof employ the originally existed high voltage supply unit and the voltage detector connected to the wordline in the flash memory device, in which the high voltage supply unit applies the test signal to the selected wordline, and the voltage detector detects the voltage signal of the wordline. By comparing the test signal with the voltage signal, the wordline will be indicated as current leakage when the voltage signal is lower than the test signal.

Semiconductor device and method of driving semiconductor device

A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the semiconductor device included a transistor formed using an oxide semiconductor and a transistor formed using a material other than an oxide semiconductor. A variation in threshold value of the memory cells is derived before data of a data buffer is written by using a writing circuit. Data in which the variation in threshold value is compensated with respect to the data of the data buffer is written to the memory cell.

Using Channel-To-Channel Coupling To Compensate Floating Gate-To-Floating Gate Coupling In Programming Of Non-Volatile Memory

In a non-volatile storage system, during a verify operation, a verify voltage of a currently-sensed target data state is applied to a selected word line. A higher, nominal bit line voltage is used for the storage elements which have the currently-sensed target data state and a verify status of pass or no pass, a target data state lower than the currently-sensed target data state and a verify status of pass or no pass, or a target data state higher than the currently-sensed target data state and a verify status of pass. A lower bit line voltage is used for the storage elements which have the target data state higher than the currently-sensed target data state and a verify status of no pass, to enhance channel-to-channel coupling, as an offset to floating gate-to-floating gate coupling which is later caused by these storage elements.

Method of programming memory and memory apparatus utilizing the method

A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.

Field side sub-bitline nor flash array and method of fabricating the same

Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

3-dimensional non-volatile memory device and method of manufacturing the same

A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines.

Semiconductor memory apparatus

A semiconductor memory apparatus includes a boundary circuit unit positioned between a low voltage page buffer and a high voltage page buffer and having circuits configured to electrically couple the low voltage page buffer and the high voltage page buffer. The boundary circuit unit includes: a first boundary circuit unit having first and second transistors configured to receive data of a corresponding memory cell area through a signal transmission line selected from a plurality of signal transmission lines extended and arranged along a first direction for each column; a second boundary circuit unit disposed adjacent in the first direction from the first boundary circuit unit and having the plurality of signal transmission lines extended and arranged thereon; and an active region where the first transistor is formed and an active region where the second transistor is formed are isolated from each other.

Method for operating non-volatile memory device

A method for operating a non-volatile memory device includes performing an erase operation onto a memory block including a plurality of memory cells, and performing a first soft program operation onto all the memory cells of a string, after the erase operation, grouping word lines of the string into a plurality of word line groups, and performing a second soft program operation onto memory cells coupled with the word lines of each word line group.

Data storage system having multi-level memory device and operating method thereof

A method for a data storage system is disclosed. The method includes providing a memory cell array, and providing N blocks in a first region of the memory cell array, N being an integer greater than 1. Each cell of each block of the N blocks is configured to store no more than N−1 bits of data. The method further includes providing a block in the second region of the memory cell array. Each cell of the block in the second region is configured to store N bits of data. The method additionally includes configuring the data storage system so that when data is programmed to the memory cell array, N pages of the data are initially stored in N respective blocks of the first region of the memory cell array, and then the N pages of the data are stored in the block of the second region.

Nonvolatile semiconductor memory device

In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than the writing-prohibited bit line to a second voltage. In this way, the control circuit prohibits writing into a memory transistor corresponding to the writing-prohibited bit line. On the other hand, the control circuit executes writing into a memory transistor corresponding to the writing bit line.

Erase operation control sequencing apparatus, systems, and methods

Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.

Method for memory cell erasure with a programming monitor of reference cells

Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

In-field block retiring

Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Semiconductor memory device

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

Method of operating semiconductor device

A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.

Apparatuses and methods including memory array and data line architecture

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.