Verfahren zur Herstellung eines Grabenkondensators

Chemical mechanical polishing device with a pressure-controlling mechanism

The present invention provides a CMP device with a pressure-controlling mechanism comprising a rotating polishing plate, a slurry supplying system for supplying slurry, a rotating carrier that holds and rotates a silicon wafer such that the wafer surface is polished against the rotating polishing plate and the slurry during a CMP process, and a pressure-controlling mechanism capable of exerting different pressures to different locations on the wafer in response to different polishing rates corresponding to each of the specified locations. By utilizing the CMP device according to the present invention, the polishing rate and finish quality at different locations of the silicon wafer will be more uniform, which in turn contributes to an improved wafer planarizing effect.

Method of doping sidewall of isolation trench

A method of doping sidewalls of an isolation trench is provided. A substrate having a trench thereon is provided. A blocking layer is formed within the trench such that the top surface of the blocking layer is lower than the top surface of the substrate. A sidewall doping process is performed to form a doped region in the substrate at the upper trench sidewall. The blocking layer is removed from the trench. Because the blocking layer prevent dopants from reaching the bottom half of the trench during the sidewall doping process, junction leakage at the bottom section of the trench is prevented.

Method and system for configuring to a desired order the order of a data array

A method and system of configuring an array of data is disclosed. The method and system comprise generating an array of data an order and reconfiguring the array of data into a plurality sub arrays of data, the plurality of sub arrays of data being in a desired order. By utilizing the method and system in accordance with the present invention, a converted data array can be processed in a parallel fashion thereby increasing the overall processing speed of the computer system. The present invention has particular utility when converting data either from a bit reverse order to a natural order or from a natural order to a bit reverse order. In accordance with the present invention, the array of data is reconfigured utilizing a swap operation to allow for conversion of the data array from either a bit reverse order to a natural order or from a natural order to a bit reversed order.

Methods of fabricating integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges

A widened contact area ( 170 X) of a conductive feature ( 170 ) is formed by means of self-alignment between an edge ( 170 E 2 ) of the conductive feature and an edge ( 140 E) of another feature ( 140 ). The other feature ("first feature") is formed from a first layer, and the conductive feature is formed from a second layer overlying the first layer. The edge ( 170 E 2 ) of the conductive feature is shaped to provide a widened contact area. This shaping is achieved in a self-aligned manner by shaping the corresponding edge ( 140 E) of the first feature.

Method of fabricating semiconductor device

Method of forming contact plugs

A method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area. First, the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer. Then, an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer. Next, a bitline contact hole is formed in the ILD layer to expose the first conductive layer. Thereafter, the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.

Method for preventing native oxide growth during nitridation

A method for forming a layer of silicon nitride that includes providing at least one silicon wafer in a first chamber with ammonia gas, wherein the first chamber is substantially enclosed, and the at least one silicon wafer reacts with the ammonia gas to form a first layer of silicon nitride on the at least one silicon wafer, providing a second chamber with the ammonia gas, moving the at least one silicon wafer into the second chamber, and forming a second layer of silicon nitride on the silicon wafer.

Leseverstärker mit lokalen Schreibtreibern

Bitline contact plug formation method for flash memory manufacture, involves forming contact hole in inter-layered dielectric layer that covers conductive layer and fills gap between respective gate conducting structures

An inter-layered dielectric (ILD) layer (72) with planarized surface, is formed on a semiconductor substrate (50) comprising gate conducting structures, to cover a conductive layer and to fill gap between respective conducting structures. A bitline contact hole formed in the ILD layer, is filled with a conductive layer, to function as bitline contact plug.

Modifikation eines E-Quadrat-Düsensockels

Pipeline layout apparatus for cooling system

Method for identifying the best tool in a semiconductor manufacturing process

A computer-implemented method for identifying a best tool from a plurality of tools that perform a same operation in a semiconductor fabrication line that includes the steps of determining a first median yield for each of the plurality of tools within a first time interval, weighting the first median yield based on a total number of wafers processed by each of the plurality of tools within the first time interval, determining a second median yield for the semiconductor fabrication line over the first time interval, obtaining a weighted yield difference for each of the plurality of tools relative to the second median yield, and outputting the weighted yield difference for each of the plurality of tools.

Method of forming an opening through an insulating layer of a semiconductor device

An opening through an insulating layer between a first layer and a second layer of a semiconductor device is formed where the second layer is a polysilicon or amorphous silicon hard mask layer. The polysilicon or amorphous silicon hard mask layer is etched to form at least one opening through the polysilicon or amorphous silicon hard mask layer using a patterning layer as a mask having at least one opening. The insulating layer is etched to form the opening through the insulating layer using the etched polysilicon or amorphous silicon hard mask layer as a mask. The etched polysilicon or amorphous silicon hard mask layer is nitridized prior to subsequent processing.

Pre-biased voltage level shifting circuit for integrated circuit devices utilizing differing power supply levels

A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speeds of the level translation of signals based upon two different power supplies.

Substrathalter-Tisch und Verfahren für die Sputter-Reinigung eines Substrats

Reparaturverfahren für einen dielektrischen Film mit einem Lochdefekt auf einem Substrat

Verfahren zum Ausbilden eines doppelimplantierten Gates

Verfahren zum Ausbilden eines doppelimplantierten Gates auf einem Substrat (100) mit einer darauf ausgebildeten Gateoxidschicht (102), wobei das Verfahren folgende Schritte umfasst: Ausbilden einer Vielzahl von Stapelstrukturen (110) auf dem Substrat (100), wobei jede Stapelstruktur (110) zu einer ersten Gruppe oder einer zweiten Gruppe gehört und wobei jede Stapelstruktur (110) eine Polysiliziumschicht (104), eine Opferschicht (106) und eine Maskenschicht (108) umfasst, Ausbilden einer dielektrischen Schicht (112) über dem Substrat (100), das die Stapelstrukturen (110) bedeckt, Planarisieren der dielektrischen Schicht (112), um die Oberfläche der Maskenschicht (108) in den Stapelstrukturen (110) freizulegen, Entfernen der Maskenschicht (108), um eine Vielzahl von Gräben (114) zu bilden, Durchführen einer ersten Ionenimplantation (118), um einen ersten Typ von Ionen in die Stapelstrukturen (110) der ersten Gruppe zu implantieren, Durchführen einer zweiten Ionenimplantation (122), um einen ...

Wafer-transferring pod capable of monitoring process environment

Falut detection system and method for controlling the same

Method for controlling cmp process

Memory structure and method for preparing the same

Method of manufacturing fin-structure cylindrical capacitor

A method of manufacturing cylindrical capacitors with fin-structure is disclosed, wherein comprising: (1) forming an insulating layer on the semiconductor substrate for isolating the drain of MOSFET and the capacitor; (2) forming laminated structure of oxide/BPSG layer to define the capacitor region; (3) removing part of BPSG layer for forming a fin-structure over the fin-structure; (4) depositing a layer of polysilicon on surface of the component to define the lower level storage node; and (5) removing the laminated structure. Fin structure is thus formed over the polysilicon layer, which becomes the storage node of cylindrical capacitor.

Memory structure with high coupling ratio

A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Diagnostic system and operating method for the same

An operating method for a fault detection of a semiconductor process and a diagnostic system for fault detection in a semiconductor process are described. By using the method and the diagnostic system, the real-time process parameters collected during the process is performed by the tool become meaningful and are correlated with the historic process performance data obtained by the post process metrology process. Moreover, the method and the diagnostic system further provide an alarm index for the process performed on the tool to actually reflect the process environment during the process is performed after correlating the real-time process parameters and the historic process performance data. With referring to the alarm index, the current process performance under the real-time process parameters in the tool can be accurately diagnosed.

Semiconductor device with SI-GE layer-containing low resistance, tunable contact

The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1-x (0 Подробнее

Gate structure and method for preparing the same

Method of manufacturing self-aligned contact with reduced process steps

A method of manufacturing a self-aligned contact with reduced process steps, essentially comprises pre-removing silicon nitride layer of a field effect transistor requiring metal-gate contact while opening a first polysilicon to a second polysilicon contact in a structure having interconnect between the first polysilicon and the second polysilicon; and in the subsequent process steps, simultaneously defining a metal-active self-aligned contact and a metal-interconnect-to-gate contact. The process steps comprise: forming electric elements on a semiconductor substrate, forming a first dielectric layer on the surface and two sides of the gate, forming a first interlayer dielectric layer, separately etching the first interlayer dielectric layer and the first dielectric layer to open a metal-to-gate contact, depositing a second polysilicon layer in the contact, forming a second interlayer dielectric layer, etching the second interlayer dielectric layer and the first interlayer dielectric layer ...

Method of selectively etching HSG layer in deep trench capacitor fabrication

The invention provides a method of selectively etching a Hemispherical Silicon Grain (HSG) layer during deep trench capacitor fabrication. A substrate having a pad structure and a deep trench is provided. A buried oxide layer is formed on the upper sidewall of the deep trench and a HSG layer and an ASG layer are formed in the deep trench sequentially. A mask layer is filled into the deep trench and recessed; the exposed ASG layer is then removed. The HSG layer is doped to form a plasma doping layer on the upper portion of the deep trench, which is removed without damaging the silicon substrate. After the mask layer is removed, a cap oxide layer is formed on the deep trench, and the substrate is subjected to a thermal treatment to form a buried plate.

Rapid thermal processing method and apparatus

An apparatus for the rapid thermal processing of a semiconductor wafer is disclosed. The apparatus includes a preheat unit for preheating a gas composition, and a RTP reactor having a processing chamber and a heat source for heating the wafer. The processing chamber has a wafer holder, and a gas inlet and a gas outlet through which the preheated gas composition flows in and out of the processing chamber.

Highly sensitive defect detection method

A highly sensitive defect detection method is disclosed. A medium with a refractive index greater than 1 is formed on a sample. As a result, incident light projected by a defect detecting system attenuates less when reaching the bottom defects. The detection sensitivity of the defect detecting system is enhanced accordingly.

Method of forming a deep trench DRAM cell

A method of forming a deep trench DRAM cell on a semiconductor substrate has steps of: forming a deep trench capacitor in the semiconductor substrate; using silicon-on-insulator (SOI) technology to form a silicon layer on the deep trench capacitor; and forming a vertical transistor on the silicon layer over the deep trench capacitor, wherein the vertical transistor is electrically connected to the deep trench capacitor.

Fabrication method of metal oxide semiconductor transistor

A manufacturing method of metal oxide semiconductor transistor is provided. A substrate is provided. A source/drain extension region is formed in the substrate. A pad material layer with low dielectric constant is formed on the substrate. A trench is formed in the substrate and the pad material layer. A gate dielectric layer is formed on the surface of the substrate in the trench. A stacked gate structure is formed in the trench, wherein the top surface of a conductive layer of the stacked gate structure is higher than the surface of the pad material layer. A spacer material layer is formed conformably on the substrate. Portions of the spacer material layer and the pad material layer are removed so as to form a pair of first spacers and a pair of pad blocks. A source/drain is formed on the substrate beside the stacked gate structure.

Verfahren zur Vorbereitung eines Kondensators mit tiefem Graben zur Strukturanalyse und zugehöriges Strukturanalyseverfahren

Verfahren zur Vorbereitung eines Kondensators (40) mit tiefem Graben zur Analyse, wobei der Kondensator (40) mit tiefem Graben in einem Halbleiterdie (10) vorgesehen ist, welcher eine Oberseite (20) und eine Rückseite (50) aufweist, sowie ein Substrat (30), mit folgenden Schritten: (a) mechanische Behandlung der Rückseite (50) des Dies (10), um so einen ersten Abschnitt (31) des Substrats (30) zu entfernen; (b) Montieren des mechanisch behandelten Dies (10) durch Befestigung der Oberseite (20) des Dies (10) an einer Montagevorrichtung; und (c) chemische Behandlung des Dies (10), um so einen zweiten Abschnitt (32) des Substrats (30) zu entfernen, um den zumindest einen Kondensator (40) mit tiefem Graben für die dreidimensionale Betrachtung freizulegen. (d) Entfernen des Kondensators (40) mit tiefem Graben von dem Die (10) und Befestigen des entfernten Kondensators (40) mit tiefem Graben an einem Kohlenstoffilmgitter.

Verfahren zur Ausbildung eines Kontaktes

Verfahren zur Ausbildung eines Kontakts, umfassend: Vorsehen mindestens zweier Transistoren auf einem Substrat, wobei jeder der Transistoren eine auf einem Gate-Oxid vorgesehene Gate-Elektrode, ein auf der Gate-Elektrode ausgebildetes Silicid, eine auf dem Silicid ausgebildete Kappe und ein Paar von im Substrat ausgebildeten, in Abstand befindlichen Diffusionsbereichen umfasst; Abscheiden einer ersten Schicht aus einem dielektrischen Material auf dem Substrat und den Transistoren; Vorsehen eines ersten Fotoresists auf der ersten Schicht des dielektrischen Materials; Definieren und Strukturieren des ersten Fotoresists; Ätzen der ersten Schicht des dielektrischen Materials und der Kappe, welche nicht durch das erste Fotoresist maskiert sind, um eine erste Öffnung auszubilden, wobei die erste Öffnung das Silicid eines ersten Transistors freilegt; Entfernen des ersten Fotoresists; Abscheiden einer zweiten Schicht aus dielektrischem Material auf der ersten Schicht aus dielektrischem Material ...

Waferauflageplatte

Waferauflageplatte (10), geeignet zum Erfassen der Positionslage eines darauf aufgelegten Wafers (20), umfassend: einen Auflagenplattenkörper; zumindest drei tragende Aufstützungen (30), die auf dem Auflagenplattenkörper angeordnet sind zum Aufnehmen und Tragen des Wafers (20); und zumindest drei Erfassungseinrichtungen, die jeweils neben den tragenden Aufstützungen (30) und innerhalb des von den tragenden Aufstützungen (30) auf der Auflageplatte umschlossenen Gebiets angeordnet sind zum Erfassen, ob der Wafer (20) von allen tragenden Aufstützungen (30) getragen wird.

Method of forming ONO-type sidewall with reduced bird's beak

Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the ...

Fabrication of gate dielectric in nonvolatile memories having select, floating and control gates

In a nonvolatile memory, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed simultaneously. In a nonvolatile memory, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness. Portions of the control gates (170) overlie the select gates.

Verfahren zur Herstellung eines vergrabenen Streifens durch Diffusion mittels Gasphasendotierung

Verfahren zur Herstellung eines vergrabenen Streifens (50), wobei das Verfahren die Schritte aufweist: Bereitstellen eines Substrats (10) mit einer darauf gebildeten Zwischenoxidschicht (24); Bilden einer Maskenschicht (26) über der Zwischenoxidschicht (24); Ätzen der Maskenschicht, der Zwischenoxidschicht und des Substrats, um einen Graben (12, 14) in dem Substrat zu bilden; wobei der Graben eine äußere Seitenwand und einen oberen Bereich aufweist; Beschichten des oberen Bereichs des Grabens mit einem Rand (20, 22); Bilden einer Polysiliziumelektrode (16, 18) in dem Graben; Ätzen der Polysiliziumelektrode (16, 18) und des Randes (20, 22) bis unter die obere Oberfläche des Substrats (10), um eine vertiefte Polysiliziumelektrode (16', 18') und einen vertieften Rand (20', 22') zu bilden, wodurch ein Teil der äußeren Seitenwand (30, 32) des Grabens freigelegt wird; Einführen von Ionen in das Substrat (10) durch die freigelegte äußere Seitenwand des Grabens durch Gasphasendotierung (34); und ...

Verfahren und Vorrichtung zum chemisch-mechanischen Polieren von Halbleiterscheiben

Es wird ein Verfahren und eine Einrichtung zum Polieren von Halbleiterscheiben und insbesondere zur Zufuhr von Schmirgelpulveremulsion bereitgestellt. Die Einrichtung zur Zufuhr von Schmirgelpulveremulsion hat einen Hauptbehälter, der die Schmirgelpulveremulsion enthält, einen Puffertank, wenigstens zwei Schallgeber, eine Schmirgelpulveremulsion-Verteilerleitung und eine Pulssteuerschaltung. Das Verteilerleitungssystem hat eine erste Rohrleitung, eine zweite Rohrleitung und eine dritte Rohrleitung. Gepulste akustische Energie wird an die Schmirgelpulveremulsion in dem Verteilerleitungssystem und an den Hauptbehälter angelegt, um ein Gelieren und Klumpenbildung von Schmirgelpulveremulsion aufzubrechen. Die gepulste akustische Energie kann eine mögliche Gelierung auch verhindern. Daher kann Schmirgelpulvermittel mit einer gleichförmigen Konsistenz und einer kleinen Teilchengröße während des chemisch-mechanischen Polierverfahrens zugeführt werden.

Wafer ID optical sorting system

A wafer ID optical sorting system includes an auto-ID reader, a manual-ID reader and a conveying device, operation of which units is controlled by a monitoring system. The auto-ID reader, connected to the monitoring system, can automatically read and identify an ID and allows the ID to be displayed on the monitoring system. The manual-ID reader, connected to the monitoring system, can fetch the ID image and allows it to be displayed on the monitoring system. The conveying device, connected to the monitoring system, can move the auto-ID reader and the manual-ID reader.

Method and apparatus for determining and assessing chamber inconsistency in a tool

A method is disclosed to determine and assess chamber inconsistency in a multi-chambered tool, especially a multi-chambered tool involved in mass production processes. Wafers produced by the tool are grouped in lots measured to obtain loss yield groups. The invention sorts yield losses to obtain a corresponding monotonic sequence. The invention then averages the monotonic sequences. If the resulting mean monotonic sequence fits with a predetermined aberration, the tool is determined to suffer from chamber inconsistency.

Apparatus and method for preventing a wafer mapping system of an SMIF system from being polluted by corrosive gases remaining on wafers

An apparatus and a method for preventing a wafer mapping system of an SMIF system from being polluted by a corrosive gas remaining on wafers according to the present invention are disclosed. The wafer mapping system includes a plurality of mirrors and sensors used to detect the positions of the wafers. The apparatus of the prevent invention comprises a pipe having a plurality of holes thereon and a purge gas flowing inside the pipe, and is characterized in that the purge gas is emitted out from the plurality of holes toward the mirrors of the wafer mapping system, thereby preventing the mirrors from being polluted by the corrosive gas remaining on the wafers. The method of the prevent invention is characterized by emitting a purge gas from a pipe toward the mirrors of the wafer mapping system, thereby preventing the mirrors from being polluted by the corrosive gas remaining on the wafers.

Method for automatically searching for and sorting failure signatures of wafers

A method of searching for and sorting failure signatures of wafers is provided. First, a failure signature database is built up for recording a plurality of failure signature data, wherein each failure signature data includes a failure signature, a location field for the faulty dies, a failure mode, a position dependence information and a dependent signature. Next, a selected wafer is tested and a test result is generated. Last, a comparison result is generated by an automatic comparing device, wherein the comparison result includes a hit or a miss. When the comparison result is a hit, the comparison result further includes a hit ratio. And as the hit ratio exceeds a predetermined value, the step of comparing the dependent signature of the failure signature database is skipped.

Capacitor dielectric structure of a DRAM cell and method for forming thereof

A capacitor dielectric structure of a deep trench capacitor for a DRAM cell is disclosed. A semiconductor silicon substrate is provided with a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking

The voltage on the high voltage rails of sense amplifier in dynamic random access memories are controlled during turn-on of the sense amplifier to remain approximately at voltage of the voltage source internal to integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltage source at which time the external voltage source is disconnected.

Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices

A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.

Method for reducing capacitance in metal lines using air gaps

A method for forming a metal interconnect having a plurality of metal lines and an interlayer dielectric is disclosed. The metal interconnect has a decreased capacitance between the metal lines of the metal interconnect. First, a metal interconnect is formed onto a substrate. A first HDPCVD oxide layer is formed over the metal interconnect. A second HDPCVD oxide layer is formed over the first HDPCVD oxide layer, the second HDPCVD oxide layer being formed such that air gaps are formed between the metal lines of the metal interconnect. Furthermore, a third HDPCVD oxide layer may be formed over the second HDPCVD oxide layer, the third HDPCVD oxide formed using a sputter to deposition ratio higher than that used to form the second HDPCVD oxide layer.

Method for analyzing the structure of deep trench capacitors and a preparation method thereof

A method for analyzing the structure of deep trench capacitors and a preparation method thereof are described. A protective layer is formed on a selected inspection area. Overlying circuit layers and an upper portion of a substrate, surrounding the selected inspection area, of the die are removed. A chemical etchant is used to selectively remove the exposed substrate material to uncover deep trench capacitors. A structural analysis of those deep trench capacitors is then performed.

Use of pedestals to fabricate contact openings

Nonvolatile memory wordlines ( 160 ) are formed as sidewall spacers on sidewalls of control gate structures ( 280 ). Each control gate structure may contain floating and control gates ( 120, 140 ), or some other elements. Pedestals ( 340 ) are formed adjacent to the control gate structures before the conductive layer ( 160 ) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings ( 330.1 ) that will be etched in an overlying dielectric ( 310 ) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.

Trench capacitor dynamic random access memory featuring structurally independent symmetric active areas

A dynamic random access memory structure is provided, each active area of a memory unit cell is distributed individually in a substrate, and deep trench patterns are designed to have a checkerboard-like arrangement in the substrate. Also, there is a constant space between each deep trench pattern in a row. Further, long bit line contact plugs are located to electrically connect active areas of two diagonally neighbor memory unit cells, and a contact hole is formed on each long bit line contact plug to enable bit lines contact the long bit line contact plugs so two diagonally neighbor memory unit cells are controlled by the same bit line.

Verfahren zum Testen von Halbleiterwafern unter Verwendung von in Unterbereiche aufgeteilten Bereichen

Verfahren zum Testen von Halbleiterwafern, die eine Mehrzahl von Chips aufweisen, aufweisend folgende Schritte: a) Aufteilen von jedem Wafer in eine Mehrzahl von Bereichen, b) Aufteilen von jedem Bereich in eine Mehrzahl von Unterbereichen, c) Durchführen eines elektrischen Tests auf jedem der Chips auf jedem der Wafer, d) für jeden Unterbereich von jedem Wafer: Bestimmen des Anteils an Chips, die den elektrischen Test nicht bestanden haben, e) für jeden Bereich von jedem Wafer: Bestimmen des Anteils an Chips, die den elektrischen Test nicht bestanden haben, f) für jeden Unterbereich: Bestimmen der Anzahl von Wafern, die einen höheren Anteil von Chips, die den elektrischen Test nicht bestanden haben, in dem Unterbereich aufweisen als der Anteil von Chips die den elektrischen Test nicht bestanden haben, in dem den jeweiligen Unterbereich enthaltenden Bereich, und g) Erzeugen einer Ausgabe, die den Unterbereich darstellt, der die höchste im...

Positioning photo routes protecting frame for wafer loader of stepper

A kind of positioning photo routes protecting frame for wafer load of stepper which is to mount the protecting frame on the wafer loader which has the expansion portion as a long sheet and the barrier portion. The one end of expansion portion of protecting frame is connected with the tuyere of wafer loader by screws or bonding. The other end is connected with the barrier portion which is allocated between the positioning light source of wafer loader and the opening and extends a certain length along the photo signal of the light source to protect the photo route of that light signal. By this means, when the operator is maintaining and cleaning the wafer loader from the opening, it can prevent the photo route being obstructed. In this way, it can save the persecution of management and the time wasted on resetting the positioning of wafer loader.

Fabrication of dielectric for a nonvolatile memory cell having multiple floating gates

A memory cell ( 110 ) has a select gate ( 140 ) and at least two floating gates ( 160 ). A gate dielectric ( 150 ) for the floating gates ( 160 ) is formed by thermal oxidation simultaneously with as a dielectric on a surface of the select gate ( 140 ). The dielectric thickness on the select gate is controlled by the dopant concentration in the select gate. Other features are also provided.

Semiconductor structure with lining layer partially etched on sidewall of the gate

A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.

Method for measuring bias voltage of sense amplifier in memory device

A method for measuring a bias voltage of plural sense amplifiers in a memory device is provided. The method includes the steps of: selecting the plural sense amplifiers as a measurement area, writing a midlevel voltage into the respective memory cell modules connected to the plural the sense amplifiers respectively, providing a reference voltage of the midlevel voltage into the plural sense amplifiers in the measurement area, recording output signals of the plural sense amplifiers, wherein the output signal is valued one of "0" and "1", counting numbers of "0" and "1", and obtaining a ratio of the number of "0" over the number of "1", and obtaining the bias voltage of the plural sense amplifiers in the measurement area as the ratio.

Power MOSFET array

A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration.

Verfahren zur Aufbereitung einer Reaktionskammer

Verfahren zum Aufbereiten einer Reaktionskammer (100) mit folgenden Schritten: (a) Reinigen der Reaktionskammer (100), umfassend: Einlassen einer ersten Gasmischung (108) in die Reaktionskammer (100); Einschalten einer Quelle für Radiofrequenzenergie zum Einleiten eines Trockenreinigungsvorgangs, um Mikroteilchen mit hohem Molekulargewicht aus dem Inneren der Reaktionskammer (100) zu entfernen; Entfernen der ersten Gasmischung (108) aus der Reaktionskammer (100); (b) Aufbereiten der Reaktionskammer (100), umfassend: Anordnen eines Dummy-Wafers oder eines Produktwafers (118; 122) mit einer Photolackschicht (120) auf der Oberfläche des Dummy-Wafers oder des Produktwafers (118; 122) im Inneren der Reaktionskammer (100), Einlassen einer zweiten Gasmischung (114) aus Wasserstoff und Stickstoff in die Reaktionskammer (100); und Einschalten der Quelle für Radiofrequenzenergie, um eine Reaktion zwischen der zweiten Gasmischung (114) und dem Photolackmaterial auf dem Dummy-Wafer oder dem Produktwafer ...

Verfahren zum Auffinden der eigentlichen Ursache des Ausfalls eines fehlerhaften Chips

Fabrication method of a dynamic random access memory

A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Advanced contact integration scheme for deep-sub-150 nm devices

An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicide combined with ion mixing implantation. The contact integration technique realizes junctions having low contact resistance (RC), with ultra-shallow contact junction depth (XJC) and high doping concentration in the silicide contact interface (Nc).

Method and apparatus to reduce bias between dense and sparse photoresist patterns

A method and apparatus to eliminate bias between dense and sparse patterns of photoresist images is presented. By placing an attenuator along the optical axis of a photolithography mask and its projected image, the intensity of radiation passing through a sparse pattern of the photolithography mask is attenuated so that the intensity of the projected sparse pattern falls within the same range as the intensity of radiation that passes the dense pattern of the photolithography mask. In this way, the bias between dense patterns and sparse patterns caused by differing radiation intensities during exposure is eliminated. The attenuator has both a transparent region and an attenuating region. The attenuating region is designed to attenuate only the sparse patterns projected from the photolithography mask. The attenuator is covered by materials that can attenuate the density of passed radiation to make the intensity of both low spatial frequency and high spatial frequency images fall within the ...

Apparatus and method for continuity testing of pogo pins in a probe

An apparatus for continuity testing of a pogo pin in a probe comprises a substrate having a pad, a power supply providing a voltage difference between the pad and the pogo pin, and a sensing device signaling when the substrate contacts the probe, and a current is generated by the connection of the pogo pin and the pad.

Integration of silicon carbide into DRAM cell to improve retention characteristics

A DRAM memory cell and a method of making a DRAM memory cell are provided. The DRAM memory cell includes a semiconductor substrate, including a trench formed therein and a buried plate region, at least a first doped region and a second doped region provided on a sidewall of the trench above the buried plate region in the substrate, where the first doped region contains carbon and the second doped region contains germanium provided in a portion of the first region, a dielectric layer formed on the bottom and sidewall of the trench, at least one polysilicon layer deposited in the trench and on the dielectric layer to cover the dielectric layer, and a transistor formed on a surface of the semiconductor substrate.

Gate structure and method for fabricating the same, and method for fabricating memory and CMOS transistor layout

A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.

Memory devices with split gate and blocking layer

Thin film transistor static random access memory structure

A thin film transistor static random access memory structure comprises having field oxides on the surface of a silicon substrate, covering a gate oxide layer between the field oxides, covering the surface of the gate oxide layer with a gate structure as a common gate of PMOS and NMOS, having a doped region in the silicon substrate on both sides of the gate structure as the active region of the NMOS element. The top face of the gate structure is covered with a gate dielectric layer and a polysilicon layer. The polysilicon layer comprises the active region and the channel region of the TFT PMOS element. The surfaces of the TFT PMOS, through the gate dielectric layer, and the common gate of the NMOS element are covered with a dielectric layer. A metal contact structure exists in the dielectric layer as the metal interconnect of the integrated circuit, thereby completing a TFT SRAM structure.

Semiconductor device and fabricating method thereof

Method for forming a protective buffer layer for high temperature oxide processing

A thin buffer layer of SiON is formed on the top surface of the floating gate, in order to protect the polysilicon surface from attack by atomic chlorine produced during the formation of the high temperature oxide of the ONO stack. The buffer layer can also be formed on other dielectric surfaces which are otherwise subject to adverse conditions in subsequent processing, such as the nitride layer in the ONO dielectric stack.

Method of forming a silicon nitride layer on a gate oxide film of a semiconductor device and annealing the nitride layer

A process for forming a silicon nitride layer on a gate oxide film as part of formation of a gate structure in a semiconductor device includes: forming a layer of silicon nitride on top of a gate oxide film on a semiconductor substrate by a nitridation process, heating the semiconductor substrate in an annealing chamber, exposing the semiconductor substrate to N2 in the annealing chamber, and exposing the semiconductor substrate to a mixture of N2 and N2O in the annealing chamber.

Verfahren zum Auffinden eines fehlerhaften Werkzeuges in einer Halbleiterfertigungseinrichtung sowie System zur Durchführung des Verfahrens

Testing model

[DRAM structure and fabricating method thereof]

A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

Method for tungsten deposition without fluorine-contaminated silicon substrate

A method for forming tungsten structures over silicon substrates, including the following steps. A silicon substrate is having a patterned dielectric layer formed thereon defining a tungsten structure opening is provided. The silicon substrate is pre-heated to a temperature of from about 430 to 440° C. A Si-rich WSx layer is formed over the patterned dielectric layer, lining the tungsten structure opening. A WSix nucleation layer is formed over the Si-rich WSix layer. A tungsten bulk layer is formed over the WSix nucleation layer, filling the tungsten structure opening, whereby fluorine attack of the Si substrate is minimized.

Method for removal of hemispherical grained silicon in a deep trench

A method for removal of hemispherical grained silicon (HSG) in a deep trench is described. A buried silicon germanium (SiGe) layer serving as an etch stop layer is formed in the collar region of the trench, followed by depositing a HSG layer. The HSG layer is then successfully striped by wet etching with a potassium hydroxide/propanone/water etchant, that is, without damage to the trench sidewalls, since a good etch rate selectivity between the HSG layer and the SiGe layer is obtained by the wet etchant. In addition, no etch stop layer exists between the HSG layer and the bottom of the trench when manufacturing trench capacitors in accordance with the method; capacitance degradation is therefore not of concern.

System and method for processing residual gas

A system for processing residual gas that includes a chamber having at least one baffle for increasing gas flow path, a residual gas inlet mechanism connected to the chamber for supplying residual gas to the chamber, at least one first gas inlet mechanism connected to the chamber for supplying inert gas to the chamber, at least one second gas inlet mechanism connected to the chamber for supplying a reactive gas to the chamber, and a gas outlet mechanism for connected to the chamber for outputting mixed gases from mixing the residual gas, inert gas and reactive gas and non-reacted residual gas, inert gas and reactive gas.

Method for prioritizing failure modes to improve yield rate in manufacturing semiconductor devices

A method for determining a failure mode with the greatest effect on yield loss in a semiconductor manufacturing process is disclosed. A predetermined number of wafers are processed, and each chip on each wafer is divided into a plurality of regions with each region having a plurality of cells. Electrical tests are performed on each cell, and a region is said to have a failure mode if one cell within the region has that failure mode. The yield loss contribution of a failure mode is determined by considering the yield loss from several wafers having that failure mode as the main failure mode. The yield loss contribution of a failure mode can also be determined by considering the percentage of defective chips on a wafer having that failure mode as the main failure mode. The failure mode with the highest yield loss contribution has the greatest effect on yield loss.

Method of making a silicon nitride film that is transmissive to ultraviolet light

A method for producing an ultraviolet light (UV) transmissive silicon nitride layer in a plasma enhanced chemical vapor deposition (PECVD) reactor is presented. The UV transmissive film is produced by reducing, in comparison to a standard silicon nitride process, a flow rate of the silane and ammonia gas precursors to the PECVD reactor, and significantly increasing a flow rate of nitrogen gas to the reactor. The process reduces the concentration of Si-H bonds in the silicon nitride film to provide UV transmissivity. Further, the amount of nitrogen in the film is greater than in a standard PECVD silicon nitride film, and as a percentage constitutes a greater part of the film than silicon. The film has excellent step coverage and a low number of pinhole defects. The film may be used as a passivation layer in a UV erasable memory integrated circuit.

Method for preparing a memory structure

A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask to reduce the width of the line-shaped blocks to form a second etching mask including a plurality of first blocks and second blocks arranged in an interlaced manner. Subsequently, a portion of the dielectric structure not covered by the second etching mask is removed to form a plurality of openings in the dielectric structure, and a conductive plug is formed in each of the openings. The plurality of openings includes first openings positioned between the first blocks and second openings positioned between the second blocks, and the first opening and the second opening extend to opposite sides of an active area.

Verfahren zur Bildung von Kontakten bei der Herstellung einer integrierten DRAM-Schaltung

Verfahren zur Ausbildung einer Diffusionssperrschicht in einem pMOS-Bauteil

Verfahren zur Ausbildung einer Diffusionssperrschicht in einem pMOS-Bauteil mit folgenden Schritten: Ausbildung einer Gatedielektrikumsschicht (14) mit hohem k-Wert über einem Substrat (10); Ausbildung einer Silizium-Sperrschicht (16) über der Gatedielektrikumsschicht (14) mit hohem k-Wert; Ausbilden einer p-dotierten Gateelektrodenschicht (18) über der Siliziumnitrid-Sperrschicht (16); wobei die Siliziumnitrid-Sperrschicht (16) durch Reaktion von Tetrachlorosilan mit Ammoniak über einen chemischen Dampfablagerungsprozess gebildet wird, so dass die Siliziumnitrid-Sperrschicht (16) die Diffusion eines Dotiermittels des p-Types aus der Gateelektrodenschicht (18) blockiert.

Verfahren zum Entfernen von festen Rückständen auf Oberflächen von Halbleiterscheiben

Technique for programming floating-gate transistor used in circuitry as flash EPROM

The sequence in which the voltages (V_SL, V_DL, V_SG, and V_CL) applied to the source/drain regions (S and D), select gate (SG), and (if present) control gate (CG) of a floating-gate field-effect transistor ( 20 ) start to change value during a programming operation is controlled so as to avoid adjusting the transistor's programmable threshold voltage toward a programmed value when the transistor is intended to remain in the erased condition, i.e., not go into the programmed condition. With the voltage (V_SL) at one source/drain region (S) changing from a nominal value to a programming value, the sequence entails causing the voltage (SG) at the select gate to start changing from a nominal value to a programming-enable value after the voltage at the other source/drain region (D) starts changing from a nominal value to a programming-inhibit value.

Defects reduction for a metal etcher

A method of patterning a metal line and removing the polymer layer that forms on the metal lines sidewalls in an important post etch-polymer removal step (e.g., step 4). A semiconductor structure and an overlying dielectric layer, a first barrier layer, a metal layer; a second barrier layer and resist pattern are provided. A four step etch process is performed in sequence in the same etch chamber. In a first etch step (A), we etch through the second barrier layer using a B and Cl containing gas and a Cl containing gas in a reactive ion etch to form a first polymer layer over the sidewall of the second barrier layer. In a second etch step (B), the metal layer is etched exposing the first barrier layer to form a second polymer over the first polymer and the sidewall of the metal layer; the second etch step performed using a B and Cl containing gas and a Cl containing gas. In a third etch step (C), the first barrier layer is etched to form a third polymer layer over the first and second polymer ...

Photolithography method including a double exposure/double bake

A photoresist exposure process is disclosed which produces features which are substantially smaller than the aperture dimension of the mask used to make the feature. The smaller feature size results from a double exposure of the photoresist, combined with a double baking process to create the features in the photoresist. The double baking process thins the layer of photoresist, prior to the second exposure, thereby improving the resolution of the mark created by the second exposure on the photoresist. The process also uses a binary bias mask through which the first exposure is made, which overlaps with the area of the second exposure, to allow a process tolerance for the realignment of the mask over the wafer for the second exposure.

Verfahren zur Herstellung eines Kontaktlochs

Verfahren zur Herstellung von Kontaktlöchern mit den Schritten: Bereitstellen eines Halbleitersubstrats (50) mit einer ersten Gateleitungsstruktur (561), einer zweiten Gateleitungsstruktur (562), einer dritten Gateleitungsstruktur (563) und einer vierten Gateleitungsstruktur (564), die der Reihe nach angeordnet sind, wobei die zweite Gateleitungsstruktur (562) und die dritte Gateleitungsstruktur (563) in einem aktiven Gebiet gebildet sind; Bilden einer dielektrischen Beschichtung (68) in konformer Weise auf dem Substrat (50); Entfernen von Teilen der dielektrischen Beschichtung (68) zwischen der zweiten Gateleitungsstruktur (562) und der dritten Gateleitungsstruktur (563); Bilden einer leitenden Beschichtung (70) in konformer Weise auf dem Substrat (50); Entfernen von Teilen der leitenden Beschichtung (70), um Bereiche der leitenden Beschichtung (70) zwischen der zweiten Gateleitungsstruktur (562) und der dritten Gateleitungsstruktur (563) zurückzulassen; Bilden einer Zwischendielektrikums ...

Verfahren zum Einebnen einer Isolierung in Form eines flachen Grabens

Verfahren zur Herstellung von DRAM-Grabenkondensatorstrukturen mit kleinen Durchmessern mittels SOI-Technologie

Verfahren zur Herstellung von Grabenkondensatorstrukturen für eine Direktzugriffsspeicherzelle (DRAM) mit den Schritten: Bilden tiefer Grabenöffnungen (4) mit weitem Durchmesser in einem ersten Halbleitersubstrat (1a); Bilden eines vergrabenen Plattengebiets (6) in einem Bereich des ersten Halbleitersubstrats (1a), das die tiefen Grabenöffnungen (4) mit weitem Durchmesser umschließt; Bilden einer dielektrischen Knotenpunktschicht (7) an freigelegten Oberflächen der tiefen Grabenöffnungen (4) mit weitem Durchmesser; Bilden einer leitenden Speicherknotenpunktplattenstruktur (8) in den tiefen Grabenöffnungen (4) mit weitem Durchmesser, woraus sich tiefe Grabenkondensatorstrukturen (60) mit weitem Durchmesser in einem Oberseitenbereich des ersten Halbleitersubstrats (1a) ergeben, wobei jede tiefe Grabenkondensatorstruktur (60) mit weitem Durchmesser die Speicherknotenpunktplattenstruktur (8), die dielektrische Knotenpunktschicht (7) und das vergrabene Plattengebiet (6) aufweist; Bilden eines ...

Method and system for improved audio data retrieval from an optical media

The present invention provides a method and system for audio data retrieval from an optical media. The method includes reading a sector of audio data from the optical media, the sector comprising a sector data and a sector sub-code; collecting the sector sub-code; correcting any errors in the sector data in a fixed time period; calculating a time offset between a time for the collecting of the sector sub-code and the fixed time period; and matching the corrected sector data to the sector sub-code based on the calculated time offset. A method and system for retrieving audio data from an optical media has been disclosed. The present invention uses a fixed time period for the sector data error correction process. By using a fixed correction time, the sector data and the sector sub-code can be automatically matched based upon an offset calculated from the fixed correction time. In this manner, the sector data and its corresponding sector sub-code may be accurately matched without the need for ...

Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section

An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the "read" data path for each section such that the number of delays in the address/clock path plus the number of delays in the "read" data path is substantially constant.

Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures

In a nonvolatile memory, the select gates ( 144 S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines ( 144 ) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric ( 310 ) formed over control gates ( 134 ). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates ( 120 ) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Self aligned contact formation method for CMOS integrated circuit device for DRAM, involves subjecting contact regions formed in substrate to silicide process by depositing refractory metal to form metal silicide regions

The method involves subjecting the raised contact window regions formed in semiconductor substrate to silicide process by depositing refractory metal to form metal silicide regions. Independent claims are included for the following: (1) semiconductor integrated circuit device manufacturing method; and (2) semiconductor integrated circuit device.

Method for preventing forming of water mark or oxide layer on the doped polycrystalline silicon layer of semiconductor chip

The invention provides a kind of method for preventing forming of water mark or oxide layer on the doped polycrystalline silicon layer of semiconductor chip which is used after the hydrous processing preventing forming water mark of native oxide structure on the surface so that the followed metal silicide layer will not have the problem of not being adhesive with the surface of doped polycrystalline silicon layer. The method includes the following steps: (1) by the insitu method to form the silicon layer with water-rejective property on the surface of polycrystalline silicon layer of semiconductor chip; (2) proceed a hydrous process to remove the contaminants on the chip surface; (3) proceed heat treatment for interaction of doped polycrystalline silicon layer and the silicon layer with water-rejective property to form a complete doped polycrystalline silicon layer.

Method of fabricating a recess channel array transistor

Method for producing element-isolation

This invention relates to a method for producing an element-isolation, particularly a method for producing an element-isolation with high anti-punch through power. The method comprises etching a slit on the silicon substrate, covering the aperture of the slit with a CVD silicon oxide as the field oxide thereby forming an element-isolation with high anti-punch through power.

Method of fabricating deep trench capacitor

A method of fabrication deep trench capacitors includes forming a plurality of deep trenches in a substrate. A bottom electrode is formed in the substrate surrounding the bottom of each deep trench. A capacitor dielectric layer and a first conductive layer are formed at the bottom of each deep trench. A collar oxide layer is formed on the sidewall of the deep trench exposed by the first conductive layer. A second conductive layer fills each deep trench. An opening is formed in a region predetermined for an isolation structure between adjacent deep trenches, wherein the depth of the opening is greater than that of the isolation structure. An isolation layer is filled in the opening.

Method of two-step backside etching

The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then, the hard masks and the substrate are patterned in sequence to form a plurality of trenches in the substrate. Finally, before performing a wet bath step, the edge of the substrate is backside-etched to remove needle structures on the edge of the substrate.

Semiconductor device and fabricating method thereof

A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of the gate structures. Removing the cap layer and spacers that are not covered by the mask layer. After the mask layer is removed, a dielectric layer is formed over the substrate covering the gate structures. A self-aligned contact hole is formed in the dielectric layer. A conductive layer is formed in the self-aligned contact hole and on the dielectric layer. Since the cap layer and spacers that are not covered by the mask layer are removed and substituted by the dielectric layer having lower dielectric constant property, the parasitic capacitance can be reduced.

Recessed channel transistor and method for preparing the same

Reconfigurable multiplexed address scheme for asymmetrically addressed DRAM

A long X bit or a long Y bit is stored in a latch and used to supplement the Y address bits in an asymmetric DRAM memory thereby to allow one part to be used for a design requiring a long X bit and also for a design requiring a long Y bit.

Two-step chemical mechanical polishing method

【要約】 【目的】 フュームド研磨剤を使用する研磨段階とコロ イダル研磨剤を使用する研磨段階でなる２段階研磨を行 い、工程時間を短縮するとともに研磨定盤・ポリシング パッドの切り換えを不要にする。 【構成】 先ず、フュームド研磨剤で第１段階の研磨を 行い、被研磨物の大部分を除去する。フュームド研磨剤 の砥粒は大きいので、研磨速度が速く短時間で必要な研 磨を終了できて半導体構造の表面平坦化を実現する。次 に、コロイダル研磨剤で第２段階の研磨を行い、被研磨 物の残り部分を除去する。コロイダル研磨剤の砥粒は小 さくて均一であるので、第１段階の研磨によって生じた 損傷を除去でき、表面損傷の少ない半導体構造の平坦表 面の均一性を向上させることができる。 Kind Code: A1 Abstract: A two-stage polishing is performed by a polishing step using a fumed abrasive and a polishing step using a colloidal abrasive, thereby shortening the process time and making it unnecessary to switch between a polishing platen and a polishing pad. First, a first stage polishing is performed with a fumed abrasive to remove most of the object to be polished. Since the abrasive grains of the fumed abrasive are large, the polishing speed is high and the required polishing can be completed in a short time, thereby realizing the planarization of the surface of the semiconductor structure. Next, the second stage polishing is performed with a colloidal abrasive to remove the remaining portion of the object to be polished. Since the abrasive grains of the colloidal abrasive are small and uniform, damage caused by the first-stage polishing can be removed, and the uniformity of the flat surface of the semiconductor structure with less surface damage can be improved.

Chemical mechanical polishing of a metal layer using a composite polishing pad

A method of polishing a wafer is disclosed. The wafer has formed thereon an oxide layer that has at least one via. A metal layer is formed on the oxide layer and in the via. The wafer is then polished against an outer portion of a polishing pad until the metal layer outside of the via has been removed. The outer portion has a first hardness. Next, the wafer is polished against an inner portion of the polishing pad. The inner portion of the polishing pad has a second hardness that is less than the first hardness.

Removal method of residual particles on wafer surface after planarization process

Two-slurry CMP polishing with different particle size abrasives

A method for chemical mechanical polishing (CMP) of a wafer having a top layer to be polished is disclosed. The method comprises the steps of: using a CMP apparatus to polish the top layer using a first slurry having abrasive particles of a first size; and using the CMP apparatus to polish the top layer using a second slurry having abrasive particles of a second size, the second size being smaller than the first size.

Addition of planarizing dielectric layer to reduce a dishing phenomena experienced during a chemical mechanical procedure used in the formation of shallow trench isolation regions

A process for fabricating silicon oxide filled, shallow trench isolation (STI), regions, in a semiconductor substrate, featuring the use of a disposable boro-phosphosilicate glass (BPSG), layer, used for planarization of various width, silicon oxide filled, STI regions, has been developed. After completely filling all STI shapes with a high density plasma (HDP), silicon oxide layer, resulting in a non-planar, HDP silicon oxide top surface topography, a BPSG layer is deposited. An anneal procedure is then performed resulting in a planar top surface topography of the reflowed BPSG layer. A chemical mechanical polishing procedure is next employed to remove the planar, reflowed BPSG layer, and portions of the underlying HDP silicon oxide, from the top surface of a silicon nitride stop layer, resulting in a planar top surface topography for all silicon oxide filled, insulator regions.

Self-aligned non-volatile memory and method of forming the same

A non-volatile memory is described. A substrate comprising a stacked layer is provided. A sacrificial layer is deposited and patterned to form a first opening. A first spacer is formed on sidewalls of the first opening, and the stacked layer is etched using the first spacer as a first mask to form a second opening. An isolation layer is formed in a portion of the first and the second openings, and a conductive filling layer is formed thereon. The stacked layer is etched using a portion of the conductive filling layer as a second mask.

Writing data to nonvolatile memory

In some embodiments, of the present invention, data are written to a plurality of nonvolatile memory cells (Q 0 , Q 15 ) as follows. A data writing signal is supplied to one of the memory cells (Q 0 ) but not to both of the memory cells. Then data writing signals are supplied to both of the memory cells simultaneously.

Method for forming bottle type slot

一种瓶型沟渠(bottle－shaped trench)的形成方法，包括下列步骤：提供一半导体衬底。于该半导体衬底中形成一沟渠。在该沟渠中形成一离子注入掩模层，露出该沟渠的上部侧壁表面。对上部侧壁表面进行一抑制氧化的离子注入工艺。去除该离子注入掩模层，露出该沟渠的下部侧壁表面以及底部表面。进行一热氧化工艺，使沟渠的表面形成一氧化层，其中上部侧壁表面上的氧化层厚度远小于下部侧壁表面以及底部表面的氧化层厚度。并且移除氧化层，而形成该瓶型沟渠。

Method for fabricating MOSFET element

一种金属氧化物半导体晶体管元件的制造方法，先以栅极与衬层为掩模进行一离子注入，在栅极两侧的基底中形成源极/漏极。然后蚀刻此衬层使其厚度减少，再进行另一离子注入以在源极/漏极轮廓的外围形成环掺杂区。此包围源极/漏极的环掺杂区较靠近沟道区且与源极/漏极重迭较少，因此，可同时维持稳定的元件开启电压并达到降低结漏电流的目的。

Method for preparing aqueduct type power transistor

一种沟渠式功率晶体管的制备方法，首先形成一具有多个开口的掩模层于一半导体基板上，并局部去除该开口下方的半导体基板以形成多个以阵列方式设置的沟渠于该半导体基板中。接着，涂布一覆盖该掩模层表面的光致抗蚀剂层。定义该光致抗蚀剂层并去除未被该光致抗蚀剂层覆盖的掩模层而形成一掩模区块，其定义该阵列区并曝露在该阵列区内的半导体基板。

Integrated circuit memory and its operation method

本发明提供一种用于集成电路记忆体的资料汇流排电路，包括用于将记忆体与I/O区块连接的每I/O垫4位元汇流排，但是仅将每I/O两位元用于写入，而每I/O垫4位元用于读取。在输入资料闪控讯号的每个下降边缘时，可经由汇流排传输后两个位元，故毋须精确地计数输入资料闪控脉冲。此外，该资料汇流排电路可相容于DDR1及DDR2操作模式。

Method of manufacturing deep trench capacitor storage electrode

Anisotropic formation process of oxide layers for vertical transistors

The method of the present invention forms a thin oxide layer on the circumferential wall of a recess in a trench and, at the same time, forms a thick oxide layer on the bottom surface of the recess. The thick oxide layer serves as the trench top oxide and the thin oxide layer serves as the gate oxide.

Reduction of reflection effects in photolithographic processes, used in semiconductor processing, comprises forming a dielectric anti-reflection coating layer below a hard mask layer

Reduction of photolithographic process reflection effects, by forming a dielectric anti-reflection coating (DARC) layer (32) below a hard mask layer (33), is new. Reflection effects are reduced during a photolithographic process by forming a DARC layer (32) on a substrate (30), applying a hard mask layer (33) and a photo lacquer and then carrying out the photolithographic process. Preferred Features: The hard mask layer consists of SiO2. An underlayer (31) may be applied to the substrate (30) prior to forming the DARC layer (32).

Chip package with esd protection structure

A chip package comprises a semiconductor chip, a plurality of pins coupled to the semiconductor chip, and a conductive structure configured to form an electrical connection between the pins, wherein the electrical connection is configured to be disabled as the chip package is inserted into a socket. Since the pins are electrically connected by the conductive structure, the surge current caused by an ESD event can be distributed to all pins rather than to a single pin as the ESD event occurs. Consequently, all ESD protection circuits connected to the pins can be used to dissipate the surge current during the ESD event, and the circuit damage caused by the ESD can be dramatically reduced.

Dynamic random access memory structure

A dynamic random access memory structure comprises a substrate having a first diffusion region and a second diffusion region, a dielectric structure overlaying the substrate, a capacitor contact plug disposed in the dielectric structure and connected to the first diffusion region, a bit-line contact plug disposed in the dielectric structure and connected to the second diffusion region, a metal silicide disposed on the capacitor contact plug, and a capacitive structure disposed on the dielectric structure and connected to the metal silicide.

Bonding pad structure

A bonding pad structure with a bonding pad with a circular shape or an elliptical shape. The circular or the elliptical bonding pad structure does not have any sharp angularity. It improves the stress concentration problem which results from the abrupt shrinkage of the cross section of the protective layer. The circular or the elliptical shape of the bonding pad structure can also prevent the abrupt shrinkage of the cross section of the protective layer due to the gradual change of angularity. Therefore, this kind of shape can disperse the stress and prevent the abruption on the protective layer after the bonding wire and packaging produces.

Method and apparatus for controlling backside pressure during chemical mechanical polishing

A plug for plugging selected perforations in a carrier assembly used in a chemical mechanical polishing system for polishing semiconductor wafers is disclosed. The plug comprises a pressure-resistant portion; a bottom portion attached to the pressure-resistant portion; and a leak-resistant portion extending from the pressure-resistant portion, dimensioned to fit snugly into the bottom portion.

A method of improving the surface uniformity of an anti-reflective coating used to make contact connections

Flash memory structure and method for fabricating the same

A flash memory structure comprises a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack having trapping sites interposed therein positioned on the V-groove, and a conductive layer positioned on the surface of the dielectric stack above the V-groove. A method for forming the V-groove comprises steps of forming a mask layer on the surface of the semiconductor substrate, forming an opening in the mask layer, etching a portion of the semiconductor substrate below the opening to form the V-groove, and removing the mask layer. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.

Semiconductor structure with partial etching grid and making method thereof

本发明涉及一种具有局部蚀刻栅极的半导体结构及其制作方法，该方法包括：提供一半导体衬底，在该半导体衬底上具有至少两邻近的栅极结构，其中上述栅极结构由形成在半导体衬底的一栅极介电层、一栅极导电层以及一上盖层所构成，且上述栅极结构的各侧边覆盖有一衬垫层；顺序形成一保护层和一掩膜层在上述栅极结构上；在掩膜层内定义出至少一开口，并蚀刻部分上述开口内的该保护层，以部分露出开口内两邻近栅极结构单一侧边上的衬垫层；蚀刻去除上述部分露出的衬垫层，且可选择地部分去除邻近该些露出衬垫层的栅极导电层；去除掩膜层和保护层；以及形成一间隔壁覆盖在上述栅极结构各侧壁上，以形成多个单一侧边具有局部蚀刻的栅极结构。

Semiconductor device comprising an undoped oxide barrier

The present invention relates to a semiconductor device comprising at least one gate located in each of a memory array area and a periphery circuit area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. The semiconductor device also comprises a barrier layer, which is located in the memory array area and the periphery circuit area, an undoped oxide barrier, which is located on the barrier layer in the periphery circuit area, and a boron-containing silicate glass, which is located on the barrier layer in the memory array area and on the undoped oxide barrier in the periphery circuit area.

Process for compensating for etching stress during etching of a semiconductor wafer comprises exposing a substrate bead from the edge of the wafer forming a pattern using photolacquer

Process for compensating for etching stress during etching of a semiconductor wafer comprises exposing a substrate bead from the edge of the wafer forming a pattern using photolacquer. Preferred Features: The bead of silicon is removed from the whole periphery of the wafer. The bead has a width of 1 mm and a depth of 7000-8000 angstroms. The bead is etched in the wafer with the simultaneous formation of deep trenches. Etching is carried out for 10 minutes.

Method and apparatus for wafer analysis

The present invention discloses method and apparatus for wafer analysis. First, a plurality of specific distribution maps, which respectively refer to a defect pattern distribution in a pattern group, is defined. Next, a plurality of distribution features is defined so that each specific distribution map correlates to one of the distribution features. Then, each pattern group on the wafer is compared to each specific distribution map in order to relate each pattern group to at least one of the specific distribution maps, and relate each pattern group on the wafer indirectly to at least one of the distribution features while allocating each distribution feature indirectly related to each pattern group with a respective relative value. Finally, the relative values of each distribution feature are totaled on the wafer respectively to obtain total values of the distribution features. With the method and apparatus disclosed in the present invention, it is easier to detect defective patterns on the wafer systematically and effectively.

Semiconductor device with Si-Ge layer-containing low resistance, tunable contact

The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si x Ge 1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Method of fabricating non-volatile memory device

Manufacturing method for improving the step coverage of titanium barrier capability

Trench isolation without grooving

A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

Levenson phase shifting mask and method for preparing the same and method for preparing a semiconductor device using the same

Levenson phase transfer mask and preparation method thereof, and method for preparing semiconductor element

本发明的雷文生相转移掩模的制备方法首先形成一金属层于一基板上，再利用微影及蚀刻工艺形成多个开口于该金属层中。之后，利用旋转涂布工艺形成一高分子层于该基板上，并利用一电子束照射该高分子层的一预定区域以形成一相转移图案，再去除未被该电子束照射的高分子层。该高分子层可由氢硅酸盐、甲基硅酸盐或混成有机硅烷高分子构成，而去除未被该电子束照射的高分子层可利用一碱性溶液、醇类溶液或乙酸丙酯溶液进行显影工艺，其中该碱性溶液系选自氢氧化钠溶液、氢氧化钾溶液及四甲基氢氧化铵溶液构成的组。

Process for etching in a plasma chamber comprises adjusting an upper electrode and a receiver, etching at a first distance over a first specified time, adjusting the upper electrode

Process for etching in a plasma chamber (101) comprises adjusting an upper electrode (111) and a receiver (105); carrying out etching at a first distance over a first specified time; adjusting the upper electrode and the receiver at a second distance second specified time; and carrying out etching at a second distance second specified time. Preferred Features: The first specified time is larger or smaller than the second specified time. The first distance is the maximum removal of the receiver and the upper electrode in the plasma chamber. The second distance is the minimum removal of the receiver and the upper electrode in the plasma chamber

Method for manufacturing high voltage transistor as well as transistor integrated with low voltage and high voltage

一种具有双扩散漏极的高压晶体管的制造方法，其优点为利用定义栅极图案的原有光致抗蚀剂来作为定义双扩散漏极的光致抗蚀剂，而不增加工艺的复杂度。先在衬底上依序形成介电层与导电层，然后在导电层上形成图案化的光致抗蚀剂。以光致抗蚀剂为蚀刻掩模来蚀刻导电层与介电层，以在衬底上形成栅极与栅介电层。稳定光致抗蚀剂的结构之后，进行第一离子掺杂工艺，以在栅极两侧的衬底中分别形成深结轻掺杂区。去除上述的光致抗蚀剂，再形成二间隙壁于栅极的侧壁。接着，进行第二离子掺杂工艺，以在间隙壁外侧的衬底中分别形成重掺杂区。本发明还涉及一种低压晶体管与具有双扩散漏极的高压晶体管的整合制造方法。

Control of air gap position in a dielectric layer

A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at least two features and a substrate and an air gap is formed between the at least two features and above the feature height. The first dielectric layer is etched between the at least two features to open the air gap. Then a second dielectric layer is deposited over the etched first dielectric layer to form an air gap between the at least two features and completely below the feature height.

Integrated circuit memory and its operation method

本发明提供一种用于集成电路记忆体的资料汇流排电路，包括用于将记忆体与I/O区块连接的每I/O垫4位元汇流排，但是仅将每I/O两位元用于写入，而每I/O垫4位元用于读取。在输入资料闪控讯号的每个下降边缘时，可经由汇流排传输后两个位元，故毋须精确地计数输入资料闪控脉冲。此外，该资料汇流排电路可相容于DDR1及DDR2操作模式。

Production of trench isolation regions in a semiconductor substrate

Verfahren zur Herstellung von mit Siliziumoxid gefüllten flachen Grabenisolierungs-Bereichen in einem Halbleitersubstrat, wobei eine entsorgbare, aufgeschmolzene Schicht aus Borphosphorsilikat oberhalb einer Siliziumoxidschicht verwendet wird, und die Borphosphorsilikat-Schicht dazu eingesetzt wird, die Einebnung der mit Siliziumoxid gefüllten flachen Grabenisolienungs-Bereiche zu optimieren, mit folgenden Schritten: Ablagern einer ersten Siliziumoxidschicht (2) auf dem Halbleitersubstrat (1); Ablagern einer Siliziumnitridschicht (3); Ausbilden von flachen Grabenisolierungs-Formen (4) mit einer ersten Breite und von flachen Grabenisolierungs-Formen (5) mit einer zweiten Breite in der Siliziumnitridschicht (3), in der ersten Siliziumoxidschicht (2), und in einem oberen Abschnitt des Halbleitersubstrats (1); thermisches Aufwachsen einer Siliziumoxidauskleidungsschicht (6) auf den freigelegten Oberflächen des Halbleitersubstrats (1) in den flachen Grabenisolierungs-Formen (4; 5); Ablagern einer zweiten Siliziumoxidschicht (7) mit einem Plasma hoher Dichte auf der Siliziumnitridschicht (3), und vollständiges Füllen der flachen Grabenisolierungs-Formen (4, 5) mit der ersten Breite und der zweiten Breite; Ablagern der Borphosphorsilikat-Schicht (8) auf...

Automated experimental result evaluation for wafer manufacture in semiconductor factory, involves comparing condition of attributes after each experiment, and listing out mismatching attributes in separate table

The attributes corresponding to varying control factors are tabulated in a look-up table, and an evaluation table is generated by comparing the condition of the attributes after each experiment. The specific attributes which do not match with the other ones are listed individually in another table.

Manufacturing a semiconductor wafer according to the process time by process tool

A semiconductor process for manufacturing a wafer. First, a previously predicted process rate and a previously measured process rate are provided by a process tool. Next, a presently predicted process rate is obtained by a first linear equation having a first variable weighting factor using the previously predicted process rate and the previously measured process rate as variables. Next, a process time is obtained according to the presently predicted process rate and a predetermined process target to input to the process tool. Finally, the wafer is manufactured according to the process time by the process tool.

Flash Memory Structure and Fabrication Method Thereof

A flash memory structure comprises a semiconductor substrate, a source region, a drain region, a first insulating dielectric layer, a floating gate, a second insulating dielectric layer, and a control gate. The semiconductor substrate has a first top surface and a second top surface that is lower than the first top surface. The source region and the drain region are respectively in the second top surface and the first top surface of the semiconductor substrate, and the semiconductor substrate connecting the source region and the drain region is a vertical channel region. The whole channel region is covered by the first insulating dielectric layer, the floating gate, the second insulating dielectric layer, and the control gate in turn.

Wafer yield detect method

Physical vapor deposition process and apparatus

一种物理气相沉积设备，此沉积设备由一反应室与一电磁铁磁控装置所构成，此电磁铁磁控装置配置于反应室的外部上方。其中当于进行物理气相沉积工艺时，临场反转此电磁铁磁控装置的磁极，因此可以解决开口侧壁的不对称沉积的问题。

Reduced device count level shifter with power savings

A level shifting circuit includes an input node, an output node, a first power supply node, a second power supply node, a third power supply node, an inverter coupled to the first and second power supply nodes having an input coupled to the input node and an output, a transistor having a current path coupled between the output of the inverter an the output node, a first transistor circuit coupled between the first power supply node and the third power supply node having a first input coupled to the output of the inverter, a second input coupled to the output node, and an output, and a second transistor circuit coupled between the output node and the third power supply node having a first input coupled to the output of the first transistor circuit and a second input coupled to the input node.

Batch treatment apparatus and wafer treatment method

本发明提供一种批式处理装置及晶片处理方法，该批式处理装置至少包括：一晶舟，该晶舟的一第一端部至一第二端部之间具有多个晶片插槽，且此些晶片插槽使配置于其中的晶片以晶片表面互相平行，其中此些晶片插槽的间距由晶舟的第一端部朝向第二端部逐渐增加；和一气体入口，其中该气体入口由该第一端部朝向该第二端部提供一气体，以使该气体与该些晶片反应。此晶舟能够配置于一垂直式热炉管中，其中第一端部配置于底部，第二端部则位于顶部。使用具有此晶舟的垂直式热炉管进行晶片处理工艺时，能够缩小同一批处理的晶片的电性差异，以及沉积薄膜的特性差异。

Plasma chamber with erosion resistive securement screws

An apparatus is provided for treating a wafer under fabrication with an erosive plasma, in a contamination controlled environment. The apparatus includes a chamber for containing the wafer to be treated by the plasma, and for isolating the wafer from contaminants external to the chamber during treatment. The chamber also includes one or more plasma erosion resistive screws. Each screw has a shaft secured within the chamber so that the shaft is unexposed to the plasma, and a raised head which is integral with, and made of the same material as, the shaft. The head has a continuous, surface shape with a reduced number of edges so as to reduce the accumulation of charge thereon, thereby resisting erosion by the plasma.

Physical vapor deposition process and apparatus

一种物理气相沉积设备，此沉积设备由一反应室与一电磁铁磁控装置所构成，此电磁铁磁控装置配置于反应室的外部上方。其中当于进行物理气相沉积工艺时，临场反转此电磁铁磁控装置的磁极，因此可以解决开口侧壁的不对称沉积的问题。

Wall embedded grid structure and its making method

一种嵌壁式栅极结构包含半导体基板、设置于该半导体基板中之沟槽、设置于该沟槽内之栅氧化层以及设置于该栅氧化层上之导电层，其中该沟槽内之半导体基板呈多层阶梯结构。该多层阶梯结构之各阶梯表面的栅氧化层厚度可不相同。此外，该嵌壁式栅极结构另包含多个设置于该多层阶梯结构下方之半导体基板中的掺杂区，且各阶梯下之掺杂区之掺杂浓度及掺质种类可不相同。该多阶式栅极结构之载流子通道的整体长度为该多层阶梯结构之宽度(W)及二倍高度(2H)之总和。

Shallow trench isolation structure and method for forming the same

A method for forming shallow trench isolation structures is provided. The method comprises the following steps: providing a substrate with a “v” shaped trench, forming a first dielectric layer to cover the upper portion of the inner wall of the trench; conducting the first etching process to pull back the uncovered inner wall of the trench; removing the first dielectric layer; and forming a second dielectric layer to cover the trench and form a void inside the trench.

Aligning marker capable of correcting manufacturing deviation and aligning method thereof

本发明公开了一种可校正制造工艺偏差的对准标记及其对准方法，该方法应用至少两个具有宽度逐渐缩减至零的两端点的沟槽作为对准标记。利用沟槽宽度为零时由位于沟槽上的具有不对称轮廓的薄膜所造成的偏移误差也随之为零的特点，来再现前一层的对准目标的位置。

Vortex mask and method for preparing the same and method for preparing a circular pattern using the same

Method of selectively etching HSG layer in deep trench capacitor fabrication

Method for manufacturing a memory structure

Production of a capacitor used in DRAM cells comprises forming a silicon nitride layer on a substrate, depositing a borosilicate glass layer, forming a pattern, etching to form trenches

Production of a capacitor comprises forming a silicon substrate (10); forming a silicon nitride layer (12) on the substrate; depositing a borosilicate glass layer on the silicon nitride layer; forming a pattern and establishing the borosilicate glass layer to expose two regions of the silicon substrate which are separated by a mask which contains the glass layer and the silicon nitride layer; etching both regions of the substrate to form trenches; depositing a silicon nitride layer on the side walls of the trench to form a dielectric layer; and removing doped polysilicon in the trenches to form a single capacitor. Preferred Features: Etching is carried out by reactive etching. The mask has a width of approximately 50 nm. The borosilicate glass layer is depositing in a thickness of 5500 A.

Method for identifying the best tool in a semiconductor production line, requires outputting a weighted yield difference for each tool

A computer-implemented method for identifying the best tool among several tools which execute the same operation in a semiconductor fabrication line involves initially determining a first average value yield for each of the several tools within a first time interval and then weighting the first average value yield on the basis of the total number of wafers which are processed by each of the tools within the first time interval. A second average value yield is then determined for the semiconductor-fabrication line in the first time interval followed by obtaining a weighted yield difference for each of the tools in relation to the second average value yield, and then outputting the weighted yield difference for each of the tools.

[multi-gate dram with deep-trench capacitor and fabrication thereof]

A multi-gate DRAM cell is described, including a multi-gate transistor and a deep trench capacitor. The transistor includes a semiconductor pillar, a multi-gate, a gate dielectric layer, a first and a second source/drain regions. The pillar is beside the deep trench capacitor not overlapping with the latter. The multi-gate is at least on three sidewalls of the pillar separated by the gate dielectric layer, and can be a treble gate or a surrounding gate. The first source/drain region is in the top portion of the pillar, and the second source/drain region in the pillar coupling with the deep trench capacitor.

Polishing tool used for CMP

A polishing tool used for a CMP process is disclosed. The polishing tool includes a polishing platen for holding a wafer faced-up thereon and carrying the wafer to move to and fro between a first position and a second position, a polishing pad for polishing the wafer, and a holder for holding the polishing pad to self-rotate and carrying the polishing pad to move across the wafer surface and further driving the polishing pad to polish the wafer.

Method and structure for preventing barrier layer from being over etched and application thereof

本发明公开了一种防止阻挡层被过度蚀刻的方法及半导体结构，其可以减缓阻挡层在后续硼磷硅玻璃蒸汽步骤中厚度变薄，该方法包括步骤：提供一形成有多个栅极结构的半导体基底；保形地形成一阻挡层覆盖该多个栅极结构；保形地形成一保护介电层于该阻挡层上；以及形成一层间介电层覆盖该多个栅极结构并填满该多个栅极结构之间。本发明还公开了使用该方法形成接触窗的方法。

Nonvolatile memory cell with multiple floating gates formed after the select gate

In a memory cell ( 110 ) having multiple floating gates ( 160 ), the select gate ( 140 ) is formed before the floating gates. In some embodiments, the memory cell also has control gates ( 170 ) formed after the select gate. Substrate isolation regions ( 220 ) are formed in a semiconductor substrate ( 120 ). The substrate isolation regions protrude above the substrate. Then select gate lines ( 140 ) are formed. Then a floating gate layer ( 160 ) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric ( 164 ) is formed over the floating gate layer, and a control gate layer ( 170 ) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates ( 160 ). A dielectric layer ( 164 ) overlying the floating gate has a continuous feature that overlies the floating gate and also overlays a sidewall of the select gate ( 140 ). Each control gate ( 160 ) overlies the continuous feature of the dielectric layer and also overlies the floating gate. In another aspect, substrate isolation regions ( 220 ) are formed in a semiconductor substrate. Select gate lines cross over the substrate isolation regions. Each select gate line has a planar top surface, but its bottom surface goes up and down over the substrate isolation regions. Other features are also provided.

Process for the formation of dielectric layers with air pockets

Semiconductor structure with locally-etched gate and method of manufacturing same

Semiconductor device and manufacturing method thereof

Method of fabricating a recess channel transistor

A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semiconductor layer. An implantation process is performed with a tilt angle on sidewalls of the trench to form an implant area. A thermal oxidation process is performed to form an oxide layer. The oxide layer comprises a first thickness on the source/drain in the sidewalls of the trench and a second thickness on the other portion in the sidewalls of the trench.

Phase change memory device and fabrications thereof

Phase-change memory cell structures and methods for fabricating the same

Efficient register for additive latency in DDR2 mode of operation

An additive latency circuit for a DDR2 standard compliant integrated circuit memory includes a half flip-flop register assigned for each case of additive latency. A unique clock is generated to control each bit in the register chain. Sufficient register bits are required in the chain to support the highest additive latency specified. For latency settings less than the maximum, those clocks assigned to the bits above the chosen latency are enabled so the data passes through un-clocked. For the additive latency zero case, a separate bypass path is provided. Both address and command information is delayed by the additive latency delay chain. Once delayed by the proper number of cycles, the address information remains in that state until the time when a new state is required. Command information remains valid for one cycle upon reaching the proper delay point. A reset circuit is provided to reset command signals.

Confinement ring for wafer fixation

DRAM cell structure with buried surrounding capacitor and process for manufacturing the same

A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

A method for forming a shallow trench isolation structure with reduced stress

Slurry feeder and method thereof

(57)【要約】 【課題】 スラリー容器と管路とに音波発振器を配設し て、研磨剤の凝集・凝固を防止し、良好なスラリーを化 学的機械研磨装置に供給する。 【解決手段】 スラリーを充填するスラリー容器と、緩 衝供給タンクと、少なくとも２つの音波発振器と、パル ス制御器とを備え、管路を介して緩衝供給タンクへスラ リーを供給するスラリー容器に１つの音波発振器が配設 され、緩衝供給タンクから化学的機械研磨装置へスラリ ーを提供する管路にもう１つの音波発振器が配設される ものであって、パルス制御器が２つの音波発振器に電気 接続されて、２つの音波発振器の発振周波数を約５ＫＨ ｚ〜５ＭＨｚ、発振時間を約１〜３分間、発振間隔を約 １〜５分間毎に１回となるように制御するものである。

Low voltage differential amplifier circuit and bias control technique enabling accommodation of an increased range of input levels

Manufacturing method of bottle-shaped deep trench

Photolithography system with a frequency domain filter mask

Verfahren zur Verbesserung eines Fotolithografieverfahrens mit den Schritten: Anordnen eines Phasenverschiebungsfilters (308) zwischen einer ersten fokussierenden Linse (306) und einer zweiten fokussierenden Linse (310), wobei der Phasenverschiebungsfilter (308) eine in eine Richtung linear variierende Opazität aufweist und derart ausgebildet ist, dass eine Phasenverschiebung in einem Gebiet des Phasenverschiebungsfilters erzeugt wird, das von dem Mittelpunkt des Phasenverschiebungsfilters zu einem seitlichen Rand des Phasenverschiebungsfilters reicht; Anordnen der ersten Linse (306) und der zweiten Linse (310) zwischen einer Belichtungsretikelmaske (304) und einem Wafer (312), wobei die Retikelmaske (304) ein Maskenmuster (330) aufweist; und Ausrichten einer Lichtquelle (302), der ersten Linse (306), des Phasenverschiebungsfilters (308), der zweiten Linse (310) und des Wafers (312) entlang einer Achse (314); wobei durch Projizieren von Licht der Lichtquelle (302) durch die Retikelmaske (304), die erste Linse (306), den Phasenverschiebungsfilter (308), und die zweite Linse (310) auf den Wafer (312) unmittelbar nach dem Durchgang durch... Method of improving a photolithography method comprising the steps of: Arranging a phase shift filter (308) between a first focusing lens (306) and a second focusing lens (310), the phase shift filter (308) having unidirectionally varying opacity and being configured to have a phase shift in a region of the phase shift filter is generated, which extends from the center of the phase shift filter to a lateral edge of the phase shift filter; Arranging the first lens (306) and the second lens (310) between an exposure reticle mask (304) and a wafer (312), the reticle mask (304) having a mask pattern (330); and Aligning a light source (302), the first lens (306), the phase shift filter (308), the second lens (310) and the wafer (312) along an axis (314); wherein, by projecting light from the light source (302) through the reticle mask ( ...

Method for molecular nitrogen implantation dosage monitoring

A method for estimating molecular nitrogen implantation dosage. The semiconductor wafers are first implanted with various concentration of molecular nitrogen. After implantation, the implanted wafers and a non-implanted wafer are subjected to thermal process to grow oxide layer. The thickness of oxide layer on the wafers with various implantation dosage is measured. Because implanted nitrogen on the wafers suppresses the growth of oxide layer, a suppression ratio is computed from the difference in thickness of the oxide layer between the implanted and non-implanted semiconductor wafers to stand for the thickness variation. Then, a relation between the suppression ratio and the dosages of molecular nitrogen is built. A molecular nitrogen dosage needed to grow a predetermined thickness of oxide layer on a process wafer is computed by inputting the predetermined thickness into the relation.

Inspecting method and adjusting method of pressure of probe

Phase shift alignment system

Efficient register for additive latency in DDR2 mode of operation

An additive latency circuit for a DDR2 standard compliant integrated circuit memory includes a half flip-flop register assigned for each case of additive latency. A unique clock is generated to control each bit in the register chain. Sufficient register bits are required in the chain to support the highest additive latency specified. For latency settings less than the maximum, those clocks assigned to the bits above the chosen latency are enabled so the data passes through un-clocked. For the additive latency zero case, a separate bypass path is provided. Both address and command information is delayed by the additive latency delay chain. Once delayed by the proper number of cycles, the address information remains in that state until the time when a new state is required. Command information remains valid for one cycle upon reaching the proper delay point. A reset circuit is provided to reset command signals.

Chemical-mechanical polishing method and apparatus

Contact chain total resistance measurement method for testing semiconductor chips, involves measuring voltage and current in probe pads to obtain total resistance, by selectively connecting n-type doped layers to substrate

The contact structures having a contact hole (38) which is electrically connected to n-type doped layer and a pair of ends coupled to probe pads, are connected in series. The n-type doped layers (32a,32b) are selectively connected to a substrate, and the voltage across the pair of probe pads and current through any one probe pad are measured to obtain total resistance on powering the contact chain. An Independent claim is included for contact structure debugging method.

Tungsten deposition process

A tungsten deposition process. A crystal growth step is carried out in a reaction chamber to form a tungsten crystal layer over a substrate using tungsten hexafluoride, silane and nitrogen as reactive gases. An intermediate step is conducted such that the supply of tungsten hexafluoride to the reaction chamber is cut but the supply of silane is continued. Furthermore, nitrogen is passed into the reaction chamber selectively. A main deposition step is finally conducted to form a tungsten layer over the tungsten crystal layer using tungsten hexafluoride, hydrogen and nitrogen as reactive gases.

Phase change memory device and fabrication method thereof

A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.

Furnace boat-push device

Trench capacitor and process for preventing parasitic leakage

A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of the trench and performing an annealing process on the doping layer to form a dopant region in the substrate adjacent to each sidewall of the trench and blocks leakage current from a parasitic transistor adjacent to the trench.

Manufacture method of deep trench capacitor storage node

Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures

In a nonvolatile memory, the select gates ( 144 S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines ( 144 ) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an dielectric ( 302, 304, 310 ) formed over control gate lines ( 134 ). Each control gate line provides control gates for one column of the memory cells. The adjacent control gate lines for the adjacent memory columns are spaced from each other. The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates ( 120 ) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Dynamic random access memory cell and fabrication thereof

A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The vertical transistor includes a first doped region, a second doped region, a gate and a gate insulating layer. The first doped region is located in the sidewall and is coupled with the capacitor. The second doped region is located in a top portion of the pillar. The gate is disposed on the sidewall of the pillar between the first and the second doped regions, and the gate insulating layer is disposed between the sidewall and the gate.

Anisotropic manufacturing process of oxide layers in a substrate trench

Verfahren zur Bildung einer dicken Oxidschicht (211) auf einer Unterseitenfläche (209) einer Vertiefung (208) und einer dünnen Oxidschicht (212) auf einer Umfangswand (210) der Vertiefung (208), wobei die Vertiefung (208) ein Teil eines in einem Substrat (201) gebildeten Grabens (204) ist, und wobei die Umfangswand (210) senkrecht zu der Unterseitenfläche (209) angeordnet ist, mit den Schritten: Implantieren von Inertgas-Ionen in die Unterseitenfläche (209) in einer Richtung, die im Wesentlichen parallel zu der Umfangswand (210) ist; und thermisches Prozessieren des Substrats (201) durch einen thermischen Oxidationsprozess, um die dicke Oxidschicht (211) auf der Unterseitenfläche (209) und die dünne Oxidschicht (212) an der Umfangswand (210) zu bilden.

A process for producing a tungsten glycol gate having a nitride barrier layer formed by a rapid thermal process

Verfahren zur Ausbildung eines Gates auf einem Halbleitersubstrat (40), mit folgenden Schritten: Ausbildung einer Gateoxidschicht (44) auf dem Substrat (40); Ausbildung einer Polysiliziumschicht (46) oben auf der Gateoxidschicht (44); Ausbildung einer Wolframsilizidschicht (52) über der Polysiliziumschicht (46); Ausbildung einer Wolframnitridsperrschicht (56) oben auf der Wolframsilizidschicht (52) unter Verwendung eines schnellen thermischen Prozesses unter Verwendung eines stickstoffhaltigen Gases und unter einem Druck von einer Atmosphäre; und Musterbildung und Ätzung der Wolframnitridsperrschicht (56), der Wolframsilizidschicht (52), der Polysiliziumschicht (46) und der Gateoxidschicht (44), um das Gate auszubilden. Method for forming a gate on a semiconductor substrate (40), comprising the following steps: Forming a gate oxide layer (44) on the substrate (40); Forming a polysilicon layer (46) on top of the gate oxide layer (44); Forming a tungsten silicide layer (52) over the polysilicon layer (46); Forming a tungsten nitride barrier layer (56) on top of the tungsten silicide layer (52) using a rapid thermal process using a nitrogen-containing gas and under a pressure of one atmosphere; and Patterning and etching the tungsten nitride barrier layer (56), the tungsten silicide layer (52), the polysilicon layer (46), and the gate oxide layer (44) to form the gate.

Method for preparing gate oxide layer

Method for forming gate structure with local pulled-back conductive layer and its use

A method for forming a gate structure with a pulled-back conductive layer and the use of the method are provided. The method conducts a local, not global, pull-back process on the conductive layer of the gate structure at the position intended for contact window formation, wherein the pull-back process is conducted after rapid thermal oxidation to prevent CBCB short, CB open and/or CBGC short.

Method for making complementary MOS field-effect transistor

一种利用离子注入及厚侧壁隔离层制程的互补型金属氧化物半导体场效应晶体管的制造方法，其步骤如下：制造硅衬底，进行离子注入，形成轻掺杂漏极；形成侧壁隔离层；应用第一光掩模形成N型离子注入区；应用第二光掩模形成P型离子注入区；在场氧化层和晶体管上淀积绝缘层；应用第三光掩模形成氧化层与栅极间的接触窗；本方法可有效地解决当元件尺寸缩小时所产生的穿透效应，可减少使用光掩模的次数并可保证质量。

Data sensing method for dynamic random access memory

Atomic layer deposition of interpoly oxides in a non-volatile memory device

Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

Method for planarizing a shallow trench isolation

A method of planarizing an isolation region. Key elements of the invention include the two chemical-mechanical polish (CMP) steps and the CMP stop structure comprised of a sacrificial oxide layer and the second nitride layer. First a pad oxide layer, a first nitride layer, a sacrificial oxide layer and a second nitride layer are formed over a substrate. A trench is formed through the pad oxide layer, the first nitride layer, the sacrificial oxide layer and the second nitride layer and in the substrate. An oxide layer is deposited filling the trench and over the second nitride layer. The oxide layer is preferably formed by a high density plasma chemical vapor deposition (HDPCVD) deposition. In a first CMP step, we chemical-mechanical polish the oxide layer and the second nitride layer down to a level. The second nitride layer and the sacrificial oxide layer are then removed. In the second CMP step, we chemical-mechanical polish the oxide layer and the first nitride layer so that the oxide layer is level with the first nitride layer. The invention reduces dishing effects.

Phase-change memory and fabrication method thereof

Method for preparing a MOS transistor

New integration process for the formation of elevated contacts for sub-150nm devices

Ein Verfahren zur Ausbildung von Kontakten bei der Herstellung eines integrierten Schaltkreis-Bauelements, das umfasst: Bereitstellen von Halbleiter-Bauelementstrukturen in und auf einem Substrat (10); Bedecken der Halbleiter-Bauelementstrukturen mit einer dielektrischen Schicht (40); Ätzen durch die dielektrische Schicht (40), um erste Öffnungen (50, 52) zu dem Substrat (10) auszubilden; Amorphisieren einer Oberfläche des Substrats (10) an Stellen, an denen es in den ersten Öffnungen (50, 52) freigelegt ist; selektives Ausbilden einer Polysiliziumschicht (120) auf der amorphisierten Substratoberfläche; Implantieren von Ionen in die Polysiliziumschicht (120), um erhobene Kontakte auszubilden; darauf folgend Ätzen durch die dielektrische Schicht (40) um zweite Öffnungen (54) zu Gates auszubilden; und Füllen der ersten (50, 52) und zweiten (54) Öffnungen mit einer leitenden Schicht (170), um die Ausbildung der Kontakte zu vervollständigen bei der Herstellung des integrierten Schaltkreis-Bauelements. A method of forming contacts in the manufacture of an integrated circuit device, comprising: Providing semiconductor device structures in and on a substrate (10); Covering the semiconductor device structures with a dielectric layer (40); Etching through the dielectric layer (40) to form first openings (50, 52) to the substrate (10); Amorphizing a surface of the substrate (10) at locations where it is exposed in the first openings (50, 52); selectively forming a polysilicon layer (120) on the amorphized substrate surface; Implanting ions into the polysilicon layer (120) to form raised contacts; thereafter etching through the dielectric layer (40) to form second openings (54) to gates; and Filling the first (50, 52) and second (54) openings with a conductive layer (170) to complete the formation of the contacts in the fabrication of the integrated circuit device.

Wafer supporting plate

A wafer supporting plate suitable for supporting a wafer during a semiconductor-forming process. In particular, the present invention relates to a wafer supporting plate capable of sensing the positioning condition of the wafer on the supporting plate during a heat treatment or other semiconductor-forming processes for detecting whether the wafer is being positioned normally on the supporting plate. The wafer supporting plate comprises a supporting plate body, at least three supporting props disposed on the supporting plate body for receiving and supporting a wafer, at least three sensing devices each disposed besides the supporting props and within the range encircled by the supporting props on the supporting plate body respectively. Furthermore, the wafer supporting plate of the present invention is provided with a logic circuit connected to the sensing devices which can be triggered by the sensing devices to suspend the semiconductor-forming process being performed on the wafer as soon as one of the sensing devices detects an abnormality in the positioning condition of the wafer at the location of the supporting props.

Via etch post-clean process

Method for preventing formation of defects in cmp method

(57)【要約】 （修正有） 【課題】 CMPにおける凹陥及びエロ―ジョンの生成を 防止する方法の提供。 【解決手段】 半導体基板１０表面に順次に第１の誘電 層１４とウェットエッチング速度が該第１の誘電層のそ れより小さい第２の誘電層１６とを形成し、所定のコン タクトホールのエリアに複数の第１の孔（前記第２の誘 電層を貫通し前記第１の誘電層に所定の深さで嵌入す る）をドライエッチングで形成する。次に、前記第１の 孔内において前記第１の誘電層を横方向にエッチング し、前記複数の所定のコンタクトホールのエリアに複数 の第２の孔（その開口の径と前記所定のコンタクトホー ルのエリアの径との比が0.55より小さい）をウェットエ ッチングプロセスで形成する。各前記第２の孔を充填す るように電気伝導層２２を形成し、前記電気伝導層表面 と前記第２の誘電層表面とが同一表面となるように前記 電気伝導層を部分的に除去するためにCMPプロセスを実 施する。