УСТРОЙСТВО АКТИВНОЙ ЗОНЫ УРАН-ГРАФИТОВОГО РЕАКТОРА

Устройство активной зоны уран-графитового реактора, образованное нижней, боковой и верхней металлоконструкциями, внутри которых заключена графитовая кладка с отражателями и вертикальными трактами технологических каналов, каналов системы управления и защиты, каналов охлаждения отражателя и коллектора парогазовой смеси, отличающееся тем, что в боковом отражателе в районе коллектора, между трактами технологических каналов и трактами каналов охлаждения отражателя, выполнен хотя бы один канал для размещения облучаемого материала. (19) RU (11) (13) 9 083 U1 (51) МПК G21C 1/12 (1995.01) C30B 31/20 (1995.01) РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К СВИДЕТЕЛЬСТВУ (21), (22) Заявка: 98112823/20, 15.07.1998 (46) Опубликовано: 16.01.1999 U 1 9 0 8 3 R U (54) УСТРОЙСТВО АКТИВНОЙ ЗОНЫ УРАН-ГРАФИТОВОГО РЕАКТОРА (57) Формула полезной модели Устройство активной зоны уран-графитового реактора, образованное нижней, боковой и верхней металлоконструкциями, внутри которых заключена графитовая кладка с отражателями и вертикальными трактами технологических каналов, каналов системы управления и защиты, каналов охлаждения отражателя и коллектора парогазовой смеси, отличающееся тем, что в боковом отражателе в районе коллектора, между трактами технологических каналов и трактами каналов охлаждения отражателя, выполнен хотя бы один канал для размещения облучаемого материала. Ñòðàíèöà: 1 U 1 (73) Патентообладатель(и): Государственное предприятие "Ленинградская атомная электростанция им.В.И.Ленина", Закрытое акционерное общество Научно-производственное объединение "Энергоатоминвент" 9 0 8 3 (72) Автор(ы): Лебедев В.И., Гарусов Ю.В., Павлов М.А., Шмаков Л.В., Ковалев С.М., Пеунов А.Н., Бугаков И.М. R U Адрес для переписки: 188537 Ленинградская обл.Сосновый Бор, Ленинградская АЭС главному инженеру ЛАЭС Гарусову Ю.В. (71) Заявитель(и): Государственное предприятие "Ленинградская атомная электростанция им.В.И.Ленина", Закрытое акционерное общество Научно- ...

Hybrid Silicon Wafer

A hybrid silicon wafer which is a silicon wafer having a structure wherein monocrystalline silicon is embedded in polycrystalline silicon that is prepared by the unidirectional solidification/melting method. The longitudinal plane of crystal grains of the polycrystalline portion prepared by the unidirectional solidification/melting method is used as the wafer plane, and the monocrystalline silicon is embedded so that the longitudinal direction of the crystal grains of the polycrystalline portion forms an angle of 120° to 150° relative to the cleaved surface of the monocrystalline silicon. Thus provided is a hybrid silicon wafer comprising the functions of both a polycrystalline silicon wafer and a monocrystalline wafer.

Method for Fabricating Black Silicon by Using Plasma Immersion Ion Implantation

A method for fabricating black silicon by using plasma immersion ion implantation is provided, which includes: putting a silicon wafer into a chamber of a black silicon fabrication apparatus; adjusting processing parameters of the black silicon fabrication apparatus to preset scales; generating plasmas in the chamber of the black silicon fabrication apparatus; implanting reactive ions among the plasmas into the silicon wafer, and forming the black silicon by means of the reaction of the reactive ions and the silicon wafer. The method can form the black silicon which has a strong light absorption property and is sensitive to light, and has advantages of high productivity, low cost and simple production process.

Architectural construct having a plurality of implementations

An architectural construct is a synthetic material that includes a matrix characterization of different crystals. An architectural construct can be configured as a solid mass or as parallel layers that can be on a nano-, micro-, and macro-scale. Its configuration can determine its behavior and functionality under a variety of conditions. Implementations of an architectural construct can include its use as a substrate, sacrificial construct, carrier, filter, sensor, additive, and catalyst for other molecules, compounds, and substances, or may also include a means to store energy and generate power.

Method and jig for holding silicon wafer

Provided are a method and a jig for holding a silicon wafer, which are applied to the production of the silicon wafer having {110} or {100} plane as its principal surface, in which the silicon wafer is held while a silicon wafer holding positions are properly defined at wafer edge regions relative to the reference direction as being from the center of the silicon wafer toward <110> in crystal orientation in parallel to the wafer surface. In handling the silicon wafer, generation of contact scratches is suppressed as little as possible, and a fracture which is caused by development of the crack initiating from easily generated contact scratches can be prevented in the silicon wafer, particularly in the silicon wafer having {110} plane as its principal surface.

Method of semiconductor film stabilization

Embodiments of the invention generally relate to methods for forming silicon-germanium-tin alloy epitaxial layers, germanium-tin alloy epitaxial layers, and germanium epitaxial layers that may be doped with boron, phosphorus, arsenic, or other n-type or p-type dopants. The methods generally include positioning a substrate in a processing chamber. A germanium precursor gas is then introduced into the chamber concurrently with a stressor precursor gas, such as a tin precursor gas, to form an epitaxial layer. The flow of the germanium gas is then halted, and an etchant gas is introduced into the chamber. An etch back is then performed while in the presence of the stressor precursor gas used in the formation of the epitaxial film. The flow of the etchant gas is then stopped, and the cycle may then be repeated. In addition to or as an alternative to the etch back process, an annealing processing may be performed.

Semiconductor Structure and Method

A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

METHOD FOR CONTROLLING DONOR CONCENTRATION IN Ga2O3 SINGLE CRYSTAL BODY, AND METHOD FOR FORMING OHMIC CONTACT

Provided is a method for controlling a donor concentration in a GaO-based single crystal body. In addition, an ohmic contact having a low resistance is formed between a GaO-based single crystal body and an electrode. A donor concentration in a GaO-based single crystal body is controlled by a method which includes a step wherein Si, which serves as a donor impurity, is introduced into the GaO-based single crystal body by an ion implantation method at an implantation concentration of 1×10cmor less, so that a donor impurity implanted region is formed in the GaO-based single crystal body, the donor impurity implanted region having a higher donor impurity concentration than the regions into which Si is not implanted, and a step wherein Si in the donor impurity implanted region is activated by annealing, so that a high donor concentration region is formed. 1. A method for controlling a donor concentration in a GaOsingle crystal body , comprising:{'sub': 2', '3', '2', '3, 'sup': 20', '−3, 'introducing Si as a donor impurity into the GaOsingle crystal body by an ion implantation method at an implantation concentration of not more than 1×10cmso as to form a donor impurity implanted region in the GaOsingle crystal body, the donor impurity implanted region having a higher donor impurity concentration than a region into which the Si is not implanted; and'}activating the Si in the donor impurity implanted region by annealing so as to form a high donor concentration region.2. The method for controlling a donor concentration in a GaOsingle crystal body according to claim 1 , wherein the implantation concentration is not less than 1×10cm.3. The method for controlling a donor concentration in a GaOsingle crystal body according to claim 2 , wherein the implantation concentration is not less than 1×10cmand not more than 1×10cm.4. The method for controlling a donor concentration in a GaOsingle crystal body according to claim 3 , wherein the implantation concentration is not less than 2 ...

APPARATUS AND METHOD FOR NEUTRON TRANSMUTATION DOPING OF SEMICONDUCTOR WAFERS

An apparatus for processing a plurality of semiconductor wafers, the apparatus including a spallation chamber, a neutron producing material mounted in the spallation chamber, a neutron moderator, and an irradiation chamber coupled to the spallation chamber, wherein the neutron moderator is disposed between the spallation chamber and the irradiation chamber, wherein the irradiation chamber is configured to accommodate the plurality of semiconductor wafers, wherein each of the plurality of semiconductor wafers has a first surface and a second surface opposite the first surface, wherein the plurality of semiconductor wafers are positioned so that a first surface of one semiconductor wafer faces a second surface of another semiconductor wafer. 1. An apparatus for processing a plurality of semiconductor wafers , the apparatus comprising:a spallation chamber;a neutron producing material mounted in the spallation chamber;a neutron moderator; andan irradiation chamber coupled to the spallation chamber, wherein the neutron moderator is disposed between the spallation chamber and the irradiation chamber, wherein the irradiation chamber is configured to accommodate the plurality of semiconductor wafers, wherein each of the plurality of semiconductor wafers has a first surface and a second surface opposite the first surface, wherein the plurality of semiconductor wafers are positioned so that a first surface of one semiconductor wafer faces a second surface of another semiconductor wafer.2. The apparatus of claim 1 ,wherein the neutron producing material comprises lithium, lithium/carbon mixture, tungsten, boron, or boron compounds.3. The apparatus of claim 1 , further comprising:an adjustable mount, wherein the neutron producing material is mounted on the adjustable mount.4. The apparatus of claim 1 , further comprising:a cooling unit coupled to the neutron producing material.5. The apparatus of claim 1 ,wherein the neutron moderator comprises heavy water, carbon, or carbon ...

EPITAXIAL STRUCTURE OF N-FACE GROUP III NITRIDE, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME WITH INTEGRATION AND POLARITY INVERSION

The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlGaN layer to the junction between the i-GaN channel layer and the i-AlGaN layer. 1. An epitaxial structure of N-face AlGaN/GaN , comprising:a substrate;a buffer layer (C-doped) layer on the substrate;a carbon doped (C-doped) i-GaN layer on the buffer layer (C-doped);{'sub': 'y', 'an i-AlGaN layer, located on said C-doped i-GaN layer;'}{'sub': 'y', 'an i-GaN channel layer, located on said i-AlGaN layer;'}{'sub': 'x', 'an i-AlGaN layer, located on said i-GaN channel layer;'}{'sub': 'x', 'a fluorine-ion structure, located in said i-AlGaN layer; and'}a first gate dielectric layer, located on said fluorine-ion structure;where x=0.1˜0.3 and y=0.05˜0.75.2. The structure of claim 1 , wherein an i-AlGaN grading buffer layer is further disposed between said C-doped i-GaN layer and said i-AlGaN layer and z=0.01˜0.75.3. The structure of claim 1 , wherein the two-dimensional electron gas in said i-GaN channel layer is depleted below said fluorine-ion structure and the two-dimensional electron gas is located at the junction between said i-GaN channel layer and said i-AlGaN layer.4. A method for fabricating an enhancement-mode N-face AlGaN/GaN high electron mobility transistor with polarity inversion using an epitaxial structure of N-face AlGaN/ ...

Methods for creating a semiconductor wafer having profiled doping and wafers and solar cell components having a profiled field, such as drift and back surface

A semiconductor wafer forms on a mold containing a dopant. The dopant dopes a melt region adjacent the mold. There, dopant concentration is higher than in the melt bulk. A wafer starts solidifying. Dopant diffuses poorly in solid semiconductor. After a wafer starts solidifying, dopant can not enter the melt. Afterwards, the concentration of dopant in the melt adjacent the wafer surface is less than what was present where the wafer began to form. New wafer regions grow from a melt region whose dopant concentration lessens over time. This establishes a dopant gradient in the wafer, with higher concentration adjacent the mold. The gradient can be tailored. A gradient gives rise to a field that can function as a drift or back surface field. Solar collectors can have open grid conductors and better optical reflectors on the back surface, made possible by the intrinsic back surface field.

Thermal processing techniques for metallic materials

A method of thermally processing a material with a thermal processing system includes providing a material for treating in an in-line thermal process to a heating system, providing a force to the material at a portion of the material configured to be heated by the heating system, adjusting the heating system to a specified temperature value, and heating the portion of the material to the specified temperature value while the portion of the material is under the force to change a magnetic property in the portion of the material. The heating system is moveable from a first position that is away from a path of the material through the in-line thermal process to a second position in which the heating system is configured to heat the portion of the material to the specified temperature value. The heating system can include induction-based heating.

Synthesis and processing of novel phase of carbon (q-carbon)

Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting boron nitride or amorphous carbon into an undercooled state followed by quenching. Exemplary new materials disclosed herein can be ferromagnetic and/or harder than diamond. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits. A novel phase of solid carbon has structure different than diamond and graphite.

Synthesis and processing of q-carbon, graphene, and diamond

Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting boron nitride or amorphous carbon into an undercooled state followed by quenching. Exemplary new materials disclosed herein can be ferromagnetic and/or harder than diamond. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits. A novel phase of solid carbon has structure different than diamond and graphite.

Conversion of boron nitride into n-type and p-type doped cubic boron nitride and structures

Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting boron nitride or amorphous carbon into an undercooled state followed by quenching. Exemplary new materials disclosed herein can be ferromagnetic and/or harder than diamond. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits. A novel phase of solid carbon has structure different than diamond and graphite.

PRODUCTION OF ROUNDED SALT PARTICLES

The present disclosure generally relates to methods of preparing spherical salt particles for industrial, medical, and other uses. The methods can include combining the angular salt particles with a quantity of finishing media, for example, into a receptacle. Thereafter, the angular salt particles and the finishing media can be moved or agitated until the angular salt particles have a desired sphericity. 1. A method for producing rounded salt particles from angular salt particles , the method comprising combining the angular salt particles with a quantity of finishing media in a receptacle , and moving or agitating the angular salt particles and the finishing media until the angular salt particles have a sphericity of greater than about 0.75.2. The method of claim 1 , wherein the angular salt particles have a particle size in the range of about 100 to about 1200 μm.3. The method of claim 1 , wherein the angular salt particles are selected from the group consisting of sodium chloride claim 1 , potassium chloride claim 1 , calcium carbonate claim 1 , lithium chloride claim 1 , magnesium chloride claim 1 , calcium chloride claim 1 , ammonium chloride claim 1 , sodium iodide claim 1 , potassium iodide claim 1 , lithium iodide claim 1 , magnesium iodide claim 1 , calcium iodide claim 1 , ammonium iodide claim 1 , sodium bromide claim 1 , potassium bromide claim 1 , lithium bromide claim 1 , magnesium bromide claim 1 , calcium bromide claim 1 , ammonium bromide claim 1 , sodium carbonate claim 1 , potassium carbonate claim 1 , lithium carbonate claim 1 , magnesium carbonate claim 1 , ammonium carbonate claim 1 , sodium bicarbonate claim 1 , potassium bicarbonate claim 1 , lithium bicarbonate claim 1 , ammonium bicarbonate claim 1 , sodium nitrate claim 1 , potassium nitrate claim 1 , lithium nitrate claim 1 , magnesium nitrate claim 1 , calcium nitrate claim 1 , ammonium nitrate claim 1 , sodium acetate claim 1 , potassium acetate claim 1 , lithium acetate claim 1 , ...

Susceptor and wafer holder

Disclosed is a susceptor. The susceptor comprises a susceptor bottom plate supporting a wafer holder; a susceptor top plate opposite to a susceptor bottom plate; and susceptor lateral-side plates extending from the susceptor bottom plate to the susceptor top plate, and wherein at least one of the susceptor top plate, the susceptor bottom plate, and the susceptor lateral-side plates includes the adiabatic layer.

LITHIUM TANTALATE SINGLE CRYSTAL SUBSTRATE, BONDED SUBSTRATE, MANUFACTURING METHOD OF THE BONDED SUBSTRATE, AND SURFACE ACOUSTIC WAVE DEVICE USING THE BONDED SUBSTRATE

The lithium tantalate single crystal substrate is a rotated Y-cut LiTaOsingle crystal substrate having a crystal orientation of 36° Y-49° Y cut characterized in that: the substrate is diffused with Li from its surface into its depth such that it has a Li concentration profile showing a difference in the Li concentration between the substrate surface and the depth of the substrate; and the substrate is treated with single polarization treatment so that the Li concentration is substantially uniform from the substrate surface to a depth which is equivalent to 5-15 times the wavelength of either a surface acoustic wave or a leaky surface acoustic wave propagating in the LiTaOsubstrate surface. 1. A method of manufacturing a bonded substrate , comprising:{'sub': '3', "bonding a base substrate to a LiTaOsingle crystal substrate which has a concentration profile wherein Li concentration is different between a substrate surface and an inner part of the substrate and wherein Li concentration is substantially uniform in a region ranging from at least one of the substrate's surfaces to a depth; and"}{'sub': '3', 'removing a LiTaOsurface layer opposite the bonding face in a manner such that at least part of said region where the Li concentration is substantially uniform is left.'}2. A method of manufacturing a bonded substrate , comprising:{'sub': '3', "bonding a base substrate to a LiTaOsingle crystal substrate which has a concentration profile wherein Li concentration is different between a substrate surface and an inner part of the substrate and wherein Li concentration is substantially uniform in a region ranging from at least one of the substrate's surfaces to a depth and"}{'sub': '3', 'removing a LiTaOsurface layer opposite the bonding face in a manner such that only said region where the Li concentration is substantially uniform is left.'}3. The method of manufacturing a bonded substrate as claimed in claim 2 , wherein that region in which the Li concentration is ...

METHODS OF PREPARATION OF ORGANOMETALLIC HALIDE STRUCTURES

Methods of growing organometallic halide structures such as AMX3 single crystal organometallic halide perovskites, using the inverse temperature solubility. 1. A method of making an AMX3 structure , comprising:dissolving MX2 and AX in a solvent to form dissolved AMX3 in a container, wherein A is an organic cation, M is a divalent cation selected from the group consisting of: Pb, Sn, Cu, Ni, Co, Fe, Mn, Pd, Cd, Ge, Cs, or Eu, and X is selected from a halide; andheating the mixture in the solvent to a temperature to form the AMX3 structure, wherein the temperature corresponds to the inverse temperature solubility for dissolved AMX3.2. The method of wherein A is selected from alkyl-ammonium claim 1 , formamidinum (FA) claim 1 , 5-ammoniumvaleric acid claim 1 , or Cesium (Cs).3. The method of claim 1 , wherein the AMXstructure is selected from the group consisting of: MAPbI claim 1 , MAPbBr claim 1 , FAPbBr claim 1 , FAPbI claim 1 , MAPbCl claim 1 , FAPbCl claim 1 , CsPbI claim 1 , CsPbCl claim 1 , CsPbBr claim 1 , FASnI claim 1 , FASnBr claim 1 , FASnCl claim 1 , MASnI claim 1 , MASnBr claim 1 , and MASnCl claim 1 , wherein MA is methylammonium and FA is formamidinum4. The method of claim 1 , wherein the solvent is selected from the group consisting of: N claim 1 ,N-dimethylformamide (DMF) claim 1 , dimethylsulfoxide (DMSO) claim 1 , gamma-butyrolactone (GBL) claim 1 , dichlorobenzene (DCB) claim 1 , toluene claim 1 , and a combination thereof.5. The method of claim 1 , wherein the AMX3 structure is a single crystal.6. The method of claim 1 , wherein when the AMX3 structure is a MAPbBr3 perovskite structure and the solvent is N claim 1 ,N-dimethylformamide (DMF).7. The method of claim 1 , wherein when the AMX3 structure is MAPbI3 perovskite structure and the solvent is γ-butyrolactone (GBL).8. The method of claim 1 , further comprising: controlling the size of the AMX3 structure by adjusting one or more of the following: bottom surface dimensions of the container claim ...

Crystal laminate structure

A crystal laminate structure includes a Ga 2 O 3 -based substrate, and a β-Ga 2 O 3 -based single crystal film formed by epitaxial crystal growth on a principal surface of the Ga 2 O 3 -based substrate. The β-Ga 2 O 3 -based single crystal film includes Cl and a dopant doped in parallel with the crystal growth at a concentration of not less than 1×10 13 atoms/cm 3 and not more than 5.0×10 20 atoms/cm 3 .

n-TYPE 4H-SiC SINGLE CRYSTAL SUBSTRATE AND METHOD OF PRODUCING n-TYPE 4H-SiC SINGLE CRYSTAL SUBSTRATE

In an n-type 4H-SiC single crystal substrate of the present disclosure, the concentration of the element N as a donor and the concentration of the element B as an acceptor are both 3×10 18 /cm 3 or more, and a threading dislocation density is less than 4,000/cm 2 .

LITHIUM TANTALATE SINGLE CRYSTAL SUBSTRATE, BONDED SUBSTRATE, MANUFACTURING METHOD OF THE BONDED SUBSTRATE, AND SURFACE ACOUSTIC WAVE DEVICE USING THE BONDED SUBSTRATE

[Object] 1: A rotated Y-cut lithium tantalate (LiTaO) single crystal substrate having a crystal orientation of 36° Y-49° Y cut , wherein said substrate is diffused with Li from its surface into its depth such that it has a Li concentration profile showing a difference in the Li concentration between the substrate surface and the depth of the substrate; and said substrate is treated with single polarization treatment so that the Li concentration is substantially uniform from the substrate surface to a depth which is equivalent to 5-15 times the wavelength of either a surface acoustic wave or a leaky surface acoustic wave propagating in the LiTaOsubstrate surface.2: The lithium tantalate single crystal substrate of claim 1 , wherein said Li concentration profile is one in which the Li concentration is higher at an area closer to the substrate surface of said rotated Y-cut LiTaOsubstrate and is lower at an area closer to the middle of said substrate.3: The lithium tantalate single crystal substrate of claim 1 , wherein a ratio of Li to Ta at the substrate surface is such that Li:Ta=50−α:50+α where α is in the range of −0.5<α<0.5.4: The lithium tantalate single crystal substrate of claim 1 , wherein said substrate is doped with Fe in an amount of 25 ppm-150 ppm.5: A bonded substrate claim 1 , comprising:a base substrate; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a lithium tantalate single crystal substrate of , being bonded to said base substrate.'}6: The bonded substrate of claim 5 , wherein a LiTaOsurface layer opposite the bonding face of said lithium tantalate single crystal substrate is removed in a manner such that at least part of said area where the Li concentration is substantially uniform is left.7: The bonded substrate of claim 5 , wherein said base substrate is made of Si claim 5 , SiC or spinel.8: A surface acoustic wave device claim 5 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the lithium tantalate single crystal substrate ...

THERMAL DIFFUSION DOPING OF DIAMOND

Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process. 1. Boron-doped diamond comprising: a layer of diamond comprising a doped region extending into the layer from a surface , the doped region comprising substitutional boron dopant atoms , wherein the concentration of substitutional boron dopant atoms at the surface is at least 1×10cmand the depth profile of the substitutional boron dopant atoms corresponds to a complimentary-error-function.2. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at the surface is at least 2×10cm.3. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at the surface is at least 2.2×10cm.4. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.5. The diamond of claim 1 , wherein the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.6. The diamond of claim 1 , wherein the diamond is free of Si atoms at a depth of 5 nm or greater from the surface.7. The diamond of claim 1 , wherein the surface is free of graphitized diamond.8. The diamond of claim 1 , wherein the diamond is natural diamond.9. The diamond of claim 1 , wherein the diamond comprises type IIa diamond.10. The diamond of claim 1 , wherein the diamond is single-crystalline diamond.11. The diamond of claim 1 , wherein the diamond is single-crystalline diamond claim 1 , the concentration of substitutional boron dopant atoms at the surface is at least 2×10cm claim 1 , and the concentration of substitutional boron dopant atoms at a depth of 100 nm from the surface is no greater than 1×10cm.12. A method of making substitutionally boron-doped diamond claim 1 , the method comprising: ...

EXPOSURE OF A SILICON RIBBON TO GAS IN A FURNACE

A system for producing a ribbon from a melt includes a crucible to contain a melt and a cold block. The cold block has a surface that directly faces an exposed surface of the melt. A ribbon is formed on the melt using the cold block. A furnace is operatively connected to the crucible. The ribbon passes through the furnace after removal from the melt. The furnace includes at least one gas jet. The gas jet can dope the ribbon, form a diffusion barrier on the ribbon, and/or passivate the ribbon. Part of the ribbon passes through the furnace while part of the ribbon is being formed in the crucible using the cold block. 1. A system comprising:a crucible for containing a melt;a cold block having a cold block surface that directly faces an exposed surface of the melt, the cold block configured to generate a cold block temperature at the cold block surface that is lower than a melt temperature of the melt at the exposed surface whereby a ribbon is formed on the melt;a furnace operatively connected to the crucible, wherein the ribbon passes through the furnace after removal from the melt such that part of the ribbon passes through the furnace while part of the ribbon is being formed in the crucible using the cold block, wherein the furnace includes at least one gas jet; anda gas source in fluid communication with the gas jet, wherein the gas source contains a gas that dopes the ribbon, forms a surface oxide or other diffusion barrier on the ribbon, and/or passivates the ribbon.2. The system of claim 1 , wherein the furnace includes a plurality of the gas jets.3. The system of claim 2 , wherein the gas jets are arranged in a plurality of zones separated by a gas curtain claim 2 , wherein each of the zones provides a different gas.4. The system of claim 1 , wherein the gas source is one of a syngas gas source that includes argon and hydrogen claim 1 , a syngas source that includes argon and nitrogen claim 1 , a POClgas source claim 1 , or an oxygen gas source.5. The system of ...

WAFER BOAT STRUCTURE, AS WELL AS WAFER BOAT ASSEMBLY AND DIFFUSION FURNACE WITH SAME

A wafer boat structure as well as a wafer boat assembly and a diffusion furnace with the wafer boat structure are provided. The wafer boat structure includes a supporting frame and a wafer supporting part. The supporting frame includes an upper supporting member and a lower supporting member. A plurality of supporting rods are arranged between the upper supporting member and the lower supporting member. An opening for access of wafers is formed between each two adjacent supporting rods. The wafer supporting part is arranged on the supporting rods for supporting the wafer. The wafer supporting part comprises a supporting plate and at least one wafer board. The wafer board is arranged on the inner side of the supporting rod so as to support the edge of the wafer. 1. A wafer boat structure , comprising:a supporting frame, comprising an upper supporting member and a lower supporting member, a plurality of supporting rods being arranged between the upper supporting member and the lower supporting member, one end of each of the supporting rods being connected with the upper supporting member and the other end being connected with the lower supporting member, the plurality of supporting rods being spaced apart from each other in a circumferential direction of the upper supporting member, and an opening for access of wafers is formed between each two adjacent supporting rods; andat least one wafer supporting part arranged on the supporting rods for supporting the wafer, the wafer supporting part comprising a supporting plate and at least one wafer board, the supporting plate and the at least one wafer board supporting the same wafer, the supporting plate being connected with the supporting rod and a position of the supporting plate corresponding to central positions of the upper supporting member and the lower supporting member, the wafer board being arranged on an inner side of the supporting rod to support a edge of the wafer.2. The wafer boat structure of claim 1 , ...

Methods of preparation of organometallic halide structures

Embodiments of the present disclosure provide methods of growing organometallic halide structures such as single crystal organometallic halide perovskites, methods of use, devices incorporating organometallic halide structures, and the like.

CRYSTAL LAMINATE STRUCTURE

[Problem] To provide a crystal laminate structure having a β-GaObased single crystal film in which a dopant is included throughout the crystal and the concentration of the dopant can be set across a broad range. [Solution] In one embodiment of the present invention, provided is a crystal laminate structure which includes: a GaObased substrate ; and a β-GaObased single crystal film 12 formed by epitaxial crystal growth on a primary face 11 of the GaObased substrate 10 and including Cl and a dopant doped in parallel with the crystal growth at a concentration of 1×10to 5.0×10atoms/cm. 1. A crystal laminate structure , comprising:a Ga2O3-based substrate;a β-Ga2O3-based single crystal epitaxial film grown on a primary plane of the Ga2O3-based substrate;wherein the β-Ga2O3-based single crystal epitaxial film has an electron mobility from 8.98×10 to 1.60×102 cm2/V·s at 25° C.2. The crystal laminate structure claim 1 , according to claim 1 , wherein the β-Ga2O3-based single crystal epitaxial film has a carrier density from 1.2×1018/cm3 to 3.2×1015/cm3.3. The crystal laminate structure claim 1 , according to claim 1 , wherein the β-Ga2O3-based single crystal epitaxial film has a resistivity from 5.96×10-2 Ω·cm to 12.5 Ω·cm. The present application is a continuation application filed under 35 USC § 120 claiming priority to co-pending application U.S. Ser. No. 15/559,167, filed Sep. 18, 2017, which claims priority as a national stage filing under 35 USC § 371 of PCT/JP2016/054620 filed Feb. 17, 2016, the entire contents of each of which are incorporated herein by reference.The invention relates to a crystal laminate structure.Conventionally, a method in which a dopant is added during crystal growth by the MBE (Molecular Beam Epitaxy) method or the EFG (Edge-defined Film-fed Growth) method (see, e.g., PTLs 1 and 2) and a method in which a dopant is added to a grown β-GaO-based single crystal by ion implantation (see, e.g., PTL 3) are known to dope a β-GaO-based single crystal. ...

Silicon single crystal wafer, manufacturing method thereof and method of detecting defects

A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.

Diamond tool piece

A high-pressure high-temperature, HPHT, diamond tool piece and a method of producing an HPHT diamond tool piece. At least a portion of the HPHT diamond tool piece comprises an aggregated nitrogen centre to C-nitrogen centre ratio of greater than 30%. The method includes irradiating an HPHTdiamond material to introduce vacancies in the diamond crystal lattice, annealing the HPHT diamond material such that at least a portion of the HPHT diamond material comprises an aggregated nitrogen centre to C-nitrogen centre ratio of greater than 30%,andprocessing the HPHT diamond material to form an HPHT diamond tool piece.

SILICON EPITAXIAL WAFER AND METHOD OF PRODUCING SILICON EPITAXIAL WAFER

A silicon epitaxial wafer including: a second intermediate epitaxial layer on a silicon substrate produced by being cut from a silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 3×10to 2×10atoms/cm, a first intermediate epitaxial layer doped with a dopant, and an epitaxial layer of a device forming region stacked on the first intermediate epitaxial layer, and to a method of producing this wafer. Also providing an industrially excellent silicon epitaxial wafer that is produced with a silicon substrate doped with carbon and used as a semiconductor device substrate such as a memory, a logic, or a solid-state image sensor, and a method of producing this silicon epitaxial wafer. 18-. (canceled)9. A silicon epitaxial wafer comprising:{'sup': 16', '17', '3, 'a silicon substrate doped with carbon, the silicon substrate being produced by being cut from a silicon single crystal ingot grown by a Czochralski method so as to have a carbon concentration ranging from 3×10to 2×10atoms/cm;'}a first intermediate epitaxial layer that is doped with a dopant and disposed on the silicon substrate;an epitaxial layer stacked on the first intermediate epitaxial layer, the epitaxial layer being a region at which a device is to be formed; anda second intermediate epitaxial layer disposed between the silicon substrate and the first intermediate epitaxial layer.10. The silicon epitaxial wafer according to claim 9 , wherein the second intermediate epitaxial layer has a thickness ranging from 0.5 μm to 2 μm.11. The silicon epitaxial wafer according to claim 9 , wherein a thickness of the second intermediate epitaxial layer is adjusted depending on an amount of the carbon with which the silicon substrate is doped.12. The silicon epitaxial wafer according to claim 10 , wherein a thickness of the second intermediate epitaxial layer is adjusted depending on an amount of the carbon with which the silicon substrate is doped.13. The silicon epitaxial ...

Screen-printable boron doping paste with simultaneous inhibition of phosphorus diffusion in co-diffusion processes

The present invention relates to a novel printable boron doping paste in the form of a hybrid gel based on precursors of inorganic oxides, preferably of silicon dioxide, aluminium oxide and boron oxide, in the presence of organic polymer particles, where the pastes according to the invention can be used in a simplified process for the production of solar cells, where the hybrid gel according to the invention functions both as doping medium and as diffusion barrier.

METHOD OF MANUFACTURING A SILICON INGOT AND SILICON INGOT

A method of Czochralski growth of a silicon ingot includes melting a mixture of silicon material and an n-type dopant material in a crucible. The silicon ingot is extracted from the molten silicon during an extraction time period. The silicon ingot is doped with additional n-type dopant material during at least one sub-period of the extraction time period. 1. A method of Czochralski growth of a silicon ingot , the method comprising:melting a mixture of silicon material and an n-type dopant material in a crucible;extracting the silicon ingot from the molten silicon during an extraction time period; anddoping the silicon ingot with additional n-type dopant material during at least one sub-period of the extraction time period.2. The method of claim 1 , wherein the additional n-type dopant material is phosphorus.3. The method of claim 1 , wherein the silicon ingot is doped with the additional n-type dopant material by a vapor phase doping technique.4. The method of claim 3 , further comprising controlling inlet of a dopant precursor gas into a reaction chamber including the silicon ingot.5. The method of claim 1 , wherein doping the silicon ingot with the additional n-type dopant material includes melting an n-type dopant source material in the crucible.6. The method of claim 5 , wherein the silicon ingot is doped with the additional n-type dopant material by adjusting a depth of the n-type dopant source material into the molten silicon claim 5 , the n-type dopant source material including the additional n-type dopant material.7. The method of claim 6 , wherein adjusting the depth of the n-type dopant source material dipped into the molten silicon in the crucible includes measuring a weight of the n-type dopant source material.8. The method of claim 5 , wherein the n-type dopant source material is in the shape of one or more rods.9. The method of claim 5 , wherein the n-type dopant source material is made of quartz or silicon carbide doped with the additional n-type ...

BIOTEMPLATED PEROVSKITE NANOMATERIALS

A biotemplated nanomaterial can include a crystalline perovskite. 129-. (canceled)30. A method of making a perovskite nanomaterial comprising:combining an aqueous solution of a biotemplate having affinity for a metal ion and an inorganic precursor of a perovskite material to form an aqueous mixture, andreacting the inorganic precursor and the biotemplate to form the perovskite nanomaterial,wherein the perovskite comprises strontium titanate, bismuth ferrite, sodium tantalate, zirconium oxide/tantalum oxynitride, zirconium tantalum oxynitride, tantalum oxynitride, or zirconium tantalum nitride.31. The method of claim 30 , wherein the biotemplate includes a virus particle.32. The method of claim 31 , wherein the virus particle is an M13 bacteriophage.33. The method of claim 30 , wherein the inorganic precursor comprises a first inorganic ion and a second inorganic ion.34. The method of claim 33 , further comprising forming an ion source including the first inorganic ion and the second inorganic ion before forming the aqueous mixture.35. The method of claim 33 , further comprising adjusting the pH of the aqueous mixture and incubating the aqueous mixture for a predetermined time at a predetermined temperature.36. The method of claim 33 , further comprising incubating the aqueous mixture and then calcining the reaction products.37. A method of making a perovskite nanomaterial comprising:combining an aqueous solution of a biotemplate having affinity for a metal ion and an inorganic precursor of a perovskite material to form an aqueous mixture, andreacting the inorganic precursor and the biotemplate to form the perovskite nanomaterial, {'br': None, 'sub': x', '1-x', 'y', '1-y', '3±δ, 'AA′BB′O\u2003\u2003(I)'}, 'wherein the perovskite has the formula (I)whereineach of A and A′, independently, are selected from the group consisting of Mg, Pb, and Bi;each of B and B′, independently, are selected from the group consisting of Zr, V, Nb, Mn, Fe, Ru, Rh, Ni, Pd, Pt, Al, and Mg;x ...

System and Method for Increasing III-Nitride Semiconductor Growth Rate and Reducing Damaging Ion Flux

Systems and methods are disclosed for rapid growth of Group III metal nitrides using plasma assisted molecular beam epitaxy. The disclosure includes higher pressure and flow rates of nitrogen in the plasma, and the application of mixtures of nitrogen and an inert gas. Growth rates exceeding 8 μm/hour can be achieved. 1. A plasma assisted MBE system comprising:a growth chamber having a substrate;a remote plasma chamber; anda gas-conductance barrier separating the plasma chamber from the growth chamber;{'sub': g', 'p', 'g', 'P, 'wherein the growth chamber has a pressure P, and the plasma chamber has a pressure P, and the gas conductance barrier allows the pressure Pto be lower that P.'}2. The system of claim 1 , wherein Pis at least 0.1 mTorr.34.-. (canceled)5. The system of claim 1 , wherein Pis at least 100 mTorr.6. The system of claim 1 , wherein Pis less than about 0.1 mTorr.78.-. (canceled)9. The system of claim 1 , wherein the plasma chamber contains plasma comprising nitrogen and an inert gas mixture; andwherein the system is configured such that the nitrogen gas flow of the plasma is at least 3 sccm based on a 2 inch diameter substrate.1114.-. (canceled)15. The system of claim 9 , wherein the nitrogen to inert gas ratio is 1:20 to 20:1.16. The system of claim 9 , wherein the nitrogen to inert gas ratio is 1:1 to 10:117. The system of claim 9 , wherein the system is configured such that the gas-conductance barrier has a conductance value of at least about 5 L/s.1823.-. (canceled)24. A method for growing Group III metal nitrides comprising:flowing a plasma from a remote plasma chamber through a gas-conductance barrier and into a growth chamber; andgrowing a group III metal nitride product on a substrate in the growth chamber.25. The method of claim 57 , wherein the plasma comprises a combination of nitrogen and an inert gas selected from the group consisting of neon claim 57 , argon and xenon.26. The method of claim 25 , wherein the nitrogen gas flow of the ...

Semiconductor device manufacturing method and semiconductor device

A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 μm or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).

Extreme large grain (1 mm) lateral growth of cd(se,te) alloy thin films by reactive anneals

Disclosed herein are compositions and methods for making polycrystalline thin films having very large grains sizes and exhibiting improved properties over existing thin films.

SYSTEM AND METHOD FOR INCREASING GROUP III-NITRIDE SEMICONDUCTOR GROWTH RATE AND REDUCING DAMAGING ION FLUX

Systems and methods for the rapid growth of Group III metal nitrides using plasma assisted molecular beam epitaxy. The disclosure includes higher pressure and flow rates of nitrogen in the plasma, and the application of mixtures of nitrogen and an inert gas. Growth rates exceeding 8 μm/hour can be achieved. 1. A vacuum deposition method for growing a semiconductor material comprising:depositing semiconductor material on a substrate; andgrowing the thickness of the semiconductor material at a growth rate of greater than 3 μm/hour.2. The method of claim 1 , wherein the growth rate is greater than 4 μm/hour.3. The method of claim 1 , wherein the growth rate is greater than 8 μm/hour.4. The method of further comprising flowing a plasma though a gas-conductance barrier;wherein growing the thickness of the semiconductor material occurs downstream of the gas-conductance barrier.5. The method of further comprising:generating a plasma upstream of a gas-conductance barrier; andflowing the plasma though the gas-conductance barrier;wherein growing the thickness of the semiconductor material occurs downstream of the gas-conductance barrier.6. The method of further comprising flowing a plasma from a plasma chamber claim 1 , though a gas-conductance barrier claim 1 , and into a growth chamber;wherein the semiconductor material is a group III metal nitride product;wherein the group III metal nitride product is grown in the growth chamber;{'sub': g', 'P, 'wherein the gas conductance barrier has a conductance C such that the growth chamber pressure Pis lower than the plasma chamber pressure P; and'}{'sub': 'P', 'wherein Pis at least 1 mTorr.'}7. The method of claim 6 , wherein Pis at least 10 mTorr.8. The method of claim 6 , wherein Pis at least 100 mTorr.9. The method of claim 6 , wherein the plasma comprises nitrogen.10. The method of claim 6 , wherein the plasma comprises nitrogen and argon.11. The method of further comprising:flowing a plasma from a plasma chamber, though a gas- ...

METHOD FOR MANUFACTURING SUBSTRATE FOR SOLAR CELL AND SUBSTRATE FOR SOLAR CELL

A solar cell includes a light-receiving surface electrode formed on a light-receiving surface, a back surface electrode formed on a backside, and a CZ silicon single crystal substrate doped with gallium. The CZ silicon single crystal substrate contains 12 ppm or more oxygen atoms. A spiral oxygen-induced defect is not observed in an EL (electroluminescence) image of the solar cell. 1. A solar cell comprising a light-receiving surface electrode formed on a light-receiving surface , a back surface electrode formed on a backside , and a CZ silicon single crystal substrate doped with gallium ,wherein the CZ silicon single crystal substrate contains 12 ppm or more oxygen atoms, anda spiral oxygen-induced defect is not observed in an EL (electroluminescence) image of the solar cell.2. The solar cell according to claim 1 , wherein the CZ silicon single crystal substrate contains 17 to 18 ppm oxygen atoms.3. The solar cell according to claim 1 , comprising a light-receiving surface antireflection coating and an emitter layer on the light-receiving surface claim 1 , anda back surface antireflection coating and a BSF layer on the backside,wherein the light-receiving surface electrode is electrically connected with the emitter layer passing through the light-receiving surface antireflection coating, andthe back surface electrode is electrically connected with the BSF layer passing through the back surface antireflection coating.4. The solar cell according to claim 2 , comprising a light-receiving surface antireflection coating and an emitter layer on the light-receiving surface claim 2 , anda back surface antireflection coating and a BSF layer on the backside,wherein the light-receiving surface electrode is electrically connected with the emitter layer passing through the light-receiving surface antireflection coating, andthe back surface electrode is electrically connected with the BSF layer passing through the back surface antireflection coating.5. The solar cell according ...

Method for Reducing the Thickness of Solid-State Layers Provided with Components

The invention relates to a method for separating at least one solid-state layer ( 4 ) from at least one solid ( 1 ). The method according to the invention includes the steps of: producing a plurality of modifications ( 9 ) by means of laser beams in the interior of the solid ( 1 ) in order to form a separation plane ( 8 ); producing a composite structure by arranging or producing layers and/or components ( 150 ) on or above an initially exposed surface ( 5 ) of the solid ( 1 ), the exposed surface ( 5 ) being part of the solid-state layer ( 4 ) to be separated; introducing an external force into the solid ( 1 ) in order to create stresses in the solid ( 1 ), the external force being so great that the stresses cause a crack to propagate along the separation plane ( 8 ), wherein the modifications for forming the separation plane ( 8 ) are produced before the composite structure is produced.

LARGE DIAMETER SILICON CARBIDE WAFERS

Silicon carbide (SiC) wafers and related methods are disclosed that include large diameter SiC wafers with wafer shape characteristics suitable for semiconductor manufacturing. Large diameter SiC wafers are disclosed that have reduced deformation related to stress and strain effects associated with forming such SiC wafers. As described herein, wafer shape and flatness characteristics may be improved by reducing crystallographic stress profiles during growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics may also be improved after individual SiC wafers have been separated from corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed that include large diameter SiC wafers with suitable crystal quality and wafer shape characteristics including low values for wafer bow, warp, and thickness variation. 1. A silicon carbide (SiC) wafer comprising a diameter of at least 195 millimeters (mm) , a thickness in a range from 300 microns (μm) to 1000 μm , and a bow in a range from −25 inn to 25 μm.2. The SiC wafer of claim 1 , further comprising a warp of less than or equal to 40 μm.3. The SiC wafer of claim 1 , wherein the diameter is in a range from 195 mm to 455 mm.4. The SiC wafer of claim 1 , wherein the diameter is in a range from 195 mm to 305 mm.5. The SiC wafer of claim 1 , wherein the thickness is in a range from 300 to 500 μm.6. (canceled)7. The SiC wafer of claim 1 , further comprising a total thickness variation (TTV) of less than 7 μm.8. (canceled)9. The SiC wafer of claim 1 , further comprising a local thickness variation (LTV) of less than 4 μm for a site area of 1 cm.10. The SiC wafer of claim 1 , further comprising a site front least-squares (SFQR) maximum value of less than 1.5 μm for a site area of 1 cm.11. The SiC wafer of claim 1 , wherein the SiC wafer comprises at least one of 4-H SiC claim 1 , semi-insulating SiC claim 1 , and n-type SiC.1214-. (canceled)15. The SiC wafer of claim 1 , ...

METHOD FOR PRODUCING COMPOSITE WAFER HAVING OXIDE SINGLE-CRYSTAL FILM

A composite wafer having an oxide single-crystal film transferred onto a support wafer, the film being a lithium tantalate or lithium niobate film, and the composite wafer being unlikely to have cracking or peeling caused in the lamination interface between the film and the support wafer. More specifically, a method of producing the composite wafer, including steps of: implanting hydrogen atom ions or molecule ions from a surface of the oxide wafer to form an ion-implanted layer inside thereof; subjecting at least one of the surface of the oxide wafer and a surface of the support wafer to surface activation treatment; bonding the surfaces together to obtain a laminate; heat-treating the laminate at 90° C. or higher at which cracking is not caused; and exposing the heat-treated laminate to visible light to split along the ion-implanted layer to obtain the composite wafer. 2. The method of producing a composite wafer according to claim 1 , wherein the temperature in the step of heat-treating is from 90 to 225° C. when the support wafer is the sapphire wafer; from 90° C. to 200° C. when the support wafer is the silicon wafer or the silicon wafer with an oxide film; and from 90 to 110° C. when the support wafer is the glass wafer.3. The method of producing a composite wafer according to claim 1 , wherein the step of exposition comprises exposing the laminate to the visible light while bringing a wedge-like blade into contact with the ion-implanted layer of the laminate.4. The method of producing a composite wafer according to claim 1 , wherein the surface activation treatment is selected from the group consisting of ozone water treatment claim 1 , UV ozone treatment claim 1 , ion beam treatment claim 1 , and plasma treatment.5. The method of producing a composite wafer according to claim 1 , wherein a source of the visible light is a flash lamp of a flash lamp annealer.6. The method of producing a composite wafer according to claim 1 , wherein the source of the visible ...

Method and system for mutliline mir-ir laser

A method of performing spatial separation of different wavelengths in a single laser cavity includes generating, from a pump radiation source, pump radiations in spatially separate channels and focusing the generated pump radiations in the spatially separate channels towards an active gain medium having amplification spectra. The method also includes emitting from the active gain medium, amplified radiations of the spatially separate channels, each channel of the spatially separate channels representing a corresponding wavelength and focusing the emitted amplified radiations of the spatially separated channels towards an aperture. The method further includes suppressing, at the aperture, an off-axis mode of the amplified radiations of the spatially separate channels, diffracting the amplified radiations of the spatially separate channels received through the aperture to provide diffracted radiations and returning a portion of the diffracted radiations back to the aperture, and collimating the diffracted radiations of the spatially separate channel.

METHODS FOR ATOM INCORPORATION INTO MATERIALS USING A PLASMA AFTERGLOW

There are provided non-destructive methods for incorporating an atom such as N into a material such as graphene. The methods can comprise subjecting a gas comprising the atom to conditions to obtain a flowing plasma afterglow then exposing the material to the flowing plasma afterglow. There are also provided materials such as N-doped graphene produced by such methods. 1. A method for atom incorporation into a material , comprising:subjecting a gas comprising said atom to conditions to obtain a flowing plasma afterglow; andexposing said material to said flowing plasma afterglow.2. The method of claim 1 , wherein said gas is subjected to an electromagnetic field in the microwave regime to obtain a high-density plasma with a flowing plasma afterglow.3. The method of claim 2 , wherein said electromagnetic field claim 2 , has a frequency of about 433 MHz to about 3 GHz.45-. (canceled)6. The method of claim 1 , wherein said atom incorporated into said material is N claim 1 , O claim 1 , B claim 1 , H or mixtures thereof and said gas comprises N claim 1 , O claim 1 , BH claim 1 , Hor mixtures thereof claim 1 , respectively.7. The method of claim 1 , wherein said atom incorporated into said material is a mixture of N and O and said gas consists essentially of a mixture of Nand O.8. The method of claim 1 , wherein said atom incorporated into said material is N and said gas consists essentially of N.911-. (canceled)12. The method of claim 1 , wherein said method is carried out at a total gas pressure of from about 1 Torr to about 20 Torr.13. (canceled)14. The method of claim 1 , wherein said flowing plasma afterglow is a late afterglow.15. The method of claim 1 , wherein said flowing plasma afterglow has a positive ion density of about 10cmto about 10cm.1622-. (canceled)23. The method of claim 1 , wherein said material comprises graphene claim 1 , a nanomaterial claim 1 , a metal surface claim 1 , a crystal surface claim 1 , a polymer or a combination thereof.24. (canceled)25 ...

METHOD OF MANUFACTURING DIAMOND, DIAMOND, DIAMOND COMPOSITE SUBSTRATE, DIAMOND JOINED SUBSTRATE, AND TOOL

A method of manufacturing a diamond by a vapor phase synthesis method includes: preparing a substrate including a diamond seed crystal; forming a light absorbing layer lower in optical transparency than the substrate by performing ion implantation into the substrate, the light absorbing layer being formed at a predetermined depth from a main surface of the substrate; growing a diamond layer on the main surface of the substrate by the vapor phase synthesis method; and separating the diamond layer from the substrate by applying light from a main surface of at least one of the diamond layer and the substrate to allow the light absorbing layer to absorb the light and cause the light absorbing layer to be broken up. 1. A diamond comprising:a diamond layer; anda light absorbing layer disposed on one surface of the diamond layer and different in optical transparency from the diamond layer, a diamond crack having a length of not more than 100 μm,', 'a graphite layer having a maximum diameter of not more than 100 μm, and', 'a graphite layer having a length of not less than 200 μm., 'a surface of the light absorbing layer including at least one of'}2. The diamond according to claim 1 , wherein{'sup': −4', '9, 'the diamond includes a layer having a resistivity of not less than 10Ωcm and less than 10Ωcm and having a thickness of not less than 1 μm.'}3. The diamond according to claim 1 , whereinin the diamond which is a single freestanding body, a difference between an average diamond crystal grain size in one main surface of the diamond and an average diamond crystal grain size in the other main surface of the diamond is not more than 50% of a larger one of the average diamond crystal grain size in the one main surface and the average diamond crystal grain size in the other main surface.4. A diamond composite substrate comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a diamond as recited in ; and'}a different-kind substrate attached to the diamond, the different- ...

DIAMOND COMPOSITE BODY, SUBSTRATE, DIAMOND TOOL INCLUDING DIAMOND, AND METHOD FOR MANUFACTURING DIAMOND

Provided are a diamond composite body capable of shortening a separation time for separating a substrate and a diamond layer, the substrate, and a method for manufacturing a diamond, as well as a diamond obtained from the diamond composite body and a tool including the diamond. The diamond composite body includes a substrate including a diamond seed crystal and having grooves in a main surface, a diamond layer formed on the main surface of the substrate, and a non-diamond layer formed on a substrate side at a constant depth from an interface between the substrate and the diamond layer. 1. A diamond having a set of main surfaces , and including a line-shaped or lattice-shaped optical distortion when observed with light vertically passing through the set of main surfaces.2. The diamond according to claim 1 , wherein claim 1 , in a region of more than or equal to 90% of a surface of the main surface claim 1 , an average value of phase differences of the optical distortion is less than 50 nm.3. The diamond according to claim 1 , wherein claim 1 , in a region of more than or equal to 90% of a surface of the main surface claim 1 , a maximum value of phase differences in a region except for a periodic peak area of the optical distortion is less than or equal to 90 nm.4. The diamond according to claim 1 , wherein the optical distortion is substantially parallel to a <100> direction.5. The diamond according to claim 1 , wherein the optical distortion accounts for a region of more than or equal to 20% of a surface of the main surface.6. A diamond claim 1 , comprising:a single crystal diamond layer having a set of main surfaces; anda layer containing implanted ions arranged on at least one of the main surfaces of the single crystal diamond layer,the layer containing implanted ions having line-shaped or lattice-shaped grooves penetrating to the single crystal diamond layer.7. A diamond having a set of main surfaces claim 1 , including a line-shaped or lattice-shaped array in ...

LIQUID DOPING MEDIA FOR THE LOCAL DOPING OF SILICON WAFERS

The present invention relates to a novel process for the preparation of printable, low-viscosity oxide media, and to the use thereof in the production of solar cells. 1. Process for the preparation of printable , low-viscosity oxide media in the form of doping media , characterised in that an anhydrous sol-gel-based synthesis is carried out by condensation of alkoxysilanes and/or alkoxyalkylsilanes with symmetrical and asymmetrical carboxylic anhydridesi. in the presence of boron-containing compounds and/orii. in the presence of phosphorus-containing compounds and low-viscosity doping media (doping inks) are prepared by controlled gelling.2. Process according to claim 1 , where the alkoxysilanes and/or alkoxyalkylsilanes used contain individual or different saturated or unsaturated claim 1 , branched or unbranched claim 1 , aliphatic claim 1 , alicyclic or aromatic radicals claim 1 , which may in turn be functionalised at any desired position of the alkoxide and/or alkyl radical by heteroatoms selected from the group O claim 1 , N claim 1 , S claim 1 , Cl claim 1 , Br.3. Process according to claim 1 , where the boron-containing compounds are selected from the group boron oxide claim 1 , boric acid and boric acid esters.4. Process according to claim 1 , where the phosphorus-containing compounds are selected from the group phosphorus(V) oxide claim 1 , phosphoric acid claim 1 , polyphosphoric acid claim 1 , phosphoric acid esters and phosphonic acid esters containing siloxane-functionalised groups in the alpha- and beta-position.5. Process according to claim 1 , characterised in that the carboxylic anhydrides used are anhydrides from the group acetic anhydride claim 1 , ethyl formate (anhydride of formic and acetic acid) claim 1 , propionic anhydride claim 1 , succinic anhydride claim 1 , maleic anhydride claim 1 , sorbic anhydride claim 1 , phthalic anhydride and benzoic anhydride.6. Process according to claim 1 , characterised in that the printable oxide media are ...

SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR SUBSTRATE, AND CRYSTAL LAMINATE STRUCTURE

A semiconductor element includes a base substrate that includes a GaO-based crystal having a thickness of not less than 0.05 μm and not more than 50 μm, and an epitaxial layer that includes a GaO-based crystal and is epitaxially grown on the base substrate. A semiconductor element includes an epitaxial layer that includes a GaO-based crystal including an n-type dopant, an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer, an anode electrode connected to the epitaxial layer, and a cathode electrode connected to the ion implanted layer. 1. A semiconductor element , comprising:{'sub': 2', '3, 'a base substrate that comprises a GaO-based crystal having a thickness of not less than 0.05 μm and not more than 50 μm; and'}{'sub': 2', '3, 'an epitaxial layer that comprises a GaO-based crystal and is epitaxially grown on the base substrate.'}2. The semiconductor element according to claim 1 , wherein the thickness of the base substrate is less than 10 μm.3. The semiconductor element according to claim 1 , wherein a plane orientation of a principal surface of the base substrate is (010).4. The semiconductor element according to claim 1 , comprising a vertical element claim 1 , wherein the base substrate and the epitaxial layer provide a current path.5. The semiconductor element according to claim 1 , comprising a lateral element claim 1 , wherein the base substrate does not provide a current path.6. The semiconductor element according to claim 1 , wherein the base substrate and the epitaxial layer are each attached to other substrates.7. A semiconductor element claim 1 , comprising:{'sub': 2', '3, 'an epitaxial layer that comprises a GaO-based crystal including an n-type dopant;'}an ion implanted layer that is formed on a surface of the epitaxial layer and includes a higher concentration of n-type dopant than the epitaxial layer;an anode electrode connected to the epitaxial layer ...

SILICON CARBIDE CRYSTAL GROWING APPARATUS AND CRYSTAL GROWING METHOD THEREOF

A silicon carbide crystal growing apparatus includes a physical vapor transport unit and an atomic layer deposition unit. The physical vapor transport unit has a crystal growing furnace configured to grow a silicon carbide crystal in an internal space of the crystal growing furnace. The atomic layer deposition unit is coupled to the crystal growing furnace and configured to perform an atomic doping operation on the silicon carbide crystal. A silicon carbide crystal growing method is also provided. 1. A silicon carbide crystal growing apparatus , comprising:a physical vapor transport unit having a crystal growing furnace configured to grow a silicon carbide crystal in an internal space of the crystal growing furnace;an atomic layer deposition unit, coupled to the crystal growing furnace, and configured to perform an atomic doping operation on the silicon carbide crystal.2. The silicon carbide crystal growing apparatus according to claim 1 , wherein the atomic layer deposition unit uses the crystal growing furnace as a chamber.3. The silicon carbide crystal growing apparatus according to claim 2 , wherein the atomic layer deposition unit does not have another chamber.4. The silicon carbide crystal growing apparatus according to claim 1 , further comprising a gas channel configured to connect the internal space and the atomic layer deposition unit.5. The silicon carbide crystal growing apparatus according to claim 4 , wherein the physical vapor transport unit comprises a pump configured to perform a negative pressurizing operation in the internal space.6. The silicon carbide crystal growing apparatus according to claim 5 , further comprising a butterfly valve configured to control the pressure in the internal space.7. The silicon carbide crystal growing apparatus according to claim 1 , wherein the silicon carbide crystal is a semi-insulating silicon carbide crystal or an N-type silicon carbide crystal.8. The silicon carbide crystal growing apparatus according to claim ...

N-Type Aluminum Nitride Monocrystalline Substrate

A silicon-doped n-type aluminum nitride monocrystalline substrate wherein, at a photoluminescence measurement at 23° C., a ratio (I1/I2) between the emission spectrum intensity (I1) having a peak within 370 to 390 nm and the emission peak intensity (I2) of the band edge of aluminum nitride is 0.5 or less; a thickness is from 25 to 500 μm; and a ratio (electron concentration/silicon concentration) between the electron concentration and the silicon concentration at 23° C. is from 0.0005 to 0.001.

Lithium ion Battery Cell With Single Crystal Li+- Intercalated Titanium Dioxide As An Anode Material

A nonaqueous battery cell includes a casing, a negative electrode provided in the casing, the negative electrode including lithium ions intercalated into a single crystal of a titanium dioxide (TiO), in the rutile phase, with concentration on the order of 10cm, a positive electrode provided in the casing, a separator separating the negative electrode from the positive electrode, and an electrolyte disposed in the casing. 1. A method of manufacturing an electrode material to be used in a electrochemical battery , said method comprising the steps of:{'sub': '2', '(a) burying a titanium dioxide (TiO) crystal into a lithium hydroxide powder;'}(b) heating, in a furnace, said titanium dioxide buried in said lithium hydroxide powder; and{'sub': '2', '(c) isolating a single lithium ion within each “C”-axis channel aligned along the crystallographic direction of said single TiOcrystal.'}2. The method of claim 1 , wherein the step (b) includes the step of heating said TiOburied in said lithium hydroxide powder at a temperature between 425° C. and 475° C. for a duration of between 19 and 25 hours and at an atmospheric pressure of about 1 atmosphere (atm).3. The method of claim 1 , wherein the step (a) includes the step of burying only a single TiOcrystal in a rutile phase.4. The method of claim 3 , wherein step (b) includes the step of diffusing lithium ions into channels aligned along a crystallographic direction of said single TiOcrystal.5. The method of claim 3 , wherein the step (b) includes the step of producing Liconcentrations in said electrode on the order of between 5×10cmand 1×10cm.6. The method of claim 1 , wherein the step (b) comprises the step of heating said TiOburied in said lithium hydroxide powder at an ambient pressure being greater than an atmospheric pressure.7. The method of claim 1 , further comprising the step of providing said TiOin a rutile crystal form and intentionally doping said TiOcrystal claim 1 , during growth thereof claim 1 , with transition ...

METHOD FOR DEPOSITING LOW TEMPERATURE PHOSPHOROUS-DOPED SILICON

Methods and devices for low-temperature deposition of phosphorous-doped silicon layers. Disilane is used as a silicon precursor, and nitrogen or a noble gas is used as a carrier gas. Phosphine is a suitable phosphorous precursor. 1. A method for epitaxially growing a phosphorous-doped silicon layer comprising:providing a substrate comprising a monocrystalline silicon surface in a reactor chamber; and,introducing disilane, phosphine, and a carrier gas into the reactor chamber while maintaining the reaction chamber at a temperature of at least 350.0° C. to at most 450.0° C. and at a pressure of at least 10,600 Pa to epitaxially grow a phosphorous doped silicon layer on the monocrystalline silicon surface, wherein the carrier gas consists of nitrogen and/or one or more noble gasses.2. The method according to claim 1 , wherein the reaction chamber is maintained at a temperature of at least 370° C.3. The method according to claim 2 , wherein the reaction chamber is maintained at a temperature of at least 400° C.4. The method according to claim 1 , wherein the reaction chamber is maintained at a temperature of at most 420° C.5. The method according to claim 1 , wherein the reaction chamber is maintained at a pressure of at least 13 claim 1 ,300 Pa.6. The method according to claim 5 , wherein the reaction chamber is maintained at a pressure of at least 20 claim 5 ,000 Pa.7. The method according to claim 1 , wherein the reaction chamber is maintained at a pressure of at most 100 claim 1 ,000 Pa.8. The method according to claim 1 , wherein the disilane is provided to the reactor chamber at a disilane flow rate claim 1 , wherein the phosphine is provided to the reactor chamber at a phosphine flow rate claim 1 , wherein the phosphine flow rate divided by the disilane flow rate equals a phosphine disilane flow rate ratio claim 1 , and wherein the phosphine disilane flow rate ratio is from at least 0.5 to at most 1.4.9. The method according to claim 8 , wherein the phosphine ...

NITRIDE SEMICONDUCTOR LAMINATE, SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR LAMINATE, METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR FREE-STANDING SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A nitride semiconductor laminate includes: a substrate comprising a group III nitride semiconductor and including a surface and a reverse surface, the surface being formed from a nitrogen-polar surface, the reverse surface being formed from a group III element-polar surface and being provided on the reverse side from the surface; a protective layer provided at least on the reverse surface side of the substrate and having higher heat resistance than the reverse surface of the substrate; and a semiconductor layer provided on the surface side of the substrate and comprising a group III nitride semiconductor. The concentration of O in the semiconductor layer is lower than 1×10at/cm. 1. A nitride semiconductor laminate comprising:a substrate comprising a group III nitride semiconductor and including a surface and a reverse surface, the surface being formed from a nitrogen-polar surface, the reverse surface being formed from a group III element-polar surface, the reverse surface being provided on the reverse side from the surface;a protective layer provided at least on the reverse surface side of the substrate and having higher heat resistance than the reverse surface of the substrate; anda semiconductor layer provided on the surface side of the substrate and comprising a group III nitride semiconductor, wherein{'sup': 17', '3, 'concentration of O in the semiconductor layer is lower than 1×10at/cm.'}2. The nitride semiconductor laminate of claim 1 , wherein{'sup': 16', '3, 'the concentration of O in the semiconductor layer is lower than 1×10at/cm.'}3. The nitride semiconductor laminate of claim 1 , wherein{'sup': 15', '3, 'the concentration of O in the semiconductor layer is lower than 5×10at/cm.'}4. The nitride semiconductor laminate of claim 1 , wherein{'sup': 17', '3, 'concentration of C in the semiconductor layer is lower than 1×10at/cm.'}5. The nitride semiconductor laminate of claim 4 , wherein{'sup': 16', '3, 'the concentration of C in the semiconductor layer is ...

METHOD OF MANUFACTURING DIAMOND, DIAMOND, DIAMOND COMPOSITE SUBSTRATE, DIAMOND JOINED SUBSTRATE, AND TOOL

A method of manufacturing a diamond by a vapor phase synthesis method includes: preparing a substrate including a diamond seed crystal; forming a light absorbing layer lower in optical transparency than the substrate by performing ion implantation into the substrate, the light absorbing layer being formed at a predetermined depth from a main surface of the substrate; growing a diamond layer on the main surface of the substrate by the vapor phase synthesis method; and separating the diamond layer from the substrate by applying light from a main surface of at least one of the diamond layer and the substrate to allow the light absorbing layer to absorb the light and cause the light absorbing layer to be broken up. 1. A method of manufacturing a diamond by a vapor phase synthesis method , comprising:preparing a substrate including a diamond seed crystal;forming a light absorbing layer lower in optical transparency than the substrate by performing ion implantation into the substrate, the light absorbing layer being formed at a predetermined depth from a main surface of the substrate;growing a diamond layer on the main surface of the substrate by the vapor phase synthesis method; andseparating the diamond layer from the substrate by applying light from a main surface of at least one of the diamond layer and the substrate to allow the light absorbing layer to absorb the light and cause the light absorbing layer to be broken up.2. The method of manufacturing a diamond according to claim 1 , whereinthe light absorbing layer has a thickness of not less than 20 nm and not more than 10 μm, and has a maximum peak value of a density of atomic vacancies in a range of not less than 0.01% and not more than 100%.3. The method of manufacturing a diamond according to claim 1 , whereinthe ion implantation is performed with ions of at least one kind of element selected from the group consisting of hydrogen, oxygen, nitrogen, helium, neon, and argon.4. The method of manufacturing a ...

DIAMOND COMPOSITE BODY, SUBSTRATE, DIAMOND, TOOL INCLUDING DIAMOND, AND METHOD FOR MANUFACTURING DIAMOND

Provided are a diamond composite body capable of shortening a separation time for separating a substrate and a diamond layer, the substrate, and a method for manufacturing a diamond, as well as a diamond obtained from the diamond composite body and a tool including the diamond. The diamond composite body includes a substrate including a diamond seed crystal and having grooves in a main surface, a diamond layer formed on the main surface of the substrate, and a non-diamond layer formed on a substrate side at a constant depth from an interface between the substrate and the diamond layer. 1. A diamond composite body , comprising:a substrate including a diamond seed crystal and having grooves in a main surface;a single crystal diamond layer formed on the main surface of the substrate, the single crystal diamond layer being integrally present to cover an upper surface of each groove; anda non-diamond layer formed on a substrate side at a constant depth from an interface between the substrate and the single crystal diamond layer.2. The diamond composite body according to claim 1 , wherein the main surface of the substrate has an off angle of more than or equal to 0° and less than or equal to 15° with respect to a (001) plane claim 1 , andthe grooves in the main surface of the substrate are substantially parallel to a <100> direction.3. The diamond composite body according to claim 1 , wherein the grooves in the main surface of the substrate have a width W of more than or equal to 0.1 μm and less than or equal to 30 μm.4. The diamond composite body according to claim 1 , wherein a value of a ratio D/W between a width W and a depth D of the grooves in the main surface of the substrate is more than or equal to 3 and less than or equal to 50.5. The diamond composite body according to claim 2 , wherein the main surface of the substrate further has grooves intersecting with the grooves which are substantially parallel to the <100> direction.6. (canceled)7. (canceled)8. A ...

METHOD FOR MANUFACTURING SILICON-CARBIDE SEMICONDUCTOR ELEMENT

In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate () to mechanical polishing is removed by heating the substrate () under Si vapor pressure. An epitaxial layer formation step, an ion implantation step, an ion activation step, and a second removal step are then performed. In the second removal step, macro-step bunching and insufficient ion-implanted portions of the surface of the substrate () performed the ion activation step are removed by heating the substrate () under Si vapor pressure. After that, an electrode formation step in which electrodes are formed on the substrate () is performed. 1. A method for treating a surface of a substrate having an off angle , a surface of the substrate being SiC , the method comprising:forming a modified layer in the substrate by applying pressure to the substrate;a first removal step of removing the modified layer by heating the substrate under Si vapor pressure and performing isotropic etching based upon etching rate to reciprocal of heating temperature.2. A method for treating a surface of a substrate having an off angle , a surface of the substrate being SiC , the method comprising:forming a modified layer in the substrate by applying pressure to the substrate;a first removal step of removing the modified layer by heating the substrate under Si vapor pressure at an etching rate of 35 nm/min or more.3. The method for treating the surface of the substrate according to claim 1 , whereinthe first removal step is performed at an etching rate of 35 nm/min or more.4. The method for treating the surface of the substrate according to claim 1 , whereinthe first removal step is performed at the etching rate of about 100 nm/min or more.5. The method for treating the surface of the substrate according to claim 2 , whereinthe first removal step is performed at the etching rate of about 100 nm/min or more.6. The method for treating the surface of the substrate according to claim 1 ...

METHOD OF SEPARATING A FILM FROM A MAIN BODY OF A CRYSTALLINE OBJECT

Methods are provided for separating a crystalline film from its main body. The method uses ion implantation to generate an ion damaged layer underneath the surface of the crystalline object. The ion damage changes the crystal structure of the ion damaged layer, so it will have different optical transmittance and absorption characteristics from the undamaged part of the crystalline object. A laser beam with a wavelength that is higher than the absorption edge of the non-ion damaged material, but within the absorption range of the ion damaged material is irradiated at or past the ion damaged layer, causing further damage to the ion damaged layer. The film can then be separated from the main body of the crystalline object. 1. A method of separating a film from a crystalline object , the crystalline object comprising at least one material , the method comprising:implanting ions into the crystalline object through a surface to form an ion damaged layer underneath the surface;irradiating the crystalline object with amplified light, the light having a wavelength above an absorption edge of the at least one material, the light having a pulse with a duration lower than about 10 picoseconds, the light further damaging at least a portion of the ion damaged layer; andseparating the film of the crystalline object from a main body of the crystalline object at the location further damaged by the amplified light.2. The method according to claim 1 , wherein the amplified light is focused on the ion damaged layer to cause further damage to the ion damaged layer or crystalline material proximate to the ion damaged layer.3. The method according to claim 1 , wherein the amplified light passes through but is not focused on the ion damaged layer and the fluence of the amplified light is between a fluence threshold of the ion damaged layer and a fluence threshold of at least one undamaged material of the crystalline object claim 1 , causing further damage to the ion damaged layer.4. The ...

CRYSTAL LAMINATE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InAlGaN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cmor more and 4.6 cmor less under a temperature condition of normal temperature. 1. A crystal laminate comprising:{'sub': x', 'y', '1-x-y, 'a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InAlGaN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and'}a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, the crystal layer containing at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb,{'sup': −1', '−1, 'the crystal laminate being configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cmor more and 4.6 cmor less under a temperature condition of normal temperature.'}2. The crystal laminate of claim 1 , wherein{'sup': 17', '−3, 'density of an intrinsic carrier within the crystal substrate is lower than 1×10cmat least under a temperature condition of normal temperature ...

ULTRA-HIGH DENSITY SINGLE-WALLED CARBON NANOTUBE HORIZONTAL ARRAY AND ITS CONTROLLABLE PREPARATION METHOD

The present invention discloses single-walled carbon nanotubes horizontal arrays with ultra-high density and the preparation method. The method comprises the following steps: loading a catalyst on a single crystal growth substrate; after annealing, introducing hydrogen into a chemical vapor deposition system to conduct a reduction reaction of the catalyst; and maintaining the introduction of the hydrogen to conduct the orientated growth of a single-walled carbon nanotube. The density of the ultra-high density single-walled carbon nanotube horizontal array obtained by this method exceeds 130 tubes/micrometer, and an electrical performance test is performed on the prepared ultra-high density single-walled carbon nanotube horizontal array shows a high on-current density of 380 μA/μm, and the transconductance of 102.5 μS/μm. 1. A method for preparing ultra-high density single-walled carbon nanotube horizontal array , comprising the following steps:loading a catalyst on a single crystal growth substrate; after annealing, introducing hydrogen into a chemical vapor deposition system to conduct a reduction reaction of the catalyst; and maintaining the introduction of the hydrogen to conduct an orientated growth of the single-walled carbon nanotubes, then after the growth, the ultra-high density single-walled carbon nanotube horizontal array is directly obtained on the single crystal growth substrate.2. The method of claim 1 , wherein a material constituting the single crystal growth substrate is ST-cut quartz claim 1 , R-cut quartz claim 1 , a-plane α alumina claim 1 , r-plane α alumina or magnesium oxide;the catalyst is selected from a metal nanoparticle, wherein a metal element in the metal nanoparticle is selected from at least one of Fe, Co, Ni, Cu, Au, Mo, W, Ru, Rh, and Pd; the particle size of the catalyst is 1 nm-3 nm.3. The method of claim 1 , further comprising claim 1 , conducting a pretreatment of the single crystal growth substrate before loading the catalyst; ...

BORON-DOPED COPPER CATALYSTS FOR EFFICIENT CONVERSION OF CO2 TO MULTI-CARBON HYDROCARBONS AND ASSOCIATED METHODS

The invention relates to a catalyst system for catalyzing conversion of carbon dioxide into multi-carbon compounds comprising a boron-doped copper catalytic material and associated methods. 123-. (canceled)24. A catalyst system for catalyzing conversion of carbon dioxide (CO) into multi-carbon compounds , the catalyst system characterized in that the catalyst system comprises a boron-doped copper catalytic material , wherein the boron-doped copper catalytic material has a boron concentration that decreases with depth into the material , and further wherein the boron-doped copper catalytic material has a boron concentration of about 4-7 mol % proximate at the external surface of the catalyst and has a boron concentration below about 4 mol % beyond a depth of about 7 nm from the external surface; the boron concentration determined by Inductively coupled plasma optical emission spectrometry.25. The catalyst system of claim 24 , characterized in that the boron-doped copper catalytic material has a porous dendritic morphology.26. The catalyst system of claim 24 , characterized in that the boron-doped copper catalytic material has a particle size ranging from 30 to 40 nm as determined by scanning electron microscopy.27. The catalyst system of claim 24 , characterized in that the copper comprises Cu (111).28. The catalyst system of claim 24 , characterized in that the catalyst system further comprises:a gas-diffusion layer; anda catalyst layer comprising the boron-doped copper catalytic material applied to the gas-diffusion layer.29. A method to produce the boron-doped copper catalytic material for a catalyst system according to claim 24 , characterized in that the copper comprises Cu (111); and in that the boron-doped copper catalytic material is prepared via incipient wetness impregnation of a single crystal Cu (111) material with a boric acid aqueous solution.30. The method of claim 29 , characterized in that the impregnation step is followed by a calcination step.31. A ...

METHOD FOR MANUFACTURING SILICON CARBIDE EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes epitaxially growing a carrier-transport layer of a first conductivity type on a substrate of silicon carbide; irradiating the carrier-transport layer with a first light having a wavelength equal to or less than an absorption-edge wavelength of silicon carbide at a temperature of less than 400 degrees Celsius so as to expand a stacking fault originating from a basal plane dislocation which are propagated from the substrate to the carrier-transport layer; heating the carrier-transport layer in which the stacking fault has expanded so as to shrink the stacking fault, at a shrinking temperature of 400 degrees Celsius or more and 1000 degrees Celsius or less; and forming a carrier-injection region of a second conductivity type on the carrier-transport layer, the carrier-injection region injects carriers into the carrier-transport layer. 1. A method for manufacturing a semiconductor device comprising:epitaxially growing a carrier-transport layer of a first conductivity type on a substrate of silicon carbide;irradiating the carrier-transport layer with a first light having a wavelength equal to or less than an absorption-edge wavelength of silicon carbide at a temperature of less than 400° C. so as to expand a stacking fault originating from a basal plane dislocation which are propagated from the substrate to the carrier-transport layer;heating the carrier-transport layer in which the stacking fault has expanded so as to shrink the stacking fault, at a shrinking temperature of 400° C. or more and 1000° C. or less; andforming a carrier-injection region of a second conductivity type on the carrier-transport layer, the carrier-injection region injects carriers into the carrier-transport layer.2. The method according to claim 1 , wherein the shrinking the stacking fault is executed while irradiating the carrier-transport layer with a second light having a wavelength equal to or less than the absorption edge wavelength. ...

Template for Epitaxial Growth, Method for Producing the Same, and Nitride Semiconductor Device

The present invention provides a method for producing a template for epitaxial growth, the method including: a surface treatment step of dispersing Ga atoms on a surface of a sapphire substrate; and an AlN growth step of epitaxially growing an AlN layer on the sapphire substrate, wherein in a Ga concentration distribution in a depth direction perpendicular to the surface of the sapphire substrate in an internal region of the AlN layer excluding a near-surface region up to a depth of 100 nm from the surface of the AlN layer, which is obtained by secondary ion mass spectrometry, a position in the depth direction where the Ga concentration takes the maximum value is present in a near-interface region located between the interface of the sapphire substrate and a position at 400 nm spaced apart from the interface to the AlN layer side, and the maximum value of the Ga concentration is 3×10atoms/cmor more and 2×10atoms/cmor less. 1. A method for producing a template having an AlN layer on a surface of a sapphire substrate and used as an underlayer for epitaxially growing a GaN-family compound semiconductor layer , the method comprising:a surface treatment step of dispersing Ga atoms on a surface of a sapphire substrate; andan AlN growth step of epitaxially growing an AlN layer on the sapphire substrate,wherein in a Ga concentration distribution in a depth direction perpendicular to the surface of the sapphire substrate in an internal region of the AlN layer excluding a near-surface region up to a depth of 100 nm from the surface of the AlN layer, which is obtained by secondary ion mass spectrometry,a position in the depth direction where the Ga concentration takes the maximum value is present in a near-interface region located between the interface of the sapphire substrate and a position at 400 nm spaced apart from the interface to the AlN layer side, and{'sup': 17', '3', '20', '3, 'the maximum value of the Ga concentration is 3×10atoms/cmor more and 2×10atoms/cmor less ...

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

There is provided a technique of suppressing unintended substrate processing from being performed after predetermined substrate processing is ended, including a substrate support section that supports a substrate in a processing chamber; a processing gas supply section that supplies a processing gas into the processing chamber; and a moving mechanism that moves the substrate support section in the processing chamber, between a first position to which the processing gas supplied from the processing gas supply section is blown, and a second position to which the processing gas supplied from the processing gas supply section is not blown. 1. A substrate processing apparatus , comprising:a processing chamber in which a substrate is processed;a substrate support section that supports the substrate in the processing chamber;a processing gas supply section that supplies a processing gas into the processing chamber; anda moving mechanism that moves the substrate support section in the processing chamber, between a first position to which the processing gas supplied from the processing gas supply section is blown, and a second position to which the processing gas supplied from the processing gas supply section is not blown.2. The substrate processing apparatus according to claim 1 , wherein the moving mechanism moves the substrate support section supporting the substrate to the second position after substrate processing is ended and before supply of the processing gas from the processing gas supply section into the processing chamber is stopped.3. The substrate processing apparatus according to claim 1 , wherein the moving mechanism moves the substrate support section supporting the substrate to the second position after substrate processing is ended and before supply conditions of the processing gas supplied from the processing gas supply section are varied.4. The substrate processing apparatus according to claim 1 , wherein the processing gas supply section comprises a ...

Semiconductor Devices with Superjunction Structures

A semiconductor device includes: a semiconductor substrate having a bulk oxygen concentration of at least 6×1017 cm−3; an epitaxial layer on a first side of the semiconductor substrate, the epitaxial layer and the semiconductor substrate having a common interface; a superjunction semiconductor device structure in the epitaxial layer; and an interface region extending from the common interface into the semiconductor substrate to a depth of at least 10 μm. A mean oxygen concentration of the interface region is lower than the bulk oxygen concentration of the semiconductor substrate.

SYSTEM AND METHOD BASED ON LOW-PRESSURE CHEMICAL VAPOR DEPOSITION FOR FABRICATING PEROVSKITE FILM

A system and method for fabricating a perovskite film is provided, the system including a housing for use as a CVD furnace having first and second sections coupled with first and second temperature control units, respectively. The first and second sections correspond substantially to the upstream and downstream of gases, respectively. One or more substrates are loaded in the second section and controlled by the second temperature control unit, and an evaporation unit containing an organic halide material is loaded in the first section and controlled by the first temperature control unit. Each of the substrates is pre-deposited with a metal halide material. The inside of the housing is pumped down to a low pressure.

SUBSTRATE TREATING APPARATUS

Disclosed is a substrate treating apparatus comprising a wafer chuck on which a substrate is placed, an injector unit on a side of the wafer chuck and injecting process gases that include a first gas and a second gas, and a gas supply unit supplying the process gases to the injector unit. The gas supply unit comprises first and second gas supply sources that respectively accommodate the first and second gases, first and second gas supply lines that respectively connect the first and second gas supply sources to the injector unit, and first and second heating units that are respectively disposed on the first and second gas supply lines. The first heating units disposed on the first gas supply line have a density per unit length greater than the density per unit length of the second heating units disposed on the second gas supply line. 1. A substrate treating apparatus comprising:a wafer chuck configured to receive a substrate;an injector unit disposed on a side of the wafer chuck, the injector unit is configured to inject process gases that include a first gas and a second gas; anda gas supply unit that supplies the process gases to the injector unit,wherein the gas supply unit comprises:a first gas supply source configured to accommodate the first gas and a second gas supply source configured to accommodate the second gas;a first gas supply line connecting the first gas supply source to the injector unit and a second gas supply line connecting the second gas supply source to the injector unit; andfirst heating units disposed on the first gas supply line and second heating units disposed on the second gas supply line,wherein the first heating units disposed on the first gas supply line have a first density per unit length of the first gas supply line and the second heating units disposed on the second gas supply line have a second density per unit length of the second gas supply line, andwherein the first density per unit length of the first gas supply line is ...

METHOD AND STRUCTURE OF SINGLE CRYSTAL ELECTRONIC DEVICES WITH ENHANCED STRAIN INTERFACE REGIONS BY IMPURITY INTRODUCTION

A method of manufacture and resulting structure for a single crystal electronic device with an enhanced strain interface region. The method of manufacture can include forming a nucleation layer overlying a substrate and forming a first and second single crystal layer overlying the nucleation layer. This first and second layers can be doped by introducing one or more impurity species to form a strained single crystal layers. The first and second strained layers can be aligned along the same crystallographic direction to form a strained single crystal bi-layer having an enhanced strain interface region. Using this enhanced single crystal bi-layer to form active or passive devices results in improved physical characteristics, such as enhanced photon velocity or improved density charges. 1. A method for fabricating a single crystal electronic device , the method comprising:providing a substrate having a substrate surface region;forming a nucleation layer overlying the substrate surface region and being characterized by nucleation growth parameters; andforming a first single crystal piezoelectric layer overlying the nucleation layer;doping the first single crystal piezoelectric layer by introducing one or more impurity species including scandium (Sc) to form a first strained single crystal piezoelectric layer;wherein the first strained single crystal piezoelectric layer is characterized by a first strain condition and first piezoelectric layer parameters;forming a second single crystal piezoelectric layer overlying the first single crystal piezoelectric layer; anddoping the second single crystal piezoelectric layer by introducing one or more impurity species including scandium (Sc) to form a second strained single crystal piezoelectric layer;wherein the second strained single crystal piezoelectric layer is characterized by a second strain condition and second piezoelectric layer parameters;wherein the first strained single crystal piezoelectric layer and the second ...

SURFACE TREATMENT METHOD FOR SINGLE CRYSTAL SiC SUBSTRATE, AND SINGLE CRYSTAL SiC SUBSTRATE

The present application aims to provide a surface treatment method that is able to accurately control the rate of etching a single crystal SiC substrate and thereby enables correct understanding of the amount of etching. In the surface treatment method, the single crystal SiC substrate is etched by a heat treatment performed under Si vapor pressure. At a time of the etching, inert gas pressure in an atmosphere around the single crystal SiC substrate is adjusted to control the rate of etching. Accordingly, correct understanding of the amount of etching is obtained.

THERMAL DIFFUSION DOPING OF DIAMOND

Boron-doped diamond and methods for making it are provided. The doped diamond is made using an ultra-thin film of heavily boron-doped silicon as a dopant carrying material in a low temperature thermal diffusion doping process. 1. A method of making substitutionally boron-doped diamond , the method comprising:bonding a flexible, boron-doped, single-crystalline silicon nanomembrane to the surface of a layer of diamond; andannealing the diamond and the boron-doped, single-crystalline silicon nanomembrane for a time sufficient to allow boron dopant atoms from the boron-doped, single-crystalline silicon nanomembrane to diffuse into the layer of diamond to form a doped region in the diamond.2. The method of claim 1 , wherein annealing the diamond and the boron-doped claim 1 , single-crystalline silicon nanomembrane comprises annealing the diamond and the boron-doped claim 1 , single-crystalline silicon nanomembrane at a temperature of at least 700° C.3. The method of claim 1 , wherein the concentration of boron dopant atoms at the surface of the layer of diamond after annealing is at least 1×10cm.4. The method of claim 1 , wherein the concentration of boron dopant atoms at the surface of the layer of diamond after annealing is at least 1×10cm.5. The method of claim 1 , wherein the concentration of boron dopant atoms at the surface of the layer of diamond after annealing is at least 2×10cm.6. The method of claim 1 , wherein the annealing temperature is no greater than about 1000° C.7. The method of claim 1 , wherein the boron dopant atom concentration in the boron-doped claim 1 , single-crystalline silicon nanomembrane is at least 1×10cmat the surface of the boron-doped claim 1 , single-crystalline silicon nanomembrane that is bonded to the surface of the layer of diamond.8. The method of claim 1 , wherein the boron dopant atom concentration in the boron-doped claim 1 , single-crystalline silicon nanomembrane is at least 1×10cmat the surface of the boron-doped claim 1 , ...

Silicon single crystal wafer, manufacturing method thereof and method of detecting defects

A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.

COMPOSITION COMPRISING AN ENGINEERED DEFECT CONCENTRATION

A composition comprising an engineered defect concentration comprises a metal oxide single crystal having a polar surface and a bulk concentration of interstitial oxygen (O) of at least about 10atoms/cm. The polar surface comprises a concentration of impurity species of about 5% or less of a monolayer. A method of engineering a defect concentration in a single crystal comprises exposing a metal oxide single crystal having a polar surface to molecular oxygen at a temperature of about 850° C. or less, and injecting atomic oxygen into the single crystal at an effective diffusion rate Dof at least about 10cm/s. 1. A composition comprising an engineered defect concentration , the composition comprising:{'sub': 'i', 'sup': 14', '3, 'a metal oxide single crystal comprising a polar surface and having a bulk concentration of interstitial oxygen (O) of at least about 10atoms/cm,'}wherein the polar surface comprises a concentration of impurity species of about 5% or less of a monolayer.2. The composition of claim 1 , wherein the concentration of impurity species is about 1% or less of a monolayer.3. The composition of claim 1 , wherein the metal oxide single crystal comprises ZnO claim 1 , NiO claim 1 , LiCoO claim 1 , KTaO claim 1 , or SrTiO.4. The composition of claim 1 , wherein the polar surface is cation-terminated.5. The composition of claim 1 , wherein the polar surface is anion-terminated.6. The composition of claim 1 , wherein the metal oxide single crystal comprises at least one linear dimension of about 100 nm or less claim 1 , the metal oxide single crystal being nanostructured.7. The composition of comprising claim 1 , when exposed to molecular oxygen at an elevated temperature claim 1 , an oxygen diffusion profile having an exponential shape.8. The composition of claim 7 , wherein the oxygen diffusion profile comprises a near-surface pile-up region comprising an increased concentration of the interstitial oxygen (O) claim 7 , the near-surface pile-up region being ...

Printable diffusion barriers for silicon wafers

The present invention relates to a novel process for the preparation of printable, high-viscosity oxide media, and to the use thereof in the production of solar cells.

DIAMOND SINGLE CRYSTAL AND PRODUCTION METHOD THEREOF, AND SINGLE CRYSTAL DIAMOND TOOL

A method for producing a diamond single crystal includes implanting an ion other than carbon into a surface of a diamond single crystal seed substrate and thereby decreasing the transmittance of light having a wavelength of 800 nm, the surface having an off-angle of 7 degrees or less with respect to a {100} plane, and homoepitaxially growing a diamond single crystal on the ion-implanted surface of the seed substrate using a chemical vapor synthesis under synthesis conditions where the ratio N/Nof the number of carbon-containing molecules Nto the number of hydrogen molecules Nin a gas phase is 10% or more and 40% or less, the ratio N/Nof the number of nitrogen molecules Nto the number of carbon-containing molecules Nin the gas phase is 0.1% or more and 10% or less, and the seed substrate temperature T is 850° C. or more and less than 1000° C. 1. A diamond single crystal synthesized using a chemical vapor synthesis method and having an absorption coefficient of 25 cmor more and 80 cmor less for light having a wavelength of 350 nm.2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. (canceled)9. A single crystal diamond tool , comprising a cutting edge made of a diamond single crystal synthesized using a chemical vapor synthesis method and having an absorption coefficient of 25 cmor more and 80 cmor less for light having a wavelength of 350 nm.10. (canceled)11. (canceled)12. (canceled)13. (canceled) This is a continuation application of U.S. application Ser. No. 14/408,830, filed Dec. 17, 2014, which is a U.S. National stage application claiming priority under 35 U.S.C. §119(a) to Japanese Patent Application No. 2012-146444 filed in Japan on Jun. 29, 2012, Japanese Patent Application No. 2012-152485 filed in Japan on Jul. 6, 2012, and Japanese Patent Application No. 2012-152503, filed in Japan on Jul. 6, 2012. The entire contents of U.S. application Ser. No. 14/408,830, Japanese Patent Application No. 2012-146444, Japanese Patent Application ...

Silicon carbide substrate, semiconductor device, and methods for manufacturing them

A silicon carbide substrate has a first main surface, and a second main surface opposite to the first main surface. A region including at least one main surface of the first and second main surfaces is made of single-crystal silicon carbide. In the one main surface, sulfur atoms are present at not less than 60×10 10 atoms/cm 2 and not more than 2000×10 10 atoms/cm 2 , and carbon atoms as an impurity are present at not less than 3 at % and not more than 25 at %. Thereby, a silicon carbide substrate having a stable surface, a semiconductor device using the substrate, and methods for manufacturing them can be provided.

DIAMOND COMPONENTS FOR QUANTUM IMAGING, SENSING AND INFORMATION PROCESSING DEVICES

A single crystal CVD diamond component comprising: a surface, wherein at least a portion of said surface is formed of as-grown growth face single crystal CVD diamond material which has not been polished or etched and which has a surface roughness Rof no more than 100 nm; and a layer of NV defects, said layer of NV defects being disposed within 1 μm of the surface, said layer of NV defects having a thickness of no more than 500 nm, and said layer of NV defects having a concentration of NV defects of at least 10NV/cm. 1. A single crystal chemical vapour deposited (CVD) diamond component comprising:{'sub': 'a', 'a surface, wherein at least a portion of said surface is formed of as-grown growth face single crystal CVD diamond material which has not been polished or etched and which has a surface roughness Rof no more than 100 nm; and'}{'sup': −', '−', '−', '−', '−', '5', '2, 'a layer of NV defects, said layer of NV defects being disposed within 1 μm of the surface, said layer of NV defects having a thickness of no more than 500 nm, and said layer of NV defects having a concentration of NV defects of at least 10NV/cm.'}2. The single crystal CVD diamond component according to claim 1 ,{'sub': 'a', 'wherein the surface roughness Ris no more than 80 nm.'}3. The single crystal CVD diamond component according to claim 1 ,{'sub': 'a', 'sup': '2', 'wherein the portion of the surface which has said surface roughness Rhas an area of at least 100 nm.'}4. The single crystal CVD diamond component according to claim 1 ,wherein the surface comprises a projection with an outermost surface of the projection being formed of the as-grown growth face single crystal CVD diamond material.5. The single crystal CVD diamond component according to claim 1 ,{'sup': '−', 'wherein the layer of NV defects is disposed within 500 nm of the surface.'}6. The single crystal CVD diamond component according to claim 1 ,{'sup': '−', 'wherein the thickness of the layer of NV defects is no more than 200 nm.'} ...

PRODUCTION OF ROUNDED SALT PARTICLES

The present disclosure generally relates to methods of preparing spherical salt particles for industrial, medical, and other uses. The methods can include combining the angular salt particles with a quantity of finishing media, for example, into a receptacle. Thereafter, the angular salt particles and the finishing media can be moved or agitated until the angular salt particles have a desired sphericity. 1. A method for producing rounded salt particles from angular salt particles , the method comprising:providing a quantity of angular salt particles;providing a quantity of finishing media; andmoving the angular salt particles and the finishing media against each other to cause contact therebetween until the angular salt particles become rounded to a predetermined sphericity.2. The method of claim 1 , further comprising claim 1 , prior to the moving claim 1 , sieving angular salt particles to produce the quantity of angular salt particles having a predetermined particle size.3. The method claim 1 , wherein the angular salt particles have a particle size in the range of about 100 to about 1200 μm.4. The method of claim 1 , wherein the angular salt particles have a particle size in the range of about 400 to about 800 μm.5. The method of claim 1 , wherein the angular salt particles are selected from sodium chloride claim 1 , potassium chloride claim 1 , calcium carbonate claim 1 , or combinations thereof.6. The method of claim 5 , wherein the angular salt particles are sodium chloride salt particles.7. The method of claim 1 , wherein the finishing media is a material selected from the group consisting of a ceramic claim 1 , a mineral claim 1 , a metal claim 1 , an alloy claim 1 , a glass claim 1 , a plastic claim 1 , and a polymer.8. The method of claim 7 , wherein the finishing media comprises a ceramic.9. The method of claim 8 , wherein the ceramic is porcelain.10. The method of claim 1 , wherein the finishing media is in a particulate form having a particle size in ...

Methods of Planarizing SiC Surfaces

A method of planarizing a roughened surface of a SiC substrate includes: forming a sacrificial material on the roughened surface of the SiC substrate, the sacrificial material having a density between 35% and 120% of the density of the SiC substrate; implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form an amorphous region in the SiC substrate; and removing the sacrificial material and the amorphous region of the SiC substrate by wet etching. 1. A method of planarizing a roughened surface of a SiC substrate , the method comprising:forming a sacrificial material on the roughened surface of the SiC substrate, the sacrificial material having a density between 35% and 120% of the density of the SiC substrate;implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form an amorphous region in the SiC substrate; andremoving the sacrificial material and the amorphous region of the SiC substrate by wet etching.2. The method of claim 1 , wherein the surface of the SiC substrate has remaining roughness after the sacrificial material and the amorphous region of the SiC substrate are removed by wet etching claim 1 , the method further comprising:forming an additional sacrificial material on the surface of the SiC substrate with the remaining roughness, the additional sacrificial material having a density between 35% and 120% of the density of the SiC substrate;implanting ions through the additional sacrificial material and into the surface of the SiC substrate with the remaining roughness to form an additional amorphous region in the SiC substrate; andremoving the additional sacrificial material and the additional amorphous region of the SiC substrate by wet etching.3. The method of claim 1 , wherein implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form the amorphous region comprises:generating an ion beam directed towards ...

Sapphire composite base material and method for producing the same

A sapphire composite base material including: an inorganic glass substrate, a polyvinyl butyral or silica intermediate film on the inorganic glass substrate, and a single crystal sapphire film on the intermediate film. There is also provided a method for producing a sapphire composite base material, including steps of: forming an ion-implanted layer inside the single crystal sapphire substrate; forming a polyvinyl butyral or silica intermediate film on at least one surface selected from the surface of the single crystal sapphire substrate before or after the ion implantation, and a surface of an inorganic glass substrate; bonding the ion-implanted surface of the single crystal sapphire substrate to the surface of the inorganic glass substrate via the intermediate film to obtain a bonded body; and transferring a single crystal sapphire film to the inorganic glass substrate via the intermediate film.

SYNTHESIS AND PROCESSING OF PURE AND NV NANODIAMONDS AND OTHER NANOSTRUCTURES FOR QUANTUM COMPUTING AND MAGNETIC SENSING APPLICATIONS

Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting amorphous carbon doped with nitrogen and carbon-13 into an undercooled state followed by quenching. Materials disclosed herein may include dopants in concentrations exceeding thermodynamic solubility limits. 1. A quantum computer comprising:a quantum register with a size of at least two qubits, each of the at least two qubits comprising a different one of a plurality of NV-doped nanodiamonds deterministically placed on a substrate;each of the plurality of NV-doped nanodiamonds comprising one NV center and one carbon-13 atom;each of the plurality of NV-doped nanodiamonds being epitaxial with the substrate, the substrate being planar matching with diamond; and{'sup': −', '0, 'each of the plurality of NV-doped nanodiamonds having sharp transitions between NV and NV.'}2. The quantum computer of claim 1 , wherein the transitions are controllable electrically by current and/or optically by laser illumination.3. The structure of claim 1 , wherein the plurality of NV-doped diamonds have a same orientation.4. A structure comprising:a substrate; anda plurality of NV-doped diamonds deterministically placed on the substrate, each of the plurality NV-doped diamonds comprising an NV center and a carbon-13 atom.5. The structure of claim 4 , wherein the plurality of NV-doped diamonds have a same orientation.6. The structure of claim 4 ,wherein the plurality of NV-doped diamonds are epitaxial with the substrate; andwherein the substrate is planar matching with diamond.7. The structure of claim 4 , wherein the plurality of NV-doped diamonds has concentrations of NV-dopants that exceed thermodynamic solubility limits claim 4 , the NV-dopants comprising carbon-13.8. The structure of claim 4 , wherein each of the plurality of NV-doped diamonds comprises one NV center and one carbon-13 atom.9. The structure of claim 4 , wherein each of the NV-doped diamonds has ...

LARGE-SCALE SYNTHESIS OF 2D SEMICONDUCTORS BY EPITAXIAL PHASE CONVERSION

There is a method for forming an oxide or chalcogenide 2D semiconductor. The method includes a step of growing on a substrate, by a deposition method, a precursor epitaxy oxide or chalcogenide film; and a step of sulfurizing the precursor epitaxy oxide or chalcogenide film, by replacing the oxygen atoms with sulfur atoms, to obtain the oxide or chalcogenide 2D semiconductor. The oxide or chalcogenide 2D semiconductor has an epitaxy structure inherent from the precursor epitaxy oxide or chalcogenide film. 1. A method for forming an oxide or chalcogenide 2D semiconductor , the method comprising:growing on a substrate, by a deposition method, a precursor epitaxy oxide or chalcogenide film; andsulfurizing the precursor epitaxy oxide or chalcogenide film, by replacing the oxygen atoms with sulfur atoms, to obtain the oxide or chalcogenide 2D semiconductor,wherein the oxide or chalcogenide 2D semiconductor has an epitaxy structure inherent from the precursor epitaxy oxide or chalcogenide film.2. The method of claim 1 , wherein the precursor epitaxy oxide or chalcogenide film is a precursor single crystal MoOfilm claim 1 , the oxide or chalcogenide 2D semiconductor is a MoSsemiconductor claim 1 , and the deposition method is one of pulse laser deposition claim 1 , metalorganic vapor phase epitaxy or molecular beam epitaxy.3. The method of claim 2 , further comprising:providing the substrate inside a chamber of a pulse laser deposition (PLD) system;placing a target material on a target support underneath the substrate with a certain distance inside the PLD chamber; andirradiating with a laser beam the target material to ablate atoms of the target material,{'sub': '2', 'wherein the ablated atoms travel to the substrate and form the precursor single crystal MoOfilm.'}4. The method of claim 3 , wherein the target material is MoO.5. The method of claim 3 , wherein the substrate is located above the target support.6. The method of claim 3 , wherein the substrate and the target ...

METHOD OF MANUFACTURING AN OXIDE SINGLE CRYSTAL SUBSTRATE FOR A SURFACE ACOUSTIC WAVE DEVICE

[Object] 1. A method of manufacturing an oxide single crystal substrate for a surface acoustic wave device characterized by comprising steps of preparing a slurry by dispersing a powder containing a Li compound in a medium , applying said slurry to an oxide single crystal substrate , and heating said substrate with the slurry on it whereby said substrate is modified as Li is diffused into the substrate from the surface thereof.2. A method of manufacturing an oxide single crystal substrate for a surface acoustic wave device characterized by comprising steps of preparing a slurry by dispersing a powder containing a Li compound in a medium , applying said slurry to an oxide single crystal substrate , burying said oxide single crystal substrate with said slurry in a powder containing a Li compound same as the said Li compound , and heating said substrate whereby said substrate is modified as Li is diffused into the substrate from the surface thereof.3. A method of manufacturing an oxide single crystal substrate for a surface acoustic wave device characterized by comprising steps of preparing a slurry by dispersing a powder containing a Li compound in a medium , applying said slurry to a surface of an oxide single crystal substrate cut from an oxide single crystal ingot having a roughly congruent composition which has been subjected to single polarization treatment , burying said oxide single crystal substrate with said slurry in a powder containing a Li compound same as said Li compound , and heating said substrate to thereby modify it through diffusion of Li into said substrate from the surface thereof in a manner such that a profile of Li concentration occurs wherein the greater the depth is , the lower the Li concentration is.4. The method of manufacturing an oxide single crystal substrate for a surface acoustic wave device as claimed in claim 1 , wherein the powder containing the Li compound to be dispersed in the medium has an average particle size of 0.001 through ...

METHOD OF DECOMPOSING QUARTZ SAMPLE, METHOD OF ANALYZING METAL CONTAMINATION OF QUARTZ SAMPLE, AND METHOD OF MANUFACTURING QUARTZ MEMBER

Provided is a method of decomposing a quartz sample, which includes contacting a liquid in which at least a part of a quartz sample to be analyzed is immersed with a gas generated from a mixed acid to decompose at least a part of the quartz sample, wherein the liquid is a liquid containing at least water; and the mixed acid is a mixed acid of hydrogen fluoride and sulfuric acid, and a mole fraction of sulfuric acid in the mixed acid ranges from 0.07 to 0.40. 1. A method of decomposing a quartz sample ,which comprises:contacting a liquid in which at least a part of a quartz sample to be analyzed is immersed with a gas generated from a mixed acid to decompose at least a part of the quartz sample,whereinthe liquid is a liquid comprising at least water; andthe mixed acid is a mixed acid of hydrogen fluoride and sulfuric acid, and a mole fraction of sulfuric acid in the mixed acid ranges from 0.07 to 0.40.2. The method of decomposing a quartz sample according to claim 1 ,wherein a mole fraction of hydrogen fluoride in the mixed acid is equal to or more than 0.27.3. The method of decomposing a quartz sample according to claim 1 ,wherein the liquid is hydrofluoric acid.4. The method of decomposing a quartz sample according to claim 1 ,wherein the liquid is pure water.5. The method of decomposing a quartz sample according to claim 1 ,wherein the decomposition is performed in a sealed vessel.6. The method of decomposing a quartz sample according to claim 5 ,wherein the decomposition is performed without pressurization of an inside of the sealed vessel.7. The method of decomposing a quartz sample according to claim 5 ,wherein the decomposition is performed without heating of an inside of the sealed vessel.8. A method of analyzing metal contamination of a quartz sample claim 5 ,which comprises:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'decomposing a quartz sample by the method according to ; and'}analyzing a metal component in a decomposed substance obtained by the ...

Doping of particulate semiconductor materials

The invention relates to a method of doping semiconductor material. Essentially, the method comprises mixing a quantity of particulate semiconductor material with an ionic salt or a preparation of ionic salts. Preferably, the particulate semiconductor material comprises nanoparticles with a size in the range 1 nm to 100 μm. Most preferably, the particle size is in the range from 50 nm to 500 nm. Preferred semiconductor materials are intrinsic and metallurgical grade silicon. The invention extends to a printable composition comprising the doped semiconductor material as well as a binder and a solvent. The invention also extends to a semiconductor device formed from layers of the printable composition having p and n type properties.

Electromagnetically levitated substrate support

An apparatus for supporting a substrate and a method for positioning a substrate are provided. In one embodiment, an apparatus for supporting a substrate includes a substrate support, a stator circumscribing the substrate support, and an actuator. The actuator is coupled to the stator and adapted to change the elevation of the stator and/or adjust an angular orientation of the stator relative to its central axis. As the substrate support is magnetically coupled to the stator, a position, i.e., elevation and angular orientation, of the substrate support may be controlled.

Electromagnetically levitated substrate support

An apparatus for supporting a substrate and a method for positioning a substrate include a substrate support, a stator circumscribing the substrate support, and an actuator. The actuator is coupled to the stator and adapted to change the elevation of the stator and/or adjust an angular orientation of the stator relative to its central axis. As the substrate support is magnetically coupled to the stator, a position, i.e., elevation and angular orientation, of the substrate support may be controlled.

Diamond sensors, detectors and quantum devices

A synthetic single crystal diamond material comprises: a first region of synthetic single crystal diamond material comprising a plurality of electron donor defects; a second region of synthetic single crystal diamond material comprising a plurality of quantum spin defects; and a third region of synthetic single crystal diamond material disposed between the first and second regions such that the first and second regions are spaced apart by the third region, wherein the second and third regions of synthetic single crystal diamond material have a lower concentration of electron donor defects than the first region, and wherein the first and second regions are spaced apart by a distance in a range 10 nm to 100 µm. Devices comprising the diamond material and a method of making the diamond material are also disclosed.

Diamond components for quantum imaging, sensing and information processing devices

A single crystal CVD diamond component comprises: a surface, wherein at least a portion of said surface is formed of as grown growth face single crystal CVD diamond material which has not been polished or etched and which has a surface roughness Ra no more than 100 nm; and a layer of NV­-defects, said layer of NV­-defects being disposed within 1 µm of the surface, said layer of NV­-defects having a thickness of no more than 500 nm, and said layer of NV­- defects having a concentration of defects of at least 105 NV­-/cm2. A method for producing the single crystal CVD diamond component is also disclosed, and comprises: growing a single crystal CVD diamond layer having and as grown growth face, at least a portion of the as grown growth face having a surface roughness Ra of no more than 100 nm; implanting nitrogen into said as grown growth face of the single crystal CVD diamond layer without polishing and without etching the as grown growth face; and annealing the single crystal CVD diamond layer to cause migration of vacancy and/or nitrogen defects within the single crystal CVD diamond layer and formation of nitrogen vacancy defects from the implanted nitrogen and vacancy defects.

Diamond sensors, detectors, and quantum devices

A synthetic single crystal diamond material comprising: a first region of synthetic single crystal diamond material comprising a plurality of electron donor defects; a second region of synthetic single crystal diamond material comprising a plurality of quantum spin defects; and a third region of synthetic single crystal diamond material disposed between the first and second regions such that the first and second regions are spaced apart by the third region, wherein the second and third regions of synthetic single crystal diamond material have a lower concentration of electron donor defects than the first region of synthetic single crystal diamond material, and wherein the first and second regions are spaced apart by a distance in a range 10 nm to 100 μιη which is sufficiently close to allow electrons to be donated from the first region of synthetic single crystal diamond material to the second region of synthetic single crystal diamond material thus forming negatively charged quantum spin defects in the second region of synthetic single crystal diamond material and positively charged defects in the first region of synthetic single crystal diamond material while being sufficiently far apart to reduce other coupling interactions between the first and second regions which would otherwise unduly reduce the decoherence time of the plurality of quantum spin defects and/or produce strain broaden of a spectral line width of the plurality of quantum spin defects in the second region of synthetic single crystal diamond material.

Diamond sensors, detectors, and quantum devices

A synthetic single crystal diamond material comprising: a first region comprising electron donor defects; a second region comprising quantum spin defects; and a third region between the first and second regions. The second and third regions have a lower concentration of electron donor defects than the first region. The first and second regions are sufficiently close to allow electrons to be donated from the first region to the second region, thus forming negatively charged quantum spin defects in the second and positively charged defects in the first region, and sufficiently far apart to reduce other coupling interactions between the first and second regions which would otherwise unduly reduce the decoherence time of the plurality of quantum spin defects and/or produce strain broaden of a spectral line width of the plurality of quantum spin defects in the second region.

Diamond sensors, detectors, and quantum devices

A thin plate of synthetic single crystal diamond material, the thin plate of synthetic single crystal diamond material having: a thickness in a range 100 nm to 50 μιη; a concentration of quantum spin defects greater than 0.1 ppb (parts-per-billion); a concentration of point defects other than the quantum spin defects of below 200 ppm (parts-per-million); and wherein at least one major face of the thin plate of synthetic single crystal diamond material comprises surface termination species which have zero nuclear spin and/or zero electron spin.

Diamond sensors, detectors and quantum devices

A synthetic single crystal diamond material comprising: a first region of synthetic single crystal diamond material comprising a plurality of electron donor defects; a second region of synthetic single crystal diamond material comprising a plurality of quantum spin defects; and a third region of synthetic single crystal diamond material disposed between the first and second regions such that the first and second regions are spaced apart by the third region, wherein the second and third regions of synthetic single crystal diamond material have a lower concentration of electron donor defects than the first region of synthetic single crystal diamond material, and wherein the first and second regions are spaced apart by a distance in a range 10 nm to 100 mum which is sufficiently close to allow electrons to be donated from the first region of synthetic single crystal diamond material to the second region of synthetic single crystal diamond material thus forming negatively charged quantum spin defects in the second region of synthetic single crystal diamond material and positively charged defects in the first region of synthetic single crystal diamond material while being sufficiently far apart to reduce other coupling interactions between the first and second regions which would otherwise unduly reduce the decoherence time of the plurality of quantum spin defects and/or produce strain broaden of a spectral line width of the plurality of quantum spin defects in the second region of synthetic single crystal diamond material.

Diamond sensors detectors and quantum devices

A thin plate of synthetic single crystal diamond material having a thickness in a range 100 nm to 50 µm, a concentration of negatively charged nitrogen vacancy quantum (NV-) spin defects greater than 0.1 ppb (parts-per billion) and a concentration of point defects other than the quantum spin defects of below 200 ppm (parts-per-million) is used for spintronic quantum devices and sensors. At least one major face of the thin plate of synthetic single crystal diamond material is coated with a surface termination species (16O) having zero nuclear spin and/or zero electron spin. The diamond layer is provided by thinning the substrate by implantation and separation, etching, polishing or mechanical grinding.

Diamond sensors, detectors, and quantum devices

Single crystal diamond for sensors, detectors, and quantum devices

Diamond Material

Diamond sensors, detectors, and quantum devices

A synthetic single crystal diamond material comprising: a first region of synthetic single crystal diamond material comprising a plurality of electron donor defects; a second region of synthetic single crystal diamond material comprising a plurality of quantum spin defects; and a third region of synthetic single crystal diamond material disposed between the first and second regions such that the first and second regions are spaced apart by the third region, wherein the second and third regions of synthetic single crystal diamond material have a lower concentration of electron donor defects than the first region of synthetic single crystal diamond material, and wherein the first and second regions are spaced apart by a distance in a range 10 nm to 100 mum which is sufficiently close to allow electrons to be donated from the first region of synthetic single crystal diamond material to the second region of synthetic single crystal diamond material thus forming negatively charged quantum spin defects in the second region of synthetic single crystal diamond material and positively charged defects in the first region of synthetic single crystal diamond material while being sufficiently far apart to reduce other coupling interactions between the first and second regions which would otherwise unduly reduce the decoherence time of the plurality of quantum spin defects and/or produce strain broaden of a spectral line width of the plurality of quantum spin defects in the second region of synthetic single crystal diamond material.

Diamond sensors, detectors, and quantum devices

A thin plate of synthetic single crystal diamond material having a thickness in a range 100 nm to 50 µm, a concentration of negatively charged nitrogen vacancy quantum (NV-) spin defects greater than 0.1 ppb (parts-per billion) and a concentration of point defects other than the quantum spin defects of below 200 ppm (parts-per-million) is used for spintronic quantum devices and sensors. At least one major face of the thin plate of synthetic single crystal diamond material is coated with a surface termination species (16O) having zero nuclear spin and/or zero electron spin. The diamond layer is provided by thinning the substrate by implantation and separation, etching, polishing or mechanical grinding.

Diamond components for quantum imaging sensing and information processing devices

Diamond material

Single crystal diamond having a high chemical purity i.e. a low nitrogen content and a high isotopic purity i.e. a low 13 C content, methods for producing the same and a solid state system comprising such single crystal diamond are described.

METHOD OF GENERATING A DETERMINISTIC COLOR CENTER IN A DIAMOND

A method generates at least one deterministic F-center in a diamond layer. By implanting a dopant in the diamond layer and incorporating at least one foreign atom in the diamond layer by low-energy bombardment for the formation of the F-center in a second step, conversion rates of greater than 70% can be achieved. This is a significant increase in relation to undoped diamond, in which the conversion rates are only around 6%. Via doping with a donor, such as phosphorous, oxygen or sulphur, a good conversion into negatively charged F-centers can be achieved, which are used for Qubit applications. 111-. (canceled)12. A method for generating at least one deterministic NV center in a diamond layer , comprising:implanting at least one dopant in the diamond layer, wherein the dopant used is one of lithium, oxygen or sulphur; and{'sup': 10', '−2, 'incorporating at least one nitrogen atom in the diamond layer by ion bombardment with impurity atoms to form the NV center, wherein the ion bombardment with the impurity atoms has an ionic fluence of up to 10cm.'}13. The method according to claim 12 , wherein:{'sup': 4', '−2', '10', '−2, 'the ion bombardment with the impurity atoms takes place with an ionic fluence in a range from 10cmto 10cm, and/or'}the ion bombardment with the impurity atoms is low-energy with an energy of less than or equal to 100 keV.14. The method according to claim 13 , wherein the ion bombardment with the impurity atoms takes place with an ionic fluence in a range from 10cmto 10cm.15. The method according to claim 12 , wherein a dopant concentration is in a range 10cmto 10cm.16. The method according to claim 12 , wherein the dopant implantation is carried out by bombarding the dopants with energies of less than or equal to 150 keV.17. The method according to claim 12 , wherein the dopant implantation is carried out by bombarding the dopants with a dopant fluence in a range of 10cmto 10cm.18. The method according to claim 12 , wherein the dopant ...

Reflective surface for CVD reactor walls

A reflector plate is provided for scattering radiant heat energy in a semiconductor processing reactor chamber to achieve uniform temperature across a substrate to be processed. The surface is characterized by a plurality of adjoining depressions with substantially no planar sections among the depressions. The width to depth ratio for the depressions averages over 3:1. Crests separating the depressions define an angle of greater than about 60°, thus providing a relatively smooth texture for the reflecting surface. The reflecting surface is thus easy to clean. A method of manufacturing the reflector plate comprises removing material from a planar metal surface by ball-end milling. The depth of each depression and degree of overlap with adjacent depressions can randomly vary within selected ranges. A highly specular finish is then provided on the stippled surface by gold electroplating.